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This commit is contained in:
purplerain 2023-05-02 22:23:09 +00:00
parent 01bad5edf2
commit f609457dcf
Signed by: purplerain
GPG key ID: F42C07F07E2E35B7
85 changed files with 1589 additions and 1491 deletions
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2
sys/dev/acpi/abl.c
View file

@ -86,7 +86,7 @@ abl_match(struct device *parent, void *match, void *aux)
{
struct acpi_attach_args *aa = aux;
struct cfdata *cf = match;
return acpi_matchhids(aa, abl_hids, cf->cf_driver->cd_name);
}

2
sys/dev/acpi/acpi_x86.c
View file

@ -134,7 +134,7 @@ checklids(struct acpi_softc *sc)
if (lids == 0 && lid_action != 0)
return EAGAIN;
return 0;
}
}
int

2
sys/dev/acpi/acpiec.c
View file

@ -259,7 +259,7 @@ acpiec_match(struct device *parent, void *match, void *aux)
struct acpi_softc *acpisc = (struct acpi_softc *)parent;
/* Check for early ECDT table attach */
if (ecdt &&
if (ecdt &&
!memcmp(ecdt->hdr.signature, ECDT_SIG, sizeof(ECDT_SIG) - 1))
return (1);
if (acpisc->sc_ec)

8
sys/dev/acpi/acpithinkpad.c
View file

@ -435,7 +435,7 @@ thinkpad_hotkey(struct aml_node *node, int notify_type, void *arg)
case THINKPAD_BUTTON_SUSPEND:
#ifndef SMALL_KERNEL
if (acpi_record_event(sc->sc_acpi, APM_USER_SUSPEND_REQ))
acpi_addtask(sc->sc_acpi, acpi_sleep_task,
acpi_addtask(sc->sc_acpi, acpi_sleep_task,
sc->sc_acpi, SLEEP_SUSPEND);
#endif
break;
@ -456,7 +456,7 @@ thinkpad_hotkey(struct aml_node *node, int notify_type, void *arg)
case THINKPAD_BUTTON_HIBERNATE:
#if defined(HIBERNATE) && !defined(SMALL_KERNEL)
if (acpi_record_event(sc->sc_acpi, APM_USER_HIBERNATE_REQ))
acpi_addtask(sc->sc_acpi, acpi_sleep_task,
acpi_addtask(sc->sc_acpi, acpi_sleep_task,
sc->sc_acpi, SLEEP_HIBERNATE);
#endif
break;
@ -472,12 +472,12 @@ thinkpad_hotkey(struct aml_node *node, int notify_type, void *arg)
break;
case THINKPAD_PORT_REPL_DOCKED:
sc->sc_sens[THINKPAD_SENSOR_PORTREPL].value = 1;
sc->sc_sens[THINKPAD_SENSOR_PORTREPL].status =
sc->sc_sens[THINKPAD_SENSOR_PORTREPL].status =
SENSOR_S_OK;
break;
case THINKPAD_PORT_REPL_UNDOCKED:
sc->sc_sens[THINKPAD_SENSOR_PORTREPL].value = 0;
sc->sc_sens[THINKPAD_SENSOR_PORTREPL].status =
sc->sc_sens[THINKPAD_SENSOR_PORTREPL].status =
SENSOR_S_OK;
break;
default:

4
sys/dev/kstat.c
View file

@ -230,7 +230,7 @@ kstatioc_leave(struct kstat_req *ksreq, struct kstat *ks)
ksreq->ks_interval = ks->ks_interval;
if (ksreq->ks_data == NULL) {
/* userland doesn't want actual data, so shortcut */
/* userland doesn't want actual data, so shortcut */
kstat_enter(ks);
ksreq->ks_datalen = ks->ks_datalen;
ksreq->ks_updated = ks->ks_updated;
@ -633,7 +633,7 @@ kstat_remove(struct kstat *ks)
KASSERTMSG(ks->ks_state == KSTAT_S_INSTALLED,
"kstat %p %s:%u:%s:%u is not installed", ks,
ks->ks_provider, ks->ks_instance, ks->ks_name, ks->ks_unit);
ks->ks_state = KSTAT_S_CREATED;
rw_exit_write(&kstat_lock);
}

2
sys/dev/pci/aac_pci.c
View file

@ -285,7 +285,7 @@ aac_pci_attach(parent, self, aux)
printf("%s\n", intrstr);
sc->aac_dmat = pa->pa_dmat;
for (m = aac_identifiers; m->vendor != 0; m++)
if (m->vendor == PCI_VENDOR(pa->pa_id) &&
m->device == PCI_PRODUCT(pa->pa_id)) {

8
sys/dev/pci/agp.c
View file

@ -64,7 +64,7 @@ agpbus_probe(struct agp_attach_args *aa)
struct pci_attach_args *pa = aa->aa_pa;
if (strncmp(aa->aa_busname, "agp", 3) == 0 &&
PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE &&
PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE &&
PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_HOST)
return (1);
return (0);
@ -215,7 +215,7 @@ agp_generic_enable(struct agp_softc *sc, u_int32_t mode)
struct pci_attach_args pa;
pcireg_t tstatus, mstatus, command;
int rq, sba, fw, rate, capoff;
if (pci_find_device(&pa, agpvga_match) == 0 ||
pci_get_capability(pa.pa_pc, pa.pa_tag, PCI_CAP_AGP,
&capoff, NULL) == 0) {
@ -359,7 +359,7 @@ agp_acquire(void *dev)
{
struct agp_softc *sc = (struct agp_softc *)dev;
if (sc->sc_chipc == NULL)
if (sc->sc_chipc == NULL)
return (EINVAL);
if (sc->sc_state != AGP_ACQUIRE_FREE)
@ -377,7 +377,7 @@ agp_release(void *dev)
if (sc->sc_state == AGP_ACQUIRE_FREE)
return (0);
if (sc->sc_state != AGP_ACQUIRE_KERNEL)
if (sc->sc_state != AGP_ACQUIRE_KERNEL)
return (EBUSY);
sc->sc_state = AGP_ACQUIRE_FREE;

6
sys/dev/pci/agp_ali.c
View file

@ -96,7 +96,7 @@ agp_ali_probe(struct device *parent, void *match, void *aux)
return (0);
}
void
void
agp_ali_attach(struct device *parent, struct device *self, void *aux)
{
struct agp_ali_softc *asc = (struct agp_ali_softc *)self;
@ -135,7 +135,7 @@ agp_ali_attach(struct device *parent, struct device *self, void *aux)
reg = pci_conf_read(asc->asc_pc, asc->asc_tag, AGP_ALI_ATTBASE);
reg = (reg & 0xff) | gatt->ag_physical;
pci_conf_write(asc->asc_pc, asc->asc_tag, AGP_ALI_ATTBASE, reg);
/* Enable the TLB. */
reg = pci_conf_read(asc->asc_pc, asc->asc_tag, AGP_ALI_TLBCTRL);
reg = (reg & ~0xff) | 0x10;
@ -179,7 +179,7 @@ agp_ali_restore(struct agp_ali_softc *asc)
/* Install the gatt and aperture size. */
pci_conf_write(asc->asc_pc, asc->asc_tag, AGP_ALI_ATTBASE,
asc->asc_attbase);
/* Enable the TLB. */
pci_conf_write(asc->asc_pc, asc->asc_tag, AGP_ALI_TLBCTRL,
asc->asc_tlbctrl);

8
sys/dev/pci/agp_i810.c
View file

@ -59,7 +59,7 @@
/* I810/I815 only, memory is in dcache */
#define INTEL_LOCAL 0x2
/* Memory is snooped, must not be accessed through gtt from the cpu. */
#define INTEL_COHERENT 0x6
#define INTEL_COHERENT 0x6
enum {
CHIP_NONE = 0, /* not integrated graphics */
@ -194,7 +194,7 @@ agp_i810_get_chiptype(struct pci_attach_args *pa)
return (CHIP_IRONLAKE);
break;
}
return (CHIP_NONE);
}
@ -379,7 +379,7 @@ agp_i810_attach(struct device *parent, struct device *self, void *aux)
/* FALLTHROUGH */
case CHIP_I915:
/* FALLTHROUGH */
case CHIP_I965:
case CHIP_I965:
/* FALLTHROUGH */
case CHIP_G33:
/* FALLTHROUGH */
@ -559,7 +559,7 @@ agp_i810_configure(struct agp_i810_softc *isc)
tmp = isc->isc_apaddr;
if (isc->chiptype == CHIP_I810) {
tmp += isc->dcache_size;
} else {
} else {
tmp += isc->stolen << AGP_PAGE_SHIFT;
}

10
sys/dev/pci/agp_intel.c
View file

@ -59,7 +59,7 @@ struct agp_intel_softc {
CHIP_I845,
CHIP_I850,
CHIP_I865
} chiptype;
} chiptype;
/* registers saved during a suspend/resume cycle. */
pcireg_t savectrl;
pcireg_t savecmd;
@ -115,7 +115,7 @@ agp_intel_probe(struct device *parent, void *match, void *aux)
case PCI_PRODUCT_INTEL_82840_HB:
case PCI_PRODUCT_INTEL_82845_HB:
case PCI_PRODUCT_INTEL_82845G_HB:
case PCI_PRODUCT_INTEL_82850_HB:
case PCI_PRODUCT_INTEL_82850_HB:
case PCI_PRODUCT_INTEL_82855PM_HB:
case PCI_PRODUCT_INTEL_82855GM_HB:
case PCI_PRODUCT_INTEL_82860_HB:
@ -202,7 +202,7 @@ agp_intel_attach(struct device *parent, struct device *self, void *aux)
/* Install the gatt. */
pci_conf_write(pa->pa_pc, pa->pa_tag, AGP_INTEL_ATTBASE,
gatt->ag_physical);
/* Enable the GLTB and setup the control register. */
switch (isc->chiptype) {
case CHIP_I443:
@ -262,7 +262,7 @@ agp_intel_attach(struct device *parent, struct device *self, void *aux)
pci_conf_write(isc->isc_pc, isc->isc_tag,
AGP_INTEL_ERRCMD, reg);
}
isc->agpdev = (struct agp_softc *)agp_attach_bus(pa, &agp_intel_methods,
isc->isc_apaddr, isc->isc_apsize, &isc->dev);
return;
@ -329,7 +329,7 @@ agp_intel_restore(struct agp_intel_softc *isc)
/* Install the gatt. */
pci_conf_write(isc->isc_pc, isc->isc_tag, AGP_INTEL_ATTBASE,
isc->gatt->ag_physical);
/* Enable the GLTB and setup the control register. */
switch (isc->chiptype) {
case CHIP_I443:

6
sys/dev/pci/agp_sis.c
View file

@ -135,7 +135,7 @@ agp_sis_attach(struct device *parent, struct device *self, void *aux)
/* Install the gatt. */
pci_conf_write(ssc->ssc_pc, ssc->ssc_tag, AGP_SIS_ATTBASE,
gatt->ag_physical);
/* Enable the aperture and auto-tlb-inval */
reg = pci_conf_read(ssc->ssc_pc, ssc->ssc_tag, AGP_SIS_WINCTRL);
reg |= (0x05 << 24) | 3;
@ -176,7 +176,7 @@ agp_sis_restore(struct agp_sis_softc *ssc)
/* Install the gatt. */
pci_conf_write(ssc->ssc_pc, ssc->ssc_tag, AGP_SIS_ATTBASE,
ssc->gatt->ag_physical);
/*
* Enable the aperture, reset the aperture size and enable and
* auto-tlb-inval.
@ -217,7 +217,7 @@ agp_sis_set_aperture(void *sc, bus_size_t aperture)
gws = ffs(aperture / 4*1024*1024) - 1;
reg = pci_conf_read(ssc->ssc_pc, ssc->ssc_tag, AGP_SIS_WINCTRL);
reg = pci_conf_read(ssc->ssc_pc, ssc->ssc_tag, AGP_SIS_WINCTRL);
reg &= ~0x00000070;
reg |= gws << 4;
pci_conf_write(ssc->ssc_pc, ssc->ssc_tag, AGP_SIS_WINCTRL, reg);

2
sys/dev/pci/agp_via.c
View file

@ -238,7 +238,7 @@ agp_via_get_aperture(void *sc)
struct agp_via_softc *vsc = sc;
bus_size_t apsize;
apsize = pci_conf_read(vsc->vsc_pc, vsc->vsc_tag,
apsize = pci_conf_read(vsc->vsc_pc, vsc->vsc_tag,
vsc->regs[REG_APSIZE]) & 0x1f;
/*

2
sys/dev/pci/agpreg.h
View file

@ -210,7 +210,7 @@
#define AGP_I810_MISCC_RPTC 0x00c0
#define AGP_I810_MISCC_RPTC_NOLIMIT 0x0000
#define AGP_I810_MISCC_RPTC_62 0x0040
#define AGP_I810_MISCC_RPTC_50 0x0080
#define AGP_I810_MISCC_RPTC_50 0x0080
#define AGP_I810_MISCC_RPTC_37 0x00c0
/*

2
sys/dev/pci/agpvar.h
View file

@ -105,7 +105,7 @@ struct agp_softc {
pcireg_t sc_id;
int sc_opened;
int sc_capoff;
int sc_capoff;
int sc_nextid; /* next mem block id */
enum agp_acquire_state sc_state;

16
sys/dev/pci/ahc_pci.c
View file

@ -459,7 +459,7 @@ const struct ahc_pci_identity ahc_pci_ident_table [] =
ID_ALL_MASK,
ahc_aic7892_setup
},
/* aic7895 based controllers */
/* aic7895 based controllers */
{
ID_AHA_2940U_DUAL,
ID_ALL_MASK,
@ -480,7 +480,7 @@ const struct ahc_pci_identity ahc_pci_ident_table [] =
ID_AIC7895_ARO_MASK,
ahc_aic7895_setup
},
/* aic7896/97 based controllers */
/* aic7896/97 based controllers */
{
ID_AHA_3950U2B_0,
ID_ALL_MASK,
@ -506,7 +506,7 @@ const struct ahc_pci_identity ahc_pci_ident_table [] =
ID_ALL_MASK,
ahc_aic7896_setup
},
/* aic7899 based controllers */
/* aic7899 based controllers */
{
ID_AHA_3960D,
ID_ALL_MASK,
@ -665,7 +665,7 @@ ahc_find_pci_device(pcireg_t id, pcireg_t subid, u_int func)
* ID as valid.
*/
if (func > 0
&& ahc_9005_subdevinfo_valid(PCI_VENDOR(id), PCI_PRODUCT(id),
&& ahc_9005_subdevinfo_valid(PCI_VENDOR(id), PCI_PRODUCT(id),
PCI_VENDOR(subid), PCI_PRODUCT(subid))
&& SUBID_9005_MFUNCENB(PCI_PRODUCT(subid)) == 0)
return (NULL);
@ -834,7 +834,7 @@ ahc_pci_attach(struct device *parent, struct device *self, void *aux)
ahc_name(ahc));
devconfig |= DACEN;
}
/* Ensure that pci error generation, a test feature, is disabled. */
devconfig |= PCIERRGENDIS;
@ -963,7 +963,7 @@ ahc_pci_attach(struct device *parent, struct device *self, void *aux)
M_NOWAIT | M_ZERO);
if (ahc->seep_config == NULL)
goto error_out;
/* See if we have a SEEPROM and perform auto-term */
ahc_check_extport(ahc, &sxfrctl1);
@ -1208,7 +1208,7 @@ ahc_probe_ext_scbram(struct ahc_softc *ahc)
fast = FALSE;
large = FALSE;
num_scbs = 0;
if (ahc_ext_scbram_present(ahc) == 0)
goto done;
@ -1402,7 +1402,7 @@ ahc_pci_intr(struct ahc_softc *ahc)
if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) {
printf("%s: Latched PCIERR interrupt with "
"no status bits set\n", ahc_name(ahc));
"no status bits set\n", ahc_name(ahc));
} else {
ahc_outb(ahc, CLRINT, CLRPARERR);
}

26
sys/dev/pci/ahd_pci.c
View file

@ -170,7 +170,7 @@ const struct ahd_pci_identity ahd_pci_ident_table[] =
ID_ALL_MASK,
ahd_aic7901A_setup
},
/* aic7902 based controllers */
/* aic7902 based controllers */
{
ID_AHA_29320,
ID_ALL_MASK,
@ -240,7 +240,7 @@ const struct ahd_pci_identity ahd_pci_ident_table[] =
};
const u_int ahd_num_pci_devs = NUM_ELEMENTS(ahd_pci_ident_table);
#define DEVCONFIG 0x40
#define PCIXINITPAT 0x0000E000ul
#define PCIXINIT_PCI33_66 0x0000E000ul
@ -342,7 +342,7 @@ ahd_pci_attach(struct device *parent, struct device *self, void *aux)
pci_intr_handle_t ih;
const char *intrstr;
pcireg_t devconfig, memtype, subid;
uint16_t device, subvendor;
uint16_t device, subvendor;
int error, ioh_valid, ioh2_valid, l, memh_valid;
ahd->dev_softc = pa;
@ -373,10 +373,10 @@ ahd_pci_attach(struct device *parent, struct device *self, void *aux)
error = entry->setup(ahd, pa);
if (error != 0)
return;
/* XXX ahc on sparc64 needs this twice */
devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG);
if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) {
ahd->chip |= AHD_PCI;
/* Disable PCIX workarounds when running in PCI mode. */
@ -482,7 +482,7 @@ ahd_pci_attach(struct device *parent, struct device *self, void *aux)
devconfig |= DACEN;
pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG, devconfig);
}
ahd_softc_init(ahd);
/*
@ -514,7 +514,7 @@ ahd_pci_attach(struct device *parent, struct device *self, void *aux)
}
if (intrstr != NULL)
printf(": %s\n", intrstr);
/* Get the size of the cache */
ahd->pci_cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG);
ahd->pci_cachesize *= 4;
@ -668,7 +668,7 @@ ahd_check_extport(struct ahd_softc *ahd)
/*
* Fetch VPD for this function and parse it.
*/
if (bootverbose)
if (bootverbose)
printf("%s: Reading VPD from SEEPROM...",
ahd_name(ahd));
@ -681,12 +681,12 @@ ahd_check_extport(struct ahd_softc *ahd)
/*bytestream*/TRUE);
if (error == 0)
error = ahd_parse_vpddata(ahd, &vpd);
if (bootverbose)
if (bootverbose)
printf("%s: VPD parsing %s\n",
ahd_name(ahd),
error == 0 ? "successful" : "failed");
if (bootverbose)
if (bootverbose)
printf("%s: Reading SEEPROM...", ahd_name(ahd));
/* Address is always in units of 16bit words */
@ -941,7 +941,7 @@ ahd_pci_intr(struct ahd_softc *ahd)
u_int intstat;
u_int i;
u_int reg;
intstat = ahd_inb(ahd, INTSTAT);
if ((intstat & SPLTINT) != 0)
@ -965,7 +965,7 @@ ahd_pci_intr(struct ahd_softc *ahd)
for (i = 0; i < 8; i++) {
u_int bit;
if (i == 5)
continue;
@ -980,7 +980,7 @@ ahd_pci_intr(struct ahd_softc *ahd)
pci_status_strings[bit],
pci_status_source[i]);
}
}
}
}
pci_status1 = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG , pci_status1);

24
sys/dev/pci/drm/amd/amdgpu/ObjectID.h
View file

@ -1,5 +1,5 @@
/*
* Copyright 2006-2007 Advanced Micro Devices, Inc.
* Copyright 2006-2007 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -37,13 +37,13 @@
#define GRAPH_OBJECT_TYPE_CONNECTOR 0x3
#define GRAPH_OBJECT_TYPE_ROUTER 0x4
/* deleted */
#define GRAPH_OBJECT_TYPE_DISPLAY_PATH 0x6
#define GRAPH_OBJECT_TYPE_DISPLAY_PATH 0x6
#define GRAPH_OBJECT_TYPE_GENERIC 0x7
/****************************************************/
/* Encoder Object ID Definition */
/****************************************************/
#define ENCODER_OBJECT_ID_NONE 0x00
#define ENCODER_OBJECT_ID_NONE 0x00
/* Radeon Class Display Hardware */
#define ENCODER_OBJECT_ID_INTERNAL_LVDS 0x01
@ -96,7 +96,7 @@
/****************************************************/
/* Connector Object ID Definition */
/****************************************************/
#define CONNECTOR_OBJECT_ID_NONE 0x00
#define CONNECTOR_OBJECT_ID_NONE 0x00
#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I 0x01
#define CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I 0x02
#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D 0x03
@ -158,7 +158,7 @@
#define RESERVED1_ID_MASK 0x0800
#define OBJECT_TYPE_MASK 0x7000
#define RESERVED2_ID_MASK 0x8000
#define OBJECT_ID_SHIFT 0x00
#define ENUM_ID_SHIFT 0x08
#define OBJECT_TYPE_SHIFT 0x0C
@ -179,14 +179,14 @@
/* Encoder Object ID definition - Shared with BIOS */
/****************************************************/
/*
#define ENCODER_INTERNAL_LVDS_ENUM_ID1 0x2101
#define ENCODER_INTERNAL_LVDS_ENUM_ID1 0x2101
#define ENCODER_INTERNAL_TMDS1_ENUM_ID1 0x2102
#define ENCODER_INTERNAL_TMDS2_ENUM_ID1 0x2103
#define ENCODER_INTERNAL_DAC1_ENUM_ID1 0x2104
#define ENCODER_INTERNAL_DAC2_ENUM_ID1 0x2105
#define ENCODER_INTERNAL_SDVOA_ENUM_ID1 0x2106
#define ENCODER_INTERNAL_SDVOB_ENUM_ID1 0x2107
#define ENCODER_SIL170B_ENUM_ID1 0x2108
#define ENCODER_SIL170B_ENUM_ID1 0x2108
#define ENCODER_CH7303_ENUM_ID1 0x2109
#define ENCODER_CH7301_ENUM_ID1 0x210A
#define ENCODER_INTERNAL_DVO1_ENUM_ID1 0x210B
@ -200,8 +200,8 @@
#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1 0x2113
#define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1 0x2114
#define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1 0x2115
#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 0x2116
#define ENCODER_SI178_ENUM_ID1 0x2117
#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 0x2116
#define ENCODER_SI178_ENUM_ID1 0x2117
#define ENCODER_MVPU_FPGA_ENUM_ID1 0x2118
#define ENCODER_INTERNAL_DDI_ENUM_ID1 0x2119
#define ENCODER_VT1625_ENUM_ID1 0x211A
@ -316,7 +316,7 @@
#define ENCODER_SI178_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_SI178 << OBJECT_ID_SHIFT)
ENCODER_OBJECT_ID_SI178 << OBJECT_ID_SHIFT)
#define ENCODER_MVPU_FPGA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
@ -324,7 +324,7 @@
#define ENCODER_INTERNAL_DDI_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_INTERNAL_DDI << OBJECT_ID_SHIFT)
ENCODER_OBJECT_ID_INTERNAL_DDI << OBJECT_ID_SHIFT)
#define ENCODER_VT1625_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
@ -352,7 +352,7 @@
#define ENCODER_INTERNAL_KLDSCP_LVTMA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA << OBJECT_ID_SHIFT)
ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA << OBJECT_ID_SHIFT)
#define ENCODER_INTERNAL_UNIPHY1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\

2
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
View file

@ -6137,7 +6137,7 @@ int amdgpu_in_reset(struct amdgpu_device *adev)
{
return atomic_read(&adev->reset_domain->in_gpu_reset);
}
/**
* amdgpu_device_halt() - bring hardware to some kind of halt state
*

2
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
View file

@ -3418,7 +3418,7 @@ amdgpu_init_backlight(struct amdgpu_device *adev)
if (bd == NULL)
return;
drm_connector_list_iter_begin(dev, &conn_iter);
drm_for_each_connector_iter(connector, &conn_iter) {
if (connector->connector_type != DRM_MODE_CONNECTOR_LVDS &&

2
sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c
View file

@ -1100,7 +1100,7 @@ void amdgpu_bo_fini(struct amdgpu_device *adev)
arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
#else
drm_mtrr_del(0, adev->gmc.aper_base, adev->gmc.aper_size, DRM_MTRR_WC);
#endif
}
drm_dev_exit(idx);

2
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
View file

@ -101,7 +101,7 @@ amdgpu_vm_it_iter_next(struct amdgpu_bo_va_mapping *node, uint64_t start,
static void
amdgpu_vm_it_remove(struct amdgpu_bo_va_mapping *node,
struct rb_root_cached *root)
struct rb_root_cached *root)
{
rb_erase_cached(&node->rb, root);
}

4
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
View file

@ -1906,7 +1906,7 @@ static int gfx_v11_0_rlc_load_microcode(struct amdgpu_device *adev)
if (version_minor == 3)
gfx_v11_0_load_rlcp_rlcv_microcode(adev);
}
return 0;
}
@ -3348,7 +3348,7 @@ static int gfx_v11_0_cp_compute_load_microcode(struct amdgpu_device *adev)
}
memcpy(fw, fw_data, fw_size);
amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);

8
sys/dev/pci/drm/amd/amdgpu/imu_v11_0.c
View file

@ -58,7 +58,7 @@ static int imu_v11_0_init_microcode(struct amdgpu_device *adev)
imu_hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data;
adev->gfx.imu_fw_version = le32_to_cpu(imu_hdr->header.ucode_version);
//adev->gfx.imu_feature_version = le32_to_cpu(imu_hdr->ucode_feature_version);
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_IMU_I];
info->ucode_id = AMDGPU_UCODE_ID_IMU_I;
@ -240,9 +240,9 @@ static const struct imu_rlc_ram_golden imu_rlc_ram_golden_11[] =
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_BOT, 0x00000002, 0xe0000000),
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_TOP, 0x00000000, 0xe0000000),
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL2, 0x00020000, 0xe0000000),
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA0_UCODE_SELFLOAD_CONTROL, 0x00000210, 0),
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA1_UCODE_SELFLOAD_CONTROL, 0x00000210, 0),
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCPC_PSP_DEBUG, CPC_PSP_DEBUG__GPA_OVERRIDE_MASK, 0),
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA0_UCODE_SELFLOAD_CONTROL, 0x00000210, 0),
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA1_UCODE_SELFLOAD_CONTROL, 0x00000210, 0),
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCPC_PSP_DEBUG, CPC_PSP_DEBUG__GPA_OVERRIDE_MASK, 0),
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCPG_PSP_DEBUG, CPG_PSP_DEBUG__GPA_OVERRIDE_MASK, 0)
};

2
sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c
View file

@ -186,7 +186,7 @@ static int xgpu_ai_send_access_requests(struct amdgpu_device *adev,
/* Dummy REQ_GPU_INIT_DATA handling */
r = xgpu_ai_poll_msg(adev, IDH_REQ_GPU_INIT_DATA_READY);
/* version set to 0 since dummy */
adev->virt.req_init_data_ver = 0;
adev->virt.req_init_data_ver = 0;
}
return 0;

2
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
View file

@ -273,7 +273,7 @@ static int sdma_v5_0_init_microcode(struct amdgpu_device *adev)
if (ret)
return ret;
}
return ret;
}

2
sys/dev/pci/drm/amd/include/amd_shared.h
View file

@ -60,7 +60,7 @@ enum amd_apu_flags {
* acquires the list of IP blocks for the GPU in use on initialization.
* It can then operate on this list to perform standard driver operations
* such as: init, fini, suspend, resume, etc.
*
*
*
* IP block implementations are named using the following convention:
* <functionality>_v<version> (E.g.: gfx_v6_0).

534
sys/dev/pci/drm/amd/include/atomfirmware.h
View file

File diff suppressed because it is too large Load diff

4
sys/dev/pci/drm/amd/include/atomfirmwareid.h
View file

@ -1,12 +1,12 @@
/****************************************************************************\
*
*
* File Name atomfirmwareid.h
*
* Description ATOM BIOS command/data table ID definition header file
*
* Copyright 2016 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
* and associated documentation files (the "Software"), to deal in the Software without restriction,
* including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so,

22
sys/dev/pci/drm/amd/include/displayobject.h
View file

@ -1,14 +1,14 @@
/****************************************************************************\
*
*
* Module Name displayobjectsoc15.h
* Project
* Device
* Project
* Device
*
* Description Contains the common definitions for display objects for SoC15 products.
*
* Copyright 2014 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
* and associated documentation files (the "Software"), to deal in the Software without restriction,
* including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so,
@ -35,7 +35,7 @@
/****************************************************
* Display Object Type Definition
* Display Object Type Definition
*****************************************************/
enum display_object_type{
DISPLAY_OBJECT_TYPE_NONE =0x00,
@ -45,7 +45,7 @@ DISPLAY_OBJECT_TYPE_CONNECTOR =0x03
};
/****************************************************
* Encorder Object Type Definition
* Encorder Object Type Definition
*****************************************************/
enum encoder_object_type{
ENCODER_OBJECT_ID_NONE =0x00,
@ -56,11 +56,11 @@ ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 =0x03,
/****************************************************
* Connector Object ID Definition
* Connector Object ID Definition
*****************************************************/
enum connector_object_type{
CONNECTOR_OBJECT_ID_NONE =0x00,
CONNECTOR_OBJECT_ID_NONE =0x00,
CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D =0x01,
CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D =0x02,
CONNECTOR_OBJECT_ID_HDMI_TYPE_A =0x03,
@ -72,12 +72,12 @@ CONNECTOR_OBJECT_ID_OPM =0x07
/****************************************************
* Protection Object ID Definition
* Protection Object ID Definition
*****************************************************/
//No need
/****************************************************
* Object ENUM ID Definition
* Object ENUM ID Definition
*****************************************************/
enum object_enum_id{
@ -90,7 +90,7 @@ OBJECT_ENUM_ID6 =0x06
};
/****************************************************
*Object ID Bit definition
*Object ID Bit definition
*****************************************************/
enum object_id_bit{
OBJECT_ID_MASK =0x00FF,

2
sys/dev/pci/drm/amd/include/navi10_ip_offset.h
View file

@ -28,7 +28,7 @@
struct IP_BASE_INSTANCE {
unsigned int segment[MAX_SEGMENT];
};
struct IP_BASE {
struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
} __maybe_unused;

42
sys/dev/pci/drm/amd/include/pptable.h
View file

@ -133,7 +133,7 @@ typedef struct _ATOM_PPLIB_EXTENDEDHEADER
USHORT usUVDTableOffset; //points to ATOM_PPLIB_UVD_Table
USHORT usSAMUTableOffset; //points to ATOM_PPLIB_SAMU_Table
USHORT usPPMTableOffset; //points to ATOM_PPLIB_PPM_Table
USHORT usACPTableOffset; //points to ATOM_PPLIB_ACP_Table
USHORT usACPTableOffset; //points to ATOM_PPLIB_ACP_Table
/* points to ATOM_PPLIB_POWERTUNE_Table */
USHORT usPowerTuneTableOffset;
/* points to ATOM_PPLIB_CLOCK_Voltage_Dependency_Table for sclkVddgfxTable */
@ -223,14 +223,14 @@ typedef struct _ATOM_PPLIB_POWERPLAYTABLE3
typedef struct _ATOM_PPLIB_POWERPLAYTABLE4
{
ATOM_PPLIB_POWERPLAYTABLE3 basicTable3;
ULONG ulGoldenPPID; // PPGen use only
ULONG ulGoldenPPID; // PPGen use only
ULONG ulGoldenRevision; // PPGen use only
USHORT usVddcDependencyOnSCLKOffset;
USHORT usVddciDependencyOnMCLKOffset;
USHORT usVddcDependencyOnMCLKOffset;
USHORT usMaxClockVoltageOnDCOffset;
USHORT usVddcPhaseShedLimitsTableOffset; // Points to ATOM_PPLIB_PhaseSheddingLimits_Table
USHORT usMvddDependencyOnMCLKOffset;
USHORT usMvddDependencyOnMCLKOffset;
} ATOM_PPLIB_POWERPLAYTABLE4, *LPATOM_PPLIB_POWERPLAYTABLE4;
typedef struct _ATOM_PPLIB_POWERPLAYTABLE5
@ -376,21 +376,21 @@ typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO
UCHAR ucMaxHTLinkWidth; // From SBIOS - {2, 4, 8, 16}
UCHAR ucMinHTLinkWidth; // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled. Minimum down stream width could
USHORT usHTLinkFreq; // See definition ATOM_PPLIB_RS780_HTLINKFREQ_xxx or in MHz(>=200).
ULONG ulFlags;
ULONG ulFlags;
} ATOM_PPLIB_RS780_CLOCK_INFO;
#define ATOM_PPLIB_RS780_VOLTAGE_NONE 0
#define ATOM_PPLIB_RS780_VOLTAGE_LOW 1
#define ATOM_PPLIB_RS780_VOLTAGE_HIGH 2
#define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE 3
#define ATOM_PPLIB_RS780_VOLTAGE_NONE 0
#define ATOM_PPLIB_RS780_VOLTAGE_LOW 1
#define ATOM_PPLIB_RS780_VOLTAGE_HIGH 2
#define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE 3
#define ATOM_PPLIB_RS780_SPMCLK_NONE 0 // We cannot change the side port memory clock, leave it as it is.
#define ATOM_PPLIB_RS780_SPMCLK_LOW 1
#define ATOM_PPLIB_RS780_SPMCLK_HIGH 2
#define ATOM_PPLIB_RS780_HTLINKFREQ_NONE 0
#define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1
#define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2
#define ATOM_PPLIB_RS780_HTLINKFREQ_NONE 0
#define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1
#define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2
typedef struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO
{
@ -432,14 +432,14 @@ typedef struct _ATOM_PPLIB_CI_CLOCK_INFO
USHORT usMemoryClockLow;
UCHAR ucMemoryClockHigh;
UCHAR ucPCIEGen;
USHORT usPCIELane;
} ATOM_PPLIB_CI_CLOCK_INFO;
typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO{
USHORT usEngineClockLow; //clockfrequency & 0xFFFF. The unit is in 10khz
UCHAR ucEngineClockHigh; //clockfrequency >> 16.
UCHAR ucEngineClockHigh; //clockfrequency >> 16.
UCHAR vddcIndex; //2-bit vddc index;
USHORT tdpLimit;
//please initalize to 0
@ -464,10 +464,10 @@ typedef struct _ATOM_PPLIB_CZ_CLOCK_INFO {
typedef struct _ATOM_PPLIB_STATE_V2
{
//number of valid dpm levels in this state; Driver uses it to calculate the whole
//number of valid dpm levels in this state; Driver uses it to calculate the whole
//size of the state: sizeof(ATOM_PPLIB_STATE_V2) + (ucNumDPMLevels - 1) * sizeof(UCHAR)
UCHAR ucNumDPMLevels;
//a index to the array of nonClockInfos
UCHAR nonClockInfoIndex;
/**
@ -477,9 +477,9 @@ typedef struct _ATOM_PPLIB_STATE_V2
} ATOM_PPLIB_STATE_V2;
typedef struct _StateArray{
//how many states we have
//how many states we have
UCHAR ucNumEntries;
ATOM_PPLIB_STATE_V2 states[1];
}StateArray;
@ -487,10 +487,10 @@ typedef struct _StateArray{
typedef struct _ClockInfoArray{
//how many clock levels we have
UCHAR ucNumEntries;
//sizeof(ATOM_PPLIB_CLOCK_INFO)
UCHAR ucEntrySize;
UCHAR clockInfo[1];
}ClockInfoArray;
@ -500,7 +500,7 @@ typedef struct _NonClockInfoArray{
UCHAR ucNumEntries;
//sizeof(ATOM_PPLIB_NONCLOCK_INFO)
UCHAR ucEntrySize;
ATOM_PPLIB_NONCLOCK_INFO nonClockInfo[1];
}NonClockInfoArray;
@ -722,7 +722,7 @@ typedef struct _ATOM_PPLIB_PPM_Table
ULONG ulPlatformTDC;
ULONG ulSmallACPlatformTDC;
ULONG ulApuTDP;
ULONG ulDGpuTDP;
ULONG ulDGpuTDP;
ULONG ulDGpuUlvPower;
ULONG ulTjmax;
} ATOM_PPLIB_PPM_Table;

10
sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h
View file

@ -365,7 +365,7 @@ typedef struct {
uint16_t FanMaximumRpm;
uint16_t FanTargetTemperature;
uint16_t FanTargetGfxclk;
uint8_t FanZeroRpmEnable;
uint8_t FanZeroRpmEnable;
uint8_t FanTachEdgePerRev;
@ -659,8 +659,8 @@ typedef struct {
uint8_t Gfx_IdleHystLimit;
uint8_t Gfx_FPS;
uint8_t Gfx_MinActiveFreqType;
uint8_t Gfx_BoosterFreqType;
uint8_t Gfx_UseRlcBusy;
uint8_t Gfx_BoosterFreqType;
uint8_t Gfx_UseRlcBusy;
uint16_t Gfx_MinActiveFreq;
uint16_t Gfx_BoosterFreq;
uint16_t Gfx_PD_Data_time_constant;
@ -674,7 +674,7 @@ typedef struct {
uint8_t Soc_IdleHystLimit;
uint8_t Soc_FPS;
uint8_t Soc_MinActiveFreqType;
uint8_t Soc_BoosterFreqType;
uint8_t Soc_BoosterFreqType;
uint8_t Soc_UseRlcBusy;
uint16_t Soc_MinActiveFreq;
uint16_t Soc_BoosterFreq;
@ -690,7 +690,7 @@ typedef struct {
uint8_t Mem_FPS;
uint8_t Mem_MinActiveFreqType;
uint8_t Mem_BoosterFreqType;
uint8_t Mem_UseRlcBusy;
uint8_t Mem_UseRlcBusy;
uint16_t Mem_MinActiveFreq;
uint16_t Mem_BoosterFreq;
uint16_t Mem_PD_Data_time_constant;

4
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
View file

@ -1312,8 +1312,8 @@ struct pptable_funcs {
* @get_ecc_table: message SMU to get ECC INFO table.
*/
ssize_t (*get_ecc_info)(struct smu_context *smu, void *table);
/**
* @stb_collect_info: Collects Smart Trace Buffers data.
*/

12
sys/dev/pci/drm/drm_drv.c
View file

@ -90,7 +90,7 @@ DEFINE_STATIC_SRCU(drm_unplug_srcu);
* Some functions are only called once on init regardless of how many times
* drm attaches. In linux this is handled via module_init()/module_exit()
*/
int drm_refcnt;
int drm_refcnt;
struct drm_softc {
struct device sc_dev;
@ -1225,7 +1225,7 @@ drm_attach_pci(const struct drm_driver *driver, struct pci_attach_args *pa,
sc = (struct drm_softc *)config_found_sm(dev, &arg, drmprint, drmsubmatch);
if (sc == NULL)
return NULL;
return sc->sc_drm;
}
@ -1522,7 +1522,7 @@ const struct pci_device_id *
drm_find_description(int vendor, int device, const struct pci_device_id *idlist)
{
int i = 0;
for (i = 0; idlist[i].vendor != 0; i++) {
if ((idlist[i].vendor == vendor) &&
(idlist[i].device == device ||
@ -1546,7 +1546,7 @@ struct drm_file *
drm_find_file_by_minor(struct drm_device *dev, int minor)
{
struct drm_file key;
key.fminor = minor;
return (SPLAY_FIND(drm_file_tree, &dev->files, &key));
}
@ -1886,7 +1886,7 @@ drm_dmamem_alloc(bus_dma_tag_t dmat, bus_size_t size, bus_size_t alignment,
struct drm_dmamem *mem;
size_t strsize;
/*
* segs is the last member of the struct since we modify the size
* segs is the last member of the struct since we modify the size
* to allow extra segments if more than one are allowed.
*/
strsize = sizeof(*mem) + (sizeof(bus_dma_segment_t) * (nsegments - 1));
@ -1904,7 +1904,7 @@ drm_dmamem_alloc(bus_dma_tag_t dmat, bus_size_t size, bus_size_t alignment,
&mem->nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO) != 0)
goto destroy;
if (bus_dmamem_map(dmat, mem->segs, mem->nsegs, size,
if (bus_dmamem_map(dmat, mem->segs, mem->nsegs, size,
&mem->kva, BUS_DMA_NOWAIT | mapflags) != 0)
goto free;

8
sys/dev/pci/drm/drm_gem.c
View file

@ -102,7 +102,7 @@ drm_fault(struct uvm_faultinfo *ufi, vaddr_t vaddr, vm_page_t *pps,
* we do not allow device mappings to be mapped copy-on-write
* so we kill any attempt to do so here.
*/
if (UVM_ET_ISCOPYONWRITE(entry)) {
uvmfault_unlockall(ufi, ufi->entry->aref.ar_amap, uobj);
return(VM_PAGER_ERROR);
@ -144,7 +144,7 @@ drm_fault(struct uvm_faultinfo *ufi, vaddr_t vaddr, vm_page_t *pps,
return (ret);
}
boolean_t
boolean_t
drm_flush(struct uvm_object *uobj, voff_t start, voff_t stop, int flags)
{
return (TRUE);
@ -309,10 +309,10 @@ int drm_gem_object_init(struct drm_device *dev,
printf("%s size too big %lu\n", __func__, size);
return -ENOMEM;
}
obj->uao = uao_create(size, 0);
uvm_obj_init(&obj->uobj, &drm_pgops, 1);
return 0;
}

36
sys/dev/pci/drm/drm_linux.c
View file

@ -251,7 +251,7 @@ kthread_run(int (*func)(void *), void *data, const char *name)
thread->func = func;
thread->data = data;
thread->flags = 0;
if (kthread_create(kthread_func, thread, &thread->proc, name)) {
free(thread, M_DRM, sizeof(*thread));
return ERR_PTR(-ENOMEM);
@ -272,7 +272,7 @@ kthread_create_worker(unsigned int flags, const char *fmt, ...)
vsnprintf(name, sizeof(name), fmt, ap);
va_end(ap);
w->tq = taskq_create(name, 1, IPL_HIGH, 0);
return w;
}
@ -281,7 +281,7 @@ kthread_destroy_worker(struct kthread_worker *worker)
{
taskq_destroy(worker->tq);
free(worker, M_DRM, sizeof(*worker));
}
void
@ -551,7 +551,7 @@ __free_pages(struct vm_page *page, unsigned int order)
{
struct pglist mlist;
int i;
TAILQ_INIT(&mlist);
for (i = 0; i < (1 << order); i++)
TAILQ_INSERT_TAIL(&mlist, &page[i], pageq);
@ -623,7 +623,7 @@ void
kunmap_atomic(void *addr)
{
KASSERT(kmap_atomic_inuse);
pmap_kremove(kmap_atomic_va, PAGE_SIZE);
kmap_atomic_inuse = 0;
}
@ -1193,7 +1193,7 @@ retry:
int
i2c_transfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
{
int ret;
int ret;
if (adap->lock_ops)
adap->lock_ops->lock_bus(adap, 0);
@ -1497,7 +1497,7 @@ backlight_device_register(const char *name, void *kdev, void *data,
bd->data = data;
task_set(&bd->task, backlight_do_update_status, bd);
return bd;
}
@ -1720,7 +1720,7 @@ dma_fence_wait(struct dma_fence *fence, bool intr)
ret = dma_fence_wait_timeout(fence, intr, MAX_SCHEDULE_TIMEOUT);
if (ret < 0)
return ret;
return 0;
}
@ -1880,7 +1880,7 @@ dma_fence_default_wait(struct dma_fence *fence, bool intr, signed long timeout)
list_del(&cb.base.node);
out:
mtx_leave(fence->lock);
return ret;
}
@ -1926,7 +1926,7 @@ dma_fence_wait_any_timeout(struct dma_fence **fences, uint32_t count,
cb = mallocarray(count, sizeof(*cb), M_DRM, M_WAITOK|M_CANFAIL|M_ZERO);
if (cb == NULL)
return -ENOMEM;
for (i = 0; i < count; i++) {
struct dma_fence *fence = fences[i];
cb[i].proc = curproc;
@ -2022,7 +2022,7 @@ dma_fence_array_cb_func(struct dma_fence *f, struct dma_fence_cb *cb)
struct dma_fence_array_cb *array_cb =
container_of(cb, struct dma_fence_array_cb, cb);
struct dma_fence_array *dfa = array_cb->array;
if (atomic_dec_and_test(&dfa->num_pending))
timeout_add(&dfa->to, 1);
else
@ -2046,7 +2046,7 @@ dma_fence_array_enable_signaling(struct dma_fence *fence)
return false;
}
}
return true;
}
@ -2526,7 +2526,7 @@ pcie_get_speed_cap(struct pci_dev *pdev)
tag = pdev->tag;
if (!pci_get_capability(pc, tag, PCI_CAP_PCIEXPRESS,
&pos, NULL))
&pos, NULL))
return PCI_SPEED_UNKNOWN;
id = pci_conf_read(pc, tag, PCI_ID_REG);
@ -2582,7 +2582,7 @@ pcie_get_width_cap(struct pci_dev *pdev)
int bus, device, function;
if (!pci_get_capability(pc, tag, PCI_CAP_PCIEXPRESS,
&pos, NULL))
&pos, NULL))
return PCIE_LNK_WIDTH_UNKNOWN;
id = pci_conf_read(pc, tag, PCI_ID_REG);
@ -2607,13 +2607,13 @@ pcie_aspm_enabled(struct pci_dev *pdev)
pcireg_t lcsr;
if (!pci_get_capability(pc, tag, PCI_CAP_PCIEXPRESS,
&pos, NULL))
&pos, NULL))
return false;
lcsr = pci_conf_read(pc, tag, pos + PCI_PCIE_LCSR);
if ((lcsr & (PCI_PCIE_LCSR_ASPM_L0S | PCI_PCIE_LCSR_ASPM_L1)) != 0)
return true;
return false;
}
@ -2896,7 +2896,7 @@ interval_tree_iter_first(struct rb_root_cached *root, unsigned long start,
void
interval_tree_remove(struct interval_tree_node *node,
struct rb_root_cached *root)
struct rb_root_cached *root)
{
rb_erase_cached(&node->rb, root);
}
@ -3021,7 +3021,7 @@ fput(struct file *fp)
{
if (fp->f_type != DTYPE_SYNC)
return;
FRELE(fp, curproc);
}

2
sys/dev/pci/drm/drm_lock.c
View file

@ -223,7 +223,7 @@ int drm_legacy_lock(struct drm_device *dev, void *data,
ret ? "interrupted" : "has lock");
if (ret) return ret;
/* don't set the block all signals on the master process for now
/* don't set the block all signals on the master process for now
* really probably not the correct answer but lets us debug xkb
* xserver for now */
if (!drm_is_current_master(file_priv)) {

2
sys/dev/pci/drm/drm_managed.c
View file

@ -95,7 +95,7 @@ drmm_kfree(struct drm_device *dev, void *p)
}
}
mtx_leave(&dev->managed.lock);
if (m != NULL) {
free(m->p, M_DRM, m->size);
free(m, M_DRM, sizeof(*m));

2
sys/dev/pci/drm/drm_mm.c
View file

@ -174,7 +174,7 @@ drm_mm_interval_tree_iter_first(const struct rb_root_cached *root,
static void
drm_mm_interval_tree_remove(struct drm_mm_node *node,
struct rb_root_cached *root)
struct rb_root_cached *root)
{
rb_erase_cached(&node->rb, root);
}

2
sys/dev/pci/drm/i915/gt/agp_intel_gtt.c
View file

@ -177,7 +177,7 @@ intel_gmch_gtt_get(u64 *gtt_total,
{
struct inteldrm_softc *dev_priv = (void *)inteldrm_cd.cd_devs[0];
struct agp_info *ai = &dev_priv->drm.agp->info;
*gtt_total = ai->ai_aperture_size;
*mappable_base = ai->ai_aperture_base;
*mappable_end = ai->ai_aperture_size;

2
sys/dev/pci/drm/i915/gt/shmem_utils.c
View file

@ -228,7 +228,7 @@ static int __uao_rw(struct uvm_object *uao, loff_t off,
unsigned int this =
min_t(size_t, PAGE_SIZE - offset_in_page(off), len);
void *vaddr = kmap(page);
if (write) {
memcpy(vaddr + offset_in_page(off), ptr, this);
set_page_dirty(page);

6
sys/dev/pci/drm/include/linux/atomic.h
View file

@ -2,7 +2,7 @@
/**
* \file drm_atomic.h
* Atomic operations used in the DRM which may or may not be provided by the OS.
*
*
* \author Eric Anholt <anholt@FreeBSD.org>
*/
@ -298,7 +298,7 @@ __test_and_set_bit(u_int b, volatile void *p)
volatile u_int *ptr = (volatile u_int *)p;
unsigned int prev = ptr[b >> 5];
ptr[b >> 5] |= m;
return (prev & m) != 0;
}
@ -428,7 +428,7 @@ find_next_bit(const volatile void *p, int max, int b)
#define wmb() __membar("dsb sy")
#define mb() __membar("dsb sy")
#elif defined(__mips64__)
#define rmb() mips_sync()
#define rmb() mips_sync()
#define wmb() mips_sync()
#define mb() mips_sync()
#elif defined(__powerpc64__)

6
sys/dev/pci/drm/include/linux/capability.h
View file

@ -12,8 +12,8 @@
#define CAP_SYS_NICE 0x2
static inline bool
capable(int cap)
{
capable(int cap)
{
switch (cap) {
case CAP_SYS_ADMIN:
case CAP_SYS_NICE:
@ -21,7 +21,7 @@ capable(int cap)
default:
panic("unhandled capability");
}
}
}
static inline bool
perfmon_capable(void)

2
sys/dev/pci/drm/include/linux/dma-buf.h
View file

@ -61,7 +61,7 @@ struct dma_buf_export_info {
struct dma_resv *resv;
};
#define DEFINE_DMA_BUF_EXPORT_INFO(x) struct dma_buf_export_info x
#define DEFINE_DMA_BUF_EXPORT_INFO(x) struct dma_buf_export_info x
struct dma_buf *dma_buf_export(const struct dma_buf_export_info *);

2
sys/dev/pci/drm/include/linux/file.h
View file

@ -4,7 +4,7 @@
#define _LINUX_FILE_H
/* both for printf */
#include <sys/types.h>
#include <sys/types.h>
#include <sys/systm.h>
void fd_install(int, struct file *);

2
sys/dev/pci/drm/include/linux/interrupt.h
View file

@ -106,7 +106,7 @@ tasklet_hi_schedule(struct tasklet_struct *ts)
task_add(taskletq, &ts->task);
}
static inline void
static inline void
tasklet_disable_nosync(struct tasklet_struct *ts)
{
atomic_inc(&ts->count);

2
sys/dev/pci/drm/include/linux/io.h
View file

@ -119,7 +119,7 @@ static inline u32
ioread32(const volatile void __iomem *addr)
{
uint32_t val;
iobarrier();
val = lemtoh32(addr);
rmb();

12
sys/dev/pci/drm/include/linux/pci.h
View file

@ -135,7 +135,7 @@ pci_read_config_dword(struct pci_dev *pdev, int reg, u32 *val)
{
*val = pci_conf_read(pdev->pc, pdev->tag, reg);
return 0;
}
}
static inline int
pci_read_config_word(struct pci_dev *pdev, int reg, u16 *val)
@ -145,7 +145,7 @@ pci_read_config_word(struct pci_dev *pdev, int reg, u16 *val)
v = pci_conf_read(pdev->pc, pdev->tag, (reg & ~0x2));
*val = (v >> ((reg & 0x2) * 8));
return 0;
}
}
static inline int
pci_read_config_byte(struct pci_dev *pdev, int reg, u8 *val)
@ -155,14 +155,14 @@ pci_read_config_byte(struct pci_dev *pdev, int reg, u8 *val)
v = pci_conf_read(pdev->pc, pdev->tag, (reg & ~0x3));
*val = (v >> ((reg & 0x3) * 8));
return 0;
}
}
static inline int
pci_write_config_dword(struct pci_dev *pdev, int reg, u32 val)
{
pci_conf_write(pdev->pc, pdev->tag, reg, val);
return 0;
}
}
static inline int
pci_write_config_word(struct pci_dev *pdev, int reg, u16 val)
@ -174,7 +174,7 @@ pci_write_config_word(struct pci_dev *pdev, int reg, u16 val)
v |= (val << ((reg & 0x2) * 8));
pci_conf_write(pdev->pc, pdev->tag, (reg & ~0x2), v);
return 0;
}
}
static inline int
pci_write_config_byte(struct pci_dev *pdev, int reg, u8 val)
@ -319,7 +319,7 @@ static inline int
pcie_set_readrq(struct pci_dev *pdev, int rrq)
{
uint16_t val;
pcie_capability_read_word(pdev, PCI_PCIE_DCSR, &val);
val &= ~PCI_PCIE_DCSR_MPS;
val |= (ffs(rrq) - 8) << 12;

2
sys/dev/pci/drm/include/linux/rbtree.h
View file

@ -99,7 +99,7 @@ __rb_deepest_left(struct rb_node *node)
else
node = RB_RIGHT(node, __entry);
}
return parent;
return parent;
}
static inline struct rb_node *

2
sys/dev/pci/drm/include/linux/scatterlist.h
View file

@ -77,7 +77,7 @@ static inline bool
__sg_page_iter_next(struct sg_page_iter *iter)
{
iter->sg_pgoffset++;
while (iter->__nents > 0 &&
while (iter->__nents > 0 &&
iter->sg_pgoffset >= (iter->sg->length / PAGE_SIZE)) {
iter->sg_pgoffset -= (iter->sg->length / PAGE_SIZE);
iter->sg++;

2
sys/dev/pci/drm/include/linux/seqlock.h
View file

@ -91,7 +91,7 @@ typedef struct {
static inline void
seqlock_init(seqlock_t *sl, int wantipl)
{
{
sl->seq = 0;
mtx_init(&sl->lock, wantipl);
}

2
sys/dev/pci/drm/include/linux/string.h
View file

@ -74,7 +74,7 @@ match_string(const char * const *array, size_t n, const char *str)
for (i = 0; i < n; i++) {
if (array[i] == NULL)
break;
if (!strcmp(array[i], str))
if (!strcmp(array[i], str))
return i;
}

4
sys/dev/pci/drm/include/linux/swap.h
View file

@ -30,11 +30,11 @@
static inline long
get_nr_swap_pages(void)
{
{
return uvmexp.swpages - uvmexp.swpginuse;
}
/*
/*
* XXX For now, we don't want the shrinker to be too aggressive, so
* pretend we're not called from the pagedaemon even if we are.
*/

10
sys/dev/pci/drm/include/linux/types.h
View file

@ -30,12 +30,12 @@ typedef uint32_t u32;
typedef int64_t s64;
typedef uint64_t u64;
typedef uint16_t __le16;
typedef uint16_t __be16;
typedef uint32_t __le32;
typedef uint16_t __le16;
typedef uint16_t __be16;
typedef uint32_t __le32;
typedef uint32_t __be32;
typedef uint64_t __le64;
typedef uint64_t __be64;
typedef uint64_t __le64;
typedef uint64_t __be64;
typedef bus_addr_t dma_addr_t;
typedef paddr_t phys_addr_t;

4
sys/dev/pci/drm/include/linux/wait.h
View file

@ -221,7 +221,7 @@ wake_up(wait_queue_head_t *wqh)
wait_queue_entry_t *wqe;
wait_queue_entry_t *tmp;
mtx_enter(&wqh->lock);
list_for_each_entry_safe(wqe, tmp, &wqh->head, entry) {
KASSERT(wqe->func != NULL);
if (wqe->func != NULL)
@ -255,7 +255,7 @@ wake_up_all_locked(wait_queue_head_t *wqh)
.private = curproc, \
.func = autoremove_wake_function, \
.entry = LIST_HEAD_INIT((name).entry), \
}
}
static inline void
prepare_to_wait(wait_queue_head_t *wqh, wait_queue_entry_t *wqe, int state)

4
sys/dev/pci/drm/include/linux/ww_mutex.h
View file

@ -209,7 +209,7 @@ static inline int
ww_mutex_lock(struct ww_mutex *lock, struct ww_acquire_ctx *ctx) {
return __ww_mutex_lock(lock, ctx, false, false);
}
static inline void
ww_mutex_lock_slow(struct ww_mutex *lock, struct ww_acquire_ctx *ctx) {
(void)__ww_mutex_lock(lock, ctx, true, false);
@ -219,7 +219,7 @@ static inline int
ww_mutex_lock_interruptible(struct ww_mutex *lock, struct ww_acquire_ctx *ctx) {
return __ww_mutex_lock(lock, ctx, false, true);
}
static inline int __must_check
ww_mutex_lock_slow_interruptible(struct ww_mutex *lock, struct ww_acquire_ctx *ctx) {
return __ww_mutex_lock(lock, ctx, true, true);

2
sys/dev/pci/drm/include/uapi/drm/radeon_drm.h
View file

@ -233,7 +233,7 @@ typedef union {
# define R300_WAIT_3D 0x2
/* these two defines are DOING IT WRONG - however
* we have userspace which relies on using these.
* The wait interface is backwards compat new
* The wait interface is backwards compat new
* code should use the NEW_WAIT defines below
* THESE ARE NOT BIT FIELDS
*/

4
sys/dev/pci/drm/linux_sort.c
View file

@ -56,7 +56,7 @@ static __inline void swapfunc(char *, char *, size_t, int);
static __inline void
swapfunc(char *a, char *b, size_t n, int swaptype)
{
if (swaptype <= 1)
if (swaptype <= 1)
swapcode(long, a, b, n)
else
swapcode(char, a, b, n)
@ -167,7 +167,7 @@ loop: SWAPINIT(a, es);
void
sort(void *a, size_t n, size_t es, int (*cmp)(const void *, const void *),
void *x)
void *x)
{
KASSERT(x == NULL);
qsort(a, n, es, cmp);

24
sys/dev/pci/drm/radeon/ObjectID.h
View file

@ -1,5 +1,5 @@
/*
* Copyright 2006-2007 Advanced Micro Devices, Inc.
* Copyright 2006-2007 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -37,13 +37,13 @@
#define GRAPH_OBJECT_TYPE_CONNECTOR 0x3
#define GRAPH_OBJECT_TYPE_ROUTER 0x4
/* deleted */
#define GRAPH_OBJECT_TYPE_DISPLAY_PATH 0x6
#define GRAPH_OBJECT_TYPE_DISPLAY_PATH 0x6
#define GRAPH_OBJECT_TYPE_GENERIC 0x7
/****************************************************/
/* Encoder Object ID Definition */
/****************************************************/
#define ENCODER_OBJECT_ID_NONE 0x00
#define ENCODER_OBJECT_ID_NONE 0x00
/* Radeon Class Display Hardware */
#define ENCODER_OBJECT_ID_INTERNAL_LVDS 0x01
@ -96,7 +96,7 @@
/****************************************************/
/* Connector Object ID Definition */
/****************************************************/
#define CONNECTOR_OBJECT_ID_NONE 0x00
#define CONNECTOR_OBJECT_ID_NONE 0x00
#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I 0x01
#define CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I 0x02
#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D 0x03
@ -156,7 +156,7 @@
#define RESERVED1_ID_MASK 0x0800
#define OBJECT_TYPE_MASK 0x7000
#define RESERVED2_ID_MASK 0x8000
#define OBJECT_ID_SHIFT 0x00
#define ENUM_ID_SHIFT 0x08
#define OBJECT_TYPE_SHIFT 0x0C
@ -177,14 +177,14 @@
/* Encoder Object ID definition - Shared with BIOS */
/****************************************************/
/*
#define ENCODER_INTERNAL_LVDS_ENUM_ID1 0x2101
#define ENCODER_INTERNAL_LVDS_ENUM_ID1 0x2101
#define ENCODER_INTERNAL_TMDS1_ENUM_ID1 0x2102
#define ENCODER_INTERNAL_TMDS2_ENUM_ID1 0x2103
#define ENCODER_INTERNAL_DAC1_ENUM_ID1 0x2104
#define ENCODER_INTERNAL_DAC2_ENUM_ID1 0x2105
#define ENCODER_INTERNAL_SDVOA_ENUM_ID1 0x2106
#define ENCODER_INTERNAL_SDVOB_ENUM_ID1 0x2107
#define ENCODER_SIL170B_ENUM_ID1 0x2108
#define ENCODER_SIL170B_ENUM_ID1 0x2108
#define ENCODER_CH7303_ENUM_ID1 0x2109
#define ENCODER_CH7301_ENUM_ID1 0x210A
#define ENCODER_INTERNAL_DVO1_ENUM_ID1 0x210B
@ -198,8 +198,8 @@
#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1 0x2113
#define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1 0x2114
#define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1 0x2115
#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 0x2116
#define ENCODER_SI178_ENUM_ID1 0x2117
#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 0x2116
#define ENCODER_SI178_ENUM_ID1 0x2117
#define ENCODER_MVPU_FPGA_ENUM_ID1 0x2118
#define ENCODER_INTERNAL_DDI_ENUM_ID1 0x2119
#define ENCODER_VT1625_ENUM_ID1 0x211A
@ -314,7 +314,7 @@
#define ENCODER_SI178_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_SI178 << OBJECT_ID_SHIFT)
ENCODER_OBJECT_ID_SI178 << OBJECT_ID_SHIFT)
#define ENCODER_MVPU_FPGA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
@ -322,7 +322,7 @@
#define ENCODER_INTERNAL_DDI_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_INTERNAL_DDI << OBJECT_ID_SHIFT)
ENCODER_OBJECT_ID_INTERNAL_DDI << OBJECT_ID_SHIFT)
#define ENCODER_VT1625_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
@ -350,7 +350,7 @@
#define ENCODER_INTERNAL_KLDSCP_LVTMA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA << OBJECT_ID_SHIFT)
ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA << OBJECT_ID_SHIFT)
#define ENCODER_INTERNAL_UNIPHY1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\

1842
sys/dev/pci/drm/radeon/atombios.h
View file

File diff suppressed because it is too large Load diff

4
sys/dev/pci/if_aq_pci.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: if_aq_pci.c,v 1.21 2023/05/01 08:25:55 kettenis Exp $ */
/* $OpenBSD: if_aq_pci.c,v 1.22 2023/05/02 12:32:22 kettenis Exp $ */
/* $NetBSD: if_aq.c,v 1.27 2021/06/16 00:21:18 riastradh Exp $ */
/*
@ -1970,7 +1970,7 @@ aq2_fw_reboot(struct aq_softc *sc)
snprintf(buf, sizeof(buf), "(unknown 0x%08x)", v);
break;
}
printf(", Atlantic2 %s, F/W version %d.%d.%d\n", buf,
printf(", Atlantic2 %s, F/W version %d.%d.%d", buf,
FW_VERSION_MAJOR(sc), FW_VERSION_MINOR(sc), FW_VERSION_BUILD(sc));
aq2_interface_buffer_read(sc, AQ2_FW_INTERFACE_OUT_FILTER_CAPS_REG,

2
sys/dev/softraid_raid1c.c
View file

@ -329,7 +329,7 @@ sr_raid1c_rw(struct sr_workunit *wu)
if (sr_validate_io(wu, &blkno, "sr_raid1c_rw"))
return (1);
if (ISSET(wu->swu_xs->flags, SCSI_DATA_OUT) &&
!ISSET(wu->swu_flags, SR_WUF_REBUILD)) {
mdd_raid1c = &wu->swu_dis->mds.mdd_raid1c;

8
sys/dev/spdmem.c
View file

@ -673,7 +673,7 @@ spdmem_ddr3_decode(struct spdmem_softc *sc, struct spdmem *s)
SPDMEM_DDR3_DATAWIDTH_PRIMASK;
chipwidth = s->sm_data[SPDMEM_DDR3_MOD_ORG] &
SPDMEM_DDR3_MOD_ORG_CHIPWIDTH_MASK;
physbanks = (s->sm_data[SPDMEM_DDR3_MOD_ORG] >>
physbanks = (s->sm_data[SPDMEM_DDR3_MOD_ORG] >>
SPDMEM_DDR3_MOD_ORG_BANKS_SHIFT) & SPDMEM_DDR3_MOD_ORG_BANKS_MASK;
dimm_size = (chipsize + 28 - 20) - 3 + (datawidth + 3) -
@ -691,7 +691,7 @@ spdmem_ddr3_decode(struct spdmem_softc *sc, struct spdmem *s)
if (mtype == SPDMEM_DDR3_RDIMM || mtype == SPDMEM_DDR3_MINI_RDIMM)
printf(" registered");
if (s->sm_data[SPDMEM_DDR3_DATAWIDTH] & SPDMEM_DDR3_DATAWIDTH_ECCMASK)
if (s->sm_data[SPDMEM_DDR3_DATAWIDTH] & SPDMEM_DDR3_DATAWIDTH_ECCMASK)
printf(" ECC");
dividend = s->sm_data[SPDMEM_DDR3_MTB_DIVIDEND];
@ -759,7 +759,7 @@ spdmem_ddr4_decode(struct spdmem_softc *sc, struct spdmem *s)
SPDMEM_DDR4_DATAWIDTH_PRIMASK;
chipwidth = s->sm_data[SPDMEM_DDR4_MOD_ORG] &
SPDMEM_DDR4_MOD_ORG_CHIPWIDTH_MASK;
physbanks = (s->sm_data[SPDMEM_DDR4_MOD_ORG] >>
physbanks = (s->sm_data[SPDMEM_DDR4_MOD_ORG] >>
SPDMEM_DDR4_MOD_ORG_BANKS_SHIFT) & SPDMEM_DDR4_MOD_ORG_BANKS_MASK;
if ((s->sm_data[SPDMEM_DDR4_PACK_TYPE] &
@ -796,7 +796,7 @@ spdmem_ddr4_decode(struct spdmem_softc *sc, struct spdmem *s)
if (mtype == SPDMEM_DDR4_16B_SO_DIMM)
printf(" 16-bit");
if (s->sm_data[SPDMEM_DDR4_DATAWIDTH] & SPDMEM_DDR4_DATAWIDTH_ECCMASK)
if (s->sm_data[SPDMEM_DDR4_DATAWIDTH] & SPDMEM_DDR4_DATAWIDTH_ECCMASK)
printf(" ECC");
mtb = s->sm_data[SPDMEM_DDR4_TCKMIN_MTB];