sync with OpenBSD -current

This commit is contained in:
purplerain 2024-09-07 01:23:23 +00:00
parent d592c28c93
commit c6ae013d06
Signed by: purplerain
GPG key ID: F42C07F07E2E35B7
30 changed files with 524 additions and 103 deletions

View file

@ -1,4 +1,4 @@
/* $OpenBSD: dt_dev.c,v 1.36 2024/08/22 10:08:25 mvs Exp $ */
/* $OpenBSD: dt_dev.c,v 1.37 2024/09/06 08:38:21 mpi Exp $ */
/*
* Copyright (c) 2019 Martin Pieuchot <mpi@openbsd.org>
@ -26,6 +26,8 @@
#include <sys/proc.h>
#include <sys/ptrace.h>
#include <machine/intr.h>
#include <dev/dt/dtvar.h>
/*
@ -96,6 +98,7 @@ struct dt_softc {
SLIST_ENTRY(dt_softc) ds_next; /* [K] descriptor list */
int ds_unit; /* [I] D_CLONE unique unit */
pid_t ds_pid; /* [I] PID of tracing program */
void *ds_si; /* [I] to defer wakeup(9) */
struct mutex ds_mtx;
@ -142,6 +145,9 @@ int dt_ioctl_get_auxbase(struct dt_softc *, struct dtioc_getaux *);
int dt_pcb_ring_copy(struct dt_pcb *, struct uio *, size_t, size_t *,
uint64_t *);
void dt_wakeup(struct dt_softc *);
void dt_deferred_wakeup(void *);
void
dtattach(struct device *parent, struct device *self, void *aux)
{
@ -183,6 +189,11 @@ dtopen(dev_t dev, int flags, int mode, struct proc *p)
sc->ds_evtcnt = 0;
sc->ds_readevt = 0;
sc->ds_dropevt = 0;
sc->ds_si = softintr_establish(IPL_SOFTCLOCK, dt_deferred_wakeup, sc);
if (sc->ds_si == NULL) {
free(sc, M_DEVBUF, sizeof(*sc));
return ENOMEM;
}
SLIST_INSERT_HEAD(&dtdev_list, sc, ds_next);
@ -205,6 +216,7 @@ dtclose(dev_t dev, int flags, int mode, struct proc *p)
SLIST_REMOVE(&dtdev_list, sc, dt_softc, ds_next);
dt_ioctl_record_stop(sc);
dt_pcb_purge(&sc->ds_pcbs);
softintr_disestablish(sc->ds_si);
free(sc, M_DEVBUF, sizeof(*sc));
@ -719,7 +731,7 @@ dt_pcb_ring_consume(struct dt_pcb *dp, struct dt_evt *dtev)
mtx_enter(&dp->dp_sc->ds_mtx);
dp->dp_sc->ds_evtcnt++;
mtx_leave(&dp->dp_sc->ds_mtx);
wakeup(dp->dp_sc);
dt_wakeup(dp->dp_sc);
}
/*
@ -780,3 +792,24 @@ out:
*rcvd = copied;
return error;
}
void
dt_wakeup(struct dt_softc *sc)
{
/*
* It is not always safe or possible to call wakeup(9) and grab
* the SCHED_LOCK() from a given tracepoint. This is true for
* any tracepoint that might trigger inside the scheduler or at
* any IPL higher than IPL_SCHED. For this reason use a soft-
* interrupt to defer the wakeup.
*/
softintr_schedule(sc->ds_si);
}
void
dt_deferred_wakeup(void *arg)
{
struct dt_softc *sc = arg;
wakeup(sc);
}

View file

@ -1,4 +1,4 @@
/* $OpenBSD: inphyreg.h,v 1.5 2008/06/26 05:42:16 ray Exp $ */
/* $OpenBSD: inphyreg.h,v 1.6 2024/09/06 10:54:08 jsg Exp $ */
/* $NetBSD: inphyreg.h,v 1.1 1998/08/11 00:00:28 thorpej Exp $ */
/*-
@ -60,7 +60,7 @@
#define SCTRL_SCRBYPASS 0x8000 /* scrambler bypass */
#define SCTRL_4B5BNYPASS 0x4000 /* 4bit to 5bit bypass */
#define SCTRL_FTHP 0x2000 /* force transmit H-pattern */
#define SCTRL_F34TP 0x1000 /* force 34 transmit patter */
#define SCTRL_F34TP 0x1000 /* force 34 transmit pattern */
#define SCTRL_GOODLINK 0x0800 /* 100baseTX link good */
#define SCTRL_TCSD 0x0200 /* transmit carrier sense disable */
#define SCTRL_DDPD 0x0100 /* disable dynamic power-down */

View file

@ -1,4 +1,4 @@
/* $OpenBSD: dwiic_pci.c,v 1.30 2024/08/17 02:31:15 deraadt Exp $ */
/* $OpenBSD: dwiic_pci.c,v 1.31 2024/09/06 03:52:38 jsg Exp $ */
/*
* Synopsys DesignWare I2C controller
* PCI attachment
@ -179,6 +179,12 @@ const struct pci_matchid dwiic_pci_ids[] = {
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_I2C_3 },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_I2C_4 },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_MTL_I2C_5 },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_I2C_0 },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_I2C_1 },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_I2C_2 },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_I2C_3 },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_I2C_4 },
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_I2C_5 },
};
int

View file

@ -1,4 +1,4 @@
/* $OpenBSD: if_lge.c,v 1.81 2024/05/24 06:02:53 jsg Exp $ */
/* $OpenBSD: if_lge.c,v 1.82 2024/09/06 10:54:08 jsg Exp $ */
/*
* Copyright (c) 2001 Wind River Systems
* Copyright (c) 1997, 1998, 1999, 2000, 2001
@ -1063,7 +1063,7 @@ lge_init(void *xsc)
CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX|
LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT);
/* Workarond: FIFO overflow */
/* Workaround: FIFO overflow */
CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF);
CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT);

View file

@ -1,4 +1,4 @@
/* $OpenBSD: if_wb.c,v 1.77 2024/05/24 06:02:57 jsg Exp $ */
/* $OpenBSD: if_wb.c,v 1.78 2024/09/06 10:54:08 jsg Exp $ */
/*
* Copyright (c) 1997, 1998
@ -1304,7 +1304,7 @@ wb_start(struct ifnet *ifp)
* the own bit is clear because the chip cleared it
* and where the own bit is clear because we haven't
* set it yet. The magic value WB_UNSET is just some
* ramdomly chosen number which doesn't have the own
* randomly chosen number which doesn't have the own
* bit set. When we actually transmit the frame, the
* status word will have _only_ the own bit set, so
* the txeoc handler will be able to tell if it needs

View file

@ -1,4 +1,4 @@
/* $OpenBSD: igc_defines.h,v 1.1 2021/10/31 14:52:57 patrick Exp $ */
/* $OpenBSD: igc_defines.h,v 1.2 2024/09/06 10:54:08 jsg Exp $ */
/*-
* Copyright 2021 Intel Corp
@ -749,7 +749,7 @@
/* TTQF SCTP Bit, shift with IGC_TTQF_PROTOCOL_SHIFT */
#define IGC_TTQF_PROTOCOL_SCTP 0x2
#define IGC_TTQF_PROTOCOL_SHIFT 5 /* TTQF Protocol Shift */
#define IGC_TTQF_QUEUE_SHIFT 16 /* TTQF Queue Shfit */
#define IGC_TTQF_QUEUE_SHIFT 16 /* TTQF Queue Shift */
#define IGC_TTQF_RX_QUEUE_MASK 0x70000 /* TTQF Queue Mask */
#define IGC_TTQF_MASK_ENABLE 0x10000000 /* TTQF Mask Enable Bit */
#define IGC_IMIR_CLEAR_MASK 0xF001FFFF /* IMIR Reg Clear Mask */

View file

@ -1,4 +1,4 @@
$OpenBSD: pcidevs,v 1.2088 2024/09/04 23:56:43 dlg Exp $
$OpenBSD: pcidevs,v 1.2089 2024/09/06 03:48:20 jsg Exp $
/* $NetBSD: pcidevs,v 1.30 1997/06/24 06:20:24 thorpej Exp $ */
/*
@ -6157,6 +6157,14 @@ product INTEL APOLLOLAKE_AHCI 0x5ae3 Apollo Lake AHCI
product INTEL APOLLOLAKE_LPC 0x5ae8 Apollo Lake LPC
product INTEL APOLLOLAKE_UART_4 0x5aee Apollo Lake HSUART
product INTEL APOLLOLAKE_HB 0x5af0 Apollo Lake Host
product INTEL LNL_HB 0x6400 Core Ultra Host
product INTEL LNL_DTT 0x641d Core Ultra DTT
product INTEL LNL_GT_1 0x6420 Graphics
product INTEL LNL_NPU 0x643e Core Ultra NPU
product INTEL LNL_IPU 0x645d Core Ultra IPU
product INTEL LNL_CT 0x647d Core Ultra CT
product INTEL LNL_GT_2 0x64a0 Graphics
product INTEL LNL_GT_3 0x64b0 Graphics
product INTEL 5100_HB 0x65c0 5100 Host
product INTEL 5100_PCIE_2 0x65e2 5100 PCIE
product INTEL 5100_PCIE_3 0x65e3 5100 PCIE
@ -7263,6 +7271,58 @@ product INTEL RPL_P_GT_4 0xa7aa Graphics
product INTEL RPL_P_GT_5 0xa7ab Graphics
product INTEL RPL_U_GT_4 0xa7ac Graphics
product INTEL RPL_U_GT_5 0xa7ad Graphics
product INTEL LNL_ESPI 0xa807 Core Ultra eSPI
product INTEL LNL_P2SB_1 0xa820 Core Ultra P2SB
product INTEL LNL_PMC 0xa821 Core Ultra PMC
product INTEL LNL_SPI 0xa823 Core Ultra SPI
product INTEL LNL_TH 0xa824 Core Ultra TH
product INTEL LNL_UART_0 0xa825 Core Ultra UART
product INTEL LNL_UART_1 0xa826 Core Ultra UART
product INTEL LNL_GSPI_0 0xa827 Core Ultra GSPI
product INTEL LNL_HDA 0xa828 Core Ultra HD Audio
product INTEL LNL_GSPI_1 0xa830 Core Ultra GSPI
product INTEL LNL_TC_XHCI 0xa831 Core Ultra xHCI
product INTEL LNL_TBT_DMA0 0xa833 Core Ultra TBT
product INTEL LNL_TBT_DMA1 0xa834 Core Ultra TBT
product INTEL LNL_PCIE_1 0xa838 Core Ultra PCIE
product INTEL LNL_PCIE_2 0xa839 Core Ultra PCIE
product INTEL LNL_PCIE_3 0xa83a Core Ultra PCIE
product INTEL LNL_PCIE_4 0xa83b Core Ultra PCIE
product INTEL LNL_PCIE_5 0xa83c Core Ultra PCIE
product INTEL LNL_PCIE_6 0xa83d Core Ultra PCIE
product INTEL LNL_ISH 0xa845 Core Ultra ISH
product INTEL LNL_GSPI_2 0xa846 Core Ultra GSPI
product INTEL LNL_THC_0_1 0xa848 Core Ultra THC
product INTEL LNL_THC_0_2 0xa849 Core Ultra THC
product INTEL LNL_THC_1_1 0xa84a Core Ultra THC
product INTEL LNL_THC_1_2 0xa84b Core Ultra THC
product INTEL LNL_P2SB_2 0xa84c Core Ultra P2SB
product INTEL LNL_TC_PCIE_21 0xa84e Core Ultra PCIE
product INTEL LNL_TC_PCIE_22 0xa84f Core Ultra PCIE
product INTEL LNL_I2C_4 0xa850 Core Ultra I2C
product INTEL LNL_I2C_5 0xa851 Core Ultra I2C
product INTEL LNL_UART_2 0xa852 Core Ultra UART
product INTEL LNL_HECI_4 0xa85d Core Ultra HECI
product INTEL LNL_HECI_5 0xa85e Core Ultra HECI
product INTEL LNL_HECI_6 0xa85f Core Ultra HECI
product INTEL LNL_TC_PCIE_23 0xa860 Core Ultra PCIE
product INTEL LNL_HECI_1 0xa862 Core Ultra HECI
product INTEL LNL_HECI_2 0xa863 Core Ultra HECI
product INTEL LNL_HECI_3 0xa864 Core Ultra HECI
product INTEL LNL_CSE_HECI_1 0xa870 Core Ultra HECI
product INTEL LNL_CSE_HECI_2 0xa871 Core Ultra HECI
product INTEL LNL_IDER 0xa872 Core Ultra IDE-R
product INTEL LNL_KT 0xa873 Core Ultra KT
product INTEL LNL_CSE_HECI_3 0xa874 Core Ultra HECI
product INTEL LNL_CSE_HECI_4 0xa875 Core Ultra HECI
product INTEL LNL_I3C_2 0xa877 Core Ultra I3C
product INTEL LNL_I2C_0 0xa878 Core Ultra I2C
product INTEL LNL_I2C_1 0xa879 Core Ultra I2C
product INTEL LNL_I2C_2 0xa87a Core Ultra I2C
product INTEL LNL_I2C_3 0xa87b Core Ultra I2C
product INTEL LNL_I3C_1 0xa87c Core Ultra I3C
product INTEL LNL_XHCI 0xa87d Core Ultra xHCI
product INTEL LNL_SRAM 0xa87f Core Ultra SRAM
product INTEL 21152 0xb152 S21152BB
product INTEL 21154 0xb154 21154AE/BE
product INTEL CORE_DMI_0 0xd130 Core DMI

View file

@ -2,7 +2,7 @@
* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* generated from:
* OpenBSD: pcidevs,v 1.2088 2024/09/04 23:56:43 dlg Exp
* OpenBSD: pcidevs,v 1.2089 2024/09/06 03:48:20 jsg Exp
*/
/* $NetBSD: pcidevs,v 1.30 1997/06/24 06:20:24 thorpej Exp $ */
@ -6162,6 +6162,14 @@
#define PCI_PRODUCT_INTEL_APOLLOLAKE_LPC 0x5ae8 /* Apollo Lake LPC */
#define PCI_PRODUCT_INTEL_APOLLOLAKE_UART_4 0x5aee /* Apollo Lake HSUART */
#define PCI_PRODUCT_INTEL_APOLLOLAKE_HB 0x5af0 /* Apollo Lake Host */
#define PCI_PRODUCT_INTEL_LNL_HB 0x6400 /* Core Ultra Host */
#define PCI_PRODUCT_INTEL_LNL_DTT 0x641d /* Core Ultra DTT */
#define PCI_PRODUCT_INTEL_LNL_GT_1 0x6420 /* Graphics */
#define PCI_PRODUCT_INTEL_LNL_NPU 0x643e /* Core Ultra NPU */
#define PCI_PRODUCT_INTEL_LNL_IPU 0x645d /* Core Ultra IPU */
#define PCI_PRODUCT_INTEL_LNL_CT 0x647d /* Core Ultra CT */
#define PCI_PRODUCT_INTEL_LNL_GT_2 0x64a0 /* Graphics */
#define PCI_PRODUCT_INTEL_LNL_GT_3 0x64b0 /* Graphics */
#define PCI_PRODUCT_INTEL_5100_HB 0x65c0 /* 5100 Host */
#define PCI_PRODUCT_INTEL_5100_PCIE_2 0x65e2 /* 5100 PCIE */
#define PCI_PRODUCT_INTEL_5100_PCIE_3 0x65e3 /* 5100 PCIE */
@ -7268,6 +7276,58 @@
#define PCI_PRODUCT_INTEL_RPL_P_GT_5 0xa7ab /* Graphics */
#define PCI_PRODUCT_INTEL_RPL_U_GT_4 0xa7ac /* Graphics */
#define PCI_PRODUCT_INTEL_RPL_U_GT_5 0xa7ad /* Graphics */
#define PCI_PRODUCT_INTEL_LNL_ESPI 0xa807 /* Core Ultra eSPI */
#define PCI_PRODUCT_INTEL_LNL_P2SB_1 0xa820 /* Core Ultra P2SB */
#define PCI_PRODUCT_INTEL_LNL_PMC 0xa821 /* Core Ultra PMC */
#define PCI_PRODUCT_INTEL_LNL_SPI 0xa823 /* Core Ultra SPI */
#define PCI_PRODUCT_INTEL_LNL_TH 0xa824 /* Core Ultra TH */
#define PCI_PRODUCT_INTEL_LNL_UART_0 0xa825 /* Core Ultra UART */
#define PCI_PRODUCT_INTEL_LNL_UART_1 0xa826 /* Core Ultra UART */
#define PCI_PRODUCT_INTEL_LNL_GSPI_0 0xa827 /* Core Ultra GSPI */
#define PCI_PRODUCT_INTEL_LNL_HDA 0xa828 /* Core Ultra HD Audio */
#define PCI_PRODUCT_INTEL_LNL_GSPI_1 0xa830 /* Core Ultra GSPI */
#define PCI_PRODUCT_INTEL_LNL_TC_XHCI 0xa831 /* Core Ultra xHCI */
#define PCI_PRODUCT_INTEL_LNL_TBT_DMA0 0xa833 /* Core Ultra TBT */
#define PCI_PRODUCT_INTEL_LNL_TBT_DMA1 0xa834 /* Core Ultra TBT */
#define PCI_PRODUCT_INTEL_LNL_PCIE_1 0xa838 /* Core Ultra PCIE */
#define PCI_PRODUCT_INTEL_LNL_PCIE_2 0xa839 /* Core Ultra PCIE */
#define PCI_PRODUCT_INTEL_LNL_PCIE_3 0xa83a /* Core Ultra PCIE */
#define PCI_PRODUCT_INTEL_LNL_PCIE_4 0xa83b /* Core Ultra PCIE */
#define PCI_PRODUCT_INTEL_LNL_PCIE_5 0xa83c /* Core Ultra PCIE */
#define PCI_PRODUCT_INTEL_LNL_PCIE_6 0xa83d /* Core Ultra PCIE */
#define PCI_PRODUCT_INTEL_LNL_ISH 0xa845 /* Core Ultra ISH */
#define PCI_PRODUCT_INTEL_LNL_GSPI_2 0xa846 /* Core Ultra GSPI */
#define PCI_PRODUCT_INTEL_LNL_THC_0_1 0xa848 /* Core Ultra THC */
#define PCI_PRODUCT_INTEL_LNL_THC_0_2 0xa849 /* Core Ultra THC */
#define PCI_PRODUCT_INTEL_LNL_THC_1_1 0xa84a /* Core Ultra THC */
#define PCI_PRODUCT_INTEL_LNL_THC_1_2 0xa84b /* Core Ultra THC */
#define PCI_PRODUCT_INTEL_LNL_P2SB_2 0xa84c /* Core Ultra P2SB */
#define PCI_PRODUCT_INTEL_LNL_TC_PCIE_21 0xa84e /* Core Ultra PCIE */
#define PCI_PRODUCT_INTEL_LNL_TC_PCIE_22 0xa84f /* Core Ultra PCIE */
#define PCI_PRODUCT_INTEL_LNL_I2C_4 0xa850 /* Core Ultra I2C */
#define PCI_PRODUCT_INTEL_LNL_I2C_5 0xa851 /* Core Ultra I2C */
#define PCI_PRODUCT_INTEL_LNL_UART_2 0xa852 /* Core Ultra UART */
#define PCI_PRODUCT_INTEL_LNL_HECI_4 0xa85d /* Core Ultra HECI */
#define PCI_PRODUCT_INTEL_LNL_HECI_5 0xa85e /* Core Ultra HECI */
#define PCI_PRODUCT_INTEL_LNL_HECI_6 0xa85f /* Core Ultra HECI */
#define PCI_PRODUCT_INTEL_LNL_TC_PCIE_23 0xa860 /* Core Ultra PCIE */
#define PCI_PRODUCT_INTEL_LNL_HECI_1 0xa862 /* Core Ultra HECI */
#define PCI_PRODUCT_INTEL_LNL_HECI_2 0xa863 /* Core Ultra HECI */
#define PCI_PRODUCT_INTEL_LNL_HECI_3 0xa864 /* Core Ultra HECI */
#define PCI_PRODUCT_INTEL_LNL_CSE_HECI_1 0xa870 /* Core Ultra HECI */
#define PCI_PRODUCT_INTEL_LNL_CSE_HECI_2 0xa871 /* Core Ultra HECI */
#define PCI_PRODUCT_INTEL_LNL_IDER 0xa872 /* Core Ultra IDE-R */
#define PCI_PRODUCT_INTEL_LNL_KT 0xa873 /* Core Ultra KT */
#define PCI_PRODUCT_INTEL_LNL_CSE_HECI_3 0xa874 /* Core Ultra HECI */
#define PCI_PRODUCT_INTEL_LNL_CSE_HECI_4 0xa875 /* Core Ultra HECI */
#define PCI_PRODUCT_INTEL_LNL_I3C_2 0xa877 /* Core Ultra I3C */
#define PCI_PRODUCT_INTEL_LNL_I2C_0 0xa878 /* Core Ultra I2C */
#define PCI_PRODUCT_INTEL_LNL_I2C_1 0xa879 /* Core Ultra I2C */
#define PCI_PRODUCT_INTEL_LNL_I2C_2 0xa87a /* Core Ultra I2C */
#define PCI_PRODUCT_INTEL_LNL_I2C_3 0xa87b /* Core Ultra I2C */
#define PCI_PRODUCT_INTEL_LNL_I3C_1 0xa87c /* Core Ultra I3C */
#define PCI_PRODUCT_INTEL_LNL_XHCI 0xa87d /* Core Ultra xHCI */
#define PCI_PRODUCT_INTEL_LNL_SRAM 0xa87f /* Core Ultra SRAM */
#define PCI_PRODUCT_INTEL_21152 0xb152 /* S21152BB */
#define PCI_PRODUCT_INTEL_21154 0xb154 /* 21154AE/BE */
#define PCI_PRODUCT_INTEL_CORE_DMI_0 0xd130 /* Core DMI */

View file

@ -2,7 +2,7 @@
* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* generated from:
* OpenBSD: pcidevs,v 1.2088 2024/09/04 23:56:43 dlg Exp
* OpenBSD: pcidevs,v 1.2089 2024/09/06 03:48:20 jsg Exp
*/
/* $NetBSD: pcidevs,v 1.30 1997/06/24 06:20:24 thorpej Exp $ */
@ -21975,6 +21975,38 @@ static const struct pci_known_product pci_known_products[] = {
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_APOLLOLAKE_HB,
"Apollo Lake Host",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_HB,
"Core Ultra Host",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_DTT,
"Core Ultra DTT",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_GT_1,
"Graphics",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_NPU,
"Core Ultra NPU",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_IPU,
"Core Ultra IPU",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_CT,
"Core Ultra CT",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_GT_2,
"Graphics",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_GT_3,
"Graphics",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_5100_HB,
"5100 Host",
@ -26399,6 +26431,214 @@ static const struct pci_known_product pci_known_products[] = {
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_RPL_U_GT_5,
"Graphics",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_ESPI,
"Core Ultra eSPI",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_P2SB_1,
"Core Ultra P2SB",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_PMC,
"Core Ultra PMC",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_SPI,
"Core Ultra SPI",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_TH,
"Core Ultra TH",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_UART_0,
"Core Ultra UART",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_UART_1,
"Core Ultra UART",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_GSPI_0,
"Core Ultra GSPI",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_HDA,
"Core Ultra HD Audio",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_GSPI_1,
"Core Ultra GSPI",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_TC_XHCI,
"Core Ultra xHCI",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_TBT_DMA0,
"Core Ultra TBT",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_TBT_DMA1,
"Core Ultra TBT",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_PCIE_1,
"Core Ultra PCIE",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_PCIE_2,
"Core Ultra PCIE",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_PCIE_3,
"Core Ultra PCIE",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_PCIE_4,
"Core Ultra PCIE",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_PCIE_5,
"Core Ultra PCIE",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_PCIE_6,
"Core Ultra PCIE",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_ISH,
"Core Ultra ISH",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_GSPI_2,
"Core Ultra GSPI",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_THC_0_1,
"Core Ultra THC",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_THC_0_2,
"Core Ultra THC",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_THC_1_1,
"Core Ultra THC",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_THC_1_2,
"Core Ultra THC",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_P2SB_2,
"Core Ultra P2SB",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_TC_PCIE_21,
"Core Ultra PCIE",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_TC_PCIE_22,
"Core Ultra PCIE",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_I2C_4,
"Core Ultra I2C",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_I2C_5,
"Core Ultra I2C",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_UART_2,
"Core Ultra UART",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_HECI_4,
"Core Ultra HECI",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_HECI_5,
"Core Ultra HECI",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_HECI_6,
"Core Ultra HECI",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_TC_PCIE_23,
"Core Ultra PCIE",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_HECI_1,
"Core Ultra HECI",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_HECI_2,
"Core Ultra HECI",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_HECI_3,
"Core Ultra HECI",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_CSE_HECI_1,
"Core Ultra HECI",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_CSE_HECI_2,
"Core Ultra HECI",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_IDER,
"Core Ultra IDE-R",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_KT,
"Core Ultra KT",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_CSE_HECI_3,
"Core Ultra HECI",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_CSE_HECI_4,
"Core Ultra HECI",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_I3C_2,
"Core Ultra I3C",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_I2C_0,
"Core Ultra I2C",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_I2C_1,
"Core Ultra I2C",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_I2C_2,
"Core Ultra I2C",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_I2C_3,
"Core Ultra I2C",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_I3C_1,
"Core Ultra I3C",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_XHCI,
"Core Ultra xHCI",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_LNL_SRAM,
"Core Ultra SRAM",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_21152,
"S21152BB",

View file

@ -1,4 +1,4 @@
/* $OpenBSD: pciide_cmd_reg.h,v 1.11 2010/07/23 07:47:13 jsg Exp $ */
/* $OpenBSD: pciide_cmd_reg.h,v 1.12 2024/09/06 10:54:08 jsg Exp $ */
/* $NetBSD: pciide_cmd_reg.h,v 1.9 2000/08/02 20:23:46 bouyer Exp $ */
/*
@ -78,12 +78,12 @@
#define CMD_DMA 0x00
#define CMD_DMA_MULTIPLE 0x01
#define CMD_DMA_LINE 0x03
/* the followings bits are only for 0646U/646U2/648/649 */
/* the following bits are only for 0646U/646U2/648/649 */
#define CMD_DMA_IRQ(chan) (0x4 << (chan))
#define CMD_DMA_IRQ_DIS(chan) (0x10 << (chan))
#define CMD_DMA_RST 0x40
/* the followings are only for 0646U/646U2/648/649 */
/* the following is only for 0646U/646U2/648/649 */
/* busmaster control/status register */
#define CMD_BICSR 0x79
#define CMD_BICSR_80(chan) (0x01 << (chan))