sync with OpenBSD -current
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parent
074e641852
commit
8d26df7b18
GPG key ID:
F42C07F07E2E35B7
19 changed files with 436 additions and 412 deletions
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@ -1,4 +1,4 @@
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/* $OpenBSD: if_ix.c,v 1.217 2024/09/04 07:54:52 mglocker Exp $ */
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/* $OpenBSD: if_ix.c,v 1.218 2024/10/04 05:22:10 yasuoka Exp $ */
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/******************************************************************************
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@ -508,8 +508,7 @@ ixgbe_start(struct ifqueue *ifq)
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* hardware that this frame is available to transmit.
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*/
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if (post)
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IXGBE_WRITE_REG(&sc->hw, IXGBE_TDT(txr->me),
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txr->next_avail_desc);
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IXGBE_WRITE_REG(&sc->hw, txr->tail, txr->next_avail_desc);
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}
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/*********************************************************************
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@ -706,7 +705,7 @@ ixgbe_watchdog(struct ifnet * ifp)
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for (i = 0; i < sc->num_queues; i++, txr++) {
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printf("%s: Queue(%d) tdh = %d, hw tdt = %d\n", ifp->if_xname, i,
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IXGBE_READ_REG(hw, IXGBE_TDH(i)),
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IXGBE_READ_REG(hw, IXGBE_TDT(i)));
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IXGBE_READ_REG(hw, sc->tx_rings[i].tail));
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printf("%s: TX(%d) Next TX to Clean = %d\n", ifp->if_xname,
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i, txr->next_to_clean);
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}
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@ -826,7 +825,7 @@ ixgbe_init(void *arg)
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msec_delay(1);
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}
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IXGBE_WRITE_FLUSH(&sc->hw);
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IXGBE_WRITE_REG(&sc->hw, IXGBE_RDT(i), rxr->last_desc_filled);
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IXGBE_WRITE_REG(&sc->hw, rxr[i].tail, rxr->last_desc_filled);
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}
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/* Set up VLAN support and filter */
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@ -2365,9 +2364,12 @@ ixgbe_initialize_transmit_units(struct ix_softc *sc)
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IXGBE_WRITE_REG(hw, IXGBE_TDLEN(i),
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sc->num_tx_desc * sizeof(struct ixgbe_legacy_tx_desc));
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/* Set Tx Tail register */
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txr->tail = IXGBE_TDT(i);
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/* Setup the HW Tx Head and Tail descriptor pointers */
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IXGBE_WRITE_REG(hw, IXGBE_TDH(i), 0);
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IXGBE_WRITE_REG(hw, IXGBE_TDT(i), 0);
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IXGBE_WRITE_REG(hw, txr->tail, 0);
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/* Setup Transmit Descriptor Cmd Settings */
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txr->txd_cmd = IXGBE_TXD_CMD_IFCS;
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@ -2844,8 +2846,7 @@ ixgbe_rxrefill(void *xrxr)
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if (ixgbe_rxfill(rxr)) {
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/* Advance the Rx Queue "Tail Pointer" */
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IXGBE_WRITE_REG(&sc->hw, IXGBE_RDT(rxr->me),
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rxr->last_desc_filled);
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IXGBE_WRITE_REG(&sc->hw, rxr->tail, rxr->last_desc_filled);
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} else if (if_rxr_inuse(&rxr->rx_ring) == 0)
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timeout_add(&rxr->rx_refill, 1);
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@ -2940,6 +2941,9 @@ ixgbe_initialize_receive_units(struct ix_softc *sc)
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srrctl = bufsz | IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
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IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(i), srrctl);
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/* Capture Rx Tail index */
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rxr->tail = IXGBE_RDT(i);
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if (ISSET(ifp->if_xflags, IFXF_LRO)) {
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rdrxctl = IXGBE_READ_REG(&sc->hw, IXGBE_RSCCTL(i));
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@ -2952,7 +2956,7 @@ ixgbe_initialize_receive_units(struct ix_softc *sc)
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/* Setup the HW Rx Head and Tail Descriptor Pointers */
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IXGBE_WRITE_REG(hw, IXGBE_RDH(i), 0);
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IXGBE_WRITE_REG(hw, IXGBE_RDT(i), 0);
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IXGBE_WRITE_REG(hw, rxr->tail, 0);
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}
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if (sc->hw.mac.type != ixgbe_mac_82598EB) {
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@ -1,4 +1,4 @@
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/* $OpenBSD: if_ix.h,v 1.47 2024/05/21 11:19:39 bluhm Exp $ */
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/* $OpenBSD: if_ix.h,v 1.48 2024/10/04 05:22:10 yasuoka Exp $ */
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/******************************************************************************
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@ -169,6 +169,7 @@ struct ix_txring {
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struct ix_softc *sc;
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struct ifqueue *ifq;
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uint32_t me;
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uint32_t tail;
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uint32_t watchdog_timer;
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union ixgbe_adv_tx_desc *tx_base;
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struct ixgbe_tx_buf *tx_buffers;
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@ -194,6 +195,7 @@ struct ix_rxring {
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struct ix_softc *sc;
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struct ifiqueue *ifiq;
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uint32_t me;
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uint32_t tail;
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union ixgbe_adv_rx_desc *rx_base;
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struct ixgbe_dma_alloc rxdma;
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#if 0
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@ -244,6 +246,7 @@ struct ix_softc {
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uint16_t num_segs;
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uint32_t link_speed;
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bool link_up;
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bool link_enabled;
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uint32_t linkvec;
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struct rwlock sfflock;
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@ -1,4 +1,4 @@
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/* $OpenBSD: if_mcx.c,v 1.115 2024/05/24 06:02:53 jsg Exp $ */
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/* $OpenBSD: if_mcx.c,v 1.116 2024/10/04 06:37:22 jmatthew Exp $ */
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/*
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* Copyright (c) 2017 David Gwynne <dlg@openbsd.org>
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@ -2927,23 +2927,25 @@ mcx_attach(struct device *parent, struct device *self, void *aux)
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goto teardown;
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}
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printf(", %s, address %s\n", intrstr,
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ether_sprintf(sc->sc_ac.ac_enaddr));
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msix--; /* admin ops took one */
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sc->sc_intrmap = intrmap_create(&sc->sc_dev, msix, MCX_MAX_QUEUES,
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INTRMAP_POWEROF2);
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if (sc->sc_intrmap == NULL) {
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printf("%s: unable to create interrupt map\n", DEVNAME(sc));
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printf(": unable to create interrupt map\n");
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goto teardown;
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}
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sc->sc_queues = mallocarray(intrmap_count(sc->sc_intrmap),
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sizeof(*sc->sc_queues), M_DEVBUF, M_WAITOK|M_ZERO);
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if (sc->sc_queues == NULL) {
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printf("%s: unable to create queues\n", DEVNAME(sc));
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printf(": unable to create queues\n");
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goto intrunmap;
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}
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printf(", %s, %d queue%s, address %s\n", intrstr,
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intrmap_count(sc->sc_intrmap),
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intrmap_count(sc->sc_intrmap) > 1 ? "s" : "",
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ether_sprintf(sc->sc_ac.ac_enaddr));
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strlcpy(ifp->if_xname, DEVNAME(sc), IFNAMSIZ);
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ifp->if_softc = sc;
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ifp->if_flags = IFF_BROADCAST | IFF_MULTICAST | IFF_SIMPLEX;
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@ -1,4 +1,4 @@
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/* $OpenBSD: if_qwx_pci.c,v 1.22 2024/07/06 05:34:35 patrick Exp $ */
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/* $OpenBSD: if_qwx_pci.c,v 1.23 2024/10/04 07:46:33 kevlo Exp $ */
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/*
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* Copyright 2023 Stefan Sperling <stsp@openbsd.org>
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@ -374,11 +374,9 @@ struct qwx_pci_softc {
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struct qwx_dmamem *cmd_ctxt;
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struct qwx_pci_xfer_ring xfer_rings[4];
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#define QWX_PCI_XFER_RING_LOOPBACK_OUTBOUND 0
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#define QWX_PCI_XFER_RING_LOOPBACK_INBOUND 1
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#define QWX_PCI_XFER_RING_IPCR_OUTBOUND 2
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#define QWX_PCI_XFER_RING_IPCR_INBOUND 3
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struct qwx_pci_xfer_ring xfer_rings[2];
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#define QWX_PCI_XFER_RING_IPCR_OUTBOUND 0
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#define QWX_PCI_XFER_RING_IPCR_INBOUND 1
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struct qwx_pci_event_ring event_rings[QWX_NUM_EVENT_CTX];
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struct qwx_pci_cmd_ring cmd_ring;
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};
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@ -745,7 +743,6 @@ qwx_pci_attach(struct device *parent, struct device *self, void *aux)
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struct ieee80211com *ic = &sc->sc_ic;
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struct ifnet *ifp = &ic->ic_if;
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uint32_t soc_hw_version_major, soc_hw_version_minor;
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const struct qwx_pci_ops *pci_ops;
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struct pci_attach_args *pa = aux;
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pci_intr_handle_t ih;
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pcireg_t memtype, reg;
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@ -884,6 +881,9 @@ qwx_pci_attach(struct device *parent, struct device *self, void *aux)
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pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0);
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/* register PCI ops */
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psc->sc_pci_ops = &qwx_pci_ops_qca6390;
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switch (PCI_PRODUCT(pa->pa_id)) {
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case PCI_PRODUCT_QUALCOMM_QCA6390:
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qwx_pci_read_hw_version(sc, &soc_hw_version_major,
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@ -898,11 +898,10 @@ qwx_pci_attach(struct device *parent, struct device *self, void *aux)
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return;
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}
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pci_ops = &qwx_pci_ops_qca6390;
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psc->max_chan = QWX_MHI_CONFIG_QCA6390_MAX_CHANNELS;
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break;
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case PCI_PRODUCT_QUALCOMM_QCN9074:
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pci_ops = &qwx_pci_ops_qcn9074;
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psc->sc_pci_ops = &qwx_pci_ops_qcn9074;
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sc->sc_hw_rev = ATH11K_HW_QCN9074_HW10;
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psc->max_chan = QWX_MHI_CONFIG_QCA9074_MAX_CHANNELS;
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break;
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@ -932,7 +931,6 @@ unsupported_wcn6855_soc:
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return;
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}
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pci_ops = &qwx_pci_ops_qca6390;
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psc->max_chan = QWX_MHI_CONFIG_QCA6390_MAX_CHANNELS;
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break;
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default:
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@ -940,9 +938,6 @@ unsupported_wcn6855_soc:
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return;
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}
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/* register PCI ops */
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psc->sc_pci_ops = pci_ops;
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error = qwx_pcic_init_msi_config(sc);
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if (error)
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goto err_pci_free_region;
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@ -1296,18 +1291,6 @@ qwx_pci_alloc_xfer_rings_qca6390(struct qwx_pci_softc *psc)
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struct qwx_softc *sc = &psc->sc_sc;
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int ret;
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ret = qwx_pci_alloc_xfer_ring(sc,
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&psc->xfer_rings[QWX_PCI_XFER_RING_LOOPBACK_OUTBOUND],
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0, MHI_CHAN_TYPE_OUTBOUND, 0, 32);
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if (ret)
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goto fail;
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ret = qwx_pci_alloc_xfer_ring(sc,
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&psc->xfer_rings[QWX_PCI_XFER_RING_LOOPBACK_INBOUND],
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1, MHI_CHAN_TYPE_INBOUND, 0, 32);
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if (ret)
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goto fail;
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ret = qwx_pci_alloc_xfer_ring(sc,
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&psc->xfer_rings[QWX_PCI_XFER_RING_IPCR_OUTBOUND],
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20, MHI_CHAN_TYPE_OUTBOUND, 1, 64);
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@ -1332,18 +1315,6 @@ qwx_pci_alloc_xfer_rings_qcn9074(struct qwx_pci_softc *psc)
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struct qwx_softc *sc = &psc->sc_sc;
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int ret;
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ret = qwx_pci_alloc_xfer_ring(sc,
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&psc->xfer_rings[QWX_PCI_XFER_RING_LOOPBACK_OUTBOUND],
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0, MHI_CHAN_TYPE_OUTBOUND, 1, 32);
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if (ret)
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goto fail;
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ret = qwx_pci_alloc_xfer_ring(sc,
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&psc->xfer_rings[QWX_PCI_XFER_RING_LOOPBACK_INBOUND],
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1, MHI_CHAN_TYPE_INBOUND, 1, 32);
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if (ret)
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goto fail;
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ret = qwx_pci_alloc_xfer_ring(sc,
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&psc->xfer_rings[QWX_PCI_XFER_RING_IPCR_OUTBOUND],
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20, MHI_CHAN_TYPE_OUTBOUND, 1, 32);
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