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This commit is contained in:
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5b49f88fed
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F42C07F07E2E35B7
681 changed files with 35748 additions and 35743 deletions
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@ -6,17 +6,17 @@
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* All rights reserved.
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*
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* Author: Chris G. Demetriou
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*
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*
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* Permission to use, copy, modify and distribute this software and
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* its documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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@ -236,7 +236,7 @@ tga_getdevconfig(memt, pc, tag, dc)
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dc->dc_paddr = ALPHA_K0SEG_TO_PHYS(dc->dc_vaddr); /* XXX */
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#endif
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DPRINTF("tga_getdevconfig: allocating subregion\n");
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bus_space_subregion(dc->dc_memt, dc->dc_memh,
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bus_space_subregion(dc->dc_memt, dc->dc_memh,
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TGA_MEM_CREGS, TGA_CREGS_SIZE,
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&dc->dc_regs);
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@ -274,7 +274,7 @@ tga_getdevconfig(memt, pc, tag, dc)
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if (dc->dc_tga2) {
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tga2_init(dc);
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}
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i = TGARREG(dc, TGA_REG_VHCR) & 0x1ff;
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DPRINTF("tga_getdevconfig: TGA_REG_VHCR & 0x1ff = %d\n", i);
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switch (i) { /* XXX */
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@ -319,14 +319,14 @@ tga_getdevconfig(memt, pc, tag, dc)
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1 * tgac->tgac_vvbr_units;
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dc->dc_blanked = 1;
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tga_unblank(dc);
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DPRINTF("tga_getdevconfig: dc_videobase = 0x%016llx\n"
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" dc_vaddr = 0x%016llx\n"
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" tgac_dbuf[0] = %d\n"
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" tgac_vvbr_units = %d\n",
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dc->dc_videobase, dc->dc_vaddr, tgac->tgac_dbuf[0],
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tgac->tgac_vvbr_units);
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/*
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* Set all bits in the pixel mask, to enable writes to all pixels.
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* It seems that the console firmware clears some of them
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@ -362,10 +362,10 @@ tga_getdevconfig(memt, pc, tag, dc)
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DPRINTF("tga_getdevconfig: wsfont_init\n");
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wsfont_init();
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if (rip->ri_width > 80*12)
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if (rip->ri_width > 80*12)
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/* High res screen, choose a big font */
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cookie = wsfont_find(NULL, 12, 0, 0);
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else
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else
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/* lower res, choose a 8 pixel wide font */
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cookie = wsfont_find(NULL, 8, 0, 0);
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if (cookie <= 0)
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@ -384,17 +384,17 @@ tga_getdevconfig(memt, pc, tag, dc)
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rip->ri_wsfcookie = cookie;
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/* fill screen size */
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rasops_init(rip, rip->ri_height / rip->ri_font->fontheight,
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rip->ri_width / rip->ri_font->fontwidth);
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rip->ri_width / rip->ri_font->fontwidth);
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/* add our accelerated functions */
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/* XXX shouldn't have to do this; rasops should leave non-NULL
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/* XXX shouldn't have to do this; rasops should leave non-NULL
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* XXX entries alone.
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*/
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rip->ri_ops.copyrows = tga_copyrows;
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rip->ri_ops.eraserows = tga_eraserows;
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rip->ri_ops.erasecols = tga_erasecols;
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rip->ri_ops.copycols = tga_copycols;
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rip->ri_ops.putchar = tga_putchar;
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rip->ri_ops.putchar = tga_putchar;
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tga_stdscreen.nrows = rip->ri_rows;
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tga_stdscreen.ncols = rip->ri_cols;
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@ -489,18 +489,18 @@ tgaattach(parent, self, aux)
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"bt485_funcs\n",
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(sc->sc_dc->dc_tgaconf->ramdac_funcs == bt485_funcs)
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? "==" : "!=");
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if (sc->sc_dc->dc_tgaconf->ramdac_funcs == bt485_funcs)
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sc->sc_dc->dc_ramdac_cookie =
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if (sc->sc_dc->dc_tgaconf->ramdac_funcs == bt485_funcs)
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sc->sc_dc->dc_ramdac_cookie =
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sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc,
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tga_sched_update, tga_ramdac_wr, tga_ramdac_rd);
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else
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sc->sc_dc->dc_ramdac_cookie =
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sc->sc_dc->dc_ramdac_cookie =
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sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc,
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tga_sched_update, tga_bt463_wr, tga_bt463_rd);
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} else {
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DPRINTF("tgaattach: sc->sc_dc->dc_tga2\n");
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sc->sc_dc->dc_ramdac_cookie =
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sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc,
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sc->sc_dc->dc_ramdac_cookie =
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sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc,
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tga_sched_update, tga2_ramdac_wr, tga2_ramdac_rd);
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/* XXX this is a bit of a hack, setting the dotclock here */
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@ -548,14 +548,14 @@ tgaattach(parent, self, aux)
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#endif
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}
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void
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void
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tga_config_interrupts (d)
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struct device *d;
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{
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struct tga_softc *sc = (struct tga_softc *)d;
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sc->sc_dc->dc_intrenabled = 1;
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}
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int
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tga_ioctl(v, cmd, data, flag, p)
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@ -585,7 +585,7 @@ tga_ioctl(v, cmd, data, flag, p)
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default:
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/* XXX it this useful, except for not breaking Xtga? */
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TGAWREG(dc, TGA_REG_VVBR, 1);
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break;
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break;
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}
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break;
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@ -663,7 +663,7 @@ tga_sched_update(v, f)
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TGAWREG(dc, TGA_REG_SISR, 0x00000001);
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TGAREGWB(dc, TGA_REG_SISR, 1);
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}
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return 0;
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}
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@ -685,7 +685,7 @@ tga_intr(v)
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TGAREGWB(dc, TGA_REG_SISR, 1);
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/* This was our interrupt, even if we're puzzled as to why
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* we got it. Don't make the interrupt handler think it
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* was a stray.
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* was a stray.
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*/
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return -1;
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} else {
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@ -715,7 +715,7 @@ tga_mmap(v, offset, prot)
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return -1;
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if (sc->sc_mode == WSDISPLAYIO_MODE_DUMBFB) {
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/*
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/*
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* The framebuffer starts at the upper half of tga mem
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*/
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offset += dc->dc_tgaconf->tgac_cspace_size / 2;
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@ -744,7 +744,7 @@ tga_alloc_screen(v, type, cookiep, curxp, curyp, attrp)
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*cookiep = &sc->sc_dc->dc_rinfo; /* one and only for now */
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*curxp = 0;
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*curyp = 0;
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sc->sc_dc->dc_rinfo.ri_ops.pack_attr(&sc->sc_dc->dc_rinfo,
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sc->sc_dc->dc_rinfo.ri_ops.pack_attr(&sc->sc_dc->dc_rinfo,
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0, 0, 0, &defattr);
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*attrp = defattr;
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sc->nscreens++;
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@ -875,7 +875,7 @@ tga_cnattach(iot, memt, pc, bus, device, function)
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}
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dcp->dc_rinfo.ri_ops.pack_attr(&dcp->dc_rinfo, 0, 0, 0, &defattr);
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wsdisplay_cnattach(&tga_stdscreen, &dcp->dc_rinfo, 0, 0, defattr);
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return(0);
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}
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@ -957,7 +957,7 @@ tga_builtin_set_cursor(dc, cursorp)
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TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) & ~0x04);
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}
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if (v & WSDISPLAY_CURSOR_DOPOS) {
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TGAWREG(dc, TGA_REG_CXYR,
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TGAWREG(dc, TGA_REG_CXYR,
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((cursorp->pos.y & 0xfff) << 12) | (cursorp->pos.x & 0xfff));
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}
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if (v & WSDISPLAY_CURSOR_DOCMAP) {
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@ -1194,9 +1194,9 @@ tga_rop_vtov(dst, dx, dy, w, h, src, sx, sy)
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srcb = sy * src->ri_stride + sx * (src->ri_depth/8);
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dstb = dy * dst->ri_stride + dx * (dst->ri_depth/8);
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tga_srcb = offset + (sy + src->ri_yorigin) * src->ri_stride +
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tga_srcb = offset + (sy + src->ri_yorigin) * src->ri_stride +
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(sx + src->ri_xorigin) * (src->ri_depth/8);
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tga_dstb = offset + (dy + dst->ri_yorigin) * dst->ri_stride +
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tga_dstb = offset + (dy + dst->ri_yorigin) * dst->ri_stride +
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(dx + dst->ri_xorigin) * (dst->ri_depth/8);
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TGAWALREG(dc, TGA_REG_GMOR, 3, 0x0007); /* Copy mode */
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@ -1218,7 +1218,7 @@ tga_rop_vtov(dst, dx, dy, w, h, src, sx, sy)
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x <= xend && xleft >= 4*64;
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x += XINC256, xleft -= XINC256) {
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/* XXX XXX Eight writes to different addresses should fill
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/* XXX XXX Eight writes to different addresses should fill
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* XXX XXX up the write buffers on 21064 and 21164 chips,
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* XXX XXX but later CPUs might have larger write buffers which
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* XXX XXX require further unrolling of this loop, or the
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@ -1265,7 +1265,7 @@ tga_rop_vtov(dst, dx, dy, w, h, src, sx, sy)
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x >= xend && xleft >= 4*64;
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x -= XINC256, xleft -= XINC256) {
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/* XXX XXX Eight writes to different addresses should fill
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/* XXX XXX Eight writes to different addresses should fill
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* XXX XXX up the write buffers on 21064 and 21164 chips,
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* XXX XXX but later CPUs might have larger write buffers which
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* XXX XXX require further unrolling of this loop, or the
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@ -1339,7 +1339,7 @@ tga_putchar(c, row, col, uc, attr)
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ri->ri_ops.unpack_attr(c, attr, &fg, &bg, &ul);
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TGAWREG(dc, TGA_REG_GFGR, ri->ri_devcmap[fg]);
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TGAWREG(dc, TGA_REG_GBGR, ri->ri_devcmap[bg]);
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/* Set raster operation to "copy"... */
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if (ri->ri_depth == 8)
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TGAWREG(dc, TGA_REG_GOPR, 0x3);
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@ -1351,15 +1351,15 @@ tga_putchar(c, row, col, uc, attr)
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/* Set drawing mode to opaque stipple. */
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TGAWREG(dc, TGA_REG_GMOR, 0x1);
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/* Insert write barrier before actually sending data */
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/* XXX Abuses the fact that there is only one write barrier on Alphas */
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TGAREGWB(dc, TGA_REG_GMOR, 1);
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while (height--) {
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/* The actual stipple write */
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*rp = fr[0] | (fr[1] << 8) | (fr[2] << 16) | (fr[3] << 24);
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*rp = fr[0] | (fr[1] << 8) | (fr[2] << 16) | (fr[3] << 24);
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fr += fs;
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rp = (int32_t *)((caddr_t)rp + ri->ri_stride);
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}
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@ -1418,7 +1418,7 @@ tga_eraserows(c, row, num, attr)
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/* Set drawing mode to block fill. */
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TGAWREG(dc, TGA_REG_GMOR, 0x2d);
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/* Insert write barrier before actually sending data */
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/* XXX Abuses the fact that there is only one write barrier on Alphas */
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TGAREGWB(dc, TGA_REG_GMOR, 1);
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@ -1430,7 +1430,7 @@ tga_eraserows(c, row, num, attr)
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/* Set graphics mode back to normal. */
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TGAWREG(dc, TGA_REG_GMOR, 0);
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return 0;
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}
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@ -1475,7 +1475,7 @@ tga_erasecols (c, row, col, num, attr)
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/* Set drawing mode to block fill. */
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TGAWREG(dc, TGA_REG_GMOR, 0x2d);
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/* Insert write barrier before actually sending data */
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/* XXX Abuses the fact that there is only one write barrier on Alphas */
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TGAREGWB(dc, TGA_REG_GMOR, 1);
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@ -1519,7 +1519,7 @@ tga2_ramdac_wr(v, btreg, val)
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if (btreg > BT485_REG_MAX)
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panic("tga_ramdac_wr: reg %d out of range", btreg);
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bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC +
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bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC +
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(0xe << 12) + (btreg << 8), 4, &ramdac);
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bus_space_write_4(dc->dc_memt, ramdac, 0, val & 0xff);
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bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_WRITE);
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@ -1533,11 +1533,11 @@ tga_bt463_rd(v, btreg)
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struct tga_devconfig *dc = v;
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tga_reg_t rdval;
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/*
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* Strobe CE# (high->low->high) since status and data are latched on
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/*
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* Strobe CE# (high->low->high) since status and data are latched on
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* the falling and rising edges (respectively) of this active-low signal.
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*/
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TGAREGWB(dc, TGA_REG_EPSR, 1);
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TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1);
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TGAREGWB(dc, TGA_REG_EPSR, 1);
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@ -1560,12 +1560,12 @@ tga_bt463_wr(v, btreg, val)
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{
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struct tga_devconfig *dc = v;
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/*
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/*
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* In spite of the 21030 documentation, to set the MPU bus bits for
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* a write, you set them in the upper bits of EPDR, not EPSR.
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*/
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/*
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/*
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* Strobe CE# (high->low->high) since status and data are latched on
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* the falling and rising edges of this active-low signal.
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*/
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@ -1609,7 +1609,7 @@ tga2_ramdac_rd(v, btreg)
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if (btreg > BT485_REG_MAX)
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panic("tga_ramdac_rd: reg %d out of range", btreg);
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bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC +
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bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC +
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(0xe << 12) + (btreg << 8), 4, &ramdac);
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retval = bus_space_read_4(dc->dc_memt, ramdac, 0) & 0xff;
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bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_READ);
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@ -1646,19 +1646,19 @@ tga2_init(dc)
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tga2_ics9110_wr(dc, m->dotclock);
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}
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#if 0
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TGAWREG(dc, TGA_REG_VHCR,
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TGAWREG(dc, TGA_REG_VHCR,
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((m->hbp / 4) << 21) |
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((m->hsync / 4) << 14) |
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(((m->hfp - 4) / 4) << 9) |
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((m->cols + 4) / 4));
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#else
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TGAWREG(dc, TGA_REG_VHCR,
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TGAWREG(dc, TGA_REG_VHCR,
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((m->hbp / 4) << 21) |
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((m->hsync / 4) << 14) |
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(((m->hfp) / 4) << 9) |
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((m->cols) / 4));
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#endif
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TGAWREG(dc, TGA_REG_VVCR,
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TGAWREG(dc, TGA_REG_VVCR,
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(m->vbp << 22) |
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(m->vsync << 16) |
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(m->vfp << 11) |
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@ -1730,14 +1730,14 @@ tga2_ics9110_wr(dc, dotclock)
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for (i = 24; i > 0; i--) {
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u_int32_t writeval;
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writeval = valU & 0x1;
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if (i == 1)
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writeval |= 0x2;
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if (i == 1)
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writeval |= 0x2;
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valU >>= 1;
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bus_space_write_4(dc->dc_memt, clock, 0, writeval);
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bus_space_barrier(dc->dc_memt, clock, 0, 4, BUS_SPACE_BARRIER_WRITE);
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}
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}
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bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV +
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TGA2_MEM_CLOCK + (0xe << 12) + (0x1 << 11) + (0x1 << 11), 4,
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&clock); /* XXX */
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