From 4de47ea9889506a49d3d567e4a69227468741d0a Mon Sep 17 00:00:00 2001 From: purplerain Date: Tue, 26 Sep 2023 19:52:17 +0000 Subject: [PATCH] zap whitespace and tab --- lib/libcrypto/aes/asm/aes-mips.pl | 10 +- lib/libcrypto/aes/asm/aesni-x86.pl | 16 +- lib/libcrypto/aes/asm/bsaes-x86_64.pl | 4 +- lib/libcrypto/aes/asm/vpaes-x86.pl | 8 +- lib/libcrypto/aes/asm/vpaes-x86_64.pl | 26 +- lib/libcrypto/arc4random/getentropy_hpux.c | 2 +- lib/libcrypto/arc4random/getentropy_win.c | 2 +- lib/libcrypto/arch/alpha/Makefile.inc | 2 +- lib/libcrypto/arch/alpha/opensslconf.h | 2 +- lib/libcrypto/arch/hppa/Makefile.inc | 2 +- lib/libcrypto/arch/hppa/opensslconf.h | 2 +- lib/libcrypto/arch/m88k/opensslconf.h | 2 +- lib/libcrypto/arch/mips64/Makefile.inc | 2 +- lib/libcrypto/arch/mips64/opensslconf.h | 2 +- lib/libcrypto/arch/powerpc/Makefile.inc | 2 +- lib/libcrypto/arch/powerpc/opensslconf.h | 2 +- lib/libcrypto/arch/powerpc64/Makefile.inc | 2 +- lib/libcrypto/arch/powerpc64/opensslconf.h | 2 +- lib/libcrypto/arch/riscv64/opensslconf.h | 2 +- lib/libcrypto/arch/sh/opensslconf.h | 2 +- lib/libcrypto/arch/sparc64/Makefile.inc | 2 +- lib/libcrypto/arch/sparc64/opensslconf.h | 2 +- lib/libcrypto/bn/arch/riscv64/bn_arch.h | 2 +- lib/libcrypto/bn/asm/alpha-mont.pl | 2 +- lib/libcrypto/bn/asm/armv4-mont.pl | 6 +- lib/libcrypto/bn/asm/bn-586.pl | 2 +- lib/libcrypto/bn/asm/co-586.pl | 12 +- lib/libcrypto/bn/asm/mips-mont.pl | 2 +- lib/libcrypto/bn/asm/mips.pl | 6 +- lib/libcrypto/bn/asm/parisc-mont.pl | 22 +- lib/libcrypto/bn/asm/ppc-mont.pl | 14 +- lib/libcrypto/bn/asm/ppc.pl | 264 +- lib/libcrypto/bn/asm/ppc64-mont.pl | 20 +- lib/libcrypto/bn/asm/x86-mont.pl | 18 +- lib/libcrypto/bn/asm/x86_64-mont.pl | 9 +- lib/libcrypto/bytestring/bytestring.h | 2 +- lib/libcrypto/camellia/asm/cmll-x86.pl | 6 +- lib/libcrypto/camellia/camellia.c | 4 +- lib/libcrypto/camellia/camellia.h | 2 +- lib/libcrypto/camellia/cmll_cbc.c | 2 +- lib/libcrypto/camellia/cmll_cfb.c | 14 +- lib/libcrypto/camellia/cmll_ctr.c | 2 +- lib/libcrypto/camellia/cmll_ecb.c | 2 +- lib/libcrypto/camellia/cmll_local.h | 4 +- lib/libcrypto/camellia/cmll_misc.c | 2 +- lib/libcrypto/camellia/cmll_ofb.c | 14 +- lib/libcrypto/conf/README | 2 +- lib/libcrypto/conf/keysets.pl | 12 +- lib/libcrypto/des/asm/des-586.pl | 6 +- lib/libcrypto/des/asm/des_enc.m4 | 10 +- lib/libcrypto/des/asm/desboth.pl | 2 +- lib/libcrypto/dh/dh_asn1.c | 2 +- lib/libcrypto/dh/dh_check.c | 12 +- lib/libcrypto/dh/dh_err.c | 2 +- lib/libcrypto/dh/dh_key.c | 12 +- lib/libcrypto/dh/dh_pmeth.c | 6 +- lib/libcrypto/dsa/dsa.h | 12 +- lib/libcrypto/dsa/dsa_local.h | 2 +- lib/libcrypto/gost/gost_err.c | 2 +- lib/libcrypto/gost/gost_local.h | 2 +- lib/libcrypto/gost/gostr341194.c | 4 +- lib/libcrypto/idea/idea_local.h | 2 +- lib/libcrypto/md5/asm/md5-586.pl | 2 +- lib/libcrypto/modes/asm/ghash-armv4.pl | 2 +- lib/libcrypto/modes/asm/ghash-parisc.pl | 8 +- lib/libcrypto/modes/asm/ghash-x86.pl | 24 +- lib/libcrypto/modes/asm/ghash-x86_64.pl | 18 +- lib/libcrypto/objects/obj_dat.pl | 18 +- lib/libcrypto/objects/objects.pl | 12 +- lib/libcrypto/objects/objects.txt | 4 +- lib/libcrypto/pem/pkcs7.lis | 34 +- lib/libcrypto/perlasm/cbc.pl | 8 +- lib/libcrypto/perlasm/ppc-xlate.pl | 2 +- lib/libcrypto/perlasm/readme | 2 +- lib/libcrypto/perlasm/x86_64-xlate.pl | 20 +- lib/libcrypto/pkcs12/p12_asn.c | 16 +- lib/libcrypto/pkcs7/pk7_asn1.c | 12 +- lib/libcrypto/pkcs7/pk7_doit.c | 2 +- lib/libcrypto/rc2/rrc2.doc | 100 +- lib/libcrypto/rc2/version | 2 +- lib/libcrypto/rc4/asm/rc4-md5-x86_64.pl | 4 +- lib/libcrypto/rc4/asm/rc4-parisc.pl | 4 +- lib/libcrypto/rc4/asm/rc4-x86_64.pl | 2 +- lib/libcrypto/ripemd/asm/rmd-586.pl | 12 +- lib/libcrypto/rsa/rsa_oaep.c | 2 +- lib/libcrypto/sha/asm/sha256-586.pl | 4 +- lib/libcrypto/sha/asm/sha512-586.pl | 2 +- lib/libcrypto/sha/asm/sha512-parisc.pl | 4 +- lib/libcrypto/sha/asm/sha512-sparcv9.pl | 4 +- lib/libcrypto/stack/safestack.h | 4 +- lib/libcrypto/util/mkstack.pl | 2 +- lib/libcrypto/whrlpool/asm/wp-mmx.pl | 4 +- lib/libcrypto/x509/x509.h | 16 +- sys/arch/arm64/dev/acpipci.c | 2 +- sys/arch/i386/isa/ahc_isa.c | 2 +- sys/arch/i386/stand/libsa/pxe.h | 2 +- sys/dev/fdt/tascodec.c | 2 +- sys/dev/i2c/ihidev.c | 2 +- sys/dev/ic/bt8xx.h | 2 +- sys/dev/ic/gem.c | 16 +- sys/dev/ic/sili.c | 2 +- sys/dev/isa/ad1848.c | 28 +- sys/dev/isa/ad1848var.h | 8 +- sys/dev/isa/aps.c | 12 +- sys/dev/isa/fd.c | 4 +- sys/dev/isa/gus.c | 4 +- sys/dev/isa/hsq.c | 6 +- sys/dev/isa/i82365_isasubr.c | 4 +- sys/dev/isa/i82365_isavar.h | 2 +- sys/dev/isa/if_ec.c | 4 +- sys/dev/isa/if_eg.c | 66 +- sys/dev/isa/if_egreg.h | 4 +- sys/dev/isa/if_el.c | 2 +- sys/dev/isa/if_ex.c | 108 +- sys/dev/isa/if_ie.c | 20 +- sys/dev/isa/if_lc_isa.c | 2 +- sys/dev/isa/if_levar.h | 2 +- sys/dev/isa/if_ne_isa.c | 2 +- sys/dev/isa/if_we.c | 8 +- sys/dev/isa/isapnpdebug.c | 2 +- sys/dev/isa/isapnpres.c | 6 +- sys/dev/isa/isavar.h | 8 +- sys/dev/isa/lpt_isa.c | 22 +- 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sys/dev/microcode/aic7xxx/aicasm_macro_scan.l | 4 +- sys/dev/microcode/aic7xxx/aicasm_scan.l | 4 +- sys/dev/microcode/aic7xxx/aicasm_symbol.c | 6 +- .../microcode/atmel/atmel_at76c503_i3863_fw.h | 4 +- .../microcode/atmel/atmel_at76c503_rfmd2_fw.h | 4 +- .../atmel/atmel_at76c503_rfmd_acc_fw.h | 4 +- sys/dev/microcode/atmel/atmel_at76c505_rfmd.h | 4 +- sys/dev/microcode/atmel/atmel_intersil_fw.h | 4 +- .../microcode/atmel/atmel_rfmd2958-smc_fw.h | 6 +- sys/dev/microcode/atmel/atmel_rfmd2958_fw.h | 4 +- sys/dev/microcode/atmel/atmel_rfmd_fw.h | 5050 +-- sys/dev/microcode/atmel/atu-license | 4 +- sys/dev/microcode/bnx/bnxfw.h | 2 +- sys/dev/microcode/cyclades/cyzfirm.h | 26870 ++++++++-------- sys/dev/microcode/esa/esadsp.h | 2 +- sys/dev/microcode/fxp/rcvbundl.h | 30 +- sys/dev/microcode/isp/asm_1040.h | 2 +- sys/dev/microcode/isp/asm_1080.h | 2 +- sys/dev/microcode/isp/asm_12160.h | 2 +- sys/dev/microcode/isp/asm_2100.h | 2 +- sys/dev/microcode/isp/asm_2200.h | 2 +- sys/dev/microcode/isp/asm_2300.h | 2 +- sys/dev/microcode/isp/asm_2400.h | 2 +- sys/dev/microcode/isp/asm_2500.h | 2 +- sys/dev/microcode/isp/asm_sbus.h | 2 +- sys/dev/microcode/myx/eth_z8e.h | 2 +- sys/dev/microcode/myx/ethp_z8e.h | 2 +- sys/dev/microcode/rum/microcode.h | 2 +- sys/dev/microcode/siop/ncr53cxxx.c | 6 +- sys/dev/microcode/siop/osiop.ss | 2 +- sys/dev/microcode/symbol/spectrum24t_cf.h | 2 +- sys/dev/microcode/tht/microcode.h | 2 +- sys/dev/microcode/tht/tht-license | 2 +- sys/dev/microcode/tigon/ti_fw.h | 9144 +++--- sys/dev/microcode/tigon/ti_fw2.h | 9698 +++--- sys/dev/microcode/tusb3410/tusb3410-license | 82 +- sys/dev/microcode/tusb3410/tusb3410.h | 84 +- sys/dev/microcode/typhoon/3c990-license | 2 +- sys/dev/microcode/typhoon/3c990img.h | 8526 ++--- sys/dev/mii/brgphy.c | 10 +- sys/dev/mii/brgphyreg.h | 2 +- sys/dev/mii/ciphy.c | 4 +- sys/dev/mii/eephy.c | 2 +- sys/dev/mii/etphy.c | 10 +- sys/dev/mii/ipgphy.c | 4 +- sys/dev/mii/ipgphyreg.h | 6 +- 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.../amd/display/modules/color/color_gamma.c | 2 +- sys/dev/pci/drm/amd/include/amd_shared.h | 2 +- .../include/asic_reg/nbif/nbif_6_1_offset.h | 2254 +- sys/dev/pci/drm/amd/include/atomfirmware.h | 530 +- sys/dev/pci/drm/amd/include/atomfirmwareid.h | 4 +- sys/dev/pci/drm/amd/include/displayobject.h | 22 +- .../amd/include/ivsrcid/dcn/irqsrcs_dcn_1_0.h | 700 +- .../amd/include/ivsrcid/ivsrcid_vislands30.h | 48 +- .../include/ivsrcid/sdma1/irqsrcs_sdma1_5_0.h | 4 +- .../pci/drm/amd/include/navi10_ip_offset.h | 2 +- sys/dev/pci/drm/amd/include/pptable.h | 44 +- .../drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.c | 2 +- .../amd/pm/powerplay/inc/smu11_driver_if.h | 8 +- .../drm/amd/pm/powerplay/inc/smu73_discrete.h | 2 +- .../drm/amd/pm/powerplay/inc/smu74_discrete.h | 4 +- .../amd/pm/powerplay/inc/smu_ucode_xfer_cz.h | 64 +- .../pm/powerplay/inc/vega12/smu9_driver_if.h | 10 +- sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 4 +- .../inc/pmfw_if/smu11_driver_if_navi10.h | 234 +- .../pmfw_if/smu11_driver_if_sienna_cichlid.h | 322 +- .../pm/swsmu/inc/pmfw_if/smu12_driver_if.h | 2 +- .../pm/swsmu/inc/pmfw_if/smu_v11_0_7_ppsmc.h | 2 +- .../pm/swsmu/inc/pmfw_if/smu_v11_0_ppsmc.h | 8 +- .../pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h | 4 +- .../pm/swsmu/inc/pmfw_if/smu_v13_0_1_ppsmc.h | 26 +- .../amd/pm/swsmu/inc/smu_v11_0_7_pptable.h | 32 +- .../drm/amd/pm/swsmu/inc/smu_v11_0_pptable.h | 6 +- .../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 2 +- sys/dev/pci/drm/include/linux/types.h | 10 +- sys/dev/pci/drm/radeon/atombios.h | 2 +- sys/dev/pci/drm/ttm/ttm_resource.c | 2 +- sys/dev/pci/eap.c | 20 +- sys/dev/pci/eapreg.h | 4 +- sys/dev/pci/ehci_pci.c | 2 +- sys/dev/pci/emuxki.c | 20 +- sys/dev/pci/emuxkireg.h | 2 +- sys/dev/pci/envy.c | 8 +- sys/dev/pci/esareg.h | 4 +- sys/dev/pci/esavar.h | 4 +- sys/dev/pci/eso.c | 54 +- sys/dev/pci/esoreg.h | 2 +- sys/dev/pci/esovar.h | 2 +- sys/dev/pci/fms.c | 130 +- sys/dev/pci/fmsvar.h | 4 +- sys/dev/pci/gcu.c | 8 +- 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sys/dev/pci/if_txp.c | 4 +- sys/dev/pci/if_vic.c | 2 +- sys/dev/pci/if_vmxreg.h | 2 +- sys/dev/pci/if_vr.c | 2 +- sys/dev/pci/if_vrreg.h | 4 +- sys/dev/pci/if_vte.c | 26 +- sys/dev/pci/if_wb.c | 12 +- sys/dev/pci/if_wbreg.h | 2 +- sys/dev/pci/if_wi_pci.c | 6 +- sys/dev/pci/if_wpi.c | 2 +- sys/dev/pci/if_wpireg.h | 2 +- sys/dev/pci/if_xge.c | 2 +- sys/dev/pci/if_xgereg.h | 10 +- sys/dev/pci/if_xl_pci.c | 2 +- sys/dev/pci/igc_mac.c | 2 +- sys/dev/pci/igc_phy.c | 2 +- sys/dev/pci/igc_regs.h | 2 +- sys/dev/pci/ixgb_ee.c | 14 +- sys/dev/pci/ixgb_ee.h | 10 +- sys/dev/pci/ixgb_hw.c | 18 +- sys/dev/pci/ixgb_hw.h | 20 +- sys/dev/pci/ixgb_ids.h | 12 +- sys/dev/pci/ixgbe.c | 2 +- sys/dev/pci/ixgbe_type.h | 2 +- sys/dev/pci/kate.c | 4 +- sys/dev/pci/maestro.c | 64 +- sys/dev/pci/mbg.c | 2 +- sys/dev/pci/nviic.c | 2 +- sys/dev/pci/ohci_pci.c | 4 +- sys/dev/pci/pci.c | 14 +- sys/dev/pci/pci_map.c | 4 +- sys/dev/pci/pcidevs | 4 +- sys/dev/pci/pciide.c | 16 +- sys/dev/pci/pciidevar.h | 2 +- sys/dev/pci/pcscp.c | 18 +- sys/dev/pci/piixpm.c | 2 +- sys/dev/pci/ppb.c | 6 +- sys/dev/pci/ppbreg.h | 2 +- sys/dev/pci/qla_pci.c | 2 +- sys/dev/pci/qlereg.h | 4 +- sys/dev/pci/rtsx_pci.c | 2 +- sys/dev/pci/sv.c | 98 +- sys/dev/pci/tcpcib.c | 2 +- sys/dev/pci/tga.c | 110 +- sys/dev/pci/tgareg.h | 10 +- sys/dev/pci/tgavar.h | 12 +- sys/dev/pci/uhci_pci.c | 6 +- sys/dev/pci/vga_pci.c | 2 +- sys/dev/pci/vga_pcivar.h | 12 +- sys/dev/pci/yds.c | 24 +- sys/dev/pckbc/pckbd.c | 12 +- sys/dev/pcmcia/cfxga.c | 8 +- sys/dev/pcmcia/if_an_pcmcia.c | 2 +- sys/dev/pcmcia/if_malo.c | 6 +- sys/dev/pcmcia/if_malovar.h | 2 +- sys/dev/pcmcia/if_xe.c | 22 +- sys/dev/pcmcia/pcmcia_cis.c | 2 +- sys/dev/pcmcia/pcmcia_cis_quirks.c | 14 +- sys/dev/pcmcia/pcmciachip.h | 2 +- sys/dev/pcmcia/pcmciadevs | 6 +- sys/dev/pcmcia/wdc_pcmcia.c | 8 +- sys/dev/puc/lpt_puc.c | 2 +- sys/dev/sbus/agten.c | 2 +- sys/dev/sbus/bwtwo.c | 4 +- sys/dev/sbus/cgsix.c | 2 +- sys/dev/sbus/cgthree.c | 2 +- sys/dev/sbus/cgtwelve.c | 2 +- sys/dev/sbus/cgtwelvereg.h | 2 +- sys/dev/sbus/cs4231.c | 2 +- sys/dev/sbus/dma_sbus.c | 2 +- sys/dev/sbus/esp_sbus.c | 10 +- sys/dev/sbus/spif.c | 2 +- sys/dev/sbus/spifreg.h | 2 +- sys/dev/sbus/stp4020.c | 2 +- sys/dev/sbus/vigra.c | 2 +- sys/dev/sbus/xbox.c | 2 +- sys/dev/sbus/zx.c | 2 +- sys/dev/sbus/zxreg.h | 2 +- sys/dev/sdmmc/sdhc.c | 8 +- sys/dev/sdmmc/sdmmc_io.c | 6 +- sys/dev/sdmmc/sdmmcreg.h | 2 +- sys/dev/sun/sunkbdmap.c | 6 +- sys/dev/sun/z8530ms.c | 2 +- sys/dev/tc/asc_tc.c | 6 +- sys/dev/tc/if_le_ioasic.c | 6 +- sys/dev/tc/if_le_tc.c | 2 +- sys/dev/tc/ioasic_subr.c | 10 +- sys/dev/tc/ioasicreg.h | 12 +- sys/dev/tc/tcds.c | 14 +- sys/dev/tc/tcdsreg.h | 12 +- sys/dev/tc/tcdsvar.h | 10 +- sys/dev/tc/tcreg.h | 10 +- sys/dev/tc/tcvar.h | 12 +- sys/dev/usb/dwc2/dwc2.c | 2 +- sys/dev/usb/dwc2/dwc2_hcdqueue.c | 2 +- sys/dev/usb/if_mos.c | 8 +- sys/dev/usb/if_mosreg.h | 4 +- sys/dev/usb/if_mtw.c | 18 +- sys/dev/usb/if_mtwvar.h | 2 +- sys/dev/usb/if_mue.c | 30 +- sys/dev/usb/if_rsu.c | 4 +- sys/dev/usb/if_run.c | 12 +- sys/dev/usb/if_smsc.c | 46 +- sys/dev/usb/if_smscreg.h | 4 +- sys/dev/usb/if_uath.c | 2 +- sys/dev/usb/if_udav.c | 8 +- sys/dev/usb/if_udavreg.h | 2 +- sys/dev/usb/if_umb.c | 6 +- sys/dev/usb/if_upgt.c | 2 +- sys/dev/usb/if_urtw.c | 6 +- sys/dev/usb/if_wi_usb.c | 20 +- sys/dev/usb/if_wi_usb.h | 2 +- sys/dev/usb/if_zyd.c | 2 +- sys/dev/usb/moscom.c | 14 +- sys/dev/usb/ohci.c | 2 +- sys/dev/usb/uark.c | 4 +- sys/dev/usb/uaudio.c | 4 +- sys/dev/usb/uberry.c | 2 +- sys/dev/usb/ubsa.c | 4 +- sys/dev/usb/udcf.c | 6 +- sys/dev/usb/udl.c | 10 +- sys/dev/usb/udlio.h | 2 +- sys/dev/usb/udsbr.c | 26 +- sys/dev/usb/uftdi.c | 4 +- sys/dev/usb/ugen.c | 2 +- sys/dev/usb/uhci.c | 2 +- sys/dev/usb/uhid.c | 16 +- sys/dev/usb/uhid.h | 4 +- sys/dev/usb/uipaq.c | 2 +- sys/dev/usb/umass.c | 14 +- sys/dev/usb/umbg.c | 4 +- sys/dev/usb/umcs.h | 8 +- sys/dev/usb/umidi.c | 62 +- sys/dev/usb/umidivar.h | 2 +- sys/dev/usb/umsm.c | 2 +- sys/dev/usb/umstc.c | 2 +- sys/dev/usb/uoak.h | 2 +- sys/dev/usb/uoak_subr.c | 12 +- sys/dev/usb/uoaklux.c | 6 +- sys/dev/usb/uoakrh.c | 8 +- sys/dev/usb/uow.c | 26 +- sys/dev/usb/usb.h | 2 +- sys/dev/usb/usb_quirks.c | 4 +- sys/dev/usb/usb_subr.c | 6 +- sys/dev/usb/usbdevs | 20 +- sys/dev/usb/uscom.c | 2 +- sys/dev/usb/uslcom.c | 6 +- sys/dev/usb/usps.c | 16 +- sys/dev/usb/utvfu.c | 6 +- sys/dev/usb/utvfu.h | 2 +- sys/dev/usb/uvideo.c | 20 +- sys/dev/usb/uvisor.c | 14 +- sys/dev/usb/uxrcom.c | 2 +- sys/dev/videomode/devlist2h.awk | 2 +- sys/dev/videomode/edid.c | 22 +- sys/dev/videomode/ediddevs | 2 +- sys/dev/videomode/edidreg.h | 2 +- sys/dev/videomode/edidvar.h | 2 +- sys/dev/videomode/modelines | 2 +- sys/dev/videomode/modelines2c.awk | 4 +- sys/dev/videomode/vesagtf.c | 122 +- sys/dev/videomode/vesagtf.h | 2 +- sys/dev/x86emu/x86emu_regs.h | 4 +- sys/kern/init_main.c | 2 +- sys/netinet/ip_ipsp.h | 2 +- sys/ntfs/ntfs_subr.c | 4 +- usr.bin/rdist/client.c | 2 +- usr.sbin/amd/amd/wire.c | 2 +- usr.sbin/amd/amq/amq.c | 2 +- usr.sbin/apmd/apm-proto.h | 6 +- usr.sbin/apmd/apmsubr.c | 6 +- usr.sbin/apmd/pathnames.h | 6 +- usr.sbin/btrace/btrace.8 | 2 +- usr.sbin/config/sem.c | 2 +- usr.sbin/crunchgen/crunchgen.c | 54 +- usr.sbin/crunchgen/crunchide.c | 10 +- usr.sbin/crunchgen/mangle.c | 6 +- usr.sbin/eigrpd/eigrpd.c | 2 +- usr.sbin/eigrpd/packet.c | 2 +- usr.sbin/fdformat/fdformat.c | 4 +- usr.sbin/ftp-proxy/ftp-proxy.c | 10 +- usr.sbin/iscsictl/iscsictl.c | 6 +- usr.sbin/iscsid/initiator.c | 4 +- usr.sbin/iscsid/pdu.c | 4 +- usr.sbin/lpd/lp.c | 2 +- usr.sbin/lpd/lp_stty.c | 2 +- usr.sbin/lpr/SMM.doc/2.t | 8 +- usr.sbin/lpr/SMM.doc/4.t | 4 +- usr.sbin/lpr/SMM.doc/5.t | 2 +- usr.sbin/lpr/SMM.doc/7.t | 24 +- usr.sbin/lpr/common_source/common.c | 2 +- usr.sbin/lpr/filters/lpf.c | 4 +- usr.sbin/lpr/lpc/cmds.c | 8 +- usr.sbin/lpr/lpd/extern.h | 6 +- usr.sbin/lpr/lpd/printjob.c | 2 +- usr.sbin/lpr/lpd/recvjob.c | 2 +- usr.sbin/lpr/lpr/lpr.c | 6 +- usr.sbin/map-mbone/mapper.c | 26 +- usr.sbin/memconfig/memconfig.c | 2 +- usr.sbin/mkuboot/copy_elf.c | 2 +- usr.sbin/mkuboot/mkuboot.c | 2 +- usr.sbin/mopd/mopchk/Makefile | 2 +- usr.sbin/mopd/mopchk/mopchk.c | 8 +- usr.sbin/mopd/mopd/mopd.c | 4 +- usr.sbin/mopd/mopd/process.c | 4 +- usr.sbin/mopd/mopprobe/Makefile | 2 +- usr.sbin/mopd/mopprobe/mopprobe.c | 20 +- usr.sbin/mopd/moptrace/moptrace.c | 8 +- usr.sbin/mopd/otherOS/Makefile | 6 +- usr.sbin/mopd/otherOS/loop-linux2.c | 12 +- usr.sbin/mopd/otherOS/loop.c | 2 +- usr.sbin/mopd/otherOS/mdtype | 14 +- usr.sbin/mopd/otherOS/ostype | 4 +- usr.sbin/mopd/otherOS/pf-snit.c | 52 +- usr.sbin/mrinfo/mrinfo.c | 2 +- usr.sbin/netgroup_mkdb/netgroup_mkdb.c | 2 +- usr.sbin/npppd/l2tp/l2tp_ctrl.c | 2 +- usr.sbin/npppd/l2tp/l2tp_local.h | 2 +- usr.sbin/npppd/l2tp/l2tpd.c | 2 +- usr.sbin/npppd/npppd/chap.c | 4 +- usr.sbin/npppd/npppd/fsm.h | 2 +- usr.sbin/npppd/npppd/lcp.c | 4 +- usr.sbin/npppd/npppd/npppd.c | 2 +- usr.sbin/npppd/npppd/npppd_auth.c | 4 +- usr.sbin/npppd/npppd/npppd_ctl.h | 2 +- usr.sbin/npppd/npppd/npppd_radius.c | 8 +- usr.sbin/npppd/npppd/pap.c | 2 +- usr.sbin/npppd/npppd/radius_req.c | 2 +- usr.sbin/nsd/Makefile.in | 4 +- usr.sbin/nsd/acx_nlnetlabs.m4 | 40 +- usr.sbin/nsd/buffer.c | 12 +- usr.sbin/nsd/buffer.h | 2 +- usr.sbin/nsd/configlexer.lex | 2 +- usr.sbin/nsd/configparser.y | 2 +- usr.sbin/nsd/configure.ac | 2 +- usr.sbin/nsd/dbaccess.c | 2 +- usr.sbin/nsd/difffile.c | 8 +- usr.sbin/nsd/dns.c | 2 +- usr.sbin/nsd/dnstap/dnstap.c | 2 +- usr.sbin/nsd/dnstap/dnstap_collector.c | 6 +- usr.sbin/nsd/edns.c | 6 +- usr.sbin/nsd/install-sh | 14 +- usr.sbin/nsd/ipc.h | 4 +- usr.sbin/nsd/ixfrcreate.c | 4 +- usr.sbin/nsd/lookup3.c | 42 +- usr.sbin/nsd/lookup3.h | 10 +- usr.sbin/nsd/mini_event.c | 32 +- usr.sbin/nsd/mini_event.h | 24 +- usr.sbin/nsd/namedb.c | 2 +- usr.sbin/nsd/namedb.h | 2 +- usr.sbin/nsd/netio.c | 2 +- usr.sbin/nsd/nsd-checkconf.8.in | 26 +- usr.sbin/nsd/nsd-control.8.in | 14 +- usr.sbin/nsd/nsd-control.c | 12 +- usr.sbin/nsd/nsd.8.in | 92 +- usr.sbin/nsd/nsd.conf.5.in | 262 +- usr.sbin/nsd/nsd.conf.sample.in | 12 +- usr.sbin/nsd/nsec3.c | 2 +- usr.sbin/nsd/options.c | 8 +- usr.sbin/nsd/options.h | 2 +- usr.sbin/nsd/query.c | 4 +- usr.sbin/nsd/radtree.c | 20 +- usr.sbin/nsd/radtree.h | 2 +- usr.sbin/nsd/rdata.c | 6 +- usr.sbin/nsd/region-allocator.h | 6 +- usr.sbin/nsd/remote.c | 40 +- usr.sbin/nsd/remote.h | 12 +- usr.sbin/nsd/server.c | 10 +- usr.sbin/nsd/udb.c | 4 +- usr.sbin/nsd/udb.h | 28 +- usr.sbin/nsd/udbradtree.c | 12 +- usr.sbin/nsd/udbzone.c | 4 +- usr.sbin/nsd/xfrd-disk.c | 4 +- usr.sbin/nsd/xfrd-notify.c | 2 +- usr.sbin/nsd/xfrd-notify.h | 2 +- usr.sbin/nsd/xfrd-tcp.c | 10 +- usr.sbin/nsd/xfrd.c | 10 +- usr.sbin/nsd/xfrd.h | 2 +- usr.sbin/nsd/zlexer.lex | 26 +- usr.sbin/nsd/zonec.c | 20 +- usr.sbin/nsd/zparser.y | 18 +- usr.sbin/ntpd/client.c | 2 +- usr.sbin/ntpd/config.c | 2 +- usr.sbin/ntpd/constraint.c | 2 +- usr.sbin/ntpd/ntp_dns.c | 6 +- usr.sbin/ntpd/sensors.c | 2 +- usr.sbin/ntpd/util.c | 2 +- usr.sbin/ospf6d/rde.c | 2 +- usr.sbin/pppd/cbcp.c | 12 +- usr.sbin/pppd/chap.c | 2 +- usr.sbin/pppd/chat/chat.c | 62 +- usr.sbin/pppd/fsm.c | 12 +- usr.sbin/pppd/ipcp.c | 2 +- usr.sbin/pppd/ipcp.h | 2 +- usr.sbin/pppd/options.c | 16 +- usr.sbin/pppd/pppstats/pppstats.c | 4 +- usr.sbin/pppd/sys-bsd.c | 10 +- usr.sbin/pppd/upap.c | 2 +- usr.sbin/pstat/pstat.c | 2 +- usr.sbin/radiusctl/radiusctl.c | 2 +- usr.sbin/rbootd/utils.c | 2 +- usr.sbin/rcctl/rcctl.sh | 2 +- usr.sbin/repquota/repquota.c | 8 +- usr.sbin/ripd/ripd.c | 4 +- usr.sbin/ripd/ripe.c | 4 +- usr.sbin/route6d/route6d.c | 38 +- usr.sbin/route6d/route6d.h | 4 +- usr.sbin/rpc.lockd/lockd_lock.c | 14 +- usr.sbin/rpc.lockd/procs.c | 4 +- usr.sbin/rpc.lockd/test.c | 2 +- usr.sbin/sasyncd/monitor.c | 2 +- usr.sbin/slowcgi/slowcgi.c | 2 +- usr.sbin/unbound/doc/Changelog | 246 +- usr.sbin/unbound/util/data/msgparse.h | 2 +- usr.sbin/unbound/validator/validator.c | 2 +- 681 files changed, 35748 insertions(+), 35743 deletions(-) diff --git a/lib/libcrypto/aes/asm/aes-mips.pl b/lib/libcrypto/aes/asm/aes-mips.pl index b95d1afd5..598811c64 100644 --- a/lib/libcrypto/aes/asm/aes-mips.pl +++ b/lib/libcrypto/aes/asm/aes-mips.pl @@ -96,7 +96,7 @@ $code.=<<___; #endif .set noat ___ - + {{{ my $FRAMESIZE=16*$SZREG; my $SAVED_REGS_MASK = ($flavour =~ /nubi/i) ? 0xc0fff008 : 0xc0ff0000; @@ -437,7 +437,7 @@ $code.=<<___; $PTR_ADD $sp,$FRAMESIZE .end AES_encrypt ___ - + $code.=<<___; .align 5 .ent _mips_AES_decrypt @@ -774,7 +774,7 @@ $code.=<<___; .end AES_decrypt ___ }}} - + {{{ my $FRAMESIZE=8*$SZREG; my $SAVED_REGS_MASK = ($flavour =~ /nubi/i) ? 0xc000f008 : 0xc0000000; @@ -1087,7 +1087,7 @@ $code.=<<___; $PTR_ADD $sp,$FRAMESIZE .end AES_set_encrypt_key ___ - + my ($head,$tail)=($inp,$bits); my ($tp1,$tp2,$tp4,$tp8,$tp9,$tpb,$tpd,$tpe)=($a4,$a5,$a6,$a7,$s0,$s1,$s2,$s3); my ($m,$x80808080,$x7f7f7f7f,$x1b1b1b1b)=($at,$t0,$t1,$t2); @@ -1570,7 +1570,7 @@ AES_Td: .byte 0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, 0x26 .byte 0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d ___ - + foreach (split("\n",$code)) { s/\`([^\`]*)\`/eval $1/ge; diff --git a/lib/libcrypto/aes/asm/aesni-x86.pl b/lib/libcrypto/aes/asm/aesni-x86.pl index 0a65d023c..011993830 100644 --- a/lib/libcrypto/aes/asm/aesni-x86.pl +++ b/lib/libcrypto/aes/asm/aesni-x86.pl @@ -90,7 +90,7 @@ sub aesenc { aescommon(0xdc,@_); } sub aesenclast { aescommon(0xdd,@_); } sub aesdec { aescommon(0xde,@_); } sub aesdeclast { aescommon(0xdf,@_); } - + # Inline version of internal aesni_[en|de]crypt1 { my $sn; sub aesni_inline_generate1 @@ -157,7 +157,7 @@ sub aesni_generate1 # fully unrolled loop &ret(); &function_end_B("_aesni_${p}rypt1"); } - + # void $PREFIX_encrypt (const void *inp,void *out,const AES_KEY *key); &aesni_generate1("enc") if (!$inline); &function_begin_B("${PREFIX}_encrypt"); @@ -349,7 +349,7 @@ sub aesni_generate6 &aesni_generate4("dec"); &aesni_generate6("enc") if ($PREFIX eq "aesni"); &aesni_generate6("dec"); - + if ($PREFIX eq "aesni") { ###################################################################### # void aesni_ecb_encrypt (const void *in, void *out, @@ -569,7 +569,7 @@ if ($PREFIX eq "aesni") { &set_label("ecb_ret"); &function_end("aesni_ecb_encrypt"); - + ###################################################################### # void aesni_ccm64_[en|de]crypt_blocks (const void *in, void *out, # size_t blocks, const AES_KEY *key, @@ -756,7 +756,7 @@ if ($PREFIX eq "aesni") { &movups (&QWP(0,$out),$cmac); &function_end("aesni_ccm64_decrypt_blocks"); } - + ###################################################################### # void aesni_ctr32_encrypt_blocks (const void *in, void *out, # size_t blocks, const AES_KEY *key, @@ -1010,7 +1010,7 @@ if ($PREFIX eq "aesni") { &set_label("ctr32_ret"); &mov ("esp",&DWP(80,"esp")); &function_end("aesni_ctr32_encrypt_blocks"); - + ###################################################################### # void aesni_xts_[en|de]crypt(const char *inp,char *out,size_t len, # const AES_KEY *key1, const AES_KEY *key2 @@ -1716,7 +1716,7 @@ if ($PREFIX eq "aesni") { &function_end("aesni_xts_decrypt"); } } - + ###################################################################### # void $PREFIX_cbc_encrypt (const void *inp, void *out, # size_t length, const AES_KEY *key, @@ -1943,7 +1943,7 @@ if ($PREFIX eq "aesni") { &movups (&QWP(0,$key_),$ivec); # output IV &set_label("cbc_abort"); &function_end("${PREFIX}_cbc_encrypt"); - + ###################################################################### # Mechanical port from aesni-x86_64.pl. # diff --git a/lib/libcrypto/aes/asm/bsaes-x86_64.pl b/lib/libcrypto/aes/asm/bsaes-x86_64.pl index 7098ba27f..f7cf13810 100644 --- a/lib/libcrypto/aes/asm/bsaes-x86_64.pl +++ b/lib/libcrypto/aes/asm/bsaes-x86_64.pl @@ -128,7 +128,7 @@ my @s=@_[12..15]; sub InBasisChange { # input in lsb > [b0, b1, b2, b3, b4, b5, b6, b7] < msb -# output in lsb > [b6, b5, b0, b3, b7, b1, b4, b2] < msb +# output in lsb > [b6, b5, b0, b3, b7, b1, b4, b2] < msb my @b=@_[0..7]; $code.=<<___; pxor @b[6], @b[5] @@ -378,7 +378,7 @@ $code.=<<___; pxor @s[0], @t[3] pxor @s[1], @t[2] pxor @s[2], @t[1] - pxor @s[3], @t[0] + pxor @s[3], @t[0] #Inv_GF16 \t0, \t1, \t2, \t3, \s0, \s1, \s2, \s3 diff --git a/lib/libcrypto/aes/asm/vpaes-x86.pl b/lib/libcrypto/aes/asm/vpaes-x86.pl index 6e7bd36d0..c42f4e2b6 100644 --- a/lib/libcrypto/aes/asm/vpaes-x86.pl +++ b/lib/libcrypto/aes/asm/vpaes-x86.pl @@ -432,7 +432,7 @@ $k_dsbo=0x2c0; # decryption sbox final output ## &set_label("schedule_192",16); &movdqu ("xmm0",&QWP(8,$inp)); # load key part 2 (very unaligned) - &call ("_vpaes_schedule_transform"); # input transform + &call ("_vpaes_schedule_transform"); # input transform &movdqa ("xmm6","xmm0"); # save short part &pxor ("xmm4","xmm4"); # clear 4 &movhlps("xmm6","xmm4"); # clobber low side with zeros @@ -463,7 +463,7 @@ $k_dsbo=0x2c0; # decryption sbox final output ## &set_label("schedule_256",16); &movdqu ("xmm0",&QWP(16,$inp)); # load key part 2 (unaligned) - &call ("_vpaes_schedule_transform"); # input transform + &call ("_vpaes_schedule_transform"); # input transform &mov ($round,7); &set_label("loop_schedule_256"); @@ -474,7 +474,7 @@ $k_dsbo=0x2c0; # decryption sbox final output &call ("_vpaes_schedule_round"); &dec ($round); &jz (&label("schedule_mangle_last")); - &call ("_vpaes_schedule_mangle"); + &call ("_vpaes_schedule_mangle"); # low round. swap xmm7 and xmm6 &pshufd ("xmm0","xmm0",0xFF); @@ -597,7 +597,7 @@ $k_dsbo=0x2c0; # decryption sbox final output # subbyte &movdqa ("xmm4",&QWP($k_s0F,$const)); &movdqa ("xmm5",&QWP($k_inv,$const)); # 4 : 1/j - &movdqa ("xmm1","xmm4"); + &movdqa ("xmm1","xmm4"); &pandn ("xmm1","xmm0"); &psrld ("xmm1",4); # 1 = i &pand ("xmm0","xmm4"); # 0 = k diff --git a/lib/libcrypto/aes/asm/vpaes-x86_64.pl b/lib/libcrypto/aes/asm/vpaes-x86_64.pl index 8ff8d8602..f15580c0e 100644 --- a/lib/libcrypto/aes/asm/vpaes-x86_64.pl +++ b/lib/libcrypto/aes/asm/vpaes-x86_64.pl @@ -164,7 +164,7 @@ _vpaes_encrypt_core: pshufb %xmm1, %xmm0 ret .size _vpaes_encrypt_core,.-_vpaes_encrypt_core - + ## ## Decryption core ## @@ -218,7 +218,7 @@ _vpaes_decrypt_core: pshufb %xmm3, %xmm0 # 0 = sbdt pxor %xmm4, %xmm0 # 0 = ch sub \$1,%rax # nr-- - + pshufb %xmm5, %xmm0 # MC ch movdqa 0x20(%r10),%xmm4 # 4 : sbbu pshufb %xmm2, %xmm4 # 4 = sbbu @@ -226,7 +226,7 @@ _vpaes_decrypt_core: movdqa 0x30(%r10),%xmm0 # 0 : sbbt pshufb %xmm3, %xmm0 # 0 = sbbt pxor %xmm4, %xmm0 # 0 = ch - + pshufb %xmm5, %xmm0 # MC ch movdqa 0x40(%r10),%xmm4 # 4 : sbeu pshufb %xmm2, %xmm4 # 4 = sbeu @@ -236,7 +236,7 @@ _vpaes_decrypt_core: pxor %xmm4, %xmm0 # 0 = ch palignr \$12, %xmm5, %xmm5 - + .Ldec_entry: # top of round movdqa %xmm9, %xmm1 # 1 : i @@ -328,7 +328,7 @@ _vpaes_schedule_core: ## .Lschedule_128: mov \$10, %esi - + .Loop_schedule_128: call _vpaes_schedule_round dec %rsi @@ -362,7 +362,7 @@ _vpaes_schedule_core: .Loop_schedule_192: call _vpaes_schedule_round - palignr \$8,%xmm6,%xmm0 + palignr \$8,%xmm6,%xmm0 call _vpaes_schedule_mangle # save key n call _vpaes_schedule_192_smear call _vpaes_schedule_mangle # save key n+1 @@ -388,7 +388,7 @@ _vpaes_schedule_core: movdqu 16(%rdi),%xmm0 # load key part 2 (unaligned) call _vpaes_schedule_transform # input transform mov \$7, %esi - + .Loop_schedule_256: call _vpaes_schedule_mangle # output low result movdqa %xmm0, %xmm6 # save cur_lo in xmm6 @@ -397,7 +397,7 @@ _vpaes_schedule_core: call _vpaes_schedule_round dec %rsi jz .Lschedule_mangle_last - call _vpaes_schedule_mangle + call _vpaes_schedule_mangle # low round. swap xmm7 and xmm6 pshufd \$0xFF, %xmm0, %xmm0 @@ -405,10 +405,10 @@ _vpaes_schedule_core: movdqa %xmm6, %xmm7 call _vpaes_schedule_low_round movdqa %xmm5, %xmm7 - + jmp .Loop_schedule_256 - + ## ## .aes_schedule_mangle_last ## @@ -509,9 +509,9 @@ _vpaes_schedule_round: # rotate pshufd \$0xFF, %xmm0, %xmm0 palignr \$1, %xmm0, %xmm0 - + # fall through... - + # low round: same as high round, but no rotation and no rcon. _vpaes_schedule_low_round: # smear xmm7 @@ -550,7 +550,7 @@ _vpaes_schedule_low_round: pxor %xmm4, %xmm0 # 0 = sbox output # add in smeared stuff - pxor %xmm7, %xmm0 + pxor %xmm7, %xmm0 movdqa %xmm0, %xmm7 ret .size _vpaes_schedule_round,.-_vpaes_schedule_round diff --git a/lib/libcrypto/arc4random/getentropy_hpux.c b/lib/libcrypto/arc4random/getentropy_hpux.c index 7188ae5e1..5fdcf7637 100644 --- a/lib/libcrypto/arc4random/getentropy_hpux.c +++ b/lib/libcrypto/arc4random/getentropy_hpux.c @@ -102,7 +102,7 @@ getentropy(void *buf, size_t len) * should raise(SIGKILL) * - Do the best under the circumstances.... * - * This code path exists to bring light to the issue that hpux + * This code path exists to bring light to the issue that hpux * does not provide a failsafe API for entropy collection. * * We hope this demonstrates that hpux should consider diff --git a/lib/libcrypto/arc4random/getentropy_win.c b/lib/libcrypto/arc4random/getentropy_win.c index 64514b3a3..5521e418d 100644 --- a/lib/libcrypto/arc4random/getentropy_win.c +++ b/lib/libcrypto/arc4random/getentropy_win.c @@ -1,7 +1,7 @@ /* $OpenBSD: getentropy_win.c,v 1.6 2020/11/11 10:41:24 bcook Exp $ */ /* - * Copyright (c) 2014, Theo de Raadt + * Copyright (c) 2014, Theo de Raadt * Copyright (c) 2014, Bob Beck * * Permission to use, copy, modify, and distribute this software for any diff --git a/lib/libcrypto/arch/alpha/Makefile.inc b/lib/libcrypto/arch/alpha/Makefile.inc index 4cdcf64e0..5e50a5233 100644 --- a/lib/libcrypto/arch/alpha/Makefile.inc +++ b/lib/libcrypto/arch/alpha/Makefile.inc @@ -3,7 +3,7 @@ # alpha-specific libcrypto build rules # aes -SRCS+= aes_core.c aes_cbc.c +SRCS+= aes_core.c aes_cbc.c # bf SRCS+= bf_enc.c # bn diff --git a/lib/libcrypto/arch/alpha/opensslconf.h b/lib/libcrypto/arch/alpha/opensslconf.h index 47f2aa8f2..b9ca2ddf8 100644 --- a/lib/libcrypto/arch/alpha/opensslconf.h +++ b/lib/libcrypto/arch/alpha/opensslconf.h @@ -117,7 +117,7 @@ YOU SHOULD NOT HAVE BOTH DES_RISC1 AND DES_RISC2 DEFINED!!!!! even newer MIPS CPU's, but at the moment one size fits all for optimization options. Older Sparc's work better with only UNROLL, but there's no way to tell at compile time what it is you're running on */ - + #if defined( sun ) /* Newer Sparc's */ # define DES_PTR # define DES_RISC1 diff --git a/lib/libcrypto/arch/hppa/Makefile.inc b/lib/libcrypto/arch/hppa/Makefile.inc index c11b89944..8449bf569 100644 --- a/lib/libcrypto/arch/hppa/Makefile.inc +++ b/lib/libcrypto/arch/hppa/Makefile.inc @@ -3,7 +3,7 @@ # hppa-specific libcrypto build rules # aes -SRCS+= aes_core.c aes_cbc.c +SRCS+= aes_core.c aes_cbc.c CFLAGS+= -DAES_ASM SSLASM+= aes aes-parisc aes-parisc # bf diff --git a/lib/libcrypto/arch/hppa/opensslconf.h b/lib/libcrypto/arch/hppa/opensslconf.h index f17d3d280..e9b744c0a 100644 --- a/lib/libcrypto/arch/hppa/opensslconf.h +++ b/lib/libcrypto/arch/hppa/opensslconf.h @@ -119,7 +119,7 @@ YOU SHOULD NOT HAVE BOTH DES_RISC1 AND DES_RISC2 DEFINED!!!!! even newer MIPS CPU's, but at the moment one size fits all for optimization options. Older Sparc's work better with only UNROLL, but there's no way to tell at compile time what it is you're running on */ - + #if defined( sun ) /* Newer Sparc's */ # define DES_PTR # define DES_RISC1 diff --git a/lib/libcrypto/arch/m88k/opensslconf.h b/lib/libcrypto/arch/m88k/opensslconf.h index f17d3d280..e9b744c0a 100644 --- a/lib/libcrypto/arch/m88k/opensslconf.h +++ b/lib/libcrypto/arch/m88k/opensslconf.h @@ -119,7 +119,7 @@ YOU SHOULD NOT HAVE BOTH DES_RISC1 AND DES_RISC2 DEFINED!!!!! even newer MIPS CPU's, but at the moment one size fits all for optimization options. Older Sparc's work better with only UNROLL, but there's no way to tell at compile time what it is you're running on */ - + #if defined( sun ) /* Newer Sparc's */ # define DES_PTR # define DES_RISC1 diff --git a/lib/libcrypto/arch/mips64/Makefile.inc b/lib/libcrypto/arch/mips64/Makefile.inc index 2d547f4a5..da9e7f479 100644 --- a/lib/libcrypto/arch/mips64/Makefile.inc +++ b/lib/libcrypto/arch/mips64/Makefile.inc @@ -3,7 +3,7 @@ # mips64-specific libcrypto build rules # aes -SRCS+= aes_cbc.c +SRCS+= aes_cbc.c CFLAGS+= -DAES_ASM SSLASM+= aes aes-mips aes-mips # bf diff --git a/lib/libcrypto/arch/mips64/opensslconf.h b/lib/libcrypto/arch/mips64/opensslconf.h index ed1204c8c..bcd2ecf38 100644 --- a/lib/libcrypto/arch/mips64/opensslconf.h +++ b/lib/libcrypto/arch/mips64/opensslconf.h @@ -119,7 +119,7 @@ YOU SHOULD NOT HAVE BOTH DES_RISC1 AND DES_RISC2 DEFINED!!!!! even newer MIPS CPU's, but at the moment one size fits all for optimization options. Older Sparc's work better with only UNROLL, but there's no way to tell at compile time what it is you're running on */ - + #if defined( sun ) /* Newer Sparc's */ # define DES_PTR # define DES_RISC1 diff --git a/lib/libcrypto/arch/powerpc/Makefile.inc b/lib/libcrypto/arch/powerpc/Makefile.inc index 6c168c798..3457e04c9 100644 --- a/lib/libcrypto/arch/powerpc/Makefile.inc +++ b/lib/libcrypto/arch/powerpc/Makefile.inc @@ -3,7 +3,7 @@ # powerpc-specific libcrypto build rules # aes -SRCS+= aes_core.c aes_cbc.c +SRCS+= aes_core.c aes_cbc.c # slower than C code #CFLAGS+= -DAES_ASM #SSLASM+= aes aes-ppc aes-ppc diff --git a/lib/libcrypto/arch/powerpc/opensslconf.h b/lib/libcrypto/arch/powerpc/opensslconf.h index f17d3d280..e9b744c0a 100644 --- a/lib/libcrypto/arch/powerpc/opensslconf.h +++ b/lib/libcrypto/arch/powerpc/opensslconf.h @@ -119,7 +119,7 @@ YOU SHOULD NOT HAVE BOTH DES_RISC1 AND DES_RISC2 DEFINED!!!!! even newer MIPS CPU's, but at the moment one size fits all for optimization options. Older Sparc's work better with only UNROLL, but there's no way to tell at compile time what it is you're running on */ - + #if defined( sun ) /* Newer Sparc's */ # define DES_PTR # define DES_RISC1 diff --git a/lib/libcrypto/arch/powerpc64/Makefile.inc b/lib/libcrypto/arch/powerpc64/Makefile.inc index fe19069ee..7494e6905 100644 --- a/lib/libcrypto/arch/powerpc64/Makefile.inc +++ b/lib/libcrypto/arch/powerpc64/Makefile.inc @@ -3,7 +3,7 @@ # powerpc-specific libcrypto build rules # aes -SRCS+= aes_core.c aes_cbc.c +SRCS+= aes_core.c aes_cbc.c # slower than C code #CFLAGS+= -DAES_ASM #SSLASM+= aes aes-ppc aes-ppc diff --git a/lib/libcrypto/arch/powerpc64/opensslconf.h b/lib/libcrypto/arch/powerpc64/opensslconf.h index 5cad089a8..4ea0426df 100644 --- a/lib/libcrypto/arch/powerpc64/opensslconf.h +++ b/lib/libcrypto/arch/powerpc64/opensslconf.h @@ -114,7 +114,7 @@ YOU SHOULD NOT HAVE BOTH DES_RISC1 AND DES_RISC2 DEFINED!!!!! even newer MIPS CPU's, but at the moment one size fits all for optimization options. Older Sparc's work better with only UNROLL, but there's no way to tell at compile time what it is you're running on */ - + #if defined( sun ) /* Newer Sparc's */ # define DES_PTR # define DES_RISC1 diff --git a/lib/libcrypto/arch/riscv64/opensslconf.h b/lib/libcrypto/arch/riscv64/opensslconf.h index 748ed8f8b..204eb505a 100644 --- a/lib/libcrypto/arch/riscv64/opensslconf.h +++ b/lib/libcrypto/arch/riscv64/opensslconf.h @@ -119,7 +119,7 @@ YOU SHOULD NOT HAVE BOTH DES_RISC1 AND DES_RISC2 DEFINED!!!!! even newer MIPS CPU's, but at the moment one size fits all for optimization options. Older Sparc's work better with only UNROLL, but there's no way to tell at compile time what it is you're running on */ - + #if defined( sun ) /* Newer Sparc's */ # define DES_PTR # define DES_RISC1 diff --git a/lib/libcrypto/arch/sh/opensslconf.h b/lib/libcrypto/arch/sh/opensslconf.h index f17d3d280..e9b744c0a 100644 --- a/lib/libcrypto/arch/sh/opensslconf.h +++ b/lib/libcrypto/arch/sh/opensslconf.h @@ -119,7 +119,7 @@ YOU SHOULD NOT HAVE BOTH DES_RISC1 AND DES_RISC2 DEFINED!!!!! even newer MIPS CPU's, but at the moment one size fits all for optimization options. Older Sparc's work better with only UNROLL, but there's no way to tell at compile time what it is you're running on */ - + #if defined( sun ) /* Newer Sparc's */ # define DES_PTR # define DES_RISC1 diff --git a/lib/libcrypto/arch/sparc64/Makefile.inc b/lib/libcrypto/arch/sparc64/Makefile.inc index 1b149ffb4..17bbd02ce 100644 --- a/lib/libcrypto/arch/sparc64/Makefile.inc +++ b/lib/libcrypto/arch/sparc64/Makefile.inc @@ -3,7 +3,7 @@ # sparc64-specific libcrypto build rules # aes -SRCS+= aes_core.c aes_cbc.c +SRCS+= aes_core.c aes_cbc.c CFLAGS+= -DAES_ASM SSLASM+= aes aes-sparcv9 aes-sparcv9 # bf diff --git a/lib/libcrypto/arch/sparc64/opensslconf.h b/lib/libcrypto/arch/sparc64/opensslconf.h index ed1204c8c..bcd2ecf38 100644 --- a/lib/libcrypto/arch/sparc64/opensslconf.h +++ b/lib/libcrypto/arch/sparc64/opensslconf.h @@ -119,7 +119,7 @@ YOU SHOULD NOT HAVE BOTH DES_RISC1 AND DES_RISC2 DEFINED!!!!! even newer MIPS CPU's, but at the moment one size fits all for optimization options. Older Sparc's work better with only UNROLL, but there's no way to tell at compile time what it is you're running on */ - + #if defined( sun ) /* Newer Sparc's */ # define DES_PTR # define DES_RISC1 diff --git a/lib/libcrypto/bn/arch/riscv64/bn_arch.h b/lib/libcrypto/bn/arch/riscv64/bn_arch.h index e67de835c..1cece3a24 100644 --- a/lib/libcrypto/bn/arch/riscv64/bn_arch.h +++ b/lib/libcrypto/bn/arch/riscv64/bn_arch.h @@ -42,7 +42,7 @@ bn_addw(BN_ULONG a, BN_ULONG b, BN_ULONG *out_r1, BN_ULONG *out_r0) } #define HAVE_BN_MULW - + static inline void bn_mulw(BN_ULONG a, BN_ULONG b, BN_ULONG *out_r1, BN_ULONG *out_r0) { diff --git a/lib/libcrypto/bn/asm/alpha-mont.pl b/lib/libcrypto/bn/asm/alpha-mont.pl index 874597f1c..e021069b1 100644 --- a/lib/libcrypto/bn/asm/alpha-mont.pl +++ b/lib/libcrypto/bn/asm/alpha-mont.pl @@ -256,7 +256,7 @@ bn_mul_mont: cmplt $i,$num,$tj # borrow $tj stq $hi1,16($tp) bne $tj,.Louter - + s8addq $num,sp,$tj # &tp[num] mov $rp,$bp # put rp aside mov sp,$tp diff --git a/lib/libcrypto/bn/asm/armv4-mont.pl b/lib/libcrypto/bn/asm/armv4-mont.pl index f78a8b5f0..fd7121341 100644 --- a/lib/libcrypto/bn/asm/armv4-mont.pl +++ b/lib/libcrypto/bn/asm/armv4-mont.pl @@ -16,7 +16,7 @@ # [depending on key length, less for longer keys] on ARM920T, and # +115-80% on Intel IXP425. This is compared to pre-bn_mul_mont code # base and compiler generated code with in-lined umull and even umlal -# instructions. The latter means that this code didn't really have an +# instructions. The latter means that this code didn't really have an # "advantage" of utilizing some "secret" instruction. # # The code is interoperable with Thumb ISA and is rather compact, less @@ -110,7 +110,7 @@ bn_mul_mont: adc $nhi,$nhi,#0 str $nlo,[$num] @ tp[num-1]= str $nhi,[$num,#4] @ tp[num]= - + .Louter: sub $tj,$num,sp @ "original" $num-1 value sub $ap,$ap,$tj @ "rewind" ap to &ap[1] @@ -158,7 +158,7 @@ bn_mul_mont: cmp $tp,$tj bne .Louter - + ldr $rp,[$_rp] @ pull rp add $num,$num,#4 @ $num to point at &tp[num] sub $aj,$num,sp @ "original" num value diff --git a/lib/libcrypto/bn/asm/bn-586.pl b/lib/libcrypto/bn/asm/bn-586.pl index 71b775af8..90d64d69a 100644 --- a/lib/libcrypto/bn/asm/bn-586.pl +++ b/lib/libcrypto/bn/asm/bn-586.pl @@ -42,7 +42,7 @@ sub bn_mul_add_words &movd("mm0",&wparam(3)); # mm0 = w &pxor("mm1","mm1"); # mm1 = carry_in &jmp(&label("maw_sse2_entry")); - + &set_label("maw_sse2_unrolled",16); &movd("mm3",&DWP(0,$r,"",0)); # mm3 = r[0] &paddq("mm1","mm3"); # mm1 = carry_in + r[0] diff --git a/lib/libcrypto/bn/asm/co-586.pl b/lib/libcrypto/bn/asm/co-586.pl index 37d79cc0c..8fd31ad04 100644 --- a/lib/libcrypto/bn/asm/co-586.pl +++ b/lib/libcrypto/bn/asm/co-586.pl @@ -36,7 +36,7 @@ sub mul_add_c &mov("edx",&DWP(($nb)*4,$b,"",0)) if $pos == 1; # load next b ### &adc($c2,0); - # is pos > 1, it means it is the last loop + # is pos > 1, it means it is the last loop &mov(&DWP($i*4,"eax","",0),$c0) if $pos > 0; # save r[]; &mov("eax",&DWP(($na)*4,$a,"",0)) if $pos == 1; # load next a } @@ -65,7 +65,7 @@ sub sqr_add_c &mov("edx",&DWP(($nb)*4,$a,"",0)) if ($pos == 1) && ($na != $nb); ### &adc($c2,0); - # is pos > 1, it means it is the last loop + # is pos > 1, it means it is the last loop &mov(&DWP($i*4,$r,"",0),$c0) if $pos > 0; # save r[]; &mov("eax",&DWP(($na)*4,$a,"",0)) if $pos == 1; # load next b } @@ -116,7 +116,7 @@ sub bn_mul_comba $c2="ebp"; $a="esi"; $b="edi"; - + $as=0; $ae=0; $bs=0; @@ -131,9 +131,9 @@ sub bn_mul_comba &push("ebx"); &xor($c0,$c0); - &mov("eax",&DWP(0,$a,"",0)); # load the first word + &mov("eax",&DWP(0,$a,"",0)); # load the first word &xor($c1,$c1); - &mov("edx",&DWP(0,$b,"",0)); # load the first second + &mov("edx",&DWP(0,$b,"",0)); # load the first second for ($i=0; $i<$tot; $i++) { @@ -141,7 +141,7 @@ sub bn_mul_comba $bi=$bs; $end=$be+1; - &comment("################## Calculate word $i"); + &comment("################## Calculate word $i"); for ($j=$bs; $j<$end; $j++) { diff --git a/lib/libcrypto/bn/asm/mips-mont.pl b/lib/libcrypto/bn/asm/mips-mont.pl index caae04ed3..201731f27 100644 --- a/lib/libcrypto/bn/asm/mips-mont.pl +++ b/lib/libcrypto/bn/asm/mips-mont.pl @@ -350,7 +350,7 @@ $code.=<<___; addu $i,$BNSZ sltu $t0,$i,$num bnez $t0,.Louter - + .set noreorder $PTR_ADD $tj,$sp,$num # &tp[num] move $tp,$sp diff --git a/lib/libcrypto/bn/asm/mips.pl b/lib/libcrypto/bn/asm/mips.pl index 02d43e15b..4f059e46e 100644 --- a/lib/libcrypto/bn/asm/mips.pl +++ b/lib/libcrypto/bn/asm/mips.pl @@ -580,13 +580,13 @@ $code.=<<___; sltu $v0,$t2,$ta2 $ST $t2,-2*$BNSZ($a0) $ADDU $v0,$t8 - + $ADDU $ta3,$t3 sltu $t9,$ta3,$t3 $ADDU $t3,$ta3,$v0 sltu $v0,$t3,$ta3 $ST $t3,-$BNSZ($a0) - + .set noreorder bgtz $at,.L_bn_add_words_loop $ADDU $v0,$t9 @@ -785,7 +785,7 @@ bn_div_3_words: # so that we can save two arguments # and return address in registers # instead of stack:-) - + $LD $a0,($a3) move $ta2,$a1 bne $a0,$a2,bn_div_3_words_internal diff --git a/lib/libcrypto/bn/asm/parisc-mont.pl b/lib/libcrypto/bn/asm/parisc-mont.pl index 0c7aff93b..9b2caea91 100644 --- a/lib/libcrypto/bn/asm/parisc-mont.pl +++ b/lib/libcrypto/bn/asm/parisc-mont.pl @@ -59,7 +59,7 @@ # Special thanks to polarhome.com for providing HP-UX account on # PA-RISC 1.1 machine, and to correspondent who chose to remain # anonymous for testing the code on PA-RISC 2.0 machine. - + $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1; $flavour = shift; @@ -228,7 +228,7 @@ $code.=<<___; # PA-RISC 2.0 code-path ldo 8($idx),$idx ; j++++ addl $ab0,$nm0,$nm0 ; low part is discarded extrd,u $nm0,31,32,$hi1 - + L\$1st xmpyu ${fai}R,${fbi},${fab1} ; ap[j+1]*bp[0] xmpyu ${fni}R,${fm0}R,${fnm1} ; np[j+1]*m @@ -349,7 +349,7 @@ L\$outer extrd,u $nm0,31,32,$hi1 fstds ${fab0},-16($xfer) fstds ${fnm0},-8($xfer) - + L\$inner xmpyu ${fai}R,${fbi},${fab1} ; ap[j+1]*bp[i] xmpyu ${fni}R,${fm0}R,${fnm1} ; np[j+1]*m @@ -464,7 +464,7 @@ $code.=<<___; b L\$outer ldo `$LOCALS+32+4`($fp),$tp - + L\$outerdone addl $hi0,$ab1,$ab1 addl $ti1,$ab1,$ab1 @@ -529,7 +529,7 @@ L\$copy ldd $idx($np),$hi0 std,ma %r0,8($tp) addib,<> 8,$idx,.-8 ; L\$copy - std,ma $hi0,8($rp) + std,ma $hi0,8($rp) ___ if ($BN_SZ==4) { # PA-RISC 1.1 code-path @@ -562,7 +562,7 @@ L\$parisc11 ldw 4($xfer),$ablo ldw 0($xfer),$abhi nop - + L\$1st_pa11 xmpyu ${fai}R,${fbi},${fab1} ; ap[j+1]*bp[0] flddx $idx($ap),${fai} ; ap[j,j+1] @@ -687,7 +687,7 @@ L\$outer_pa11 fstds ${fnm0},-8($xfer) ldw 4($xfer),$ablo ldw 0($xfer),$abhi - + L\$inner_pa11 xmpyu ${fai}R,${fbi},${fab1} ; ap[j+1]*bp[i] flddx $idx($ap),${fai} ; ap[j,j+1] @@ -806,7 +806,7 @@ L\$inner_pa11 b L\$outer_pa11 ldo `$LOCALS+32+4`($fp),$tp - + L\$outerdone_pa11 add $hi0,$ablo,$ablo addc %r0,$abhi,$abhi @@ -852,13 +852,13 @@ L\$copy_pa11 ldwx $idx($np),$hi0 stws,ma %r0,4($tp) addib,<> 4,$idx,L\$copy_pa11 - stws,ma $hi0,4($rp) + stws,ma $hi0,4($rp) nop ; alignment L\$done ___ } - + $code.=<<___; ldi 1,%r28 ; signal "handled" ldo $FRAME($fp),%sp ; destroy tp[num+1] @@ -877,7 +877,7 @@ L\$abort $POPMB -$FRAME(%sp),%r3 .PROCEND ___ - + # Explicitly encode PA-RISC 2.0 instructions used in this module, so # that it can be compiled with .LEVEL 1.0. It should be noted that I # wouldn't have to do this, if GNU assembler understood .ALLOW 2.0 diff --git a/lib/libcrypto/bn/asm/ppc-mont.pl b/lib/libcrypto/bn/asm/ppc-mont.pl index 293343619..2283f7db8 100644 --- a/lib/libcrypto/bn/asm/ppc-mont.pl +++ b/lib/libcrypto/bn/asm/ppc-mont.pl @@ -19,7 +19,7 @@ # So far RSA *sign* performance improvement over pre-bn_mul_mont asm # for 64-bit application running on PPC970/G5 is: # -# 512-bit +65% +# 512-bit +65% # 1024-bit +35% # 2048-bit +18% # 4096-bit +4% @@ -42,7 +42,7 @@ if ($flavour =~ /32/) { $UMULL= "mullw"; # unsigned multiply low $UMULH= "mulhwu"; # unsigned multiply high $UCMP= "cmplw"; # unsigned compare - $SHRI= "srwi"; # unsigned shift right by immediate + $SHRI= "srwi"; # unsigned shift right by immediate $PUSH= $ST; $POP= $LD; } elsif ($flavour =~ /64/) { @@ -62,7 +62,7 @@ if ($flavour =~ /32/) { $UMULL= "mulld"; # unsigned multiply low $UMULH= "mulhdu"; # unsigned multiply high $UCMP= "cmpld"; # unsigned compare - $SHRI= "srdi"; # unsigned shift right by immediate + $SHRI= "srdi"; # unsigned shift right by immediate $PUSH= $ST; $POP= $LD; } else { die "nonsense $flavour"; } @@ -147,7 +147,7 @@ $code.=<<___; $LD $n0,0($n0) ; pull n0[0] value addi $num,$num,-2 ; adjust $num for counter register - + $LD $m0,0($bp) ; m0=bp[0] $LD $aj,0($ap) ; ap[0] addi $tp,$sp,$LOCALS @@ -206,7 +206,7 @@ L1st: addc $hi1,$hi1,$hi0 addze $ovf,$ovf ; upmost overflow bit $ST $hi1,$BNSZ($tp) - + li $i,$BNSZ .align 4 Louter: @@ -230,7 +230,7 @@ Louter: $UMULL $nlo,$nj,$m1 ; np[1]*m1 addze $hi1,$hi1 $UMULH $nhi,$nj,$m1 - + mtctr $num li $j,`2*$BNSZ` .align 4 @@ -277,7 +277,7 @@ Linner: $UCMP $i,$tj addi $i,$i,$BNSZ ble- Louter - + addi $num,$num,2 ; restore $num subfc $j,$j,$j ; j=0 and "clear" XER[CA] addi $tp,$sp,$LOCALS diff --git a/lib/libcrypto/bn/asm/ppc.pl b/lib/libcrypto/bn/asm/ppc.pl index c9b7f9477..0978d7d09 100644 --- a/lib/libcrypto/bn/asm/ppc.pl +++ b/lib/libcrypto/bn/asm/ppc.pl @@ -32,7 +32,7 @@ #rsa 2048 bits 0.3036s 0.0085s 3.3 117.1 #rsa 4096 bits 2.0040s 0.0299s 0.5 33.4 #dsa 512 bits 0.0087s 0.0106s 114.3 94.5 -#dsa 1024 bits 0.0256s 0.0313s 39.0 32.0 +#dsa 1024 bits 0.0256s 0.0313s 39.0 32.0 # # Same benchmark with this assembler code: # @@ -68,7 +68,7 @@ #rsa 4096 bits 0.3700s 0.0058s 2.7 171.0 #dsa 512 bits 0.0016s 0.0020s 610.7 507.1 #dsa 1024 bits 0.0047s 0.0058s 212.5 173.2 -# +# # Again, performance increases by at about 75% # # Mac OS X, Apple G5 1.8GHz (Note this is 32 bit code) @@ -119,7 +119,7 @@ if ($flavour =~ /32/) { $CNTLZ= "cntlzw"; # count leading zeros $SHL= "slw"; # shift left $SHR= "srw"; # unsigned shift right - $SHRI= "srwi"; # unsigned shift right by immediate + $SHRI= "srwi"; # unsigned shift right by immediate $SHLI= "slwi"; # shift left by immediate $CLRU= "clrlwi"; # clear upper bits $INSR= "insrwi"; # insert right @@ -143,10 +143,10 @@ if ($flavour =~ /32/) { $CNTLZ= "cntlzd"; # count leading zeros $SHL= "sld"; # shift left $SHR= "srd"; # unsigned shift right - $SHRI= "srdi"; # unsigned shift right by immediate + $SHRI= "srdi"; # unsigned shift right by immediate $SHLI= "sldi"; # shift left by immediate $CLRU= "clrldi"; # clear upper bits - $INSR= "insrdi"; # insert right + $INSR= "insrdi"; # insert right $ROTL= "rotldi"; # rotate left by immediate $TR= "td"; # conditional trap } else { die "nonsense $flavour"; } @@ -183,7 +183,7 @@ $data=<=d? blt Lppcasm_div3 #goto Lppcasm_div3 if not - subf r3,r5,r3 #h-=d ; + subf r3,r5,r3 #h-=d ; Lppcasm_div3: #r7 = BN_BITS2-i. so r7=i cmpi 0,0,r7,0 # is (i == 0)? beq Lppcasm_div4 @@ -1638,7 +1638,7 @@ Lppcasm_div4: # as it saves registers. li r6,2 #r6=2 mtctr r6 #counter will be in count. -Lppcasm_divouterloop: +Lppcasm_divouterloop: $SHRI r8,r3,`$BITS/2` #r8 = (h>>BN_BITS4) $SHRI r11,r4,`$BITS/2` #r11= (l&BN_MASK2h)>>BN_BITS4 # compute here for innerloop. @@ -1646,7 +1646,7 @@ Lppcasm_divouterloop: bne Lppcasm_div5 # goto Lppcasm_div5 if not li r8,-1 - $CLRU r8,r8,`$BITS/2` #q = BN_MASK2l + $CLRU r8,r8,`$BITS/2` #q = BN_MASK2l b Lppcasm_div6 Lppcasm_div5: $UDIV r8,r3,r9 #q = h/dh @@ -1654,7 +1654,7 @@ Lppcasm_div6: $UMULL r12,r9,r8 #th = q*dh $CLRU r10,r5,`$BITS/2` #r10=dl $UMULL r6,r8,r10 #tl = q*dl - + Lppcasm_divinnerloop: subf r10,r12,r3 #t = h -th $SHRI r7,r10,`$BITS/2` #r7= (t &BN_MASK2H), sort of... @@ -1727,7 +1727,7 @@ Lppcasm_div9: addi r4,r4,-$BNSZ addi r3,r3,-$BNSZ mtctr r5 -Lppcasm_sqr_mainloop: +Lppcasm_sqr_mainloop: #sqr(r[0],r[1],a[0]); $LDU r6,$BNSZ(r4) $UMULL r7,r6,r6 @@ -1735,7 +1735,7 @@ Lppcasm_sqr_mainloop: $STU r7,$BNSZ(r3) $STU r8,$BNSZ(r3) bdnz- Lppcasm_sqr_mainloop -Lppcasm_sqr_adios: +Lppcasm_sqr_adios: blr # @@ -1745,7 +1745,7 @@ Lppcasm_sqr_adios: # done in the build # -.align 4 +.align 4 .bn_mul_words: # # BN_ULONG bn_mul_words(BN_ULONG *rp, BN_ULONG *ap, int num, BN_ULONG w) @@ -1759,7 +1759,7 @@ Lppcasm_sqr_adios: rlwinm. r7,r5,30,2,31 # num >> 2 beq Lppcasm_mw_REM mtctr r7 -Lppcasm_mw_LOOP: +Lppcasm_mw_LOOP: #mul(rp[0],ap[0],w,c1); $LD r8,`0*$BNSZ`(r4) $UMULL r9,r6,r8 @@ -1771,7 +1771,7 @@ Lppcasm_mw_LOOP: #using adde. $ST r9,`0*$BNSZ`(r3) #mul(rp[1],ap[1],w,c1); - $LD r8,`1*$BNSZ`(r4) + $LD r8,`1*$BNSZ`(r4) $UMULL r11,r6,r8 $UMULH r12,r6,r8 adde r11,r11,r10 @@ -1792,7 +1792,7 @@ Lppcasm_mw_LOOP: addze r12,r12 #this spin we collect carry into #r12 $ST r11,`3*$BNSZ`(r3) - + addi r3,r3,`4*$BNSZ` addi r4,r4,`4*$BNSZ` bdnz- Lppcasm_mw_LOOP @@ -1808,25 +1808,25 @@ Lppcasm_mw_REM: addze r10,r10 $ST r9,`0*$BNSZ`(r3) addi r12,r10,0 - + addi r5,r5,-1 cmpli 0,0,r5,0 beq Lppcasm_mw_OVER - + #mul(rp[1],ap[1],w,c1); - $LD r8,`1*$BNSZ`(r4) + $LD r8,`1*$BNSZ`(r4) $UMULL r9,r6,r8 $UMULH r10,r6,r8 addc r9,r9,r12 addze r10,r10 $ST r9,`1*$BNSZ`(r3) addi r12,r10,0 - + addi r5,r5,-1 cmpli 0,0,r5,0 beq Lppcasm_mw_OVER - + #mul_add(rp[2],ap[2],w,c1); $LD r8,`2*$BNSZ`(r4) $UMULL r9,r6,r8 @@ -1835,8 +1835,8 @@ Lppcasm_mw_REM: addze r10,r10 $ST r9,`2*$BNSZ`(r3) addi r12,r10,0 - -Lppcasm_mw_OVER: + +Lppcasm_mw_OVER: addi r3,r12,0 blr @@ -1860,11 +1860,11 @@ Lppcasm_mw_OVER: # empirical evidence suggests that unrolled version performs best!! # xor r0,r0,r0 #r0 = 0 - xor r12,r12,r12 #r12 = 0 . used for carry + xor r12,r12,r12 #r12 = 0 . used for carry rlwinm. r7,r5,30,2,31 # num >> 2 beq Lppcasm_maw_leftover # if (num < 4) go LPPCASM_maw_leftover mtctr r7 -Lppcasm_maw_mainloop: +Lppcasm_maw_mainloop: #mul_add(rp[0],ap[0],w,c1); $LD r8,`0*$BNSZ`(r4) $LD r11,`0*$BNSZ`(r3) @@ -1880,9 +1880,9 @@ Lppcasm_maw_mainloop: #by multiply and will be collected #in the next spin $ST r9,`0*$BNSZ`(r3) - + #mul_add(rp[1],ap[1],w,c1); - $LD r8,`1*$BNSZ`(r4) + $LD r8,`1*$BNSZ`(r4) $LD r9,`1*$BNSZ`(r3) $UMULL r11,r6,r8 $UMULH r12,r6,r8 @@ -1891,7 +1891,7 @@ Lppcasm_maw_mainloop: addc r11,r11,r9 #addze r12,r12 $ST r11,`1*$BNSZ`(r3) - + #mul_add(rp[2],ap[2],w,c1); $LD r8,`2*$BNSZ`(r4) $UMULL r9,r6,r8 @@ -1902,7 +1902,7 @@ Lppcasm_maw_mainloop: addc r9,r9,r11 #addze r10,r10 $ST r9,`2*$BNSZ`(r3) - + #mul_add(rp[3],ap[3],w,c1); $LD r8,`3*$BNSZ`(r4) $UMULL r11,r6,r8 @@ -1916,7 +1916,7 @@ Lppcasm_maw_mainloop: addi r3,r3,`4*$BNSZ` addi r4,r4,`4*$BNSZ` bdnz- Lppcasm_maw_mainloop - + Lppcasm_maw_leftover: andi. r5,r5,0x3 beq Lppcasm_maw_adios @@ -1933,10 +1933,10 @@ Lppcasm_maw_leftover: addc r9,r9,r12 addze r12,r10 $ST r9,0(r3) - + bdz Lppcasm_maw_adios #mul_add(rp[1],ap[1],w,c1); - $LDU r8,$BNSZ(r4) + $LDU r8,$BNSZ(r4) $UMULL r9,r6,r8 $UMULH r10,r6,r8 $LDU r11,$BNSZ(r3) @@ -1945,7 +1945,7 @@ Lppcasm_maw_leftover: addc r9,r9,r12 addze r12,r10 $ST r9,0(r3) - + bdz Lppcasm_maw_adios #mul_add(rp[2],ap[2],w,c1); $LDU r8,$BNSZ(r4) @@ -1957,8 +1957,8 @@ Lppcasm_maw_leftover: addc r9,r9,r12 addze r12,r10 $ST r9,0(r3) - -Lppcasm_maw_adios: + +Lppcasm_maw_adios: addi r3,r12,0 blr .align 4 diff --git a/lib/libcrypto/bn/asm/ppc64-mont.pl b/lib/libcrypto/bn/asm/ppc64-mont.pl index a9291f4bf..7ac05105e 100644 --- a/lib/libcrypto/bn/asm/ppc64-mont.pl +++ b/lib/libcrypto/bn/asm/ppc64-mont.pl @@ -154,7 +154,7 @@ $T0a="f24"; $T0b="f25"; $T1a="f26"; $T1b="f27"; $T2a="f28"; $T2b="f29"; $T3a="f30"; $T3b="f31"; - + # sp----------->+-------------------------------+ # | saved sp | # +-------------------------------+ @@ -189,7 +189,7 @@ $T3a="f30"; $T3b="f31"; # . . # . . # +-------------------------------+ - + $code=<<___; .machine "any" .text @@ -260,7 +260,7 @@ $code.=<<___; li $i,-64 add $nap_d,$tp,$num and $nap_d,$nap_d,$i ; align to 64 bytes - + mulld $t7,$a0,$t3 ; ap[0]*bp[0] ; nap_d is off by 1, because it's used with stfdu/lfdu addi $nap_d,$nap_d,-8 @@ -416,7 +416,7 @@ $code.=<<___; stfd $T2b,`$FRAME+40`($sp) stfd $T3a,`$FRAME+48`($sp) stfd $T3b,`$FRAME+56`($sp) - + .align 5 L1st: ___ @@ -562,7 +562,7 @@ $code.=<<___; std $t0,8($tp) ; tp[j-1] stdu $t4,16($tp) ; tp[j] bdnz- L1st - + fctid $dota,$dota fctid $dotb,$dotb @@ -614,7 +614,7 @@ $code.=<<___; slwi $t7,$num,2 subf $nap_d,$t7,$nap_d ; rewind pointer - + li $i,8 ; i=1 .align 5 Louter: @@ -741,7 +741,7 @@ $code.=<<___; stfd $T2b,`$FRAME+40`($sp) stfd $T3a,`$FRAME+48`($sp) stfd $T3b,`$FRAME+56`($sp) - + .align 5 Linner: fmul $T1a,$A1,$ba @@ -857,7 +857,7 @@ $code.=<<___; std $t3,-16($tp) ; tp[j-1] std $t5,-8($tp) ; tp[j] bdnz- Linner - + fctid $dota,$dota fctid $dotb,$dotb ld $t0,`$FRAME+0`($sp) @@ -933,7 +933,7 @@ $code.=<<___; cmpw $i,$num blt- Louter ___ - + $code.=<<___ if ($SIZE_T==8); subf $np,$num,$np ; rewind np addi $j,$j,1 ; restore counter @@ -1048,7 +1048,7 @@ Lcopy: ; copy or in-place refresh stdu $i,16($tp) bdnz- Lcopy ___ - + $code.=<<___; $POP $i,0($sp) li r3,1 ; signal "handled" diff --git a/lib/libcrypto/bn/asm/x86-mont.pl b/lib/libcrypto/bn/asm/x86-mont.pl index 652465174..17641415d 100755 --- a/lib/libcrypto/bn/asm/x86-mont.pl +++ b/lib/libcrypto/bn/asm/x86-mont.pl @@ -102,7 +102,7 @@ $frame=32; # size of above frame rounded up to 16n &lea ($num,&DWP(-3,"edi")); # num=num-1 to assist modulo-scheduling #&mov ($_num,$num); # redundant as $num is not reused &mov ($_sp,"ebp"); # saved stack pointer! - + if($sse2) { $acc0="mm0"; # mmx register bank layout $acc1="mm1"; @@ -183,7 +183,7 @@ $mask="mm7"; &paddq ($car1,$car0); &movq (&QWP($frame,"esp",$num,4),$car1); # tp[num].tp[num-1] - + &inc ($i); # i++ &set_label("outer"); &xor ($j,$j); # j=0 @@ -262,7 +262,7 @@ $mask="mm7"; &set_label("non_sse2",16); } - + if (0) { &mov ("esp",$_sp); &xor ("eax","eax"); # signal "not fast enough [yet]" @@ -325,7 +325,7 @@ $carry="ebp"; &inc ($j); &jmp (&label("2ndmadd")); - + &set_label("1stmadd",16); &mov ($carry,"edx"); &mul ($word); # ap[j]*bp[i] @@ -362,7 +362,7 @@ $carry="ebp"; &mov ("eax",&DWP(4,$inp)); # np[1] &adc ("edx",0); &mov ($j,1); - + &set_label("2ndmadd",16); &mov ($carry,"edx"); &mul ($word); # np[j]*m @@ -401,7 +401,7 @@ $carry="ebp"; &xor ("edx","edx"); &mov ("eax",&DWP(0,$inp)); &jmp (&label("1stmadd")); - + &set_label("bn_sqr_mont",16); $sbit=$num; &mov ($_num,$num); @@ -452,7 +452,7 @@ $sbit=$num; &adc ("edx",0); &mov ("eax",&DWP(4,$inp)); # np[1] &mov ($j,1); - + &set_label("3rdmadd",16); &mov ($carry,"edx"); &mul ($word); # np[j]*m @@ -492,7 +492,7 @@ $sbit=$num; &cmp ($j,$num); &mov (&DWP($frame+4,"esp",$num,4),"eax"); # tp[num]= &je (&label("common_tail")); - + &mov ($word,&DWP(4,$inp,$j,4)); # ap[i] &lea ($j,&DWP(1,$j)); &mov ("eax",$word); @@ -552,7 +552,7 @@ $sbit=$num; &jmp (&label("3rdmadd")); } - + &set_label("common_tail",16); &mov ($np,$_np); # load modulus pointer &mov ($rp,$_rp); # load result pointer diff --git a/lib/libcrypto/bn/asm/x86_64-mont.pl b/lib/libcrypto/bn/asm/x86_64-mont.pl index 6f5ab331e..a6ff073c6 100755 --- a/lib/libcrypto/bn/asm/x86_64-mont.pl +++ b/lib/libcrypto/bn/asm/x86_64-mont.pl @@ -686,7 +686,8 @@ $code.=<<___; .size bn_mul4x_mont,.-bn_mul4x_mont ___ }}} - {{{ + +{{{ ###################################################################### # void bn_sqr4x_mont( my $rptr="%rdi"; # const BN_ULONG *rptr, @@ -1191,7 +1192,8 @@ $code.=<<___; mov $S[2],-16($tptr) mov $S[3],-8($tptr) ___ -} +} + ############################################################## # Montgomery reduction part, "word-by-word" algorithm. # @@ -1398,7 +1400,8 @@ $code.=<<___; mov 0(%rsp),$num # restore $num mov $topbit,($tptr) # save $topbit ___ -} +} + ############################################################## # Post-condition, 4x unrolled copy from bn_mul_mont # diff --git a/lib/libcrypto/bytestring/bytestring.h b/lib/libcrypto/bytestring/bytestring.h index d80e89c9a..198557c62 100644 --- a/lib/libcrypto/bytestring/bytestring.h +++ b/lib/libcrypto/bytestring/bytestring.h @@ -559,6 +559,6 @@ int cbs_get_any_asn1_element_internal(CBS *cbs, CBS *out, unsigned int *out_tag, int CBS_asn1_indefinite_to_definite(CBS *in, uint8_t **out, size_t *out_len); #endif /* LIBRESSL_INTERNAL */ -__END_HIDDEN_DECLS +__END_HIDDEN_DECLS #endif /* OPENSSL_HEADER_BYTESTRING_H */ diff --git a/lib/libcrypto/camellia/asm/cmll-x86.pl b/lib/libcrypto/camellia/asm/cmll-x86.pl index a4ab11e54..7880913da 100644 --- a/lib/libcrypto/camellia/asm/cmll-x86.pl +++ b/lib/libcrypto/camellia/asm/cmll-x86.pl @@ -772,9 +772,9 @@ if ($OPENSSL) { 64, 40,211,123,187,201, 67,193, 21,227,173,244,119,199,128,158); sub S1110 { my $i=shift; $i=@SBOX[$i]; return $i<<24|$i<<16|$i<<8; } -sub S4404 { my $i=shift; $i=($i<<1|$i>>7)&0xff; $i=@SBOX[$i]; return $i<<24|$i<<16|$i; } -sub S0222 { my $i=shift; $i=@SBOX[$i]; $i=($i<<1|$i>>7)&0xff; return $i<<16|$i<<8|$i; } -sub S3033 { my $i=shift; $i=@SBOX[$i]; $i=($i>>1|$i<<7)&0xff; return $i<<24|$i<<8|$i; } +sub S4404 { my $i=shift; $i=($i<<1|$i>>7)&0xff; $i=@SBOX[$i]; return $i<<24|$i<<16|$i; } +sub S0222 { my $i=shift; $i=@SBOX[$i]; $i=($i<<1|$i>>7)&0xff; return $i<<16|$i<<8|$i; } +sub S3033 { my $i=shift; $i=@SBOX[$i]; $i=($i>>1|$i<<7)&0xff; return $i<<24|$i<<8|$i; } &rodataseg(); &set_label("Camellia_SIGMA",64); diff --git a/lib/libcrypto/camellia/camellia.c b/lib/libcrypto/camellia/camellia.c index 336074ad7..355cf6b35 100644 --- a/lib/libcrypto/camellia/camellia.c +++ b/lib/libcrypto/camellia/camellia.c @@ -1,6 +1,6 @@ /* $OpenBSD: camellia.c,v 1.12 2022/11/26 16:08:51 tb Exp $ */ /* ==================================================================== - * Copyright 2006 NTT (Nippon Telegraph and Telephone Corporation) . + * Copyright 2006 NTT (Nippon Telegraph and Telephone Corporation) . * ALL RIGHTS RESERVED. * * Intellectual Property information for Camellia: @@ -24,7 +24,7 @@ * are met: * * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. + * notice, this list of conditions and the following disclaimer. * * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in diff --git a/lib/libcrypto/camellia/camellia.h b/lib/libcrypto/camellia/camellia.h index b9b5f792b..0fe50d24b 100644 --- a/lib/libcrypto/camellia/camellia.h +++ b/lib/libcrypto/camellia/camellia.h @@ -7,7 +7,7 @@ * are met: * * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. + * notice, this list of conditions and the following disclaimer. * * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in diff --git a/lib/libcrypto/camellia/cmll_cbc.c b/lib/libcrypto/camellia/cmll_cbc.c index 6567e5deb..9e5484ec5 100644 --- a/lib/libcrypto/camellia/cmll_cbc.c +++ b/lib/libcrypto/camellia/cmll_cbc.c @@ -7,7 +7,7 @@ * are met: * * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. + * notice, this list of conditions and the following disclaimer. * * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in diff --git a/lib/libcrypto/camellia/cmll_cfb.c b/lib/libcrypto/camellia/cmll_cfb.c index 755ab9f8b..82ea2ec57 100644 --- a/lib/libcrypto/camellia/cmll_cfb.c +++ b/lib/libcrypto/camellia/cmll_cfb.c @@ -7,7 +7,7 @@ * are met: * * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. + * notice, this list of conditions and the following disclaimer. * * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in @@ -54,21 +54,21 @@ * This package is an SSL implementation written * by Eric Young (eay@cryptsoft.com). * The implementation was written so as to conform with Netscapes SSL. - * + * * This library is free for commercial and non-commercial use as long as * the following conditions are aheared to. The following conditions * apply to all code found in this distribution, be it the RC4, RSA, * lhash, DES, etc., code; not just the SSL code. The SSL documentation * included with this distribution is covered by the same copyright terms * except that the holder is Tim Hudson (tjh@cryptsoft.com). - * + * * Copyright remains Eric Young's, and as such any Copyright notices in * the code are not to be removed. * If this package is used in a product, Eric Young should be given attribution * as the author of the parts of the library used. * This can be in the form of a textual message at program startup or * in documentation (online or textual) provided with the package. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: @@ -83,10 +83,10 @@ * Eric Young (eay@cryptsoft.com)" * The word 'cryptographic' can be left out if the rouines from the library * being used are not cryptographic related :-). - * 4. If you include any Windows specific code (or a derivative thereof) from + * 4. If you include any Windows specific code (or a derivative thereof) from * the apps directory (application code) you must include an acknowledgement: * "This product includes software written by Tim Hudson (tjh@cryptsoft.com)" - * + * * THIS SOFTWARE IS PROVIDED BY ERIC YOUNG ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -98,7 +98,7 @@ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. - * + * * The licence and distribution terms for any publically available version or * derivative of this code cannot be changed. i.e. this code cannot simply be * copied and put under another distribution licence diff --git a/lib/libcrypto/camellia/cmll_ctr.c b/lib/libcrypto/camellia/cmll_ctr.c index 59a351ee1..8c65a6793 100644 --- a/lib/libcrypto/camellia/cmll_ctr.c +++ b/lib/libcrypto/camellia/cmll_ctr.c @@ -7,7 +7,7 @@ * are met: * * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. + * notice, this list of conditions and the following disclaimer. * * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in diff --git a/lib/libcrypto/camellia/cmll_ecb.c b/lib/libcrypto/camellia/cmll_ecb.c index 0575d29e2..86733f37a 100644 --- a/lib/libcrypto/camellia/cmll_ecb.c +++ b/lib/libcrypto/camellia/cmll_ecb.c @@ -7,7 +7,7 @@ * are met: * * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. + * notice, this list of conditions and the following disclaimer. * * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in diff --git a/lib/libcrypto/camellia/cmll_local.h b/lib/libcrypto/camellia/cmll_local.h index 831625e77..30597737b 100644 --- a/lib/libcrypto/camellia/cmll_local.h +++ b/lib/libcrypto/camellia/cmll_local.h @@ -1,6 +1,6 @@ /* $OpenBSD: cmll_local.h,v 1.3 2023/09/04 08:43:41 tb Exp $ */ /* ==================================================================== - * Copyright 2006 NTT (Nippon Telegraph and Telephone Corporation) . + * Copyright 2006 NTT (Nippon Telegraph and Telephone Corporation) . * ALL RIGHTS RESERVED. * * Intellectual Property information for Camellia: @@ -24,7 +24,7 @@ * are met: * * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. + * notice, this list of conditions and the following disclaimer. * * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in diff --git a/lib/libcrypto/camellia/cmll_misc.c b/lib/libcrypto/camellia/cmll_misc.c index 9fce92df2..9738f0cdc 100644 --- a/lib/libcrypto/camellia/cmll_misc.c +++ b/lib/libcrypto/camellia/cmll_misc.c @@ -7,7 +7,7 @@ * are met: * * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. + * notice, this list of conditions and the following disclaimer. * * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in diff --git a/lib/libcrypto/camellia/cmll_ofb.c b/lib/libcrypto/camellia/cmll_ofb.c index cd3a65e2f..86998f9f0 100644 --- a/lib/libcrypto/camellia/cmll_ofb.c +++ b/lib/libcrypto/camellia/cmll_ofb.c @@ -7,7 +7,7 @@ * are met: * * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. + * notice, this list of conditions and the following disclaimer. * * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in @@ -54,21 +54,21 @@ * This package is an SSL implementation written * by Eric Young (eay@cryptsoft.com). * The implementation was written so as to conform with Netscapes SSL. - * + * * This library is free for commercial and non-commercial use as long as * the following conditions are aheared to. The following conditions * apply to all code found in this distribution, be it the RC4, RSA, * lhash, DES, etc., code; not just the SSL code. The SSL documentation * included with this distribution is covered by the same copyright terms * except that the holder is Tim Hudson (tjh@cryptsoft.com). - * + * * Copyright remains Eric Young's, and as such any Copyright notices in * the code are not to be removed. * If this package is used in a product, Eric Young should be given attribution * as the author of the parts of the library used. * This can be in the form of a textual message at program startup or * in documentation (online or textual) provided with the package. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: @@ -83,10 +83,10 @@ * Eric Young (eay@cryptsoft.com)" * The word 'cryptographic' can be left out if the rouines from the library * being used are not cryptographic related :-). - * 4. If you include any Windows specific code (or a derivative thereof) from + * 4. If you include any Windows specific code (or a derivative thereof) from * the apps directory (application code) you must include an acknowledgement: * "This product includes software written by Tim Hudson (tjh@cryptsoft.com)" - * + * * THIS SOFTWARE IS PROVIDED BY ERIC YOUNG ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -98,7 +98,7 @@ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. - * + * * The licence and distribution terms for any publically available version or * derivative of this code cannot be changed. i.e. this code cannot simply be * copied and put under another distribution licence diff --git a/lib/libcrypto/conf/README b/lib/libcrypto/conf/README index 96e53b34e..a89828cf7 100644 --- a/lib/libcrypto/conf/README +++ b/lib/libcrypto/conf/README @@ -64,7 +64,7 @@ where "name" is the name in the configuration file this function corresponds to. A set of builtin modules (currently only an ASN1 non functional test module) -can be added by calling OPENSSL_load_builtin_modules(). +can be added by calling OPENSSL_load_builtin_modules(). The function OPENSSL_config() is intended as a simple configuration function that any application can call to perform various default configuration tasks. diff --git a/lib/libcrypto/conf/keysets.pl b/lib/libcrypto/conf/keysets.pl index fe17be57f..a344e568b 100644 --- a/lib/libcrypto/conf/keysets.pl +++ b/lib/libcrypto/conf/keysets.pl @@ -59,21 +59,21 @@ print <<"EOF"; * This package is an SSL implementation written * by Eric Young (eay\@cryptsoft.com). * The implementation was written so as to conform with Netscapes SSL. - * + * * This library is free for commercial and non-commercial use as long as * the following conditions are aheared to. The following conditions * apply to all code found in this distribution, be it the RC4, RSA, * lhash, DES, etc., code; not just the SSL code. The SSL documentation * included with this distribution is covered by the same copyright terms * except that the holder is Tim Hudson (tjh\@cryptsoft.com). - * + * * Copyright remains Eric Young's, and as such any Copyright notices in * the code are not to be removed. * If this package is used in a product, Eric Young should be given attribution * as the author of the parts of the library used. * This can be in the form of a textual message at program startup or * in documentation (online or textual) provided with the package. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: @@ -88,10 +88,10 @@ print <<"EOF"; * Eric Young (eay\@cryptsoft.com)" * The word 'cryptographic' can be left out if the rouines from the library * being used are not cryptographic related :-). - * 4. If you include any Windows specific code (or a derivative thereof) from + * 4. If you include any Windows specific code (or a derivative thereof) from * the apps directory (application code) you must include an acknowledgement: * "This product includes software written by Tim Hudson (tjh\@cryptsoft.com)" - * + * * THIS SOFTWARE IS PROVIDED BY ERIC YOUNG ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -103,7 +103,7 @@ print <<"EOF"; * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. - * + * * The licence and distribution terms for any publically available version or * derivative of this code cannot be changed. i.e. this code cannot simply be * copied and put under another distribution licence diff --git a/lib/libcrypto/des/asm/des-586.pl b/lib/libcrypto/des/asm/des-586.pl index e11b2ef80..3dad595b9 100644 --- a/lib/libcrypto/des/asm/des-586.pl +++ b/lib/libcrypto/des/asm/des-586.pl @@ -74,7 +74,7 @@ sub DES_encrypt_internal() &function_end_B("_x86_DES_encrypt"); } - + sub DES_decrypt_internal() { &function_begin_B("_x86_DES_decrypt"); @@ -111,7 +111,7 @@ sub DES_decrypt_internal() &function_end_B("_x86_DES_decrypt"); } - + sub DES_encrypt { local($name,$do_ip)=@_; @@ -269,7 +269,7 @@ sub IP_new &R_PERM_OP($l,$tt,$r,14,"0x33333333",$r); &R_PERM_OP($tt,$r,$l,22,"0x03fc03fc",$r); &R_PERM_OP($l,$r,$tt, 9,"0xaaaaaaaa",$r); - + if ($lr != 3) { if (($lr-3) < 0) diff --git a/lib/libcrypto/des/asm/des_enc.m4 b/lib/libcrypto/des/asm/des_enc.m4 index 3fbb026dd..268fc28c2 100644 --- a/lib/libcrypto/des/asm/des_enc.m4 +++ b/lib/libcrypto/des/asm/des_enc.m4 @@ -331,7 +331,7 @@ $4: sll out1, 28, out1 ! rotate xor $1, local1, $1 ! 1 finished, local1 now sbox 7 - ld [global2+local2], local2 ! 2 + ld [global2+local2], local2 ! 2 srl out0, 24, local1 ! 7 or out1, local0, out1 ! rotate @@ -1358,7 +1358,7 @@ DES_encrypt2: DES_encrypt3: save %sp, FRAME, %sp - + sethi %hi(.PIC.DES_SPtrans-1f),global1 or global1,%lo(.PIC.DES_SPtrans-1f),global1 1: call .+8 @@ -1403,7 +1403,7 @@ DES_encrypt3: DES_decrypt3: save %sp, FRAME, %sp - + sethi %hi(.PIC.DES_SPtrans-1f),global1 or global1,%lo(.PIC.DES_SPtrans-1f),global1 1: call .+8 @@ -1448,7 +1448,7 @@ DES_decrypt3: DES_ncbc_encrypt: save %sp, FRAME, %sp - + define({INPUT}, { [%sp+BIAS+ARG0+0*ARGSZ] }) define({OUTPUT}, { [%sp+BIAS+ARG0+1*ARGSZ] }) define({IVEC}, { [%sp+BIAS+ARG0+4*ARGSZ] }) @@ -1459,7 +1459,7 @@ DES_ncbc_encrypt: add %o7,global1,global1 sub global1,.PIC.DES_SPtrans-.des_and,out2 - cmp in5, 0 ! enc + cmp in5, 0 ! enc #ifdef OPENSSL_SYSNAME_ULTRASPARC be,pn %icc, .ncbc.dec diff --git a/lib/libcrypto/des/asm/desboth.pl b/lib/libcrypto/des/asm/desboth.pl index eec00886e..7cfe3a7c0 100644 --- a/lib/libcrypto/des/asm/desboth.pl +++ b/lib/libcrypto/des/asm/desboth.pl @@ -27,7 +27,7 @@ sub DES_encrypt3 &IP_new($L,$R,"edx",0); # put them back - + if ($enc) { &mov(&DWP(4,"ebx","",0),$R); diff --git a/lib/libcrypto/dh/dh_asn1.c b/lib/libcrypto/dh/dh_asn1.c index 2e0b054d3..dcb3a084d 100644 --- a/lib/libcrypto/dh/dh_asn1.c +++ b/lib/libcrypto/dh/dh_asn1.c @@ -10,7 +10,7 @@ * are met: * * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. + * notice, this list of conditions and the following disclaimer. * * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in diff --git a/lib/libcrypto/dh/dh_check.c b/lib/libcrypto/dh/dh_check.c index be79c2a04..db104cedf 100644 --- a/lib/libcrypto/dh/dh_check.c +++ b/lib/libcrypto/dh/dh_check.c @@ -5,21 +5,21 @@ * This package is an SSL implementation written * by Eric Young (eay@cryptsoft.com). * The implementation was written so as to conform with Netscapes SSL. - * + * * This library is free for commercial and non-commercial use as long as * the following conditions are aheared to. The following conditions * apply to all code found in this distribution, be it the RC4, RSA, * lhash, DES, etc., code; not just the SSL code. The SSL documentation * included with this distribution is covered by the same copyright terms * except that the holder is Tim Hudson (tjh@cryptsoft.com). - * + * * Copyright remains Eric Young's, and as such any Copyright notices in * the code are not to be removed. * If this package is used in a product, Eric Young should be given attribution * as the author of the parts of the library used. * This can be in the form of a textual message at program startup or * in documentation (online or textual) provided with the package. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: @@ -34,10 +34,10 @@ * Eric Young (eay@cryptsoft.com)" * The word 'cryptographic' can be left out if the rouines from the library * being used are not cryptographic related :-). - * 4. If you include any Windows specific code (or a derivative thereof) from + * 4. If you include any Windows specific code (or a derivative thereof) from * the apps directory (application code) you must include an acknowledgement: * "This product includes software written by Tim Hudson (tjh@cryptsoft.com)" - * + * * THIS SOFTWARE IS PROVIDED BY ERIC YOUNG ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -49,7 +49,7 @@ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. - * + * * The licence and distribution terms for any publically available version or * derivative of this code cannot be changed. i.e. this code cannot simply be * copied and put under another distribution licence diff --git a/lib/libcrypto/dh/dh_err.c b/lib/libcrypto/dh/dh_err.c index f5dda2898..dfa52b5b6 100644 --- a/lib/libcrypto/dh/dh_err.c +++ b/lib/libcrypto/dh/dh_err.c @@ -7,7 +7,7 @@ * are met: * * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. + * notice, this list of conditions and the following disclaimer. * * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in diff --git a/lib/libcrypto/dh/dh_key.c b/lib/libcrypto/dh/dh_key.c index 050d1143f..296050ba7 100644 --- a/lib/libcrypto/dh/dh_key.c +++ b/lib/libcrypto/dh/dh_key.c @@ -5,21 +5,21 @@ * This package is an SSL implementation written * by Eric Young (eay@cryptsoft.com). * The implementation was written so as to conform with Netscapes SSL. - * + * * This library is free for commercial and non-commercial use as long as * the following conditions are aheared to. The following conditions * apply to all code found in this distribution, be it the RC4, RSA, * lhash, DES, etc., code; not just the SSL code. The SSL documentation * included with this distribution is covered by the same copyright terms * except that the holder is Tim Hudson (tjh@cryptsoft.com). - * + * * Copyright remains Eric Young's, and as such any Copyright notices in * the code are not to be removed. * If this package is used in a product, Eric Young should be given attribution * as the author of the parts of the library used. * This can be in the form of a textual message at program startup or * in documentation (online or textual) provided with the package. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: @@ -34,10 +34,10 @@ * Eric Young (eay@cryptsoft.com)" * The word 'cryptographic' can be left out if the rouines from the library * being used are not cryptographic related :-). - * 4. If you include any Windows specific code (or a derivative thereof) from + * 4. If you include any Windows specific code (or a derivative thereof) from * the apps directory (application code) you must include an acknowledgement: * "This product includes software written by Tim Hudson (tjh@cryptsoft.com)" - * + * * THIS SOFTWARE IS PROVIDED BY ERIC YOUNG ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -49,7 +49,7 @@ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. - * + * * The licence and distribution terms for any publically available version or * derivative of this code cannot be changed. i.e. this code cannot simply be * copied and put under another distribution licence diff --git a/lib/libcrypto/dh/dh_pmeth.c b/lib/libcrypto/dh/dh_pmeth.c index 7a598da27..768dfb2fd 100644 --- a/lib/libcrypto/dh/dh_pmeth.c +++ b/lib/libcrypto/dh/dh_pmeth.c @@ -10,7 +10,7 @@ * are met: * * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. + * notice, this list of conditions and the following disclaimer. * * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in @@ -98,7 +98,7 @@ pkey_dh_init(EVP_PKEY_CTX *ctx) ctx->data = dctx; ctx->keygen_info = dctx->gentmp; ctx->keygen_info_count = 2; - + return 1; } @@ -149,7 +149,7 @@ pkey_dh_ctrl(EVP_PKEY_CTX *ctx, int type, int p1, void *p2) return -2; } } - + static int pkey_dh_ctrl_str(EVP_PKEY_CTX *ctx, const char *type, const char *value) { diff --git a/lib/libcrypto/dsa/dsa.h b/lib/libcrypto/dsa/dsa.h index 8029e7f94..73b92d59e 100644 --- a/lib/libcrypto/dsa/dsa.h +++ b/lib/libcrypto/dsa/dsa.h @@ -5,21 +5,21 @@ * This package is an SSL implementation written * by Eric Young (eay@cryptsoft.com). * The implementation was written so as to conform with Netscapes SSL. - * + * * This library is free for commercial and non-commercial use as long as * the following conditions are aheared to. The following conditions * apply to all code found in this distribution, be it the RC4, RSA, * lhash, DES, etc., code; not just the SSL code. The SSL documentation * included with this distribution is covered by the same copyright terms * except that the holder is Tim Hudson (tjh@cryptsoft.com). - * + * * Copyright remains Eric Young's, and as such any Copyright notices in * the code are not to be removed. * If this package is used in a product, Eric Young should be given attribution * as the author of the parts of the library used. * This can be in the form of a textual message at program startup or * in documentation (online or textual) provided with the package. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: @@ -34,10 +34,10 @@ * Eric Young (eay@cryptsoft.com)" * The word 'cryptographic' can be left out if the rouines from the library * being used are not cryptographic related :-). - * 4. If you include any Windows specific code (or a derivative thereof) from + * 4. If you include any Windows specific code (or a derivative thereof) from * the apps directory (application code) you must include an acknowledgement: * "This product includes software written by Tim Hudson (tjh@cryptsoft.com)" - * + * * THIS SOFTWARE IS PROVIDED BY ERIC YOUNG ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -49,7 +49,7 @@ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. - * + * * The licence and distribution terms for any publically available version or * derivative of this code cannot be changed. i.e. this code cannot simply be * copied and put under another distribution licence diff --git a/lib/libcrypto/dsa/dsa_local.h b/lib/libcrypto/dsa/dsa_local.h index a413db974..25f5a634a 100644 --- a/lib/libcrypto/dsa/dsa_local.h +++ b/lib/libcrypto/dsa/dsa_local.h @@ -7,7 +7,7 @@ * are met: * * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. + * notice, this list of conditions and the following disclaimer. * * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in diff --git a/lib/libcrypto/gost/gost_err.c b/lib/libcrypto/gost/gost_err.c index 380f60289..cb23b2f0a 100644 --- a/lib/libcrypto/gost/gost_err.c +++ b/lib/libcrypto/gost/gost_err.c @@ -7,7 +7,7 @@ * are met: * * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. + * notice, this list of conditions and the following disclaimer. * * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in diff --git a/lib/libcrypto/gost/gost_local.h b/lib/libcrypto/gost/gost_local.h index db07d06f0..2059cca08 100644 --- a/lib/libcrypto/gost/gost_local.h +++ b/lib/libcrypto/gost/gost_local.h @@ -66,7 +66,7 @@ typedef struct { unsigned char k3[16]; unsigned char k2[16]; unsigned char k1[16]; -} gost_subst_block; +} gost_subst_block; #if defined(__i386) || defined(__i386__) || defined(__x86_64) || defined(__x86_64__) # define c2l(c,l) ((l)=*((const unsigned int *)(c)), (c)+=4) diff --git a/lib/libcrypto/gost/gostr341194.c b/lib/libcrypto/gost/gostr341194.c index 311c30453..f47f7d5f2 100644 --- a/lib/libcrypto/gost/gostr341194.c +++ b/lib/libcrypto/gost/gostr341194.c @@ -125,8 +125,8 @@ xor_blocks(unsigned char *result, const unsigned char *a, result[i] = a[i] ^ b[i]; } -/* - * Calculate H(i+1) = Hash(Hi,Mi) +/* + * Calculate H(i+1) = Hash(Hi,Mi) * Where H and M are 32 bytes long */ static int diff --git a/lib/libcrypto/idea/idea_local.h b/lib/libcrypto/idea/idea_local.h index c7fd3271a..7be0286af 100644 --- a/lib/libcrypto/idea/idea_local.h +++ b/lib/libcrypto/idea/idea_local.h @@ -67,7 +67,7 @@ if (ul != 0) \ r-=((r)>>16); \ } \ else \ - r=(-(int)a-b+1); /* assuming a or b is 0 and in range */ + r=(-(int)a-b+1); /* assuming a or b is 0 and in range */ /* 7/12/95 - Many thanks to Rhys Weatherley * for pointing out that I was assuming little endian diff --git a/lib/libcrypto/md5/asm/md5-586.pl b/lib/libcrypto/md5/asm/md5-586.pl index 6cb66bb49..ec7f1772f 100644 --- a/lib/libcrypto/md5/asm/md5-586.pl +++ b/lib/libcrypto/md5/asm/md5-586.pl @@ -45,7 +45,7 @@ sub R0 local($pos,$a,$b,$c,$d,$K,$ki,$s,$t)=@_; &mov($tmp1,$C) if $pos < 0; - &mov($tmp2,&DWP($xo[$ki]*4,$K,"",0)) if $pos < 0; # very first one + &mov($tmp2,&DWP($xo[$ki]*4,$K,"",0)) if $pos < 0; # very first one # body proper diff --git a/lib/libcrypto/modes/asm/ghash-armv4.pl b/lib/libcrypto/modes/asm/ghash-armv4.pl index 2d57806b4..25aa56438 100644 --- a/lib/libcrypto/modes/asm/ghash-armv4.pl +++ b/lib/libcrypto/modes/asm/ghash-armv4.pl @@ -410,7 +410,7 @@ gcm_ghash_neon: #ifdef __ARMEL__ vrev64.8 $Z,$Z #endif - sub $Xi,#16 + sub $Xi,#16 vst1.64 `&Dhi("$Z")`,[$Xi,:64]! @ write out Xi vst1.64 `&Dlo("$Z")`,[$Xi,:64] diff --git a/lib/libcrypto/modes/asm/ghash-parisc.pl b/lib/libcrypto/modes/asm/ghash-parisc.pl index 3f9851310..2e5e220fd 100644 --- a/lib/libcrypto/modes/asm/ghash-parisc.pl +++ b/lib/libcrypto/modes/asm/ghash-parisc.pl @@ -121,7 +121,7 @@ $code.=<<___ if ($SIZE_T==4); b L\$parisc1_gmult nop ___ - + $code.=<<___; ldb 15($Xi),$nlo ldo 8($Htbl),$Hll @@ -207,7 +207,7 @@ L\$oop_gmult_pa2 std $Zll,8($Xi) std $Zhh,0($Xi) ___ - + $code.=<<___ if ($SIZE_T==4); b L\$done_gmult nop @@ -378,7 +378,7 @@ $code.=<<___ if ($SIZE_T==4); b L\$parisc1_ghash nop ___ - + $code.=<<___; ldb 15($Xi),$nlo ldo 8($Htbl),$Hll @@ -475,7 +475,7 @@ L\$oop_ghash_pa2 cmpb,*<> $inp,$len,L\$outer_ghash_pa2 copy $Zll,$nlo ___ - + $code.=<<___ if ($SIZE_T==4); b L\$done_ghash nop diff --git a/lib/libcrypto/modes/asm/ghash-x86.pl b/lib/libcrypto/modes/asm/ghash-x86.pl index 5e868a43f..c50454dcf 100644 --- a/lib/libcrypto/modes/asm/ghash-x86.pl +++ b/lib/libcrypto/modes/asm/ghash-x86.pl @@ -125,7 +125,7 @@ for (@ARGV) { $sse2=1 if (/-DOPENSSL_IA32_SSE2/); } ($Zhh,$Zhl,$Zlh,$Zll) = ("ebp","edx","ecx","ebx"); $inp = "edi"; $Htbl = "esi"; - + $unroll = 0; # Affects x86 loop. Folded loop performs ~7% worse # than unrolled, which has to be weighted against # 2.5x x86-specific code size reduction. @@ -243,7 +243,7 @@ sub deposit_rem_4bit { &mov (&DWP($bias+56,"esp"),0xA9C0<<16); &mov (&DWP($bias+60,"esp"),0xB5E0<<16); } - + $suffix = $x86only ? "" : "_x86"; &function_begin("gcm_gmult_4bit".$suffix); @@ -326,7 +326,7 @@ $suffix = $x86only ? "" : "_x86"; &mov (&DWP(0,$inp),$Zhh); &stack_pop(16+4+1); &function_end("gcm_ghash_4bit".$suffix); - + if (!$x86only) {{{ &static_label("rem_4bit"); @@ -425,7 +425,7 @@ $S=12; # shift factor for rem_4bit &mov (&DWP(8,$inp),$Zlh); &mov (&DWP(0,$inp),$Zhh); &function_end("gcm_gmult_4bit_mmx"); - + # Streamed version performs 20% better on P4, 7% on Opteron, # 10% on Core2 and PIII... &function_begin("gcm_ghash_4bit_mmx"); @@ -477,7 +477,7 @@ $S=12; # shift factor for rem_4bit &stack_pop(4+1); &function_end("gcm_ghash_4bit_mmx"); - + }} else {{ # "June" MMX version... # ... has slower "April" gcm_gmult_4bit_mmx with folded # loop. This is done to conserve code size... @@ -593,7 +593,7 @@ sub mmx_loop() { &mov (&DWP(8,$inp),$Zlh); &mov (&DWP(0,$inp),$Zhh); &function_end("gcm_gmult_4bit_mmx"); - + ###################################################################### # Below subroutine is "528B" variant of "4-bit" GCM GHASH function # (see gcm128.c for details). It provides further 20-40% performance @@ -782,7 +782,7 @@ sub mmx_loop() { &bswap ($dat); &pshufw ($Zhi,$Zhi,0b00011011); # 76543210 &bswap ("ebx"); - + &cmp ("ecx",&DWP(528+16+8,"esp")); # are we done? &jne (&label("outer")); } @@ -797,7 +797,7 @@ sub mmx_loop() { } &function_end("gcm_ghash_4bit_mmx"); }} - + if ($sse2) {{ ###################################################################### # PCLMULQDQ version. @@ -862,7 +862,7 @@ my ($Xhi,$Xi,$Hkey)=@_; &pxor ($Xhi,$T2); &pxor ($Xi,$T3); # } - + if (1) { # Algorithm 9 with <<1 twist. # Reduction is shorter and uses only two # temporary registers, which makes it better @@ -1015,7 +1015,7 @@ my ($Xhi,$Xi) = @_; &psllq ($Xi,57); # &movdqa ($T2,$Xi); # &pslldq ($Xi,8); - &psrldq ($T2,8); # + &psrldq ($T2,8); # &pxor ($Xi,$T1); &pshufd ($T1,$T3,0b01001110); &pxor ($Xhi,$T2); # @@ -1073,7 +1073,7 @@ my ($Xhi,$Xi) = @_; &pshufb ($Xi,$T3); &movdqu (&QWP(0,$Xip),$Xi); &function_end("gcm_ghash_clmul"); - + } else { # Algorithm 5. Kept for reference purposes. sub reduction_alg5 { # 19/16 times faster than Intel version @@ -1250,7 +1250,7 @@ my ($Xhi,$Xi)=@_; &function_end("gcm_ghash_clmul"); } - + &rodataseg(); &set_label("bswap",64); &data_byte(15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0); diff --git a/lib/libcrypto/modes/asm/ghash-x86_64.pl b/lib/libcrypto/modes/asm/ghash-x86_64.pl index 9ce0c3814..509e54bc4 100644 --- a/lib/libcrypto/modes/asm/ghash-x86_64.pl +++ b/lib/libcrypto/modes/asm/ghash-x86_64.pl @@ -79,7 +79,7 @@ sub AUTOLOAD() # thunk [simplified] 32-bit style perlasm $arg = "\$$arg" if ($arg*1 eq $arg); $code .= "\t$opcode\t".join(',',$arg,reverse @_)."\n"; } - + { my $N; sub loop() { my $inp = shift; @@ -184,7 +184,7 @@ $code.=<<___; ret .size gcm_gmult_4bit,.-gcm_gmult_4bit ___ - + # per-function register layout $inp="%rdx"; $len="%rcx"; @@ -341,7 +341,7 @@ $code.=<<___; ret .size gcm_ghash_4bit,.-gcm_ghash_4bit ___ - + ###################################################################### # PCLMULQDQ version. @@ -389,7 +389,7 @@ $code.=<<___; psllq \$57,$Xi # movdqa $Xi,$T2 # pslldq \$8,$Xi - psrldq \$8,$T2 # + psrldq \$8,$T2 # pxor $T1,$Xi pxor $T2,$Xhi # @@ -404,7 +404,7 @@ $code.=<<___; pxor $T2,$Xi # ___ } - + { my ($Htbl,$Xip)=@_4args; $code.=<<___; @@ -465,7 +465,7 @@ $code.=<<___; .size gcm_gmult_clmul,.-gcm_gmult_clmul ___ } - + { my ($Xip,$Htbl,$inp,$len)=@_4args; my $Xn="%xmm6"; my $Xhn="%xmm7"; @@ -552,7 +552,7 @@ $code.=<<___; psllq \$57,$Xi # movdqa $Xi,$T2 # pslldq \$8,$Xi - psrldq \$8,$T2 # + psrldq \$8,$T2 # pxor $T1,$Xi pxor $T2,$Xhi # @@ -675,7 +675,7 @@ $code.=<<___; .align 64 .text ___ - + # EXCEPTION_DISPOSITION handler (EXCEPTION_RECORD *rec,ULONG64 frame, # CONTEXT *context,DISPATCHER_CONTEXT *disp) if ($win64) { @@ -802,7 +802,7 @@ se_handler: .byte 0x04,0xa2,0x00,0x00 #sub rsp,0x58 ___ } - + $code =~ s/\`([^\`]*)\`/eval($1)/gem; print $code; diff --git a/lib/libcrypto/objects/obj_dat.pl b/lib/libcrypto/objects/obj_dat.pl index 86bcefb97..e5b384591 100644 --- a/lib/libcrypto/objects/obj_dat.pl +++ b/lib/libcrypto/objects/obj_dat.pl @@ -58,7 +58,7 @@ while () { print "WARNING: Duplicate short name \"$d\"\n"; } - else + else { $snames{$d} = "X"; } $sn{$1}=$d; } @@ -68,7 +68,7 @@ while () { print "WARNING: Duplicate long name \"$d\"\n"; } - else + else { $lnames{$d} = "X"; } $ln{$1}=$d; } @@ -110,7 +110,7 @@ for ($i=0; $i<$n; $i++) $ln=$sn; $ln{$nid{$i}} = $sn; } - + $out ="{"; $out.="\"$sn\""; $out.=","."\"$ln\""; @@ -181,21 +181,21 @@ print OUT <<'EOF'; * This package is an SSL implementation written * by Eric Young (eay@cryptsoft.com). * The implementation was written so as to conform with Netscapes SSL. - * + * * This library is free for commercial and non-commercial use as long as * the following conditions are aheared to. The following conditions * apply to all code found in this distribution, be it the RC4, RSA, * lhash, DES, etc., code; not just the SSL code. The SSL documentation * included with this distribution is covered by the same copyright terms * except that the holder is Tim Hudson (tjh@cryptsoft.com). - * + * * Copyright remains Eric Young's, and as such any Copyright notices in * the code are not to be removed. * If this package is used in a product, Eric Young should be given attribution * as the author of the parts of the library used. * This can be in the form of a textual message at program startup or * in documentation (online or textual) provided with the package. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: @@ -210,10 +210,10 @@ print OUT <<'EOF'; * Eric Young (eay@cryptsoft.com)" * The word 'cryptographic' can be left out if the rouines from the library * being used are not cryptographic related :-). - * 4. If you include any Windows specific code (or a derivative thereof) from + * 4. If you include any Windows specific code (or a derivative thereof) from * the apps directory (application code) you must include an acknowledgement: * "This product includes software written by Tim Hudson (tjh@cryptsoft.com)" - * + * * THIS SOFTWARE IS PROVIDED BY ERIC YOUNG ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -225,7 +225,7 @@ print OUT <<'EOF'; * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. - * + * * The licence and distribution terms for any publically available version or * derivative of this code cannot be changed. i.e. this code cannot simply be * copied and put under another distribution licence diff --git a/lib/libcrypto/objects/objects.pl b/lib/libcrypto/objects/objects.pl index d2bf659d8..265f3b915 100644 --- a/lib/libcrypto/objects/objects.pl +++ b/lib/libcrypto/objects/objects.pl @@ -133,21 +133,21 @@ print OUT <<'EOF'; * This package is an SSL implementation written * by Eric Young (eay@cryptsoft.com). * The implementation was written so as to conform with Netscapes SSL. - * + * * This library is free for commercial and non-commercial use as long as * the following conditions are aheared to. The following conditions * apply to all code found in this distribution, be it the RC4, RSA, * lhash, DES, etc., code; not just the SSL code. The SSL documentation * included with this distribution is covered by the same copyright terms * except that the holder is Tim Hudson (tjh@cryptsoft.com). - * + * * Copyright remains Eric Young's, and as such any Copyright notices in * the code are not to be removed. * If this package is used in a product, Eric Young should be given attribution * as the author of the parts of the library used. * This can be in the form of a textual message at program startup or * in documentation (online or textual) provided with the package. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: @@ -162,10 +162,10 @@ print OUT <<'EOF'; * Eric Young (eay@cryptsoft.com)" * The word 'cryptographic' can be left out if the rouines from the library * being used are not cryptographic related :-). - * 4. If you include any Windows specific code (or a derivative thereof) from + * 4. If you include any Windows specific code (or a derivative thereof) from * the apps directory (application code) you must include an acknowledgement: * "This product includes software written by Tim Hudson (tjh@cryptsoft.com)" - * + * * THIS SOFTWARE IS PROVIDED BY ERIC YOUNG ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -177,7 +177,7 @@ print OUT <<'EOF'; * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. - * + * * The licence and distribution terms for any publically available version or * derivative of this code cannot be changed. i.e. this code cannot simply be * copied and put under another distribution licence diff --git a/lib/libcrypto/objects/objects.txt b/lib/libcrypto/objects/objects.txt index 964a0ec46..5b71048cf 100644 --- a/lib/libcrypto/objects/objects.txt +++ b/lib/libcrypto/objects/objects.txt @@ -578,7 +578,7 @@ id-cmc 19 : id-cmc-responseInfo id-cmc 21 : id-cmc-queryPending id-cmc 22 : id-cmc-popLinkRandom id-cmc 23 : id-cmc-popLinkWitness -id-cmc 24 : id-cmc-confirmCertAcceptance +id-cmc 24 : id-cmc-confirmCertAcceptance # other names id-on 1 : id-on-personalData @@ -1309,7 +1309,7 @@ cryptocom 1 8 1 : id-GostR3410-2001-ParamSet-cc : GOST R 3410-2001 Parameter Se # Definitions for Camellia cipher - ECB, CFB, OFB MODE !Alias ntt-ds 0 3 4401 5 -!Alias camellia ntt-ds 3 1 9 +!Alias camellia ntt-ds 3 1 9 camellia 1 : CAMELLIA-128-ECB : camellia-128-ecb !Cname camellia-128-ofb128 diff --git a/lib/libcrypto/pem/pkcs7.lis b/lib/libcrypto/pem/pkcs7.lis index be90c5d87..b6bcf3fd6 100644 --- a/lib/libcrypto/pem/pkcs7.lis +++ b/lib/libcrypto/pem/pkcs7.lis @@ -1,22 +1,22 @@ -21 0:d=0 hl=2 l= 0 cons: univ: SEQUENCE +21 0:d=0 hl=2 l= 0 cons: univ: SEQUENCE 00 2:d=0 hl=2 l= 9 prim: univ: OBJECT_IDENTIFIER :pkcs-7-signedData 21 13:d=0 hl=2 l= 0 cons: cont: 00 # explicit tag - 21 15:d=0 hl=2 l= 0 cons: univ: SEQUENCE - 00 17:d=0 hl=2 l= 1 prim: univ: INTEGER # version - 20 20:d=0 hl=2 l= 0 cons: univ: SET - 21 22:d=0 hl=2 l= 0 cons: univ: SEQUENCE + 21 15:d=0 hl=2 l= 0 cons: univ: SEQUENCE + 00 17:d=0 hl=2 l= 1 prim: univ: INTEGER # version + 20 20:d=0 hl=2 l= 0 cons: univ: SET + 21 22:d=0 hl=2 l= 0 cons: univ: SEQUENCE 00 24:d=0 hl=2 l= 9 prim: univ: OBJECT_IDENTIFIER :pkcs-7-data - 00 35:d=0 hl=2 l= 0 prim: univ: EOC + 00 35:d=0 hl=2 l= 0 prim: univ: EOC 21 37:d=0 hl=2 l= 0 cons: cont: 00 # cert tag - 20 39:d=0 hl=4 l=545 cons: univ: SEQUENCE - 20 588:d=0 hl=4 l=524 cons: univ: SEQUENCE - 00 1116:d=0 hl=2 l= 0 prim: univ: EOC + 20 39:d=0 hl=4 l=545 cons: univ: SEQUENCE + 20 588:d=0 hl=4 l=524 cons: univ: SEQUENCE + 00 1116:d=0 hl=2 l= 0 prim: univ: EOC 21 1118:d=0 hl=2 l= 0 cons: cont: 01 # crl tag - 20 1120:d=0 hl=4 l=653 cons: univ: SEQUENCE - 20 1777:d=0 hl=4 l=285 cons: univ: SEQUENCE - 00 2066:d=0 hl=2 l= 0 prim: univ: EOC - 21 2068:d=0 hl=2 l= 0 cons: univ: SET # signers - 00 2070:d=0 hl=2 l= 0 prim: univ: EOC - 00 2072:d=0 hl=2 l= 0 prim: univ: EOC - 00 2074:d=0 hl=2 l= 0 prim: univ: EOC -00 2076:d=0 hl=2 l= 0 prim: univ: EOC + 20 1120:d=0 hl=4 l=653 cons: univ: SEQUENCE + 20 1777:d=0 hl=4 l=285 cons: univ: SEQUENCE + 00 2066:d=0 hl=2 l= 0 prim: univ: EOC + 21 2068:d=0 hl=2 l= 0 cons: univ: SET # signers + 00 2070:d=0 hl=2 l= 0 prim: univ: EOC + 00 2072:d=0 hl=2 l= 0 prim: univ: EOC + 00 2074:d=0 hl=2 l= 0 prim: univ: EOC +00 2076:d=0 hl=2 l= 0 prim: univ: EOC diff --git a/lib/libcrypto/perlasm/cbc.pl b/lib/libcrypto/perlasm/cbc.pl index 392f23e14..42d9f8e57 100644 --- a/lib/libcrypto/perlasm/cbc.pl +++ b/lib/libcrypto/perlasm/cbc.pl @@ -8,7 +8,7 @@ # des_cblock (*ivec); # int enc; # -# calls +# calls # des_encrypt((DES_LONG *)tin,schedule,DES_ENCRYPT); # @@ -29,7 +29,7 @@ sub cbc # name is the function name # enc_func and dec_func and the functions to call for encrypt/decrypt # swap is true if byte order needs to be reversed - # iv_off is parameter number for the iv + # iv_off is parameter number for the iv # enc_off is parameter number for the encrypt/decrypt flag # p1,p2,p3 are the offsets for parameters to be passed to the # underlying calls. @@ -116,7 +116,7 @@ sub cbc ############################################################# &set_label("encrypt_loop"); - # encrypt start + # encrypt start # "eax" and "ebx" hold iv (or the last cipher text) &mov("ecx", &DWP(0,$in,"",0)); # load first 4 bytes @@ -209,7 +209,7 @@ sub cbc ############################################################# ############################################################# &set_label("decrypt",1); - # decrypt start + # decrypt start &and($count,0xfffffff8); # The next 2 instructions are only for if the jz is taken &mov("eax", &DWP($data_off+8,"esp","",0)); # get iv[0] diff --git a/lib/libcrypto/perlasm/ppc-xlate.pl b/lib/libcrypto/perlasm/ppc-xlate.pl index a3edd982b..9b67b997e 100755 --- a/lib/libcrypto/perlasm/ppc-xlate.pl +++ b/lib/libcrypto/perlasm/ppc-xlate.pl @@ -19,7 +19,7 @@ my $globl = sub { my $ret; $name =~ s|^[\.\_]||; - + SWITCH: for ($flavour) { /aix/ && do { $name = ".$name"; last; diff --git a/lib/libcrypto/perlasm/readme b/lib/libcrypto/perlasm/readme index a7876bcc9..079013313 100644 --- a/lib/libcrypto/perlasm/readme +++ b/lib/libcrypto/perlasm/readme @@ -61,7 +61,7 @@ So a very simple version of this function could be coded as push(@INC,"perlasm","../../perlasm"); require "x86asm.pl"; - + &asm_init($ARGV[0],"cacl.pl"); &external_label("other"); diff --git a/lib/libcrypto/perlasm/x86_64-xlate.pl b/lib/libcrypto/perlasm/x86_64-xlate.pl index 5dbed2a8c..b5d142d1b 100755 --- a/lib/libcrypto/perlasm/x86_64-xlate.pl +++ b/lib/libcrypto/perlasm/x86_64-xlate.pl @@ -57,7 +57,7 @@ # 9. .init segment is allowed to contain calls to functions only. # a. If function accepts more than 4 arguments *and* >4th argument # is declared as non 64-bit value, do clear its upper part. - + my $flavour = shift; my $output = shift; if ($flavour =~ /\./) { $output = $flavour; undef $flavour; } @@ -141,7 +141,7 @@ my %globals; if ($gas) { if ($self->{op} eq "movz") { # movz is pain... sprintf "%s%s%s",$self->{op},$self->{sz},shift; - } elsif ($self->{op} =~ /^set/) { + } elsif ($self->{op} =~ /^set/) { "$self->{op}"; } elsif ($self->{op} eq "ret") { my $epilogue = ""; @@ -168,7 +168,7 @@ my %globals; $self->{op} .= $self->{sz}; } elsif ($self->{op} eq "call" && $current_segment eq ".CRT\$XCU") { $self->{op} = "\tDQ"; - } + } $self->{op}; } } @@ -608,7 +608,7 @@ my %globals; if ($sz eq "D" && ($current_segment=~/.[px]data/ || $dir eq ".rva")) { $var=~s/([_a-z\$\@][_a-z0-9\$\@]*)/$nasm?"$1 wrt ..imagebase":"imagerel $1"/egi; } $var; - }; + }; $sz =~ tr/bvlrq/BWDDQ/; $self->{value} = "\tD$sz\t"; @@ -618,7 +618,7 @@ my %globals; }; /\.byte/ && do { my @str=split(/,\s*/,$line); map(s/(0b[0-1]+)/oct($1)/eig,@str); - map(s/0x([0-9a-f]+)/0$1h/ig,@str) if ($masm); + map(s/0x([0-9a-f]+)/0$1h/ig,@str) if ($masm); while ($#str>15) { $self->{value}.="DB\t" .join(",",@str[0..15])."\n"; @@ -802,7 +802,7 @@ while($line=<>) { } elsif ($opcode=opcode->re(\$line)) { my $asm = eval("\$".$opcode->mnemonic()); undef @bytes; - + if ((ref($asm) eq 'CODE') && scalar(@bytes=&$asm($line))) { print $gas?".byte\t":"DB\t",join(',',@bytes),"\n"; next; @@ -857,7 +857,8 @@ print "END\n" if ($masm); close STDOUT; - ################################################# + +################################################# # Cross-reference x86_64 ABI "card" # # Unix Win64 @@ -877,7 +878,7 @@ close STDOUT; # %r13 - - # %r14 - - # %r15 - - -# +# # (*) volatile register # (-) preserved by callee # (#) Nth argument, volatile @@ -922,7 +923,8 @@ close STDOUT; # endif # ret # - ################################################# + +################################################# # Win64 SEH, Structured Exception Handling. # # Unlike on Unix systems(*) lack of Win64 stack unwinding information diff --git a/lib/libcrypto/pkcs12/p12_asn.c b/lib/libcrypto/pkcs12/p12_asn.c index a9decccb5..d32b6730f 100644 --- a/lib/libcrypto/pkcs12/p12_asn.c +++ b/lib/libcrypto/pkcs12/p12_asn.c @@ -211,7 +211,7 @@ static const ASN1_ADB_TABLE PKCS12_BAGS_adbtbl[] = { .field_name = "value.x509cert", .item = &ASN1_OCTET_STRING_it, }, - + }, { .value = NID_x509Crl, @@ -222,7 +222,7 @@ static const ASN1_ADB_TABLE PKCS12_BAGS_adbtbl[] = { .field_name = "value.x509crl", .item = &ASN1_OCTET_STRING_it, }, - + }, { .value = NID_sdsiCertificate, @@ -233,7 +233,7 @@ static const ASN1_ADB_TABLE PKCS12_BAGS_adbtbl[] = { .field_name = "value.sdsicert", .item = &ASN1_IA5STRING_it, }, - + }, }; @@ -321,7 +321,7 @@ static const ASN1_ADB_TABLE PKCS12_SAFEBAG_adbtbl[] = { .field_name = "value.keybag", .item = &PKCS8_PRIV_KEY_INFO_it, }, - + }, { .value = NID_pkcs8ShroudedKeyBag, @@ -332,7 +332,7 @@ static const ASN1_ADB_TABLE PKCS12_SAFEBAG_adbtbl[] = { .field_name = "value.shkeybag", .item = &X509_SIG_it, }, - + }, { .value = NID_safeContentsBag, @@ -353,7 +353,7 @@ static const ASN1_ADB_TABLE PKCS12_SAFEBAG_adbtbl[] = { .field_name = "value.bag", .item = &PKCS12_BAGS_it, }, - + }, { .value = NID_crlBag, @@ -364,7 +364,7 @@ static const ASN1_ADB_TABLE PKCS12_SAFEBAG_adbtbl[] = { .field_name = "value.bag", .item = &PKCS12_BAGS_it, }, - + }, { .value = NID_secretBag, @@ -375,7 +375,7 @@ static const ASN1_ADB_TABLE PKCS12_SAFEBAG_adbtbl[] = { .field_name = "value.bag", .item = &PKCS12_BAGS_it, }, - + }, }; diff --git a/lib/libcrypto/pkcs7/pk7_asn1.c b/lib/libcrypto/pkcs7/pk7_asn1.c index 27f410302..c0f8345df 100644 --- a/lib/libcrypto/pkcs7/pk7_asn1.c +++ b/lib/libcrypto/pkcs7/pk7_asn1.c @@ -84,7 +84,7 @@ static const ASN1_ADB_TABLE PKCS7_adbtbl[] = { .field_name = "d.data", .item = &ASN1_OCTET_STRING_NDEF_it, }, - + }, { .value = NID_pkcs7_signed, @@ -95,7 +95,7 @@ static const ASN1_ADB_TABLE PKCS7_adbtbl[] = { .field_name = "d.sign", .item = &PKCS7_SIGNED_it, }, - + }, { .value = NID_pkcs7_enveloped, @@ -106,7 +106,7 @@ static const ASN1_ADB_TABLE PKCS7_adbtbl[] = { .field_name = "d.enveloped", .item = &PKCS7_ENVELOPE_it, }, - + }, { .value = NID_pkcs7_signedAndEnveloped, @@ -117,7 +117,7 @@ static const ASN1_ADB_TABLE PKCS7_adbtbl[] = { .field_name = "d.signed_and_enveloped", .item = &PKCS7_SIGN_ENVELOPE_it, }, - + }, { .value = NID_pkcs7_digest, @@ -128,7 +128,7 @@ static const ASN1_ADB_TABLE PKCS7_adbtbl[] = { .field_name = "d.digest", .item = &PKCS7_DIGEST_it, }, - + }, { .value = NID_pkcs7_encrypted, @@ -139,7 +139,7 @@ static const ASN1_ADB_TABLE PKCS7_adbtbl[] = { .field_name = "d.encrypted", .item = &PKCS7_ENCRYPT_it, }, - + }, }; diff --git a/lib/libcrypto/pkcs7/pk7_doit.c b/lib/libcrypto/pkcs7/pk7_doit.c index d5edaedbd..bec789ec4 100644 --- a/lib/libcrypto/pkcs7/pk7_doit.c +++ b/lib/libcrypto/pkcs7/pk7_doit.c @@ -985,7 +985,7 @@ PKCS7_dataVerify(X509_STORE *cert_store, X509_STORE_CTX *ctx, BIO *bio, return PKCS7_signatureVerify(bio, p7, si, x509); err: - + return ret; } LCRYPTO_ALIAS(PKCS7_dataVerify); diff --git a/lib/libcrypto/rc2/rrc2.doc b/lib/libcrypto/rc2/rrc2.doc index f93ee003d..cd0197251 100644 --- a/lib/libcrypto/rc2/rrc2.doc +++ b/lib/libcrypto/rc2/rrc2.doc @@ -17,19 +17,19 @@ X-Newsreader: NN version 6.5.0 #3 (NOV) Ron Rivest's Cipher No.2 ------------------------ - + Ron Rivest's Cipher No.2 (hereafter referred to as RRC.2, other people may refer to it by other names) is word oriented, operating on a block of 64 bits divided into four 16-bit words, with a key table of 64 words. All data units are little-endian. This functional description of the algorithm is based in the paper "The RC5 Encryption Algorithm" (RC5 is a trademark of RSADSI), using the same general layout, terminology, and pseudocode style. - - + + Notation and RRC.2 Primitive Operations - + RRC.2 uses the following primitive operations: - + 1. Two's-complement addition of words, denoted by "+". The inverse operation, subtraction, is denoted by "-". 2. Bitwise exclusive OR, denoted by "^". @@ -37,141 +37,141 @@ RRC.2 uses the following primitive operations: 4. Bitwise NOT, denoted by "~". 5. A left-rotation of words; the rotation of word x left by y is denoted x <<< y. The inverse operation, right-rotation, is denoted x >>> y. - + These operations are directly and efficiently supported by most processors. - - + + The RRC.2 Algorithm - + RRC.2 consists of three components, a *key expansion* algorithm, an *encryption* algorithm, and a *decryption* algorithm. - - + + Key Expansion - + The purpose of the key-expansion routine is to expand the user's key K to fill the expanded key array S, so S resembles an array of random binary words determined by the user's secret key K. - + Initialising the S-box - + RRC.2 uses a single 256-byte S-box derived from the ciphertext contents of Beale Cipher No.1 XOR'd with a one-time pad. The Beale Ciphers predate modern cryptography by enough time that there should be no concerns about trapdoors hidden in the data. They have been published widely, and the S-box can be easily recreated from the one-time pad values and the Beale Cipher data taken from a standard source. To initialise the S-box: - + for i = 0 to 255 do sBox[ i ] = ( beale[ i ] mod 256 ) ^ pad[ i ] - + The contents of Beale Cipher No.1 and the necessary one-time pad are given as an appendix at the end of this document. For efficiency, implementors may wish to skip the Beale Cipher expansion and store the sBox table directly. - + Expanding the Secret Key to 128 Bytes - + The secret key is first expanded to fill 128 bytes (64 words). The expansion consists of taking the sum of the first and last bytes in the user key, looking up the sum (modulo 256) in the S-box, and appending the result to the key. The operation is repeated with the second byte and new last byte of the key until all 128 bytes have been generated. Note that the following pseudocode treats the S array as an array of 128 bytes rather than 64 words. - + for j = 0 to length-1 do S[ j ] = K[ j ] for j = length to 127 do s[ j ] = sBox[ ( S[ j-length ] + S[ j-1 ] ) mod 256 ]; - + At this point it is possible to perform a truncation of the effective key length to ease the creation of espionage-enabled software products. However since the author cannot conceive why anyone would want to do this, it will not be considered further. - + The final phase of the key expansion involves replacing the first byte of S with the entry selected from the S-box: - + S[ 0 ] = sBox[ S[ 0 ] ] - - + + Encryption - + The cipher has 16 full rounds, each divided into 4 subrounds. Two of the full rounds perform an additional transformation on the data. Note that the following pseudocode treats the S array as an array of 64 words rather than 128 bytes. - + for i = 0 to 15 do j = i * 4; word0 = ( word0 + ( word1 & ~word3 ) + ( word2 & word3 ) + S[ j+0 ] ) <<< 1 word1 = ( word1 + ( word2 & ~word0 ) + ( word3 & word0 ) + S[ j+1 ] ) <<< 2 word2 = ( word2 + ( word3 & ~word1 ) + ( word0 & word1 ) + S[ j+2 ] ) <<< 3 word3 = ( word3 + ( word0 & ~word2 ) + ( word1 & word2 ) + S[ j+3 ] ) <<< 5 - + In addition the fifth and eleventh rounds add the contents of the S-box indexed by one of the data words to another of the data words following the four subrounds as follows: - + word0 = word0 + S[ word3 & 63 ]; word1 = word1 + S[ word0 & 63 ]; word2 = word2 + S[ word1 & 63 ]; word3 = word3 + S[ word2 & 63 ]; - - + + Decryption - + The decryption operation is simply the inverse of the encryption operation. Note that the following pseudocode treats the S array as an array of 64 words rather than 128 bytes. - + for i = 15 downto 0 do j = i * 4; word3 = ( word3 >>> 5 ) - ( word0 & ~word2 ) - ( word1 & word2 ) - S[ j+3 ] word2 = ( word2 >>> 3 ) - ( word3 & ~word1 ) - ( word0 & word1 ) - S[ j+2 ] word1 = ( word1 >>> 2 ) - ( word2 & ~word0 ) - ( word3 & word0 ) - S[ j+1 ] word0 = ( word0 >>> 1 ) - ( word1 & ~word3 ) - ( word2 & word3 ) - S[ j+0 ] - + In addition the fifth and eleventh rounds subtract the contents of the S-box indexed by one of the data words from another one of the data words following the four subrounds as follows: - + word3 = word3 - S[ word2 & 63 ] word2 = word2 - S[ word1 & 63 ] word1 = word1 - S[ word0 & 63 ] word0 = word0 - S[ word3 & 63 ] - - + + Test Vectors - + The following test vectors may be used to test the correctness of an RRC.2 implementation: - + Key: 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 Plain: 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 Cipher: 0x1C, 0x19, 0x8A, 0x83, 0x8D, 0xF0, 0x28, 0xB7 - + Key: 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 Plain: 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 Cipher: 0x21, 0x82, 0x9C, 0x78, 0xA9, 0xF9, 0xC0, 0x74 - + Key: 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 Plain: 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF Cipher: 0x13, 0xDB, 0x35, 0x17, 0xD3, 0x21, 0x86, 0x9E - + Key: 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F Plain: 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 Cipher: 0x50, 0xDC, 0x01, 0x62, 0xBD, 0x75, 0x7F, 0x31 - - + + Appendix: Beale Cipher No.1, "The Locality of the Vault", and One-time Pad for Creating the S-Box - + Beale Cipher No.1. - + 71, 194, 38,1701, 89, 76, 11, 83,1629, 48, 94, 63, 132, 16, 111, 95, 84, 341, 975, 14, 40, 64, 27, 81, 139, 213, 63, 90,1120, 8, 15, 3, 126,2018, 40, 74, 758, 485, 604, 230, 436, 664, 582, 150, 251, 284, 308, 231, @@ -188,9 +188,9 @@ Beale Cipher No.1. 93, 86, 116, 530, 82, 568, 9, 102, 38, 416, 89, 71, 216, 728, 965, 818, 2, 38, 121, 195, 14, 326, 148, 234, 18, 55, 131, 234, 361, 824, 5, 81, 623, 48, 961, 19, 26, 33, 10,1101, 365, 92, 88, 181, 275, 346, 201, 206 - + One-time Pad. - + 158, 186, 223, 97, 64, 145, 190, 190, 117, 217, 163, 70, 206, 176, 183, 194, 146, 43, 248, 141, 3, 54, 72, 223, 233, 153, 91, 210, 36, 131, 244, 161, 105, 120, 113, 191, 113, 86, 19, 245, 213, 221, 43, 27, 242, 157, 73, 213, @@ -207,10 +207,10 @@ One-time Pad. 142, 86, 146, 221, 179, 166, 161, 74, 69, 182, 88, 120, 128, 58, 76, 155, 15, 30, 77, 216, 165, 117, 107, 90, 169, 127, 143, 181, 208, 137, 200, 127, 170, 195, 26, 84, 255, 132, 150, 58, 103, 250, 120, 221, 237, 37, 8, 99 - - + + Implementation - + A non-US based programmer who has never seen any encryption code before will shortly be implementing RRC.2 based solely on this specification and not on knowledge of any other encryption algorithms. Stand by. diff --git a/lib/libcrypto/rc2/version b/lib/libcrypto/rc2/version index 8ca161a61..0205b7fb1 100644 --- a/lib/libcrypto/rc2/version +++ b/lib/libcrypto/rc2/version @@ -18,5 +18,5 @@ So if you are paranoid, used Triple DES, else IDEA. If RC2 does get used more, perhaps more people will look for weaknesses in it. - + diff --git a/lib/libcrypto/rc4/asm/rc4-md5-x86_64.pl b/lib/libcrypto/rc4/asm/rc4-md5-x86_64.pl index 3190e6a8e..50d9f0444 100644 --- a/lib/libcrypto/rc4/asm/rc4-md5-x86_64.pl +++ b/lib/libcrypto/rc4/asm/rc4-md5-x86_64.pl @@ -38,7 +38,7 @@ my ($rc4,$md5)=(1,1); # what to generate? my $D="#" if (!$md5); # if set to "#", MD5 is stitched into RC4(), # but its result is discarded. Idea here is # to be able to use 'openssl speed rc4' for - # benchmarking the stitched subroutine... + # benchmarking the stitched subroutine... my $flavour = shift; my $output = shift; @@ -405,7 +405,7 @@ $code.=<<___ if ($rc4 && (!$md5 || $D)); and \$63,$len # remaining bytes jnz .Loop1 jmp .Ldone - + .align 16 .Loop1: add $TX[0]#b,$YY#b diff --git a/lib/libcrypto/rc4/asm/rc4-parisc.pl b/lib/libcrypto/rc4/asm/rc4-parisc.pl index 6a1a2aad7..1b4116257 100644 --- a/lib/libcrypto/rc4/asm/rc4-parisc.pl +++ b/lib/libcrypto/rc4/asm/rc4-parisc.pl @@ -91,7 +91,7 @@ sub unrolledloopbody { for ($i=0;$i<4;$i++) { $code.=<<___; ldo 1($XX[0]),$XX[1] - `sprintf("$LDX %$TY(%$key),%$dat1") if ($i>0)` + `sprintf("$LDX %$TY(%$key),%$dat1") if ($i>0)` and $mask,$XX[1],$XX[1] $LDX $YY($key),$TY $MKX $YY,$key,$ix @@ -158,7 +158,7 @@ RC4 ldo `2*$SZ`($key),$key ldi 0xff,$mask - ldi 3,$dat0 + ldi 3,$dat0 ldo 1($XX[0]),$XX[0] ; warm up loop and $mask,$XX[0],$XX[0] diff --git a/lib/libcrypto/rc4/asm/rc4-x86_64.pl b/lib/libcrypto/rc4/asm/rc4-x86_64.pl index 0472acce8..c9dfdcb7d 100755 --- a/lib/libcrypto/rc4/asm/rc4-x86_64.pl +++ b/lib/libcrypto/rc4/asm/rc4-x86_64.pl @@ -41,7 +41,7 @@ # April 2005 # -# P4 EM64T core appears to be "allergic" to 64-bit inc/dec. Replacing +# P4 EM64T core appears to be "allergic" to 64-bit inc/dec. Replacing # those with add/sub results in 50% performance improvement of folded # loop... diff --git a/lib/libcrypto/ripemd/asm/rmd-586.pl b/lib/libcrypto/ripemd/asm/rmd-586.pl index e8b2bc2db..85f815e2b 100644 --- a/lib/libcrypto/ripemd/asm/rmd-586.pl +++ b/lib/libcrypto/ripemd/asm/rmd-586.pl @@ -24,7 +24,7 @@ $KL2=0x6ED9EBA1; $KL3=0x8F1BBCDC; $KL4=0xA953FD4E; $KR0=0x50A28BE6; -$KR1=0x5C4DD124; +$KR1=0x5C4DD124; $KR2=0x6D703EF3; $KR3=0x7A6D76E9; @@ -531,28 +531,28 @@ sub ripemd160_block # &mov($tmp2, &wparam(0)); # Moved into last round &mov($tmp1, &DWP( 4,$tmp2,"",0)); # ctx->B - &add($D, $tmp1); + &add($D, $tmp1); &mov($tmp1, &swtmp(16+2)); # $c &add($D, $tmp1); &mov($tmp1, &DWP( 8,$tmp2,"",0)); # ctx->C - &add($E, $tmp1); + &add($E, $tmp1); &mov($tmp1, &swtmp(16+3)); # $d &add($E, $tmp1); &mov($tmp1, &DWP(12,$tmp2,"",0)); # ctx->D - &add($A, $tmp1); + &add($A, $tmp1); &mov($tmp1, &swtmp(16+4)); # $e &add($A, $tmp1); &mov($tmp1, &DWP(16,$tmp2,"",0)); # ctx->E - &add($B, $tmp1); + &add($B, $tmp1); &mov($tmp1, &swtmp(16+0)); # $a &add($B, $tmp1); &mov($tmp1, &DWP( 0,$tmp2,"",0)); # ctx->A - &add($C, $tmp1); + &add($C, $tmp1); &mov($tmp1, &swtmp(16+1)); # $b &add($C, $tmp1); diff --git a/lib/libcrypto/rsa/rsa_oaep.c b/lib/libcrypto/rsa/rsa_oaep.c index c2c3a61da..9266d2a86 100644 --- a/lib/libcrypto/rsa/rsa_oaep.c +++ b/lib/libcrypto/rsa/rsa_oaep.c @@ -7,7 +7,7 @@ * are met: * * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. + * notice, this list of conditions and the following disclaimer. * * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in diff --git a/lib/libcrypto/sha/asm/sha256-586.pl b/lib/libcrypto/sha/asm/sha256-586.pl index 2b05c9606..d400da55a 100644 --- a/lib/libcrypto/sha/asm/sha256-586.pl +++ b/lib/libcrypto/sha/asm/sha256-586.pl @@ -13,7 +13,7 @@ # # Pentium PIII P4 AMD K8 Core2 # gcc 46 36 41 27 26 -# icc 57 33 38 25 23 +# icc 57 33 38 25 23 # x86 asm 40 30 33 20 18 # x86_64 asm(*) - - 21 16 16 # @@ -145,7 +145,7 @@ sub BODY_00_15() { &mov ($Boff,"ebx"); &mov ($Coff,"ecx"); &mov ($Doff,"edi"); - &mov ($E,&DWP(16,"esi")); + &mov ($E,&DWP(16,"esi")); &mov ("ebx",&DWP(20,"esi")); &mov ("ecx",&DWP(24,"esi")); &mov ("edi",&DWP(28,"esi")); diff --git a/lib/libcrypto/sha/asm/sha512-586.pl b/lib/libcrypto/sha/asm/sha512-586.pl index c1d0684e9..a4dea8443 100644 --- a/lib/libcrypto/sha/asm/sha512-586.pl +++ b/lib/libcrypto/sha/asm/sha512-586.pl @@ -334,7 +334,7 @@ if ($sse2) { &BODY_00_15_sse2(1); &set_label("16_79_sse2",16); - #&movq ("mm2",&QWP(8*(9+16-1),"esp")); #prefetched in BODY_00_15 + #&movq ("mm2",&QWP(8*(9+16-1),"esp")); #prefetched in BODY_00_15 #&movq ("mm6",&QWP(8*(9+16-14),"esp")); &movq ("mm1","mm2"); diff --git a/lib/libcrypto/sha/asm/sha512-parisc.pl b/lib/libcrypto/sha/asm/sha512-parisc.pl index 42832e29f..804109705 100755 --- a/lib/libcrypto/sha/asm/sha512-parisc.pl +++ b/lib/libcrypto/sha/asm/sha512-parisc.pl @@ -370,7 +370,7 @@ $code.=<<___ if ($SZ==8 && $SIZE_T==4); ___ @V=( $Ahi, $Alo, $Bhi, $Blo, $Chi, $Clo, $Dhi, $Dlo, - $Ehi, $Elo, $Fhi, $Flo, $Ghi, $Glo, $Hhi, $Hlo) = + $Ehi, $Elo, $Fhi, $Flo, $Ghi, $Glo, $Hhi, $Hlo) = ( "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", "%r8", "%r9","%r10","%r11","%r12","%r13","%r14","%r15","%r16"); $a0 ="%r17"; @@ -421,7 +421,7 @@ $code.=<<___; add $t0,$hlo,$hlo shd $ahi,$alo,$Sigma0[0],$t0 addc $t1,$hhi,$hhi ; h += Sigma1(e) - shd $alo,$ahi,$Sigma0[0],$t1 + shd $alo,$ahi,$Sigma0[0],$t1 add $a0,$hlo,$hlo shd $ahi,$alo,$Sigma0[1],$t2 addc $a1,$hhi,$hhi ; h += Ch(e,f,g) diff --git a/lib/libcrypto/sha/asm/sha512-sparcv9.pl b/lib/libcrypto/sha/asm/sha512-sparcv9.pl index 3c9379944..3f2a153d8 100644 --- a/lib/libcrypto/sha/asm/sha512-sparcv9.pl +++ b/lib/libcrypto/sha/asm/sha512-sparcv9.pl @@ -93,7 +93,7 @@ if ($output =~ /512/) { $locals=0; # X[16] is register resident @X=("%o0","%o1","%o2","%o3","%o4","%o5","%g1","%o7"); - + $A="%l0"; $B="%l1"; $C="%l2"; @@ -244,7 +244,7 @@ $code.=<<___; $SLL $a,`$SZ*8-@Sigma0[1]`,$tmp1 xor $tmp0,$h,$h $SRL $a,@Sigma0[2],$tmp0 - xor $tmp1,$h,$h + xor $tmp1,$h,$h $SLL $a,`$SZ*8-@Sigma0[0]`,$tmp1 xor $tmp0,$h,$h xor $tmp1,$h,$h ! Sigma0(a) diff --git a/lib/libcrypto/stack/safestack.h b/lib/libcrypto/stack/safestack.h index 4f575ba94..df580eb3f 100644 --- a/lib/libcrypto/stack/safestack.h +++ b/lib/libcrypto/stack/safestack.h @@ -7,7 +7,7 @@ * are met: * * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. + * notice, this list of conditions and the following disclaimer. * * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in @@ -65,7 +65,7 @@ /* In C++ we get problems because an explicit cast is needed from (void *) * we use CHECKED_STACK_OF to ensure the correct type is passed in the macros - * below. + * below. */ #define CHECKED_STACK_OF(type, p) \ diff --git a/lib/libcrypto/util/mkstack.pl b/lib/libcrypto/util/mkstack.pl index 77b0ec494..33288b632 100644 --- a/lib/libcrypto/util/mkstack.pl +++ b/lib/libcrypto/util/mkstack.pl @@ -69,7 +69,7 @@ while() { } next if($inside_block != 1); $new_stackfile .= "/* This block of defines is updated by util/mkstack.pl, please do not touch! */"; - + foreach $type_thing (sort @stacklst) { $new_stackfile .= <sc_refcnt > 0) return; - + /* power down until we're opened */ if (ihidev_hid_command(sc, I2C_HID_CMD_SET_POWER, &I2C_HID_POWER_OFF)) { printf("%s: failed to power down\n", sc->sc_dev.dv_xname); diff --git a/sys/dev/ic/bt8xx.h b/sys/dev/ic/bt8xx.h index 67cfc8e5f..71d1fb496 100644 --- a/sys/dev/ic/bt8xx.h +++ b/sys/dev/ic/bt8xx.h @@ -21,7 +21,7 @@ * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Mark Tinguely and Jim Lowe - * 4. The name of the author may not be used to endorse or promote products + * 4. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR diff --git a/sys/dev/ic/gem.c b/sys/dev/ic/gem.c index 42bdeb9cb..15467e053 100644 --- a/sys/dev/ic/gem.c +++ b/sys/dev/ic/gem.c @@ -243,7 +243,7 @@ gem_config(struct gem_softc *sc) mii_flags = MIIF_DOPAUSE; - /* + /* * Look for an external PHY. */ if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { @@ -293,7 +293,7 @@ gem_config(struct gem_softc *sc) MII_OFFSET_ANY, mii_flags); } - /* + /* * Try the external PCS SERDES if we didn't find any MII * devices. */ @@ -785,11 +785,11 @@ gem_init(struct ifnet *ifp) gem_iff(sc); /* step 6 & 7. Program Descriptor Ring Base Addresses */ - bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, + bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, (((uint64_t)GEM_CDTXADDR(sc,0)) >> 32)); bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); - bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, + bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, (((uint64_t)GEM_CDRXADDR(sc,0)) >> 32)); bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); @@ -820,7 +820,7 @@ gem_init(struct ifnet *ifp) /* Encode Receive Descriptor ring size: four possible values */ v = gem_ringsize(GEM_NRXDESC /*XXX*/); /* Enable DMA */ - bus_space_write_4(t, h, GEM_RX_CONFIG, + bus_space_write_4(t, h, GEM_RX_CONFIG, v|(GEM_THRSH_1024<sc_arpcom.ac_enaddr[4]<<8) | sc->sc_arpcom.ac_enaddr[5]); - bus_space_write_4(t, h, GEM_MAC_ADDR1, + bus_space_write_4(t, h, GEM_MAC_ADDR1, (sc->sc_arpcom.ac_enaddr[2]<<8) | sc->sc_arpcom.ac_enaddr[3]); - bus_space_write_4(t, h, GEM_MAC_ADDR2, + bus_space_write_4(t, h, GEM_MAC_ADDR2, (sc->sc_arpcom.ac_enaddr[0]<<8) | sc->sc_arpcom.ac_enaddr[1]); } diff --git a/sys/dev/ic/sili.c b/sys/dev/ic/sili.c index f112277ba..748f017c4 100644 --- a/sys/dev/ic/sili.c +++ b/sys/dev/ic/sili.c @@ -470,7 +470,7 @@ sili_port_intr(struct sili_port *sp, int timeout_slot) /* Extract real NCQ error slot & RFIS from * log page. - */ + */ if (!sili_read_ncq_error(sp, &err_slot, err_port)) { /* got real err_slot */ DPRINTF(SILI_D_VERBOSE, "%s.%d: error slot " diff --git a/sys/dev/isa/ad1848.c b/sys/dev/isa/ad1848.c index c322a3882..dfbdc4f44 100644 --- a/sys/dev/isa/ad1848.c +++ b/sys/dev/isa/ad1848.c @@ -63,7 +63,7 @@ /* * Portions of this code are from the VOXware support for the ad1848 * by Hannu Savolainen - * + * * Portions also supplied from the SoundBlaster driver for NetBSD. */ @@ -238,7 +238,7 @@ ad1848_dump_regs(struct ad1848_softc *sc) { int i; u_char r; - + printf("ad1848 status=%02x", ADREAD(sc, AD1848_STATUS)); printf(" regs: "); for (i = 0; i < 16; i++) { @@ -381,7 +381,7 @@ ad1848_probe(struct ad1848_softc *sc) default: sc->chip_name = "unknown"; DPRINTF(("ad1848: unknown codec version %#02X\n", (tmp1 & 0x8f))); - } + } #if 0 /* @@ -538,7 +538,7 @@ ad1848_attach(struct ad1848_softc *sc) if (ad1848_init_values[i] != 0) { ad_write(sc, i, ad1848_init_values[i]); timeout = AD1848_TIMO; - while (timeout > 0 && + while (timeout > 0 && ADREAD(sc, AD1848_IADDR) & SP_IN_INIT) timeout--; } @@ -587,7 +587,7 @@ struct ad1848_mixerinfo { { SP_LEFT_AUX1_CONTROL, SP_RIGHT_AUX1_CONTROL, AUX_INPUT_ATTEN_BITS, AUX_INPUT_ATTEN_MASK }, { SP_LEFT_OUTPUT_CONTROL, SP_RIGHT_OUTPUT_CONTROL, OUTPUT_ATTEN_BITS, - OUTPUT_ATTEN_MASK }, + OUTPUT_ATTEN_MASK }, { CS_LEFT_LINE_CONTROL, CS_RIGHT_LINE_CONTROL, LINE_INPUT_ATTEN_BITS, LINE_INPUT_ATTEN_MASK }, { CS_MONO_IO_CONTROL, 0, MONO_INPUT_ATTEN_BITS, MONO_INPUT_ATTEN_MASK }, @@ -600,7 +600,7 @@ struct ad1848_mixerinfo { * However, the driver occasionally wants to mute devices (e.g. when changing * sampling rate). These operations should not affect the mute flags. */ -void +void ad1848_mute_channel(struct ad1848_softc *sc, int device, int mute) { u_char reg; @@ -690,7 +690,7 @@ int ad1848_set_rec_gain(struct ad1848_softc *sc, struct ad1848_volume *gp) { u_char reg, gain; - + DPRINTF(("ad1848_set_rec_gain: %d:%d\n", gp->left, gp->right)); sc->rec_gain = *gp; @@ -798,7 +798,7 @@ ad1848_mixer_get_port(struct ad1848_softc *ac, struct ad1848_devmap *map, dev > AD1848_MONITOR_CHANNEL) break; if (cp->un.value.num_channels != 1 && - mixer_channel_info[dev].right_reg == 0) + mixer_channel_info[dev].right_reg == 0) break; error = ad1848_get_device_gain(ac, dev, &vol); if (!error) @@ -843,7 +843,7 @@ ad1848_mixer_get_port(struct ad1848_softc *ac, struct ad1848_devmap *map, return error; } -int +int ad1848_mixer_set_port(struct ad1848_softc *ac, struct ad1848_devmap *map, int cnt, mixer_ctrl_t *cp) { @@ -865,7 +865,7 @@ ad1848_mixer_set_port(struct ad1848_softc *ac, struct ad1848_devmap *map, dev > AD1848_MONITOR_CHANNEL) break; if (cp->un.value.num_channels != 1 && - mixer_channel_info[dev].right_reg == 0) + mixer_channel_info[dev].right_reg == 0) break; ad1848_to_vol(cp, &vol); error = ad1848_set_channel_gain(ac, dev, &vol); @@ -914,7 +914,7 @@ ad1848_set_params(void *addr, int setmode, int usemode, struct audio_params *p, struct ad1848_softc *sc = addr; int error, bits, enc; - DPRINTF(("ad1848_set_params: %d %d %d %ld\n", + DPRINTF(("ad1848_set_params: %d %d %d %ld\n", p->encoding, p->precision, p->channels, p->sample_rate)); enc = p->encoding; @@ -1082,7 +1082,7 @@ ad1848_close(void *addr) /* Disable interrupts */ DPRINTF(("ad1848_close: disable intrs\n")); - ad_write(sc, SP_PIN_CONTROL, + ad_write(sc, SP_PIN_CONTROL, ad_read(sc, SP_PIN_CONTROL) & ~INTERRUPT_ENABLE); DPRINTF(("ad1848_close: disable capture and playback\n")); @@ -1171,7 +1171,7 @@ ad1848_commit_settings(void *addr) ad1848_mute_monitor(sc, 0); mtx_leave(&audio_lock); - + sc->need_commit = 0; return 0; @@ -1395,7 +1395,7 @@ ad1848_intr(void *arg) mtx_enter(&audio_lock); /* Get intr status */ status = ADREAD(sc, AD1848_STATUS); - + #ifdef AUDIO_DEBUG if (ad1848debug > 1) printf("ad1848_intr: mode=%d pintr=%p prun=%d rintr=%p rrun=%d status=0x%x\n", diff --git a/sys/dev/isa/ad1848var.h b/sys/dev/isa/ad1848var.h index cdf2ec03d..2f1d80673 100644 --- a/sys/dev/isa/ad1848var.h +++ b/sys/dev/isa/ad1848var.h @@ -61,7 +61,7 @@ struct ad1848_softc { int sc_irq; /* interrupt */ int sc_drq; /* DMA */ int sc_recdrq; /* record/capture DMA */ - + int sc_flags; #define AD1848_FLAG_32REGS 0x01 /* newer chip (cs4231 compatible) */ @@ -79,10 +79,10 @@ struct ad1848_softc { char *chip_name; int mode; - + u_int precision; /* 8/16 bits */ int channels; - + u_char speed_bits; u_char format_bits; u_char need_commit; @@ -175,7 +175,7 @@ void ad1848_attach(struct ad1848_softc *); int ad1848_open(void *, int); void ad1848_close(void *); - + void ad1848_forceintr(struct ad1848_softc *); int ad1848_set_params(void *, int, int, struct audio_params *, struct audio_params *); diff --git a/sys/dev/isa/aps.c b/sys/dev/isa/aps.c index 93e5069c6..d4c1c63d3 100644 --- a/sys/dev/isa/aps.c +++ b/sys/dev/isa/aps.c @@ -179,7 +179,7 @@ aps_do_io(bus_space_tag_t iot, bus_space_handle_t ioh, DPRINTF(("aps_do_io: CMD: 0x%02x, wmask: 0x%04x, rmask: 0x%04x\n", buf[0], wmask, rmask)); - /* write init byte using arbitration */ + /* write init byte using arbitration */ for (n = 0; n < 100; n++) { stat = bus_space_read_1(iot, ioh, APS_STR3); if (stat & (APS_STR3_OBF3B | APS_STR3_SWMF)) { @@ -449,15 +449,15 @@ aps_refresh_sensor_data(struct aps_softc *sc) sc->sensors[APS_SENSOR_YACCEL].value = sc->aps_data.y_accel; /* convert to micro (mu) degrees */ - temp = sc->aps_data.temp1 * 1000000; + temp = sc->aps_data.temp1 * 1000000; /* convert to kelvin */ - temp += 273150000; + temp += 273150000; sc->sensors[APS_SENSOR_TEMP1].value = temp; /* convert to micro (mu) degrees */ - temp = sc->aps_data.temp2 * 1000000; + temp = sc->aps_data.temp2 * 1000000; /* convert to kelvin */ - temp += 273150000; + temp += 273150000; sc->sensors[APS_SENSOR_TEMP2].value = temp; sc->sensors[APS_SENSOR_XVAR].value = sc->aps_data.x_var; @@ -504,7 +504,7 @@ aps_activate(struct device *self, int act) break; case DVACT_RESUME: /* - * Redo the init sequence on resume, because APS is + * Redo the init sequence on resume, because APS is * as forgetful as it is deaf. */ diff --git a/sys/dev/isa/fd.c b/sys/dev/isa/fd.c index 644a51ba9..f8ea00836 100644 --- a/sys/dev/isa/fd.c +++ b/sys/dev/isa/fd.c @@ -1060,7 +1060,7 @@ fdioctl(dev_t dev, u_long cmd, caddr_t addr, int flag, struct proc *p) case FD_GOPTS: /* get drive options */ *(int *)addr = fd->sc_opts; return 0; - + case FD_SOPTS: /* set drive options */ fd->sc_opts = *(int *)addr; return 0; @@ -1101,7 +1101,7 @@ fdformat(dev_t dev, struct fd_formb *finfo, struct proc *p) bp->b_bcount = sizeof(struct fd_idfield_data) * finfo->fd_formb_nsecs; bp->b_data = (caddr_t)finfo; - + #ifdef DEBUG printf("fdformat: blkno %llx count %lx\n", bp->b_blkno, bp->b_bcount); #endif diff --git a/sys/dev/isa/gus.c b/sys/dev/isa/gus.c index 487bff53a..48be233b0 100644 --- a/sys/dev/isa/gus.c +++ b/sys/dev/isa/gus.c @@ -669,12 +669,12 @@ gus_dmaout_timeout(void *arg) mtx_enter(&audio_lock); SELECT_GUS_REG(iot, ioh2, GUSREG_DMA_CONTROL); bus_space_write_1(iot, ioh2, GUS_DATA_HIGH, 0); - + #if 0 /* XXX we will dmadone below? */ isa_dmaabort(sc->sc_dev.dv_parent, sc->sc_drq); #endif - + gus_dmaout_dointr(sc); mtx_leave(&audio_lock); } diff --git a/sys/dev/isa/hsq.c b/sys/dev/isa/hsq.c index f1e2d2d65..e9509c3a5 100644 --- a/sys/dev/isa/hsq.c +++ b/sys/dev/isa/hsq.c @@ -39,7 +39,7 @@ * * Hostess may be the registered trademark of Comtrol Corp. * WARNING! The information that is below about Hostess family - * serial cards is not based on any information from Comtrol, + * serial cards is not based on any information from Comtrol, * and I DON'T guarantee this information is authentic or right. * For authentic information on Hostess serial cards visit * http://www.comtrol.com @@ -51,7 +51,7 @@ * muxes should work. It works ifine with my mux (it has ti16c750 * UARTs on it, and current com driver detects them as 550A, so i * changed it a bit, to use the power of 750). - * + * * Hostess cards use scratch register of lead UART to control the mux. * When a byte is written to the register it is meant as mask, which * enables/disables interrupts from 1-8 UARTs by setting 0-7 bits to @@ -66,7 +66,7 @@ * * Shitty feature: UER's value upon power up is absolutely random, * so that UARTs can work and can not and you don't understand what's up... - * Thus, we have to set its value to 0x0f to get all four UARTs + * Thus, we have to set its value to 0x0f to get all four UARTs * interrupting, just after we've attached the mux... * * Use it and share my fun! diff --git a/sys/dev/isa/i82365_isasubr.c b/sys/dev/isa/i82365_isasubr.c index fb66caaad..25ab581e1 100644 --- a/sys/dev/isa/i82365_isasubr.c +++ b/sys/dev/isa/i82365_isasubr.c @@ -119,7 +119,7 @@ pcic_isa_bus_width_probe(struct pcic_softc *sc, bus_space_tag_t iot, * range-- apparently missing a bit or more of address lines. * (e.g. CIRRUS_PD672X with Linksys EthernetCard ne2000 clone * in TI TravelMate 5000 -- not clear which is at fault) - * + * * Add a kludge to detect 10 bit wide buses and deal with them, * and also a config file option to override the probe. */ @@ -206,7 +206,7 @@ pcic_isa_chip_intr_establish(pcmcia_chipset_handle_t pch, h->pcmcia->dv_xname); } -void +void pcic_isa_chip_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) { struct pcic_handle *h = (struct pcic_handle *) pch; diff --git a/sys/dev/isa/i82365_isavar.h b/sys/dev/isa/i82365_isavar.h index 7b5f0ec9f..bd0972257 100644 --- a/sys/dev/isa/i82365_isavar.h +++ b/sys/dev/isa/i82365_isavar.h @@ -34,7 +34,7 @@ extern char pcic_isa_intr_list[]; extern int npcic_isa_intr_list; -/* +/* * Establish/disestablish interrupts for PCMCIA functions. */ diff --git a/sys/dev/isa/if_ec.c b/sys/dev/isa/if_ec.c index ee3fa381f..ee735ef4c 100644 --- a/sys/dev/isa/if_ec.c +++ b/sys/dev/isa/if_ec.c @@ -413,7 +413,7 @@ ec_attach(struct device *parent, struct device *self, void *aux) sc->tx_page_start = ELINK2_TX_PAGE_OFFSET_16BIT; sc->rec_page_start = ELINK2_RX_PAGE_OFFSET_16BIT; - sc->rec_page_stop = (memsize >> ED_PAGE_SHIFT) + + sc->rec_page_stop = (memsize >> ED_PAGE_SHIFT) + sc->rec_page_start; sc->mem_ring = sc->mem_start; } else { @@ -657,7 +657,7 @@ ec_write_mbuf(struct dp8390_softc *sc, struct mbuf *m, int buf) if (esc->sc_16bitp) bus_space_write_1(asict, asich, ELINK2_GACFR, ELINK2_GACFR_RSEL | ELINK2_GACFR_MBS0); - + return (savelen); } diff --git a/sys/dev/isa/if_eg.c b/sys/dev/isa/if_eg.c index 686eb1f2b..525108356 100644 --- a/sys/dev/isa/if_eg.c +++ b/sys/dev/isa/if_eg.c @@ -84,8 +84,8 @@ struct eg_softc { bus_space_tag_t sc_bst; bus_space_handle_t sc_bsh; struct arpcom sc_arpcom; /* Ethernet common part */ - u_char eg_rom_major; /* Cards ROM version (major number) */ - u_char eg_rom_minor; /* Cards ROM version (minor number) */ + u_char eg_rom_major; /* Cards ROM version (major number) */ + u_char eg_rom_minor; /* Cards ROM version (minor number) */ short eg_ram; /* Amount of RAM on the card */ u_char eg_pcb[64]; /* Primary Command Block buffer */ u_char eg_incount; /* Number of buffers currently used */ @@ -125,12 +125,12 @@ static int egreadPCB(struct eg_softc *); /* * Support stuff */ - + static __inline void egprintpcb(struct eg_softc *sc) { int i; - + for (i = 0; i < sc->eg_pcb[1] + 2; i++) DPRINTF(("pcb[%2d] = %x\n", i, sc->eg_pcb[i])); } @@ -153,7 +153,7 @@ egoutPCB(struct eg_softc *sc, u_char b) DPRINTF(("egoutPCB failed\n")); return (1); } - + static int egreadPCBstat(struct eg_softc *sc, u_char statb) { @@ -163,11 +163,11 @@ egreadPCBstat(struct eg_softc *sc, u_char statb) for (i=0; i < 5000; i++) { if ((bus_space_read_1(bst, bsh, EG_STATUS) & EG_PCB_STAT) != - EG_PCB_NULL) + EG_PCB_NULL) break; delay(10); } - if ((bus_space_read_1(bst, bsh, EG_STATUS) & EG_PCB_STAT) == statb) + if ((bus_space_read_1(bst, bsh, EG_STATUS) & EG_PCB_STAT) == statb) return (0); return (1); } @@ -188,7 +188,7 @@ egreadPCBready(struct eg_softc *sc) bus_space_read_1(bst, bsh, EG_STATUS))); return (1); } - + static int egwritePCB(struct eg_softc *sc) { @@ -204,7 +204,7 @@ egwritePCB(struct eg_softc *sc) len = sc->eg_pcb[1] + 2; for (i = 0; i < len; i++) egoutPCB(sc, sc->eg_pcb[i]); - + for (i=0; i < 4000; i++) { if (bus_space_read_1(bst, bsh, EG_STATUS) & EG_STAT_HCRE) break; @@ -220,8 +220,8 @@ egwritePCB(struct eg_softc *sc) if (egreadPCBstat(sc, EG_PCB_ACCEPT)) return (1); return (0); -} - +} + static int egreadPCB(struct eg_softc *sc) { @@ -229,7 +229,7 @@ egreadPCB(struct eg_softc *sc) bus_space_handle_t bsh = sc->sc_bsh; int i; u_char b; - + bus_space_write_1(bst, bsh, EG_CONTROL, (bus_space_read_1(bst, bsh, EG_CONTROL) & ~EG_PCB_STAT) | EG_PCB_NULL); @@ -240,7 +240,7 @@ egreadPCB(struct eg_softc *sc) return (1); sc->eg_pcb[0] = bus_space_read_1(bst, bsh, EG_COMMAND); - + if (egreadPCBready(sc)) return (1); @@ -250,7 +250,7 @@ egreadPCB(struct eg_softc *sc) DPRINTF(("len %d too large\n", sc->eg_pcb[1])); return (1); } - + for (i = 0; i < sc->eg_pcb[1]; i++) { if (egreadPCBready(sc)) return (1); @@ -270,7 +270,7 @@ egreadPCB(struct eg_softc *sc) EG_PCB_ACCEPT); return (0); -} +} /* * Real stuff @@ -289,7 +289,7 @@ egprobe(struct device *parent, void *match, void *aux) DPRINTF(("Weird iobase %x\n", ia->ia_iobase)); return (0); } - + if (bus_space_map(bst, ia->ia_iobase, EG_IO_PORTS, 0, &bsh)) { DPRINTF(("%s: can't map i/o space\n", sc->sc_dev.dv_xname)); return (0); @@ -297,12 +297,12 @@ egprobe(struct device *parent, void *match, void *aux) sc->sc_bsh = bsh; /* hard reset card */ - bus_space_write_1(bst, bsh, EG_CONTROL, EG_CTL_RESET); + bus_space_write_1(bst, bsh, EG_CONTROL, EG_CTL_RESET); bus_space_write_1(bst, bsh, EG_CONTROL, 0); for (i = 0; i < 5000; i++) { delay(1000); if ((bus_space_read_1(bst, bsh, EG_STATUS) & EG_PCB_STAT) == - EG_PCB_NULL) + EG_PCB_NULL) break; } if ((bus_space_read_1(bst, bsh, EG_STATUS) & EG_PCB_STAT) != @@ -314,7 +314,7 @@ egprobe(struct device *parent, void *match, void *aux) sc->eg_pcb[1] = 0; if (egwritePCB(sc) != 0) goto lose; - + if (egreadPCB(sc) != 0) { egprintpcb(sc); goto lose; @@ -328,7 +328,7 @@ egprobe(struct device *parent, void *match, void *aux) sc->eg_rom_major = sc->eg_pcb[3]; sc->eg_rom_minor = sc->eg_pcb[2]; sc->eg_ram = sc->eg_pcb[6] | (sc->eg_pcb[7] << 8); - + ia->ia_iosize = 0x08; ia->ia_msize = 0; bus_space_unmap(bst, bsh, EG_IO_PORTS); @@ -347,7 +347,7 @@ egattach(struct device *parent, struct device *self, void *aux) bus_space_tag_t bst = sc->sc_bst = ia->ia_iot; bus_space_handle_t bsh; struct ifnet *ifp = &sc->sc_arpcom.ac_if; - + if (bus_space_map(bst, ia->ia_iobase, EG_IO_PORTS, 0, &bsh)) { printf("%s: can't map i/o space\n", sc->sc_dev.dv_xname); return; @@ -361,7 +361,7 @@ egattach(struct device *parent, struct device *self, void *aux) if (egwritePCB(sc) != 0) { DPRINTF(("write error\n")); return; - } + } if (egreadPCB(sc) != 0) { DPRINTF(("read error\n")); egprintpcb(sc); @@ -369,7 +369,7 @@ egattach(struct device *parent, struct device *self, void *aux) } /* check Get station address response */ - if (sc->eg_pcb[0] != EG_RSP_GETEADDR || sc->eg_pcb[1] != 0x06) { + if (sc->eg_pcb[0] != EG_RSP_GETEADDR || sc->eg_pcb[1] != 0x06) { DPRINTF(("parse error\n")); egprintpcb(sc); return; @@ -404,11 +404,11 @@ egattach(struct device *parent, struct device *self, void *aux) ifp->if_ioctl = egioctl; ifp->if_watchdog = egwatchdog; ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX; - + /* Now we can attach the interface. */ if_attach(ifp); ether_ifattach(ifp); - + sc->sc_ih = isa_intr_establish(ia->ia_ic, ia->ia_irq, IST_EDGE, IPL_NET, egintr, sc, sc->sc_dev.dv_xname); } @@ -503,7 +503,7 @@ loop: m0 = ifq_dequeue(&ifp->if_snd); if (m0 == NULL) return; - + ifq_set_oactive(&ifp->if_snd); /* We need to use m->m_pkthdr.len, so require the header */ @@ -542,8 +542,8 @@ loop: /* set direction bit: host -> adapter */ bus_space_write_1(bst, bsh, EG_CONTROL, - bus_space_read_1(bst, bsh, EG_CONTROL) & ~EG_CTL_DIR); - + bus_space_read_1(bst, bsh, EG_CONTROL) & ~EG_CTL_DIR); + for (ptr = (u_short *)sc->eg_outbuf; len > 0; len -= 2) { bus_space_write_2(bst, bsh, EG_DATA, *ptr++); for (i = 10000; i != 0; i--) { @@ -556,7 +556,7 @@ loop: break; } } - + m_freem(m0); } @@ -576,11 +576,11 @@ egintr(void *arg) switch (sc->eg_pcb[0]) { case EG_RSP_RECVPACKET: len = sc->eg_pcb[6] | (sc->eg_pcb[7] << 8); - + /* Set direction bit : Adapter -> host */ bus_space_write_1(bst, bsh, EG_CONTROL, bus_space_read_1(bst, bsh, EG_CONTROL) | - EG_CTL_DIR); + EG_CTL_DIR); for (ptr = (u_short *)sc->eg_inbuf; len > 0; len -= 2) { for (i = 10000; i != 0; i--) { @@ -630,7 +630,7 @@ egintr(void *arg) DPRINTF(("overrun errors %d\n", *(short *)&sc->eg_pcb[16])); break; - + default: DPRINTF(("egintr: Unknown response %x??\n", sc->eg_pcb[0])); @@ -792,6 +792,6 @@ egstop(register struct eg_softc *sc) { bus_space_tag_t bst = sc->sc_bst; bus_space_handle_t bsh = sc->sc_bsh; - + bus_space_write_1(bst, bsh, EG_CONTROL, 0); } diff --git a/sys/dev/isa/if_egreg.h b/sys/dev/isa/if_egreg.h index 24f6492c9..cb00bb8d6 100644 --- a/sys/dev/isa/if_egreg.h +++ b/sys/dev/isa/if_egreg.h @@ -66,7 +66,7 @@ /* * Host Status Register bits - * EG_STAT_HRDY - Data Register ready + * EG_STAT_HRDY - Data Register ready * EG_STAT_HCRE - Host Command Register empty * EG_STAT_ACRF - Adapter Command register full * EG_STAT_DIR - Direction flag, 0 = host -> adapter, 1 = adapter -> host @@ -86,7 +86,7 @@ #define EG_STAT_ASF1 0x01 #define EG_PCB_NULL 0x00 -#define EG_PCB_ACCEPT 0x01 +#define EG_PCB_ACCEPT 0x01 #define EG_PCB_REJECT 0x02 #define EG_PCB_DONE 0x03 #define EG_PCB_STAT 0x03 diff --git a/sys/dev/isa/if_el.c b/sys/dev/isa/if_el.c index e99011002..43d0b4564 100644 --- a/sys/dev/isa/if_el.c +++ b/sys/dev/isa/if_el.c @@ -327,7 +327,7 @@ elstart(struct ifnet *ifp) for (i = 0; i < ETHER_MIN_LEN - ETHER_CRC_LEN - m0->m_pkthdr.len; i++) outb(iobase+EL_BUF, 0); - + m_freem(m0); /* Now transmit the datagram. */ diff --git a/sys/dev/isa/if_ex.c b/sys/dev/isa/if_ex.c index d3341244f..60ae2185d 100644 --- a/sys/dev/isa/if_ex.c +++ b/sys/dev/isa/if_ex.c @@ -46,7 +46,7 @@ #include #include -#include +#include #include #include @@ -79,24 +79,24 @@ struct ex_softc { int iobase; /* I/O base address. */ u_short irq_no; /* IRQ number. */ u_int mem_size; /* Total memory size, in bytes. */ - u_int rx_mem_size; /* Rx memory size (by default, first 3/4 of + u_int rx_mem_size; /* Rx memory size (by default, first 3/4 of total memory). */ - u_int rx_lower_limit, + u_int rx_lower_limit, rx_upper_limit; /* Lower and upper limits of receive buffer. */ u_int rx_head; /* Head of receive ring buffer. */ - u_int tx_mem_size; /* Tx memory size (by default, last quarter of + u_int tx_mem_size; /* Tx memory size (by default, last quarter of total memory). */ - u_int tx_lower_limit, + u_int tx_lower_limit, tx_upper_limit; /* Lower and upper limits of transmit buffer. */ u_int tx_head, tx_tail; /* Head and tail of transmit ring buffer. */ - u_int tx_last; /* Pointer to beginning of last frame in the + u_int tx_last; /* Pointer to beginning of last frame in the chain. */ bus_space_tag_t sc_iot; /* ISA i/o space tag */ bus_space_handle_t sc_ioh; /* ISA i/o space handle */ void *sc_ih; /* Device interrupt handler */ }; -static char irq2eemap[] = { -1, -1, 0, 1, -1, 2, -1, -1, -1, 0, 3, 4, -1, -1, +static char irq2eemap[] = { -1, -1, 0, 1, -1, 2, -1, -1, -1, 0, 3, 4, -1, -1, -1, -1 }; static u_char ee2irqmap[] = { 9, 3, 5, 10, 11, 0, 0, 0 }; @@ -145,7 +145,7 @@ struct cfdriver ex_cd = { bus_space_write_multi_2((sc)->sc_iot, (sc)->sc_ioh, (off), \ (u_int16_t *)(addr), (count)) -int +int ex_look_for_card(struct isa_attach_args *ia, struct ex_softc *sc) { int count1, count2; @@ -165,7 +165,7 @@ ex_look_for_card(struct isa_attach_args *ia, struct ex_softc *sc) return(0); } -int +int ex_probe(struct device *parent, void *match, void *aux) { struct ex_softc *sc = match; @@ -183,7 +183,7 @@ ex_probe(struct device *parent, void *match, void *aux) if (!ex_look_for_card(ia, sc)) { bus_space_unmap(sc->sc_iot, sc->sc_ioh, EX_IOSIZE); - return(0); + return(0); } } else return(0); @@ -200,7 +200,7 @@ ex_probe(struct device *parent, void *match, void *aux) * Fill in several fields of the softc structure: * - I/O base address. * - Hardware Ethernet address. - * - IRQ number (if not supplied in config file, read it from + * - IRQ number (if not supplied in config file, read it from * EEPROM). */ sc->iobase = ia->ia_iobase; @@ -283,7 +283,7 @@ ex_attach(struct device *parent, struct device *self, void *aux) DODEBUG(Start_End, printf("ex_attach: finish\n");); } -void +void ex_init(struct ex_softc *sc) { struct ifnet *ifp = &sc->arpcom.ac_if; @@ -317,7 +317,7 @@ ex_init(struct ex_softc *sc) RX_CRC_InMem); CSR_WRITE_1(sc, REG3, (CSR_READ_1(sc, REG3) & 0x3f)); CSR_WRITE_1(sc, CMD_REG, Bank1_Sel); - CSR_WRITE_1(sc, INT_NO_REG, (CSR_READ_1(sc, INT_NO_REG) & 0xf8) | + CSR_WRITE_1(sc, INT_NO_REG, (CSR_READ_1(sc, INT_NO_REG) & 0xf8) | irq2eemap[sc->irq_no]); /* @@ -372,7 +372,7 @@ ex_init(struct ex_softc *sc) DODEBUG(Start_End, printf("ex_init: finish\n");); } -void +void ex_start(struct ifnet *ifp) { struct ex_softc *sc = ifp->if_softc; @@ -393,10 +393,10 @@ ex_start(struct ifnet *ifp) break; /* - * Ensure there is enough free transmit buffer space for this - * packet, including its header. Note: the header cannot wrap - * around the end of the transmit buffer and must be kept - * together, so we allow space for twice the length of the + * Ensure there is enough free transmit buffer space for this + * packet, including its header. Note: the header cannot wrap + * around the end of the transmit buffer and must be kept + * together, so we allow space for twice the length of the * header, just in case. */ for (len = 0, m = opkt; m != NULL; m = m->m_next) @@ -415,29 +415,29 @@ ex_start(struct ifnet *ifp) if (avail >= len + XMT_HEADER_LEN) { ifq_deq_commit(&ifp->if_snd, opkt); -#ifdef EX_PSA_INTR +#ifdef EX_PSA_INTR /* * Disable rx and tx interrupts, to avoid corruption of - * the host address register by interrupt service - * routines. XXX Is this necessary with splnet() + * the host address register by interrupt service + * routines. XXX Is this necessary with splnet() * enabled? */ CSR_WRITE_2(sc, MASK_REG, All_Int); #endif - /* - * Compute the start and end addresses of this frame + /* + * Compute the start and end addresses of this frame * in the tx buffer. */ dest = sc->tx_tail; next = dest + len; if (next > sc->tx_upper_limit) { - if ((sc->tx_upper_limit + 2 - sc->tx_tail) <= + if ((sc->tx_upper_limit + 2 - sc->tx_tail) <= XMT_HEADER_LEN) { dest = sc->tx_lower_limit; next = dest + len; } else - next = sc->tx_lower_limit + next - + next = sc->tx_lower_limit + next - sc->tx_upper_limit - 2; } @@ -450,8 +450,8 @@ ex_start(struct ifnet *ifp) CSR_WRITE_2(sc, IO_PORT_REG, data_len); /* - * Output the packet data to the card. Ensure all - * transfers are 16-bit wide, even if individual mbufs + * Output the packet data to the card. Ensure all + * transfers are 16-bit wide, even if individual mbufs * have odd length. */ @@ -461,29 +461,29 @@ ex_start(struct ifnet *ifp) tmp16[1] = *(mtod(m, caddr_t)); CSR_WRITE_MULTI_2(sc, IO_PORT_REG, tmp16, 1); } - CSR_WRITE_MULTI_2(sc, IO_PORT_REG, mtod(m, caddr_t) + CSR_WRITE_MULTI_2(sc, IO_PORT_REG, mtod(m, caddr_t) + i, (m->m_len - i) / 2); if ((i = (m->m_len - i) & 1)) - tmp16[0] = *(mtod(m, caddr_t) + + tmp16[0] = *(mtod(m, caddr_t) + m->m_len - 1); } if (i) CSR_WRITE_MULTI_2(sc, IO_PORT_REG, tmp16, 1); /* - * If there were other frames chained, update the + * If there were other frames chained, update the * chain in the last one. */ if (sc->tx_head != sc->tx_tail) { if (sc->tx_tail != dest) { - CSR_WRITE_2(sc, HOST_ADDR_REG, + CSR_WRITE_2(sc, HOST_ADDR_REG, sc->tx_last + XMT_Chain_Point); CSR_WRITE_2(sc, IO_PORT_REG, dest); } - CSR_WRITE_2(sc, HOST_ADDR_REG, sc->tx_last + + CSR_WRITE_2(sc, HOST_ADDR_REG, sc->tx_last + XMT_Byte_Count); i = CSR_READ_2(sc, IO_PORT_REG); - CSR_WRITE_2(sc, HOST_ADDR_REG, sc->tx_last + + CSR_WRITE_2(sc, HOST_ADDR_REG, sc->tx_last + XMT_Byte_Count); CSR_WRITE_2(sc, IO_PORT_REG, i | Ch_bit); } @@ -526,7 +526,7 @@ ex_start(struct ifnet *ifp) DODEBUG(Start_End, printf("ex_start: finish\n");); } -void +void ex_stop(struct ex_softc *sc) { DODEBUG(Start_End, printf("ex_stop: start\n");); @@ -543,8 +543,8 @@ ex_stop(struct ex_softc *sc) CSR_WRITE_1(sc, CMD_REG, Bank0_Sel); CSR_WRITE_1(sc, CMD_REG, Rcv_Stop); sc->tx_head = sc->tx_tail = sc->tx_lower_limit; - sc->tx_last = 0; /* XXX I think these two lines are not necessary, - because ex_init will always be called again + sc->tx_last = 0; /* XXX I think these two lines are not necessary, + because ex_init will always be called again to reinit the interface. */ CSR_WRITE_1(sc, MASK_REG, All_Int); CSR_WRITE_1(sc, STATUS_REG, All_Int); @@ -555,7 +555,7 @@ ex_stop(struct ex_softc *sc) } -int +int ex_intr(void *arg) { struct ex_softc *sc = arg; @@ -567,7 +567,7 @@ ex_intr(void *arg) #ifdef EX_DEBUG if (++exintr_count != 1) - printf("WARNING: nested interrupt (%d). Mail the author.\n", + printf("WARNING: nested interrupt (%d). Mail the author.\n", exintr_count); #endif @@ -600,7 +600,7 @@ ex_intr(void *arg) return handled; } -void +void ex_tx_intr(struct ex_softc *sc) { struct ifnet *ifp = &sc->arpcom.ac_if; @@ -632,7 +632,7 @@ ex_tx_intr(struct ex_softc *sc) DODEBUG(Start_End, printf("ex_tx_intr: finish\n");); } -void +void ex_rx_intr(struct ex_softc *sc) { struct ifnet *ifp = &sc->arpcom.ac_if; @@ -674,20 +674,20 @@ ex_rx_intr(struct ex_softc *sc) } m->m_len = min(m->m_len, pkt_len); /* - * NOTE: I'm assuming that all mbufs + * NOTE: I'm assuming that all mbufs * allocated are of even length, except - * for the last one in an odd-length + * for the last one in an odd-length * packet. */ CSR_READ_MULTI_2(sc, IO_PORT_REG, mtod(m, caddr_t), m->m_len / 2); if (m->m_len & 1) - *(mtod(m, caddr_t) + - m->m_len - 1) = + *(mtod(m, caddr_t) + + m->m_len - 1) = CSR_READ_1(sc, IO_PORT_REG); pkt_len -= m->m_len; if (pkt_len > 0) { - MGET(m->m_next, M_DONTWAIT, + MGET(m->m_next, M_DONTWAIT, MT_DATA); if (m->m_next == NULL) { m_freem(ipkt); @@ -700,7 +700,7 @@ ex_rx_intr(struct ex_softc *sc) } #ifdef EX_DEBUG if (debug_mask & Rcvd_Pkts) { - if ((eh->ether_dhost[5] != 0xff) || + if ((eh->ether_dhost[5] != 0xff) || (eh->ether_dhost[0] != 0xff)) { printf("Receive packet with %d data bytes: %6D -> ", QQQ, eh->ether_shost, ":"); printf("%6D\n", eh->ether_dhost, ":"); @@ -722,9 +722,9 @@ ex_rx_intr(struct ex_softc *sc) if_input(ifp, &ml); DODEBUG(Start_End, printf("ex_rx_intr: finish\n");); -} +} -int +int ex_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) { struct ex_softc *sc = ifp->if_softc; @@ -811,7 +811,7 @@ ex_setmulti(struct ex_softc *sc) /* Borrow space from TX buffer; this should be safe * as this is only called from ex_init */ - + CSR_WRITE_2(sc, HOST_ADDR_REG, sc->tx_lower_limit); CSR_WRITE_2(sc, IO_PORT_REG, MC_Setup_CMD); CSR_WRITE_2(sc, IO_PORT_REG, 0); @@ -863,13 +863,13 @@ ex_setmulti(struct ex_softc *sc) } } -void +void ex_reset(struct ex_softc *sc) { int s; DODEBUG(Start_End, printf("ex_reset: start\n");); - + s = splnet(); ex_stop(sc); ex_init(sc); @@ -878,7 +878,7 @@ ex_reset(struct ex_softc *sc) DODEBUG(Start_End, printf("ex_reset: finish\n");); } -void +void ex_watchdog(struct ifnet *ifp) { struct ex_softc *sc = ifp->if_softc; @@ -936,7 +936,7 @@ ex_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) ifmr->ifm_active = ex_get_media(sc); } -u_short +u_short ex_eeprom_read(struct ex_softc *sc, int location) { int i; @@ -947,7 +947,7 @@ ex_eeprom_read(struct ex_softc *sc, int location) CSR_WRITE_1(sc, CMD_REG, Bank2_Sel); CSR_WRITE_1(sc, EEPROM_REG, EECS); for (i = 8; i >= 0; i--) { - short outval = (read_cmd & (1 << i)) ? ctrl_val | EEDI : + short outval = (read_cmd & (1 << i)) ? ctrl_val | EEDI : ctrl_val; CSR_WRITE_1(sc, EEPROM_REG, outval); CSR_WRITE_1(sc, EEPROM_REG, outval | EESK); diff --git a/sys/dev/isa/if_ie.c b/sys/dev/isa/if_ie.c index 38aba1606..bd96edc89 100644 --- a/sys/dev/isa/if_ie.c +++ b/sys/dev/isa/if_ie.c @@ -578,7 +578,7 @@ ee16_probe(struct ie_softc *sc, struct isa_attach_args *ia) } if (board_id != IEE16_ID) - return 0; + return 0; /* need sc->sc_iobase for ee16_read_eeprom */ sc->sc_iobase = ia->ia_iobase; @@ -588,10 +588,10 @@ ee16_probe(struct ie_softc *sc, struct isa_attach_args *ia) * If ia->maddr == MADDRUNK, use value in eeprom location 6. * * The shared RAM location on the EE16 is encoded into bits - * 3-7 of EEPROM location 6. We zero the upper byte, and + * 3-7 of EEPROM location 6. We zero the upper byte, and * shift the 5 bits right 3. The resulting number tells us * the RAM location. Because the EE16 supports either 16k or 32k - * of shared RAM, we only worry about the 32k locations. + * of shared RAM, we only worry about the 32k locations. * * NOTE: if a 64k EE16 exists, it should be added to this switch. * then the ia->ia_msize would need to be set per case statement. @@ -603,7 +603,7 @@ ee16_probe(struct ie_softc *sc, struct isa_attach_args *ia) * 0x0C 0x8000 0xD4000 * 0x18 0x8000 0xD8000 * - */ + */ if ((ia->ia_maddr == MADDRUNK) || (ia->ia_msize == 0)) { i = (ee16_read_eeprom(sc, 6) & 0x00ff ) >> 3; @@ -624,27 +624,27 @@ ee16_probe(struct ie_softc *sc, struct isa_attach_args *ia) return 0 ; break; /* NOTREACHED */ } - ia->ia_msize = 0x8000; + ia->ia_msize = 0x8000; } /* need to set these after checking for MADDRUNK */ sc->sc_maddr = ISA_HOLE_VADDR(ia->ia_maddr); - sc->sc_msize = ia->ia_msize; + sc->sc_msize = ia->ia_msize; /* need to put the 586 in RESET, and leave it */ - outb( PORT + IEE16_ECTRL, IEE16_RESET_586); + outb( PORT + IEE16_ECTRL, IEE16_RESET_586); /* read the eeprom and checksum it, should == IEE16_ID */ for(i=0 ; i< 0x40 ; i++) checksum += ee16_read_eeprom(sc, i); if (checksum != IEE16_ID) - return 0; + return 0; /* * Size and test the memory on the board. The size of the memory * can be one of 16k, 32k, 48k or 64k. It can be located in the - * address range 0xC0000 to 0xEFFFF on 16k boundaries. + * address range 0xC0000 to 0xEFFFF on 16k boundaries. * * If the size does not match the passed in memory allocation size * issue a warning, but continue with the minimum of the two sizes. @@ -1924,7 +1924,7 @@ ieinit(struct ie_softc *sc) bart_config &= ~IEE16_BART_LOOPBACK; bart_config |= IEE16_BART_MCS16_TEST; /* inb doesn't get bit! */ outb(PORT + IEE16_CONFIG, bart_config); - ee16_interrupt_enable(sc); + ee16_interrupt_enable(sc); ee16_chan_attn(sc); } } diff --git a/sys/dev/isa/if_lc_isa.c b/sys/dev/isa/if_lc_isa.c index 6e11f41ac..7151b989d 100644 --- a/sys/dev/isa/if_lc_isa.c +++ b/sys/dev/isa/if_lc_isa.c @@ -174,7 +174,7 @@ lemac_isa_probe(struct device *parent, void *match, void *aux) snprintf(sc.sc_dv.dv_xname, sizeof sc.sc_dv.dv_xname, "%s%d", lc_cd.cd_name, cf->cf_unit); - + return (lemac_isa_find(&sc, ia, 0)); } diff --git a/sys/dev/isa/if_levar.h b/sys/dev/isa/if_levar.h index e016e55ec..01ececb1b 100644 --- a/sys/dev/isa/if_levar.h +++ b/sys/dev/isa/if_levar.h @@ -56,5 +56,5 @@ struct le_softc { }; void le_isa_wrcsr(struct lance_softc *, uint16_t, uint16_t); -uint16_t le_isa_rdcsr(struct lance_softc *, uint16_t); +uint16_t le_isa_rdcsr(struct lance_softc *, uint16_t); int le_isa_intredge(void *); diff --git a/sys/dev/isa/if_ne_isa.c b/sys/dev/isa/if_ne_isa.c index 846f2f2bc..513977afb 100644 --- a/sys/dev/isa/if_ne_isa.c +++ b/sys/dev/isa/if_ne_isa.c @@ -62,7 +62,7 @@ #include #include -#include +#include #include diff --git a/sys/dev/isa/if_we.c b/sys/dev/isa/if_we.c index 22bfa46de..4b09e2718 100644 --- a/sys/dev/isa/if_we.c +++ b/sys/dev/isa/if_we.c @@ -812,19 +812,19 @@ we_params(bus_space_tag_t asict, bus_space_handle_t asich, type = bus_space_read_1(asict, asich, WE_CARD_ID); switch (type) { - case WE_TYPE_WD8003S: - typestr = "WD8003S"; + case WE_TYPE_WD8003S: + typestr = "WD8003S"; break; case WE_TYPE_WD8003E: typestr = "WD8003E"; break; - case WE_TYPE_WD8003EB: + case WE_TYPE_WD8003EB: typestr = "WD8003EB"; break; case WE_TYPE_WD8003W: typestr = "WD8003W"; break; - case WE_TYPE_WD8013EBT: + case WE_TYPE_WD8013EBT: typestr = "WD8013EBT"; memsize = 16384; is16bit = 1; diff --git a/sys/dev/isa/isapnpdebug.c b/sys/dev/isa/isapnpdebug.c index 9b463666a..cad3d79b2 100644 --- a/sys/dev/isa/isapnpdebug.c +++ b/sys/dev/isa/isapnpdebug.c @@ -182,7 +182,7 @@ isapnp_print_dep_start(const char *str, const u_char pref) case ISAPNP_DEP_PREFERRED: printf("preferred\n"); break; - + case ISAPNP_DEP_ACCEPTABLE: printf("acceptable\n"); break; diff --git a/sys/dev/isa/isapnpres.c b/sys/dev/isa/isapnpres.c index 5c5a82beb..da8b52810 100644 --- a/sys/dev/isa/isapnpres.c +++ b/sys/dev/isa/isapnpres.c @@ -100,7 +100,7 @@ isapnp_newdev(struct isa_attach_args *card) if (card->ipa_child == NULL) card->ipa_child = dev; else { - for (ipa = card->ipa_child; ipa->ipa_sibling != NULL; + for (ipa = card->ipa_child; ipa->ipa_sibling != NULL; ipa = ipa->ipa_sibling) continue; ipa->ipa_sibling = dev; @@ -267,7 +267,7 @@ isapnp_process_tag(u_char tag, u_char len, u_char *buf, (*conf)->ipa_pref); #endif return 0; - + case ISAPNP_TAG_DEP_END: DPRINTF(("<<maxbase = (buf[8] << 24) | (buf[7] << 16) | (buf[6] << 8) | buf[5]; - r->align = (buf[12] << 24) | (buf[11] << 16) | + r->align = (buf[12] << 24) | (buf[11] << 16) | (buf[10] << 8) | buf[9]; r->length = (buf[16] << 24) | (buf[15] << 16) | (buf[14] << 8) | buf[13]; diff --git a/sys/dev/isa/isavar.h b/sys/dev/isa/isavar.h index ae0cb642f..c3e6b3445 100644 --- a/sys/dev/isa/isavar.h +++ b/sys/dev/isa/isavar.h @@ -93,7 +93,7 @@ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * - * BSDI Id: isavar.h,v 1.5 1992/12/01 18:06:00 karels Exp + * BSDI Id: isavar.h,v 1.5 1992/12/01 18:06:00 karels Exp */ #ifndef _DEV_ISA_ISAVAR_H_ @@ -110,7 +110,7 @@ #include "isadma.h" #endif -/* +/* * Structures and definitions needed by the machine-dependent header. */ struct isabus_attach_args; @@ -367,7 +367,7 @@ struct isa_softc { /* * ISA interrupt handler manipulation. - * + * * To establish an ISA interrupt handler, a driver calls isa_intr_establish() * with the interrupt number, type, level, function, and function argument of * the interrupt it wants to handle. Isa_intr_establish() returns an opaque @@ -377,7 +377,7 @@ struct isa_softc { * not for me", 1 for "I took care of it", or -1 for "I guess it was mine, * but I wasn't expecting it." * - * To remove an interrupt handler, the driver calls isa_intr_disestablish() + * To remove an interrupt handler, the driver calls isa_intr_disestablish() * with the handle returned by isa_intr_establish() for that handler. */ diff --git a/sys/dev/isa/lpt_isa.c b/sys/dev/isa/lpt_isa.c index 551540dec..66bfd693f 100644 --- a/sys/dev/isa/lpt_isa.c +++ b/sys/dev/isa/lpt_isa.c @@ -15,25 +15,25 @@ * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: - * This software is a component of "386BSD" developed by + * This software is a component of "386BSD" developed by * William F. Jolitz, TeleMuse. * 4. Neither the name of the developer nor the name "386BSD" * may be used to endorse or promote products derived from this software * without specific prior written permission. * - * THIS SOFTWARE IS A COMPONENT OF 386BSD DEVELOPED BY WILLIAM F. JOLITZ - * AND IS INTENDED FOR RESEARCH AND EDUCATIONAL PURPOSES ONLY. THIS - * SOFTWARE SHOULD NOT BE CONSIDERED TO BE A COMMERCIAL PRODUCT. - * THE DEVELOPER URGES THAT USERS WHO REQUIRE A COMMERCIAL PRODUCT + * THIS SOFTWARE IS A COMPONENT OF 386BSD DEVELOPED BY WILLIAM F. JOLITZ + * AND IS INTENDED FOR RESEARCH AND EDUCATIONAL PURPOSES ONLY. THIS + * SOFTWARE SHOULD NOT BE CONSIDERED TO BE A COMMERCIAL PRODUCT. + * THE DEVELOPER URGES THAT USERS WHO REQUIRE A COMMERCIAL PRODUCT * NOT MAKE USE OF THIS WORK. * * FOR USERS WHO WISH TO UNDERSTAND THE 386BSD SYSTEM DEVELOPED - * BY WILLIAM F. JOLITZ, WE RECOMMEND THE USER STUDY WRITTEN - * REFERENCES SUCH AS THE "PORTING UNIX TO THE 386" SERIES - * (BEGINNING JANUARY 1991 "DR. DOBBS JOURNAL", USA AND BEGINNING - * JUNE 1991 "UNIX MAGAZIN", GERMANY) BY WILLIAM F. JOLITZ AND - * LYNNE GREER JOLITZ, AS WELL AS OTHER BOOKS ON UNIX AND THE - * ON-LINE 386BSD USER MANUAL BEFORE USE. A BOOK DISCUSSING THE INTERNALS + * BY WILLIAM F. JOLITZ, WE RECOMMEND THE USER STUDY WRITTEN + * REFERENCES SUCH AS THE "PORTING UNIX TO THE 386" SERIES + * (BEGINNING JANUARY 1991 "DR. DOBBS JOURNAL", USA AND BEGINNING + * JUNE 1991 "UNIX MAGAZIN", GERMANY) BY WILLIAM F. JOLITZ AND + * LYNNE GREER JOLITZ, AS WELL AS OTHER BOOKS ON UNIX AND THE + * ON-LINE 386BSD USER MANUAL BEFORE USE. A BOOK DISCUSSING THE INTERNALS * OF 386BSD ENTITLED "386BSD FROM THE INSIDE OUT" WILL BE AVAILABLE LATE 1992. * * THIS SOFTWARE IS PROVIDED BY THE DEVELOPER ``AS IS'' AND diff --git a/sys/dev/isa/mpu_isa.c b/sys/dev/isa/mpu_isa.c index 49565aa77..53818eacd 100644 --- a/sys/dev/isa/mpu_isa.c +++ b/sys/dev/isa/mpu_isa.c @@ -96,8 +96,8 @@ mpu_test(bus_space_tag_t iot, int iobase) /* base port number to try */ } delay (10); } - - if (rc == 1) { + + if (rc == 1) { bus_space_write_1(iot, ioh, MPU_COMMAND, MPU_RESET); rc = 0; for (i = 0; i < 2 * MPU_MAXWAIT; i++) diff --git a/sys/dev/isa/pas.c b/sys/dev/isa/pas.c index 906326fce..535bef64c 100644 --- a/sys/dev/isa/pas.c +++ b/sys/dev/isa/pas.c @@ -35,7 +35,7 @@ * */ /* - * jfw 7/13/97 - The soundblaster code requires the generic bus-space + * jfw 7/13/97 - The soundblaster code requires the generic bus-space * structures to be set up properly. Rather than go to the effort of making * code for a dead line fully generic, properly set up the SB structures and * leave the rest x86/ISA/default-configuration specific. If you have a @@ -166,13 +166,13 @@ pasconf(int model, int sbbase, int sbirq, int sbdrq) paswrite(I_C_2_PCM_DMA_DISABLED, IO_CONFIGURATION_2); paswrite(I_C_3_PCM_IRQ_DISABLED, IO_CONFIGURATION_3); - -#ifdef BROKEN_BUS_CLOCK + +#ifdef BROKEN_BUS_CLOCK paswrite(S_C_1_PCS_ENABLE | S_C_1_PCS_STEREO | S_C_1_PCS_REALSOUND | S_C_1_FM_EMULATE_CLOCK, SYSTEM_CONFIGURATION_1); #else paswrite(S_C_1_PCS_ENABLE | S_C_1_PCS_STEREO | S_C_1_PCS_REALSOUND, - SYSTEM_CONFIGURATION_1); + SYSTEM_CONFIGURATION_1); #endif /*XXX*/ @@ -189,7 +189,7 @@ pasconf(int model, int sbbase, int sbirq, int sbdrq) paswrite(P_M_MV508_ADDRESS | P_M_MV508_PCM, PARALLEL_MIXER); paswrite(5, PARALLEL_MIXER); - + /* * Setup SoundBlaster emulation. */ @@ -202,7 +202,7 @@ pasconf(int model, int sbbase, int sbirq, int sbdrq) * Set mid-range levels. */ paswrite(P_M_MV508_ADDRESS | P_M_MV508_MODE, PARALLEL_MIXER); - paswrite(P_M_MV508_LOUDNESS | P_M_MV508_ENHANCE_NONE, PARALLEL_MIXER); + paswrite(P_M_MV508_LOUDNESS | P_M_MV508_ENHANCE_NONE, PARALLEL_MIXER); paswrite(P_M_MV508_ADDRESS | P_M_MV508_MASTER_A, PARALLEL_MIXER); paswrite(50, PARALLEL_MIXER); @@ -253,7 +253,7 @@ pasprobe(struct device *parent, void *match, void *aux) * warm boot reset of the card will screw up this detect code * something fierce. Adding code to handle this means possibly * interfering with other cards on the bus if you have something - * on base port 0x388. SO be forewarned. + * on base port 0x388. SO be forewarned. */ /* Talk to first board */ outb(MASTER_DECODE, 0xbc); @@ -312,7 +312,7 @@ pasprobe(struct device *parent, void *match, void *aux) if (ia->ia_irq == IRQUNK) { DPRINTF(("pas: sb emulation requires known irq\n")); return (0); - } + } pasconf(sc->model, ia->ia_iobase, ia->ia_irq, 1); } else { DPRINTF(("pas: could not probe pas\n")); @@ -355,7 +355,7 @@ pasprobe(struct device *parent, void *match, void *aux) sc->sc_sbdsp.sc_drq8 = ia->ia_drq; sc->sc_sbdsp.sc_drq16 = -1; /* XXX */ sc->sc_sbdsp.sc_ic = ia->ia_ic; - + if (sbdsp_probe(&sc->sc_sbdsp) == 0) { DPRINTF(("pas: sbdsp probe failed\n")); goto unmap; @@ -379,7 +379,7 @@ pasattach(struct device *parent, struct device *self, void *aux) struct pas_softc *sc = (struct pas_softc *)self; struct isa_attach_args *ia = (struct isa_attach_args *)aux; int iobase = ia->ia_iobase; - + sc->sc_sbdsp.sc_isa = parent; sc->sc_sbdsp.sc_iobase = iobase; sc->sc_sbdsp.sc_ih = isa_intr_establish(ia->ia_ic, ia->ia_irq, @@ -387,7 +387,7 @@ pasattach(struct device *parent, struct device *self, void *aux) sbdsp_intr, &sc->sc_sbdsp, sc->sc_sbdsp.sc_dev.dv_xname); printf(" ProAudio Spectrum %s [rev %d] ", pasnames[sc->model], sc->rev); - + sbdsp_attach(&sc->sc_sbdsp); audio_attach_mi(&pas_hw_if, &sc->sc_sbdsp, NULL, &sc->sc_sbdsp.sc_dev); diff --git a/sys/dev/isa/pasreg.h b/sys/dev/isa/pasreg.h index 33eb9b770..724c4cd6e 100644 --- a/sys/dev/isa/pasreg.h +++ b/sys/dev/isa/pasreg.h @@ -3,13 +3,13 @@ /* Port addresses and bit fields for the Media Vision Pro AudioSpectrum * second generation sound cards. - * + * * Feel free to use this header file in any application you create that * has support for the Media Vision Pro AudioSpectrum second generation * sound cards. Other uses prohibited without prior permission. - * + * * - cmetz@thor.tjhsst.edu - * + * * Notes: * * - All of these ports go into the MVD101 multimedia controller chip, @@ -22,7 +22,7 @@ * - The PAS2 series cards are all really different at the hardware level, * though the MVD101 hides some of the incompatibilities, there still * are differences that need to be accounted for. - * + * * Card CD-ROM interface PCM chip Mixer chip FM chip * PAS Plus Sony proprietary (Crystal?) 8-bit DAC National OPL3 * PAS 16 Zilog SCSI MVA416 16-bit Codec MVA508 OPL3 @@ -51,7 +51,7 @@ #define SYSTEM_CONFIGURATION_1 0x8388 /* R W Control */ #define S_C_1_PCS_ENABLE 0x01 /* R W PC speaker 1=enable, 0=disable PC speaker emulation */ - #define S_C_1_PCM_CLOCK_SELECT 0x02 /* R W PCM 1=14.31818MHz/12, 0=28.224MHz master clock */ + #define S_C_1_PCM_CLOCK_SELECT 0x02 /* R W PCM 1=14.31818MHz/12, 0=28.224MHz master clock */ #define S_C_1_FM_EMULATE_CLOCK 0x04 /* R W FM 1=use 28.224MHz/2, 0=use 14.31818MHz clock */ #define S_C_1_PCS_STEREO 0x10 /* R W PC speaker 1=enable PC speaker stereo effect, 0=disable */ #define S_C_1_PCS_REALSOUND 0x20 /* R W PC speaker 1=enable RealSound enhancement, 0=disable */ @@ -118,7 +118,7 @@ struct { /* R W Mixer Filter translation */ unsigned int freq:24; unsigned int value:8; - } F_F_FILTER_translate[] = + } F_F_FILTER_translate[] = { { 73500, 0x01 }, /* 73500Hz - divide by 16 */ { 65333, 0x02 }, /* 65333Hz - divide by 18 */ { 49000, 0x09 }, /* 49000Hz - divide by 24 */ @@ -145,7 +145,7 @@ char I_C_2_PCM_DMA_translate[] = /* R W PCM PCM DMA channel value translations */ { 4, 1, 2, 3, 0, 5, 6, 7 }; char I_C_3_PCM_IRQ_translate[] = /* R W PCM PCM IRQ level value translation */ - { 0, 0, 1, 2, 3, 4, 5, 6, 0, 0, 7, 8, 9, 0, 10, 11 }; + { 0, 0, 1, 2, 3, 4, 5, 6, 0, 0, 7, 8, 9, 0, 10, 11 }; char E_C_MPU401_IRQ_translate[] = /* R W MIDI MPU401 emulation IRQ value translation */ { 0x00, 0x00, 0x01, 0x02, 0x00, 0x03, 0x00, 0x04, 0x00, 0x00, 0x05, 0x06, 0x07 }; char E_C_SB_IRQ_translate[] = /* R W PCM SB emulation IRQ translate */ @@ -153,7 +153,7 @@ char E_C_SB_DMA_translate[] = /* R W PCM SB emulation DMA translate */ { 0x00, 0x40, 0x80, 0xC0 }; char O_M_1_to_card[] = /* R W Control Translate (OM1 & 0x0f) to card type */ - { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 4, 0, 2, 3 }; + { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 4, 0, 2, 3 }; #else extern char I_C_2_PCM_DMA_translate[]; /* R W PCM PCM DMA channel value translations */ extern char I_C_3_PCM_IRQ_translate[]; /* R W PCM PCM IRQ level value translation */ diff --git a/sys/dev/isa/pcppi.c b/sys/dev/isa/pcppi.c index 60191b9dc..28b36e4ca 100644 --- a/sys/dev/isa/pcppi.c +++ b/sys/dev/isa/pcppi.c @@ -6,17 +6,17 @@ * All rights reserved. * * Author: Chris G. Demetriou - * + * * Permission to use, copy, modify and distribute this software and * its documentation is hereby granted, provided that both the copyright * notice and this permission notice appear in all copies of the * software, derivative works or modified versions, and any portions * thereof, and that both notices appear in supporting documentation. - * - * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" - * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. - * + * * Carnegie Mellon requests users of this software to return to * * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU diff --git a/sys/dev/isa/pcppivar.h b/sys/dev/isa/pcppivar.h index 3ddf41955..4348e27b1 100644 --- a/sys/dev/isa/pcppivar.h +++ b/sys/dev/isa/pcppivar.h @@ -6,17 +6,17 @@ * All rights reserved. * * Author: Chris G. Demetriou - * + * * Permission to use, copy, modify and distribute this software and * its documentation is hereby granted, provided that both the copyright * notice and this permission notice appear in all copies of the * software, derivative works or modified versions, and any portions * thereof, and that both notices appear in supporting documentation. - * - * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" - * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. - * + * * Carnegie Mellon requests users of this software to return to * * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU diff --git a/sys/dev/isa/pnpdevs b/sys/dev/isa/pnpdevs index f31bc7465..543bbe4c5 100644 --- a/sys/dev/isa/pnpdevs +++ b/sys/dev/isa/pnpdevs @@ -74,7 +74,7 @@ wdc PNP0600 # Generic ESDI/IDE/ATA compatible hard disk controller # use PNPB0xx instead) #--Display Adapters-- # PNP0900 # VGA Compatible -# PNP0901 # Video Seven VRAM/VRAM II/1024i +# PNP0901 # Video Seven VRAM/VRAM II/1024i # PNP0902 # 8514/A Compatible # PNP0903 # Trident VGA # PNP0904 # Cirrus Logic Laptop VGA @@ -125,9 +125,9 @@ wdc PNP0600 # Generic ESDI/IDE/ATA compatible hard disk controller # PNP0C03 # Plug and Play BIOS Event Notification Interrupt # PNP0C04 # Math Coprocessor # PNP0C05 # APM BIOS (Version independent) -# PNP0C06 # Reserved for identification of early Plug and Play +# PNP0C06 # Reserved for identification of early Plug and Play # BIOS implementation. -# PNP0C07 # Reserved for identification of early Plug and Play +# PNP0C07 # Reserved for identification of early Plug and Play # BIOS implementation. #--PCMCIA Controller Chipsets-- @@ -325,11 +325,11 @@ sb PNPB002 # Sound Blaster Pro-compatible sound device sb PNPB003 # Sound Blaster 16-compatible sound device # PNPB004 # Thunderboard-compatible sound device # PNPB005 # Adlib-compatible FM synthesizer device -mpu PNPB006 # MPU401 compatible +mpu PNPB006 # MPU401 compatible # PNPB007 # Microsoft Windows Sound System-compatible sound device # PNPB008 # Compaq Business Audio # PNPB009 # Plug and Play Microsoft Windows Sound System Device -# PNPB00A # MediaVision Pro Audio Spectrum +# PNPB00A # MediaVision Pro Audio Spectrum # (Trantor SCSI enabled, Thunder Chip Disabled) # PNPB00B # MediaVision Pro Audio 3D # PNPB00C # MusicQuest MQX-32M @@ -350,7 +350,7 @@ com PNPC000 # Compaq 14400 Modem (TBD) com PNPC001 # Compaq 2400/9600 Modem (TBD) # -# Everything else. The following list is exclusively for devices which +# Everything else. The following list is exclusively for devices which # do not have correct PNPxxx IDs set; in which case we must match on the # vendor specific ID # diff --git a/sys/dev/isa/sb.c b/sys/dev/isa/sb.c index 6bef5bda9..4c8967fb3 100644 --- a/sys/dev/isa/sb.c +++ b/sys/dev/isa/sb.c @@ -154,8 +154,8 @@ sbmatch(struct sbdsp_softc *sc) } if (0 <= sc->sc_drq16 && sc->sc_drq16 <= 3) - /* - * XXX Some ViBRA16 cards seem to have two 8 bit DMA + /* + * XXX Some ViBRA16 cards seem to have two 8 bit DMA * channels. I've no clue how to use them, so ignore * one of them for now. -- augustss@netbsd.org */ @@ -171,7 +171,7 @@ sbmatch(struct sbdsp_softc *sc) } } else sc->sc_drq16 = sc->sc_drq8; - + if (ISSBPROCLASS(sc)) { if (!SBP_IRQ_VALID(sc->sc_irq)) { DPRINTF(("%s: configured irq %d invalid\n", diff --git a/sys/dev/isa/sb_isa.c b/sys/dev/isa/sb_isa.c index e698e6ef3..20ad4c685 100644 --- a/sys/dev/isa/sb_isa.c +++ b/sys/dev/isa/sb_isa.c @@ -140,7 +140,7 @@ sb_isa_attach(struct device *parent, struct device *self, void *aux) struct sbdsp_softc *sc = (struct sbdsp_softc *)self; struct isa_attach_args *ia = aux; - if (!sbfind(parent, sc, ia) || + if (!sbfind(parent, sc, ia) || bus_space_map(sc->sc_iot, ia->ia_iobase, ia->ia_iosize, 0, &sc->sc_ioh)) { printf("%s: sbfind failed\n", sc->sc_dev.dv_xname); diff --git a/sys/dev/isa/sb_isapnp.c b/sys/dev/isa/sb_isapnp.c index a80a136a2..c0b4ef6db 100644 --- a/sys/dev/isa/sb_isapnp.c +++ b/sys/dev/isa/sb_isapnp.c @@ -94,7 +94,7 @@ sb_isapnp_attach(struct device *parent, struct device *self, void *aux) sc->sc_iobase = ia->ipa_io[0].base; sc->sc_ic = ia->ia_ic; sc->sc_drq8 = ia->ipa_drq[0].num; - + if (ia->ipa_ndrq > 1 && ia->ipa_drq[0].num != ia->ipa_drq[1].num) { /* Some cards have the 16 bit drq first */ if (sc->sc_drq8 >= 4) { diff --git a/sys/dev/isa/sbdsp.c b/sys/dev/isa/sbdsp.c index 19c823a2c..453ef9491 100644 --- a/sys/dev/isa/sbdsp.c +++ b/sys/dev/isa/sbdsp.c @@ -1074,7 +1074,7 @@ sbdsp_trigger_input(void *addr, void *start, void *end, int blksize, #ifdef DIAGNOSTIC if (sc->sc_i.dmachan != sc->sc_drq8) { printf("sbdsp_trigger_input: width=%d bad chan %d\n", - width, sc->sc_i.dmachan); + width, sc->sc_i.dmachan); return (EIO); } #endif @@ -1332,7 +1332,7 @@ sbdsp_intr(void *arg) mtx_enter(&audio_lock); DPRINTFN(2, ("sbdsp_intr: intr8=%p, intr16=%p\n", sc->sc_intr8, sc->sc_intr16)); - if (ISSB16CLASS(sc)) { + if (ISSB16CLASS(sc)) { bus_space_write_1(sc->sc_iot, sc->sc_ioh, SBP_MIXER_ADDR, SBP_IRQ_STATUS); delay(20); diff --git a/sys/dev/isa/sbreg.h b/sys/dev/isa/sbreg.h index fce014340..d8649d938 100644 --- a/sys/dev/isa/sbreg.h +++ b/sys/dev/isa/sbreg.h @@ -179,7 +179,7 @@ * DSP commands. This unit handles MIDI and audio capabilities. * The DSP can be reset, data/commands can be read or written to it, * and it can generate interrupts. Interrupts are generated for MIDI - * input or DMA completion. They seem to have neglected the fact + * input or DMA completion. They seem to have neglected the fact * that it would be nice to have a MIDI transmission complete interrupt. * Worse, the DMA engine is half-duplex. This means you need to do * (timed) programmed I/O to be able to record and play simultaneously. @@ -281,7 +281,7 @@ #define SB_IRQ_VALID(irq) ((irq) == 3 || (irq) == 5 || (irq) == 7 || (irq) == 9) #define SB16_DRQ_VALID(chan) ((chan) == 0 || (chan) == 1 || (chan) == 3 || \ - (chan) == 5 || (chan) == 6 || (chan) == 7) + (chan) == 5 || (chan) == 6 || (chan) == 7) #define SBP_DRQ_VALID(chan) ((chan) == 0 || (chan) == 1 || (chan) == 3) #define SB_DRQ_VALID(chan) ((chan) == 1) diff --git a/sys/dev/isa/skgpio.c b/sys/dev/isa/skgpio.c index 93a104e4b..727d372bc 100644 --- a/sys/dev/isa/skgpio.c +++ b/sys/dev/isa/skgpio.c @@ -17,7 +17,7 @@ */ /* - * Soekris net6501 GPIO and LEDs as implemented by the onboard Xilinx FPGA + * Soekris net6501 GPIO and LEDs as implemented by the onboard Xilinx FPGA */ #include diff --git a/sys/dev/isa/tcic2_isa.c b/sys/dev/isa/tcic2_isa.c index c757bd40a..6e34f36b5 100644 --- a/sys/dev/isa/tcic2_isa.c +++ b/sys/dev/isa/tcic2_isa.c @@ -257,7 +257,7 @@ tcic_isa_attach(struct device *parent, struct device *self, void *aux) * apparently missing a bit or more of address lines. (e.g. * CIRRUS_PD672X with Linksys EthernetCard ne2000 clone in TI * TravelMate 5000--not clear which is at fault) - * + * * Add a kludge to detect 10 bit wide buses and deal with them, * and also a config file option to override the probe. */ @@ -345,7 +345,7 @@ tcic_isa_chip_intr_establish(pcmcia_chipset_handle_t pch, return (ih); } -void +void tcic_isa_chip_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) { struct tcic_handle *h = (struct tcic_handle *) pch; diff --git a/sys/dev/isa/vga_isa.c b/sys/dev/isa/vga_isa.c index fcc9166df..012b59422 100644 --- a/sys/dev/isa/vga_isa.c +++ b/sys/dev/isa/vga_isa.c @@ -6,17 +6,17 @@ * All rights reserved. * * Author: Chris G. Demetriou - * + * * Permission to use, copy, modify and distribute this software and * its documentation is hereby granted, provided that both the copyright * notice and this permission notice appear in all copies of the * software, derivative works or modified versions, and any portions * thereof, and that both notices appear in supporting documentation. - * - * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" - * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. - * + * * Carnegie Mellon requests users of this software to return to * * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU @@ -47,7 +47,7 @@ #include struct vga_isa_softc { - struct device sc_dev; + struct device sc_dev; #if 0 struct vga_config *sc_vc; /* VGA configuration */ #endif diff --git a/sys/dev/isa/vga_isavar.h b/sys/dev/isa/vga_isavar.h index 6b84fbbac..1986cfeba 100644 --- a/sys/dev/isa/vga_isavar.h +++ b/sys/dev/isa/vga_isavar.h @@ -6,17 +6,17 @@ * All rights reserved. * * Author: Chris G. Demetriou - * + * * Permission to use, copy, modify and distribute this software and * its documentation is hereby granted, provided that both the copyright * notice and this permission notice appear in all copies of the * software, derivative works or modified versions, and any portions * thereof, and that both notices appear in supporting documentation. - * - * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" - * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. - * + * * Carnegie Mellon requests users of this software to return to * * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU diff --git a/sys/dev/isa/viasio.c b/sys/dev/isa/viasio.c index 6ba63d8dc..1f6e9ed76 100644 --- a/sys/dev/isa/viasio.c +++ b/sys/dev/isa/viasio.c @@ -416,7 +416,7 @@ viasio_hm_refresh(void *arg) /* Convert to RPM */ /* XXX: conversion function is guessed */ - if (val != 0) { + if (val != 0) { sc->sc_hm_sensors[VT1211_HMS_FAN1].value = (sc->sc_hm_clock * 60 / 2) / val; sc->sc_hm_sensors[VT1211_HMS_FAN1].flags &= ~SENSOR_FINVALID; @@ -432,7 +432,7 @@ viasio_hm_refresh(void *arg) /* Convert to RPM */ /* XXX: conversion function is guessed */ - if (val != 0) { + if (val != 0) { sc->sc_hm_sensors[VT1211_HMS_FAN2].value = (sc->sc_hm_clock * 60 / 2) / val; sc->sc_hm_sensors[VT1211_HMS_FAN2].flags &= ~SENSOR_FINVALID; diff --git a/sys/dev/isa/wdc_isa.c b/sys/dev/isa/wdc_isa.c index 2d22cd798..6469d75fa 100644 --- a/sys/dev/isa/wdc_isa.c +++ b/sys/dev/isa/wdc_isa.c @@ -178,7 +178,7 @@ static void wdc_isa_dma_setup(struct wdc_isa_softc *sc) { if (isa_dmamap_create(sc->sc_isa, sc->sc_drq, - MAXPHYS, BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW)) { + MAXPHYS, BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW)) { printf("%s: can't create map for drq %d\n", sc->sc_wdcdev.sc_dev.dv_xname, sc->sc_drq); sc->sc_wdcdev.cap &= ~WDC_CAPABILITY_DMA; diff --git a/sys/dev/microcode/adw/advmcode.c b/sys/dev/microcode/adw/advmcode.c index 2ad0588e4..55b71f656 100644 --- a/sys/dev/microcode/adw/advmcode.c +++ b/sys/dev/microcode/adw/advmcode.c @@ -4,7 +4,7 @@ /* * Generic driver definitions and exported functions for the Advanced * Systems Inc. SCSI controllers - * + * * Copyright (c) 1998 The NetBSD Foundation, Inc. * All rights reserved. * @@ -36,7 +36,7 @@ */ /* * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters - * + * * Copyright (c) 1995-1998 Advanced System Products, Inc. * All Rights Reserved. * diff --git a/sys/dev/microcode/adw/advmcode.h b/sys/dev/microcode/adw/advmcode.h index a9d9d9112..bd80c36d4 100644 --- a/sys/dev/microcode/adw/advmcode.h +++ b/sys/dev/microcode/adw/advmcode.h @@ -4,7 +4,7 @@ /* * Generic driver definitions and exported functions for the Advanced * Systems Inc. SCSI controllers - * + * * Copyright (c) 1998 The NetBSD Foundation, Inc. * All rights reserved. * diff --git a/sys/dev/microcode/adw/adwmcode.c b/sys/dev/microcode/adw/adwmcode.c index b9da7eb20..1c79fd95a 100644 --- a/sys/dev/microcode/adw/adwmcode.c +++ b/sys/dev/microcode/adw/adwmcode.c @@ -4,7 +4,7 @@ /* * Generic driver definitions and exported functions for the Advanced * Systems Inc. SCSI controllers - * + * * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc. * All rights reserved. * @@ -36,7 +36,7 @@ */ /* * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters - * + * * Copyright (c) 1995-2000 Advanced System Products, Inc. * All Rights Reserved. * diff --git a/sys/dev/microcode/adw/adwmcode.h b/sys/dev/microcode/adw/adwmcode.h index 9cfcafaad..611a9484b 100644 --- a/sys/dev/microcode/adw/adwmcode.h +++ b/sys/dev/microcode/adw/adwmcode.h @@ -4,7 +4,7 @@ /* * Generic driver definitions and exported functions for the Advanced * Systems Inc. SCSI controllers - * + * * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc. * All rights reserved. * diff --git a/sys/dev/microcode/aic7xxx/aic79xx.reg b/sys/dev/microcode/aic7xxx/aic79xx.reg index 9365dfaa5..0521fc00b 100644 --- a/sys/dev/microcode/aic7xxx/aic79xx.reg +++ b/sys/dev/microcode/aic7xxx/aic79xx.reg @@ -152,7 +152,7 @@ register SEQINTCODE { MKMSG_FAILED, /* * Target completed command * without honoring our ATN - * request to issue a message. + * request to issue a message. */ MISSED_BUSFREE, /* * The sequencer never saw @@ -1081,7 +1081,7 @@ register SFUNCT { } /* - * Data FIFO 0 PCI Status + * Data FIFO 0 PCI Status */ register DF0PCISTAT { address 0x0A0 @@ -1098,7 +1098,7 @@ register DF0PCISTAT { } /* - * Data FIFO 1 PCI Status + * Data FIFO 1 PCI Status */ register DF1PCISTAT { address 0x0A1 @@ -1115,7 +1115,7 @@ register DF1PCISTAT { } /* - * S/G PCI Status + * S/G PCI Status */ register SGPCISTAT { address 0x0A2 @@ -1131,7 +1131,7 @@ register SGPCISTAT { } /* - * CMC PCI Status + * CMC PCI Status */ register CMCPCISTAT { address 0x0A3 @@ -1148,7 +1148,7 @@ register CMCPCISTAT { } /* - * Overlay PCI Status + * Overlay PCI Status */ register OVLYPCISTAT { address 0x0A4 @@ -1266,7 +1266,7 @@ register CMDLENPTR { * Task Attribute Pointer * Scb offset for the byte field specifying the attribute byte * to be used in command packets. - */ + */ register ATTRPTR { address 0x026 access_mode RW @@ -1277,7 +1277,7 @@ register ATTRPTR { * Task Management Flags Pointer * Scb offset for the byte field specifying the attribute flags * byte to be used in command packets. - */ + */ register FLAGPTR { address 0x027 access_mode RW @@ -3234,7 +3234,7 @@ register FLAGS { /* * Sequencer Interrupt Control - */ + */ register SEQINTCTL { address 0x0D9 access_mode RW @@ -3373,7 +3373,7 @@ register DINDIR { * Function One * 2's complement to bit value conversion. Write the 2's complement value * (0-7 only) to the top nibble and retrieve the bit indexed by that value - * on the next read of this register. + * on the next read of this register. * Example: * Write 0x60 * Read 0x40 @@ -3616,7 +3616,7 @@ scratch_ram { size 1 } /* - * The last bus phase as seen by the sequencer. + * The last bus phase as seen by the sequencer. */ LASTPHASE { size 1 @@ -3650,7 +3650,7 @@ scratch_ram { KERNEL_TQINPOS { size 1 } - TQINPOS { + TQINPOS { size 1 } /* @@ -3865,7 +3865,7 @@ scb { SCB_TASK_ATTRIBUTE { size 1 /* - * Overloaded field for non-packetized + * Overloaded field for non-packetized * ignore wide residue message handling. */ field SCB_XFERLEN_ODD 0x01 diff --git a/sys/dev/microcode/aic7xxx/aic79xx.seq b/sys/dev/microcode/aic7xxx/aic79xx.seq index 232899c6a..4a0e8f234 100644 --- a/sys/dev/microcode/aic7xxx/aic79xx.seq +++ b/sys/dev/microcode/aic7xxx/aic79xx.seq @@ -178,7 +178,7 @@ gsfifo_complete_normally: * Case 1 can be detected by noticing a non-zero FIFO active * count in the SCB. In this case, we allow the routine servicing * the FIFO to complete the SCB. - * + * * Case 2 implies either a pending or yet to occur save data * pointers for this same context in the other FIFO. So, if * we detect case 1, we will properly defer the post of the SCB @@ -264,7 +264,7 @@ qoutfifo_updated: add A, -1, INT_COALESCING_MINCMDS; add NONE, A, CMDS_PENDING; jnc issue_cmdcmplt; - + /* * If coalescing, only coalesce up to the limit * provided by the host driver. @@ -363,20 +363,20 @@ fetch_new_scb_done: * immediately. If the queue is not empty, we must * wait for it to empty before entering this SCB * into the waiting for selection queue. Otherwise - * our batching and round-robin selection scheme + * our batching and round-robin selection scheme * could allow commands to be queued out of order. * To simplify the implementation, we stop pulling * new commands from the host until the MK_MESSAGE * SCB can be queued to the waiting for selection * list. */ - test A, MK_MESSAGE jz batch_scb; + test A, MK_MESSAGE jz batch_scb; /* * If the last SCB is also a MK_MESSAGE SCB, then * order is preserved even if we batch. */ - test SCB_CONTROL, MK_MESSAGE jz batch_scb; + test SCB_CONTROL, MK_MESSAGE jz batch_scb; /* * Defer this SCB and stop fetching new SCBs until @@ -550,7 +550,7 @@ BEGIN_CRITICAL; * 2) In a non QAS, protocol allowed phase change, * the queue is shifted 1 too far. LASTSCB is * the last SCB that was correctly processed. - * + * * 3) In the QAS case, if the full list of commands * was successfully sent, NEXTSCB is NULL and neither * CURRSCB nor LASTSCB can be trusted. We must @@ -894,7 +894,7 @@ p_command_from_host: jmp p_command_xfer; p_command_embedded: bmov SHCNT[0], SCB_CDB_LEN, 1; - bmov DFDAT, SCB_CDB_STORE, 16; + bmov DFDAT, SCB_CDB_STORE, 16; mvi DFCNTRL, SCSIEN; p_command_xfer: and SEQ_FLAGS, ~NO_CDB_SENT; @@ -956,7 +956,7 @@ p_status_okay: * associated with this target is set, we will also interrupt the host, * thereby allowing it to send a message on the next selection regardless * of the transaction being sent. - * + * * If MSG_OUT is == HOST_MSG, also interrupt the host and take a message. * This is done to allow the host to send messages outside of an identify * sequence while protecting the sequencer from testing the MK_MESSAGE bit @@ -1389,7 +1389,7 @@ msgin_rdptrs_get_fifo: call allocate_fifo; jmp mesgin_done; -phase_lock: +phase_lock: if ((ahd->bugs & AHD_EARLY_REQ_BUG) != 0) { /* * Don't ignore persistent REQ assertions just because @@ -1632,7 +1632,7 @@ p_data: test SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT jz p_data_allowed; SET_SEQINTCODE(PROTO_VIOLATION) p_data_allowed: - + test SEQ_FLAGS, DPHASE jz data_phase_initialize; /* @@ -1733,7 +1733,7 @@ data_phase_finish: /* * If the target has left us in data phase, loop through * the dma code again. We will only loop if there is a - * data overrun. + * data overrun. */ if ((ahd->flags & AHD_TARGETROLE) != 0) { test SSTAT0, TARGET jnz data_phase_done; @@ -1823,7 +1823,7 @@ sgptr_fixup: test SG_CACHE_SHADOW, 0x80 jz sgptr_fixup_done; test SCB_RESIDUAL_SGPTR[0], 0x80 jnz sgptr_fixup_done; add SCB_RESIDUAL_SGPTR[1], -1; - adc SCB_RESIDUAL_SGPTR[2], -1; + adc SCB_RESIDUAL_SGPTR[2], -1; adc SCB_RESIDUAL_SGPTR[3], -1; sgptr_fixup_done: and SCB_RESIDUAL_SGPTR[0], SG_ADDR_MASK, SG_CACHE_SHADOW; @@ -1867,7 +1867,7 @@ export seq_isr: * (DIRECTION set in DFCNTRL). The delay is performed by * disabling SCSIEN until we see the first REQ from the * target. - * + * * First instruction in an ISR cannot be a branch on * Rev A. Snapshot LQISTAT2 so the status is not missed * and deffer the test by one instruction. diff --git a/sys/dev/microcode/aic7xxx/aic7xxx.reg b/sys/dev/microcode/aic7xxx/aic7xxx.reg index d026d6b95..20c367ecb 100644 --- a/sys/dev/microcode/aic7xxx/aic7xxx.reg +++ b/sys/dev/microcode/aic7xxx/aic7xxx.reg @@ -158,7 +158,7 @@ register SCSISIGO { mask P_MESGIN CDI|IOI|MSGI } -/* +/* * SCSI Rate Control (p. 3-17). * Contents of this register determine the Synchronous SCSI data transfer * rate and the maximum synchronous Req/Ack offset. An offset of 0 in the @@ -219,7 +219,7 @@ register SCSIDATH { * across the SCSI bus. The counter is decremented only once * the data has been safely transferred. SDONE in SSTAT0 is * set when STCNT goes to 0 - */ + */ register STCNT { address 0x008 size 3 @@ -483,7 +483,7 @@ register SPIOCAP { access_mode RW field SOFT1 0x80 field SOFT0 0x40 - field SOFTCMDEN 0x20 + field SOFTCMDEN 0x20 field EXT_BRDCTL 0x10 /* External Board control */ field SEEPROM 0x08 /* External serial eeprom logic */ field EEPROM 0x04 /* Writable external BIOS ROM */ @@ -518,19 +518,19 @@ register BRDCTL { * port is not busy servicing another request, it reconfigures * to allow access to the serial EEPROM. When this happens, SEERDY * gets set high to verify that the memory port access has been - * granted. + * granted. * - * After successful arbitration for the memory port, the SEECS bit of - * the SEECTL register is connected to the chip select. The SEECK, - * SEEDO, and SEEDI are connected to the clock, data out, and data in - * lines respectively. The SEERDY bit of SEECTL is useful in that it - * gives us an 800 nsec timer. After a write to the SEECTL register, - * the SEERDY goes high 800 nsec later. The one exception to this is - * when we first request access to the memory port. The SEERDY goes - * high to signify that access has been granted and, for this case, has + * After successful arbitration for the memory port, the SEECS bit of + * the SEECTL register is connected to the chip select. The SEECK, + * SEEDO, and SEEDI are connected to the clock, data out, and data in + * lines respectively. The SEERDY bit of SEECTL is useful in that it + * gives us an 800 nsec timer. After a write to the SEECTL register, + * the SEERDY goes high 800 nsec later. The one exception to this is + * when we first request access to the memory port. The SEERDY goes + * high to signify that access has been granted and, for this case, has * no implied timing. * - * See 93cx6.c for detailed information on the protocol necessary to + * See 93cx6.c for detailed information on the protocol necessary to * read the serial EEPROM. */ register SEECTL { @@ -807,7 +807,7 @@ register INTSTAT { field SEQINT 0x01 mask BAD_PHASE SEQINT /* unknown scsi bus phase */ mask SEND_REJECT 0x10|SEQINT /* sending a message reject */ - mask PROTO_VIOLATION 0x20|SEQINT /* SCSI protocol violation */ + mask PROTO_VIOLATION 0x20|SEQINT /* SCSI protocol violation */ mask NO_MATCH 0x30|SEQINT /* no cmd match for reconnect */ mask IGN_WIDE_RES 0x40|SEQINT /* Complex IGN Wide Res Msg */ mask PDATA_REINIT 0x50|SEQINT /* @@ -840,7 +840,7 @@ register INTSTAT { mask MKMSG_FAILED 0xa0|SEQINT /* * Target completed command * without honoring our ATN - * request to issue a message. + * request to issue a message. */ mask MISSED_BUSFREE 0xb0|SEQINT /* * The sequencer never saw @@ -1360,7 +1360,7 @@ scratch_ram { size 1 } /* - * The last bus phase as seen by the sequencer. + * The last bus phase as seen by the sequencer. */ LASTPHASE { size 1 @@ -1437,7 +1437,7 @@ scratch_ram { KERNEL_TQINPOS { size 1 } - TQINPOS { + TQINPOS { size 1 } ARG_1 { @@ -1539,7 +1539,7 @@ scratch_ram { address 0x05f size 1 mask BIOSMODE 0x30 - mask BIOSDISABLED 0x30 + mask BIOSDISABLED 0x30 field CHANNEL_B_PRIMARY 0x08 } } diff --git a/sys/dev/microcode/aic7xxx/aic7xxx.seq b/sys/dev/microcode/aic7xxx/aic7xxx.seq index 8d3da492c..c759fbd01 100644 --- a/sys/dev/microcode/aic7xxx/aic7xxx.seq +++ b/sys/dev/microcode/aic7xxx/aic7xxx.seq @@ -57,9 +57,9 @@ PREFIX = "ahc_" * on just in case the reselection wins so that we can retry the selection at * a later time. This problem cannot be resolved by holding a single entry * in scratch ram since a reconnecting target can request sense and this will - * create yet another SCB waiting for selection. The solution used here is to + * create yet another SCB waiting for selection. The solution used here is to * use byte 27 of the SCB as a psuedo-next pointer and to thread a list - * of SCBs that are awaiting selection. Since 0-0xfe are valid SCB indexes, + * of SCBs that are awaiting selection. Since 0-0xfe are valid SCB indexes, * SCB_LIST_NULL is 0xff which is out of range. An entry is also added to * this list everytime a request sense occurs or after completing a non-tagged * command for which a second SCB has been queued. The sequencer will @@ -104,7 +104,7 @@ BEGIN_CRITICAL; mov ARG_1, NEXT_QUEUED_SCB; /* - * We have at least one queued SCB now and we don't have any + * We have at least one queued SCB now and we don't have any * SCBs in the list of SCBs awaiting selection. Allocate a * card SCB for the host's SCB and get to work on it. */ @@ -282,7 +282,7 @@ select_in: } else { mov DFDAT, DINDEX; } - + /* * If the initiator doesn't feel like providing a tag number, * we've got a failed selection and must transition to bus @@ -401,7 +401,7 @@ set_transfer_settings: if ((ahc->features & AHC_ULTRA) != 0) { test SCB_CONTROL, ULTRAENB jz . + 2; or SXFRCTL0, FAST20; - } + } /* * Initialize SCSIRATE with the appropriate value for this target. */ @@ -413,7 +413,7 @@ set_transfer_settings: if ((ahc->flags & AHC_TARGETROLE) != 0) { /* - * We carefully toggle SPIOEN to allow us to return the + * We carefully toggle SPIOEN to allow us to return the * message byte we receive so it can be checked prior to * driving REQ on the bus for the next byte. */ @@ -481,7 +481,7 @@ target_synccmd: * to go through. */ mov SEQ_FLAGS, SCB_TARGET_PHASES; - + test SCB_CONTROL, MK_MESSAGE jz target_ITloop; mvi P_MESGIN|BSYO call change_phase; jmp host_target_message_loop; @@ -499,7 +499,7 @@ target_ITloop: * No more work to do. Either disconnect or not depending * on the state of NO_DISCONNECT. */ - test SEQ_FLAGS, NO_DISCONNECT jz target_disconnect; + test SEQ_FLAGS, NO_DISCONNECT jz target_disconnect; mvi TARG_IMMEDIATE_SCB, SCB_LIST_NULL; call complete_target_cmd; if ((ahc->flags & AHC_PAGESCBS) != 0) { @@ -520,7 +520,7 @@ target_mesgout_pending: and SEQ_FLAGS2, ~TARGET_MSG_PENDING; /* Local Processing goes here... */ jmp host_target_message_loop; - + target_disconnect: mvi P_MESGIN|BSYO call change_phase; test SEQ_FLAGS, DPHASE jz . + 2; @@ -558,7 +558,7 @@ target_cmdphase: jmp target_busfree_wait; mvi STATUS_BUSY call target_outb; jmp target_busfree_wait; -tqinfifo_has_space: +tqinfifo_has_space: mvi P_COMMAND|BSYO call change_phase; call target_inb; mov A, DINDEX; @@ -620,7 +620,7 @@ target_sphase: /* MSG_CMDCMPLT is 0, but we can't do an immediate of 0 */ mov ALLZEROS call target_outb; jmp target_busfree_wait; - + complete_target_cmd: test SEQ_FLAGS, TARG_CMD_PENDING jnz . + 2; mov SCB_TAG jmp complete_post; @@ -689,7 +689,7 @@ await_busfree: test SSTAT1, BUSFREE jnz poll_for_work; mvi MISSED_BUSFREE call set_seqint; } - + clear_target_state: /* * We assume that the kernel driver may reset us @@ -792,7 +792,7 @@ idle_sg_avail: if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 && ahc->pci_cachesize != 0) { /* * Calculate the trailing portion of this S/G segment that cannot - * be transferred using memory write and invalidate PCI transactions. + * be transferred using memory write and invalidate PCI transactions. * XXX Can we optimize this for PCI writes only??? */ calc_mwi_residual: @@ -1001,7 +1001,7 @@ sgptr_fixup: test SG_CACHE_SHADOW, 0x80 jz sgptr_fixup_done; test SCB_RESIDUAL_SGPTR[0], 0x80 jnz sgptr_fixup_done; add SCB_RESIDUAL_SGPTR[1], -1; - adc SCB_RESIDUAL_SGPTR[2], -1; + adc SCB_RESIDUAL_SGPTR[2], -1; adc SCB_RESIDUAL_SGPTR[3], -1; sgptr_fixup_done: and SCB_RESIDUAL_SGPTR[0], SG_ADDR_MASK, SG_CACHE_SHADOW; @@ -1146,7 +1146,7 @@ dma_dmadone: dma_halt: /* * Some revisions of the aic78XX have a problem where, if the - * data fifo is full, but the PCI input latch is not empty, + * data fifo is full, but the PCI input latch is not empty, * HDMAEN cannot be cleared. The fix used here is to drain * the prefetched but unused data from the data fifo until * there is space for the input latch to drain. @@ -1162,7 +1162,7 @@ dma_halt: test STCNT[2], 0xff jnz data_phase_finish; /* - * Advance the scatter-gather pointers if needed + * Advance the scatter-gather pointers if needed */ if ((ahc->bugs & AHC_PCI_MWI_BUG) != 0 && ahc->pci_cachesize != 0) { @@ -1414,7 +1414,7 @@ p_command_embedded: clr HADDR[0]; if ((ahc->features & AHC_ULTRA2) != 0) { mvi DFCNTRL, (PRELOADEN|SCSIEN|DIRECTION); - bmov DFDAT, SCB_CDB_STORE, 12; + bmov DFDAT, SCB_CDB_STORE, 12; } else if ((ahc->features & AHC_CMD_CHAN) != 0) { if ((ahc->flags & AHC_SCB_BTT) != 0) { /* @@ -1429,7 +1429,7 @@ p_command_embedded: } else { mvi DFCNTRL, (SCSIEN|SDMAEN|DIRECTION|FIFORESET); } - bmov DFDAT, SCB_CDB_STORE, 12; + bmov DFDAT, SCB_CDB_STORE, 12; if ((ahc->flags & AHC_SCB_BTT) != 0) { mvi DFCNTRL, (SCSIEN|SDMAEN|DIRECTION|FIFOFLUSH); } else { @@ -1485,7 +1485,7 @@ p_status_okay: * associated with this target is set, we will also interrupt the host, * thereby allowing it to send a message on the next selection regardless * of the transaction being sent. - * + * * If MSG_OUT is == HOST_MSG, also interrupt the host and take a message. * This is done to allow the host to send messages outside of an identify * sequence while protecting the sequencer from testing the MK_MESSAGE bit @@ -1608,11 +1608,11 @@ mesgin_done: * and trigger a completion interrupt. Before doing so, check to see if there * is a residual or the status byte is something other than STATUS_GOOD (0). * In either of these conditions, we upload the SCB back to the host so it can - * process this information. In the case of a non zero status byte, we + * process this information. In the case of a non zero status byte, we * additionally interrupt the kernel driver synchronously, allowing it to * decide if sense should be retrieved. If the kernel driver wishes to request * sense, it will fill the kernel SCB with a request sense command, requeue - * it to the QINFIFO and tell us not to post to the QOUTFIFO by setting + * it to the QINFIFO and tell us not to post to the QOUTFIFO by setting * RETURN_1 to SEND_SENSE. */ mesgin_complete: @@ -1633,7 +1633,7 @@ mesgin_complete: * any status will do. Optimize this fast path. */ test SCB_CONTROL, STATUS_RCVD jz mesgin_proto_violation; - test SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT jz complete_accepted; + test SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT jz complete_accepted; /* * If the target never sent an identify message but instead went @@ -2037,7 +2037,7 @@ target_outb: test SSTAT0, SPIORDY jz .; and SXFRCTL0, ~SPIOEN ret; } - + /* * Locate a disconnected SCB by SCBID. Upon return, SCBPTR and SINDEX will * be set to the position of the SCB. If the SCB cannot be found locally, @@ -2111,7 +2111,7 @@ post_byte: phase_lock_perr: mvi PERR_DETECTED call set_seqint; -phase_lock: +phase_lock: /* * If there is a parity error, wait for the kernel to * see the interrupt and prepare our message response diff --git a/sys/dev/microcode/aic7xxx/aicasm.c b/sys/dev/microcode/aic7xxx/aicasm.c index af3e0bfcb..de143798b 100644 --- a/sys/dev/microcode/aic7xxx/aicasm.c +++ b/sys/dev/microcode/aic7xxx/aicasm.c @@ -128,7 +128,7 @@ main(int argc, char *argv[]) /* Set Sentinal scope node */ sentinal = scope_alloc(); sentinal->type = SCOPE_ROOT; - + includes_search_curdir = 1; appname = *argv; regfile = NULL; @@ -552,7 +552,7 @@ output_listing(char *ifilename) if (func_values == NULL) stop("Could not malloc", EX_OSERR); - + func_values[0] = 0; /* FALSE func */ func_count--; @@ -560,13 +560,13 @@ output_listing(char *ifilename) * Ask the user to fill in the return values for * the rest of the functions. */ - - + + for (cur_func = SLIST_FIRST(&patch_functions); cur_func != NULL && SLIST_NEXT(cur_func, links) != NULL; cur_func = SLIST_NEXT(cur_func, links), func_count--) { int input; - + fprintf(stdout, "\n(%s)\n", cur_func->symbol->name); fprintf(stdout, "Enter the return value for " @@ -750,7 +750,7 @@ cs_alloc() if (new_cs == NULL) stop("Unable to malloc critical_section object", EX_SOFTWARE); memset(new_cs, 0, sizeof(*new_cs)); - + TAILQ_INSERT_TAIL(&cs_tailq, new_cs, links); return new_cs; } @@ -765,7 +765,7 @@ scope_alloc() stop("Unable to malloc scope object", EX_SOFTWARE); memset(new_scope, 0, sizeof(*new_scope)); TAILQ_INIT(&new_scope->inner_scope); - + if (SLIST_FIRST(&scope_stack) != NULL) { TAILQ_INSERT_TAIL(&SLIST_FIRST(&scope_stack)->inner_scope, new_scope, scope_links); diff --git a/sys/dev/microcode/aic7xxx/aicasm.h b/sys/dev/microcode/aic7xxx/aicasm.h index e647c180a..d60469801 100644 --- a/sys/dev/microcode/aic7xxx/aicasm.h +++ b/sys/dev/microcode/aic7xxx/aicasm.h @@ -63,7 +63,7 @@ typedef struct path_entry { SLIST_ENTRY(path_entry) links; } *path_entry_t; -typedef enum { +typedef enum { QUOTED_INCLUDE, BRACKETED_INCLUDE, SOURCE_FILE diff --git a/sys/dev/microcode/aic7xxx/aicasm_gram.y b/sys/dev/microcode/aic7xxx/aicasm_gram.y index 1aeee3293..c683cd142 100644 --- a/sys/dev/microcode/aic7xxx/aicasm_gram.y +++ b/sys/dev/microcode/aic7xxx/aicasm_gram.y @@ -307,13 +307,13 @@ reg_definition: stop("Register multiply defined", EX_DATAERR); /* NOTREACHED */ } - cur_symbol = $1; + cur_symbol = $1; cur_symbol->type = cur_symtype; initialize_symbol(cur_symbol); } reg_attribute_list '}' - { + { /* * Default to allowing everything in for registers * with no bit or mask definitions. @@ -343,7 +343,7 @@ reg_attribute_list: | reg_attribute_list reg_attribute ; -reg_attribute: +reg_attribute: reg_address | size | access_mode @@ -708,7 +708,7 @@ expression: ; constant: - T_CONST T_SYMBOL expression + T_CONST T_SYMBOL expression { if ($2->type != UNINITIALIZED) { stop("Re-definition of symbol as a constant", @@ -1513,7 +1513,7 @@ initialize_symbol(symbol_t *symbol) sizeof(struct cond_info)); break; case MACRO: - symbol->info.macroinfo = + symbol->info.macroinfo = (struct macro_info *)malloc(sizeof(struct macro_info)); if (symbol->info.macroinfo == NULL) { stop("Can't create macro info", EX_SOFTWARE); @@ -1537,7 +1537,7 @@ add_macro_arg(const char *argtext, int argnum) struct macro_arg *marg; int i; int retval; - + if (cur_symbol == NULL || cur_symbol->type != MACRO) { stop("Invalid current symbol for adding macro arg", @@ -1782,7 +1782,7 @@ format_3_instr(int opcode, symbol_ref_t *src, static void test_readable_symbol(symbol_t *symbol) { - + if ((symbol->info.rinfo->modes & (0x1 << src_mode)) == 0) { snprintf(errbuf, sizeof(errbuf), "Register %s unavailable in source reg mode %d", @@ -1800,7 +1800,7 @@ test_readable_symbol(symbol_t *symbol) static void test_writable_symbol(symbol_t *symbol) { - + if ((symbol->info.rinfo->modes & (0x1 << dst_mode)) == 0) { snprintf(errbuf, sizeof(errbuf), "Register %s unavailable in destination reg mode %d", diff --git a/sys/dev/microcode/aic7xxx/aicasm_macro_scan.l b/sys/dev/microcode/aic7xxx/aicasm_macro_scan.l index 3b63657d6..2b9afb297 100644 --- a/sys/dev/microcode/aic7xxx/aicasm_macro_scan.l +++ b/sys/dev/microcode/aic7xxx/aicasm_macro_scan.l @@ -2,7 +2,7 @@ /* /* $OpenBSD: aicasm_macro_scan.l,v 1.4 2004/09/18 19:51:53 mickey Exp $ */ /* - * Sub-Lexical Analyzer for macro invokation in + * Sub-Lexical Analyzer for macro invokation in * the Aic7xxx SCSI Host adapter sequencer assembler. * * Copyright (c) 2001 Adaptec Inc. @@ -144,7 +144,7 @@ MCARG [^(), \t]+ BEGIN ARGLIST; return T_SYMBOL; } -. { +. { snprintf(buf, sizeof(buf), "Invalid character " "'%c'", mmtext[0]); stop(buf, EX_DATAERR); diff --git a/sys/dev/microcode/aic7xxx/aicasm_scan.l b/sys/dev/microcode/aic7xxx/aicasm_scan.l index 57f9eaaa7..28fdcb810 100644 --- a/sys/dev/microcode/aic7xxx/aicasm_scan.l +++ b/sys/dev/microcode/aic7xxx/aicasm_scan.l @@ -129,7 +129,7 @@ if[ \t]*\( { && string_buf_ptr != string_buf && string_buf_ptr[-1] == ' ') yptr++; - else + else *string_buf_ptr++ = *yptr++; } } @@ -430,7 +430,7 @@ else { return T_ELSE; } return T_SYMBOL; } } -. { +. { snprintf(buf, sizeof(buf), "Invalid character " "'%c'", yytext[0]); stop(buf, EX_DATAERR); diff --git a/sys/dev/microcode/aic7xxx/aicasm_symbol.c b/sys/dev/microcode/aic7xxx/aicasm_symbol.c index 4c6b834cf..55df7c531 100644 --- a/sys/dev/microcode/aic7xxx/aicasm_symbol.c +++ b/sys/dev/microcode/aic7xxx/aicasm_symbol.c @@ -352,7 +352,7 @@ aic_print_reg_dump_types(FILE *ofile) { if (ofile == NULL) return; - + fprintf(ofile, "typedef int (%sreg_print_t)(u_int, u_int *, u_int);\n" "typedef struct %sreg_parse_entry {\n" @@ -386,7 +386,7 @@ aic_print_reg_dump_end(FILE *ofile, FILE *dfile, lower_name = strdup(regnode->symbol->name); if (lower_name == NULL) stop("Unable to strdup symbol name", EX_SOFTWARE); - + for (letter = lower_name; *letter != '\0'; letter++) *letter = tolower(*letter); @@ -647,7 +647,7 @@ symtable_dump(FILE *ofile, FILE *dfile) free(curnode); } - + fprintf(ofile, "\n\n/* Downloaded Constant Definitions */\n"); for (i = 0; SLIST_FIRST(&download_constants) != NULL; i++) { diff --git a/sys/dev/microcode/atmel/atmel_at76c503_i3863_fw.h b/sys/dev/microcode/atmel/atmel_at76c503_i3863_fw.h index 4f8975d96..73f72f9d1 100644 --- a/sys/dev/microcode/atmel/atmel_at76c503_i3863_fw.h +++ b/sys/dev/microcode/atmel/atmel_at76c503_i3863_fw.h @@ -13,7 +13,7 @@ * and/or other materials provided with the distribution; and * 3. The name of Atmel Corporation may not be used to endorse or promote products * derived from this Firmware without specific prior written consent. - * + * * DISCLAIMER: ATMEL PROVIDES THIS FIRMWARE "AS IS'' WITH NO WARRANTIES * OR INDEMNITIES WHATSOEVER. ATMEL EXPRESSLY DISCLAIMS ANY * EXPRESS, STATUTORY OR IMPLIED WARRANTIES, INCLUDING, BUT NOT @@ -26,7 +26,7 @@ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * FIRMWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * * USER ACKNOWLEDGES AND AGREES THAT THE PURCHASE OR USE OF THE * FIRMWARE WILL NOT CREATE OR GIVE GROUNDS FOR A LICENSE BY * IMPLICATION, ESTOPPEL, OR OTHERWISE IN ANY INTELLECTUAL PROPERTY diff --git a/sys/dev/microcode/atmel/atmel_at76c503_rfmd2_fw.h b/sys/dev/microcode/atmel/atmel_at76c503_rfmd2_fw.h index dac6229ce..00adadd47 100644 --- a/sys/dev/microcode/atmel/atmel_at76c503_rfmd2_fw.h +++ b/sys/dev/microcode/atmel/atmel_at76c503_rfmd2_fw.h @@ -13,7 +13,7 @@ * and/or other materials provided with the distribution; and * 3. The name of Atmel Corporation may not be used to endorse or promote products * derived from this Firmware without specific prior written consent. - * + * * DISCLAIMER: ATMEL PROVIDES THIS FIRMWARE "AS IS'' WITH NO WARRANTIES * OR INDEMNITIES WHATSOEVER. ATMEL EXPRESSLY DISCLAIMS ANY * EXPRESS, STATUTORY OR IMPLIED WARRANTIES, INCLUDING, BUT NOT @@ -26,7 +26,7 @@ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * FIRMWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * * USER ACKNOWLEDGES AND AGREES THAT THE PURCHASE OR USE OF THE * FIRMWARE WILL NOT CREATE OR GIVE GROUNDS FOR A LICENSE BY * IMPLICATION, ESTOPPEL, OR OTHERWISE IN ANY INTELLECTUAL PROPERTY diff --git a/sys/dev/microcode/atmel/atmel_at76c503_rfmd_acc_fw.h b/sys/dev/microcode/atmel/atmel_at76c503_rfmd_acc_fw.h index e4679633e..0401664f1 100644 --- a/sys/dev/microcode/atmel/atmel_at76c503_rfmd_acc_fw.h +++ b/sys/dev/microcode/atmel/atmel_at76c503_rfmd_acc_fw.h @@ -13,7 +13,7 @@ * and/or other materials provided with the distribution; and * 3. The name of Atmel Corporation may not be used to endorse or promote products * derived from this Firmware without specific prior written consent. - * + * * DISCLAIMER: ATMEL PROVIDES THIS FIRMWARE "AS IS'' WITH NO WARRANTIES * OR INDEMNITIES WHATSOEVER. ATMEL EXPRESSLY DISCLAIMS ANY * EXPRESS, STATUTORY OR IMPLIED WARRANTIES, INCLUDING, BUT NOT @@ -26,7 +26,7 @@ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * FIRMWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * * USER ACKNOWLEDGES AND AGREES THAT THE PURCHASE OR USE OF THE * FIRMWARE WILL NOT CREATE OR GIVE GROUNDS FOR A LICENSE BY * IMPLICATION, ESTOPPEL, OR OTHERWISE IN ANY INTELLECTUAL PROPERTY diff --git a/sys/dev/microcode/atmel/atmel_at76c505_rfmd.h b/sys/dev/microcode/atmel/atmel_at76c505_rfmd.h index 866000c8d..dc1dcca8e 100644 --- a/sys/dev/microcode/atmel/atmel_at76c505_rfmd.h +++ b/sys/dev/microcode/atmel/atmel_at76c505_rfmd.h @@ -13,7 +13,7 @@ * and/or other materials provided with the distribution; and * 3. The name of Atmel Corporation may not be used to endorse or promote products * derived from this Firmware without specific prior written consent. - * + * * DISCLAIMER: ATMEL PROVIDES THIS FIRMWARE "AS IS'' WITH NO WARRANTIES * OR INDEMNITIES WHATSOEVER. ATMEL EXPRESSLY DISCLAIMS ANY * EXPRESS, STATUTORY OR IMPLIED WARRANTIES, INCLUDING, BUT NOT @@ -26,7 +26,7 @@ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * FIRMWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * * USER ACKNOWLEDGES AND AGREES THAT THE PURCHASE OR USE OF THE * FIRMWARE WILL NOT CREATE OR GIVE GROUNDS FOR A LICENSE BY * IMPLICATION, ESTOPPEL, OR OTHERWISE IN ANY INTELLECTUAL PROPERTY diff --git a/sys/dev/microcode/atmel/atmel_intersil_fw.h b/sys/dev/microcode/atmel/atmel_intersil_fw.h index c39c6dfcd..619051768 100644 --- a/sys/dev/microcode/atmel/atmel_intersil_fw.h +++ b/sys/dev/microcode/atmel/atmel_intersil_fw.h @@ -14,7 +14,7 @@ * and/or other materials provided with the distribution; and * 3. The name of Atmel Corporation may not be used to endorse or promote products * derived from this Firmware without specific prior written consent. - * + * * DISCLAIMER: ATMEL PROVIDES THIS FIRMWARE "AS IS'' WITH NO WARRANTIES * OR INDEMNITIES WHATSOEVER. ATMEL EXPRESSLY DISCLAIMS ANY * EXPRESS, STATUTORY OR IMPLIED WARRANTIES, INCLUDING, BUT NOT @@ -27,7 +27,7 @@ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * FIRMWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * * USER ACKNOWLEDGES AND AGREES THAT THE PURCHASE OR USE OF THE * FIRMWARE WILL NOT CREATE OR GIVE GROUNDS FOR A LICENSE BY * IMPLICATION, ESTOPPEL, OR OTHERWISE IN ANY INTELLECTUAL PROPERTY diff --git a/sys/dev/microcode/atmel/atmel_rfmd2958-smc_fw.h b/sys/dev/microcode/atmel/atmel_rfmd2958-smc_fw.h index a85fb0c54..9dcfc12f1 100644 --- a/sys/dev/microcode/atmel/atmel_rfmd2958-smc_fw.h +++ b/sys/dev/microcode/atmel/atmel_rfmd2958-smc_fw.h @@ -13,7 +13,7 @@ * and/or other materials provided with the distribution; and * 3. The name of Atmel Corporation may not be used to endorse or promote products * derived from this Firmware without specific prior written consent. - * + * * DISCLAIMER: ATMEL PROVIDES THIS FIRMWARE "AS IS'' WITH NO WARRANTIES * OR INDEMNITIES WHATSOEVER. ATMEL EXPRESSLY DISCLAIMS ANY * EXPRESS, STATUTORY OR IMPLIED WARRANTIES, INCLUDING, BUT NOT @@ -26,7 +26,7 @@ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * FIRMWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * * USER ACKNOWLEDGES AND AGREES THAT THE PURCHASE OR USE OF THE * FIRMWARE WILL NOT CREATE OR GIVE GROUNDS FOR A LICENSE BY * IMPLICATION, ESTOPPEL, OR OTHERWISE IN ANY INTELLECTUAL PROPERTY @@ -34,7 +34,7 @@ * PROPRIETARY RIGHT) EMBODIED IN ANY OTHER ATMEL HARDWARE OR * FIRMWARE EITHER SOLELY OR IN COMBINATION WITH THE FIRMWARE. */ - + unsigned char atmel_fw_rfmd2958_smc_int[] = { 0x80,0xf1,0x9f,0xe5,0x80,0xf1,0x9f,0xe5,0x80,0xf1,0x9f,0xe5,0x80,0xf1, 0x9f,0xe5,0x80,0xf1,0x9f,0xe5,0x80,0xf1,0x9f,0xe5,0x80,0xf1,0x9f,0xe5, diff --git a/sys/dev/microcode/atmel/atmel_rfmd2958_fw.h b/sys/dev/microcode/atmel/atmel_rfmd2958_fw.h index b177124fe..0a94a77ab 100644 --- a/sys/dev/microcode/atmel/atmel_rfmd2958_fw.h +++ b/sys/dev/microcode/atmel/atmel_rfmd2958_fw.h @@ -14,7 +14,7 @@ * and/or other materials provided with the distribution; and * 3. The name of Atmel Corporation may not be used to endorse or promote products * derived from this Firmware without specific prior written consent. - * + * * DISCLAIMER: ATMEL PROVIDES THIS FIRMWARE "AS IS'' WITH NO WARRANTIES * OR INDEMNITIES WHATSOEVER. ATMEL EXPRESSLY DISCLAIMS ANY * EXPRESS, STATUTORY OR IMPLIED WARRANTIES, INCLUDING, BUT NOT @@ -27,7 +27,7 @@ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * FIRMWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * * USER ACKNOWLEDGES AND AGREES THAT THE PURCHASE OR USE OF THE * FIRMWARE WILL NOT CREATE OR GIVE GROUNDS FOR A LICENSE BY * IMPLICATION, ESTOPPEL, OR OTHERWISE IN ANY INTELLECTUAL PROPERTY diff --git a/sys/dev/microcode/atmel/atmel_rfmd_fw.h b/sys/dev/microcode/atmel/atmel_rfmd_fw.h index 933414adc..e28dba3f5 100644 --- a/sys/dev/microcode/atmel/atmel_rfmd_fw.h +++ b/sys/dev/microcode/atmel/atmel_rfmd_fw.h @@ -14,7 +14,7 @@ * and/or other materials provided with the distribution; and * 3. The name of Atmel Corporation may not be used to endorse or promote products * derived from this Firmware without specific prior written consent. - * + * * DISCLAIMER: ATMEL PROVIDES THIS FIRMWARE "AS IS'' WITH NO WARRANTIES * OR INDEMNITIES WHATSOEVER. ATMEL EXPRESSLY DISCLAIMS ANY * EXPRESS, STATUTORY OR IMPLIED WARRANTIES, INCLUDING, BUT NOT @@ -27,7 +27,7 @@ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * FIRMWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * * USER ACKNOWLEDGES AND AGREES THAT THE PURCHASE OR USE OF THE * FIRMWARE WILL NOT CREATE OR GIVE GROUNDS FOR A LICENSE BY * IMPLICATION, ESTOPPEL, OR OTHERWISE IN ANY INTELLECTUAL PROPERTY @@ -37,2532 +37,2532 @@ */ unsigned char atmel_fw_rfmd_int[] = { -0x7C,0xF1,0x9F,0xE5,0x7C,0xF1,0x9F,0xE5,0x7C,0xF1,0x9F,0xE5,0x7C,0xF1,0x9F, -0xE5,0x7C,0xF1,0x9F,0xE5,0x7C,0xF1,0x9F,0xE5,0x7C,0xF1,0x9F,0xE5,0x7C,0xF1, -0x9F,0xE5,0xD3,0x00,0xA0,0xE3,0x00,0xF0,0x21,0xE1,0x0E,0x04,0xA0,0xE3,0x00, -0x10,0xA0,0xE3,0x81,0x11,0xA0,0xE1,0x00,0x10,0x81,0xE3,0x00,0x10,0x80,0xE5, -0x0F,0x04,0xA0,0xE3,0x00,0x10,0xA0,0xE3,0x04,0x10,0x80,0xE5,0x0C,0x10,0x80, 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-0xFF,0xEA,0xFE,0xFF,0xFF,0xEA,0xFE,0xFF,0xFF,0xEA,0x60,0x0F,0x00,0xEA,0x02, -0xF0,0xD4,0xFA,0x22,0x48,0x87,0x46,0x79,0x0F,0x00,0xEA,0x02,0xF0,0xE8,0xF8, -0x20,0x48,0x87,0x46,0xCD,0x05,0x00,0x00,0xC0,0x03,0x00,0x02,0x00,0x01,0x00, -0x00,0x00,0x01,0x00,0x00,0x00,0x01,0x00,0x00,0x44,0x04,0x00,0x02,0x64,0x04, -0x00,0x02,0x68,0x04,0x00,0x02,0x6C,0x04,0x00,0x02,0xFE,0xFF,0xFF,0xEA,0xFE, -0xFF,0xFF,0xEA,0xFE,0xFF,0xFF,0xEA,0xFE,0xFF,0xFF,0xEA,0x00,0x00,0xA0,0xE3, -0x0E,0xF0,0xA0,0xE1,0xFE,0xFF,0xFF,0xEA,0xFE,0xFF,0xFF,0xEA,0x00,0x00,0xA0, -0xE3,0x0E,0xF0,0xA0,0xE1,0x00,0x00,0xA0,0xE3,0x0E,0xF0,0xA0,0xE1,0x20,0x00, -0x00,0x00,0x04,0x01,0x00,0x00,0x08,0x01,0x00,0x00,0x0C,0x01,0x00,0x00,0x10, -0x01,0x00,0x00,0x14,0x01,0x00,0x00,0x18,0x01,0x00,0x00,0x24,0x01,0x00,0x00, -0x00,0x60,0x00,0x01,0xE0,0x59,0x00,0x01,0x91,0x3F,0x00,0x00,0x81,0x40,0x00, -0x00,0x78,0x47,0x00,0x00,0xF0,0x40,0x2D,0xE9,0x80,0x31,0x9F,0xE5,0x03,0x00, -0x83,0xE8,0x3F,0x40,0x01,0xE2,0x00,0x00,0x54,0xE3,0x01,0x50,0xA0,0x03,0x07, -0x50,0xC3,0x05,0x00,0x00,0xA0,0xE3,0x5F,0x00,0x00,0xEB,0x60,0x31,0x9F,0xE5, -0xB4,0x20,0xD3,0xE1,0x00,0x00,0x52,0xE3,0x02,0x00,0x00,0x0A,0x01,0x00,0xA0, -0xE3,0x59,0x00,0x00,0xEB,0x0B,0x00,0x00,0xEA,0x07,0x00,0xD3,0xE5,0x01,0x00, -0x50,0xE3,0x03,0x00,0x00,0x0A,0x3C,0x01,0x9F,0xE5,0x10,0x10,0xA0,0xE3,0x00, -0x10,0xC0,0xE5,0x07,0x00,0x00,0xEA,0x00,0x10,0xA0,0xE3,0x07,0x10,0xC3,0xE5, -0x24,0x01,0x9F,0xE5,0x10,0x10,0xA0,0xE3,0x00,0x10,0xC0,0xE5,0x14,0x31,0x9F, -0xE5,0x01,0x00,0xA0,0xE3,0x06,0x00,0xC3,0xE5,0xF0,0x40,0xBD,0xE8,0x1E,0xFF, -0x2F,0xE1,0x78,0x47,0x00,0x00,0xF0,0x40,0x2D,0xE9,0xFC,0x00,0x9F,0xE5,0x00, -0x10,0xD0,0xE5,0x01,0x00,0x51,0xE3,0x39,0x00,0x00,0x1A,0xF0,0x30,0x9F,0xE5, -0x35,0x30,0xD3,0xE5,0x01,0x00,0x53,0xE3,0x00,0x00,0x00,0xCA,0x04,0x00,0x00, -0xEA,0xE0,0x20,0x9F,0xE5,0x01,0x20,0x82,0xE3,0x0F,0xE0,0xA0,0xE1,0x12,0xFF, -0x2F,0xE1,0x78,0x47,0x00,0x00,0xC4,0x00,0x9F,0xE5,0x00,0x10,0xA0,0xE3,0x00, -0x10,0xC0,0xE5,0xB4,0x00,0x9F,0xE5,0x06,0x10,0xD0,0xE5,0x00,0x00,0x51,0xE3, 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+0x00,0x20,0xFF,0xF7,0x85,0xFE,0x00,0x20,0xB8,0x70,0xB8,0x78,0x40,0x08,0x40, +0x00,0xB8,0x70,0xB8,0x78,0x08,0x23,0x98,0x43,0xB8,0x70,0x80,0xBD,0x80,0x00, +0x00,0x04,0x08,0x01,0x00,0x02,0x84,0x00,0x00,0x02,0x50,0x09,0x00,0x02,0x80, +0xB5,0xF8,0xF7,0x67,0xFE,0x08,0x48,0x01,0x21,0x41,0x60,0x41,0x7F,0x10,0x30, +0x00,0x27,0x01,0x29,0x00,0xD1,0x47,0x73,0x01,0x20,0xF6,0xF7,0x97,0xFD,0x03, +0x48,0x07,0x83,0x87,0x82,0x80,0xBD,0x00,0x00,0x50,0x09,0x00,0x02,0x20,0x00, +0x20,0x0F,0x80,0xB5,0x0F,0x48,0x40,0x23,0x81,0x69,0x0E,0x4F,0x99,0x43,0x81, +0x61,0xF8,0x69,0x9B,0x01,0x18,0x43,0xF8,0x61,0x14,0x20,0xF6,0xF7,0x6A,0xFD, +0xF8,0x69,0x0A,0x4B,0x0A,0x49,0x18,0x40,0xF8,0x61,0x01,0x20,0x08,0x72,0x4A, +0x7A,0x06,0x2A,0x00,0xD0,0x48,0x72,0x08,0x73,0x00,0x20,0xC8,0x72,0x05,0x49, +0x08,0x70,0x80,0xBD,0x00,0x00,0x80,0x00,0x00,0x04,0x40,0x00,0x00,0x04,0xFF, +0xEF,0x00,0x00,0x50,0x09,0x00,0x02,0xE8,0x01,0x00,0x02,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 }; diff --git a/sys/dev/microcode/atmel/atu-license b/sys/dev/microcode/atmel/atu-license index ccf68add0..a5cd2239d 100644 --- a/sys/dev/microcode/atmel/atu-license +++ b/sys/dev/microcode/atmel/atu-license @@ -7,7 +7,7 @@ * and/or other materials provided with the distribution; and * 3. The name of Atmel Corporation may not be used to endorse or promote products * derived from this Firmware without specific prior written consent. - * + * * DISCLAIMER: ATMEL PROVIDES THIS FIRMWARE "AS IS'' WITH NO WARRANTIES * OR INDEMNITIES WHATSOEVER. ATMEL EXPRESSLY DISCLAIMS ANY * EXPRESS, STATUTORY OR IMPLIED WARRANTIES, INCLUDING, BUT NOT @@ -20,7 +20,7 @@ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * FIRMWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * * USER ACKNOWLEDGES AND AGREES THAT THE PURCHASE OR USE OF THE * FIRMWARE WILL NOT CREATE OR GIVE GROUNDS FOR A LICENSE BY * IMPLICATION, ESTOPPEL, OR OTHERWISE IN ANY INTELLECTUAL PROPERTY diff --git a/sys/dev/microcode/bnx/bnxfw.h b/sys/dev/microcode/bnx/bnxfw.h index 63a1335f5..79df92c4d 100644 --- a/sys/dev/microcode/bnx/bnxfw.h +++ b/sys/dev/microcode/bnx/bnxfw.h @@ -11087,7 +11087,7 @@ static u_int32_t bnx_xi_rv2p_proc2[] = { 0x00000010, 0x001f0000, 0x00000018, 0x8000fe35, }; - + static u_int32_t bnx_xi90_rv2p_proc1[] = { 0x00000010, 0xb1800006, diff --git a/sys/dev/microcode/cyclades/cyzfirm.h b/sys/dev/microcode/cyclades/cyzfirm.h index 8a2d6ad56..c1814ff68 100644 --- a/sys/dev/microcode/cyclades/cyzfirm.h +++ b/sys/dev/microcode/cyclades/cyzfirm.h @@ -12,13441 +12,13441 @@ #define _CYZFIRM_H_ static const u_int8_t cycladesz_firmware[] = { - 0x43, 0x79, 0x63, 0x6c, 0x6f, 0x6d, 0x2d, 0x5a, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x4d, 0x6f, 0x6e, 0x20, 0x53, 0x65, - 0x70, 0x20, 0x32, 0x37, 0x20, 0x31, 0x33, 0x3a, 0x33, 0x32, - 0x3a, 0x33, 0x33, 0x20, 0x31, 0x39, 0x39, 0x39, 0x0a, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x63, 0x29, 0x31, - 0x39, 0x39, 0x37, 0x2c, 0x43, 0x79, 0x63, 0x6c, 0x61, 0x64, - 0x65, 0x73, 0x5f, 0x43, 0x6f, 0x72, 0x70, 0x2e, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, - 0x00, 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0x00, + 0x71, 0x00, 0x00, 0x00, 0x72, 0x00, 0x00, 0x00, 0x73, 0x00, + 0x00, 0x00, 0x74, 0x00, 0x00, 0x00, 0x75, 0x00, 0x00, 0x00, + 0x76, 0x00, 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x78, 0x00, + 0x00, 0x00, 0x79, 0x00, 0x00, 0x00, 0x7a, 0x00, 0x00, 0x00, + 0x7b, 0x00, 0x00, 0x00, 0x7c, 0x00, 0x00, 0x00, 0x7d, 0x00, + 0x00, 0x00, 0x7e, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x00, 0x81, 0x00, 0x00, 0x00, 0x82, 0x00, + 0x00, 0x00, 0x83, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x00, + 0x85, 0x00, 0x00, 0x00, 0x86, 0x00, 0x00, 0x00, 0x87, 0x00, + 0x00, 0x00, 0x88, 0x00, 0x00, 0x00, 0x89, 0x00, 0x00, 0x00, + 0x8a, 0x00, 0x00, 0x00, 0x8b, 0x00, 0x00, 0x00, 0x8c, 0x00, + 0x00, 0x00, 0x8d, 0x00, 0x00, 0x00, 0x8e, 0x00, 0x00, 0x00, + 0x8f, 0x00, 0x00, 0x00, 0x90, 0x00, 0x00, 0x00, 0x91, 0x00, + 0x00, 0x00, 0x92, 0x00, 0x00, 0x00, 0x93, 0x00, 0x00, 0x00, + 0x94, 0x00, 0x00, 0x00, 0x95, 0x00, 0x00, 0x00, 0x96, 0x00, + 0x00, 0x00, 0x97, 0x00, 0x00, 0x00, 0x98, 0x00, 0x00, 0x00, + 0x99, 0x00, 0x00, 0x00, 0x9a, 0x00, 0x00, 0x00, 0x9b, 0x00, + 0x00, 0x00, 0x9c, 0x00, 0x00, 0x00, 0x9d, 0x00, 0x00, 0x00, + 0x9e, 0x00, 0x00, 0x00, 0x9f, 0x00, 0x00, 0x00, 0xa0, 0x00, + 0x00, 0x00, 0xa1, 0x00, 0x00, 0x00, 0xa2, 0x00, 0x00, 0x00, + 0xa3, 0x00, 0x00, 0x00, 0xa4, 0x00, 0x00, 0x00, 0xa5, 0x00, + 0x00, 0x00, 0xa6, 0x00, 0x00, 0x00, 0xa7, 0x00, 0x00, 0x00, + 0xa8, 0x00, 0x00, 0x00, 0xa9, 0x00, 0x00, 0x00, 0xaa, 0x00, + 0x00, 0x00, 0xab, 0x00, 0x00, 0x00, 0xac, 0x00, 0x00, 0x00, + 0xad, 0x00, 0x00, 0x00, 0xae, 0x00, 0x00, 0x00, 0xaf, 0x00, + 0x00, 0x00, 0xb0, 0x00, 0x00, 0x00, 0xb1, 0x00, 0x00, 0x00, + 0xb2, 0x00, 0x00, 0x00, 0xb3, 0x00, 0x00, 0x00, 0xb4, 0x00, + 0x00, 0x00, 0xb5, 0x00, 0x00, 0x00, 0xb6, 0x00, 0x00, 0x00, + 0xb7, 0x00, 0x00, 0x00, 0xb8, 0x00, 0x00, 0x00, 0xb9, 0x00, + 0x00, 0x00, 0xba, 0x00, 0x00, 0x00, 0xbb, 0x00, 0x00, 0x00, + 0xbc, 0x00, 0x00, 0x00, 0xbd, 0x00, 0x00, 0x00, 0xbe, 0x00, + 0x00, 0x00, 0xbf, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, + 0xc1, 0x00, 0x00, 0x00, 0xc2, 0x00, 0x00, 0x00, 0xc3, 0x00, + 0x00, 0x00, 0xc4, 0x00, 0x00, 0x00, 0xc5, 0x00, 0x00, 0x00, + 0xc6, 0x00, 0x00, 0x00, 0xc7, 0x00, 0x00, 0x00, 0xc8, 0x00, + 0x00, 0x00, 0xc9, 0x00, 0x00, 0x00, 0xca, 0x00, 0x00, 0x00, + 0xcb, 0x00, 0x00, 0x00, 0xcc, 0x00, 0x00, 0x00, 0xcd, 0x00, + 0x00, 0x00, 0xce, 0x00, 0x00, 0x00, 0xcf, 0x00, 0x00, 0x00, + 0xd0, 0x00, 0x00, 0x00, 0xd1, 0x00, 0x00, 0x00, 0xd2, 0x00, + 0x00, 0x00, 0xd3, 0x00, 0x00, 0x00, 0xd4, 0x00, 0x00, 0x00, + 0xd5, 0x00, 0x00, 0x00, 0xd6, 0x00, 0x00, 0x00, 0xd7, 0x00, + 0x00, 0x00, 0xd8, 0x00, 0x00, 0x00, 0xd9, 0x00, 0x00, 0x00, + 0xda, 0x00, 0x00, 0x00, 0xdb, 0x00, 0x00, 0x00, 0xdc, 0x00, + 0x00, 0x00, 0xdd, 0x00, 0x00, 0x00, 0xde, 0x00, 0x00, 0x00, + 0xdf, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0xe1, 0x00, + 0x00, 0x00, 0xe2, 0x00, 0x00, 0x00, 0xe3, 0x00, 0x00, 0x00, + 0xe4, 0x00, 0x00, 0x00, 0xe5, 0x00, 0x00, 0x00, 0xe6, 0x00, + 0x00, 0x00, 0xe7, 0x00, 0x00, 0x00, 0xe8, 0x00, 0x00, 0x00, + 0xe9, 0x00, 0x00, 0x00, 0xea, 0x00, 0x00, 0x00, 0xeb, 0x00, + 0x00, 0x00, 0xec, 0x00, 0x00, 0x00, 0xed, 0x00, 0x00, 0x00, + 0xee, 0x00, 0x00, 0x00, 0xef, 0x00, 0x00, 0x00, 0xf0, 0x00, + 0x00, 0x00, 0xf1, 0x00, 0x00, 0x00, 0xf2, 0x00, 0x00, 0x00, + 0xf3, 0x00, 0x00, 0x00, 0xf4, 0x00, 0x00, 0x00, 0xf5, 0x00, + 0x00, 0x00, 0xf6, 0x00, 0x00, 0x00, 0xf7, 0x00, 0x00, 0x00, + 0xf8, 0x00, 0x00, 0x00, 0xf9, 0x00, 0x00, 0x00, 0xfa, 0x00, + 0x00, 0x00, 0xfb, 0x00, 0x00, 0x00, 0xfc, 0x00, 0x00, 0x00, + 0xfd, 0x00, 0x00, 0x00, 0xfe, 0x00, 0x00, 0x00, 0xff, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x74, 0x74, 0x79, 0x30, 0x00, 0x00, 0x00, 0x00, + 0x72, 0x00, 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x28, 0x4e, + 0x61, 0x4e, 0x29, 0x00, 0x00, 0x00, 0x28, 0x53, 0x4e, 0x61, + 0x4e, 0x29, 0x00, 0x00, 0x28, 0x6e, 0x75, 0x6c, 0x6c, 0x29, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; #endif /* _CYZFIRM_H_ */ diff --git a/sys/dev/microcode/esa/esadsp.h b/sys/dev/microcode/esa/esadsp.h index 632890d7d..168363245 100644 --- a/sys/dev/microcode/esa/esadsp.h +++ b/sys/dev/microcode/esa/esadsp.h @@ -28,7 +28,7 @@ /* * ESS Allegro-1 / Maestro3 Audio Driver - * + * * Lots of magic based on the FreeBSD maestro3 driver and * reverse engineering. * Original driver by Don Kim. diff --git a/sys/dev/microcode/fxp/rcvbundl.h b/sys/dev/microcode/fxp/rcvbundl.h index 538385559..fd4747ee4 100644 --- a/sys/dev/microcode/fxp/rcvbundl.h +++ b/sys/dev/microcode/fxp/rcvbundl.h @@ -1,22 +1,22 @@ /* $OpenBSD: rcvbundl.h,v 1.2 2005/04/24 20:41:34 brad Exp $ */ /* -Copyright (c) 1999-2001, Intel Corporation +Copyright (c) 1999-2001, Intel Corporation All rights reserved. -Redistribution and use in source and binary forms, with or without +Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - 1. Redistributions of source code must retain the above copyright notice, + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation + this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - 3. Neither the name of Intel Corporation nor the names of its contributors - may be used to endorse or promote products derived from this software + 3. Neither the name of Intel Corporation nor the names of its contributors + may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' @@ -25,10 +25,10 @@ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* rcvbundl.h @@ -38,7 +38,7 @@ Date: 05/30/2000 Version: 3.28 This file contains the loadable micro code arrays to implement receive bundling on the -D101 A-step, D101 B-step, D101M (B-step only), D101S, D102 B-step, +D101 A-step, D101 B-step, D101M (B-step only), D101S, D102 B-step, D102 B-step with TCO work around, D102 C-step and D102 E-step. Each controller has its own specific micro code array. The array for one controller @@ -92,7 +92,7 @@ rcvbundl.h file given above). * * The current default is 0xFF80, which masks out the lower 7 bits. * This means that any frame which is x7F (127) bytes or smaller -* will cause an immediate interrupt. Because this value must be a +* will cause an immediate interrupt. Because this value must be a * bit mask, there are only a few valid values that can be used. To * turn this feature off, the driver can write the value xFFFF to the * lower word of this instruction (in the same way that the other @@ -650,7 +650,7 @@ rcvbundl.h file given above). still need to be loaded. Before this happens, the hit addresses for the CPUSaver algorithm must be set to 0x1FFFF. The hit addresses for CPUSaver are (starting with 0, and remember that - + */ /* Parameter values for the D102 B-step */ @@ -809,7 +809,7 @@ rcvbundl.h file given above). /* This version is a fix to TCO bug. This version can be loaded instead the CPUSaver version by modifing the registry key "LoadTcoUCodeInsteadOfCpuSaver" - + */ @@ -967,8 +967,8 @@ rcvbundl.h file given above). #if 0 -// this uCode include the CPU Saver and the TCO work around -//for IP fregments. +// this uCode include the CPU Saver and the TCO work around +//for IP fregments. #endif #define D102_C_RCVBUNDLE_UCODE \ { \ diff --git a/sys/dev/microcode/isp/asm_1040.h b/sys/dev/microcode/isp/asm_1040.h index 82be749ad..537723a78 100644 --- a/sys/dev/microcode/isp/asm_1040.h +++ b/sys/dev/microcode/isp/asm_1040.h @@ -23,7 +23,7 @@ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ + */ /************************************************************************ * * diff --git a/sys/dev/microcode/isp/asm_1080.h b/sys/dev/microcode/isp/asm_1080.h index ce471273e..56e31ed48 100644 --- a/sys/dev/microcode/isp/asm_1080.h +++ b/sys/dev/microcode/isp/asm_1080.h @@ -23,7 +23,7 @@ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ + */ #ifndef ISP_TARGET_MODE /************************************************************************ diff --git a/sys/dev/microcode/isp/asm_12160.h b/sys/dev/microcode/isp/asm_12160.h index 70aab4a0b..142a6e5de 100644 --- a/sys/dev/microcode/isp/asm_12160.h +++ b/sys/dev/microcode/isp/asm_12160.h @@ -24,7 +24,7 @@ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ + */ /************************************************************************ * * diff --git a/sys/dev/microcode/isp/asm_2100.h b/sys/dev/microcode/isp/asm_2100.h index b5281131d..14001f683 100644 --- a/sys/dev/microcode/isp/asm_2100.h +++ b/sys/dev/microcode/isp/asm_2100.h @@ -23,7 +23,7 @@ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ + */ /* * Some very early boards have problems loading firmware that is larger than diff --git a/sys/dev/microcode/isp/asm_2200.h b/sys/dev/microcode/isp/asm_2200.h index 07c454b4f..089c215f3 100644 --- a/sys/dev/microcode/isp/asm_2200.h +++ b/sys/dev/microcode/isp/asm_2200.h @@ -24,7 +24,7 @@ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ + */ /************************************************************************ * * diff --git a/sys/dev/microcode/isp/asm_2300.h b/sys/dev/microcode/isp/asm_2300.h index 367c2ce63..6cbce5c2a 100644 --- a/sys/dev/microcode/isp/asm_2300.h +++ b/sys/dev/microcode/isp/asm_2300.h @@ -24,7 +24,7 @@ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ + */ /************************************************************************ * * diff --git a/sys/dev/microcode/isp/asm_2400.h b/sys/dev/microcode/isp/asm_2400.h index 6ce5691d1..a0ee59269 100644 --- a/sys/dev/microcode/isp/asm_2400.h +++ b/sys/dev/microcode/isp/asm_2400.h @@ -24,7 +24,7 @@ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ + */ /************************************************************************ * --- ISP2400 Initiator/Target Firmware with support --- * diff --git a/sys/dev/microcode/isp/asm_2500.h b/sys/dev/microcode/isp/asm_2500.h index 6b2a14ce9..683d8c76f 100644 --- a/sys/dev/microcode/isp/asm_2500.h +++ b/sys/dev/microcode/isp/asm_2500.h @@ -23,7 +23,7 @@ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ + */ /* ******************************************************************** * * * * ISP2500 Firmware * diff --git a/sys/dev/microcode/isp/asm_sbus.h b/sys/dev/microcode/isp/asm_sbus.h index f5c855565..9cb94336d 100644 --- a/sys/dev/microcode/isp/asm_sbus.h +++ b/sys/dev/microcode/isp/asm_sbus.h @@ -24,7 +24,7 @@ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ + */ #define ISP_1000_RISC_CODE isp_1000_risc_code #ifndef ISP_TARGET_MODE diff --git a/sys/dev/microcode/myx/eth_z8e.h b/sys/dev/microcode/myx/eth_z8e.h index b83621226..06a8fcb9d 100644 --- a/sys/dev/microcode/myx/eth_z8e.h +++ b/sys/dev/microcode/myx/eth_z8e.h @@ -30,7 +30,7 @@ $FreeBSD$ static unsigned int eth_z8e_uncompressed_length = 377284 ; static unsigned int eth_z8e_length = 120629 ; -static unsigned char eth_z8e[120629 + 1] = +static unsigned char eth_z8e[120629 + 1] = "\x78\x9c\xec\xbd\x7f\x78\x54\xd5\xb5\x3f\xbc\x32\x19\x60\x12\x03" "\x13\x31\xe2\x94\x62\x1d\x2d\xd8\x68\x51\x82\x62\x4d\x2d\x68\x14" "\xd0\xa8\xfc\x88\x8a\x6d\x54\x34\xa0\x01\x83\x46\x88\x10\x61\x80" diff --git a/sys/dev/microcode/myx/ethp_z8e.h b/sys/dev/microcode/myx/ethp_z8e.h index 3da83416c..f42114c93 100644 --- a/sys/dev/microcode/myx/ethp_z8e.h +++ b/sys/dev/microcode/myx/ethp_z8e.h @@ -30,7 +30,7 @@ $FreeBSD$ static unsigned int ethp_z8e_uncompressed_length = 387604 ; static unsigned int ethp_z8e_length = 121317 ; -static unsigned char ethp_z8e[121317 + 1] = +static unsigned char ethp_z8e[121317 + 1] = "\x78\x9c\xec\xbd\x7f\x7c\x54\xc5\xd5\x3f\x7e\xb2\x59\x60\x13\x03" "\x1b\x31\xe2\x96\x62\x5d\x2d\xd8\x68\x51\x82\x62\x4d\x2d\x68\x14" "\xd0\xa8\xfc\x88\x4a\xdb\xa8\x68\x82\x06\x0c\x1a\x21\x42\x80\x05" diff --git a/sys/dev/microcode/rum/microcode.h b/sys/dev/microcode/rum/microcode.h index e8edc9302..35e3eec8c 100644 --- a/sys/dev/microcode/rum/microcode.h +++ b/sys/dev/microcode/rum/microcode.h @@ -209,7 +209,7 @@ static const uint8_t rt2573[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x07, - 0x29, 0xe9 + 0x29, 0xe9 }; static const uint8_t rt2870[] = { diff --git a/sys/dev/microcode/siop/ncr53cxxx.c b/sys/dev/microcode/siop/ncr53cxxx.c index b7730981b..44a7806c3 100644 --- a/sys/dev/microcode/siop/ncr53cxxx.c +++ b/sys/dev/microcode/siop/ncr53cxxx.c @@ -161,7 +161,7 @@ struct ncrregs regs[] = { {"sbdl", {0x0a, 0x0a, -1, -1, -1}}, {"socl", { -1, -1, 0x09, 0x09, 0x09}}, {"ssid", { -1, -1, 0x0a, 0x0a, 0x0a}}, - {"sbcl", {0x0b, 0x0b, 0x0b, 0x0b, 0x0b}}, + {"sbcl", {0x0b, 0x0b, 0x0b, 0x0b, 0x0b}}, {"dstat", {0x0c, 0x0c, 0x0c, 0x0c, 0x0c}}, {"sstat0", {0x0d, 0x0d, 0x0d, 0x0d, 0x0d}}, {"sstat1", {0x0e, 0x0e, 0x0e, 0x0e, 0x0e}}, @@ -1113,7 +1113,7 @@ void loadstore(int i) int reg, size; reg = CheckRegister(i); - if (reg < 0) + if (reg < 0) errout ("Expected register"); else inst0 |= reg << 16; @@ -1481,7 +1481,7 @@ char * makefn (base, sub) char *sub; { char *fn; - size_t len = strlen (base) + strlen (sub) + 2; + size_t len = strlen (base) + strlen (sub) + 2; fn = malloc (len); strlcpy (fn, base, len); diff --git a/sys/dev/microcode/siop/osiop.ss b/sys/dev/microcode/siop/osiop.ss index f477647bd..dc374708e 100644 --- a/sys/dev/microcode/siop/osiop.ss +++ b/sys/dev/microcode/siop/osiop.ss @@ -1,4 +1,4 @@ -; $OpenBSD: osiop.ss,v 1.3 2023/01/04 10:05:44 jsg Exp $ +; $OpenBSD: osiop.ss,v 1.3 2023/01/04 10:05:44 jsg Exp $ ; $NetBSD: osiop.ss,v 1.1 2001/04/30 04:47:51 tsutsui Exp $ ; diff --git a/sys/dev/microcode/symbol/spectrum24t_cf.h b/sys/dev/microcode/symbol/spectrum24t_cf.h index 9b09ed8cd..fb1d411f6 100644 --- a/sys/dev/microcode/symbol/spectrum24t_cf.h +++ b/sys/dev/microcode/symbol/spectrum24t_cf.h @@ -24,7 +24,7 @@ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ + */ /* * Firmware for Symbol Wireless Networker Spectrum24t CF card. diff --git a/sys/dev/microcode/tht/microcode.h b/sys/dev/microcode/tht/microcode.h index 32114724d..28d2ab390 100644 --- a/sys/dev/microcode/tht/microcode.h +++ b/sys/dev/microcode/tht/microcode.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2007 Tehuti Networks. + * Copyright (c) 2007 Tehuti Networks. * * All rights reserved. * diff --git a/sys/dev/microcode/tht/tht-license b/sys/dev/microcode/tht/tht-license index d06dfcb73..ad14ccaf4 100644 --- a/sys/dev/microcode/tht/tht-license +++ b/sys/dev/microcode/tht/tht-license @@ -1,4 +1,4 @@ -Copyright (c) 2007 Tehuti Networks. +Copyright (c) 2007 Tehuti Networks. All rights reserved. diff --git a/sys/dev/microcode/tigon/ti_fw.h b/sys/dev/microcode/tigon/ti_fw.h index e5c4abb77..05ced1619 100644 --- a/sys/dev/microcode/tigon/ti_fw.h +++ b/sys/dev/microcode/tigon/ti_fw.h @@ -21,4580 +21,4580 @@ static const int tigonFwSbssLen = 0x38; static const u_int32_t tigonFwBssAddr = 0x00015e20; static const int tigonFwBssLen = 0x2080; static const u_int32_t tigonFwText[] = { -0x10000003, -0x0, 0xd, 0xd, 0x3c1d0001, -0x8fbd5c94, 0x3a0f021, 0x3c100000, 0x26104000, -0xc00100c, 0x0, 0xd, 0x27bdffd8, -0x3c1cc000, 0x3c1b0013, 0x377bd800, 0xd021, -0x3c170013, 0x36f75418, 0x2e02021, 0x340583e8, -0xafbf0024, 0xc002488, 0xafb00020, 0xc0023e8, -0x0, 0x3c040001, 0x248451c4, 0x24050001, -0x2e03021, 0x3821, 0x3c100001, 0x26107ea0, -0xafb00010, 0xc002403, 0xafbb0014, 0x3c02000f, -0x3442ffff, 0x2021024, 0x362102b, 0x10400009, -0x24050003, 0x3c040001, 0x248451d0, 0x2003021, -0x3603821, 0x3c020010, 0xafa20010, 0xc002403, -0xafa00014, 0x2021, 0x3405c000, 0x3c010001, -0x370821, 0xa02083b0, 0x3c010001, 0x370821, -0xa02083b2, 0x3c010001, 0x370821, 0xa02083b3, -0x3c010001, 0x370821, 0xac2083b4, 0xa2e004d8, -0x418c0, 0x24840001, 0x771021, 0xac40727c, -0x771021, 0xac407280, 0x2e31021, 0xa445727c, -0x2c820020, 0x1440fff7, 0x418c0, 0x2021, -0x3405c000, 0x418c0, 0x24840001, 0x771021, -0xac40737c, 0x771021, 0xac407380, 0x2e31021, -0xa445737c, 0x2c820080, 0x5440fff7, 0x418c0, -0xaf800054, 0xaf80011c, 0x8f820044, 0x34420040, -0xaf820044, 0x8f820044, 0x34420020, 0xaf820044, -0x8f420218, 0x30420002, 0x10400009, 0x0, -0x8f420220, 0x3c030002, 0x34630004, 0x431025, -0xaee204c4, 0x8f42021c, 0x8001074, 0x34420004, -0x8f420220, 0x3c030002, 0x34630006, 0x431025, -0xaee204c4, 0x8f42021c, 0x34420006, 0xaee204cc, -0x8f420218, 0x30420010, 0x1040000a, 0x0, -0x8f42021c, 0x34420004, 0xaee204c8, 0x8f420220, -0x3c03000a, 0x34630004, 0x431025, 0x800108a, -0xaee204c0, 0x8f420220, 0x3c03000a, 0x34630006, -0x431025, 0xaee204c0, 0x8f42021c, 0x34420006, -0xaee204c8, 0x8f420218, 0x30420200, 0x10400003, -0x24020001, 0x8001091, 0xa2e27248, 0xa2e07248, -0x24020001, 0xaf8200a0, 0xaf8200b0, 0x8f830054, -0x8f820054, 0x8001099, 0x24630064, 0x8f820054, -0x621023, 0x2c420065, 0x1440fffc, 0x0, -0xaf800044, 0x8f420208, 0x8f43020c, 0xaee20010, -0xaee30014, 0x8ee40010, 0x8ee50014, 0x26e20030, -0xaee20028, 0x24020490, 0xaee20018, 0xaf840090, -0xaf850094, 0x8ee20028, 0xaf8200b4, 0x96e2001a, -0xaf82009c, 0x8f8200b0, 0x8ee304cc, 0x431025, -0xaf8200b0, 0x8f8200b0, 0x30420004, 0x1440fffd, -0x0, 0x8ee20450, 0x8ee30454, 0xaee304fc, -0x8ee204fc, 0x2442e000, 0x2c422001, 0x1440000d, -0x26e40030, 0x8ee20450, 0x8ee30454, 0x3c040001, -0x248451dc, 0x3c050001, 0xafa00010, 0xafa00014, -0x8ee704fc, 0x34a5f000, 0xc002403, 0x603021, -0x26e40030, 0xc002488, 0x24050400, 0x27440080, -0xc002488, 0x24050080, 0x26e4777c, 0xc002488, -0x24050400, 0x8f42025c, 0x26e40094, 0xaee20060, -0x8f420260, 0x27450200, 0x24060008, 0xaee20068, -0x24020006, 0xc00249a, 0xaee20064, 0x3c023b9a, -0x3442ca00, 0x2021, 0x24030002, 0xaee30074, -0xaee30070, 0xaee2006c, 0x240203e8, 0xaee20104, -0x24020001, 0xaee30100, 0xaee2010c, 0x3c030001, -0x641821, 0x90635c60, 0x2e41021, 0x24840001, -0xa043009c, 0x2c82000f, 0x1440fff8, 0x0, -0x8f820040, 0x2e41821, 0x24840001, 0x21702, -0x24420030, 0xa062009c, 0x2e41021, 0xa040009c, -0x96e2046a, 0x30420003, 0x14400009, 0x0, -0x96e2047a, 0x30420003, 0x50400131, 0x3c030800, -0x96e2046a, 0x30420003, 0x1040002a, 0x3c020700, -0x96e2047a, 0x30420003, 0x10400026, 0x3c020700, -0x96e3047a, 0x96e2046a, 0x14620022, 0x3c020700, -0x8ee204c0, 0x24030001, 0xa2e34e20, 0x34420e00, -0xaee204c0, 0x8f420218, 0x30420100, 0x10400005, -0x0, 0x3c020001, 0x2442e168, 0x800111d, -0x21100, 0x3c020001, 0x2442d35c, 0x21100, -0x21182, 0x3c030800, 0x431025, 0x3c010001, -0xac221238, 0x3c020001, 0x2442f680, 0x21100, -0x21182, 0x3c030800, 0x431025, 0x3c010001, -0xac221278, 0x8ee20000, 0x34424000, 0x8001238, -0xaee20000, 0x34423000, 0xafa20018, 0x8ee20608, -0x8f430228, 0x24420001, 0x304900ff, 0x512300e2, -0xafa00010, 0x8ee20608, 0x210c0, 0x571021, -0x8fa30018, 0x8fa4001c, 0xac43060c, 0xac440610, -0x8f870120, 0x27623800, 0x24e80020, 0x102102b, -0x50400001, 0x27683000, 0x8f820128, 0x11020004, -0x0, 0x8f820124, 0x15020007, 0x1021, -0x8ee201a4, 0x3021, 0x24420001, 0xaee201a4, -0x80011a0, 0x8ee201a4, 0x8ee40608, 0x420c0, -0x801821, 0x8ee40430, 0x8ee50434, 0xa32821, -0xa3302b, 0x822021, 0x862021, 0xace40000, -0xace50004, 0x8ee30608, 0x24020008, 0xa4e2000e, -0x2402000d, 0xace20018, 0xace9001c, 0x318c0, -0x2463060c, 0x2e31021, 0xace20008, 0x8ee204c4, -0xace20010, 0xaf880120, 0x92e24e20, 0x14400037, -0x24060001, 0x8ee24e30, 0x210c0, 0x24425038, -0x2e22021, 0x8c830000, 0x24020007, 0x1462001f, -0x0, 0x8ee34e30, 0x8ee24e34, 0x1062001b, -0x24030040, 0x8c820004, 0x24420001, 0xac820004, -0x8ee24e34, 0x8ee54e30, 0x24420001, 0x10430007, -0x0, 0x8ee24e34, 0x24420001, 0x10a20005, -0x0, 0x800118a, 0x0, 0x14a00005, -0x0, 0x8f820128, 0x24420020, 0xaf820128, -0x8f820128, 0x8c820004, 0x2c420011, 0x50400013, -0xac800000, 0x80011a0, 0x0, 0x8ee24e30, -0x24030040, 0x24420001, 0x50430003, 0x1021, -0x8ee24e30, 0x24420001, 0xaee24e30, 0x8ee24e30, -0x210c0, 0x24425038, 0x2e22021, 0x24020007, -0xac820000, 0x24020001, 0xac820004, 0x54c0000c, -0xaee90608, 0x3c040001, 0x248451e8, 0xafa00010, -0xafa00014, 0x8ee60608, 0x8f470228, 0x3c050009, -0xc002403, 0x34a5f000, 0x8001223, 0x0, -0x8f830120, 0x27623800, 0x24660020, 0xc2102b, -0x50400001, 0x27663000, 0x8f820128, 0x10c20004, -0x0, 0x8f820124, 0x14c20007, 0x0, -0x8ee201a4, 0x3021, 0x24420001, 0xaee201a4, -0x8001207, 0x8ee201a4, 0x8ee20608, 0xac62001c, -0x8ee404a0, 0x8ee504a4, 0x2462001c, 0xac620008, -0x24020008, 0xa462000e, 0x24020011, 0xac620018, -0xac640000, 0xac650004, 0x8ee204c4, 0xac620010, -0xaf860120, 0x92e24e20, 0x14400037, 0x24060001, -0x8ee24e30, 0x210c0, 0x24425038, 0x2e22021, -0x8c830000, 0x24020012, 0x1462001f, 0x0, -0x8ee34e30, 0x8ee24e34, 0x1062001b, 0x24030040, -0x8c820004, 0x24420001, 0xac820004, 0x8ee24e34, -0x8ee54e30, 0x24420001, 0x10430007, 0x0, -0x8ee24e34, 0x24420001, 0x10a20005, 0x0, -0x80011f1, 0x0, 0x14a00005, 0x0, -0x8f820128, 0x24420020, 0xaf820128, 0x8f820128, -0x8c820004, 0x2c420011, 0x50400013, 0xac800000, -0x8001207, 0x0, 0x8ee24e30, 0x24030040, -0x24420001, 0x50430003, 0x1021, 0x8ee24e30, -0x24420001, 0xaee24e30, 0x8ee24e30, 0x210c0, -0x24425038, 0x2e22021, 0x24020012, 0xac820000, -0x24020001, 0xac820004, 0x14c0001b, 0x0, -0x3c040001, 0x248451f0, 0xafa00010, 0xafa00014, -0x8ee60608, 0x8f470228, 0x3c050009, 0xc002403, -0x34a5f001, 0x8ee201b0, 0x24420001, 0xaee201b0, -0x8001223, 0x8ee201b0, 0x3c040001, 0x248451fc, -0xafa00014, 0x8ee60608, 0x8f470228, 0x3c050009, -0xc002403, 0x34a5f005, 0x8ee201ac, 0x24420001, -0xaee201ac, 0x8ee201ac, 0x8ee20160, 0x3c040001, -0x24845208, 0x3405f001, 0x24420001, 0xaee20160, -0x8ee20160, 0x3021, 0x3821, 0xafa00010, -0xc002403, 0xafa00014, 0x8001238, 0x0, -0x3c020001, 0x2442f5a8, 0x21100, 0x21182, -0x431025, 0x3c010001, 0xac221278, 0x96e2045a, -0x30420003, 0x10400025, 0x3c050fff, 0x8ee204c8, -0x34a5ffff, 0x34420a00, 0xaee204c8, 0x8ee304c8, -0x3c040001, 0x24845214, 0x24020001, 0xa2e204ec, -0xa2e204ed, 0x3c020002, 0x621825, 0x3c020001, -0x2442a390, 0x451024, 0x21082, 0xaee304c8, -0x3c030800, 0x431025, 0x3c010001, 0xac221220, -0x3c020001, 0x2442add4, 0x451024, 0x21082, -0x431025, 0x3c010001, 0xac221280, 0x96e6045a, -0x3821, 0x24050011, 0xafa00010, 0xc002403, -0xafa00014, 0x8001268, 0x0, 0x3c020001, -0x2442a9d4, 0x21100, 0x21182, 0x3c030800, -0x431025, 0x3c010001, 0xac221280, 0x96e2046a, -0x30420010, 0x14400009, 0x0, 0x96e2047a, -0x30420010, 0x10400112, 0x0, 0x96e2046a, -0x30420010, 0x10400005, 0x3c020700, 0x96e2047a, -0x30420010, 0x14400102, 0x3c020700, 0x34423000, -0xafa20018, 0x8ee20608, 0x8f430228, 0x24420001, -0x304900ff, 0x512300e2, 0xafa00010, 0x8ee20608, -0x210c0, 0x571021, 0x8fa30018, 0x8fa4001c, -0xac43060c, 0xac440610, 0x8f870120, 0x27623800, -0x24e80020, 0x102102b, 0x50400001, 0x27683000, -0x8f820128, 0x11020004, 0x0, 0x8f820124, -0x15020007, 0x1021, 0x8ee201a4, 0x3021, -0x24420001, 0xaee201a4, 0x80012ea, 0x8ee201a4, -0x8ee40608, 0x420c0, 0x801821, 0x8ee40430, -0x8ee50434, 0xa32821, 0xa3302b, 0x822021, -0x862021, 0xace40000, 0xace50004, 0x8ee30608, -0x24020008, 0xa4e2000e, 0x2402000d, 0xace20018, -0xace9001c, 0x318c0, 0x2463060c, 0x2e31021, -0xace20008, 0x8ee204c4, 0xace20010, 0xaf880120, -0x92e24e20, 0x14400037, 0x24060001, 0x8ee24e30, -0x210c0, 0x24425038, 0x2e22021, 0x8c830000, -0x24020007, 0x1462001f, 0x0, 0x8ee34e30, -0x8ee24e34, 0x1062001b, 0x24030040, 0x8c820004, -0x24420001, 0xac820004, 0x8ee24e34, 0x8ee54e30, -0x24420001, 0x10430007, 0x0, 0x8ee24e34, -0x24420001, 0x10a20005, 0x0, 0x80012d4, -0x0, 0x14a00005, 0x0, 0x8f820128, -0x24420020, 0xaf820128, 0x8f820128, 0x8c820004, -0x2c420011, 0x50400013, 0xac800000, 0x80012ea, -0x0, 0x8ee24e30, 0x24030040, 0x24420001, -0x50430003, 0x1021, 0x8ee24e30, 0x24420001, -0xaee24e30, 0x8ee24e30, 0x210c0, 0x24425038, -0x2e22021, 0x24020007, 0xac820000, 0x24020001, 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0x8ee24e2c, 0x1062001b, 0x24030040, -0x8c820004, 0x24420001, 0xac820004, 0x8ee24e2c, -0x8ee54e28, 0x24420001, 0x10430007, 0x0, -0x8ee24e2c, 0x24420001, 0x10a20005, 0x0, -0x80029a9, 0x0, 0x14a00005, 0x0, -0x8f820108, 0x24420020, 0xaf820108, 0x8f820108, -0x8c820004, 0x2c420011, 0x50400013, 0xac800000, -0x80029bf, 0x0, 0x8ee24e28, 0x24030040, -0x24420001, 0x50430003, 0x1021, 0x8ee24e28, -0x24420001, 0xaee24e28, 0x8ee24e28, 0x210c0, -0x24424e38, 0x2e22021, 0x24020005, 0xac820000, -0x24020001, 0xac820004, 0x1540000a, 0x24020001, -0xafa90010, 0x8ee27264, 0x3c040001, 0x24845750, -0x3c050004, 0xafa20014, 0x8ee604e4, 0x8002a4f, -0x34a5f204, 0xa2e204ed, 0x8ee204e8, 0x8ee304fc, -0x8ee47258, 0x3c060001, 0x34c63800, 0x3c010001, -0x370821, 0xac2083d8, 0x3c010001, 0x370821, -0xac2083dc, 0x21100, 0x431021, 0xac44000c, -0x8ee27264, 0x2405fff8, 0x30e3ffff, 0x431021, -0x24420007, 0x451024, 0x24630007, 0xaee27258, -0x8ee2726c, 0x8ee47258, 0x651824, 0x431023, -0xaee2726c, 0x3661021, 0x82202b, 0x14800004, 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0x1021, 0x8ee24e2c, 0x24420001, -0x210c0, 0x24424e38, 0x2e22021, 0x8c820004, -0x8f830108, 0x21140, 0x621821, 0xaf830108, -0xac800000, 0x8cc20018, 0x2443fffe, 0x2c620013, -0x104000c1, 0x31080, 0x3c010001, 0x220821, -0x8c225790, 0x400008, 0x0, 0x8ee204f0, -0x471021, 0xaee204f0, 0x8ee204f0, 0x8f43023c, -0x43102b, 0x144000be, 0x0, 0x8ee304e4, -0x8ee204f8, 0x506200ba, 0xa2e004f4, 0x8f830120, -0x27623800, 0x24660020, 0xc2102b, 0x50400001, -0x27663000, 0x8f820128, 0x10c20004, 0x0, -0x8f820124, 0x14c20007, 0x0, 0x8ee201a4, -0x8021, 0x24420001, 0xaee201a4, 0x8002b12, -0x8ee201a4, 0x8ee204e4, 0xac62001c, 0x8ee404b0, -0x8ee504b4, 0x2462001c, 0xac620008, 0x24020008, -0xa462000e, 0x24020011, 0xac620018, 0xac640000, -0xac650004, 0x8ee204c4, 0xac620010, 0xaf860120, -0x92e24e20, 0x14400037, 0x24100001, 0x8ee24e30, -0x210c0, 0x24425038, 0x2e22021, 0x8c830000, -0x24020012, 0x1462001f, 0x0, 0x8ee34e30, -0x8ee24e34, 0x1062001b, 0x24030040, 0x8c820004, -0x24420001, 0xac820004, 0x8ee24e34, 0x8ee54e30, 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0x3c020001, 0x571021, -0x904283b1, 0x10400014, 0x0, 0x8ee201d0, -0x8ee35240, 0x441021, 0xaee201d0, 0x8ee201d8, -0x641821, 0x306300ff, 0x8002b59, 0xaee35240, -0x8ee201cc, 0x8ee30e10, 0x441021, 0xaee201cc, -0x8ee201d8, 0x641821, 0x306301ff, 0xaee30e10, -0x441021, 0xaee201d8, 0x8ee20000, 0x34420040, -0x8002b71, 0xaee20000, 0x8ee2014c, 0x3c010001, -0x370821, 0xa02083e0, 0x24420001, 0xaee2014c, -0x8002b71, 0x8ee2014c, 0x94c7000e, 0x8cc2001c, -0x3c040001, 0x24845780, 0xafa60014, 0xafa20010, -0x8cc60018, 0x3c050008, 0xc002403, 0x34a50910, -0x8fbf001c, 0x8fb00018, 0x3e00008, 0x27bd0020, -0x27bdff98, 0xafbf0060, 0xafbe005c, 0xafb60058, -0xafb50054, 0xafb40050, 0xafb3004c, 0xafb20048, -0xafb10044, 0xafb00040, 0x8f830108, 0x8f820104, -0xafa00024, 0x106203e7, 0xafa0002c, 0x3c1e0001, -0x37de3800, 0x3c0bffff, 0x8f930108, 0x8e620018, -0x8f830104, 0x2443fffe, 0x2c620014, 0x104003cf, -0x31080, 0x3c010001, 0x220821, 0x8c2257e0, -0x400008, 0x0, 0x9663000e, 0x8ee2725c, -0x8ee404f0, 0x431021, 0xaee2725c, 0x8e63001c, -0x96e20458, 0x24840001, 0xaee404f0, 0x24630001, -0x2442ffff, 0x621824, 0xaee304e4, 0x8f42023c, -0x82202b, 0x148003b9, 0x0, 0x8f830120, -0x27623800, 0x24660020, 0xc2102b, 0x50400001, -0x27663000, 0x8f820128, 0x10c20004, 0x0, -0x8f820124, 0x14c20007, 0x0, 0x8ee201a4, -0x8021, 0x24420001, 0xaee201a4, 0x8002bfe, -0x8ee201a4, 0x8ee204e4, 0xac62001c, 0x8ee404b0, -0x8ee504b4, 0x2462001c, 0xac620008, 0x24020008, -0xa462000e, 0x24020011, 0xac620018, 0xac640000, -0xac650004, 0x8ee204c4, 0xac620010, 0xaf860120, -0x92e24e20, 0x14400037, 0x24100001, 0x8ee24e30, -0x210c0, 0x24425038, 0x2e22021, 0x8c830000, -0x24020012, 0x1462001f, 0x0, 0x8ee34e30, -0x8ee24e34, 0x1062001b, 0x240c0040, 0x8c820004, -0x24420001, 0xac820004, 0x8ee24e34, 0x8ee34e30, -0x24420001, 0x104c0007, 0x0, 0x8ee24e34, -0x24420001, 0x10620005, 0x0, 0x8002be8, -0x0, 0x14600005, 0x0, 0x8f820128, -0x24420020, 0xaf820128, 0x8f820128, 0x8c820004, -0x2c420011, 0x50400013, 0xac800000, 0x8002bfe, -0x0, 0x8ee24e30, 0x240c0040, 0x24420001, -0x504c0003, 0x1021, 0x8ee24e30, 0x24420001, -0xaee24e30, 0x8ee24e30, 0x210c0, 0x24425038, -0x2e22021, 0x24020012, 0x240c0001, 0xac820000, -0xac8c0004, 0x5600000d, 0x24100001, 0x8ee204e4, -0x3c040001, 0x24845774, 0xafa00014, 0xafa20010, -0x8ee60608, 0x8f470228, 0x3c050009, 0x34a5f006, -0xc002403, 0xafab0038, 0x8fab0038, 0x1200030a, -0x240c0001, 0x8002f19, 0x0, 0x966c001c, -0xafac002c, 0x9662001e, 0x3c0c8000, 0xafac0024, -0xae62001c, 0x8e75001c, 0x8ee204fc, 0x8ee404fc, -0x151900, 0x621021, 0x8c52000c, 0x92e27b98, -0x641821, 0x9476000a, 0x14400003, 0x32c20002, -0xaef27ba4, 0xaef57b9c, 0x1040004b, 0x8021, -0x96e2045a, 0x30420002, 0x10400047, 0x0, -0x8e63001c, 0x8ee204fc, 0x32100, 0x821021, -0x8c42000c, 0x37e1821, 0x24420022, 0x43102b, -0x1440000a, 0x24050014, 0x8ee204fc, 0x821021, -0x8c44000c, 0xafab0038, 0xc002f75, 0x2484000e, -0x8fab0038, 0x8002c52, 0x3050ffff, 0x8ee204fc, -0x821021, 0x8c42000c, 0x9450000e, 0x94430010, -0x94440012, 0x94450014, 0x2038021, 0x2048021, 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+0x3c010001, 0xac205de8, 0x78940, 0x3c010001, +0x310821, 0xac307e88, 0x3c024000, 0x2021024, +0x14400016, 0x0, 0x3c020001, 0x8c425de8, +0x10400008, 0x24040004, 0x24050001, 0xc004d93, +0x24062000, 0x24020001, 0x3c010001, 0x370821, +0xac2283ac, 0x3c020001, 0x511021, 0x8c427e80, +0x3c03bfff, 0x3463ffff, 0x431024, 0x3c010001, +0x310821, 0x800529f, 0xac227e80, 0x3c020001, +0x8c425de8, 0x1040002b, 0x3c0300a0, 0x2031024, +0x1443000f, 0x3c020020, 0x3c020001, 0x8c425dec, +0x24030100, 0x3c010001, 0x310821, 0xac237e94, +0x3c030001, 0x3c010001, 0x310821, 0xac237e9c, +0x34420400, 0x3c010001, 0x800521b, 0xac225dec, +0x2021024, 0x1040000a, 0x24030100, 0x3c020001, +0x8c425dec, 0x3c010001, 0x310821, 0xac237e94, +0x34420800, 0x3c010001, 0x800521b, 0xac225dec, +0x3c020080, 0x2021024, 0x10400023, 0x3c030001, +0x3c020001, 0x8c425dec, 0x3c010001, 0x310821, +0xac237e9c, 0x34420c00, 0x3c010001, 0x800521b, +0xac225dec, 0x3c020020, 0x2021024, 0x10400006, +0x24020100, 0x3c010001, 0x310821, 0xac227e94, +0x800520f, 0x3c020080, 0x3c010001, 0x310821, +0xac207e94, 0x3c020080, 0x2021024, 0x10400006, +0x71940, 0x3c020001, 0x3c010001, 0x230821, +0x800521b, 0xac227e9c, 0x71140, 0x3c010001, +0x220821, 0xac207e9c, 0xc00429b, 0x0, +0x3c030001, 0x771821, 0x8c6383ac, 0x24020003, +0x1062007f, 0x24020001, 0x3c010001, 0xac225d0c, +0x3c010001, 0xac225d14, 0x3c010001, 0x80052a1, +0xac225d94, 0x3c02ffec, 0x3442ffff, 0x2028024, +0x3c020008, 0x2028025, 0x71140, 0x3c010001, +0x220821, 0xac307e88, 0x3c022000, 0x2021024, +0x10400009, 0x0, 0x3c020001, 0x8c425db4, +0x14400005, 0x24020001, 0x3c010001, 0xac225de8, +0x8005242, 0x3c024000, 0x3c010001, 0xac205de8, +0x3c024000, 0x2021024, 0x1440001c, 0x0, +0x3c020001, 0x8c425de8, 0x10400007, 0x24022020, +0x3c010001, 0xac225dec, 0x24020001, 0x3c010001, +0x370821, 0xac2283ac, 0x3c04bfff, 0x71940, +0x3c020001, 0x431021, 0x8c427e80, 0x3c050001, +0x8ca55d08, 0x3484ffff, 0x441024, 0x3c010001, +0x230821, 0xac227e80, 0x24020001, 0x10a20044, +0x0, 0x800529f, 0x0, 0x3c020001, +0x8c425de8, 0x1040001c, 0x24022000, 0x3c010001, +0xac225dec, 0x3c0300a0, 0x2031024, 0x14430005, +0x71140, 0x3402a000, 0x3c010001, 0x800529a, +0xac225dec, 0x3c030001, 0x621821, 0x8c637e88, +0x3c020020, 0x621024, 0x10400004, 0x24022001, +0x3c010001, 0x800529a, 0xac225dec, 0x3c020080, +0x621024, 0x1040001f, 0x3402a001, 0x3c010001, +0x800529a, 0xac225dec, 0x3c020020, 0x2021024, +0x10400007, 0x71940, 0x24020100, 0x3c010001, +0x230821, 0xac227e94, 0x800528e, 0x3c020080, +0x71140, 0x3c010001, 0x220821, 0xac207e94, +0x3c020080, 0x2021024, 0x10400006, 0x71940, +0x3c020001, 0x3c010001, 0x230821, 0x800529a, +0xac227e9c, 0x71140, 0x3c010001, 0x220821, +0xac207e9c, 0x3c030001, 0x8c635d08, 0x24020001, +0x10620003, 0x0, 0xc00429b, 0x0, +0x8fbf0024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, +0x3e00008, 0x27bd0028, 0x27bdffd8, 0xafb20020, +0x809021, 0xafb1001c, 0x8821, 0x24020002, +0xafbf0024, 0xafb00018, 0xa7a00012, 0x10a200d3, +0xa7a00010, 0x2ca20003, 0x10400005, 0x24020001, +0x10a2000a, 0x128140, 0x8005385, 0x2201021, +0x24020004, 0x10a2007d, 0x24020008, 0x10a2007c, +0x122940, 0x8005385, 0x2201021, 0x3c030001, +0x701821, 0x8c637e8c, 0x3c024000, 0x621024, +0x14400009, 0x24040001, 0x3c027fff, 0x3442ffff, +0x628824, 0x3c010001, 0x300821, 0xac317e84, +0x8005385, 0x2201021, 0x24050001, 0xc004980, +0x27a60010, 0x24040001, 0x24050001, 0xc004980, +0x27a60010, 0x97a20010, 0x30420004, 0x10400034, +0x3c114000, 0x3c020001, 0x8c425e0c, 0x2443ffff, +0x2c620007, 0x10400034, 0x31080, 0x3c010001, +0x220821, 0x8c225c20, 0x400008, 0x0, +0x24040001, 0x24050011, 0x27b00012, 0xc004980, +0x2003021, 0x24040001, 0x24050011, 0xc004980, +0x2003021, 0x97a50012, 0x30a24000, 0x10400002, +0x3c040010, 0x3c040008, 0x3c030001, 0x8005306, +0x30a28000, 0x24040001, 0x24050014, 0x27b00012, +0xc004980, 0x2003021, 0x24040001, 0x24050014, +0xc004980, 0x2003021, 0x97a50012, 0x30a21000, +0x10400002, 0x3c040010, 0x3c040008, 0x3c030001, +0x30a20800, 0x54400001, 0x3c030002, 0x3c028000, +0x2221025, 0x641825, 0x8005313, 0x438825, +0x3c110001, 0x2308821, 0x8e317e8c, 0x3c027fff, +0x3442ffff, 0x2228824, 0x3c020001, 0x8c425d18, +0x1040001d, 0x121140, 0x3c020001, 0x8c425de8, +0x10400002, 0x3c022000, 0x2228825, 0x121140, +0x3c010001, 0x220821, 0x8c227e90, 0x10400003, +0x3c020020, 0x8005327, 0x2228825, 0x3c02ffdf, +0x3442ffff, 0x2228824, 0x121140, 0x3c010001, +0x220821, 0x8c227e98, 0x10400003, 0x3c020080, +0x8005332, 0x2228825, 0x3c02ff7f, 0x3442ffff, +0x2228824, 0x121140, 0x3c010001, 0x220821, +0xac317e84, 0x8005385, 0x2201021, 0x122940, +0x3c030001, 0x651821, 0x8c637e88, 0x3c024000, +0x621024, 0x14400008, 0x3c027fff, 0x3442ffff, +0x628824, 0x3c010001, 0x250821, 0xac317e80, +0x8005385, 0x2201021, 0x3c020001, 0x8c425d18, +0x10400033, 0x3c11c00c, 0x3c020001, 0x8c425db4, +0x3c04c00c, 0x34842000, 0x3c030001, 0x8c635de8, +0x2102b, 0x21023, 0x441024, 0x10600003, +0x518825, 0x3c022000, 0x2228825, 0x3c020001, +0x451021, 0x8c427e94, 0x10400003, 0x3c020020, +0x8005362, 0x2228825, 0x3c02ffdf, 0x3442ffff, +0x2228824, 0x121140, 0x3c010001, 0x220821, +0x8c227e9c, 0x10400003, 0x3c020080, 0x800536d, +0x2228825, 0x3c02ff7f, 0x3442ffff, 0x2228824, +0x3c020001, 0x8c425da0, 0x10400002, 0x3c020800, +0x2228825, 0x3c020001, 0x8c425da4, 0x10400002, +0x3c020400, 0x2228825, 0x3c020001, 0x8c425da8, +0x10400006, 0x3c020100, 0x8005380, 0x2228825, +0x3c027fff, 0x3442ffff, 0x628824, 0x121140, +0x3c010001, 0x220821, 0xac317e80, 0x2201021, +0x8fbf0024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, +0x3e00008, 0x27bd0028, 0x27bdffd8, 0xafb40020, +0x80a021, 0xafbf0024, 0xafb3001c, 0xafb20018, +0xafb10014, 0xafb00010, 0x8f900200, 0x3c030001, +0x8c635d08, 0x8f930220, 0x24020002, 0x106200b4, +0x2c620003, 0x10400005, 0x24020001, 0x1062000a, +0x141940, 0x800544d, 0x0, 0x24020004, +0x1062005a, 0x24020008, 0x10620059, 0x149140, +0x800544d, 0x0, 0x3c040001, 0x832021, +0x8c847e8c, 0x3c110001, 0x2238821, 0x8e317e84, +0x3c024000, 0x821024, 0x1040003e, 0x3c020008, +0x2221024, 0x10400020, 0x36100002, 0x3c020001, +0x431021, 0x8c427e90, 0x10400005, 0x36100020, +0x36100100, 0x3c020020, 0x80053c2, 0x2228825, +0x2402feff, 0x2028024, 0x3c02ffdf, 0x3442ffff, +0x2228824, 0x141140, 0x3c010001, 0x220821, +0x8c227e98, 0x10400005, 0x3c020001, 0x2629825, +0x3c020080, 0x80053e1, 0x2228825, 0x3c02fffe, +0x3442ffff, 0x2629824, 0x3c02ff7f, 0x3442ffff, +0x80053e1, 0x2228824, 0x2402fedf, 0x2028024, +0x3c02fffe, 0x3442ffff, 0x2629824, 0x3c02ff5f, +0x3442ffff, 0x2228824, 0x3c010001, 0x230821, +0xac207e90, 0x3c010001, 0x230821, 0xac207e98, +0xc00489f, 0x0, 0xaf900200, 0xaf930220, +0x8f820220, 0x2403fffb, 0x431024, 0xaf820220, +0x8f820220, 0x34420002, 0xaf820220, 0x80053f8, +0x141140, 0x8f820200, 0x2403fffd, 0x431024, +0xc00489f, 0xaf820200, 0x3c02bfff, 0x3442ffff, +0xc00429b, 0x2228824, 0x141140, 0x3c010001, +0x220821, 0x800544d, 0xac317e84, 0x149140, +0x3c040001, 0x922021, 0x8c847e88, 0x3c110001, +0x2328821, 0x8e317e80, 0x3c024000, 0x821024, +0x14400011, 0x0, 0x3c020001, 0x8c425de8, +0x14400006, 0x3c02bfff, 0x8f820200, 0x34420002, +0xc00489f, 0xaf820200, 0x3c02bfff, 0x3442ffff, +0xc00429b, 0x2228824, 0x3c010001, 0x320821, +0x800544d, 0xac317e80, 0x3c020001, 0x8c425de8, +0x10400005, 0x3c020020, 0x3c020001, 0x8c425db4, +0x1040002b, 0x3c020020, 0x821024, 0x10400007, +0x36100020, 0x24020100, 0x3c010001, 0x320821, +0xac227e94, 0x800542d, 0x36100100, 0x3c010001, +0x320821, 0xac207e94, 0x2402feff, 0x2028024, +0x3c020080, 0x821024, 0x10400007, 0x141940, +0x3c020001, 0x3c010001, 0x230821, 0xac227e9c, +0x800543e, 0x2629825, 0x141140, 0x3c010001, +0x220821, 0xac207e9c, 0x3c02fffe, 0x3442ffff, +0x2629824, 0xc00489f, 0x0, 0xaf900200, +0xaf930220, 0x8f820220, 0x2403fffb, 0x431024, +0xaf820220, 0x8f820220, 0x34420002, 0xaf820220, +0x141140, 0x3c010001, 0x220821, 0xac317e80, +0x8fbf0024, 0x8fb40020, 0x8fb3001c, 0x8fb20018, +0x8fb10014, 0x8fb00010, 0x3e00008, 0x27bd0028, 0x0, 0x0, 0x0, 0x0 }; static const u_int32_t tigonFwRodata[] = { -0x24486561, 0x6465723a, 0x202f7072, -0x6f6a6563, 0x74732f72, 0x63732f73, 0x772f6765, -0x2f2e2f6e, 0x69632f66, 0x772f636f, 0x6d6d6f6e, -0x2f66776d, 0x61696e2e, 0x632c7620, 0x312e312e, -0x322e3131, 0x20313939, 0x382f3034, 0x2f323720, -0x32323a31, 0x333a3432, 0x20736875, 0x616e6720, -0x45787020, 0x24000000, 0x7468655f, 0x4441574e, -0x0, 0x53544143, 0x4b5f3120, 0x0, -0x42616453, 0x6e64526e, 0x67000000, 0x3f456e71, -0x45767400, 0x3f6e6f51, 0x64457650, 0x0, -0x6576526e, 0x6746756c, 0x6c000000, 0x496c6c43, -0x6f6e6652, 0x78000000, 0x53656e64, 0x436b5375, -0x6d000000, 0x52656376, 0x566c616e, 0x0, -0x0, 0x24486561, 0x6465723a, 0x202f7072, -0x6f6a6563, 0x74732f72, 0x63732f73, 0x772f6765, -0x2f2e2f6e, 0x69632f66, 0x772f636f, 0x6d6d6f6e, -0x2f74696d, 0x65722e63, 0x2c762031, 0x2e312e32, -0x2e382031, 0x3939382f, 0x30372f33, 0x31203137, -0x3a35383a, 0x34352073, 0x6875616e, 0x67204578, -0x70202400, 0x542d446d, 0x61526431, 0x0, -0x542d446d, 0x61424200, 0x542d446d, 0x61320000, -0x3f6e6f51, 0x64547845, 0x0, 0x3f6e6f51, -0x64527845, 0x0, 0x656e714d, 0x45765046, -0x61696c00, 0x656e714d, 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0x0, +0x0, 0xf678, 0xf678, 0xf678, +0xf678, 0xf678, 0xf678, 0xf678, +0xf678, 0xf678, 0xf678, 0xf678, +0xf678, 0xf678, 0xf678, 0xf678, +0xf670, 0xf670, 0xf670, 0x572d444d, +0x41456e46, 0x0, 0x0, 0xfdc0, +0x1015c, 0xfddc, 0x1015c, 0x1015c, +0x1015c, 0x1015c, 0x1015c, 0x1015c, +0xf704, 0x1015c, 0x1015c, 0x1015c, +0x1015c, 0x1015c, 0x10154, 0x10154, +0x10154, 0x24486561, 0x6465723a, 0x202f7072, +0x6f6a6563, 0x74732f72, 0x63732f73, 0x772f6765, +0x2f2e2f6e, 0x69632f66, 0x772f636f, 0x6d6d6f6e, +0x2f6d6163, 0x2e632c76, 0x20312e31, 0x2e322e31, +0x32203139, 0x39382f30, 0x342f3237, 0x2032323a, +0x31333a34, 0x32207368, 0x75616e67, 0x20457870, +0x20240000, 0x6d616374, 0x7841544e, 0x0, +0x4e745379, 0x6e264c6b, 0x0, 0x72656d61, +0x73737274, 0x0, 0x6c696e6b, 0x444f574e, +0x0, 0x656e714d, 0x45765046, 0x61696c00, +0x656e714d, 0x45764661, 0x696c0000, 0x6661696c, +0x456e454d, 0x0, 0x6c696e6b, 0x55500000, +0x0, 0x24486561, 0x6465723a, 0x202f7072, +0x6f6a6563, 0x74732f72, 0x63732f73, 0x772f6765, +0x2f2e2f6e, 0x69632f66, 0x772f636f, 0x6d6d6f6e, +0x2f636b73, 0x756d2e63, 0x2c762031, 0x2e312e32, +0x2e322031, 0x3939382f, 0x30342f32, 0x37203232, +0x3a31333a, 0x33392073, 0x6875616e, 0x67204578, +0x70202400, 0x50726f62, 0x65506879, 0x0, +0x6c6e6b41, 0x53535254, 0x0, 0x6e6f4863, +0x644c6b00, 0x11b5c, 0x11bf4, 0x11c28, +0x11c5c, 0x11c88, 0x11cfc, 0x11d38, +0x1214c, 0x11eb4, 0x11ef4, 0x11f20, +0x11f60, 0x11f90, 0x11fcc, 0x12000, +0x1214c, 0x12394, 0x123ac, 0x123d4, +0x123f4, 0x1241c, 0x1254c, 0x12574, +0x125c8, 0x125f0, 0x0, 0x0, +0x0, 0x1285c, 0x1292c, 0x12a04, +0x12ad4, 0x12b30, 0x12c0c, 0x12c48, +0x12d24, 0x12d4c, 0x12ef4, 0x12f1c, +0x130c4, 0x132bc, 0x13550, 0x13464, +0x13550, 0x1357c, 0x130ec, 0x13294, +0x0, 0x13570, 0x13570, 0x12b20, +0x12b28, 0x13570, 0x13570, 0x12b20, +0x0, 0x13b84, 0x13bc8, 0x13c60, +0x13cac, 0x13d1c, 0x13db4, 0x13de8, +0x13e70, 0x13f08, 0x13fd8, 0x14018, +0x1409c, 0x140c0, 0x141f4, 0x646f4261, +0x73655067, 0x0, 0x0, 0x0, +0x0, 0x14c4c, 0x14c4c, 0x14b94, +0x14bd8, 0x14c4c, 0x14c4c, 0x14b94, 0x0, 0x0 }; static const u_int32_t tigonFwData[] = { -0x416c7465, -0x6f6e2041, 0x63654e49, 0x43205600, 0x416c7465, -0x6f6e2041, 0x63654e49, 0x43205600, 0x42424242, -0x0, 0x0, 0x0, 0x135418, -0x13e7fc, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x60cf00, -0x60, 0xcf000000, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x3, 0x0, -0x1, 0x0, 0x0, 0x0, -0x1, 0x0, 0x1, 0x0, -0x0, 0x0, 0x0, 0x1, -0x1, 0x0, 0x0, 0x0, -0x0, 0x0, 0x1000000, 0x21000000, -0x12000140, 0x0, 0x0, 0x20000000, -0x120000a0, 0x0, 0x12000060, 0x12000180, -0x120001e0, 0x0, 0x0, 0x0, -0x1, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x2, -0x0, 0x0, 0x30001, 0x1, -0x30201, 0x0, 0x0, 0x0, +0x416c7465, +0x6f6e2041, 0x63654e49, 0x43205600, 0x416c7465, +0x6f6e2041, 0x63654e49, 0x43205600, 0x42424242, +0x0, 0x0, 0x0, 0x135418, +0x13e7fc, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x60cf00, +0x60, 0xcf000000, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x3, 0x0, +0x1, 0x0, 0x0, 0x0, +0x1, 0x0, 0x1, 0x0, +0x0, 0x0, 0x0, 0x1, +0x1, 0x0, 0x0, 0x0, +0x0, 0x0, 0x1000000, 0x21000000, +0x12000140, 0x0, 0x0, 0x20000000, +0x120000a0, 0x0, 0x12000060, 0x12000180, +0x120001e0, 0x0, 0x0, 0x0, +0x1, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x2, +0x0, 0x0, 0x30001, 0x1, +0x30201, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; diff --git a/sys/dev/microcode/tigon/ti_fw2.h b/sys/dev/microcode/tigon/ti_fw2.h index 9b02494a3..6bbbef0f1 100644 --- a/sys/dev/microcode/tigon/ti_fw2.h +++ b/sys/dev/microcode/tigon/ti_fw2.h @@ -26,4857 +26,4857 @@ static const int tigon2FwSbssLen = 0xcc; static const u_int32_t tigon2FwBssAddr = 0x00017010; static const int tigon2FwBssLen = 0x20c0; static const u_int32_t tigon2FwText[] = { -0x0, -0x10000003, 0x0, 0xd, 0xd, -0x3c1d0001, 0x8fbd6de0, 0x3a0f021, 0x3c100000, -0x26104000, 0xc0010c0, 0x0, 0xd, -0x3c1d0001, 0x8fbd6de4, 0x3a0f021, 0x3c100000, -0x26104000, 0xc0017e0, 0x0, 0xd, -0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x2000008, -0x0, 0x800172f, 0x3c0a0001, 0x800172f, -0x3c0a0002, 0x800172f, 0x0, 0x8002ca7, -0x0, 0x8002c4a, 0x0, 0x800172f, -0x3c0a0004, 0x8003286, 0x0, 0x8001a52, -0x0, 0x8003948, 0x0, 0x80038ef, -0x0, 0x800172f, 0x3c0a0006, 0x80039b6, -0x3c0a0007, 0x800172f, 0x3c0a0008, 0x800172f, -0x3c0a0009, 0x8003a0e, 0x0, 0x8002ea1, -0x0, 0x800172f, 0x3c0a000b, 0x800172f, -0x3c0a000c, 0x800172f, 0x3c0a000d, 0x80028f7, -0x0, 0x800288c, 0x0, 0x800172f, -0x3c0a000e, 0x800208c, 0x0, 0x8001964, -0x0, 0x8001a04, 0x0, 0x8003ca2, -0x0, 0x8003c90, 0x0, 0x800172f, -0x0, 0x800191a, 0x0, 0x800172f, -0x0, 0x800172f, 0x3c0a0013, 0x800172f, -0x3c0a0014, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x27bdffe0, -0x3c1cc000, 0xafbf001c, 0xafb00018, 0x8f820140, -0x24030003, 0xaf8300ec, 0x34420004, 0xc002b1c, -0xaf820140, 0x3c0100c0, 0xc001763, 0xac203ffc, -0x401821, 0x3c020010, 0x3c010001, 0xac236f5c, -0x10620011, 0x43102b, 0x14400002, 0x3c020020, -0x3c020008, 0x1062000c, 0x24050100, 0x3c060001, -0x8cc66f5c, 0x3c040001, 0x24845d34, 0x3821, -0xafa00010, 0xc002b37, 0xafa00014, 0x3c020020, -0x3c010001, 0xac226f5c, 0x24020008, 0x3c010001, -0xac226f74, 0x2402001f, 0x3c010001, 0xac226f84, -0x24020016, 0x3c010001, 0xac226f58, 0x3c05fffe, -0x34a56f08, 0x3c020001, 0x8c426f5c, 0x3c030002, -0x246390d0, 0x3c040001, 0x8c846d84, 0x431023, -0x14800002, 0x458021, 0x2610fa38, 0x2402f000, -0x2028024, 0xc001785, 0x2002021, 0x2022823, -0x3c040020, 0x821823, 0x651823, 0x247bb000, -0x3c03fffe, 0x3463bf08, 0x363b821, 0x3c0600bf, -0x34c6f000, 0x3c070001, 0x8ce76d80, 0x3c0300bf, -0x3463e000, 0x852023, 0x3c010001, 0xac246f68, -0x822023, 0x3c010001, 0xac256f50, 0x52842, -0x3c010001, 0xac226f44, 0x27620ffc, 0x3c010001, -0xac226de0, 0x27621ffc, 0xdb3023, 0x7b1823, -0x3c010001, 0xac246f48, 0x3c010001, 0xac256f6c, -0x3c010001, 0xac226de4, 0xaf860150, 0x10e00011, -0xaf830250, 0x3c1d0001, 0x8fbd6d8c, 0x3a0f021, -0xc001749, 0x0, 0x3c020001, 0x8c426d90, -0x3c030001, 0x8c636d94, 0x2442fe00, 0x24630200, -0x3c010001, 0xac226d90, 0x3c010001, 0x10000004, -0xac236d94, 0x3c1d0001, 0x8fbd6de0, 0x3a0f021, -0x3c020001, 0x8c426d84, 0x1040000d, 0x26fafa38, -0x3c020001, 0x8c426d90, 0x3c030001, 0x8c636d94, -0x3c1a0001, 0x8f5a6d94, 0x2442fa38, 0x246305c8, -0x3c010001, 0xac226d90, 0x3c010001, 0xac236d94, -0x3c020001, 0x8c426d88, 0x14400003, 0x0, -0x3c010001, 0xac206d90, 0xc001151, 0x0, -0x8fbf001c, 0x8fb00018, 0x3e00008, 0x27bd0020, -0x3c020001, 0x8c426d90, 0x3c030001, 0x8c636d94, -0x27bdff98, 0xafb00048, 0x3c100001, 0x8e106778, -0xafb20050, 0x3c120000, 0x26524100, 0xafbf0060, -0xafbe005c, 0xafb50058, 0xafb30054, 0xafb1004c, -0xafa20034, 0xafa30030, 0xafa00010, 0xafa00014, -0x8f860040, 0x3c040001, 0x24845d40, 0x24050200, -0x3c010001, 0xac326f40, 0xc002b37, 0x2003821, -0x8f830040, 0x3c02f000, 0x621824, 0x3c026000, -0x1062000b, 0xa3a0003f, 0x240e0001, 0x3c040001, -0x24845d48, 0xa3ae003f, 0xafa00010, 0xafa00014, -0x8f860040, 0x24050300, 0xc002b37, 0x2003821, -0x8f820240, 0x3c030001, 0x431025, 0xaf820240, -0xaf800048, 0x8f820048, 0x14400005, 0x0, -0xaf800048, 0x8f820048, 0x10400004, 0x0, -0xaf800048, 0x10000003, 0x2e02021, 0xaf80004c, -0x2e02021, 0x3c050001, 0xc002ba4, 0x34a540f8, -0x3402021, 0xc002ba4, 0x240505c8, 0x3c020001, -0x8c426f68, 0x3c0d0001, 0x8dad6f48, 0x3c030001, -0x8c636f44, 0x3c080001, 0x8d086f50, 0x3c090001, -0x8d296f6c, 0x3c0a0001, 0x8d4a6f74, 0x3c0b0001, -0x8d6b6f84, 0x3c0c0001, 0x8d8c6f58, 0x3c040001, -0x24845d54, 0x24050400, 0xaf42013c, 0x8f42013c, -0x24060001, 0x24070001, 0xaf400000, 0xaf4d0138, -0xaf430144, 0xaf480148, 0xaf49014c, 0xaf4a0150, -0xaf4b0154, 0xaf4c0158, 0x2442ff80, 0xaf420140, -0x24020001, 0xafa20010, 0xc002b37, 0xafa00014, -0x8f420138, 0xafa20010, 0x8f42013c, 0xafa20014, -0x8f460144, 0x8f470148, 0x3c040001, 0x24845d60, -0xc002b37, 0x24050500, 0xafb70010, 0xafba0014, -0x8f46014c, 0x8f470150, 0x3c040001, 0x24845d6c, -0xc002b37, 0x24050600, 0x3c020001, 0x8c426f5c, -0x3603821, 0x3c060002, 0x24c690d0, 0x2448ffff, -0x1061824, 0xe81024, 0x43102b, 0x10400006, -0x24050900, 0x3c040001, 0x24845d78, 0xafa80010, -0xc002b37, 0xafa00014, 0x8f82000c, 0xafa20010, -0x8f82003c, 0xafa20014, 0x8f860000, 0x8f870004, -0x3c040001, 0x24845d84, 0xc002b37, 0x24051000, -0x8c020220, 0x8c030224, 0x8c060218, 0x8c07021c, -0x3c040001, 0x24845d8c, 0x24051100, 0xafa20010, -0xc002b37, 0xafa30014, 0xaf800054, 0xaf80011c, -0x8c020218, 0x30420002, 0x10400009, 0x0, -0x8c020220, 0x3c030002, 0x34630004, 0x431025, -0xaf42000c, 0x8c02021c, 0x10000008, 0x34420004, -0x8c020220, 0x3c030002, 0x34630006, 0x431025, -0xaf42000c, 0x8c02021c, 0x34420006, 0xaf420014, -0x8c020218, 0x30420010, 0x1040000a, 0x0, -0x8c02021c, 0x34420004, 0xaf420010, 0x8c020220, -0x3c03000a, 0x34630004, 0x431025, 0x10000009, -0xaf420008, 0x8c020220, 0x3c03000a, 0x34630006, -0x431025, 0xaf420008, 0x8c02021c, 0x34420006, -0xaf420010, 0x24020001, 0xaf8200a0, 0xaf8200b0, -0x8f830054, 0x8f820054, 0xaf8000d0, 0xaf8000c0, -0x10000002, 0x24630064, 0x8f820054, 0x621023, -0x2c420065, 0x1440fffc, 0x0, 0x8c040208, -0x8c05020c, 0x26e20028, 0xaee20020, 0x24020490, -0xaee20010, 0xaee40008, 0xaee5000c, 0x26e40008, -0x8c820000, 0x8c830004, 0xaf820090, 0xaf830094, -0x8c820018, 0xaf8200b4, 0x9482000a, 0xaf82009c, -0x8f420014, 0xaf8200b0, 0x8f8200b0, 0x30420004, -0x1440fffd, 0x0, 0x8f8200b0, 0x3c03ef00, -0x431024, 0x10400021, 0x0, 0x8f8200b4, -0xafa20010, 0x8f820090, 0x8f830094, 0x3c040001, -0x24845d94, 0xafa30014, 0x8f8600b0, 0x8f87009c, -0x3c050001, 0xc002b37, 0x34a5200d, 0x3c040001, -0x24845da0, 0x240203c3, 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+0x8f840054, 0x24030001, 0x24020002, 0x3c010001, +0xac236e5c, 0x3c010001, 0xac226e58, 0x3c010001, +0xac236e64, 0x3c010001, 0xac236ee4, 0x3c010001, +0xac246ff0, 0x1000004f, 0x2b38825, 0x16620039, +0x3c028000, 0x3c020001, 0x8c426ee0, 0x1440001e, +0x24040018, 0x2021, 0x2821, 0xc004e0b, +0x34068000, 0x8f830054, 0x8f820054, 0x2b38825, +0x10000002, 0x24630032, 0x8f820054, 0x621023, +0x2c420033, 0x1440fffc, 0x0, 0x8f830054, +0x24020001, 0x3c010001, 0xac226ee0, 0x3c010001, +0xac226e5c, 0x3c010001, 0xac226e58, 0x3c010001, +0xac226e64, 0x3c010001, 0xac226ee4, 0x3c010001, +0x1000002c, 0xac236ff0, 0x2821, 0xc004e0b, +0x24060404, 0x2021, 0x2405001e, 0x27a60018, +0x24020002, 0xc0045ee, 0xa7a20018, 0x2021, +0x2821, 0x27a60018, 0xc0045ee, 0xa7a00018, +0x24040018, 0x24050002, 0xc004e0b, 0x24060004, +0x3c028000, 0x2221025, 0x2b31825, 0x10000015, +0x438825, 0x2221025, 0x2751825, 0x438825, +0x2002021, 0x97a6001c, 0x3c070001, 0x8ce76e58, +0x3c05000c, 0x34a50326, 0xafb30010, 0xc002b37, +0xafb10014, 0x10000007, 0x0, 0x3c110002, +0x2308821, 0x8e3190bc, 0x3c027fff, 0x3442ffff, +0x2228824, 0x3c020001, 0x8c426e68, 0x1040001e, +0x0, 0x3c020001, 0x8c426fdc, 0x10400002, +0x3c022000, 0x2228825, 0x8fa8002c, 0x81140, +0x3c010002, 0x220821, 0x8c2290c0, 0x10400003, +0x3c020020, 0x10000005, 0x2228825, 0x3c02ffdf, +0x3442ffff, 0x2228824, 0x8fa8002c, 0x81140, +0x3c010002, 0x220821, 0x8c2290c8, 0x10400003, +0x3c020080, 0x10000004, 0x2228825, 0x3c02ff7f, +0x3442ffff, 0x2228824, 0x8fa8002c, 0x81140, +0x3c010002, 0x220821, 0xac3190b4, 0x10000135, +0x2201021, 0x8fa8002c, 0x8f140, 0x3c030002, +0x7e1821, 0x8c6390b8, 0x3c024000, 0x621024, +0x14400009, 0x24040001, 0x3c027fff, 0x3442ffff, +0x628824, 0x3c010002, 0x3e0821, 0xac3190b0, +0x10000124, 0x2201021, 0x2821, 0xc0045ac, +0x27a60018, 0x24040001, 0x2821, 0xc0045ac, +0x27a60018, 0x24040001, 0x24050001, 0x27b20020, +0xc0045ac, 0x2403021, 0x24040001, 0x24050001, +0xc0045ac, 0x2403021, 0x24040001, 0x24050004, +0x27b1001e, 0xc0045ac, 0x2203021, 0x24040001, +0x24050004, 0xc0045ac, 0x2203021, 0x24040001, +0x24050005, 0x27b00022, 0xc0045ac, 0x2003021, +0x24040001, 0x24050005, 0xc0045ac, 0x2003021, +0x24040001, 0x24050010, 0xc0045ac, 0x27a60018, +0x24040001, 0x24050010, 0xc0045ac, 0x27a60018, +0x24040001, 0x2405000a, 0xc0045ac, 0x2403021, +0x24040001, 0x2405000a, 0xc0045ac, 0x2403021, +0x24040001, 0x24050018, 0xc0045ac, 0x2203021, +0x24040001, 0x24050018, 0xc0045ac, 0x2203021, +0x24040001, 0x24050001, 0xc0045ac, 0x27a60018, +0x24040001, 0x24050001, 0xc0045ac, 0x27a60018, +0x97a20018, 0x30420004, 0x10400066, 0x3c114000, +0x3c030001, 0x8c636ff4, 0x24020005, 0x14620067, +0x24040001, 0x24050019, 0x27b0001c, 0xc0045ac, +0x2003021, 0x24040001, 0x24050019, 0xc0045ac, +0x2003021, 0x97a2001c, 0x30430700, 0x24020400, +0x10620027, 0x28620401, 0x1040000e, 0x24020200, +0x1062001f, 0x28620201, 0x10400005, 0x24020100, +0x5062001e, 0x3c130001, 0x1000001e, 0x3c020004, +0x24020300, 0x50620019, 0x3c130002, 0x10000019, +0x3c020004, 0x24020600, 0x1062000d, 0x28620601, +0x10400005, 0x24020500, 0x5062000b, 0x3c130002, +0x10000010, 0x3c020004, 0x24020700, 0x1462000d, +0x3c020004, 0x3c130004, 0x1000000a, 0x3c150008, +0x10000006, 0x3c130004, 0x10000005, 0x3c150008, +0x3c130001, 0x10000002, 0x3c150008, 0x3c150010, +0x3c020004, 0x12620017, 0x3c028000, 0x8f820054, +0x24100001, 0x3c010001, 0xac306e5c, 0x3c010001, +0xac306e58, 0x3c010001, 0xac306e64, 0x3c010001, +0xac306ee4, 0x3c010001, 0xac226ff0, 0x3c020001, +0x16620022, 0x2758825, 0x2021, 0x2821, +0xc004e0b, 0x34068000, 0x3c010001, 0x1000001b, +0xac306ee0, 0x2221025, 0x2b31825, 0x438825, +0x97a6001c, 0x3c020001, 0x8c426fdc, 0x3c070001, +0x8ce76e58, 0x3c040001, 0x24846d1c, 0xafa20010, +0x97a2001e, 0x3c05000c, 0x34a50323, 0x3c010001, +0xac206ee0, 0xc002b37, 0xafa20014, 0x10000007, +0x0, 0x3c110002, 0x23e8821, 0x8e3190b0, +0x3c027fff, 0x3442ffff, 0x2228824, 0x3c020001, +0x8c426e68, 0x10400069, 0x0, 0x3c020001, +0x8c426fdc, 0x10400002, 0x3c022000, 0x2228825, +0x8fa8002c, 0x81140, 0x3c010002, 0x220821, +0x8c2290c4, 0x10400003, 0x3c020020, 0x10000005, +0x2228825, 0x3c02ffdf, 0x3442ffff, 0x2228824, +0x8fa8002c, 0x81140, 0x3c010002, 0x220821, +0x8c2290cc, 0x10400003, 0x3c020080, 0x1000004f, +0x2228825, 0x3c02ff7f, 0x3442ffff, 0x1000004b, +0x2228824, 0x8fa8002c, 0x82940, 0x3c030002, +0x651821, 0x8c6390b8, 0x3c024000, 0x621024, +0x14400008, 0x3c027fff, 0x3442ffff, 0x628824, +0x3c010002, 0x250821, 0xac3190b0, 0x10000041, +0x2201021, 0x3c020001, 0x8c426e68, 0x10400034, +0x3c11c00c, 0x3c020001, 0x8c426f04, 0x3c04c00c, +0x34842000, 0x3c030001, 0x8c636fdc, 0x2102b, +0x21023, 0x441024, 0x10600003, 0x518825, +0x3c022000, 0x2228825, 0x3c020002, 0x451021, +0x8c4290c4, 0x10400003, 0x3c020020, 0x10000004, +0x2228825, 0x3c02ffdf, 0x3442ffff, 0x2228824, +0x8fa8002c, 0x81140, 0x3c010002, 0x220821, +0x8c2290cc, 0x10400003, 0x3c020080, 0x10000004, +0x2228825, 0x3c02ff7f, 0x3442ffff, 0x2228824, +0x3c020001, 0x8c426ef0, 0x10400002, 0x3c020800, +0x2228825, 0x3c020001, 0x8c426ef4, 0x10400002, +0x3c020400, 0x2228825, 0x3c020001, 0x8c426ef8, +0x10400006, 0x3c020100, 0x10000004, 0x2228825, +0x3c027fff, 0x3442ffff, 0x628824, 0x8fa8002c, +0x81140, 0x3c010002, 0x220821, 0xac3190b0, +0x2201021, 0x8fbf0048, 0x8fbe0044, 0x8fb50040, +0x8fb3003c, 0x8fb20038, 0x8fb10034, 0x8fb00030, +0x3e00008, 0x27bd0050, 0x27bdffd0, 0xafb20028, +0x809021, 0xafbf002c, 0xafb10024, 0xafb00020, +0x8f840200, 0x3c100001, 0x8e106e58, 0x8f860220, +0x24020002, 0x1202005c, 0x2e020003, 0x10400005, +0x24020001, 0x1202000a, 0x121940, 0x1000010c, +0x0, 0x24020004, 0x120200bf, 0x24020008, +0x120200be, 0x128940, 0x10000105, 0x0, +0x3c050002, 0xa32821, 0x8ca590bc, 0x3c100002, +0x2038021, 0x8e1090b4, 0x3c024000, 0xa21024, +0x10400038, 0x3c020008, 0x2021024, 0x10400020, +0x34840002, 0x3c020002, 0x431021, 0x8c4290c0, +0x10400005, 0x34840020, 0x34840100, 0x3c020020, +0x10000006, 0x2028025, 0x2402feff, 0x822024, +0x3c02ffdf, 0x3442ffff, 0x2028024, 0x121140, +0x3c010002, 0x220821, 0x8c2290c8, 0x10400005, +0x3c020001, 0xc23025, 0x3c020080, 0x10000016, +0x2028025, 0x3c02fffe, 0x3442ffff, 0xc23024, +0x3c02ff7f, 0x3442ffff, 0x1000000f, 0x2028024, +0x2402fedf, 0x822024, 0x3c02fffe, 0x3442ffff, +0xc23024, 0x3c02ff5f, 0x3442ffff, 0x2028024, +0x3c010002, 0x230821, 0xac2090c0, 0x3c010002, +0x230821, 0xac2090c8, 0xaf840200, 0xaf860220, +0x8f820220, 0x34420002, 0xaf820220, 0x1000000a, +0x121140, 0x3c02bfff, 0x3442ffff, 0x8f830200, +0x2028024, 0x2402fffd, 0x621824, 0xc003dab, +0xaf830200, 0x121140, 0x3c010002, 0x220821, +0x100000b7, 0xac3090b4, 0x3c020001, 0x8c426fdc, +0x10400069, 0x24050004, 0x24040001, 0xc0045ac, +0x27a60018, 0x24040001, 0x24050005, 0xc0045ac, +0x27a6001a, 0x97a30018, 0x97a2001a, 0x3c040001, +0x24846f08, 0x30630c00, 0x31a82, 0x30420c00, +0x21282, 0xa7a2001a, 0x21080, 0x441021, +0x431021, 0xa7a30018, 0x90480000, 0x24020001, +0x3103ffff, 0x10620029, 0x28620002, 0x10400005, +0x0, 0x10600009, 0x0, 0x1000003d, +0x0, 0x10700013, 0x24020003, 0x1062002c, +0x0, 0x10000037, 0x0, 0x8f820200, +0x2403feff, 0x431024, 0xaf820200, 0x8f820220, +0x3c03fffe, 0x3463ffff, 0x431024, 0xaf820220, +0x3c010002, 0xac2090c4, 0x3c010002, 0x10000032, +0xac2090cc, 0x8f820200, 0x34420100, 0xaf820200, +0x8f820220, 0x3c03fffe, 0x3463ffff, 0x431024, +0xaf820220, 0x24020100, 0x3c010002, 0xac2290c4, +0x3c010002, 0x10000024, 0xac2090cc, 0x8f820200, +0x2403feff, 0x431024, 0xaf820200, 0x8f820220, +0x3c030001, 0x431025, 0xaf820220, 0x3c010002, +0xac2090c4, 0x3c010002, 0x10000017, 0xac2390cc, +0x8f820200, 0x34420100, 0xaf820200, 0x8f820220, +0x3c030001, 0x431025, 0xaf820220, 0x24020100, +0x3c010002, 0xac2290c4, 0x3c010002, 0x1000000a, +0xac2390cc, 0x3c040001, 0x24846d40, 0x97a6001a, +0x97a70018, 0x3c050001, 0x34a5ffff, 0xafa80010, +0xc002b37, 0xafa00014, 0x8f820200, 0x34420002, +0x1000004b, 0xaf820200, 0x128940, 0x3c050002, +0xb12821, 0x8ca590b8, 0x3c100002, 0x2118021, +0x8e1090b0, 0x3c024000, 0xa21024, 0x14400010, +0x0, 0x3c020001, 0x8c426fdc, 0x14400005, +0x3c02bfff, 0x8f820200, 0x34420002, 0xaf820200, +0x3c02bfff, 0x3442ffff, 0xc003dab, 0x2028024, +0x3c010002, 0x310821, 0x10000031, 0xac3090b0, +0x3c020001, 0x8c426fdc, 0x10400005, 0x3c020020, +0x3c020001, 0x8c426f04, 0x10400025, 0x3c020020, +0xa21024, 0x10400007, 0x34840020, 0x24020100, +0x3c010002, 0x310821, 0xac2290c4, 0x10000006, +0x34840100, 0x3c010002, 0x310821, 0xac2090c4, +0x2402feff, 0x822024, 0x3c020080, 0xa21024, +0x10400007, 0x121940, 0x3c020001, 0x3c010002, +0x230821, 0xac2290cc, 0x10000008, 0xc23025, +0x121140, 0x3c010002, 0x220821, 0xac2090cc, +0x3c02fffe, 0x3442ffff, 0xc23024, 0xaf840200, +0xaf860220, 0x8f820220, 0x34420002, 0xaf820220, +0x121140, 0x3c010002, 0x220821, 0xac3090b0, +0x8fbf002c, 0x8fb20028, 0x8fb10024, 0x8fb00020, +0x3e00008, 0x27bd0030, 0x0, 0x1821, +0x308400ff, 0x2405ffdf, 0x2406ffbf, 0x641007, +0x30420001, 0x10400004, 0x0, 0x8f820044, +0x10000003, 0x34420040, 0x8f820044, 0x461024, +0xaf820044, 0x8f820044, 0x34420020, 0xaf820044, +0x8f820044, 0x451024, 0xaf820044, 0x24630001, +0x28620008, 0x5440ffee, 0x641007, 0x3e00008, +0x0, 0x2c820008, 0x1040001b, 0x0, +0x2405ffdf, 0x2406ffbf, 0x41880, 0x3c020001, +0x24426f20, 0x621821, 0x24640004, 0x90620000, +0x10400004, 0x0, 0x8f820044, 0x10000003, +0x34420040, 0x8f820044, 0x461024, 0xaf820044, +0x8f820044, 0x34420020, 0xaf820044, 0x8f820044, +0x451024, 0xaf820044, 0x24630001, 0x64102b, +0x1440ffee, 0x0, 0x3e00008, 0x0, +0x0, 0x0, 0x0, 0x8f8400c4, +0x8f8600e0, 0x8f8700e4, 0x2402fff8, 0xc22824, +0x10e5001a, 0x27623ff8, 0x14e20002, 0x24e80008, +0x27683000, 0x55050004, 0x8d0a0000, 0x30c20004, +0x14400012, 0x805021, 0x8ce90000, 0x8f42013c, +0x1494823, 0x49182b, 0x94eb0006, 0x10600002, +0x25630050, 0x494821, 0x123182b, 0x50400003, +0x8f4201fc, 0x3e00008, 0xe01021, 0xaf8800e8, +0x24420001, 0xaf4201fc, 0xaf8800e4, 0x3e00008, +0x1021, 0x3e00008, 0x0, 0x8f8300e4, +0x27623ff8, 0x10620004, 0x24620008, 0xaf8200e8, +0x3e00008, 0xaf8200e4, 0x27623000, 0xaf8200e8, +0x3e00008, 0xaf8200e4, 0x3e00008, 0x0, +0x0, 0x0, 0x0, 0x8f880120, +0x27624fe0, 0x8f830128, 0x15020002, 0x25090020, +0x27694800, 0x11230012, 0x8fa20010, 0xad040000, +0xad050004, 0xad060008, 0xa507000e, 0x8fa30014, +0xad020018, 0x8fa20018, 0xad03001c, 0x25030016, +0xad020010, 0xad030014, 0xaf890120, 0x8f4300fc, +0x24020001, 0x2463ffff, 0x3e00008, 0xaf4300fc, +0x8f430324, 0x1021, 0x24630001, 0x3e00008, +0xaf430324, 0x3e00008, 0x0, 0x8f880100, +0x276247e0, 0x8f830108, 0x15020002, 0x25090020, +0x27694000, 0x1123000f, 0x8fa20010, 0xad040000, +0xad050004, 0xad060008, 0xa507000e, 0x8fa30014, +0xad020018, 0x8fa20018, 0xad03001c, 0x25030016, +0xad020010, 0xad030014, 0xaf890100, 0x3e00008, +0x24020001, 0x8f430328, 0x1021, 0x24630001, +0x3e00008, 0xaf430328, 0x3e00008, 0x0, 0x0, 0x0, 0x0, 0x0 }; static const u_int32_t tigon2FwRodata[] = { -0x24486561, -0x6465723a, 0x202f7072, 0x6f6a6563, 0x74732f72, -0x63732f73, 0x772f6765, 0x2f2e2f6e, 0x69632f66, -0x77322f63, 0x6f6d6d6f, 0x6e2f6677, 0x6d61696e, -0x2e632c76, 0x20312e31, 0x2e322e34, 0x35203139, -0x39392f30, 0x312f3234, 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0x6e495f46, 0x0, +0x5173436f, 0x6e734600, 0x51725072, 0x6f644600, +0x724d6163, 0x43686b30, 0x0, 0x72784672, +0x6d324c67, 0x0, 0x72784e6f, 0x53744264, +0x0, 0x72784e6f, 0x4d694264, 0x0, +0x72784e6f, 0x4a6d4264, 0x0, 0x7278436b, +0x446d6146, 0x0, 0x72785144, 0x6d457846, +0x0, 0x72785144, 0x6d614600, 0x72785144, +0x4c426446, 0x0, 0x72785144, 0x6d426446, +0x0, 0x72784372, 0x63506164, 0x0, +0x72536d51, 0x446d6146, 0x0, 0x24486561, +0x6465723a, 0x202f7072, 0x6f6a6563, 0x74732f72, +0x63732f73, 0x772f6765, 0x2f2e2f6e, 0x69632f66, +0x77322f63, 0x6f6d6d6f, 0x6e2f6d61, 0x632e632c, +0x7620312e, 0x312e322e, 0x32322031, 0x3939382f, +0x31322f30, 0x38203032, 0x3a33363a, 0x33302073, +0x6875616e, 0x67204578, 0x70202400, 0x65767452, +0x6e674600, 0x51657674, 0x46000000, 0x51657674, +0x505f4600, 0x4d657674, 0x526e6746, 0x0, +0x4d516576, 0x74460000, 0x4d516576, 0x505f4600, +0x5173436f, 0x6e495f46, 0x0, 0x5173436f, +0x6e734600, 0x51725072, 0x6f644600, 0x6d616354, +0x68726573, 0x0, 0x23744d61, 0x6341544e, +0x0, 0x23724d61, 0x6341544e, 0x0, +0x72656d41, 0x73737274, 0x0, 0x6c696e6b, +0x444f574e, 0x0, 0x6c696e6b, 0x55500000, +0x0, 0x0, 0x0, 0x24486561, +0x6465723a, 0x202f7072, 0x6f6a6563, 0x74732f72, +0x63732f73, 0x772f6765, 0x2f2e2f6e, 0x69632f66, +0x77322f63, 0x6f6d6d6f, 0x6e2f636b, 0x73756d2e, +0x632c7620, 0x312e312e, 0x322e3920, 0x31393939, +0x2f30312f, 0x31342030, 0x303a3033, 0x3a343820, +0x73687561, 0x6e672045, 0x78702024, 0x0, +0x65767452, 0x6e674600, 0x51657674, 0x46000000, +0x51657674, 0x505f4600, 0x4d657674, 0x526e6746, +0x0, 0x4d516576, 0x74460000, 0x4d516576, +0x505f4600, 0x5173436f, 0x6e495f46, 0x0, +0x5173436f, 0x6e734600, 0x51725072, 0x6f644600, +0x0, 0x0, 0x0, 0x50726f62, +0x65506879, 0x0, 0x6c6e6b41, 0x53535254, +0x0, 0x6e6f4863, 0x644c6b00, 0x10994, +0x10a0c, 0x10a40, 0x10a6c, 0x10a98, +0x10b0c, 0x10b74, 0x112c8, 0x10ccc, +0x10d00, 0x10d18, 0x10d5c, 0x10d84, +0x10da4, 0x10dcc, 0x112c8, 0x10ccc, +0x10e58, 0x10e70, 0x10ea0, 0x10d84, +0x10ec8, 0x10ef0, 0x0, 0x1101c, +0x11048, 0x1106c, 0x112c8, 0x11090, +0x11144, 0x111d4, 0x0, 0x1192c, +0x119fc, 0x11ad4, 0x11ba4, 0x11c00, +0x11cdc, 0x11d04, 0x11de0, 0x11e08, +0x11fb0, 0x11fd8, 0x12180, 0x12378, +0x1260c, 0x12520, 0x1260c, 0x12638, +0x121a8, 0x12350, 0x7273745f, 0x676d6969, +0x0, 0x126c8, 0x12700, 0x127e8, +0x13434, 0x13474, 0x1348c, 0x7365746c, +0x6f6f7000, 0x0, 0x0, 0x13c7c, +0x13cbc, 0x13d4c, 0x13d90, 0x13df4, +0x13e80, 0x13eb4, 0x13f3c, 0x13fd4, +0x140a4, 0x140e4, 0x14168, 0x1418c, +0x1429c, 0x646f4261, 0x73655067, 0x0, +0x0, 0x0, 0x0, 0x73746d61, +0x634c4e4b, 0x0, 0x6765746d, 0x636c6e6b, +0x0, 0x14f98, 0x14f98, 0x14c4c, +0x14c98, 0x14ce4, 0x14f98, 0x7365746d, 0x61636163, 0x74000000, 0x0, 0x0 }; static const u_int32_t tigon2FwData[] = { -0x1, -0x1, 0x1, 0xc001fc, 0x3ffc, -0xc00000, 0x46726565, 0x42534420, 0x5469676f, -0x6e203200, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x46726565, -0x42534420, 0x5469676f, 0x6e203200, 0x42424242, -0x0, 0x0, 0x0, 0x1ffffc, -0x1fff7c, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x60cf00, -0x60, 0xcf000000, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x3, 0x0, -0x1, 0x0, 0x0, 0x0, -0x1, 0x0, 0x1, 0x0, -0x0, 0x0, 0x0, 0x1, -0x1, 0x0, 0x0, 0x0, -0x0, 0x0, 0x1000000, 0x21000000, -0x12000140, 0x0, 0x0, 0x20000000, -0x120000a0, 0x0, 0x12000060, 0x12000180, -0x120001e0, 0x0, 0x0, 0x0, -0x1, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x2, -0x0, 0x0, 0x30001, 0x1, -0x30201, 0x0, 0x0, 0x1010101, -0x1010100, 0x10100, 0x1010001, 0x10001, +0x1, +0x1, 0x1, 0xc001fc, 0x3ffc, +0xc00000, 0x46726565, 0x42534420, 0x5469676f, +0x6e203200, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x46726565, +0x42534420, 0x5469676f, 0x6e203200, 0x42424242, +0x0, 0x0, 0x0, 0x1ffffc, +0x1fff7c, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x60cf00, +0x60, 0xcf000000, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x0, +0x0, 0x0, 0x3, 0x0, +0x1, 0x0, 0x0, 0x0, +0x1, 0x0, 0x1, 0x0, +0x0, 0x0, 0x0, 0x1, +0x1, 0x0, 0x0, 0x0, +0x0, 0x0, 0x1000000, 0x21000000, +0x12000140, 0x0, 0x0, 0x20000000, +0x120000a0, 0x0, 0x12000060, 0x12000180, +0x120001e0, 0x0, 0x0, 0x0, +0x1, 0x0, 0x0, 0x0, +0x0, 0x0, 0x0, 0x2, +0x0, 0x0, 0x30001, 0x1, +0x30201, 0x0, 0x0, 0x1010101, +0x1010100, 0x10100, 0x1010001, 0x10001, 0x1000101, 0x101, 0x0, 0x0 }; diff --git a/sys/dev/microcode/tusb3410/tusb3410-license b/sys/dev/microcode/tusb3410/tusb3410-license index c241cd0b2..f4e67171d 100644 --- a/sys/dev/microcode/tusb3410/tusb3410-license +++ b/sys/dev/microcode/tusb3410/tusb3410-license @@ -9,52 +9,52 @@ it to be a license under copyright ... ************************************************************ THIS PROGRAM IS PROVIDED "AS IS". TI MAKES NO WARRANTIES OR -REPRESENTATIONS, EITHER EXPRESS, IMPLIED OR STATUTORY, -INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS -FOR A PARTICULAR PURPOSE, LACK OF VIRUSES, ACCURACY OR -COMPLETENESS OF RESPONSES, RESULTS AND LACK OF NEGLIGENCE. -TI DISCLAIMS ANY WARRANTY OF TITLE, QUIET ENJOYMENT, QUIET -POSSESSION, AND NON-INFRINGEMENT OF ANY THIRD PARTY -INTELLECTUAL PROPERTY RIGHTS WITH REGARD TO THE PROGRAM OR +REPRESENTATIONS, EITHER EXPRESS, IMPLIED OR STATUTORY, +INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS +FOR A PARTICULAR PURPOSE, LACK OF VIRUSES, ACCURACY OR +COMPLETENESS OF RESPONSES, RESULTS AND LACK OF NEGLIGENCE. +TI DISCLAIMS ANY WARRANTY OF TITLE, QUIET ENJOYMENT, QUIET +POSSESSION, AND NON-INFRINGEMENT OF ANY THIRD PARTY +INTELLECTUAL PROPERTY RIGHTS WITH REGARD TO THE PROGRAM OR YOUR USE OF THE PROGRAM. -IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, INCIDENTAL, -CONSEQUENTIAL OR INDIRECT DAMAGES, HOWEVER CAUSED, ON ANY -THEORY OF LIABILITY AND WHETHER OR NOT TI HAS BEEN ADVISED -OF THE POSSIBILITY OF SUCH DAMAGES, ARISING IN ANY WAY OUT -OF THIS AGREEMENT, THE PROGRAM, OR YOUR USE OF THE PROGRAM. -EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO, COST OF -REMOVAL OR REINSTALLATION, COMPUTER TIME, LABOR COSTS, LOSS -OF GOODWILL, LOSS OF PROFITS, LOSS OF SAVINGS, OR LOSS OF -USE OR INTERRUPTION OF BUSINESS. IN NO EVENT WILL TI'S -AGGREGATE LIABILITY UNDER THIS AGREEMENT OR ARISING OUT OF -YOUR USE OF THE PROGRAM EXCEED FIVE HUNDRED DOLLARS +IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, INCIDENTAL, +CONSEQUENTIAL OR INDIRECT DAMAGES, HOWEVER CAUSED, ON ANY +THEORY OF LIABILITY AND WHETHER OR NOT TI HAS BEEN ADVISED +OF THE POSSIBILITY OF SUCH DAMAGES, ARISING IN ANY WAY OUT +OF THIS AGREEMENT, THE PROGRAM, OR YOUR USE OF THE PROGRAM. +EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO, COST OF +REMOVAL OR REINSTALLATION, COMPUTER TIME, LABOR COSTS, LOSS +OF GOODWILL, LOSS OF PROFITS, LOSS OF SAVINGS, OR LOSS OF +USE OR INTERRUPTION OF BUSINESS. IN NO EVENT WILL TI'S +AGGREGATE LIABILITY UNDER THIS AGREEMENT OR ARISING OUT OF +YOUR USE OF THE PROGRAM EXCEED FIVE HUNDRED DOLLARS (U.S.$500). -Unless otherwise stated, the Program written and copyrighted -by Texas Instruments is distributed as "freeware". You may, -only under TI's copyright in the Program, use and modify the -Program without any charge or restriction. You may -distribute to third parties, provided that you transfer a -copy of this license to the third party and the third party -agrees to these terms by its first use of the Program. You -must reproduce the copyright notice and any other legend of +Unless otherwise stated, the Program written and copyrighted +by Texas Instruments is distributed as "freeware". You may, +only under TI's copyright in the Program, use and modify the +Program without any charge or restriction. You may +distribute to third parties, provided that you transfer a +copy of this license to the third party and the third party +agrees to these terms by its first use of the Program. You +must reproduce the copyright notice and any other legend of ownership on each copy or partial copy, of the Program. -You acknowledge and agree that the Program contains -copyrighted material, trade secrets and other TI proprietary -information and is protected by copyright laws, -international copyright treaties, and trade secret laws, as -well as other intellectual property laws. To protect TI's -rights in the Program, you agree not to decompile, reverse -engineer, disassemble or otherwise translate any object code -versions of the Program to a human-readable form. You agree -that in no event will you alter, remove or destroy any -copyright notice included in the Program. TI reserves all -rights not specifically granted under this license. Except -as specifically provided herein, nothing in this agreement -shall be construed as conferring by implication, estoppel, -or otherwise, upon you, any license or other right under any +You acknowledge and agree that the Program contains +copyrighted material, trade secrets and other TI proprietary +information and is protected by copyright laws, +international copyright treaties, and trade secret laws, as +well as other intellectual property laws. To protect TI's +rights in the Program, you agree not to decompile, reverse +engineer, disassemble or otherwise translate any object code +versions of the Program to a human-readable form. You agree +that in no event will you alter, remove or destroy any +copyright notice included in the Program. TI reserves all +rights not specifically granted under this license. Except +as specifically provided herein, nothing in this agreement +shall be construed as conferring by implication, estoppel, +or otherwise, upon you, any license or other right under any TI patents, copyrights or trade secrets. -You may not use the Program in non-TI devices. +You may not use the Program in non-TI devices. diff --git a/sys/dev/microcode/tusb3410/tusb3410.h b/sys/dev/microcode/tusb3410/tusb3410.h index 016229d3d..a5f0164a9 100644 --- a/sys/dev/microcode/tusb3410/tusb3410.h +++ b/sys/dev/microcode/tusb3410/tusb3410.h @@ -10,56 +10,56 @@ * ************************************************************ * THIS PROGRAM IS PROVIDED "AS IS". TI MAKES NO WARRANTIES OR - * REPRESENTATIONS, EITHER EXPRESS, IMPLIED OR STATUTORY, - * INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE, LACK OF VIRUSES, ACCURACY OR - * COMPLETENESS OF RESPONSES, RESULTS AND LACK OF NEGLIGENCE. - * TI DISCLAIMS ANY WARRANTY OF TITLE, QUIET ENJOYMENT, QUIET - * POSSESSION, AND NON-INFRINGEMENT OF ANY THIRD PARTY - * INTELLECTUAL PROPERTY RIGHTS WITH REGARD TO THE PROGRAM OR + * REPRESENTATIONS, EITHER EXPRESS, IMPLIED OR STATUTORY, + * INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE, LACK OF VIRUSES, ACCURACY OR + * COMPLETENESS OF RESPONSES, RESULTS AND LACK OF NEGLIGENCE. + * TI DISCLAIMS ANY WARRANTY OF TITLE, QUIET ENJOYMENT, QUIET + * POSSESSION, AND NON-INFRINGEMENT OF ANY THIRD PARTY + * INTELLECTUAL PROPERTY RIGHTS WITH REGARD TO THE PROGRAM OR * YOUR USE OF THE PROGRAM. * - * IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, INCIDENTAL, - * CONSEQUENTIAL OR INDIRECT DAMAGES, HOWEVER CAUSED, ON ANY - * THEORY OF LIABILITY AND WHETHER OR NOT TI HAS BEEN ADVISED - * OF THE POSSIBILITY OF SUCH DAMAGES, ARISING IN ANY WAY OUT - * OF THIS AGREEMENT, THE PROGRAM, OR YOUR USE OF THE PROGRAM. - * EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO, COST OF - * REMOVAL OR REINSTALLATION, COMPUTER TIME, LABOR COSTS, LOSS - * OF GOODWILL, LOSS OF PROFITS, LOSS OF SAVINGS, OR LOSS OF - * USE OR INTERRUPTION OF BUSINESS. IN NO EVENT WILL TI'S - * AGGREGATE LIABILITY UNDER THIS AGREEMENT OR ARISING OUT OF - * YOUR USE OF THE PROGRAM EXCEED FIVE HUNDRED DOLLARS + * IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, INCIDENTAL, + * CONSEQUENTIAL OR INDIRECT DAMAGES, HOWEVER CAUSED, ON ANY + * THEORY OF LIABILITY AND WHETHER OR NOT TI HAS BEEN ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGES, ARISING IN ANY WAY OUT + * OF THIS AGREEMENT, THE PROGRAM, OR YOUR USE OF THE PROGRAM. + * EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO, COST OF + * REMOVAL OR REINSTALLATION, COMPUTER TIME, LABOR COSTS, LOSS + * OF GOODWILL, LOSS OF PROFITS, LOSS OF SAVINGS, OR LOSS OF + * USE OR INTERRUPTION OF BUSINESS. IN NO EVENT WILL TI'S + * AGGREGATE LIABILITY UNDER THIS AGREEMENT OR ARISING OUT OF + * YOUR USE OF THE PROGRAM EXCEED FIVE HUNDRED DOLLARS * (U.S.$500). - + * - * Unless otherwise stated, the Program written and copyrighted - * by Texas Instruments is distributed as "freeware". You may, - * only under TI's copyright in the Program, use and modify the - * Program without any charge or restriction. You may - * distribute to third parties, provided that you transfer a - * copy of this license to the third party and the third party - * agrees to these terms by its first use of the Program. You - * must reproduce the copyright notice and any other legend of + * Unless otherwise stated, the Program written and copyrighted + * by Texas Instruments is distributed as "freeware". You may, + * only under TI's copyright in the Program, use and modify the + * Program without any charge or restriction. You may + * distribute to third parties, provided that you transfer a + * copy of this license to the third party and the third party + * agrees to these terms by its first use of the Program. You + * must reproduce the copyright notice and any other legend of * ownership on each copy or partial copy, of the Program. * - * You acknowledge and agree that the Program contains - * copyrighted material, trade secrets and other TI proprietary - * information and is protected by copyright laws, - * international copyright treaties, and trade secret laws, as - * well as other intellectual property laws. To protect TI's - * rights in the Program, you agree not to decompile, reverse - * engineer, disassemble or otherwise translate any object code - * versions of the Program to a human-readable form. You agree - * that in no event will you alter, remove or destroy any - * copyright notice included in the Program. TI reserves all - * rights not specifically granted under this license. Except - * as specifically provided herein, nothing in this agreement - * shall be construed as conferring by implication, estoppel, - * or otherwise, upon you, any license or other right under any + * You acknowledge and agree that the Program contains + * copyrighted material, trade secrets and other TI proprietary + * information and is protected by copyright laws, + * international copyright treaties, and trade secret laws, as + * well as other intellectual property laws. To protect TI's + * rights in the Program, you agree not to decompile, reverse + * engineer, disassemble or otherwise translate any object code + * versions of the Program to a human-readable form. You agree + * that in no event will you alter, remove or destroy any + * copyright notice included in the Program. TI reserves all + * rights not specifically granted under this license. Except + * as specifically provided herein, nothing in this agreement + * shall be construed as conferring by implication, estoppel, + * or otherwise, upon you, any license or other right under any * TI patents, copyrights or trade secrets. * - * You may not use the Program in non-TI devices. + * You may not use the Program in non-TI devices. */ #ifndef _UTICOM_FW3410_H_ diff --git a/sys/dev/microcode/typhoon/3c990-license b/sys/dev/microcode/typhoon/3c990-license index a3d9e5603..e8ca4b49b 100644 --- a/sys/dev/microcode/typhoon/3c990-license +++ b/sys/dev/microcode/typhoon/3c990-license @@ -1,4 +1,4 @@ - * Copyright 1999-2003 3Com Corporation. All Rights Reserved. + * Copyright 1999-2003 3Com Corporation. All Rights Reserved. * * Redistribution and use in source and binary forms of the 3c990img.h * microcode software are permitted provided that the following conditions diff --git a/sys/dev/microcode/typhoon/3c990img.h b/sys/dev/microcode/typhoon/3c990img.h index 4a7c79c81..8832c92b3 100644 --- a/sys/dev/microcode/typhoon/3c990img.h +++ b/sys/dev/microcode/typhoon/3c990img.h @@ -1,7 +1,7 @@ /* $OpenBSD: 3c990img.h,v 1.6 2009/03/24 11:12:10 kettenis Exp $ */ /*- - * Copyright 1999-2003 3Com Corporation. All Rights Reserved. + * Copyright 1999-2003 3Com Corporation. All Rights Reserved. * * Redistribution and use in source and binary forms of the 3c990img.h * microcode software are permitted provided that the following conditions @@ -31,4268 +31,4268 @@ * (PATENT, COPYRIGHT, TRADE SECRET, MASK WORK, OR OTHER PROPRIETARY RIGHT) * EMBODIED IN ANY OTHER 3COM HARDWARE OR SOFTWARE EITHER SOLELY OR IN * COMBINATION WITH THE 3c990img.h MICROCODE SOFTWARE - */ + */ unsigned char tc990image[] = { -0x54, 0x59, 0x50, 0x48, 0x4f, 0x4f, 0x4e, 0x00, 0x02, 0x00, 0x00, 0x00, -0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xbf, 0xcd, 0x57, 0xc3, -0xba, 0x01, 0x2c, 0xe8, 0xcd, 0xef, 0xa9, 0xd9, 0x6f, 0xbb, 0x76, 0x2f, -0x86, 0x49, 0xac, 0x1b, 0x40, 0x01, 0x00, 0x00, 0x8a, 0xe4, 0x00, 0x00, -0x00, 0x00, 0xff, 0xff, 0x39, 0x00, 0x00, 0xea, 0x05, 0x00, 0x00, 0xea, -0x04, 0x00, 0x00, 0xea, 0x03, 0x00, 0x00, 0xea, 0x02, 0x00, 0x00, 0xea, -0x01, 0x00, 0x00, 0xea, 0x32, 0x02, 0x00, 0xea, 0xc0, 0x14, 0x00, 0xea, -0x07, 0x00, 0x2d, 0xe9, 0x0e, 0x00, 0xa0, 0xe1, 0x00, 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0xd1, 0x70, 0x47, 0x52, 0x1e, 0x8b, 0x5c, 0x83, 0x54, 0xfb, 0xd1, +0x70, 0x47, 0x00, 0x00, 0x00, 0x20, 0x70, 0x47, }; diff --git a/sys/dev/mii/brgphy.c b/sys/dev/mii/brgphy.c index fbf7be2d5..2cfdb9b57 100644 --- a/sys/dev/mii/brgphy.c +++ b/sys/dev/mii/brgphy.c @@ -94,8 +94,8 @@ void brgphy_jumbo_settings(struct mii_softc *); void brgphy_eth_wirespeed(struct mii_softc *); void brgphy_bcm54xx_clock_delay(struct mii_softc *); -const struct mii_phy_funcs brgphy_copper_funcs = { - brgphy_service, brgphy_copper_status, brgphy_reset, +const struct mii_phy_funcs brgphy_copper_funcs = { + brgphy_service, brgphy_copper_status, brgphy_reset, }; const struct mii_phy_funcs brgphy_fiber_funcs = { @@ -439,7 +439,7 @@ setit: * Callback if something changed. Note that we need to poke the DSP on * the Broadcom PHYs if the media changes. */ - if (sc->mii_media_active != mii->mii_media_active || + if (sc->mii_media_active != mii->mii_media_active || sc->mii_media_status != mii->mii_media_status || cmd == MII_MEDIACHG) { switch (sc->mii_oui) { @@ -982,10 +982,10 @@ brgphy_reset_bnx(struct mii_softc *sc) brgphy_disable_early_dac(sc); /* Set Jumbo frame settings in the PHY. */ - brgphy_jumbo_settings(sc); + brgphy_jumbo_settings(sc); /* Enable Ethernet@Wirespeed */ - brgphy_eth_wirespeed(sc); + brgphy_eth_wirespeed(sc); } else if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { brgphy_ber_bug(sc); diff --git a/sys/dev/mii/brgphyreg.h b/sys/dev/mii/brgphyreg.h index e496d88a2..e893fbcf0 100644 --- a/sys/dev/mii/brgphyreg.h +++ b/sys/dev/mii/brgphyreg.h @@ -206,7 +206,7 @@ #define BRGPHY_AUXCTL_MISC_RGMII_SKEW_EN 0x0200 #define BRGPHY_AUXCTL_MISC_WIRESPEED_EN 0x0010 -/* +/* * Shadow register 0x1C, bit 15 is write enable, * bits 14-10 select function (0x00 to 0x1F). */ diff --git a/sys/dev/mii/ciphy.c b/sys/dev/mii/ciphy.c index 9caa61d97..6961fbcf3 100644 --- a/sys/dev/mii/ciphy.c +++ b/sys/dev/mii/ciphy.c @@ -196,7 +196,7 @@ setit: PHY_WRITE(sc, MII_BMCR, speed); PHY_WRITE(sc, MII_ANAR, ANAR_CSMA); - if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) + if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) break; PHY_WRITE(sc, MII_100T2CR, gig); @@ -234,7 +234,7 @@ setit: * Callback if something changed. Note that we need to poke * apply fixups for certain PHY revs. */ - if (sc->mii_media_active != mii->mii_media_active || + if (sc->mii_media_active != mii->mii_media_active || sc->mii_media_status != mii->mii_media_status || cmd == MII_MEDIACHG) { ciphy_fixup(sc); diff --git a/sys/dev/mii/eephy.c b/sys/dev/mii/eephy.c index e33abe384..7b633708d 100644 --- a/sys/dev/mii/eephy.c +++ b/sys/dev/mii/eephy.c @@ -219,7 +219,7 @@ eephy_reset(struct mii_softc *sc) reg = PHY_READ(sc, E1000_CR); reg |= E1000_CR_RESET; PHY_WRITE(sc, E1000_CR, reg); - + for (i = 0; i < 500; i++) { DELAY(1); reg = PHY_READ(sc, E1000_CR); diff --git a/sys/dev/mii/etphy.c b/sys/dev/mii/etphy.c index d9ff0c6fc..d56d598f8 100644 --- a/sys/dev/mii/etphy.c +++ b/sys/dev/mii/etphy.c @@ -2,14 +2,14 @@ /* * Copyright (c) 2007 The DragonFly Project. All rights reserved. - * + * * This code is derived from software contributed to The DragonFly Project * by Sepherosa Ziehau - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: - * + * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright @@ -19,7 +19,7 @@ * 3. Neither the name of The DragonFly Project nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific, prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS @@ -32,7 +32,7 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. - * + * * $DragonFly: src/sys/dev/netif/mii_layer/truephy.c,v 1.1 2007/10/12 14:12:42 sephe Exp $ */ diff --git a/sys/dev/mii/ipgphy.c b/sys/dev/mii/ipgphy.c index 46af49259..29c99061a 100644 --- a/sys/dev/mii/ipgphy.c +++ b/sys/dev/mii/ipgphy.c @@ -122,7 +122,7 @@ ipgphy_attach(struct device *parent, struct device *self, void *aux) sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; if (sc->mii_capabilities & BMSR_EXTSTAT) sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); - + mii_phy_add_media(sc); } @@ -274,7 +274,7 @@ ipgphy_status(struct mii_softc *sc) mii->mii_media_active = IFM_ETHER; bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); - if (bmsr & BMSR_LINK) + if (bmsr & BMSR_LINK) mii->mii_media_status |= IFM_ACTIVE; bmcr = PHY_READ(sc, MII_BMCR); diff --git a/sys/dev/mii/ipgphyreg.h b/sys/dev/mii/ipgphyreg.h index 3ef145f36..c52c150d7 100644 --- a/sys/dev/mii/ipgphyreg.h +++ b/sys/dev/mii/ipgphyreg.h @@ -3,13 +3,13 @@ /*- * Copyright (c) 2006, Pyun YongHyeon * All rights reserved. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions - * are met: + * are met: * 1. Redistributions of source code must retain the above copyright * notice unmodified, this list of conditions, and the following - * disclaimer. + * disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. diff --git a/sys/dev/mii/jmphyreg.h b/sys/dev/mii/jmphyreg.h index d8f58366f..00f77f8f5 100644 --- a/sys/dev/mii/jmphyreg.h +++ b/sys/dev/mii/jmphyreg.h @@ -2,13 +2,13 @@ /*- * Copyright (c) 2008, Pyun YongHyeon * All rights reserved. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions - * are met: + * are met: * 1. Redistributions of source code must retain the above copyright * notice unmodified, this list of conditions, and the following - * disclaimer. + * disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. diff --git a/sys/dev/mii/mii_physubr.c b/sys/dev/mii/mii_physubr.c index c5b23cca5..2bea42cee 100644 --- a/sys/dev/mii/mii_physubr.c +++ b/sys/dev/mii/mii_physubr.c @@ -150,7 +150,7 @@ mii_phy_auto(struct mii_softc *sc, int waitfor) anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; - /* + /* * Most 100baseTX PHY's only support symmetric * PAUSE, so we don't advertise asymmetric * PAUSE unless we also have 1000baseT capability. diff --git a/sys/dev/mii/miidevs b/sys/dev/mii/miidevs index d68fae976..0741f60fd 100644 --- a/sys/dev/mii/miidevs +++ b/sys/dev/mii/miidevs @@ -297,7 +297,7 @@ model RDC R6040_2 0x0005 R6040 10/100 PHY /* Realtek PHYs */ model xxREALTEK RTL8251 0x0000 RTL8251 PHY model xxREALTEK RTL8211FVD 0x0007 RTL8211F-VD PHY -model xxREALTEK RTL8201E 0x0008 RTL8201E 10/100 PHY +model xxREALTEK RTL8201E 0x0008 RTL8201E 10/100 PHY model xxREALTEK RTL8169S 0x0011 RTL8169S/8110S/8211 PHY model REALTEK RTL8201L 0x0020 RTL8201L 10/100 PHY diff --git a/sys/dev/mii/mlphy.c b/sys/dev/mii/mlphy.c index 7d50e86b4..fe41d2d60 100644 --- a/sys/dev/mii/mlphy.c +++ b/sys/dev/mii/mlphy.c @@ -183,7 +183,7 @@ mlphy_attach(struct device *parent, struct device *self, void *aux) sc->mii_funcs = &mlphy_funcs; sc->mii_pdata = mii; sc->mii_flags = ma->mii_flags; - msc->ml_dev = parent; + msc->ml_dev = parent; PHY_RESET(sc); @@ -230,7 +230,7 @@ mlphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) switch (IFM_SUBTYPE(ife->ifm_media)) { case IFM_AUTO: - msc->ml_state = ML_STATE_AUTO_SELF; + msc->ml_state = ML_STATE_AUTO_SELF; if (other != NULL) { mii_phy_reset(other); PHY_WRITE(other, MII_BMCR, BMCR_ISO); @@ -244,7 +244,7 @@ mlphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) * companion PHY (of any), then setup ourselves * to match. This will put us in pass-through * mode and let the companion PHY do all the - * work. + * work. * BMCR data is stored in the ifmedia entry. */ if (other != NULL) { @@ -322,7 +322,7 @@ mlphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) msc->ml_state = ML_STATE_AUTO_SELF; if (other != NULL) { mii_phy_reset(other); - PHY_WRITE(other, MII_BMCR, BMCR_ISO); + PHY_WRITE(other, MII_BMCR, BMCR_ISO); } mii_phy_auto(sc, 0); break; diff --git a/sys/dev/mii/rdcphy.c b/sys/dev/mii/rdcphy.c index 927e9c349..cb1c32276 100644 --- a/sys/dev/mii/rdcphy.c +++ b/sys/dev/mii/rdcphy.c @@ -147,10 +147,10 @@ rdcphy_attach(struct device *parent, struct device *self, void *aux) PHY_RESET(&sc->sc_mii); - sc->sc_mii.mii_capabilities = + sc->sc_mii.mii_capabilities = PHY_READ(&sc->sc_mii, MII_BMSR) & ma->mii_capmask; if (sc->sc_mii.mii_capabilities & BMSR_EXTSTAT) - sc->sc_mii.mii_extcapabilities = + sc->sc_mii.mii_extcapabilities = PHY_READ(&sc->sc_mii, MII_EXTSR); if (sc->sc_mii.mii_capabilities & BMSR_MEDIAMASK) @@ -306,7 +306,7 @@ rdcphy_status(struct mii_softc *sc) return; } if ((physts & STATUS_FULL_DUPLEX) != 0) - mii->mii_media_active |= IFM_FDX | + mii->mii_media_active |= IFM_FDX | mii_phy_flowstatus(sc); else mii->mii_media_active |= IFM_HDX; diff --git a/sys/dev/mii/rgephy.c b/sys/dev/mii/rgephy.c index 54ee588ff..8a86762cf 100644 --- a/sys/dev/mii/rgephy.c +++ b/sys/dev/mii/rgephy.c @@ -283,7 +283,7 @@ setit: */ if (++sc->mii_ticks <= sc->mii_anegticks) break; - + sc->mii_ticks = 0; rgephy_mii_phy_auto(sc); break; @@ -297,7 +297,7 @@ setit: * the DSP on the Realtek PHYs if the media changes. * */ - if (sc->mii_media_active != mii->mii_media_active || + if (sc->mii_media_active != mii->mii_media_active || sc->mii_media_status != mii->mii_media_status || cmd == MII_MEDIACHG) rgephy_load_dspcode(sc); @@ -334,7 +334,7 @@ rgephy_status(struct mii_softc *sc) bmsr = PHY_READ(sc, RGEPHY_SR); if (bmsr & RGEPHY_SR_LINK) mii->mii_media_status |= IFM_ACTIVE; - } + } bmsr = PHY_READ(sc, MII_BMSR); @@ -535,7 +535,7 @@ rgephy_load_dspcode(struct mii_softc *sc) PHY_SETBIT(sc, 4, 0x0800); PHY_CLRBIT(sc, 4, 0x0800); PHY_WRITE(sc, 31, 0x0000); - + DELAY(40); } diff --git a/sys/dev/mii/rgephyreg.h b/sys/dev/mii/rgephyreg.h index a9beaba3b..2bfc8a051 100644 --- a/sys/dev/mii/rgephyreg.h +++ b/sys/dev/mii/rgephyreg.h @@ -86,13 +86,13 @@ #define RGEPHY_LC_DISABLE 0x8000 /* disable leds */ /* Led pusle strething */ #define RGEPHY_LC_PULSE_1_3S 0x7000 -#define RGEPHY_LC_PULSE_670MS 0x6000 -#define RGEPHY_LC_PULSE_340MS 0x5000 -#define RGEPHY_LC_PULSE_170MS 0x4000 -#define RGEPHY_LC_PULSE_84MS 0x3000 -#define RGEPHY_LC_PULSE_42MS 0x2000 -#define RGEPHY_LC_PULSE_21MS 0x1000 -#define RGEPHY_LC_PULSE_0MS 0x0000 +#define RGEPHY_LC_PULSE_670MS 0x6000 +#define RGEPHY_LC_PULSE_340MS 0x5000 +#define RGEPHY_LC_PULSE_170MS 0x4000 +#define RGEPHY_LC_PULSE_84MS 0x3000 +#define RGEPHY_LC_PULSE_42MS 0x2000 +#define RGEPHY_LC_PULSE_21MS 0x1000 +#define RGEPHY_LC_PULSE_0MS 0x0000 #define RGEPHY_LC_LINK 0x0008 /* Link and speed indicated by combination of leds */ #define RGEPHY_LC_DUPLEX 0x0004 #define RGEPHY_LC_RX 0x0002 diff --git a/sys/dev/mii/rlphy.c b/sys/dev/mii/rlphy.c index 4be320356..4eeff6dcd 100644 --- a/sys/dev/mii/rlphy.c +++ b/sys/dev/mii/rlphy.c @@ -273,7 +273,7 @@ rlphy_status(struct mii_softc *sc) /* * If the other side doesn't support NWAY, then the * best we can do is determine if we have a 10Mbps or - * 100Mbps link. There's no way to know if the link + * 100Mbps link. There's no way to know if the link * is full or half duplex, so we default to half duplex * and hope that the user is clever enough to manually * change the media settings if we're wrong. diff --git a/sys/dev/mii/ytphy.c b/sys/dev/mii/ytphy.c index ec7fca8ae..85e5e85e6 100644 --- a/sys/dev/mii/ytphy.c +++ b/sys/dev/mii/ytphy.c @@ -106,7 +106,7 @@ int ytphy_match(struct device *parent, void *match, void *aux) { struct mii_attach_args *ma = aux; - + /* * The MotorComm YT8511 and TY8521 have bogus MII OUIs, so * match the complete ID including the rev. diff --git a/sys/dev/ofw/fdt.c b/sys/dev/ofw/fdt.c index 42edb4660..13dbeaba0 100644 --- a/sys/dev/ofw/fdt.c +++ b/sys/dev/ofw/fdt.c @@ -216,7 +216,7 @@ fdt_node_property(void *node, char *name, char **out) u_int32_t *ptr; u_int32_t nameid; char *tmp; - + if (!tree_inited) return -1; @@ -383,7 +383,7 @@ fdt_next_property(void *node, char *name, char **nextname) { u_int32_t *ptr; u_int32_t nameid; - + if (!tree_inited) return 0; @@ -805,7 +805,7 @@ fdt_print_node(void *node, int level) { u_int32_t *ptr; int cnt; - + ptr = (u_int32_t *)node; if (betoh32(*ptr) != FDT_NODE_BEGIN) @@ -984,7 +984,7 @@ OF_getpropbool(int handle, char *prop) { void *node = (char *)tree.header + handle; char *data; - + return (fdt_node_property(node, prop, &data) >= 0); } @@ -993,7 +993,7 @@ OF_getpropint(int handle, char *prop, uint32_t defval) { uint32_t val; int len; - + len = OF_getprop(handle, prop, &val, sizeof(val)); if (len != sizeof(val)) return defval; @@ -1022,7 +1022,7 @@ OF_getpropint64(int handle, char *prop, uint64_t defval) { uint64_t val; int len; - + len = OF_getprop(handle, prop, &val, sizeof(val)); if (len != sizeof(val)) return defval; diff --git a/sys/dev/ofw/ofw_misc.c b/sys/dev/ofw/ofw_misc.c index 90f541fd5..c572f9a28 100644 --- a/sys/dev/ofw/ofw_misc.c +++ b/sys/dev/ofw/ofw_misc.c @@ -42,7 +42,7 @@ struct regmap { bus_space_tag_t rm_tag; bus_space_handle_t rm_handle; bus_size_t rm_size; - + LIST_ENTRY(regmap) rm_list; }; @@ -580,7 +580,7 @@ nvmem_register_child(int node, struct nvmem_device *nd) return; OF_getpropintarray(node, "bits", bits, sizeof(bits)); - + nc = malloc(sizeof(struct nvmem_cell), M_DEVBUF, M_WAITOK); nc->nc_phandle = phandle; nc->nc_nd = nd; @@ -825,7 +825,7 @@ device_ports_register(struct device_ports *ports, node = OF_getnodebyname(ports->dp_node, "port"); if (node == 0) return; - + device_port_register(node, ports, type); return; } diff --git a/sys/dev/ofw/ofw_regulator.c b/sys/dev/ofw/ofw_regulator.c index 027cb65da..4ec246418 100644 --- a/sys/dev/ofw/ofw_regulator.c +++ b/sys/dev/ofw/ofw_regulator.c @@ -458,7 +458,7 @@ regulator_gpio_set(int node, uint32_t value) return EINVAL; regulator_do_notify(phandle, value); - + i = 0; gpio = gpios; while (gpio && gpio < gpios + (glen / sizeof(uint32_t))) { diff --git a/sys/dev/onewire/owsbm.c b/sys/dev/onewire/owsbm.c index cee3c4440..0cf626cf1 100644 --- a/sys/dev/onewire/owsbm.c +++ b/sys/dev/onewire/owsbm.c @@ -41,7 +41,7 @@ #define DSSBM_CMD_RECALL_MEMORY 0xb8 #define DSSBM_CMD_CONVERT_T 0x44 -#define DSSBM_CMD_CONVERT_V 0xb4 +#define DSSBM_CMD_CONVERT_V 0xb4 /* Scratchpad layout */ #define DS2438_SP_STATUS 0 @@ -180,7 +180,7 @@ owsbm_update(void *arg) onewire_write_byte(sc->sc_onewire, DSSBM_CMD_CONVERT_T); if (onewire_reset(sc->sc_onewire) != 0) goto done; - + onewire_matchrom(sc->sc_onewire, sc->sc_rom); onewire_write_byte(sc->sc_onewire, DSSBM_CMD_CONVERT_V); if (onewire_reset(sc->sc_onewire) != 0) diff --git a/sys/dev/pci/aac_pci.c b/sys/dev/pci/aac_pci.c index fe2a6dfaf..c739e15a2 100644 --- a/sys/dev/pci/aac_pci.c +++ b/sys/dev/pci/aac_pci.c @@ -279,7 +279,7 @@ aac_pci_attach(struct device *parent, struct device *self, void *aux) printf("%s\n", intrstr); sc->aac_dmat = pa->pa_dmat; - + for (m = aac_identifiers; m->vendor != 0; m++) if (m->vendor == PCI_VENDOR(pa->pa_id) && m->device == PCI_PRODUCT(pa->pa_id)) { diff --git a/sys/dev/pci/agp.c b/sys/dev/pci/agp.c index a0bab2839..bf6fa2774 100644 --- a/sys/dev/pci/agp.c +++ b/sys/dev/pci/agp.c @@ -64,7 +64,7 @@ agpbus_probe(struct agp_attach_args *aa) struct pci_attach_args *pa = aa->aa_pa; if (strncmp(aa->aa_busname, "agp", 3) == 0 && - PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && + PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE && PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_HOST) return (1); return (0); @@ -215,7 +215,7 @@ agp_generic_enable(struct agp_softc *sc, u_int32_t mode) struct pci_attach_args pa; pcireg_t tstatus, mstatus, command; int rq, sba, fw, rate, capoff; - + if (pci_find_device(&pa, agpvga_match) == 0 || pci_get_capability(pa.pa_pc, pa.pa_tag, PCI_CAP_AGP, &capoff, NULL) == 0) { @@ -359,7 +359,7 @@ agp_acquire(void *dev) { struct agp_softc *sc = (struct agp_softc *)dev; - if (sc->sc_chipc == NULL) + if (sc->sc_chipc == NULL) return (EINVAL); if (sc->sc_state != AGP_ACQUIRE_FREE) @@ -377,7 +377,7 @@ agp_release(void *dev) if (sc->sc_state == AGP_ACQUIRE_FREE) return (0); - if (sc->sc_state != AGP_ACQUIRE_KERNEL) + if (sc->sc_state != AGP_ACQUIRE_KERNEL) return (EBUSY); sc->sc_state = AGP_ACQUIRE_FREE; diff --git a/sys/dev/pci/agp_ali.c b/sys/dev/pci/agp_ali.c index 308299f66..db2c64316 100644 --- a/sys/dev/pci/agp_ali.c +++ b/sys/dev/pci/agp_ali.c @@ -96,7 +96,7 @@ agp_ali_probe(struct device *parent, void *match, void *aux) return (0); } -void +void agp_ali_attach(struct device *parent, struct device *self, void *aux) { struct agp_ali_softc *asc = (struct agp_ali_softc *)self; @@ -135,7 +135,7 @@ agp_ali_attach(struct device *parent, struct device *self, void *aux) reg = pci_conf_read(asc->asc_pc, asc->asc_tag, AGP_ALI_ATTBASE); reg = (reg & 0xff) | gatt->ag_physical; pci_conf_write(asc->asc_pc, asc->asc_tag, AGP_ALI_ATTBASE, reg); - + /* Enable the TLB. */ reg = pci_conf_read(asc->asc_pc, asc->asc_tag, AGP_ALI_TLBCTRL); reg = (reg & ~0xff) | 0x10; @@ -179,7 +179,7 @@ agp_ali_restore(struct agp_ali_softc *asc) /* Install the gatt and aperture size. */ pci_conf_write(asc->asc_pc, asc->asc_tag, AGP_ALI_ATTBASE, asc->asc_attbase); - + /* Enable the TLB. */ pci_conf_write(asc->asc_pc, asc->asc_tag, AGP_ALI_TLBCTRL, asc->asc_tlbctrl); diff --git a/sys/dev/pci/agp_i810.c b/sys/dev/pci/agp_i810.c index f0863f0b4..274e707e2 100644 --- a/sys/dev/pci/agp_i810.c +++ b/sys/dev/pci/agp_i810.c @@ -59,7 +59,7 @@ /* I810/I815 only, memory is in dcache */ #define INTEL_LOCAL 0x2 /* Memory is snooped, must not be accessed through gtt from the cpu. */ -#define INTEL_COHERENT 0x6 +#define INTEL_COHERENT 0x6 enum { CHIP_NONE = 0, /* not integrated graphics */ @@ -194,7 +194,7 @@ agp_i810_get_chiptype(struct pci_attach_args *pa) return (CHIP_IRONLAKE); break; } - + return (CHIP_NONE); } @@ -379,7 +379,7 @@ agp_i810_attach(struct device *parent, struct device *self, void *aux) /* FALLTHROUGH */ case CHIP_I915: /* FALLTHROUGH */ - case CHIP_I965: + case CHIP_I965: /* FALLTHROUGH */ case CHIP_G33: /* FALLTHROUGH */ @@ -559,7 +559,7 @@ agp_i810_configure(struct agp_i810_softc *isc) tmp = isc->isc_apaddr; if (isc->chiptype == CHIP_I810) { tmp += isc->dcache_size; - } else { + } else { tmp += isc->stolen << AGP_PAGE_SHIFT; } diff --git a/sys/dev/pci/agp_intel.c b/sys/dev/pci/agp_intel.c index 628b12218..0ff430869 100644 --- a/sys/dev/pci/agp_intel.c +++ b/sys/dev/pci/agp_intel.c @@ -59,7 +59,7 @@ struct agp_intel_softc { CHIP_I845, CHIP_I850, CHIP_I865 - } chiptype; + } chiptype; /* registers saved during a suspend/resume cycle. */ pcireg_t savectrl; pcireg_t savecmd; @@ -115,7 +115,7 @@ agp_intel_probe(struct device *parent, void *match, void *aux) case PCI_PRODUCT_INTEL_82840_HB: case PCI_PRODUCT_INTEL_82845_HB: case PCI_PRODUCT_INTEL_82845G_HB: - case PCI_PRODUCT_INTEL_82850_HB: + case PCI_PRODUCT_INTEL_82850_HB: case PCI_PRODUCT_INTEL_82855PM_HB: case PCI_PRODUCT_INTEL_82855GM_HB: case PCI_PRODUCT_INTEL_82860_HB: @@ -202,7 +202,7 @@ agp_intel_attach(struct device *parent, struct device *self, void *aux) /* Install the gatt. */ pci_conf_write(pa->pa_pc, pa->pa_tag, AGP_INTEL_ATTBASE, gatt->ag_physical); - + /* Enable the GLTB and setup the control register. */ switch (isc->chiptype) { case CHIP_I443: @@ -262,7 +262,7 @@ agp_intel_attach(struct device *parent, struct device *self, void *aux) pci_conf_write(isc->isc_pc, isc->isc_tag, AGP_INTEL_ERRCMD, reg); } - + isc->agpdev = (struct agp_softc *)agp_attach_bus(pa, &agp_intel_methods, isc->isc_apaddr, isc->isc_apsize, &isc->dev); return; @@ -329,7 +329,7 @@ agp_intel_restore(struct agp_intel_softc *isc) /* Install the gatt. */ pci_conf_write(isc->isc_pc, isc->isc_tag, AGP_INTEL_ATTBASE, isc->gatt->ag_physical); - + /* Enable the GLTB and setup the control register. */ switch (isc->chiptype) { case CHIP_I443: diff --git a/sys/dev/pci/agp_sis.c b/sys/dev/pci/agp_sis.c index f0d59d054..145dcfe1d 100644 --- a/sys/dev/pci/agp_sis.c +++ b/sys/dev/pci/agp_sis.c @@ -135,7 +135,7 @@ agp_sis_attach(struct device *parent, struct device *self, void *aux) /* Install the gatt. */ pci_conf_write(ssc->ssc_pc, ssc->ssc_tag, AGP_SIS_ATTBASE, gatt->ag_physical); - + /* Enable the aperture and auto-tlb-inval */ reg = pci_conf_read(ssc->ssc_pc, ssc->ssc_tag, AGP_SIS_WINCTRL); reg |= (0x05 << 24) | 3; @@ -176,7 +176,7 @@ agp_sis_restore(struct agp_sis_softc *ssc) /* Install the gatt. */ pci_conf_write(ssc->ssc_pc, ssc->ssc_tag, AGP_SIS_ATTBASE, ssc->gatt->ag_physical); - + /* * Enable the aperture, reset the aperture size and enable and * auto-tlb-inval. @@ -217,7 +217,7 @@ agp_sis_set_aperture(void *sc, bus_size_t aperture) gws = ffs(aperture / 4*1024*1024) - 1; - reg = pci_conf_read(ssc->ssc_pc, ssc->ssc_tag, AGP_SIS_WINCTRL); + reg = pci_conf_read(ssc->ssc_pc, ssc->ssc_tag, AGP_SIS_WINCTRL); reg &= ~0x00000070; reg |= gws << 4; pci_conf_write(ssc->ssc_pc, ssc->ssc_tag, AGP_SIS_WINCTRL, reg); diff --git a/sys/dev/pci/agp_via.c b/sys/dev/pci/agp_via.c index 75828c10a..d0e27d5ef 100644 --- a/sys/dev/pci/agp_via.c +++ b/sys/dev/pci/agp_via.c @@ -238,7 +238,7 @@ agp_via_get_aperture(void *sc) struct agp_via_softc *vsc = sc; bus_size_t apsize; - apsize = pci_conf_read(vsc->vsc_pc, vsc->vsc_tag, + apsize = pci_conf_read(vsc->vsc_pc, vsc->vsc_tag, vsc->regs[REG_APSIZE]) & 0x1f; /* diff --git a/sys/dev/pci/agpreg.h b/sys/dev/pci/agpreg.h index 1d8924d58..0f1e2b920 100644 --- a/sys/dev/pci/agpreg.h +++ b/sys/dev/pci/agpreg.h @@ -210,7 +210,7 @@ #define AGP_I810_MISCC_RPTC 0x00c0 #define AGP_I810_MISCC_RPTC_NOLIMIT 0x0000 #define AGP_I810_MISCC_RPTC_62 0x0040 -#define AGP_I810_MISCC_RPTC_50 0x0080 +#define AGP_I810_MISCC_RPTC_50 0x0080 #define AGP_I810_MISCC_RPTC_37 0x00c0 /* diff --git a/sys/dev/pci/agpvar.h b/sys/dev/pci/agpvar.h index 522d1dd1b..569df51f2 100644 --- a/sys/dev/pci/agpvar.h +++ b/sys/dev/pci/agpvar.h @@ -105,7 +105,7 @@ struct agp_softc { pcireg_t sc_id; int sc_opened; - int sc_capoff; + int sc_capoff; int sc_nextid; /* next mem block id */ enum agp_acquire_state sc_state; diff --git a/sys/dev/pci/ahc_pci.c b/sys/dev/pci/ahc_pci.c index 373e87e89..1fbd6e74a 100644 --- a/sys/dev/pci/ahc_pci.c +++ b/sys/dev/pci/ahc_pci.c @@ -459,7 +459,7 @@ const struct ahc_pci_identity ahc_pci_ident_table [] = ID_ALL_MASK, ahc_aic7892_setup }, - /* aic7895 based controllers */ + /* aic7895 based controllers */ { ID_AHA_2940U_DUAL, ID_ALL_MASK, @@ -480,7 +480,7 @@ const struct ahc_pci_identity ahc_pci_ident_table [] = ID_AIC7895_ARO_MASK, ahc_aic7895_setup }, - /* aic7896/97 based controllers */ + /* aic7896/97 based controllers */ { ID_AHA_3950U2B_0, ID_ALL_MASK, @@ -506,7 +506,7 @@ const struct ahc_pci_identity ahc_pci_ident_table [] = ID_ALL_MASK, ahc_aic7896_setup }, - /* aic7899 based controllers */ + /* aic7899 based controllers */ { ID_AHA_3960D, ID_ALL_MASK, @@ -665,7 +665,7 @@ ahc_find_pci_device(pcireg_t id, pcireg_t subid, u_int func) * ID as valid. */ if (func > 0 - && ahc_9005_subdevinfo_valid(PCI_VENDOR(id), PCI_PRODUCT(id), + && ahc_9005_subdevinfo_valid(PCI_VENDOR(id), PCI_PRODUCT(id), PCI_VENDOR(subid), PCI_PRODUCT(subid)) && SUBID_9005_MFUNCENB(PCI_PRODUCT(subid)) == 0) return (NULL); @@ -834,7 +834,7 @@ ahc_pci_attach(struct device *parent, struct device *self, void *aux) ahc_name(ahc)); devconfig |= DACEN; } - + /* Ensure that pci error generation, a test feature, is disabled. */ devconfig |= PCIERRGENDIS; @@ -963,7 +963,7 @@ ahc_pci_attach(struct device *parent, struct device *self, void *aux) M_NOWAIT | M_ZERO); if (ahc->seep_config == NULL) goto error_out; - + /* See if we have a SEEPROM and perform auto-term */ ahc_check_extport(ahc, &sxfrctl1); @@ -1208,7 +1208,7 @@ ahc_probe_ext_scbram(struct ahc_softc *ahc) fast = FALSE; large = FALSE; num_scbs = 0; - + if (ahc_ext_scbram_present(ahc) == 0) goto done; @@ -1283,7 +1283,7 @@ done: ahc_outb(ahc, CLRINT, CLRBRKADRINT); if (1/*bootverbose*/ && enable) { printf("%s: External SRAM, %s access%s, %dbytes/SCB\n", - ahc_name(ahc), fast ? "fast" : "slow", + ahc_name(ahc), fast ? "fast" : "slow", pcheck ? ", parity checking enabled" : "", large ? 64 : 32); } @@ -1402,7 +1402,7 @@ ahc_pci_intr(struct ahc_softc *ahc) if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { printf("%s: Latched PCIERR interrupt with " - "no status bits set\n", ahc_name(ahc)); + "no status bits set\n", ahc_name(ahc)); } else { ahc_outb(ahc, CLRINT, CLRPARERR); } diff --git a/sys/dev/pci/ahd_pci.c b/sys/dev/pci/ahd_pci.c index b6b6affaf..171579a72 100644 --- a/sys/dev/pci/ahd_pci.c +++ b/sys/dev/pci/ahd_pci.c @@ -170,7 +170,7 @@ const struct ahd_pci_identity ahd_pci_ident_table[] = ID_ALL_MASK, ahd_aic7901A_setup }, - /* aic7902 based controllers */ + /* aic7902 based controllers */ { ID_AHA_29320, ID_ALL_MASK, @@ -240,7 +240,7 @@ const struct ahd_pci_identity ahd_pci_ident_table[] = }; const u_int ahd_num_pci_devs = NUM_ELEMENTS(ahd_pci_ident_table); - + #define DEVCONFIG 0x40 #define PCIXINITPAT 0x0000E000ul #define PCIXINIT_PCI33_66 0x0000E000ul @@ -342,7 +342,7 @@ ahd_pci_attach(struct device *parent, struct device *self, void *aux) pci_intr_handle_t ih; const char *intrstr; pcireg_t devconfig, memtype, subid; - uint16_t device, subvendor; + uint16_t device, subvendor; int error, ioh_valid, ioh2_valid, l, memh_valid; ahd->dev_softc = pa; @@ -373,10 +373,10 @@ ahd_pci_attach(struct device *parent, struct device *self, void *aux) error = entry->setup(ahd, pa); if (error != 0) return; - + /* XXX ahc on sparc64 needs this twice */ devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG); - + if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) { ahd->chip |= AHD_PCI; /* Disable PCIX workarounds when running in PCI mode. */ @@ -482,7 +482,7 @@ ahd_pci_attach(struct device *parent, struct device *self, void *aux) devconfig |= DACEN; pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG, devconfig); } - + ahd_softc_init(ahd); /* @@ -514,7 +514,7 @@ ahd_pci_attach(struct device *parent, struct device *self, void *aux) } if (intrstr != NULL) printf(": %s\n", intrstr); - + /* Get the size of the cache */ ahd->pci_cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); ahd->pci_cachesize *= 4; @@ -668,7 +668,7 @@ ahd_check_extport(struct ahd_softc *ahd) /* * Fetch VPD for this function and parse it. */ - if (bootverbose) + if (bootverbose) printf("%s: Reading VPD from SEEPROM...", ahd_name(ahd)); @@ -681,12 +681,12 @@ ahd_check_extport(struct ahd_softc *ahd) /*bytestream*/TRUE); if (error == 0) error = ahd_parse_vpddata(ahd, &vpd); - if (bootverbose) + if (bootverbose) printf("%s: VPD parsing %s\n", ahd_name(ahd), error == 0 ? "successful" : "failed"); - if (bootverbose) + if (bootverbose) printf("%s: Reading SEEPROM...", ahd_name(ahd)); /* Address is always in units of 16bit words */ @@ -941,7 +941,7 @@ ahd_pci_intr(struct ahd_softc *ahd) u_int intstat; u_int i; u_int reg; - + intstat = ahd_inb(ahd, INTSTAT); if ((intstat & SPLTINT) != 0) @@ -965,7 +965,7 @@ ahd_pci_intr(struct ahd_softc *ahd) for (i = 0; i < 8; i++) { u_int bit; - + if (i == 5) continue; @@ -980,7 +980,7 @@ ahd_pci_intr(struct ahd_softc *ahd) pci_status_strings[bit], pci_status_source[i]); } - } + } } pci_status1 = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG , pci_status1); diff --git a/sys/dev/pci/amdiic.c b/sys/dev/pci/amdiic.c index 1bee1fb6c..bd8945435 100644 --- a/sys/dev/pci/amdiic.c +++ b/sys/dev/pci/amdiic.c @@ -351,7 +351,7 @@ amdiic_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, if (tsleep_nsec(sc, PRIBIO, "amdiic", SEC_TO_NSEC(AMDIIC_TIMEOUT))) return (1); - } + } if (sc->sc_i2c_xfer.error) return (1); diff --git a/sys/dev/pci/amdpcib.c b/sys/dev/pci/amdpcib.c index 3160e6d41..6119b32ec 100644 --- a/sys/dev/pci/amdpcib.c +++ b/sys/dev/pci/amdpcib.c @@ -97,7 +97,7 @@ const struct pci_matchid amdpcib_devices[] = { int amdpcib_match(struct device *parent, void *match, void *aux) -{ +{ if (pci_matchbyid((struct pci_attach_args *)aux, amdpcib_devices, sizeof(amdpcib_devices) / sizeof(amdpcib_devices[0]))) return 2; diff --git a/sys/dev/pci/amdpm.c b/sys/dev/pci/amdpm.c index dc9202f7a..71eeaa35f 100644 --- a/sys/dev/pci/amdpm.c +++ b/sys/dev/pci/amdpm.c @@ -115,7 +115,7 @@ static struct timecounter amdpm_timecounter = { #define AMDPM_RNGDONE 0x00000001 /* Random number generation complete */ #define AMDPM_SMB_REGS 0xe0 /* offset of SMB register space */ -#define AMDPM_SMB_SIZE 0xf /* size of SMB register space */ +#define AMDPM_SMB_SIZE 0xf /* size of SMB register space */ #define AMDPM_SMBSTAT 0x0 /* SMBus status */ #define AMDPM_SMBSTAT_ABRT (1 << 0) /* transfer abort */ #define AMDPM_SMBSTAT_COL (1 << 1) /* collision */ @@ -222,7 +222,7 @@ amdpm_attach(struct device *parent, struct device *self, void *aux) sc->sc_iot = pa->pa_iot; sc->sc_poll = 1; /* XXX */ - + if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_AMD) { cfg_reg = pci_conf_read(pa->pa_pc, pa->pa_tag, AMDPM_CONFREG); if ((cfg_reg & AMDPM_PMIOEN) == 0) { @@ -240,7 +240,7 @@ amdpm_attach(struct device *parent, struct device *self, void *aux) if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, AMDPM_SMB_REGS, AMDPM_SMB_SIZE, &sc->sc_i2c_ioh)) { printf(": failed to map I2C subregion\n"); - return; + return; } if ((cfg_reg & AMDPM_TMRRST) == 0 && @@ -255,11 +255,11 @@ amdpm_attach(struct device *parent, struct device *self, void *aux) if (cfg_reg & AMDPM_TMR32) amdpm_timecounter.tc_counter_mask = 0xffffffffu; tc_init(&amdpm_timecounter); - } + } if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_AMD_PBC768_PMC || PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_AMD_8111_PMC) { if ((cfg_reg & AMDPM_RNGEN) ==0) { - pci_conf_write(pa->pa_pc, pa->pa_tag, + pci_conf_write(pa->pa_pc, pa->pa_tag, AMDPM_CONFREG, cfg_reg | AMDPM_RNGEN); cfg_reg = pci_conf_read(pa->pa_pc, pa->pa_tag, AMDPM_CONFREG); @@ -269,8 +269,8 @@ amdpm_attach(struct device *parent, struct device *self, void *aux) (void) bus_space_read_4(sc->sc_iot, sc->sc_ioh, AMDPM_RNGDATA); for (i = 1000; i--; ) { - if (bus_space_read_1(sc->sc_iot, - sc->sc_ioh, AMDPM_RNGSTAT) & + if (bus_space_read_1(sc->sc_iot, + sc->sc_ioh, AMDPM_RNGSTAT) & AMDPM_RNGDONE) break; DELAY(10); @@ -278,7 +278,7 @@ amdpm_attach(struct device *parent, struct device *self, void *aux) if (bus_space_read_1(sc->sc_iot, sc->sc_ioh, AMDPM_RNGSTAT) & AMDPM_RNGDONE) { printf(": rng active"); - timeout_set(&sc->sc_rnd_ch, + timeout_set(&sc->sc_rnd_ch, amdpm_rnd_callout, sc); amdpm_rnd_callout(sc); } @@ -322,9 +322,9 @@ amdpm_activate(struct device *self, int act) /* Restart the AMD PBC768_PMC/8111_PMC RNG */ cfg_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMDPM_CONFREG); - pci_conf_write(sc->sc_pc, sc->sc_tag, + pci_conf_write(sc->sc_pc, sc->sc_tag, AMDPM_CONFREG, cfg_reg | AMDPM_RNGEN); - + } rv = config_activate_children(self, act); break; diff --git a/sys/dev/pci/ami_pci.c b/sys/dev/pci/ami_pci.c index 07fc567f1..9af2efd70 100644 --- a/sys/dev/pci/ami_pci.c +++ b/sys/dev/pci/ami_pci.c @@ -80,7 +80,7 @@ struct ami_pci_device { { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID434, AMI_BROKEN }, { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4DI, 0 }, { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4DI_2, 0 }, - { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4EDI, 0 }, + { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4EDI, 0 }, { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80960RP_ATU, AMI_CHECK_SIGN | AMI_BROKEN }, { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID, 0 }, diff --git a/sys/dev/pci/auacer.c b/sys/dev/pci/auacer.c index 17964f78a..9c93ccd00 100644 --- a/sys/dev/pci/auacer.c +++ b/sys/dev/pci/auacer.c @@ -140,9 +140,9 @@ struct cfdriver auacer_cd = { }; int auacer_match(struct device *, void *, void *); -void auacer_attach(struct device *, struct device *, void *); +void auacer_attach(struct device *, struct device *, void *); int auacer_activate(struct device *, int); -int auacer_intr(void *); +int auacer_intr(void *); const struct cfattach auacer_ca = { sizeof(struct auacer_softc), auacer_match, auacer_attach, NULL, @@ -646,7 +646,7 @@ auacer_add_entry(struct auacer_chan *chan) chan->p += chan->blksize; if (chan->p >= chan->end) chan->p = chan->start; - + if (++chan->ptr >= ALI_DMALIST_MAX) chan->ptr = 0; } @@ -670,9 +670,9 @@ auacer_upd_chan(struct auacer_softc *sc, struct auacer_chan *chan) } civ = READ1(sc, chan->port + ALI_OFF_CIV); - + DPRINTF(ALI_DEBUG_INTR,("auacer_intr: civ=%u ptr=%u\n",civ,chan->ptr)); - + /* XXX */ while (chan->ptr != civ) { auacer_add_entry(chan); diff --git a/sys/dev/pci/auglx.c b/sys/dev/pci/auglx.c index a362789ac..3d35b9526 100644 --- a/sys/dev/pci/auglx.c +++ b/sys/dev/pci/auglx.c @@ -22,7 +22,7 @@ * * The following datasheets were helpful in the development of this * driver: - * + * * AMD Geode LX Processors Data Book * http://www.amd.com/files/connectivitysolutions/geode/geode_lx/\ * 33234F_LX_databook.pdf @@ -335,7 +335,7 @@ auglx_read_codec(void *v, u_int8_t reg, u_int16_t *val) struct auglx_softc *sc = v; u_int32_t codec_cntl, codec_status; int i; - + codec_cntl = RW_CMD | ((u_int32_t)reg << 24) | CMD_NEW; bus_space_write_4(sc->sc_iot, sc->sc_ioh, ACC_CODEC_CNTL, codec_cntl); @@ -381,7 +381,7 @@ auglx_write_codec(void *v, u_int8_t reg, u_int16_t val) DPRINTF(AUGLX_DBG_ACC, ("%s: write codec register 0x%02x: 0x%04x\n", sc->sc_dev.dv_xname, reg, val)); - + codec_cntl = ((u_int32_t)reg << 24) | CMD_NEW | val; bus_space_write_4(sc->sc_iot, sc->sc_ioh, ACC_CODEC_CNTL, codec_cntl); @@ -767,7 +767,7 @@ auglx_trigger_input(void *v, void *start, void *end, int blksize, sc->bm1.arg = arg; mtx_enter(&audio_lock); - /* Program the BM1 PRD register */ + /* Program the BM1 PRD register */ bus_space_write_4(sc->sc_iot, sc->sc_ioh, ACC_BM1_PRD, sc->bm1.sc_prd->dm_segs[0].ds_addr); /* Start Audio Bus Master 0 */ @@ -787,7 +787,7 @@ auglx_allocmem(struct auglx_softc *sc, size_t size, size_t align, error = bus_dmamem_alloc(sc->sc_dmat, p->size, align, 0, p->segs, 1, &p->nsegs, BUS_DMA_NOWAIT); if (error) { - DPRINTF(AUGLX_DBG_DMA, + DPRINTF(AUGLX_DBG_DMA, ("%s: bus_dmamem_alloc failed: error %d\n", sc->sc_dev.dv_xname, error)); return error; @@ -796,7 +796,7 @@ auglx_allocmem(struct auglx_softc *sc, size_t size, size_t align, error = bus_dmamem_map(sc->sc_dmat, p->segs, 1, p->size, &p->addr, BUS_DMA_NOWAIT | sc->sc_dmamap_flags); if (error) { - DPRINTF(AUGLX_DBG_DMA, + DPRINTF(AUGLX_DBG_DMA, ("%s: bus_dmamem_map failed: error %d\n", sc->sc_dev.dv_xname, error)); goto free; @@ -805,7 +805,7 @@ auglx_allocmem(struct auglx_softc *sc, size_t size, size_t align, error = bus_dmamap_create(sc->sc_dmat, p->size, 1, p->size, 0, BUS_DMA_NOWAIT, &p->map); if (error) { - DPRINTF(AUGLX_DBG_DMA, + DPRINTF(AUGLX_DBG_DMA, ("%s: bus_dmamap_create failed: error %d\n", sc->sc_dev.dv_xname, error)); goto unmap; diff --git a/sys/dev/pci/auich.c b/sys/dev/pci/auich.c index 78de2a46f..3ac6e6ad2 100644 --- a/sys/dev/pci/auich.c +++ b/sys/dev/pci/auich.c @@ -1202,7 +1202,7 @@ auich_allocmem(struct auich_softc *sc, size_t size, size_t align, error = bus_dmamem_alloc(sc->dmat, p->size, align, 0, p->segs, 1, &p->nsegs, BUS_DMA_NOWAIT); if (error) { - DPRINTF(AUICH_DEBUG_DMA, + DPRINTF(AUICH_DEBUG_DMA, ("%s: bus_dmamem_alloc failed: error %d\n", sc->sc_dev.dv_xname, error)); return error; @@ -1211,7 +1211,7 @@ auich_allocmem(struct auich_softc *sc, size_t size, size_t align, error = bus_dmamem_map(sc->dmat, p->segs, 1, p->size, &p->addr, BUS_DMA_NOWAIT | sc->sc_dmamap_flags); if (error) { - DPRINTF(AUICH_DEBUG_DMA, + DPRINTF(AUICH_DEBUG_DMA, ("%s: bus_dmamem_map failed: error %d\n", sc->sc_dev.dv_xname, error)); goto free; @@ -1220,7 +1220,7 @@ auich_allocmem(struct auich_softc *sc, size_t size, size_t align, error = bus_dmamap_create(sc->dmat, p->size, 1, p->size, 0, BUS_DMA_NOWAIT, &p->map); if (error) { - DPRINTF(AUICH_DEBUG_DMA, + DPRINTF(AUICH_DEBUG_DMA, ("%s: bus_dmamap_create failed: error %d\n", sc->sc_dev.dv_xname, error)); goto unmap; @@ -1405,7 +1405,7 @@ auich_calibrate(struct auich_softc *sc) AUICH_PCMI + sc->sc_sts_reg); civ = bus_space_read_1(sc->iot, sc->aud_ioh, AUICH_PCMI + AUICH_CIV); - + /* turn time delta into us */ wait_us = ((t2.tv_sec - t1.tv_sec) * 1000000) + t2.tv_usec - t1.tv_usec; diff --git a/sys/dev/pci/auixp.c b/sys/dev/pci/auixp.c index e9f221655..221cab442 100644 --- a/sys/dev/pci/auixp.c +++ b/sys/dev/pci/auixp.c @@ -306,7 +306,7 @@ auixp_set_params(void *hdl, int setmode, int usemode, } - if (setmode & AUMODE_RECORD) { + if (setmode & AUMODE_RECORD) { rec->channels = 2; rec->precision = 16; switch(rec->encoding) { diff --git a/sys/dev/pci/azalia.c b/sys/dev/pci/azalia.c index 89b2a9a57..d74800d69 100644 --- a/sys/dev/pci/azalia.c +++ b/sys/dev/pci/azalia.c @@ -601,7 +601,7 @@ int azalia_pci_activate(struct device *self, int act) { azalia_t *sc = (azalia_t*)self; - int rv = 0; + int rv = 0; switch (act) { case DVACT_SUSPEND: @@ -1080,7 +1080,7 @@ azalia_init_corb(azalia_t *az, int resuming) AZ_WRITE_4(az, CORBLBASE, (uint32_t)AZALIA_DMA_DMAADDR(&az->corb_dma)); AZ_WRITE_4(az, CORBUBASE, PTR_UPPER32(AZALIA_DMA_DMAADDR(&az->corb_dma))); AZ_WRITE_1(az, CORBSIZE, az->corbsize); - + /* reset CORBRP */ corbrp = AZ_READ_2(az, CORBRP); AZ_WRITE_2(az, CORBRP, corbrp | HDA_CORBRP_CORBRPRST); @@ -1914,7 +1914,7 @@ azalia_codec_sort_pins(codec_t *this) conv = -1; /* analog out */ - if ((w->d.pin.cap & COP_PINCAP_OUTPUT) && + if ((w->d.pin.cap & COP_PINCAP_OUTPUT) && !(w->widgetcap & COP_AWCAP_DIGITAL)) { add = nd = 0; conv = azalia_codec_find_defdac(this, w->nid, 0); @@ -1947,7 +1947,7 @@ azalia_codec_sort_pins(codec_t *this) } } /* digital out */ - if ((w->d.pin.cap & COP_PINCAP_OUTPUT) && + if ((w->d.pin.cap & COP_PINCAP_OUTPUT) && (w->widgetcap & COP_AWCAP_DIGITAL)) { conv = azalia_codec_find_defdac(this, w->nid, 0); switch(w->d.pin.device) { @@ -1992,7 +1992,7 @@ azalia_codec_sort_pins(codec_t *this) } } /* digital in */ - if ((w->d.pin.cap & COP_PINCAP_INPUT) && + if ((w->d.pin.cap & COP_PINCAP_INPUT) && (w->widgetcap & COP_AWCAP_DIGITAL)) { conv = azalia_codec_find_defadc(this, w->nid, 0); switch(w->d.pin.device) { @@ -2179,7 +2179,7 @@ azalia_codec_select_dacs(codec_t *this) /* Connect the speaker to a DAC that no other output pin is connected * to by default. If that is not possible, connect to a DAC other - * than the one the first output pin is connected to. + * than the one the first output pin is connected to. */ int azalia_codec_select_spkrdac(codec_t *this) diff --git a/sys/dev/pci/azalia_codec.c b/sys/dev/pci/azalia_codec.c index 0fb0c5c3c..ff9c4c28a 100644 --- a/sys/dev/pci/azalia_codec.c +++ b/sys/dev/pci/azalia_codec.c @@ -1581,7 +1581,7 @@ azalia_mixer_default(codec_t *this) break; } this->playvols.mute = 0; - + /* get default value for record group master */ for (i = 0; i < this->recvols.nslaves; i++) { if (!(this->recvols.cur & (1 << i))) @@ -2574,7 +2574,7 @@ azalia_ampcap_ov(widget_t *w, int type, int offset, int steps, int size, cap = (offset & 0x7f) | ((steps & 0x7f) << 8) | ((size & 0x7f) << 16) | ((ctloff & 0x7f) << 24) | - (mute ? COP_AMPCAP_MUTE : 0); + (mute ? COP_AMPCAP_MUTE : 0); if (type == COP_OUTPUT_AMPCAP) { w->outamp_cap = cap; diff --git a/sys/dev/pci/bktr/bktr_audio.c b/sys/dev/pci/bktr/bktr_audio.c index 8c1926489..4757a630f 100644 --- a/sys/dev/pci/bktr/bktr_audio.c +++ b/sys/dev/pci/bktr/bktr_audio.c @@ -9,7 +9,7 @@ * bktr_audio : This deals with controlling the audio on TV cards, * controlling the Audio Multiplexer (audio source selector). * controlling any MSP34xx stereo audio decoders. - * controlling any DPL35xx dolby surround sound audio decoders. + * controlling any DPL35xx dolby surround sound audio decoders. * initialising TDA98xx audio devices. * */ @@ -76,7 +76,7 @@ void init_audio_devices( bktr_ptr_t bktr ) { /* enable stereo if appropriate on TDA audio chip */ if ( bktr->card.dbx ) init_BTSC( bktr ); - + /* reset the MSP34xx stereo audio chip */ if ( bktr->card.msp3400c ) msp_dpl_reset( bktr, bktr->msp_addr ); @@ -89,7 +89,7 @@ void init_audio_devices( bktr_ptr_t bktr ) { /* - * + * */ #define AUDIOMUX_DISCOVER_NOT int @@ -110,9 +110,9 @@ set_audio( bktr_ptr_t bktr, int cmd ) switch (cmd) { case AUDIO_TUNER: - if (bktr->reverse_mute ) + if (bktr->reverse_mute ) bktr->audio_mux_select = 0; - else + else bktr->audio_mux_select = 3; break; @@ -157,7 +157,7 @@ set_audio( bktr_ptr_t bktr, int cmd ) if ( bktr->audio_mute_state == TRUE ) { if (bktr->reverse_mute ) idx = 3; - else + else idx = 0; } else @@ -217,7 +217,7 @@ set_audio( bktr_ptr_t bktr, int cmd ) /* - * + * */ void temp_mute( bktr_ptr_t bktr, int flag ) @@ -243,9 +243,9 @@ temp_mute( bktr_ptr_t bktr, int flag ) /* registers in the TDA9850 BTSC/dbx chip */ #define CON1ADDR 0x04 #define CON2ADDR 0x05 -#define CON3ADDR 0x06 +#define CON3ADDR 0x06 #define CON4ADDR 0x07 -#define ALI1ADDR 0x08 +#define ALI1ADDR 0x08 #define ALI2ADDR 0x09 #define ALI3ADDR 0x0a @@ -253,7 +253,7 @@ temp_mute( bktr_ptr_t bktr, int flag ) * initialise the dbx chip * taken from the Linux bttv driver TDA9850 initialisation code */ -void +void init_BTSC( bktr_ptr_t bktr ) { i2cWrite(bktr, TDA9850_WADDR, CON1ADDR, 0x08); /* noise threshold st */ @@ -432,7 +432,7 @@ void msp_read_id( bktr_ptr_t bktr ){ * For the MSP3410/3415 there are two schemes for this * a) Fast autodetection - the chip is put into autodetect mode, and the function * returns immediately. This works in most cases and is the Default Mode. - * b) Slow mode. The function sets the MSP3410/3415 chip, then waits for feedback from + * b) Slow mode. The function sets the MSP3410/3415 chip, then waits for feedback from * the chip and re-programs it if needed. */ void msp_autodetect( bktr_ptr_t bktr ) { @@ -480,7 +480,7 @@ void msp_autodetect( bktr_ptr_t bktr ) { else if ( bktr->slow_msp_audio == 1) { msp_dpl_write(bktr, bktr->msp_addr, 0x12, 0x0000,0x7300);/* Set volume to 0db gain */ msp_dpl_write(bktr, bktr->msp_addr, 0x10, 0x0020,0x0001);/* Enable Auto format detection */ - + /* wait for 0.5s max for terrestrial sound autodetection */ loops = 10; do { @@ -506,8 +506,8 @@ void msp_autodetect( bktr_ptr_t bktr ) { DELAY(20000); stereo = msp_dpl_read(bktr, bktr->msp_addr, 0x12, 0x0018); if (bootverbose)printf ("%s: Stereo reg 0x18 b: %d\n", - bktr_name(bktr), stereo); - DELAY(20000); + bktr_name(bktr), stereo); + DELAY(20000); stereo = msp_dpl_read(bktr, bktr->msp_addr, 0x12, 0x0018); if (bootverbose)printf ("%s: Stereo reg 0x18 c: %d\n", bktr_name(bktr), stereo); @@ -552,7 +552,7 @@ void msp_autodetect( bktr_ptr_t bktr ) { break; default: if (bootverbose) printf ("%s: Unknown autodetection result value: %d\n", - bktr_name(bktr), auto_detect); + bktr_name(bktr), auto_detect); } } diff --git a/sys/dev/pci/bktr/bktr_audio.h b/sys/dev/pci/bktr/bktr_audio.h index 62ad94beb..ad6849525 100644 --- a/sys/dev/pci/bktr/bktr_audio.h +++ b/sys/dev/pci/bktr/bktr_audio.h @@ -78,7 +78,7 @@ void dpl_read_id( bktr_ptr_t bktr ); /* * TDA98xx Audio Chip functions. */ -void init_BTSC( bktr_ptr_t bktr ); +void init_BTSC( bktr_ptr_t bktr ); int set_BTSC( bktr_ptr_t bktr, int control ); diff --git a/sys/dev/pci/bktr/bktr_card.h b/sys/dev/pci/bktr/bktr_card.h index 772664cf1..8e02b8578 100644 --- a/sys/dev/pci/bktr/bktr_card.h +++ b/sys/dev/pci/bktr/bktr_card.h @@ -59,7 +59,7 @@ * * where is one of the following card defines. */ - + #define CARD_UNKNOWN 0 #define CARD_MIRO 1 #define CARD_HAUPPAUGE 2 diff --git a/sys/dev/pci/bktr/bktr_os.c b/sys/dev/pci/bktr/bktr_os.c index c6018b9b4..ff9d9ff1a 100644 --- a/sys/dev/pci/bktr/bktr_os.c +++ b/sys/dev/pci/bktr/bktr_os.c @@ -11,12 +11,12 @@ * probe/attach and open/close/ioctl/read/mmap * memory allocation * PCI bus interfacing - * + * * */ /* - * 1. Redistributions of source code must retain the + * 1. Redistributions of source code must retain the * Copyright (c) 1997 Amancio Hasty, 1999 Roger Hardiman * All rights reserved. * @@ -32,7 +32,7 @@ * must display the following acknowledgement: * This product includes software developed by Amancio Hasty and * Roger Hardiman - * 4. The name of the author may not be used to endorse or promote products + * 4. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR @@ -192,7 +192,7 @@ bktr_attach(struct device *parent, struct device *self, void *aux) */ OUTL(bktr, BKTR_INT_MASK, ALL_INTS_DISABLED); OUTW(bktr, BKTR_GPIO_DMA_CTL, FIFO_RISC_DISABLED); - + /* * map interrupt */ @@ -214,7 +214,7 @@ bktr_attach(struct device *parent, struct device *self, void *aux) } if (intrstr != NULL) printf(": %s\n", intrstr); - + /* * PCI latency timer. 32 is a good value for 4 bus mastering slots, if * you have more than four, then 16 would probably be a better value. @@ -231,7 +231,7 @@ bktr_attach(struct device *parent, struct device *self, void *aux) bktr_name(bktr), BROOKTREE_DEF_LATENCY_VALUE); } latency = BROOKTREE_DEF_LATENCY_VALUE; - pci_conf_write(pa->pa_pc, pa->pa_tag, + pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_LATENCY_TIMER, latency<<8); } @@ -331,7 +331,7 @@ free_bktr_mem(bktr_ptr_t bktr, bus_dmamap_t dmap, vaddr_t kva) VBI_DEV : TUNER_DEV)) /* - * + * */ int bktr_open(dev_t dev, int flags, int fmt, struct proc *p) @@ -348,7 +348,7 @@ bktr_open(dev_t dev, int flags, int fmt, struct proc *p) bktr = bktr_cd.cd_devs[unit]; if (!(bktr->flags & METEOR_INITIALIZED)) /* device not found */ - return(ENXIO); + return(ENXIO); switch (FUNCTION(dev)) { case VIDEO_DEV: @@ -364,7 +364,7 @@ bktr_open(dev_t dev, int flags, int fmt, struct proc *p) /* - * + * */ int bktr_close(dev_t dev, int flags, int fmt, struct proc *p) @@ -389,14 +389,14 @@ bktr_close(dev_t dev, int flags, int fmt, struct proc *p) } /* - * + * */ int bktr_read(dev_t dev, struct uio *uio, int ioflag) { bktr_ptr_t bktr; int unit; - + unit = UNIT(dev); bktr = bktr_cd.cd_devs[unit]; @@ -413,7 +413,7 @@ bktr_read(dev_t dev, struct uio *uio, int ioflag) /* - * + * */ int bktr_write(dev_t dev, struct uio *uio, int ioflag) @@ -423,7 +423,7 @@ bktr_write(dev_t dev, struct uio *uio, int ioflag) } /* - * + * */ int bktr_ioctl(dev_t dev, ioctl_cmd_t cmd, caddr_t arg, int flag, struct proc* pr) @@ -449,7 +449,7 @@ bktr_ioctl(dev_t dev, ioctl_cmd_t cmd, caddr_t arg, int flag, struct proc* pr) } /* - * + * */ paddr_t bktr_mmap(dev_t dev, off_t offset, int nprot) @@ -527,7 +527,7 @@ bktr_set_info(void *v, struct radio_info *ri) tv->chnlset = ri->chnlset; else tv->chnlset = DEFAULT_CHNLSET; - + temp_mute(sc, FALSE); return (0); @@ -567,7 +567,7 @@ bktr_get_info(void *v, struct radio_info *ri) * The ri->info is for that purpose. */ ri->stereo = 1; /* Can't switch to mono, always stereo */ - + ri->chan = tv->channel; ri->chnlset = tv->chnlset; diff --git a/sys/dev/pci/bktr/bktr_os.h b/sys/dev/pci/bktr/bktr_os.h index b24ed6325..1ebb0d91a 100644 --- a/sys/dev/pci/bktr/bktr_os.h +++ b/sys/dev/pci/bktr/bktr_os.h @@ -12,7 +12,7 @@ */ /* - * 1. Redistributions of source code must retain the + * 1. Redistributions of source code must retain the * Copyright (c) 1997 Amancio Hasty, 1999 Roger Hardiman * All rights reserved. * @@ -28,7 +28,7 @@ * must display the following acknowledgement: * This product includes software developed by Amancio Hasty and * Roger Hardiman - * 4. The name of the author may not be used to endorse or promote products + * 4. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR diff --git a/sys/dev/pci/bktr/bktr_reg.h b/sys/dev/pci/bktr/bktr_reg.h index e21b8a44b..a67e3b5f4 100644 --- a/sys/dev/pci/bktr/bktr_reg.h +++ b/sys/dev/pci/bktr/bktr_reg.h @@ -18,7 +18,7 @@ * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Mark Tinguely and Jim Lowe - * 4. The name of the author may not be used to endorse or promote products + * 4. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR @@ -369,8 +369,8 @@ struct bt848_registers { #define BKTR_GPIO_DATA 0x200 #define BKTR_I2C_DATA_CTL 0x110 #define BKTR_TGCTRL 0x084 -#define BKTR_PLL_F_LO 0x0F0 -#define BKTR_PLL_F_HI 0x0F4 +#define BKTR_PLL_F_LO 0x0F0 +#define BKTR_PLL_F_HI 0x0F4 #define BKTR_PLL_F_XCI 0x0F8 /* @@ -396,8 +396,8 @@ struct TUNER { u_char type; u_char pllControl[4]; u_char bandLimits[ 2 ]; - u_char bandAddrs[ 4 ]; /* 3 first for the 3 TV - ** bands. Last for radio + u_char bandAddrs[ 4 ]; /* 3 first for the 3 TV + ** bands. Last for radio ** band (0x00=NoRadio). */ @@ -514,7 +514,7 @@ struct bktr_softc { u_int vbi_sequence_number; /* sequence number for VBI */ int vbi_read_blocked; /* user process blocked on read() from /dev/vbi */ struct selinfo vbi_select; /* Data used by select() on /dev/vbi */ - + struct proc *proc; /* process to receive raised signal */ int signal; /* signal to send to process */ @@ -548,7 +548,7 @@ struct bktr_softc { u_short bktr_cap_ctl; volatile u_int flags; #define METEOR_INITIALIZED 0x00000001 -#define METEOR_OPEN 0x00000002 +#define METEOR_OPEN 0x00000002 #define METEOR_MMAP 0x00000004 #define METEOR_INTR 0x00000008 #define METEOR_READ 0x00000010 /* XXX never gets referenced */ @@ -588,7 +588,7 @@ struct bktr_softc { #define METEOR_FIELD_MODE 0x80000000 u_char tflags; /* Tuner flags (/dev/tuner) */ #define TUNER_INITIALIZED 0x00000001 -#define TUNER_OPEN 0x00000002 +#define TUNER_OPEN 0x00000002 u_char vbiflags; /* VBI flags (/dev/vbi) */ #define VBI_INITIALIZED 0x00000001 #define VBI_OPEN 0x00000002 diff --git a/sys/dev/pci/bktr/bktr_tuner.c b/sys/dev/pci/bktr/bktr_tuner.c index 5f360b645..1bb465a9e 100644 --- a/sys/dev/pci/bktr/bktr_tuner.c +++ b/sys/dev/pci/bktr/bktr_tuner.c @@ -67,7 +67,7 @@ #define AFC_MAX_STEP (5 * FREQFACTOR) /* no more than 5 MHz */ #endif /* TUNER_AFC */ - + #define TTYPE_XXX 0 #define TTYPE_NTSC 1 #define TTYPE_NTSC_J 2 @@ -75,7 +75,7 @@ #define TTYPE_PAL_M 4 #define TTYPE_PAL_N 5 #define TTYPE_SECAM 6 - + #define TSA552x_CB_MSB (0x80) #define TSA552x_CB_CP (1<<6) /* set this for fast tuning */ #define TSA552x_CB_T2 (1<<5) /* test mode - Normally set to 0 */ @@ -94,17 +94,17 @@ TSA552x_CB_T0 | \ TSA552x_CB_RSA | \ TSA552x_CB_RSB) - + /* lower the charge pump voltage for better residual oscillator FM */ #define TSA552x_SCONTROL (TSA552x_CB_MSB | \ TSA552x_CB_T0 | \ TSA552x_CB_RSA | \ TSA552x_CB_RSB) - + /* The control value for the ALPS TSCH5 Tuner */ #define TSCH5_FCONTROL 0x82 #define TSCH5_RADIO 0x86 - + /* The control value for the ALPS TSBH1 Tuner */ #define TSBH1_FCONTROL 0xce @@ -367,11 +367,11 @@ static const int hrccable[] = { * caution, some of the offsets don't compute... * * 1 4525 700 N21 - * + * * 2 4825 700 E2 * 3 5525 700 E3 * 4 6225 700 E4 - * + * * 5 17525 700 E5 * 6 18225 700 E6 * 7 18925 700 E7 @@ -380,19 +380,19 @@ static const int hrccable[] = { * 10 21025 700 E10 * 11 21725 700 E11 * 12 22425 700 E12 - * + * * 13 5375 700 ITA * 14 6225 700 ITB - * + * * 15 8225 700 ITC - * + * * 16 17525 700 ITD * 17 18325 700 ITE - * + * * 18 19225 700 ITF * 19 20125 700 ITG * 20 21025 700 ITH - * + * * 21 47125 800 E21 * 22 47925 800 E22 * 23 48725 800 E23 @@ -442,15 +442,15 @@ static const int hrccable[] = { * 67 83925 800 E67 * 68 84725 800 E68 * 69 85525 800 E69 - * + * * 70 4575 800 IA * 71 5375 800 IB * 72 6175 800 IC - * + * * 74 6925 700 S01 * 75 7625 700 S02 * 76 8325 700 S03 - * + * * 80 10525 700 S1 * 81 11225 700 S2 * 82 11925 700 S3 @@ -481,32 +481,32 @@ static const int hrccable[] = { * 102 31925 800 S23 * 103 32725 800 S24 * 104 33525 800 S25 - * 105 34325 800 S26 - * 106 35125 800 S27 - * 107 35925 800 S28 - * 108 36725 800 S29 - * 109 37525 800 S30 - * 110 38325 800 S31 - * 111 39125 800 S32 - * 112 39925 800 S33 - * 113 40725 800 S34 - * 114 41525 800 S35 - * 115 42325 800 S36 - * 116 43125 800 S37 - * 117 43925 800 S38 - * 118 44725 800 S39 - * 119 45525 800 S40 + * 105 34325 800 S26 + * 106 35125 800 S27 + * 107 35925 800 S28 + * 108 36725 800 S29 + * 109 37525 800 S30 + * 110 38325 800 S31 + * 111 39125 800 S32 + * 112 39925 800 S33 + * 113 40725 800 S34 + * 114 41525 800 S35 + * 115 42325 800 S36 + * 116 43125 800 S37 + * 117 43925 800 S38 + * 118 44725 800 S39 + * 119 45525 800 S40 * 120 46325 800 S41 - * + * * 121 3890 000 IFFREQ - * + * */ static const int weurope[] = { - 121, (int)( 38.90 * FREQFACTOR), 0, - 100, (int)(303.25 * FREQFACTOR), (int)(8.00 * FREQFACTOR), + 121, (int)( 38.90 * FREQFACTOR), 0, + 100, (int)(303.25 * FREQFACTOR), (int)(8.00 * FREQFACTOR), 90, (int)(231.25 * FREQFACTOR), (int)(7.00 * FREQFACTOR), - 80, (int)(105.25 * FREQFACTOR), (int)(7.00 * FREQFACTOR), - 74, (int)( 69.25 * FREQFACTOR), (int)(7.00 * FREQFACTOR), + 80, (int)(105.25 * FREQFACTOR), (int)(7.00 * FREQFACTOR), + 74, (int)( 69.25 * FREQFACTOR), (int)(7.00 * FREQFACTOR), 21, (int)(471.25 * FREQFACTOR), (int)(8.00 * FREQFACTOR), 17, (int)(183.25 * FREQFACTOR), (int)(9.00 * FREQFACTOR), 16, (int)(175.25 * FREQFACTOR), (int)(9.00 * FREQFACTOR), @@ -589,12 +589,12 @@ static const int jpncable[] = { #define IF_FREQ 38.90 static const int xussr[] = { 107, (int)(IF_FREQ * FREQFACTOR), 0, - 78, (int)(231.25 * FREQFACTOR), (int)(8.00 * FREQFACTOR), + 78, (int)(231.25 * FREQFACTOR), (int)(8.00 * FREQFACTOR), 70, (int)(111.25 * FREQFACTOR), (int)(8.00 * FREQFACTOR), - 35, (int)(583.25 * FREQFACTOR), (int)(8.00 * FREQFACTOR), + 35, (int)(583.25 * FREQFACTOR), (int)(8.00 * FREQFACTOR), 21, (int)(471.25 * FREQFACTOR), (int)(8.00 * FREQFACTOR), - 6, (int)(175.25 * FREQFACTOR), (int)(8.00 * FREQFACTOR), - 3, (int)( 77.25 * FREQFACTOR), (int)(8.00 * FREQFACTOR), + 6, (int)(175.25 * FREQFACTOR), (int)(8.00 * FREQFACTOR), + 3, (int)( 77.25 * FREQFACTOR), (int)(8.00 * FREQFACTOR), 1, (int)( 49.75 * FREQFACTOR), (int)(9.50 * FREQFACTOR), 0 }; @@ -604,7 +604,7 @@ static const int xussr[] = { * Australian broadcast channels */ #define OFFSET 7.00 -#define IF_FREQ 38.90 +#define IF_FREQ 38.90 static const int australia[] = { 83, (int)(IF_FREQ * FREQFACTOR), 0, 28, (int)(527.25 * FREQFACTOR), (int)(OFFSET * FREQFACTOR), @@ -618,7 +618,7 @@ static const int australia[] = { #undef OFFSET #undef IF_FREQ -/* +/* * France broadcast channels */ #define OFFSET 8.00 @@ -631,7 +631,7 @@ static const int france[] = { 3, (int)( 60.50 * FREQFACTOR), (int)(OFFSET * FREQFACTOR), /* 3 */ 1, (int)( 47.75 * FREQFACTOR), (int)(OFFSET * FREQFACTOR), /* 1 2 */ 0 -}; +}; #undef OFFSET #undef IF_FREQ @@ -649,7 +649,7 @@ static const struct { {xussr, "xussr"}, {australia, "australia"}, {france, "france"}, - + }; #define TBL_CHNL freqTable[ bktr->tuner.chnlset ].ptr[ x ] @@ -749,7 +749,7 @@ void select_tuner( bktr_ptr_t bktr, int tuner_type ) { /* * set the frequency of the tuner * If 'type' is TV_FREQUENCY, the frequency is freq MHz*16 - * If 'type' is FM_RADIO_FREQUENCY, the frequency is freq MHz * 100 + * If 'type' is FM_RADIO_FREQUENCY, the frequency is freq MHz * 100 * (note *16 gives is 4 bits of fraction, eg steps of nnn.0625) * */ @@ -867,7 +867,7 @@ tv_freq( bktr_ptr_t bktr, int frequency, int type ) if(!(band && control)) /* Don't try to set un- */ return(-1); /* supported modes. */ - + band |= bktr->tuner.radio_mode; /* tuner.radio_mode is set in * the ioctls RADIO_SETMODE * and RADIO_GETMODE */ @@ -879,7 +879,7 @@ tv_freq( bktr_ptr_t bktr, int frequency, int type ) } - + return( 0 ); } @@ -888,7 +888,7 @@ tv_freq( bktr_ptr_t bktr, int frequency, int type ) #if defined( TUNER_AFC ) /* - * + * */ int do_afc( bktr_ptr_t bktr, int addr, int frequency ) diff --git a/sys/dev/pci/bktr/bktr_tuner.h b/sys/dev/pci/bktr/bktr_tuner.h index 7e87d5bc2..79483e9b3 100644 --- a/sys/dev/pci/bktr/bktr_tuner.h +++ b/sys/dev/pci/bktr/bktr_tuner.h @@ -6,7 +6,7 @@ * and TV Tuner cards using the Brooktree Bt848, Bt848A, Bt849A, Bt878, Bt879 * chipset. * Copyright Roger Hardiman and Amancio Hasty. - * + * * bktr_tuner : This deals with controlling the tuner fitted to TV cards. * */ @@ -63,7 +63,7 @@ #define TIVISION_TVF5533 14 #define Bt848_MAX_TUNER 15 -/* experimental code for Automatic Frequency Control */ +/* experimental code for Automatic Frequency Control */ #define TUNER_AFC /* @@ -95,7 +95,7 @@ int do_afc( bktr_ptr_t bktr, int addr, int frequency ); #endif /* TUNER_AFC */ -/* +/* * This is for start-up convenience only, NOT mandatory. */ #if !defined( DEFAULT_CHNLSET ) diff --git a/sys/dev/pci/ciss_pci.c b/sys/dev/pci/ciss_pci.c index 004aface7..f34a43988 100644 --- a/sys/dev/pci/ciss_pci.c +++ b/sys/dev/pci/ciss_pci.c @@ -162,7 +162,7 @@ ciss_pci_attach(struct device *parent, struct device *self, void *aux) if (cfg_bar != CISS_BAR) { if (pci_mapreg_map(pa, cfg_bar, PCI_MAPREG_TYPE_MEM, 0, NULL, &sc->cfg_ioh, NULL, &cfgsz, 0)) { - printf(": can't map controller config space\n"); + printf(": can't map controller config space\n"); bus_space_unmap(sc->iot, sc->ioh, size); return; } diff --git a/sys/dev/pci/cs4280.c b/sys/dev/pci/cs4280.c index 837a15f65..35d01d7b8 100644 --- a/sys/dev/pci/cs4280.c +++ b/sys/dev/pci/cs4280.c @@ -110,11 +110,11 @@ struct cs4280_softc { /* I/O (BA0) */ bus_space_tag_t ba0t; bus_space_handle_t ba0h; - + /* BA1 */ bus_space_tag_t ba1t; bus_space_handle_t ba1h; - + /* DMA */ bus_dma_tag_t sc_dmatag; struct cs4280_dma *sc_dmas; @@ -152,7 +152,7 @@ struct cs4280_softc { u_int32_t cctl; struct ac97_codec_if *codec_if; - struct ac97_host_if host_if; + struct ac97_host_if host_if; u_int16_t ac97_reg[CS4280_SAVE_REG_MAX + 1]; /* Save ac97 registers */ }; @@ -259,7 +259,7 @@ const struct midi_hw_if cs4280_midi_hw_if = { }; #endif - + const struct pci_matchid cs4280_devices[] = { { PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CS4280 }, { PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CS4610 }, @@ -267,7 +267,7 @@ const struct pci_matchid cs4280_devices[] = { }; int -cs4280_match(struct device *parent, void *ma, void *aux) +cs4280_match(struct device *parent, void *ma, void *aux) { return (pci_matchbyid((struct pci_attach_args *)aux, cs4280_devices, nitems(cs4280_devices))); @@ -278,9 +278,9 @@ cs4280_read_codec(void *sc_, u_int8_t add, u_int16_t *data) { struct cs4280_softc *sc = sc_; int n; - + DPRINTFN(5,("read_codec: add=0x%02x ", add)); - /* + /* * Make sure that there is not data sitting around from a previous * uncompleted access. */ @@ -289,7 +289,7 @@ cs4280_read_codec(void *sc_, u_int8_t add, u_int16_t *data) /* Set up AC97 control registers. */ BA0WRITE4(sc, CS4280_ACCAD, add); BA0WRITE4(sc, CS4280_ACCDA, 0); - BA0WRITE4(sc, CS4280_ACCTL, + BA0WRITE4(sc, CS4280_ACCTL, ACCTL_RSTN | ACCTL_ESYN | ACCTL_VFRM | ACCTL_CRW | ACCTL_DCV ); if (cs4280_src_wait(sc) < 0) { @@ -303,7 +303,7 @@ cs4280_read_codec(void *sc_, u_int8_t add, u_int16_t *data) while (!(BA0READ4(sc, CS4280_ACSTS) & ACSTS_VSTS)) { delay(1); while (++n > 1000) { - printf("%s: AC97 read fail (VSTS==0) for add=0x%02x\n", + printf("%s: AC97 read fail (VSTS==0) for add=0x%02x\n", sc->sc_dev.dv_xname, add); return (1); } @@ -321,7 +321,7 @@ cs4280_write_codec(void *sc_, u_int8_t add, u_int16_t data) DPRINTFN(5,("write_codec: add=0x%02x data=0x%04x\n", add, data)); BA0WRITE4(sc, CS4280_ACCAD, add); BA0WRITE4(sc, CS4280_ACCDA, data); - BA0WRITE4(sc, CS4280_ACCTL, + BA0WRITE4(sc, CS4280_ACCTL, ACCTL_RSTN | ACCTL_ESYN | ACCTL_VFRM | ACCTL_DCV ); if (cs4280_src_wait(sc) < 0) { @@ -370,7 +370,7 @@ cs4280_set_adc_rate(struct cs4280_softc *sc, int rate) */ u_int32_t cci,cpi,cnt,cx,cy, tmp1; u_int16_t csrc, cgl, cdlay; - + /* XXX * Even though, embedded_audio_spec says capture rate range 11025 to * 48000, dhwiface.cpp says, @@ -379,7 +379,7 @@ cs4280_set_adc_rate(struct cs4280_softc *sc, int rate) * Return an error if an attempt is made to stray outside that limit." * * so assume range as 48000/9 to 48000 - */ + */ if (rate < 8000) rate = 8000; @@ -422,7 +422,7 @@ cs4280_set_adc_rate(struct cs4280_softc *sc, int rate) if (((rate / 3) * 3) != rate) cgl *= 3; for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) { - if (((rate / tmp1) * tmp1) != rate) + if (((rate / tmp1) * tmp1) != rate) cgl *= 5; } #if 0 @@ -451,15 +451,15 @@ cs4280_set_adc_rate(struct cs4280_softc *sc, int rate) tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK; tmp1 |= cdlay <<18; BA1WRITE4(sc, CS4280_CD, tmp1); - + BA1WRITE4(sc, CS4280_CPI, cpi); - + tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK; tmp1 |= cgl; BA1WRITE4(sc, CS4280_CGL, tmp1); BA1WRITE4(sc, CS4280_CNT, cnt); - + tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK; tmp1 |= cgl; BA1WRITE4(sc, CS4280_CGC, tmp1); @@ -482,7 +482,7 @@ cs4280_set_dac_rate(struct cs4280_softc *sc, int rate) int32_t ppi; int16_t psrc; u_int32_t px, py; - + if (rate < 8000) rate = 8000; if (rate > 48000) @@ -503,7 +503,7 @@ cs4280_set_dac_rate(struct cs4280_softc *sc, int rate) px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK; BA1WRITE4(sc, CS4280_PSRC, ( ((psrc<<16) & PSRC_MASK) | px )); -#else +#else /* suggested by cs461x.c (ALSA driver) */ BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py)); #endif @@ -554,9 +554,9 @@ cs4280_attach(struct device *parent, struct device *self, void *aux) char const *intrstr; pci_intr_handle_t ih; u_int32_t mem; - + /* Map I/O register */ - if (pci_mapreg_map(pa, CSCC_PCI_BA0, + if (pci_mapreg_map(pa, CSCC_PCI_BA0, PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->ba0t, &sc->ba0h, NULL, NULL, 0)) { printf(": can't map BA0 space\n"); @@ -581,7 +581,7 @@ cs4280_attach(struct device *parent, struct device *self, void *aux) mem |= 0x00002000; pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem); } - + /* Map and establish the interrupt. */ if (pci_intr_map(pa, &ih)) { printf(": couldn't map interrupt\n"); @@ -633,7 +633,7 @@ cs4280_intr(void *p) * * ring buffer in audio.c is pointed by BUFADDR * <------ ring buffer size == 64kB ------> - * <-----> blksize == 2048*(sc->sc_[pr]count) kB + * <-----> blksize == 2048*(sc->sc_[pr]count) kB * |= = = =|= = = =|= = = =|= = = =|= = = =| * | | | | | | <- call audio_intp every * sc->sc_[pr]_count time. @@ -751,7 +751,7 @@ cs4280_intr(void *p) int data; handled = 1; - DPRINTF(("i: %d: ", + DPRINTF(("i: %d: ", BA0READ4(sc, CS4280_MIDSR))); /* Read the received data */ while ((sc->sc_iintr != NULL) && @@ -760,7 +760,7 @@ cs4280_intr(void *p) DPRINTF(("r:%x\n",data)); sc->sc_iintr(sc->sc_arg, data); } - + /* Write the data */ #if 1 /* XXX: @@ -773,7 +773,7 @@ cs4280_intr(void *p) sc->sc_ointr(sc->sc_arg); } #else - while ((sc->sc_ointr != NULL) && + while ((sc->sc_ointr != NULL) && ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) { DPRINTF(("w: ")); sc->sc_ointr(sc->sc_arg); @@ -928,14 +928,14 @@ cs4280_reset_codec(void *sc_) delay(100); /* delay 100us */ BA0WRITE4(sc, CS4280_ACCTL, ACCTL_RSTN); - /* + /* * It looks like we do the following procedure, too */ /* Enable AC-link sync generation */ BA0WRITE4(sc, CS4280_ACCTL, ACCTL_ESYN | ACCTL_RSTN); delay(50*1000); /* XXX delay 50ms */ - + /* Assert valid frame signal */ BA0WRITE4(sc, CS4280_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN); @@ -976,11 +976,11 @@ void cs4280_close(void *addr) { struct cs4280_softc *sc = addr; - + /* XXX: already called in audio_close() */ cs4280_halt_output(sc); cs4280_halt_input(sc); - + sc->sc_pintr = 0; sc->sc_rintr = 0; } @@ -997,8 +997,8 @@ cs4280_set_params(void *addr, int setmode, int usemode, mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) { if ((setmode & mode) == 0) continue; - - p = mode == AUMODE_PLAY ? play : rec; + + p = mode == AUMODE_PLAY ? play : rec; if (p == play) { DPRINTFN(5,("play: sample=%ld precision=%d channels=%d\n", p->sample_rate, p->precision, p->channels)); @@ -1008,7 +1008,7 @@ cs4280_set_params(void *addr, int setmode, int usemode, } /* play back data format may be 8- or 16-bit and * either stereo or mono. - * playback rate may range from 8000Hz to 48000Hz + * playback rate may range from 8000Hz to 48000Hz * * capture data format must be 16bit stereo * and sample rate range from 11025Hz to 48000Hz. @@ -1078,7 +1078,7 @@ cs4280_halt_output(void *addr) { struct cs4280_softc *sc = addr; u_int32_t mem; - + mtx_enter(&audio_lock); mem = BA1READ4(sc, CS4280_PCTL); BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK); @@ -1143,8 +1143,8 @@ cs4280_allocmem(struct cs4280_softc *sc, size_t size, size_t align, sc->sc_dev.dv_xname, error); return (error); } - - error = bus_dmamem_map(sc->sc_dmatag, p->segs, p->nsegs, p->size, + + error = bus_dmamem_map(sc->sc_dmatag, p->segs, p->nsegs, p->size, &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); if (error) { printf("%s: unable to map dma, error=%d\n", @@ -1160,7 +1160,7 @@ cs4280_allocmem(struct cs4280_softc *sc, size_t size, size_t align, goto unmap; } - error = bus_dmamap_load(sc->sc_dmatag, p->map, p->addr, p->size, NULL, + error = bus_dmamap_load(sc->sc_dmatag, p->map, p->addr, p->size, NULL, BUS_DMA_NOWAIT); if (error) { printf("%s: unable to load dma map, error=%d\n", @@ -1186,17 +1186,17 @@ cs4280_malloc(void *addr, int direction, size_t size, int pool, int flags) struct cs4280_dma *p; caddr_t q; int error; - + DPRINTFN(5,("cs4280_malloc: size=%d pool=%d flags=%d\n", size, pool, flags)); q = malloc(size, pool, flags); - if (!q) + if (!q) return (0); p = malloc(sizeof(*p), pool, flags); if (!p) { free(q,pool, 0); return (0); } - /* + /* * cs4280 has fixed 4kB buffer */ error = cs4280_allocmem(sc, CS4280_DCHUNK, CS4280_DALIGN, p); @@ -1219,7 +1219,7 @@ cs4280_free(void *addr, void *ptr, int pool) { struct cs4280_softc *sc = addr; struct cs4280_dma **pp, *p; - + for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) { if (BUFADDR(p) == ptr) { cs4280_freemem(sc, p); @@ -1238,7 +1238,7 @@ cs4280_trigger_output(void *addr, void *start, void *end, int blksize, struct cs4280_softc *sc = addr; u_int32_t pfie, pctl, mem, pdtc; struct cs4280_dma *p; - + #ifdef DIAGNOSTIC if (sc->sc_prun) printf("cs4280_trigger_output: already running\n"); @@ -1258,7 +1258,7 @@ cs4280_trigger_output(void *addr, void *start, void *end, int blksize, pdtc &= ~PDTC_MASK; pdtc |= CS4280_MK_PDTC(param->precision * param->channels); BA1WRITE4(sc, CS4280_PDTC, pdtc); - + DPRINTF(("param: precision=%d channels=%d encoding=%d\n", param->precision, param->channels, param->encoding)); @@ -1327,7 +1327,7 @@ cs4280_trigger_input(void *addr, void *start, void *end, int blksize, struct cs4280_softc *sc = addr; u_int32_t cctl, cie; struct cs4280_dma *p; - + #ifdef DIAGNOSTIC if (sc->sc_rrun) printf("cs4280_trigger_input: already running\n"); @@ -1358,7 +1358,7 @@ cs4280_trigger_input(void *addr, void *start, void *end, int blksize, /* stop capture DMA */ cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK; BA1WRITE4(sc, CS4280_CCTL, cctl); - + for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next) ; if (!p) { @@ -1372,7 +1372,7 @@ cs4280_trigger_input(void *addr, void *start, void *end, int blksize, } sc->sc_rdma = p; sc->sc_rbuf = KERNADDR(p); - + /* initiate capture dma */ mtx_enter(&audio_lock); BA1WRITE4(sc, CS4280_CBA, DMAADDR(p)); @@ -1415,27 +1415,27 @@ cs4280_init(struct cs4280_softc *sc, int init) BA0WRITE4(sc, CS4280_ACCTL, 0); delay(100); /* delay 100us */ BA0WRITE4(sc, CS4280_ACCTL, ACCTL_RSTN); - + /* Enable AC-link sync generation */ BA0WRITE4(sc, CS4280_ACCTL, ACCTL_ESYN | ACCTL_RSTN); delay(50*1000); /* delay 50ms */ /* Set the serial port timing configuration */ BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97); - + /* Setup clock control */ BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE); BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE); BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8); - + /* Power up the PLL */ BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP); delay(50*1000); /* delay 50ms */ - + /* Turn on clock */ mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE; BA0WRITE4(sc, CS4280_CLKCR1, mem); - + /* Set the serial port FIFO pointer to the * first sample in FIFO. (not documented) */ cs4280_clear_fifos(sc); @@ -1444,12 +1444,12 @@ cs4280_init(struct cs4280_softc *sc, int init) /* Set the serial port FIFO pointer to the first sample in the FIFO */ BA0WRITE4(sc, CS4280_SERBSP, 0); #endif - + /* Configure the serial port */ BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97); BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97); BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97); - + /* Wait for CODEC ready */ n = 0; while ((BA0READ4(sc, CS4280_ACSTS) & ACSTS_CRDY) == 0) { @@ -1474,7 +1474,7 @@ cs4280_init(struct cs4280_softc *sc, int init) return(1); } } - + /* Set AC97 output slot valid signals */ BA0WRITE4(sc, CS4280_ACOSV, ACOSV_SLV3 | ACOSV_SLV4); @@ -1497,15 +1497,15 @@ cs4280_init2(struct cs4280_softc *sc, int init) /* Save playback parameter and then write zero. * this ensures that DMA doesn't immediately occur upon - * starting the processor core + * starting the processor core */ mem = BA1READ4(sc, CS4280_PCTL); sc->pctl = mem & PCTL_MASK; /* save startup value */ cs4280_halt_output(sc); - + /* Save capture parameter and then write zero. * this ensures that DMA doesn't immediately occur upon - * starting the processor core + * starting the processor core */ mem = BA1READ4(sc, CS4280_CCTL); sc->cctl = mem & CCTL_MASK; /* save startup value */ @@ -1526,7 +1526,7 @@ cs4280_init2(struct cs4280_softc *sc, int init) return(1); } } - + n = 0; while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) { delay(10); @@ -1595,8 +1595,8 @@ cs4280_clear_fifos(struct cs4280_softc *sc) { int pd = 0, cnt, n; u_int32_t mem; - - /* + + /* * If device power down, power up the device and keep power down * state. */ @@ -1655,7 +1655,7 @@ cs4280_midi_close(void *addr) { struct cs4280_softc *sc = addr; u_int32_t mem; - + DPRINTF(("midi_close\n")); mem = BA0READ4(sc, CS4280_MIDCR); mem &= ~MIDCR_MASK; diff --git a/sys/dev/pci/cs4281.c b/sys/dev/pci/cs4281.c index 93c96caa8..fa8305d86 100644 --- a/sys/dev/pci/cs4281.c +++ b/sys/dev/pci/cs4281.c @@ -136,11 +136,11 @@ struct cs4281_softc { #define MAX_FIFO_SIZE 64 /* 128/2 channels */ #endif -/* +/* * Hardware imposes the buffer size to be twice the block size, this * is OK, except that round_blocksize() is the only mean to expose * this hardware constraint but it doesn't know the buffer size. - * + * * So we've no other choice than hardcoding a buffer size */ #define DMA_SIZE (1024 * 4 * 2) @@ -240,7 +240,7 @@ int cs4281_match(struct device *parent, void *match, void *aux) { struct pci_attach_args *pa = (struct pci_attach_args *)aux; - + if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CIRRUS || PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_CIRRUS_CS4281) return (0); @@ -330,7 +330,7 @@ cs4281_intr(void *p) { struct cs4281_softc *sc = p; u_int32_t intr, val; - + mtx_enter(&audio_lock); intr = BA0READ4(sc, CS4281_HISR); if (!(intr & (HISR_DMA0 | HISR_DMA1 | HISR_MIDI))) { @@ -390,9 +390,9 @@ cs4281_set_params(void *addr, int setmode, int usemode, mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { if ((setmode & mode) == 0) continue; - + p = mode == AUMODE_PLAY ? play : rec; - + if (p == play) { DPRINTFN(5,("play: samp=%ld precision=%d channels=%d\n", p->sample_rate, p->precision, p->channels)); @@ -435,7 +435,7 @@ int cs4281_halt_output(void *addr) { struct cs4281_softc *sc = addr; - + BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK); #ifdef DIAGNOSTIC sc->sc_prun = 0; @@ -699,7 +699,7 @@ cs4281_init(struct cs4281_softc *sc) BA0WRITE4(sc, CS4281_CLKCR1, 0); /* Start serial ports out in known state */ BA0WRITE4(sc, CS4281_SERMC, 0); - + /* Reset codec */ BA0WRITE4(sc, CS4281_ACCTL, 0); delay(50); /* delay 50us */ @@ -761,7 +761,7 @@ cs4281_init(struct cs4281_softc *sc) /* Set the serial timing configuration */ /* XXX: undocumented but the Linux driver do this */ BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); - + /* Wait for Codec ready signal */ n = 0; do { @@ -776,7 +776,7 @@ cs4281_init(struct cs4281_softc *sc) /* Enable Valid Frame output on ASDOUT */ BA0WRITE4(sc, CS4281_ACCTL, ACCTL_ESYN | ACCTL_VFRM); - + /* Wait until Codec Calibration is finished. Codec register 26h */ n = 0; do { @@ -804,13 +804,13 @@ cs4281_init(struct cs4281_softc *sc) } dat32 = BA0READ4(sc, CS4281_ACISV) & (ACISV_ISV3 | ACISV_ISV4); } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); - + /* Start digital data transfer of audio data to the codec */ BA0WRITE4(sc, CS4281_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); - + cs4281_write_codec(sc, AC97_REG_HEADPHONE_VOLUME, 0); cs4281_write_codec(sc, AC97_REG_MASTER_VOLUME, 0); - + /* Power on the DAC */ cs4281_read_codec(sc, AC97_REG_POWER, &data); cs4281_write_codec(sc, AC97_REG_POWER, data &= 0xfdff); @@ -824,7 +824,7 @@ cs4281_init(struct cs4281_softc *sc) if (data & 0x02) break; } - + /* Power on the ADC */ cs4281_read_codec(sc, AC97_REG_POWER, &data); cs4281_write_codec(sc, AC97_REG_POWER, data &= 0xfeff); @@ -838,7 +838,7 @@ cs4281_init(struct cs4281_softc *sc) if (data & 0x01) break; } - + #if 0 /* Initialize SSCR register features */ /* XXX: hardware volume setting */ @@ -934,7 +934,7 @@ cs4281_init(struct cs4281_softc *sc) 0x01 << 8 | /* PRSS[4:0] Right PCM Playback */ 0x00 << 0; /* PLSS[4:0] Left PCM Playback */ BA0WRITE4(sc, CS4281_SRCSA, dat32); - + /* Set interrupt to occurred at Half and Full terminal * count interrupt enable for DMA channel 0 and 1. * To keep DMA stop, set MSK. @@ -942,7 +942,7 @@ cs4281_init(struct cs4281_softc *sc) dat32 = DCRn_HTCIE | DCRn_TCIE | DCRn_MSK; BA0WRITE4(sc, CS4281_DCR0, dat32); BA0WRITE4(sc, CS4281_DCR1, dat32); - + /* Set Auto-Initialize Control enable */ BA0WRITE4(sc, CS4281_DMR0, DMRn_DMA | DMRn_AUTO | DMRn_TR_READ); @@ -1028,7 +1028,7 @@ cs4281_reset_codec(void *addr) /* Set the serial timing configuration */ /* XXX: undocumented but the Linux driver do this */ BA0WRITE4(sc, CS4281_SERMC, SERMC_PTCAC97); - + /* Wait for Codec ready signal */ n = 0; do { @@ -1043,7 +1043,7 @@ cs4281_reset_codec(void *addr) /* Enable Valid Frame output on ASDOUT */ BA0WRITE4(sc, CS4281_ACCTL, ACCTL_ESYN | ACCTL_VFRM); - + /* Wait until Codec Calibration is finished. Codec register 26h */ n = 0; do { @@ -1071,7 +1071,7 @@ cs4281_reset_codec(void *addr) } dat32 = BA0READ4(sc, CS4281_ACISV) & (ACISV_ISV3 | ACISV_ISV4) ; } while (dat32 != (ACISV_ISV3 | ACISV_ISV4)); - + /* Start digital data transfer of audio data to the codec */ BA0WRITE4(sc, CS4281_ACOSV, (ACOSV_SLV3 | ACOSV_SLV4)); } @@ -1091,7 +1091,7 @@ cs4281_close(void *addr) (*sc->halt_output)(sc); (*sc->halt_input)(sc); - + sc->sc_pintr = 0; sc->sc_rintr = 0; } @@ -1267,14 +1267,14 @@ cs4281_allocmem(struct cs4281_softc *sc, size_t size, int pool, int flags, struct cs4281_dma *p) { int error; - + if (size != DMA_SIZE) { printf("%s: dma size is %zd should be %d\n", sc->sc_dev.dv_xname, size, DMA_SIZE); return ENOMEM; } - p->size = size; + p->size = size; /* allocate memory for upper audio driver */ error = bus_dmamem_alloc(sc->sc_dmatag, p->size, DMA_ALIGN, 0, diff --git a/sys/dev/pci/cs4281reg.h b/sys/dev/pci/cs4281reg.h index 4e8230a20..8ec81e055 100644 --- a/sys/dev/pci/cs4281reg.h +++ b/sys/dev/pci/cs4281reg.h @@ -32,7 +32,7 @@ */ -#define CS4281_BA0_SIZE +#define CS4281_BA0_SIZE #define CS4281_BA1_SIZE 0x10000 #define CS4281_BUFFER_SIZE 0x10000 diff --git a/sys/dev/pci/cy_pci.c b/sys/dev/pci/cy_pci.c index f85329689..a5f2a3610 100644 --- a/sys/dev/pci/cy_pci.c +++ b/sys/dev/pci/cy_pci.c @@ -165,7 +165,7 @@ cy_pci_attach(struct device *parent, struct device *self, void *aux) default: bus_space_write_2(psc->sc_iot, psc->sc_ioh, CY_PCI_INTENA, bus_space_read_2(psc->sc_iot, psc->sc_ioh, - CY_PCI_INTENA) | CY_PLX_9060_ICS_IENABLE | + CY_PCI_INTENA) | CY_PLX_9060_ICS_IENABLE | CY_PLX_9060_ICS_LOCAL_IENABLE); } } diff --git a/sys/dev/pci/drm/amd/amdgpu/ObjectID.h b/sys/dev/pci/drm/amd/amdgpu/ObjectID.h index a0f0a17e2..361559756 100644 --- a/sys/dev/pci/drm/amd/amdgpu/ObjectID.h +++ b/sys/dev/pci/drm/amd/amdgpu/ObjectID.h @@ -1,5 +1,5 @@ /* -* Copyright 2006-2007 Advanced Micro Devices, Inc. +* Copyright 2006-2007 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -37,13 +37,13 @@ #define GRAPH_OBJECT_TYPE_CONNECTOR 0x3 #define GRAPH_OBJECT_TYPE_ROUTER 0x4 /* deleted */ -#define GRAPH_OBJECT_TYPE_DISPLAY_PATH 0x6 +#define GRAPH_OBJECT_TYPE_DISPLAY_PATH 0x6 #define GRAPH_OBJECT_TYPE_GENERIC 0x7 /****************************************************/ /* Encoder Object ID Definition */ /****************************************************/ -#define ENCODER_OBJECT_ID_NONE 0x00 +#define ENCODER_OBJECT_ID_NONE 0x00 /* Radeon Class Display Hardware */ #define ENCODER_OBJECT_ID_INTERNAL_LVDS 0x01 @@ -96,7 +96,7 @@ /****************************************************/ /* Connector Object ID Definition */ /****************************************************/ -#define CONNECTOR_OBJECT_ID_NONE 0x00 +#define CONNECTOR_OBJECT_ID_NONE 0x00 #define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I 0x01 #define CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I 0x02 #define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D 0x03 @@ -158,7 +158,7 @@ #define RESERVED1_ID_MASK 0x0800 #define OBJECT_TYPE_MASK 0x7000 #define RESERVED2_ID_MASK 0x8000 - + #define OBJECT_ID_SHIFT 0x00 #define ENUM_ID_SHIFT 0x08 #define OBJECT_TYPE_SHIFT 0x0C @@ -179,14 +179,14 @@ /* Encoder Object ID definition - Shared with BIOS */ /****************************************************/ /* -#define ENCODER_INTERNAL_LVDS_ENUM_ID1 0x2101 +#define ENCODER_INTERNAL_LVDS_ENUM_ID1 0x2101 #define ENCODER_INTERNAL_TMDS1_ENUM_ID1 0x2102 #define ENCODER_INTERNAL_TMDS2_ENUM_ID1 0x2103 #define ENCODER_INTERNAL_DAC1_ENUM_ID1 0x2104 #define ENCODER_INTERNAL_DAC2_ENUM_ID1 0x2105 #define ENCODER_INTERNAL_SDVOA_ENUM_ID1 0x2106 #define ENCODER_INTERNAL_SDVOB_ENUM_ID1 0x2107 -#define ENCODER_SIL170B_ENUM_ID1 0x2108 +#define ENCODER_SIL170B_ENUM_ID1 0x2108 #define ENCODER_CH7303_ENUM_ID1 0x2109 #define ENCODER_CH7301_ENUM_ID1 0x210A #define ENCODER_INTERNAL_DVO1_ENUM_ID1 0x210B @@ -200,8 +200,8 @@ #define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1 0x2113 #define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1 0x2114 #define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1 0x2115 -#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 0x2116 -#define ENCODER_SI178_ENUM_ID1 0x2117 +#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 0x2116 +#define ENCODER_SI178_ENUM_ID1 0x2117 #define ENCODER_MVPU_FPGA_ENUM_ID1 0x2118 #define ENCODER_INTERNAL_DDI_ENUM_ID1 0x2119 #define ENCODER_VT1625_ENUM_ID1 0x211A @@ -316,7 +316,7 @@ #define ENCODER_SI178_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_SI178 << OBJECT_ID_SHIFT) + ENCODER_OBJECT_ID_SI178 << OBJECT_ID_SHIFT) #define ENCODER_MVPU_FPGA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ @@ -324,7 +324,7 @@ #define ENCODER_INTERNAL_DDI_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_INTERNAL_DDI << OBJECT_ID_SHIFT) + ENCODER_OBJECT_ID_INTERNAL_DDI << OBJECT_ID_SHIFT) #define ENCODER_VT1625_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ @@ -352,7 +352,7 @@ #define ENCODER_INTERNAL_KLDSCP_LVTMA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ - ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA << OBJECT_ID_SHIFT) + ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA << OBJECT_ID_SHIFT) #define ENCODER_INTERNAL_UNIPHY1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ diff --git a/sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c b/sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c index 803e2d9dc..12d76d2ce 100644 --- a/sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c +++ b/sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c @@ -6227,7 +6227,7 @@ int amdgpu_in_reset(struct amdgpu_device *adev) { return atomic_read(&adev->reset_domain->in_gpu_reset); } - + /** * amdgpu_device_halt() - bring hardware to some kind of halt state * diff --git a/sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c b/sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c index 57144ac7b..9683a8b33 100644 --- a/sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c +++ b/sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c @@ -3438,7 +3438,7 @@ amdgpu_init_backlight(struct amdgpu_device *adev) if (bd == NULL) return; - + drm_connector_list_iter_begin(dev, &conn_iter); drm_for_each_connector_iter(connector, &conn_iter) { if (connector->connector_type != DRM_MODE_CONNECTOR_LVDS && diff --git a/sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c b/sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c index a6b66b4d4..27c9f3523 100644 --- a/sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c +++ b/sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c @@ -1098,7 +1098,7 @@ void amdgpu_bo_fini(struct amdgpu_device *adev) arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size); #else drm_mtrr_del(0, adev->gmc.aper_base, adev->gmc.aper_size, DRM_MTRR_WC); - + #endif } drm_dev_exit(idx); diff --git a/sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c b/sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c index f8f245781..f26c20e8d 100644 --- a/sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c +++ b/sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c @@ -101,7 +101,7 @@ amdgpu_vm_it_iter_next(struct amdgpu_bo_va_mapping *node, uint64_t start, static void amdgpu_vm_it_remove(struct amdgpu_bo_va_mapping *node, - struct rb_root_cached *root) + struct rb_root_cached *root) { rb_erase_cached(&node->rb, root); } diff --git a/sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c b/sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c index 3ebb51ca9..e7c03a018 100644 --- a/sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c +++ b/sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c @@ -1906,7 +1906,7 @@ static int gfx_v11_0_rlc_load_microcode(struct amdgpu_device *adev) if (version_minor == 3) gfx_v11_0_load_rlcp_rlcv_microcode(adev); } - + return 0; } @@ -3348,7 +3348,7 @@ static int gfx_v11_0_cp_compute_load_microcode(struct amdgpu_device *adev) } memcpy(fw, fw_data, fw_size); - + amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); diff --git a/sys/dev/pci/drm/amd/amdgpu/imu_v11_0.c b/sys/dev/pci/drm/amd/amdgpu/imu_v11_0.c index 8ec1b9699..d588a4939 100644 --- a/sys/dev/pci/drm/amd/amdgpu/imu_v11_0.c +++ b/sys/dev/pci/drm/amd/amdgpu/imu_v11_0.c @@ -58,7 +58,7 @@ static int imu_v11_0_init_microcode(struct amdgpu_device *adev) imu_hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data; adev->gfx.imu_fw_version = le32_to_cpu(imu_hdr->header.ucode_version); //adev->gfx.imu_feature_version = le32_to_cpu(imu_hdr->ucode_feature_version); - + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { info = &adev->firmware.ucode[AMDGPU_UCODE_ID_IMU_I]; info->ucode_id = AMDGPU_UCODE_ID_IMU_I; @@ -240,9 +240,9 @@ static const struct imu_rlc_ram_golden imu_rlc_ram_golden_11[] = IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_BOT, 0x00000002, 0xe0000000), IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_TOP, 0x00000000, 0xe0000000), IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL2, 0x00020000, 0xe0000000), - IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA0_UCODE_SELFLOAD_CONTROL, 0x00000210, 0), - IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA1_UCODE_SELFLOAD_CONTROL, 0x00000210, 0), - IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCPC_PSP_DEBUG, CPC_PSP_DEBUG__GPA_OVERRIDE_MASK, 0), + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA0_UCODE_SELFLOAD_CONTROL, 0x00000210, 0), + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA1_UCODE_SELFLOAD_CONTROL, 0x00000210, 0), + IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCPC_PSP_DEBUG, CPC_PSP_DEBUG__GPA_OVERRIDE_MASK, 0), IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCPG_PSP_DEBUG, CPG_PSP_DEBUG__GPA_OVERRIDE_MASK, 0) }; diff --git a/sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c b/sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c index 0c16f2977..f2b487573 100644 --- a/sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c +++ b/sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c @@ -186,7 +186,7 @@ static int xgpu_ai_send_access_requests(struct amdgpu_device *adev, /* Dummy REQ_GPU_INIT_DATA handling */ r = xgpu_ai_poll_msg(adev, IDH_REQ_GPU_INIT_DATA_READY); /* version set to 0 since dummy */ - adev->virt.req_init_data_ver = 0; + adev->virt.req_init_data_ver = 0; } return 0; diff --git a/sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c b/sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c index 4c9e51093..8a9b9786a 100644 --- a/sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c +++ b/sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c @@ -273,7 +273,7 @@ static int sdma_v5_0_init_microcode(struct amdgpu_device *adev) if (ret) return ret; } - + return ret; } diff --git a/sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c b/sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c index f679b910a..49fc7cc3b 100644 --- a/sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c +++ b/sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c @@ -770,7 +770,7 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc, aux_defer_retries, AUX_MAX_RETRIES); goto fail; - } else + } else udelay(300); } else if (payload->write && ret > 0) { /* sink requested more time to complete the write via AUX_ACKM */ diff --git a/sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_resource.c b/sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_resource.c index f04595b75..4b994c923 100644 --- a/sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_resource.c +++ b/sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_resource.c @@ -672,7 +672,7 @@ static const struct dc_plane_cap plane_cap = { .max_downscale_factor = { .argb8888 = 167, .nv12 = 167, - .fp16 = 167 + .fp16 = 167 }, 64, 64 diff --git a/sys/dev/pci/drm/amd/display/modules/color/color_gamma.c b/sys/dev/pci/drm/amd/display/modules/color/color_gamma.c index 447a0ec9c..518dad437 100644 --- a/sys/dev/pci/drm/amd/display/modules/color/color_gamma.c +++ b/sys/dev/pci/drm/amd/display/modules/color/color_gamma.c @@ -359,7 +359,7 @@ static struct fixed31_32 translate_from_linear_space( scratch_1 = dc_fixpt_add(one, args->a3); /* In the first region (first 16 points) and in the * region delimited by START/END we calculate with - * full precision to avoid error accumulation. + * full precision to avoid error accumulation. */ if ((cal_buffer->buffer_index >= PRECISE_LUT_REGION_START && cal_buffer->buffer_index <= PRECISE_LUT_REGION_END) || diff --git a/sys/dev/pci/drm/amd/include/amd_shared.h b/sys/dev/pci/drm/amd/include/amd_shared.h index f175e65b8..46ed216f0 100644 --- a/sys/dev/pci/drm/amd/include/amd_shared.h +++ b/sys/dev/pci/drm/amd/include/amd_shared.h @@ -60,7 +60,7 @@ enum amd_apu_flags { * acquires the list of IP blocks for the GPU in use on initialization. * It can then operate on this list to perform standard driver operations * such as: init, fini, suspend, resume, etc. -* +* * * IP block implementations are named using the following convention: * _v (E.g.: gfx_v6_0). diff --git a/sys/dev/pci/drm/amd/include/asic_reg/nbif/nbif_6_1_offset.h b/sys/dev/pci/drm/amd/include/asic_reg/nbif/nbif_6_1_offset.h index 92fd27c26..0c8717c4e 100644 --- a/sys/dev/pci/drm/amd/include/asic_reg/nbif/nbif_6_1_offset.h +++ b/sys/dev/pci/drm/amd/include/asic_reg/nbif/nbif_6_1_offset.h @@ -24,549 +24,549 @@ // addressBlock: bif_cfg_dev0_epf0_bifcfgdecp // base address: 0x0 -#define cfgVENDOR_ID 0x0000 // duplicate -#define cfgDEVICE_ID 0x0002 // duplicate -#define cfgCOMMAND 0x0004 // duplicate -#define cfgSTATUS 0x0006 // duplicate -#define cfgREVISION_ID 0x0008 // duplicate -#define cfgPROG_INTERFACE 0x0009 // duplicate -#define cfgSUB_CLASS 0x000a // duplicate -#define cfgBASE_CLASS 0x000b // duplicate -#define cfgCACHE_LINE 0x000c // duplicate -#define cfgLATENCY 0x000d // duplicate -#define cfgHEADER 0x000e // duplicate -#define cfgBIST 0x000f // duplicate -#define cfgBASE_ADDR_1 0x0010 // duplicate -#define cfgBASE_ADDR_2 0x0014 // duplicate -#define cfgBASE_ADDR_3 0x0018 // duplicate -#define cfgBASE_ADDR_4 0x001c // duplicate -#define cfgBASE_ADDR_5 0x0020 // duplicate -#define cfgBASE_ADDR_6 0x0024 // duplicate -#define cfgADAPTER_ID 0x002c // duplicate -#define cfgROM_BASE_ADDR 0x0030 // duplicate -#define cfgCAP_PTR 0x0034 // duplicate -#define cfgINTERRUPT_LINE 0x003c // duplicate -#define cfgINTERRUPT_PIN 0x003d // duplicate -#define cfgMIN_GRANT 0x003e // duplicate -#define cfgMAX_LATENCY 0x003f // duplicate -#define cfgVENDOR_CAP_LIST 0x0048 // duplicate -#define cfgADAPTER_ID_W 0x004c // duplicate -#define cfgPMI_CAP_LIST 0x0050 // duplicate -#define cfgPMI_CAP 0x0052 // duplicate -#define cfgPMI_STATUS_CNTL 0x0054 // duplicate -#define cfgPCIE_CAP_LIST 0x0064 // duplicate -#define cfgPCIE_CAP 0x0066 // duplicate -#define cfgDEVICE_CAP 0x0068 // duplicate -#define cfgDEVICE_CNTL 0x006c // duplicate -#define cfgDEVICE_STATUS 0x006e // duplicate -#define cfgLINK_CAP 0x0070 // duplicate -#define cfgLINK_CNTL 0x0074 // duplicate -#define cfgLINK_STATUS 0x0076 // duplicate -#define cfgDEVICE_CAP2 0x0088 // duplicate -#define cfgDEVICE_CNTL2 0x008c // duplicate -#define cfgDEVICE_STATUS2 0x008e // duplicate -#define cfgLINK_CAP2 0x0090 // duplicate -#define cfgLINK_CNTL2 0x0094 // duplicate -#define cfgLINK_STATUS2 0x0096 // duplicate -#define cfgSLOT_CAP2 0x0098 // duplicate -#define cfgSLOT_CNTL2 0x009c // duplicate -#define cfgSLOT_STATUS2 0x009e // duplicate -#define cfgMSI_CAP_LIST 0x00a0 // duplicate -#define cfgMSI_MSG_CNTL 0x00a2 // duplicate -#define cfgMSI_MSG_ADDR_LO 0x00a4 // duplicate -#define cfgMSI_MSG_ADDR_HI 0x00a8 // duplicate -#define cfgMSI_MSG_DATA 0x00a8 // duplicate -#define cfgMSI_MSG_DATA_64 0x00ac // duplicate -#define cfgMSI_MASK 0x00ac // duplicate -#define cfgMSI_PENDING 0x00b0 // duplicate -#define cfgMSI_MASK_64 0x00b0 // duplicate -#define cfgMSI_PENDING_64 0x00b4 // duplicate -#define cfgMSIX_CAP_LIST 0x00c0 // duplicate -#define cfgMSIX_MSG_CNTL 0x00c2 // duplicate -#define cfgMSIX_TABLE 0x00c4 // duplicate -#define cfgMSIX_PBA 0x00c8 // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR 0x0104 // duplicate -#define cfgPCIE_VENDOR_SPECIFIC1 0x0108 // duplicate -#define cfgPCIE_VENDOR_SPECIFIC2 0x010c // duplicate -#define cfgPCIE_VC_ENH_CAP_LIST 0x0110 // duplicate -#define cfgPCIE_PORT_VC_CAP_REG1 0x0114 // duplicate -#define cfgPCIE_PORT_VC_CAP_REG2 0x0118 // duplicate -#define cfgPCIE_PORT_VC_CNTL 0x011c // duplicate -#define cfgPCIE_PORT_VC_STATUS 0x011e // duplicate -#define cfgPCIE_VC0_RESOURCE_CAP 0x0120 // duplicate -#define cfgPCIE_VC0_RESOURCE_CNTL 0x0124 // duplicate -#define cfgPCIE_VC0_RESOURCE_STATUS 0x012a // duplicate -#define cfgPCIE_VC1_RESOURCE_CAP 0x012c // duplicate -#define cfgPCIE_VC1_RESOURCE_CNTL 0x0130 // duplicate -#define cfgPCIE_VC1_RESOURCE_STATUS 0x0136 // duplicate -#define cfgPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 // duplicate -#define cfgPCIE_DEV_SERIAL_NUM_DW1 0x0144 // duplicate -#define cfgPCIE_DEV_SERIAL_NUM_DW2 0x0148 // duplicate -#define cfgPCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 // duplicate -#define cfgPCIE_UNCORR_ERR_STATUS 0x0154 // duplicate -#define cfgPCIE_UNCORR_ERR_MASK 0x0158 // duplicate -#define cfgPCIE_UNCORR_ERR_SEVERITY 0x015c // duplicate -#define cfgPCIE_CORR_ERR_STATUS 0x0160 // duplicate -#define cfgPCIE_CORR_ERR_MASK 0x0164 // duplicate -#define cfgPCIE_ADV_ERR_CAP_CNTL 0x0168 // duplicate -#define cfgPCIE_HDR_LOG0 0x016c // duplicate -#define cfgPCIE_HDR_LOG1 0x0170 // duplicate -#define cfgPCIE_HDR_LOG2 0x0174 // duplicate -#define cfgPCIE_HDR_LOG3 0x0178 // duplicate -#define cfgPCIE_ROOT_ERR_CMD 0x017c // duplicate -#define cfgPCIE_ROOT_ERR_STATUS 0x0180 // duplicate -#define cfgPCIE_ERR_SRC_ID 0x0184 // duplicate -#define cfgPCIE_TLP_PREFIX_LOG0 0x0188 // duplicate -#define cfgPCIE_TLP_PREFIX_LOG1 0x018c // duplicate -#define cfgPCIE_TLP_PREFIX_LOG2 0x0190 // duplicate -#define cfgPCIE_TLP_PREFIX_LOG3 0x0194 // duplicate -#define cfgPCIE_BAR_ENH_CAP_LIST 0x0200 // duplicate -#define cfgPCIE_BAR1_CAP 0x0204 // duplicate -#define cfgPCIE_BAR1_CNTL 0x0208 // duplicate -#define cfgPCIE_BAR2_CAP 0x020c // duplicate -#define cfgPCIE_BAR2_CNTL 0x0210 // duplicate -#define cfgPCIE_BAR3_CAP 0x0214 // duplicate -#define cfgPCIE_BAR3_CNTL 0x0218 // duplicate -#define cfgPCIE_BAR4_CAP 0x021c // duplicate -#define cfgPCIE_BAR4_CNTL 0x0220 // duplicate -#define cfgPCIE_BAR5_CAP 0x0224 // duplicate -#define cfgPCIE_BAR5_CNTL 0x0228 // duplicate -#define cfgPCIE_BAR6_CAP 0x022c // duplicate -#define cfgPCIE_BAR6_CNTL 0x0230 // duplicate -#define cfgPCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 // duplicate -#define cfgPCIE_PWR_BUDGET_DATA_SELECT 0x0244 // duplicate -#define cfgPCIE_PWR_BUDGET_DATA 0x0248 // duplicate -#define cfgPCIE_PWR_BUDGET_CAP 0x024c // duplicate -#define cfgPCIE_DPA_ENH_CAP_LIST 0x0250 // duplicate -#define cfgPCIE_DPA_CAP 0x0254 // duplicate -#define cfgPCIE_DPA_LATENCY_INDICATOR 0x0258 // duplicate -#define cfgPCIE_DPA_STATUS 0x025c // duplicate -#define cfgPCIE_DPA_CNTL 0x025e // duplicate -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 // duplicate -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 // duplicate -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 // duplicate -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 // duplicate -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 // duplicate -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 // duplicate -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 // duplicate -#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 // duplicate -#define cfgPCIE_SECONDARY_ENH_CAP_LIST 0x0270 // duplicate -#define cfgPCIE_LINK_CNTL3 0x0274 // duplicate -#define cfgPCIE_LANE_ERROR_STATUS 0x0278 // duplicate -#define cfgPCIE_LANE_0_EQUALIZATION_CNTL 0x027c // duplicate -#define cfgPCIE_LANE_1_EQUALIZATION_CNTL 0x027e // duplicate -#define cfgPCIE_LANE_2_EQUALIZATION_CNTL 0x0280 // duplicate -#define cfgPCIE_LANE_3_EQUALIZATION_CNTL 0x0282 // duplicate -#define cfgPCIE_LANE_4_EQUALIZATION_CNTL 0x0284 // duplicate -#define cfgPCIE_LANE_5_EQUALIZATION_CNTL 0x0286 // duplicate -#define cfgPCIE_LANE_6_EQUALIZATION_CNTL 0x0288 // duplicate -#define cfgPCIE_LANE_7_EQUALIZATION_CNTL 0x028a // duplicate -#define cfgPCIE_LANE_8_EQUALIZATION_CNTL 0x028c // duplicate -#define cfgPCIE_LANE_9_EQUALIZATION_CNTL 0x028e // duplicate -#define cfgPCIE_LANE_10_EQUALIZATION_CNTL 0x0290 // duplicate -#define cfgPCIE_LANE_11_EQUALIZATION_CNTL 0x0292 // duplicate -#define cfgPCIE_LANE_12_EQUALIZATION_CNTL 0x0294 // duplicate -#define cfgPCIE_LANE_13_EQUALIZATION_CNTL 0x0296 // duplicate -#define cfgPCIE_LANE_14_EQUALIZATION_CNTL 0x0298 // duplicate -#define cfgPCIE_LANE_15_EQUALIZATION_CNTL 0x029a // duplicate -#define cfgPCIE_ACS_ENH_CAP_LIST 0x02a0 // duplicate -#define cfgPCIE_ACS_CAP 0x02a4 // duplicate -#define cfgPCIE_ACS_CNTL 0x02a6 // duplicate -#define cfgPCIE_ATS_ENH_CAP_LIST 0x02b0 // duplicate -#define cfgPCIE_ATS_CAP 0x02b4 // duplicate -#define cfgPCIE_ATS_CNTL 0x02b6 // duplicate -#define cfgPCIE_PAGE_REQ_ENH_CAP_LIST 0x02c0 // duplicate -#define cfgPCIE_PAGE_REQ_CNTL 0x02c4 // duplicate -#define cfgPCIE_PAGE_REQ_STATUS 0x02c6 // duplicate -#define cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x02c8 // duplicate -#define cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC 0x02cc // duplicate -#define cfgPCIE_PASID_ENH_CAP_LIST 0x02d0 // duplicate -#define cfgPCIE_PASID_CAP 0x02d4 // duplicate -#define cfgPCIE_PASID_CNTL 0x02d6 // duplicate -#define cfgPCIE_TPH_REQR_ENH_CAP_LIST 0x02e0 // duplicate -#define cfgPCIE_TPH_REQR_CAP 0x02e4 // duplicate -#define cfgPCIE_TPH_REQR_CNTL 0x02e8 // duplicate -#define cfgPCIE_MC_ENH_CAP_LIST 0x02f0 // duplicate -#define cfgPCIE_MC_CAP 0x02f4 // duplicate -#define cfgPCIE_MC_CNTL 0x02f6 // duplicate -#define cfgPCIE_MC_ADDR0 0x02f8 // duplicate -#define cfgPCIE_MC_ADDR1 0x02fc // duplicate -#define cfgPCIE_MC_RCV0 0x0300 // duplicate -#define cfgPCIE_MC_RCV1 0x0304 // duplicate -#define cfgPCIE_MC_BLOCK_ALL0 0x0308 // duplicate -#define cfgPCIE_MC_BLOCK_ALL1 0x030c // duplicate -#define cfgPCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 // duplicate -#define cfgPCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 // duplicate -#define cfgPCIE_LTR_ENH_CAP_LIST 0x0320 // duplicate -#define cfgPCIE_LTR_CAP 0x0324 // duplicate -#define cfgPCIE_ARI_ENH_CAP_LIST 0x0328 // duplicate -#define cfgPCIE_ARI_CAP 0x032c // duplicate -#define cfgPCIE_ARI_CNTL 0x032e // duplicate -#define cfgPCIE_SRIOV_ENH_CAP_LIST 0x0330 // duplicate -#define cfgPCIE_SRIOV_CAP 0x0334 // duplicate -#define cfgPCIE_SRIOV_CONTROL 0x0338 // duplicate -#define cfgPCIE_SRIOV_STATUS 0x033a // duplicate -#define cfgPCIE_SRIOV_INITIAL_VFS 0x033c // duplicate -#define cfgPCIE_SRIOV_TOTAL_VFS 0x033e // duplicate -#define cfgPCIE_SRIOV_NUM_VFS 0x0340 // duplicate -#define cfgPCIE_SRIOV_FUNC_DEP_LINK 0x0342 // duplicate -#define cfgPCIE_SRIOV_FIRST_VF_OFFSET 0x0344 // duplicate -#define cfgPCIE_SRIOV_VF_STRIDE 0x0346 // duplicate -#define cfgPCIE_SRIOV_VF_DEVICE_ID 0x034a // duplicate -#define cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c // duplicate -#define cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350 // duplicate -#define cfgPCIE_SRIOV_VF_BASE_ADDR_0 0x0354 // duplicate -#define cfgPCIE_SRIOV_VF_BASE_ADDR_1 0x0358 // duplicate -#define cfgPCIE_SRIOV_VF_BASE_ADDR_2 0x035c // duplicate -#define cfgPCIE_SRIOV_VF_BASE_ADDR_3 0x0360 // duplicate -#define cfgPCIE_SRIOV_VF_BASE_ADDR_4 0x0364 // duplicate -#define cfgPCIE_SRIOV_VF_BASE_ADDR_5 0x0368 // duplicate -#define cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x036c // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x0400 // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x0404 // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x0408 // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x040c // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x0410 // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x0414 // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x0418 // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x041c // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x0420 // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x0424 // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x0428 // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x042c // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x0430 // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x0434 // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x0438 // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x043c // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x0440 // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x0444 // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x0448 // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x044c // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x0450 // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x0454 // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x0458 // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x045c // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x0460 // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x0464 // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x0468 // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x046c // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 0x0470 // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 0x0474 // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 0x0478 // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 0x047c // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 0x0480 // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 0x0484 // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 0x0488 // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 0x048c // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 0x0490 // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 0x0494 // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 0x0498 // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 0x049c // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 0x04a0 // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 0x04a4 // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 0x04a8 // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 0x04ac // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 0x04b0 // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 0x04b4 // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 0x04b8 // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 0x04bc // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 0x04c0 // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 0x04c4 // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 0x04c8 // duplicate -#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 0x04cc // duplicate +#define cfgVENDOR_ID 0x0000 // duplicate +#define cfgDEVICE_ID 0x0002 // duplicate +#define cfgCOMMAND 0x0004 // duplicate +#define cfgSTATUS 0x0006 // duplicate +#define cfgREVISION_ID 0x0008 // duplicate +#define cfgPROG_INTERFACE 0x0009 // duplicate +#define cfgSUB_CLASS 0x000a // duplicate +#define cfgBASE_CLASS 0x000b // duplicate +#define cfgCACHE_LINE 0x000c // duplicate +#define cfgLATENCY 0x000d // duplicate +#define cfgHEADER 0x000e // duplicate +#define cfgBIST 0x000f // duplicate +#define cfgBASE_ADDR_1 0x0010 // duplicate +#define cfgBASE_ADDR_2 0x0014 // duplicate +#define cfgBASE_ADDR_3 0x0018 // duplicate +#define cfgBASE_ADDR_4 0x001c // duplicate +#define cfgBASE_ADDR_5 0x0020 // duplicate +#define cfgBASE_ADDR_6 0x0024 // duplicate +#define cfgADAPTER_ID 0x002c // duplicate +#define cfgROM_BASE_ADDR 0x0030 // duplicate +#define cfgCAP_PTR 0x0034 // duplicate +#define cfgINTERRUPT_LINE 0x003c // duplicate +#define cfgINTERRUPT_PIN 0x003d // duplicate +#define cfgMIN_GRANT 0x003e // duplicate +#define cfgMAX_LATENCY 0x003f // duplicate +#define cfgVENDOR_CAP_LIST 0x0048 // duplicate +#define cfgADAPTER_ID_W 0x004c // duplicate +#define cfgPMI_CAP_LIST 0x0050 // duplicate +#define cfgPMI_CAP 0x0052 // duplicate +#define cfgPMI_STATUS_CNTL 0x0054 // duplicate +#define cfgPCIE_CAP_LIST 0x0064 // duplicate +#define cfgPCIE_CAP 0x0066 // duplicate +#define cfgDEVICE_CAP 0x0068 // duplicate +#define cfgDEVICE_CNTL 0x006c // duplicate +#define cfgDEVICE_STATUS 0x006e // duplicate +#define cfgLINK_CAP 0x0070 // duplicate +#define cfgLINK_CNTL 0x0074 // duplicate +#define cfgLINK_STATUS 0x0076 // duplicate +#define cfgDEVICE_CAP2 0x0088 // duplicate +#define cfgDEVICE_CNTL2 0x008c // duplicate +#define cfgDEVICE_STATUS2 0x008e // duplicate +#define cfgLINK_CAP2 0x0090 // duplicate +#define cfgLINK_CNTL2 0x0094 // duplicate +#define cfgLINK_STATUS2 0x0096 // duplicate +#define cfgSLOT_CAP2 0x0098 // duplicate +#define cfgSLOT_CNTL2 0x009c // duplicate +#define cfgSLOT_STATUS2 0x009e // duplicate +#define cfgMSI_CAP_LIST 0x00a0 // duplicate +#define cfgMSI_MSG_CNTL 0x00a2 // duplicate +#define cfgMSI_MSG_ADDR_LO 0x00a4 // duplicate +#define cfgMSI_MSG_ADDR_HI 0x00a8 // duplicate +#define cfgMSI_MSG_DATA 0x00a8 // duplicate +#define cfgMSI_MSG_DATA_64 0x00ac // duplicate +#define cfgMSI_MASK 0x00ac // duplicate +#define cfgMSI_PENDING 0x00b0 // duplicate +#define cfgMSI_MASK_64 0x00b0 // duplicate +#define cfgMSI_PENDING_64 0x00b4 // duplicate +#define cfgMSIX_CAP_LIST 0x00c0 // duplicate +#define cfgMSIX_MSG_CNTL 0x00c2 // duplicate +#define cfgMSIX_TABLE 0x00c4 // duplicate +#define cfgMSIX_PBA 0x00c8 // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR 0x0104 // duplicate +#define cfgPCIE_VENDOR_SPECIFIC1 0x0108 // duplicate +#define cfgPCIE_VENDOR_SPECIFIC2 0x010c // duplicate +#define cfgPCIE_VC_ENH_CAP_LIST 0x0110 // duplicate +#define cfgPCIE_PORT_VC_CAP_REG1 0x0114 // duplicate +#define cfgPCIE_PORT_VC_CAP_REG2 0x0118 // duplicate +#define cfgPCIE_PORT_VC_CNTL 0x011c // duplicate +#define cfgPCIE_PORT_VC_STATUS 0x011e // duplicate +#define cfgPCIE_VC0_RESOURCE_CAP 0x0120 // duplicate +#define cfgPCIE_VC0_RESOURCE_CNTL 0x0124 // duplicate +#define cfgPCIE_VC0_RESOURCE_STATUS 0x012a // duplicate +#define cfgPCIE_VC1_RESOURCE_CAP 0x012c // duplicate +#define cfgPCIE_VC1_RESOURCE_CNTL 0x0130 // duplicate +#define cfgPCIE_VC1_RESOURCE_STATUS 0x0136 // duplicate +#define cfgPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 // duplicate +#define cfgPCIE_DEV_SERIAL_NUM_DW1 0x0144 // duplicate +#define cfgPCIE_DEV_SERIAL_NUM_DW2 0x0148 // duplicate +#define cfgPCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 // duplicate +#define cfgPCIE_UNCORR_ERR_STATUS 0x0154 // duplicate +#define cfgPCIE_UNCORR_ERR_MASK 0x0158 // duplicate +#define cfgPCIE_UNCORR_ERR_SEVERITY 0x015c // duplicate +#define cfgPCIE_CORR_ERR_STATUS 0x0160 // duplicate +#define cfgPCIE_CORR_ERR_MASK 0x0164 // duplicate +#define cfgPCIE_ADV_ERR_CAP_CNTL 0x0168 // duplicate +#define cfgPCIE_HDR_LOG0 0x016c // duplicate +#define cfgPCIE_HDR_LOG1 0x0170 // duplicate +#define cfgPCIE_HDR_LOG2 0x0174 // duplicate +#define cfgPCIE_HDR_LOG3 0x0178 // duplicate +#define cfgPCIE_ROOT_ERR_CMD 0x017c // duplicate +#define cfgPCIE_ROOT_ERR_STATUS 0x0180 // duplicate +#define cfgPCIE_ERR_SRC_ID 0x0184 // duplicate +#define cfgPCIE_TLP_PREFIX_LOG0 0x0188 // duplicate +#define cfgPCIE_TLP_PREFIX_LOG1 0x018c // duplicate +#define cfgPCIE_TLP_PREFIX_LOG2 0x0190 // duplicate +#define cfgPCIE_TLP_PREFIX_LOG3 0x0194 // duplicate +#define cfgPCIE_BAR_ENH_CAP_LIST 0x0200 // duplicate +#define cfgPCIE_BAR1_CAP 0x0204 // duplicate +#define cfgPCIE_BAR1_CNTL 0x0208 // duplicate +#define cfgPCIE_BAR2_CAP 0x020c // duplicate +#define cfgPCIE_BAR2_CNTL 0x0210 // duplicate +#define cfgPCIE_BAR3_CAP 0x0214 // duplicate +#define cfgPCIE_BAR3_CNTL 0x0218 // duplicate +#define cfgPCIE_BAR4_CAP 0x021c // duplicate +#define cfgPCIE_BAR4_CNTL 0x0220 // duplicate +#define cfgPCIE_BAR5_CAP 0x0224 // duplicate +#define cfgPCIE_BAR5_CNTL 0x0228 // duplicate +#define cfgPCIE_BAR6_CAP 0x022c // duplicate +#define cfgPCIE_BAR6_CNTL 0x0230 // duplicate +#define cfgPCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 // duplicate +#define cfgPCIE_PWR_BUDGET_DATA_SELECT 0x0244 // duplicate +#define cfgPCIE_PWR_BUDGET_DATA 0x0248 // duplicate +#define cfgPCIE_PWR_BUDGET_CAP 0x024c // duplicate +#define cfgPCIE_DPA_ENH_CAP_LIST 0x0250 // duplicate +#define cfgPCIE_DPA_CAP 0x0254 // duplicate +#define cfgPCIE_DPA_LATENCY_INDICATOR 0x0258 // duplicate +#define cfgPCIE_DPA_STATUS 0x025c // duplicate +#define cfgPCIE_DPA_CNTL 0x025e // duplicate +#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 // duplicate +#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 // duplicate +#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 // duplicate +#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 // duplicate +#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 // duplicate +#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 // duplicate +#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 // duplicate +#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 // duplicate +#define cfgPCIE_SECONDARY_ENH_CAP_LIST 0x0270 // duplicate +#define cfgPCIE_LINK_CNTL3 0x0274 // duplicate +#define cfgPCIE_LANE_ERROR_STATUS 0x0278 // duplicate +#define cfgPCIE_LANE_0_EQUALIZATION_CNTL 0x027c // duplicate +#define cfgPCIE_LANE_1_EQUALIZATION_CNTL 0x027e // duplicate +#define cfgPCIE_LANE_2_EQUALIZATION_CNTL 0x0280 // duplicate +#define cfgPCIE_LANE_3_EQUALIZATION_CNTL 0x0282 // duplicate +#define cfgPCIE_LANE_4_EQUALIZATION_CNTL 0x0284 // duplicate +#define cfgPCIE_LANE_5_EQUALIZATION_CNTL 0x0286 // duplicate +#define cfgPCIE_LANE_6_EQUALIZATION_CNTL 0x0288 // duplicate +#define cfgPCIE_LANE_7_EQUALIZATION_CNTL 0x028a // duplicate +#define cfgPCIE_LANE_8_EQUALIZATION_CNTL 0x028c // duplicate +#define cfgPCIE_LANE_9_EQUALIZATION_CNTL 0x028e // duplicate +#define cfgPCIE_LANE_10_EQUALIZATION_CNTL 0x0290 // duplicate +#define cfgPCIE_LANE_11_EQUALIZATION_CNTL 0x0292 // duplicate +#define cfgPCIE_LANE_12_EQUALIZATION_CNTL 0x0294 // duplicate +#define cfgPCIE_LANE_13_EQUALIZATION_CNTL 0x0296 // duplicate +#define cfgPCIE_LANE_14_EQUALIZATION_CNTL 0x0298 // duplicate +#define cfgPCIE_LANE_15_EQUALIZATION_CNTL 0x029a // duplicate +#define cfgPCIE_ACS_ENH_CAP_LIST 0x02a0 // duplicate +#define cfgPCIE_ACS_CAP 0x02a4 // duplicate +#define cfgPCIE_ACS_CNTL 0x02a6 // duplicate +#define cfgPCIE_ATS_ENH_CAP_LIST 0x02b0 // duplicate +#define cfgPCIE_ATS_CAP 0x02b4 // duplicate +#define cfgPCIE_ATS_CNTL 0x02b6 // duplicate +#define cfgPCIE_PAGE_REQ_ENH_CAP_LIST 0x02c0 // duplicate +#define cfgPCIE_PAGE_REQ_CNTL 0x02c4 // duplicate +#define cfgPCIE_PAGE_REQ_STATUS 0x02c6 // duplicate +#define cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x02c8 // duplicate +#define cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC 0x02cc // duplicate +#define cfgPCIE_PASID_ENH_CAP_LIST 0x02d0 // duplicate +#define cfgPCIE_PASID_CAP 0x02d4 // duplicate +#define cfgPCIE_PASID_CNTL 0x02d6 // duplicate +#define cfgPCIE_TPH_REQR_ENH_CAP_LIST 0x02e0 // duplicate +#define cfgPCIE_TPH_REQR_CAP 0x02e4 // duplicate +#define cfgPCIE_TPH_REQR_CNTL 0x02e8 // duplicate +#define cfgPCIE_MC_ENH_CAP_LIST 0x02f0 // duplicate +#define cfgPCIE_MC_CAP 0x02f4 // duplicate +#define cfgPCIE_MC_CNTL 0x02f6 // duplicate +#define cfgPCIE_MC_ADDR0 0x02f8 // duplicate +#define cfgPCIE_MC_ADDR1 0x02fc // duplicate +#define cfgPCIE_MC_RCV0 0x0300 // duplicate +#define cfgPCIE_MC_RCV1 0x0304 // duplicate +#define cfgPCIE_MC_BLOCK_ALL0 0x0308 // duplicate +#define cfgPCIE_MC_BLOCK_ALL1 0x030c // duplicate +#define cfgPCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 // duplicate +#define cfgPCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 // duplicate +#define cfgPCIE_LTR_ENH_CAP_LIST 0x0320 // duplicate +#define cfgPCIE_LTR_CAP 0x0324 // duplicate +#define cfgPCIE_ARI_ENH_CAP_LIST 0x0328 // duplicate +#define cfgPCIE_ARI_CAP 0x032c // duplicate +#define cfgPCIE_ARI_CNTL 0x032e // duplicate +#define cfgPCIE_SRIOV_ENH_CAP_LIST 0x0330 // duplicate +#define cfgPCIE_SRIOV_CAP 0x0334 // duplicate +#define cfgPCIE_SRIOV_CONTROL 0x0338 // duplicate +#define cfgPCIE_SRIOV_STATUS 0x033a // duplicate +#define cfgPCIE_SRIOV_INITIAL_VFS 0x033c // duplicate +#define cfgPCIE_SRIOV_TOTAL_VFS 0x033e // duplicate +#define cfgPCIE_SRIOV_NUM_VFS 0x0340 // duplicate +#define cfgPCIE_SRIOV_FUNC_DEP_LINK 0x0342 // duplicate +#define cfgPCIE_SRIOV_FIRST_VF_OFFSET 0x0344 // duplicate +#define cfgPCIE_SRIOV_VF_STRIDE 0x0346 // duplicate +#define cfgPCIE_SRIOV_VF_DEVICE_ID 0x034a // duplicate +#define cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c // duplicate +#define cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350 // duplicate +#define cfgPCIE_SRIOV_VF_BASE_ADDR_0 0x0354 // duplicate +#define cfgPCIE_SRIOV_VF_BASE_ADDR_1 0x0358 // duplicate +#define cfgPCIE_SRIOV_VF_BASE_ADDR_2 0x035c // duplicate +#define cfgPCIE_SRIOV_VF_BASE_ADDR_3 0x0360 // duplicate +#define cfgPCIE_SRIOV_VF_BASE_ADDR_4 0x0364 // duplicate +#define cfgPCIE_SRIOV_VF_BASE_ADDR_5 0x0368 // duplicate +#define cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x036c // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x0400 // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x0404 // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x0408 // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x040c // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x0410 // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x0414 // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x0418 // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x041c // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x0420 // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x0424 // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x0428 // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x042c // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x0430 // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x0434 // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x0438 // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x043c // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x0440 // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x0444 // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x0448 // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x044c // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x0450 // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x0454 // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x0458 // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x045c // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x0460 // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x0464 // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x0468 // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x046c // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 0x0470 // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 0x0474 // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 0x0478 // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 0x047c // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 0x0480 // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 0x0484 // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 0x0488 // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 0x048c // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 0x0490 // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 0x0494 // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 0x0498 // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 0x049c // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 0x04a0 // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 0x04a4 // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 0x04a8 // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 0x04ac // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 0x04b0 // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 0x04b4 // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 0x04b8 // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 0x04bc // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 0x04c0 // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 0x04c4 // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 0x04c8 // duplicate +#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 0x04cc // duplicate // addressBlock: bif_cfg_dev0_swds_bifcfgdecp // base address: 0x0 -#define mmSUB_BUS_NUMBER_LATENCY 0x0006 // duplicate +#define mmSUB_BUS_NUMBER_LATENCY 0x0006 // duplicate #define mmSUB_BUS_NUMBER_LATENCY_BASE_IDX 0 -#define mmIO_BASE_LIMIT 0x0007 // duplicate +#define mmIO_BASE_LIMIT 0x0007 // duplicate #define mmIO_BASE_LIMIT_BASE_IDX 0 -#define mmSECONDARY_STATUS 0x0007 // duplicate +#define mmSECONDARY_STATUS 0x0007 // duplicate #define mmSECONDARY_STATUS_BASE_IDX 0 -#define mmMEM_BASE_LIMIT 0x0008 // duplicate +#define mmMEM_BASE_LIMIT 0x0008 // duplicate #define mmMEM_BASE_LIMIT_BASE_IDX 0 -#define mmPREF_BASE_LIMIT 0x0009 // duplicate +#define mmPREF_BASE_LIMIT 0x0009 // duplicate #define mmPREF_BASE_LIMIT_BASE_IDX 0 -#define mmPREF_BASE_UPPER 0x000a // duplicate +#define mmPREF_BASE_UPPER 0x000a // duplicate #define mmPREF_BASE_UPPER_BASE_IDX 0 -#define mmPREF_LIMIT_UPPER 0x000b // duplicate +#define mmPREF_LIMIT_UPPER 0x000b // duplicate #define mmPREF_LIMIT_UPPER_BASE_IDX 0 -#define mmIO_BASE_LIMIT_HI 0x000c // duplicate +#define mmIO_BASE_LIMIT_HI 0x000c // duplicate #define mmIO_BASE_LIMIT_HI_BASE_IDX 0 -#define mmIRQ_BRIDGE_CNTL 0x000f // duplicate +#define mmIRQ_BRIDGE_CNTL 0x000f // duplicate #define mmIRQ_BRIDGE_CNTL_BASE_IDX 0 -#define mmSLOT_CAP 0x001b // duplicate +#define mmSLOT_CAP 0x001b // duplicate #define mmSLOT_CAP_BASE_IDX 0 -#define mmSLOT_CNTL 0x001c // duplicate +#define mmSLOT_CNTL 0x001c // duplicate #define mmSLOT_CNTL_BASE_IDX 0 -#define mmSLOT_STATUS 0x001c // duplicate +#define mmSLOT_STATUS 0x001c // duplicate #define mmSLOT_STATUS_BASE_IDX 0 -#define mmSSID_CAP_LIST 0x0030 // duplicate +#define mmSSID_CAP_LIST 0x0030 // duplicate #define mmSSID_CAP_LIST_BASE_IDX 0 -#define mmSSID_CAP 0x0031 // duplicate +#define mmSSID_CAP 0x0031 // duplicate #define mmSSID_CAP_BASE_IDX 0 // addressBlock: rcc_shadow_reg_shadowdec // base address: 0x0 -#define ixSHADOW_COMMAND 0x0004 // duplicate -#define ixSHADOW_BASE_ADDR_1 0x0010 // duplicate -#define ixSHADOW_BASE_ADDR_2 0x0014 // duplicate -#define ixSHADOW_SUB_BUS_NUMBER_LATENCY 0x0018 // duplicate -#define ixSHADOW_IO_BASE_LIMIT 0x001c // duplicate -#define ixSHADOW_MEM_BASE_LIMIT 0x0020 // duplicate -#define ixSHADOW_PREF_BASE_LIMIT 0x0024 // duplicate -#define ixSHADOW_PREF_BASE_UPPER 0x0028 // duplicate -#define ixSHADOW_PREF_LIMIT_UPPER 0x002c // duplicate -#define ixSHADOW_IO_BASE_LIMIT_HI 0x0030 // duplicate -#define ixSHADOW_IRQ_BRIDGE_CNTL 0x003e // duplicate -#define ixSUC_INDEX 0x00e0 // duplicate -#define ixSUC_DATA 0x00e4 // duplicate +#define ixSHADOW_COMMAND 0x0004 // duplicate +#define ixSHADOW_BASE_ADDR_1 0x0010 // duplicate +#define ixSHADOW_BASE_ADDR_2 0x0014 // duplicate +#define ixSHADOW_SUB_BUS_NUMBER_LATENCY 0x0018 // duplicate +#define ixSHADOW_IO_BASE_LIMIT 0x001c // duplicate +#define ixSHADOW_MEM_BASE_LIMIT 0x0020 // duplicate +#define ixSHADOW_PREF_BASE_LIMIT 0x0024 // duplicate +#define ixSHADOW_PREF_BASE_UPPER 0x0028 // duplicate +#define ixSHADOW_PREF_LIMIT_UPPER 0x002c // duplicate +#define ixSHADOW_IO_BASE_LIMIT_HI 0x0030 // duplicate +#define ixSHADOW_IRQ_BRIDGE_CNTL 0x003e // duplicate +#define ixSUC_INDEX 0x00e0 // duplicate +#define ixSUC_DATA 0x00e4 // duplicate // addressBlock: bif_bx_pf_SUMDEC // base address: 0x0 -#define ixSUM_INDEX 0x00e0 // duplicate -#define ixSUM_DATA 0x00e4 // duplicate +#define ixSUM_INDEX 0x00e0 // duplicate +#define ixSUM_DATA 0x00e4 // duplicate // addressBlock: gdc_GDCDEC // base address: 0x1400000 -#define mmA2S_CNTL_CL0 0x4f0ab0 // duplicate +#define mmA2S_CNTL_CL0 0x4f0ab0 // duplicate #define mmA2S_CNTL_CL0_BASE_IDX 3 -#define mmA2S_CNTL_CL1 0x4f0ab1 // duplicate +#define mmA2S_CNTL_CL1 0x4f0ab1 // duplicate #define mmA2S_CNTL_CL1_BASE_IDX 3 -#define mmA2S_CNTL_CL2 0x4f0ab2 // duplicate +#define mmA2S_CNTL_CL2 0x4f0ab2 // duplicate #define mmA2S_CNTL_CL2_BASE_IDX 3 -#define mmA2S_CNTL_CL3 0x4f0ab3 // duplicate +#define mmA2S_CNTL_CL3 0x4f0ab3 // duplicate #define mmA2S_CNTL_CL3_BASE_IDX 3 -#define mmA2S_CNTL_CL4 0x4f0ab4 // duplicate +#define mmA2S_CNTL_CL4 0x4f0ab4 // duplicate #define mmA2S_CNTL_CL4_BASE_IDX 3 -#define mmA2S_CNTL_SW0 0x4f0ad0 // duplicate +#define mmA2S_CNTL_SW0 0x4f0ad0 // duplicate #define mmA2S_CNTL_SW0_BASE_IDX 3 -#define mmA2S_CNTL_SW1 0x4f0ad1 // duplicate +#define mmA2S_CNTL_SW1 0x4f0ad1 // duplicate #define mmA2S_CNTL_SW1_BASE_IDX 3 -#define mmA2S_CNTL_SW2 0x4f0ad2 // duplicate +#define mmA2S_CNTL_SW2 0x4f0ad2 // duplicate #define mmA2S_CNTL_SW2_BASE_IDX 3 -#define mmNGDC_MGCG_CTRL 0x4f0ae0 // duplicate +#define mmNGDC_MGCG_CTRL 0x4f0ae0 // duplicate #define mmNGDC_MGCG_CTRL_BASE_IDX 3 -#define mmA2S_MISC_CNTL 0x4f0ae1 // duplicate +#define mmA2S_MISC_CNTL 0x4f0ae1 // duplicate #define mmA2S_MISC_CNTL_BASE_IDX 3 -#define mmNGDC_SDP_PORT_CTRL 0x4f0ae2 // duplicate +#define mmNGDC_SDP_PORT_CTRL 0x4f0ae2 // duplicate #define mmNGDC_SDP_PORT_CTRL_BASE_IDX 3 -#define mmNGDC_RESERVED_0 0x4f0aeb // duplicate +#define mmNGDC_RESERVED_0 0x4f0aeb // duplicate #define mmNGDC_RESERVED_0_BASE_IDX 3 -#define mmNGDC_RESERVED_1 0x4f0aec // duplicate +#define mmNGDC_RESERVED_1 0x4f0aec // duplicate #define mmNGDC_RESERVED_1_BASE_IDX 3 -#define mmBIF_SDMA0_DOORBELL_RANGE 0x4f0af0 // duplicate +#define mmBIF_SDMA0_DOORBELL_RANGE 0x4f0af0 // duplicate #define mmBIF_SDMA0_DOORBELL_RANGE_BASE_IDX 3 -#define mmBIF_SDMA1_DOORBELL_RANGE 0x4f0af1 // duplicate +#define mmBIF_SDMA1_DOORBELL_RANGE 0x4f0af1 // duplicate #define mmBIF_SDMA1_DOORBELL_RANGE_BASE_IDX 3 -#define mmBIF_IH_DOORBELL_RANGE 0x4f0af2 // duplicate +#define mmBIF_IH_DOORBELL_RANGE 0x4f0af2 // duplicate #define mmBIF_IH_DOORBELL_RANGE_BASE_IDX 3 -#define mmBIF_MMSCH0_DOORBELL_RANGE 0x4f0af3 // duplicate +#define mmBIF_MMSCH0_DOORBELL_RANGE 0x4f0af3 // duplicate #define mmBIF_MMSCH0_DOORBELL_RANGE_BASE_IDX 3 -#define mmBIF_DOORBELL_FENCE_CNTL 0x4f0afe // duplicate +#define mmBIF_DOORBELL_FENCE_CNTL 0x4f0afe // duplicate #define mmBIF_DOORBELL_FENCE_CNTL_BASE_IDX 3 -#define mmS2A_MISC_CNTL 0x4f0aff // duplicate +#define mmS2A_MISC_CNTL 0x4f0aff // duplicate #define mmS2A_MISC_CNTL_BASE_IDX 3 -#define mmA2S_CNTL2_SEC_CL0 0x4f0b00 // duplicate +#define mmA2S_CNTL2_SEC_CL0 0x4f0b00 // duplicate #define mmA2S_CNTL2_SEC_CL0_BASE_IDX 3 -#define mmA2S_CNTL2_SEC_CL1 0x4f0b01 // duplicate +#define mmA2S_CNTL2_SEC_CL1 0x4f0b01 // duplicate #define mmA2S_CNTL2_SEC_CL1_BASE_IDX 3 -#define mmA2S_CNTL2_SEC_CL2 0x4f0b02 // duplicate +#define mmA2S_CNTL2_SEC_CL2 0x4f0b02 // duplicate #define mmA2S_CNTL2_SEC_CL2_BASE_IDX 3 -#define mmA2S_CNTL2_SEC_CL3 0x4f0b03 // duplicate +#define mmA2S_CNTL2_SEC_CL3 0x4f0b03 // duplicate #define mmA2S_CNTL2_SEC_CL3_BASE_IDX 3 -#define mmA2S_CNTL2_SEC_CL4 0x4f0b04 // duplicate +#define mmA2S_CNTL2_SEC_CL4 0x4f0b04 // duplicate #define mmA2S_CNTL2_SEC_CL4_BASE_IDX 3 // addressBlock: nbif_sion_SIONDEC // base address: 0x1400000 -#define ixSION_CL0_RdRsp_BurstTarget_REG0 0x1e000 -#define ixSION_CL0_RdRsp_BurstTarget_REG1 0x1e004 -#define ixSION_CL0_RdRsp_TimeSlot_REG0 0x1e008 -#define ixSION_CL0_RdRsp_TimeSlot_REG1 0x1e00c -#define ixSION_CL0_WrRsp_BurstTarget_REG0 0x1e010 -#define ixSION_CL0_WrRsp_BurstTarget_REG1 0x1e014 -#define ixSION_CL0_WrRsp_TimeSlot_REG0 0x1e018 -#define ixSION_CL0_WrRsp_TimeSlot_REG1 0x1e01c -#define ixSION_CL0_Req_BurstTarget_REG0 0x1e020 -#define ixSION_CL0_Req_BurstTarget_REG1 0x1e024 -#define ixSION_CL0_Req_TimeSlot_REG0 0x1e028 -#define ixSION_CL0_Req_TimeSlot_REG1 0x1e02c -#define ixSION_CL0_ReqPoolCredit_Alloc_REG0 0x1e030 -#define ixSION_CL0_ReqPoolCredit_Alloc_REG1 0x1e034 -#define ixSION_CL0_DataPoolCredit_Alloc_REG0 0x1e038 -#define ixSION_CL0_DataPoolCredit_Alloc_REG1 0x1e03c -#define ixSION_CL0_RdRspPoolCredit_Alloc_REG0 0x1e040 -#define ixSION_CL0_RdRspPoolCredit_Alloc_REG1 0x1e044 -#define ixSION_CL0_WrRspPoolCredit_Alloc_REG0 0x1e048 -#define ixSION_CL0_WrRspPoolCredit_Alloc_REG1 0x1e04c -#define ixSION_CL1_RdRsp_BurstTarget_REG0 0x1e050 -#define ixSION_CL1_RdRsp_BurstTarget_REG1 0x1e054 -#define ixSION_CL1_RdRsp_TimeSlot_REG0 0x1e058 -#define ixSION_CL1_RdRsp_TimeSlot_REG1 0x1e05c -#define ixSION_CL1_WrRsp_BurstTarget_REG0 0x1e060 -#define ixSION_CL1_WrRsp_BurstTarget_REG1 0x1e064 -#define ixSION_CL1_WrRsp_TimeSlot_REG0 0x1e068 -#define ixSION_CL1_WrRsp_TimeSlot_REG1 0x1e06c -#define ixSION_CL1_Req_BurstTarget_REG0 0x1e070 -#define ixSION_CL1_Req_BurstTarget_REG1 0x1e074 -#define ixSION_CL1_Req_TimeSlot_REG0 0x1e078 -#define ixSION_CL1_Req_TimeSlot_REG1 0x1e07c -#define ixSION_CL1_ReqPoolCredit_Alloc_REG0 0x1e080 -#define ixSION_CL1_ReqPoolCredit_Alloc_REG1 0x1e084 -#define ixSION_CL1_DataPoolCredit_Alloc_REG0 0x1e088 -#define ixSION_CL1_DataPoolCredit_Alloc_REG1 0x1e08c -#define ixSION_CL1_RdRspPoolCredit_Alloc_REG0 0x1e090 -#define ixSION_CL1_RdRspPoolCredit_Alloc_REG1 0x1e094 -#define ixSION_CL1_WrRspPoolCredit_Alloc_REG0 0x1e098 -#define ixSION_CL1_WrRspPoolCredit_Alloc_REG1 0x1e09c -#define ixSION_CL2_RdRsp_BurstTarget_REG0 0x1e0a0 -#define ixSION_CL2_RdRsp_BurstTarget_REG1 0x1e0a4 -#define ixSION_CL2_RdRsp_TimeSlot_REG0 0x1e0a8 -#define ixSION_CL2_RdRsp_TimeSlot_REG1 0x1e0ac -#define ixSION_CL2_WrRsp_BurstTarget_REG0 0x1e0b0 -#define ixSION_CL2_WrRsp_BurstTarget_REG1 0x1e0b4 -#define ixSION_CL2_WrRsp_TimeSlot_REG0 0x1e0b8 -#define ixSION_CL2_WrRsp_TimeSlot_REG1 0x1e0bc -#define ixSION_CL2_Req_BurstTarget_REG0 0x1e0c0 -#define ixSION_CL2_Req_BurstTarget_REG1 0x1e0c4 -#define ixSION_CL2_Req_TimeSlot_REG0 0x1e0c8 -#define ixSION_CL2_Req_TimeSlot_REG1 0x1e0cc -#define ixSION_CL2_ReqPoolCredit_Alloc_REG0 0x1e0d0 -#define ixSION_CL2_ReqPoolCredit_Alloc_REG1 0x1e0d4 -#define ixSION_CL2_DataPoolCredit_Alloc_REG0 0x1e0d8 -#define ixSION_CL2_DataPoolCredit_Alloc_REG1 0x1e0dc -#define ixSION_CL2_RdRspPoolCredit_Alloc_REG0 0x1e0e0 -#define ixSION_CL2_RdRspPoolCredit_Alloc_REG1 0x1e0e4 -#define ixSION_CL2_WrRspPoolCredit_Alloc_REG0 0x1e0e8 -#define ixSION_CL2_WrRspPoolCredit_Alloc_REG1 0x1e0ec -#define ixSION_CL3_RdRsp_BurstTarget_REG0 0x1e0f0 -#define ixSION_CL3_RdRsp_BurstTarget_REG1 0x1e0f4 -#define ixSION_CL3_RdRsp_TimeSlot_REG0 0x1e0f8 -#define ixSION_CL3_RdRsp_TimeSlot_REG1 0x1e0fc -#define ixSION_CL3_WrRsp_BurstTarget_REG0 0x1e100 -#define ixSION_CL3_WrRsp_BurstTarget_REG1 0x1e104 -#define ixSION_CL3_WrRsp_TimeSlot_REG0 0x1e108 -#define ixSION_CL3_WrRsp_TimeSlot_REG1 0x1e10c -#define ixSION_CL3_Req_BurstTarget_REG0 0x1e110 -#define ixSION_CL3_Req_BurstTarget_REG1 0x1e114 -#define ixSION_CL3_Req_TimeSlot_REG0 0x1e118 -#define ixSION_CL3_Req_TimeSlot_REG1 0x1e11c -#define ixSION_CL3_ReqPoolCredit_Alloc_REG0 0x1e120 -#define ixSION_CL3_ReqPoolCredit_Alloc_REG1 0x1e124 -#define ixSION_CL3_DataPoolCredit_Alloc_REG0 0x1e128 -#define ixSION_CL3_DataPoolCredit_Alloc_REG1 0x1e12c -#define ixSION_CL3_RdRspPoolCredit_Alloc_REG0 0x1e130 -#define ixSION_CL3_RdRspPoolCredit_Alloc_REG1 0x1e134 -#define ixSION_CL3_WrRspPoolCredit_Alloc_REG0 0x1e138 -#define ixSION_CL3_WrRspPoolCredit_Alloc_REG1 0x1e13c -#define ixSION_CL4_RdRsp_BurstTarget_REG0 0x1e140 -#define ixSION_CL4_RdRsp_BurstTarget_REG1 0x1e144 -#define ixSION_CL4_RdRsp_TimeSlot_REG0 0x1e148 -#define ixSION_CL4_RdRsp_TimeSlot_REG1 0x1e14c -#define ixSION_CL4_WrRsp_BurstTarget_REG0 0x1e150 -#define ixSION_CL4_WrRsp_BurstTarget_REG1 0x1e154 -#define ixSION_CL4_WrRsp_TimeSlot_REG0 0x1e158 -#define ixSION_CL4_WrRsp_TimeSlot_REG1 0x1e15c -#define ixSION_CL4_Req_BurstTarget_REG0 0x1e160 -#define ixSION_CL4_Req_BurstTarget_REG1 0x1e164 -#define ixSION_CL4_Req_TimeSlot_REG0 0x1e168 -#define ixSION_CL4_Req_TimeSlot_REG1 0x1e16c -#define ixSION_CL4_ReqPoolCredit_Alloc_REG0 0x1e170 -#define ixSION_CL4_ReqPoolCredit_Alloc_REG1 0x1e174 -#define ixSION_CL4_DataPoolCredit_Alloc_REG0 0x1e178 -#define ixSION_CL4_DataPoolCredit_Alloc_REG1 0x1e17c -#define ixSION_CL4_RdRspPoolCredit_Alloc_REG0 0x1e180 -#define ixSION_CL4_RdRspPoolCredit_Alloc_REG1 0x1e184 -#define ixSION_CL4_WrRspPoolCredit_Alloc_REG0 0x1e188 -#define ixSION_CL4_WrRspPoolCredit_Alloc_REG1 0x1e18c -#define ixSION_CL5_RdRsp_BurstTarget_REG0 0x1e190 -#define ixSION_CL5_RdRsp_BurstTarget_REG1 0x1e194 -#define ixSION_CL5_RdRsp_TimeSlot_REG0 0x1e198 -#define ixSION_CL5_RdRsp_TimeSlot_REG1 0x1e19c -#define ixSION_CL5_WrRsp_BurstTarget_REG0 0x1e1a0 -#define ixSION_CL5_WrRsp_BurstTarget_REG1 0x1e1a4 -#define ixSION_CL5_WrRsp_TimeSlot_REG0 0x1e1a8 -#define ixSION_CL5_WrRsp_TimeSlot_REG1 0x1e1ac -#define ixSION_CL5_Req_BurstTarget_REG0 0x1e1b0 -#define ixSION_CL5_Req_BurstTarget_REG1 0x1e1b4 -#define ixSION_CL5_Req_TimeSlot_REG0 0x1e1b8 -#define ixSION_CL5_Req_TimeSlot_REG1 0x1e1bc -#define ixSION_CL5_ReqPoolCredit_Alloc_REG0 0x1e1c0 -#define ixSION_CL5_ReqPoolCredit_Alloc_REG1 0x1e1c4 -#define ixSION_CL5_DataPoolCredit_Alloc_REG0 0x1e1c8 -#define ixSION_CL5_DataPoolCredit_Alloc_REG1 0x1e1cc -#define ixSION_CL5_RdRspPoolCredit_Alloc_REG0 0x1e1d0 -#define ixSION_CL5_RdRspPoolCredit_Alloc_REG1 0x1e1d4 -#define ixSION_CL5_WrRspPoolCredit_Alloc_REG0 0x1e1d8 -#define ixSION_CL5_WrRspPoolCredit_Alloc_REG1 0x1e1dc -#define ixSION_CNTL_REG0 0x1e1e0 -#define ixSION_CNTL_REG1 0x1e1e4 +#define ixSION_CL0_RdRsp_BurstTarget_REG0 0x1e000 +#define ixSION_CL0_RdRsp_BurstTarget_REG1 0x1e004 +#define ixSION_CL0_RdRsp_TimeSlot_REG0 0x1e008 +#define ixSION_CL0_RdRsp_TimeSlot_REG1 0x1e00c +#define ixSION_CL0_WrRsp_BurstTarget_REG0 0x1e010 +#define ixSION_CL0_WrRsp_BurstTarget_REG1 0x1e014 +#define ixSION_CL0_WrRsp_TimeSlot_REG0 0x1e018 +#define ixSION_CL0_WrRsp_TimeSlot_REG1 0x1e01c +#define ixSION_CL0_Req_BurstTarget_REG0 0x1e020 +#define ixSION_CL0_Req_BurstTarget_REG1 0x1e024 +#define ixSION_CL0_Req_TimeSlot_REG0 0x1e028 +#define ixSION_CL0_Req_TimeSlot_REG1 0x1e02c +#define ixSION_CL0_ReqPoolCredit_Alloc_REG0 0x1e030 +#define ixSION_CL0_ReqPoolCredit_Alloc_REG1 0x1e034 +#define ixSION_CL0_DataPoolCredit_Alloc_REG0 0x1e038 +#define ixSION_CL0_DataPoolCredit_Alloc_REG1 0x1e03c +#define ixSION_CL0_RdRspPoolCredit_Alloc_REG0 0x1e040 +#define ixSION_CL0_RdRspPoolCredit_Alloc_REG1 0x1e044 +#define ixSION_CL0_WrRspPoolCredit_Alloc_REG0 0x1e048 +#define ixSION_CL0_WrRspPoolCredit_Alloc_REG1 0x1e04c +#define ixSION_CL1_RdRsp_BurstTarget_REG0 0x1e050 +#define ixSION_CL1_RdRsp_BurstTarget_REG1 0x1e054 +#define ixSION_CL1_RdRsp_TimeSlot_REG0 0x1e058 +#define ixSION_CL1_RdRsp_TimeSlot_REG1 0x1e05c +#define ixSION_CL1_WrRsp_BurstTarget_REG0 0x1e060 +#define ixSION_CL1_WrRsp_BurstTarget_REG1 0x1e064 +#define ixSION_CL1_WrRsp_TimeSlot_REG0 0x1e068 +#define ixSION_CL1_WrRsp_TimeSlot_REG1 0x1e06c +#define ixSION_CL1_Req_BurstTarget_REG0 0x1e070 +#define ixSION_CL1_Req_BurstTarget_REG1 0x1e074 +#define ixSION_CL1_Req_TimeSlot_REG0 0x1e078 +#define ixSION_CL1_Req_TimeSlot_REG1 0x1e07c +#define ixSION_CL1_ReqPoolCredit_Alloc_REG0 0x1e080 +#define ixSION_CL1_ReqPoolCredit_Alloc_REG1 0x1e084 +#define ixSION_CL1_DataPoolCredit_Alloc_REG0 0x1e088 +#define ixSION_CL1_DataPoolCredit_Alloc_REG1 0x1e08c +#define ixSION_CL1_RdRspPoolCredit_Alloc_REG0 0x1e090 +#define ixSION_CL1_RdRspPoolCredit_Alloc_REG1 0x1e094 +#define ixSION_CL1_WrRspPoolCredit_Alloc_REG0 0x1e098 +#define ixSION_CL1_WrRspPoolCredit_Alloc_REG1 0x1e09c +#define ixSION_CL2_RdRsp_BurstTarget_REG0 0x1e0a0 +#define ixSION_CL2_RdRsp_BurstTarget_REG1 0x1e0a4 +#define ixSION_CL2_RdRsp_TimeSlot_REG0 0x1e0a8 +#define ixSION_CL2_RdRsp_TimeSlot_REG1 0x1e0ac +#define ixSION_CL2_WrRsp_BurstTarget_REG0 0x1e0b0 +#define ixSION_CL2_WrRsp_BurstTarget_REG1 0x1e0b4 +#define ixSION_CL2_WrRsp_TimeSlot_REG0 0x1e0b8 +#define ixSION_CL2_WrRsp_TimeSlot_REG1 0x1e0bc +#define ixSION_CL2_Req_BurstTarget_REG0 0x1e0c0 +#define ixSION_CL2_Req_BurstTarget_REG1 0x1e0c4 +#define ixSION_CL2_Req_TimeSlot_REG0 0x1e0c8 +#define ixSION_CL2_Req_TimeSlot_REG1 0x1e0cc +#define ixSION_CL2_ReqPoolCredit_Alloc_REG0 0x1e0d0 +#define ixSION_CL2_ReqPoolCredit_Alloc_REG1 0x1e0d4 +#define ixSION_CL2_DataPoolCredit_Alloc_REG0 0x1e0d8 +#define ixSION_CL2_DataPoolCredit_Alloc_REG1 0x1e0dc +#define ixSION_CL2_RdRspPoolCredit_Alloc_REG0 0x1e0e0 +#define ixSION_CL2_RdRspPoolCredit_Alloc_REG1 0x1e0e4 +#define ixSION_CL2_WrRspPoolCredit_Alloc_REG0 0x1e0e8 +#define ixSION_CL2_WrRspPoolCredit_Alloc_REG1 0x1e0ec +#define ixSION_CL3_RdRsp_BurstTarget_REG0 0x1e0f0 +#define ixSION_CL3_RdRsp_BurstTarget_REG1 0x1e0f4 +#define ixSION_CL3_RdRsp_TimeSlot_REG0 0x1e0f8 +#define ixSION_CL3_RdRsp_TimeSlot_REG1 0x1e0fc +#define ixSION_CL3_WrRsp_BurstTarget_REG0 0x1e100 +#define ixSION_CL3_WrRsp_BurstTarget_REG1 0x1e104 +#define ixSION_CL3_WrRsp_TimeSlot_REG0 0x1e108 +#define ixSION_CL3_WrRsp_TimeSlot_REG1 0x1e10c +#define ixSION_CL3_Req_BurstTarget_REG0 0x1e110 +#define ixSION_CL3_Req_BurstTarget_REG1 0x1e114 +#define ixSION_CL3_Req_TimeSlot_REG0 0x1e118 +#define ixSION_CL3_Req_TimeSlot_REG1 0x1e11c +#define ixSION_CL3_ReqPoolCredit_Alloc_REG0 0x1e120 +#define ixSION_CL3_ReqPoolCredit_Alloc_REG1 0x1e124 +#define ixSION_CL3_DataPoolCredit_Alloc_REG0 0x1e128 +#define ixSION_CL3_DataPoolCredit_Alloc_REG1 0x1e12c +#define ixSION_CL3_RdRspPoolCredit_Alloc_REG0 0x1e130 +#define ixSION_CL3_RdRspPoolCredit_Alloc_REG1 0x1e134 +#define ixSION_CL3_WrRspPoolCredit_Alloc_REG0 0x1e138 +#define ixSION_CL3_WrRspPoolCredit_Alloc_REG1 0x1e13c +#define ixSION_CL4_RdRsp_BurstTarget_REG0 0x1e140 +#define ixSION_CL4_RdRsp_BurstTarget_REG1 0x1e144 +#define ixSION_CL4_RdRsp_TimeSlot_REG0 0x1e148 +#define ixSION_CL4_RdRsp_TimeSlot_REG1 0x1e14c +#define ixSION_CL4_WrRsp_BurstTarget_REG0 0x1e150 +#define ixSION_CL4_WrRsp_BurstTarget_REG1 0x1e154 +#define ixSION_CL4_WrRsp_TimeSlot_REG0 0x1e158 +#define ixSION_CL4_WrRsp_TimeSlot_REG1 0x1e15c +#define ixSION_CL4_Req_BurstTarget_REG0 0x1e160 +#define ixSION_CL4_Req_BurstTarget_REG1 0x1e164 +#define ixSION_CL4_Req_TimeSlot_REG0 0x1e168 +#define ixSION_CL4_Req_TimeSlot_REG1 0x1e16c +#define ixSION_CL4_ReqPoolCredit_Alloc_REG0 0x1e170 +#define ixSION_CL4_ReqPoolCredit_Alloc_REG1 0x1e174 +#define ixSION_CL4_DataPoolCredit_Alloc_REG0 0x1e178 +#define ixSION_CL4_DataPoolCredit_Alloc_REG1 0x1e17c +#define ixSION_CL4_RdRspPoolCredit_Alloc_REG0 0x1e180 +#define ixSION_CL4_RdRspPoolCredit_Alloc_REG1 0x1e184 +#define ixSION_CL4_WrRspPoolCredit_Alloc_REG0 0x1e188 +#define ixSION_CL4_WrRspPoolCredit_Alloc_REG1 0x1e18c +#define ixSION_CL5_RdRsp_BurstTarget_REG0 0x1e190 +#define ixSION_CL5_RdRsp_BurstTarget_REG1 0x1e194 +#define ixSION_CL5_RdRsp_TimeSlot_REG0 0x1e198 +#define ixSION_CL5_RdRsp_TimeSlot_REG1 0x1e19c +#define ixSION_CL5_WrRsp_BurstTarget_REG0 0x1e1a0 +#define ixSION_CL5_WrRsp_BurstTarget_REG1 0x1e1a4 +#define ixSION_CL5_WrRsp_TimeSlot_REG0 0x1e1a8 +#define ixSION_CL5_WrRsp_TimeSlot_REG1 0x1e1ac +#define ixSION_CL5_Req_BurstTarget_REG0 0x1e1b0 +#define ixSION_CL5_Req_BurstTarget_REG1 0x1e1b4 +#define ixSION_CL5_Req_TimeSlot_REG0 0x1e1b8 +#define ixSION_CL5_Req_TimeSlot_REG1 0x1e1bc +#define ixSION_CL5_ReqPoolCredit_Alloc_REG0 0x1e1c0 +#define ixSION_CL5_ReqPoolCredit_Alloc_REG1 0x1e1c4 +#define ixSION_CL5_DataPoolCredit_Alloc_REG0 0x1e1c8 +#define ixSION_CL5_DataPoolCredit_Alloc_REG1 0x1e1cc +#define ixSION_CL5_RdRspPoolCredit_Alloc_REG0 0x1e1d0 +#define ixSION_CL5_RdRspPoolCredit_Alloc_REG1 0x1e1d4 +#define ixSION_CL5_WrRspPoolCredit_Alloc_REG0 0x1e1d8 +#define ixSION_CL5_WrRspPoolCredit_Alloc_REG1 0x1e1dc +#define ixSION_CNTL_REG0 0x1e1e0 +#define ixSION_CNTL_REG1 0x1e1e4 // addressBlock: syshub_mmreg_direct_syshubdirect // base address: 0x1400000 -#define ixSYSHUB_DS_CTRL_SOCCLK 0x10000 // duplicate -#define ixSYSHUB_DS_CTRL2_SOCCLK 0x10004 // duplicate -#define ixSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK 0x10008 // duplicate -#define ixSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK 0x1000c // duplicate -#define ixDMA_CLK0_SW0_SYSHUB_QOS_CNTL 0x10010 // duplicate -#define ixDMA_CLK0_SW1_SYSHUB_QOS_CNTL 0x10014 // duplicate -#define ixDMA_CLK0_SW0_CL0_CNTL 0x10018 // duplicate -#define ixDMA_CLK0_SW0_CL1_CNTL 0x1001c // duplicate -#define ixDMA_CLK0_SW0_CL2_CNTL 0x10020 // duplicate -#define ixDMA_CLK0_SW0_CL3_CNTL 0x10024 // duplicate -#define ixDMA_CLK0_SW0_CL4_CNTL 0x10028 // duplicate -#define ixDMA_CLK0_SW0_CL5_CNTL 0x1002c // duplicate -#define ixDMA_CLK0_SW1_CL0_CNTL 0x10030 // duplicate -#define ixDMA_CLK0_SW2_CL0_CNTL 0x10034 // duplicate -#define ixSYSHUB_CG_CNTL 0x10300 // duplicate -#define ixSYSHUB_TRANS_IDLE 0x10308 // duplicate -#define ixSYSHUB_HP_TIMER 0x1030c // duplicate -#define ixSYSHUB_SCRATCH 0x10f00 // duplicate -#define ixSYSHUB_DS_CTRL_SHUBCLK 0x11000 // duplicate -#define ixSYSHUB_DS_CTRL2_SHUBCLK 0x11004 // duplicate -#define ixSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK 0x11008 // duplicate -#define ixSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK 0x1100c // duplicate -#define ixDMA_CLK1_SW0_SYSHUB_QOS_CNTL 0x11010 // duplicate -#define ixDMA_CLK1_SW1_SYSHUB_QOS_CNTL 0x11014 // duplicate -#define ixDMA_CLK1_SW0_CL0_CNTL 0x11018 // duplicate -#define ixDMA_CLK1_SW0_CL1_CNTL 0x1101c // duplicate -#define ixDMA_CLK1_SW0_CL2_CNTL 0x11020 // duplicate -#define ixDMA_CLK1_SW0_CL3_CNTL 0x11024 // duplicate -#define ixDMA_CLK1_SW0_CL4_CNTL 0x11028 // duplicate -#define ixDMA_CLK1_SW1_CL0_CNTL 0x1102c // duplicate -#define ixDMA_CLK1_SW1_CL1_CNTL 0x11030 // duplicate -#define ixDMA_CLK1_SW1_CL2_CNTL 0x11034 // duplicate -#define ixDMA_CLK1_SW1_CL3_CNTL 0x11038 // duplicate -#define ixDMA_CLK1_SW1_CL4_CNTL 0x1103c // duplicate +#define ixSYSHUB_DS_CTRL_SOCCLK 0x10000 // duplicate +#define ixSYSHUB_DS_CTRL2_SOCCLK 0x10004 // duplicate +#define ixSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK 0x10008 // duplicate +#define ixSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK 0x1000c // duplicate +#define ixDMA_CLK0_SW0_SYSHUB_QOS_CNTL 0x10010 // duplicate +#define ixDMA_CLK0_SW1_SYSHUB_QOS_CNTL 0x10014 // duplicate +#define ixDMA_CLK0_SW0_CL0_CNTL 0x10018 // duplicate +#define ixDMA_CLK0_SW0_CL1_CNTL 0x1001c // duplicate +#define ixDMA_CLK0_SW0_CL2_CNTL 0x10020 // duplicate +#define ixDMA_CLK0_SW0_CL3_CNTL 0x10024 // duplicate +#define ixDMA_CLK0_SW0_CL4_CNTL 0x10028 // duplicate +#define ixDMA_CLK0_SW0_CL5_CNTL 0x1002c // duplicate +#define ixDMA_CLK0_SW1_CL0_CNTL 0x10030 // duplicate +#define ixDMA_CLK0_SW2_CL0_CNTL 0x10034 // duplicate +#define ixSYSHUB_CG_CNTL 0x10300 // duplicate +#define ixSYSHUB_TRANS_IDLE 0x10308 // duplicate +#define ixSYSHUB_HP_TIMER 0x1030c // duplicate +#define ixSYSHUB_SCRATCH 0x10f00 // duplicate +#define ixSYSHUB_DS_CTRL_SHUBCLK 0x11000 // duplicate +#define ixSYSHUB_DS_CTRL2_SHUBCLK 0x11004 // duplicate +#define ixSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK 0x11008 // duplicate +#define ixSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK 0x1100c // duplicate +#define ixDMA_CLK1_SW0_SYSHUB_QOS_CNTL 0x11010 // duplicate +#define ixDMA_CLK1_SW1_SYSHUB_QOS_CNTL 0x11014 // duplicate +#define ixDMA_CLK1_SW0_CL0_CNTL 0x11018 // duplicate +#define ixDMA_CLK1_SW0_CL1_CNTL 0x1101c // duplicate +#define ixDMA_CLK1_SW0_CL2_CNTL 0x11020 // duplicate +#define ixDMA_CLK1_SW0_CL3_CNTL 0x11024 // duplicate +#define ixDMA_CLK1_SW0_CL4_CNTL 0x11028 // duplicate +#define ixDMA_CLK1_SW1_CL0_CNTL 0x1102c // duplicate +#define ixDMA_CLK1_SW1_CL1_CNTL 0x11030 // duplicate +#define ixDMA_CLK1_SW1_CL2_CNTL 0x11034 // duplicate +#define ixDMA_CLK1_SW1_CL3_CNTL 0x11038 // duplicate +#define ixDMA_CLK1_SW1_CL4_CNTL 0x1103c // duplicate // addressBlock: gdc_ras_gdc_ras_regblk // base address: 0x1400000 -#define ixGDC_RAS_LEAF0_CTRL 0x1f800 -#define ixGDC_RAS_LEAF1_CTRL 0x1f804 -#define ixGDC_RAS_LEAF2_CTRL 0x1f808 -#define ixGDC_RAS_LEAF3_CTRL 0x1f80c -#define ixGDC_RAS_LEAF4_CTRL 0x1f810 -#define ixGDC_RAS_LEAF5_CTRL 0x1f814 +#define ixGDC_RAS_LEAF0_CTRL 0x1f800 +#define ixGDC_RAS_LEAF1_CTRL 0x1f804 +#define ixGDC_RAS_LEAF2_CTRL 0x1f808 +#define ixGDC_RAS_LEAF3_CTRL 0x1f80c +#define ixGDC_RAS_LEAF4_CTRL 0x1f810 +#define ixGDC_RAS_LEAF5_CTRL 0x1f814 // addressBlock: gdc_rst_GDCRST_DEC // base address: 0x1400000 -#define ixSHUB_PF_FLR_RST 0x1f000 -#define ixSHUB_GFX_DRV_MODE1_RST 0x1f004 -#define ixSHUB_LINK_RESET 0x1f008 -#define ixSHUB_PF0_VF_FLR_RST 0x1f020 -#define ixSHUB_HARD_RST_CTRL 0x1f040 -#define ixSHUB_SOFT_RST_CTRL 0x1f044 -#define ixSHUB_SDP_PORT_RST 0x1f048 +#define ixSHUB_PF_FLR_RST 0x1f000 +#define ixSHUB_GFX_DRV_MODE1_RST 0x1f004 +#define ixSHUB_LINK_RESET 0x1f008 +#define ixSHUB_PF0_VF_FLR_RST 0x1f020 +#define ixSHUB_HARD_RST_CTRL 0x1f040 +#define ixSHUB_SOFT_RST_CTRL 0x1f044 +#define ixSHUB_SDP_PORT_RST 0x1f048 // memoryMap:EP0F0Reg @@ -574,1117 +574,1117 @@ // addressBlock: bif_bx_pf_SYSDEC // base address: 0x0 -#define mmSBIOS_SCRATCH_0 0x0048 // duplicate +#define mmSBIOS_SCRATCH_0 0x0048 // duplicate #define mmSBIOS_SCRATCH_0_BASE_IDX 0 -#define mmSBIOS_SCRATCH_1 0x0049 // duplicate +#define mmSBIOS_SCRATCH_1 0x0049 // duplicate #define mmSBIOS_SCRATCH_1_BASE_IDX 0 -#define mmSBIOS_SCRATCH_2 0x004a // duplicate +#define mmSBIOS_SCRATCH_2 0x004a // duplicate #define mmSBIOS_SCRATCH_2_BASE_IDX 0 -#define mmSBIOS_SCRATCH_3 0x004b // duplicate +#define mmSBIOS_SCRATCH_3 0x004b // duplicate #define mmSBIOS_SCRATCH_3_BASE_IDX 0 -#define mmBIOS_SCRATCH_0 0x004c // duplicate +#define mmBIOS_SCRATCH_0 0x004c // duplicate #define mmBIOS_SCRATCH_0_BASE_IDX 0 -#define mmBIOS_SCRATCH_1 0x004d // duplicate +#define mmBIOS_SCRATCH_1 0x004d // duplicate #define mmBIOS_SCRATCH_1_BASE_IDX 0 -#define mmBIOS_SCRATCH_2 0x004e // duplicate +#define mmBIOS_SCRATCH_2 0x004e // duplicate #define mmBIOS_SCRATCH_2_BASE_IDX 0 -#define mmBIOS_SCRATCH_3 0x004f // duplicate +#define mmBIOS_SCRATCH_3 0x004f // duplicate #define mmBIOS_SCRATCH_3_BASE_IDX 0 -#define mmBIOS_SCRATCH_4 0x0050 // duplicate +#define mmBIOS_SCRATCH_4 0x0050 // duplicate #define mmBIOS_SCRATCH_4_BASE_IDX 0 -#define mmBIOS_SCRATCH_5 0x0051 // duplicate +#define mmBIOS_SCRATCH_5 0x0051 // duplicate #define mmBIOS_SCRATCH_5_BASE_IDX 0 -#define mmBIOS_SCRATCH_6 0x0052 // duplicate +#define mmBIOS_SCRATCH_6 0x0052 // duplicate #define mmBIOS_SCRATCH_6_BASE_IDX 0 -#define mmBIOS_SCRATCH_7 0x0053 // duplicate +#define mmBIOS_SCRATCH_7 0x0053 // duplicate #define mmBIOS_SCRATCH_7_BASE_IDX 0 -#define mmBIOS_SCRATCH_8 0x0054 // duplicate +#define mmBIOS_SCRATCH_8 0x0054 // duplicate #define mmBIOS_SCRATCH_8_BASE_IDX 0 -#define mmBIOS_SCRATCH_9 0x0055 // duplicate +#define mmBIOS_SCRATCH_9 0x0055 // duplicate #define mmBIOS_SCRATCH_9_BASE_IDX 0 -#define mmBIOS_SCRATCH_10 0x0056 // duplicate +#define mmBIOS_SCRATCH_10 0x0056 // duplicate #define mmBIOS_SCRATCH_10_BASE_IDX 0 -#define mmBIOS_SCRATCH_11 0x0057 // duplicate +#define mmBIOS_SCRATCH_11 0x0057 // duplicate #define mmBIOS_SCRATCH_11_BASE_IDX 0 -#define mmBIOS_SCRATCH_12 0x0058 // duplicate +#define mmBIOS_SCRATCH_12 0x0058 // duplicate #define mmBIOS_SCRATCH_12_BASE_IDX 0 -#define mmBIOS_SCRATCH_13 0x0059 // duplicate +#define mmBIOS_SCRATCH_13 0x0059 // duplicate #define mmBIOS_SCRATCH_13_BASE_IDX 0 -#define mmBIOS_SCRATCH_14 0x005a // duplicate +#define mmBIOS_SCRATCH_14 0x005a // duplicate #define mmBIOS_SCRATCH_14_BASE_IDX 0 -#define mmBIOS_SCRATCH_15 0x005b // duplicate +#define mmBIOS_SCRATCH_15 0x005b // duplicate #define mmBIOS_SCRATCH_15_BASE_IDX 0 -#define mmBIF_RLC_INTR_CNTL 0x0060 // duplicate +#define mmBIF_RLC_INTR_CNTL 0x0060 // duplicate #define mmBIF_RLC_INTR_CNTL_BASE_IDX 0 -#define mmBIF_VCE_INTR_CNTL 0x0061 // duplicate +#define mmBIF_VCE_INTR_CNTL 0x0061 // duplicate #define mmBIF_VCE_INTR_CNTL_BASE_IDX 0 -#define mmBIF_UVD_INTR_CNTL 0x0062 // duplicate +#define mmBIF_UVD_INTR_CNTL 0x0062 // duplicate #define mmBIF_UVD_INTR_CNTL_BASE_IDX 0 -#define mmGFX_MMIOREG_CAM_ADDR0 0x0080 // duplicate +#define mmGFX_MMIOREG_CAM_ADDR0 0x0080 // duplicate #define mmGFX_MMIOREG_CAM_ADDR0_BASE_IDX 0 -#define mmGFX_MMIOREG_CAM_REMAP_ADDR0 0x0081 // duplicate +#define mmGFX_MMIOREG_CAM_REMAP_ADDR0 0x0081 // duplicate #define mmGFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX 0 -#define mmGFX_MMIOREG_CAM_ADDR1 0x0082 // duplicate +#define mmGFX_MMIOREG_CAM_ADDR1 0x0082 // duplicate #define mmGFX_MMIOREG_CAM_ADDR1_BASE_IDX 0 -#define mmGFX_MMIOREG_CAM_REMAP_ADDR1 0x0083 // duplicate +#define mmGFX_MMIOREG_CAM_REMAP_ADDR1 0x0083 // duplicate #define mmGFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX 0 -#define mmGFX_MMIOREG_CAM_ADDR2 0x0084 // duplicate +#define mmGFX_MMIOREG_CAM_ADDR2 0x0084 // duplicate #define mmGFX_MMIOREG_CAM_ADDR2_BASE_IDX 0 -#define mmGFX_MMIOREG_CAM_REMAP_ADDR2 0x0085 // duplicate +#define mmGFX_MMIOREG_CAM_REMAP_ADDR2 0x0085 // duplicate #define mmGFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX 0 -#define mmGFX_MMIOREG_CAM_ADDR3 0x0086 // duplicate +#define mmGFX_MMIOREG_CAM_ADDR3 0x0086 // duplicate #define mmGFX_MMIOREG_CAM_ADDR3_BASE_IDX 0 -#define mmGFX_MMIOREG_CAM_REMAP_ADDR3 0x0087 // duplicate +#define mmGFX_MMIOREG_CAM_REMAP_ADDR3 0x0087 // duplicate #define mmGFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX 0 -#define mmGFX_MMIOREG_CAM_ADDR4 0x0088 // duplicate +#define mmGFX_MMIOREG_CAM_ADDR4 0x0088 // duplicate #define mmGFX_MMIOREG_CAM_ADDR4_BASE_IDX 0 -#define mmGFX_MMIOREG_CAM_REMAP_ADDR4 0x0089 // duplicate +#define mmGFX_MMIOREG_CAM_REMAP_ADDR4 0x0089 // duplicate #define mmGFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX 0 -#define mmGFX_MMIOREG_CAM_ADDR5 0x008a // duplicate +#define mmGFX_MMIOREG_CAM_ADDR5 0x008a // duplicate #define mmGFX_MMIOREG_CAM_ADDR5_BASE_IDX 0 -#define mmGFX_MMIOREG_CAM_REMAP_ADDR5 0x008b // duplicate +#define mmGFX_MMIOREG_CAM_REMAP_ADDR5 0x008b // duplicate #define mmGFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX 0 -#define mmGFX_MMIOREG_CAM_ADDR6 0x008c // duplicate +#define mmGFX_MMIOREG_CAM_ADDR6 0x008c // duplicate #define mmGFX_MMIOREG_CAM_ADDR6_BASE_IDX 0 -#define mmGFX_MMIOREG_CAM_REMAP_ADDR6 0x008d // duplicate +#define mmGFX_MMIOREG_CAM_REMAP_ADDR6 0x008d // duplicate #define mmGFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX 0 -#define mmGFX_MMIOREG_CAM_ADDR7 0x008e // duplicate +#define mmGFX_MMIOREG_CAM_ADDR7 0x008e // duplicate #define mmGFX_MMIOREG_CAM_ADDR7_BASE_IDX 0 -#define mmGFX_MMIOREG_CAM_REMAP_ADDR7 0x008f // duplicate +#define mmGFX_MMIOREG_CAM_REMAP_ADDR7 0x008f // duplicate #define mmGFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX 0 -#define mmGFX_MMIOREG_CAM_CNTL 0x0090 // duplicate +#define mmGFX_MMIOREG_CAM_CNTL 0x0090 // duplicate #define mmGFX_MMIOREG_CAM_CNTL_BASE_IDX 0 -#define mmGFX_MMIOREG_CAM_ZERO_CPL 0x0091 // duplicate +#define mmGFX_MMIOREG_CAM_ZERO_CPL 0x0091 // duplicate #define mmGFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX 0 -#define mmGFX_MMIOREG_CAM_ONE_CPL 0x0092 // duplicate +#define mmGFX_MMIOREG_CAM_ONE_CPL 0x0092 // duplicate #define mmGFX_MMIOREG_CAM_ONE_CPL_BASE_IDX 0 -#define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x0093 // duplicate +#define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x0093 // duplicate #define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX 0 // addressBlock: bif_bx_pf_SYSPFVFDEC // base address: 0x0 -#define mmMM_INDEX 0x0000 // duplicate +#define mmMM_INDEX 0x0000 // duplicate #define mmMM_INDEX_BASE_IDX 0 -#define mmMM_DATA 0x0001 // duplicate +#define mmMM_DATA 0x0001 // duplicate #define mmMM_DATA_BASE_IDX 0 -#define mmMM_INDEX_HI 0x0006 // duplicate +#define mmMM_INDEX_HI 0x0006 // duplicate #define mmMM_INDEX_HI_BASE_IDX 0 -#define mmSYSHUB_INDEX_OVLP 0x0008 // duplicate +#define mmSYSHUB_INDEX_OVLP 0x0008 // duplicate #define mmSYSHUB_INDEX_OVLP_BASE_IDX 0 -#define mmSYSHUB_DATA_OVLP 0x0009 // duplicate +#define mmSYSHUB_DATA_OVLP 0x0009 // duplicate #define mmSYSHUB_DATA_OVLP_BASE_IDX 0 -#define mmPCIE_INDEX 0x000c // duplicate +#define mmPCIE_INDEX 0x000c // duplicate #define mmPCIE_INDEX_BASE_IDX 0 -#define mmPCIE_DATA 0x000d // duplicate +#define mmPCIE_DATA 0x000d // duplicate #define mmPCIE_DATA_BASE_IDX 0 -#define mmPCIE_INDEX2 0x000e // duplicate +#define mmPCIE_INDEX2 0x000e // duplicate #define mmPCIE_INDEX2_BASE_IDX 0 -#define mmPCIE_DATA2 0x000f // duplicate +#define mmPCIE_DATA2 0x000f // duplicate #define mmPCIE_DATA2_BASE_IDX 0 // addressBlock: rcc_dwn_BIFDEC1 // base address: 0x0 -#define mmDN_PCIE_RESERVED 0x0d60 // duplicate +#define mmDN_PCIE_RESERVED 0x0d60 // duplicate #define mmDN_PCIE_RESERVED_BASE_IDX 0 -#define mmDN_PCIE_SCRATCH 0x0d61 // duplicate +#define mmDN_PCIE_SCRATCH 0x0d61 // duplicate #define mmDN_PCIE_SCRATCH_BASE_IDX 0 -#define mmDN_PCIE_CNTL 0x0d63 // duplicate +#define mmDN_PCIE_CNTL 0x0d63 // duplicate #define mmDN_PCIE_CNTL_BASE_IDX 0 -#define mmDN_PCIE_CONFIG_CNTL 0x0d64 // duplicate +#define mmDN_PCIE_CONFIG_CNTL 0x0d64 // duplicate #define mmDN_PCIE_CONFIG_CNTL_BASE_IDX 0 -#define mmDN_PCIE_RX_CNTL2 0x0d65 // duplicate +#define mmDN_PCIE_RX_CNTL2 0x0d65 // duplicate #define mmDN_PCIE_RX_CNTL2_BASE_IDX 0 -#define mmDN_PCIE_BUS_CNTL 0x0d66 // duplicate +#define mmDN_PCIE_BUS_CNTL 0x0d66 // duplicate #define mmDN_PCIE_BUS_CNTL_BASE_IDX 0 -#define mmDN_PCIE_CFG_CNTL 0x0d67 // duplicate +#define mmDN_PCIE_CFG_CNTL 0x0d67 // duplicate #define mmDN_PCIE_CFG_CNTL_BASE_IDX 0 -#define mmDN_PCIE_STRAP_F0 0x0d68 // duplicate +#define mmDN_PCIE_STRAP_F0 0x0d68 // duplicate #define mmDN_PCIE_STRAP_F0_BASE_IDX 0 -#define mmDN_PCIE_STRAP_MISC 0x0d69 // duplicate +#define mmDN_PCIE_STRAP_MISC 0x0d69 // duplicate #define mmDN_PCIE_STRAP_MISC_BASE_IDX 0 -#define mmDN_PCIE_STRAP_MISC2 0x0d6a // duplicate +#define mmDN_PCIE_STRAP_MISC2 0x0d6a // duplicate #define mmDN_PCIE_STRAP_MISC2_BASE_IDX 0 // addressBlock: rcc_dwnp_BIFDEC1 // base address: 0x0 -#define mmPCIEP_RESERVED 0x0d6c // duplicate +#define mmPCIEP_RESERVED 0x0d6c // duplicate #define mmPCIEP_RESERVED_BASE_IDX 0 -#define mmPCIEP_SCRATCH 0x0d6d // duplicate +#define mmPCIEP_SCRATCH 0x0d6d // duplicate #define mmPCIEP_SCRATCH_BASE_IDX 0 -#define mmPCIE_ERR_CNTL 0x0d6f // duplicate +#define mmPCIE_ERR_CNTL 0x0d6f // duplicate #define mmPCIE_ERR_CNTL_BASE_IDX 0 -#define mmPCIE_RX_CNTL 0x0d70 // duplicate +#define mmPCIE_RX_CNTL 0x0d70 // duplicate #define mmPCIE_RX_CNTL_BASE_IDX 0 -#define mmPCIE_LC_SPEED_CNTL 0x0d71 // duplicate +#define mmPCIE_LC_SPEED_CNTL 0x0d71 // duplicate #define mmPCIE_LC_SPEED_CNTL_BASE_IDX 0 -#define mmPCIE_LC_CNTL2 0x0d72 // duplicate +#define mmPCIE_LC_CNTL2 0x0d72 // duplicate #define mmPCIE_LC_CNTL2_BASE_IDX 0 -#define mmPCIEP_STRAP_MISC 0x0d73 // duplicate +#define mmPCIEP_STRAP_MISC 0x0d73 // duplicate #define mmPCIEP_STRAP_MISC_BASE_IDX 0 -#define mmLTR_MSG_INFO_FROM_EP 0x0d74 // duplicate +#define mmLTR_MSG_INFO_FROM_EP 0x0d74 // duplicate #define mmLTR_MSG_INFO_FROM_EP_BASE_IDX 0 // addressBlock: rcc_ep_BIFDEC1 // base address: 0x0 -#define mmEP_PCIE_SCRATCH 0x0d43 // duplicate +#define mmEP_PCIE_SCRATCH 0x0d43 // duplicate #define mmEP_PCIE_SCRATCH_BASE_IDX 0 -#define mmEP_PCIE_CNTL 0x0d45 // duplicate +#define mmEP_PCIE_CNTL 0x0d45 // duplicate #define mmEP_PCIE_CNTL_BASE_IDX 0 -#define mmEP_PCIE_INT_CNTL 0x0d46 // duplicate +#define mmEP_PCIE_INT_CNTL 0x0d46 // duplicate #define mmEP_PCIE_INT_CNTL_BASE_IDX 0 -#define mmEP_PCIE_INT_STATUS 0x0d47 // duplicate +#define mmEP_PCIE_INT_STATUS 0x0d47 // duplicate #define mmEP_PCIE_INT_STATUS_BASE_IDX 0 -#define mmEP_PCIE_RX_CNTL2 0x0d48 // duplicate +#define mmEP_PCIE_RX_CNTL2 0x0d48 // duplicate #define mmEP_PCIE_RX_CNTL2_BASE_IDX 0 -#define mmEP_PCIE_BUS_CNTL 0x0d49 // duplicate +#define mmEP_PCIE_BUS_CNTL 0x0d49 // duplicate #define mmEP_PCIE_BUS_CNTL_BASE_IDX 0 -#define mmEP_PCIE_CFG_CNTL 0x0d4a // duplicate +#define mmEP_PCIE_CFG_CNTL 0x0d4a // duplicate #define mmEP_PCIE_CFG_CNTL_BASE_IDX 0 -#define mmEP_PCIE_OBFF_CNTL 0x0d4b // duplicate +#define mmEP_PCIE_OBFF_CNTL 0x0d4b // duplicate #define mmEP_PCIE_OBFF_CNTL_BASE_IDX 0 -#define mmEP_PCIE_TX_LTR_CNTL 0x0d4c // duplicate +#define mmEP_PCIE_TX_LTR_CNTL 0x0d4c // duplicate #define mmEP_PCIE_TX_LTR_CNTL_BASE_IDX 0 -#define mmEP_PCIE_STRAP_MISC 0x0d4f // duplicate +#define mmEP_PCIE_STRAP_MISC 0x0d4f // duplicate #define mmEP_PCIE_STRAP_MISC_BASE_IDX 0 -#define mmEP_PCIE_STRAP_MISC2 0x0d50 // duplicate +#define mmEP_PCIE_STRAP_MISC2 0x0d50 // duplicate #define mmEP_PCIE_STRAP_MISC2_BASE_IDX 0 -#define mmEP_PCIE_STRAP_PI 0x0d51 // duplicate +#define mmEP_PCIE_STRAP_PI 0x0d51 // duplicate #define mmEP_PCIE_STRAP_PI_BASE_IDX 0 -#define mmEP_PCIE_F0_DPA_CAP 0x0d52 // duplicate +#define mmEP_PCIE_F0_DPA_CAP 0x0d52 // duplicate #define mmEP_PCIE_F0_DPA_CAP_BASE_IDX 0 -#define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR 0x0d53 // duplicate +#define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR 0x0d53 // duplicate #define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 0 -#define mmEP_PCIE_F0_DPA_CNTL 0x0d53 // duplicate +#define mmEP_PCIE_F0_DPA_CNTL 0x0d53 // duplicate #define mmEP_PCIE_F0_DPA_CNTL_BASE_IDX 0 -#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x0d53 // duplicate +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x0d53 // duplicate #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 0 -#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x0d54 // duplicate +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x0d54 // duplicate #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 0 -#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x0d54 // duplicate +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x0d54 // duplicate #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 0 -#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x0d54 // duplicate +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x0d54 // duplicate #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 0 -#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x0d54 // duplicate +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x0d54 // duplicate #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 0 -#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x0d55 // duplicate +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x0d55 // duplicate #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 0 -#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x0d55 // duplicate +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x0d55 // duplicate #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 0 -#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x0d55 // duplicate +#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x0d55 // duplicate #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 0 -#define mmEP_PCIE_PME_CONTROL 0x0d55 // duplicate +#define mmEP_PCIE_PME_CONTROL 0x0d55 // duplicate #define mmEP_PCIE_PME_CONTROL_BASE_IDX 0 -#define mmEP_PCIEP_RESERVED 0x0d56 // duplicate +#define mmEP_PCIEP_RESERVED 0x0d56 // duplicate #define mmEP_PCIEP_RESERVED_BASE_IDX 0 -#define mmEP_PCIE_TX_CNTL 0x0d58 // duplicate +#define mmEP_PCIE_TX_CNTL 0x0d58 // duplicate #define mmEP_PCIE_TX_CNTL_BASE_IDX 0 -#define mmEP_PCIE_TX_REQUESTER_ID 0x0d59 // duplicate +#define mmEP_PCIE_TX_REQUESTER_ID 0x0d59 // duplicate #define mmEP_PCIE_TX_REQUESTER_ID_BASE_IDX 0 -#define mmEP_PCIE_ERR_CNTL 0x0d5a // duplicate +#define mmEP_PCIE_ERR_CNTL 0x0d5a // duplicate #define mmEP_PCIE_ERR_CNTL_BASE_IDX 0 -#define mmEP_PCIE_RX_CNTL 0x0d5b // duplicate +#define mmEP_PCIE_RX_CNTL 0x0d5b // duplicate #define mmEP_PCIE_RX_CNTL_BASE_IDX 0 -#define mmEP_PCIE_LC_SPEED_CNTL 0x0d5c // duplicate +#define mmEP_PCIE_LC_SPEED_CNTL 0x0d5c // duplicate #define mmEP_PCIE_LC_SPEED_CNTL_BASE_IDX 0 // addressBlock: bif_bx_pf_BIFDEC1 // base address: 0x0 -#define mmBIF_MM_INDACCESS_CNTL 0x0e06 // duplicate +#define mmBIF_MM_INDACCESS_CNTL 0x0e06 // duplicate #define mmBIF_MM_INDACCESS_CNTL_BASE_IDX 0 -#define mmBUS_CNTL 0x0e07 // duplicate +#define mmBUS_CNTL 0x0e07 // duplicate #define mmBUS_CNTL_BASE_IDX 0 -#define mmBIF_SCRATCH0 0x0e08 // duplicate +#define mmBIF_SCRATCH0 0x0e08 // duplicate #define mmBIF_SCRATCH0_BASE_IDX 0 -#define mmBIF_SCRATCH1 0x0e09 // duplicate +#define mmBIF_SCRATCH1 0x0e09 // duplicate #define mmBIF_SCRATCH1_BASE_IDX 0 -#define mmBX_RESET_EN 0x0e0d // duplicate +#define mmBX_RESET_EN 0x0e0d // duplicate #define mmBX_RESET_EN_BASE_IDX 0 -#define mmMM_CFGREGS_CNTL 0x0e0e // duplicate +#define mmMM_CFGREGS_CNTL 0x0e0e // duplicate #define mmMM_CFGREGS_CNTL_BASE_IDX 0 -#define mmBX_RESET_CNTL 0x0e10 // duplicate +#define mmBX_RESET_CNTL 0x0e10 // duplicate #define mmBX_RESET_CNTL_BASE_IDX 0 -#define mmINTERRUPT_CNTL 0x0e11 // duplicate +#define mmINTERRUPT_CNTL 0x0e11 // duplicate #define mmINTERRUPT_CNTL_BASE_IDX 0 -#define mmINTERRUPT_CNTL2 0x0e12 // duplicate +#define mmINTERRUPT_CNTL2 0x0e12 // duplicate #define mmINTERRUPT_CNTL2_BASE_IDX 0 -#define mmCLKREQB_PAD_CNTL 0x0e18 // duplicate +#define mmCLKREQB_PAD_CNTL 0x0e18 // duplicate #define mmCLKREQB_PAD_CNTL_BASE_IDX 0 -#define mmCLKREQB_PERF_COUNTER 0x0e19 // duplicate +#define mmCLKREQB_PERF_COUNTER 0x0e19 // duplicate #define mmCLKREQB_PERF_COUNTER_BASE_IDX 0 -#define mmBIF_CLK_CTRL 0x0e1a // duplicate +#define mmBIF_CLK_CTRL 0x0e1a // duplicate #define mmBIF_CLK_CTRL_BASE_IDX 0 -#define mmBIF_FEATURES_CONTROL_MISC 0x0e1b // duplicate +#define mmBIF_FEATURES_CONTROL_MISC 0x0e1b // duplicate #define mmBIF_FEATURES_CONTROL_MISC_BASE_IDX 0 -#define mmBIF_DOORBELL_CNTL 0x0e1c // duplicate +#define mmBIF_DOORBELL_CNTL 0x0e1c // duplicate #define mmBIF_DOORBELL_CNTL_BASE_IDX 0 -#define mmBIF_DOORBELL_INT_CNTL 0x0e1d // duplicate +#define mmBIF_DOORBELL_INT_CNTL 0x0e1d // duplicate #define mmBIF_DOORBELL_INT_CNTL_BASE_IDX 0 -#define mmBIF_SLVARB_MODE 0x0e1e // duplicate +#define mmBIF_SLVARB_MODE 0x0e1e // duplicate #define mmBIF_SLVARB_MODE_BASE_IDX 0 -#define mmBIF_FB_EN 0x0e1f // duplicate +#define mmBIF_FB_EN 0x0e1f // duplicate #define mmBIF_FB_EN_BASE_IDX 0 -#define mmBIF_BUSY_DELAY_CNTR 0x0e20 // duplicate +#define mmBIF_BUSY_DELAY_CNTR 0x0e20 // duplicate #define mmBIF_BUSY_DELAY_CNTR_BASE_IDX 0 -#define mmBIF_PERFMON_CNTL 0x0e21 // duplicate +#define mmBIF_PERFMON_CNTL 0x0e21 // duplicate #define mmBIF_PERFMON_CNTL_BASE_IDX 0 -#define mmBIF_PERFCOUNTER0_RESULT 0x0e22 // duplicate +#define mmBIF_PERFCOUNTER0_RESULT 0x0e22 // duplicate #define mmBIF_PERFCOUNTER0_RESULT_BASE_IDX 0 -#define mmBIF_PERFCOUNTER1_RESULT 0x0e23 // duplicate +#define mmBIF_PERFCOUNTER1_RESULT 0x0e23 // duplicate #define mmBIF_PERFCOUNTER1_RESULT_BASE_IDX 0 -#define mmBIF_MST_TRANS_PENDING_VF 0x0e29 // duplicate +#define mmBIF_MST_TRANS_PENDING_VF 0x0e29 // duplicate #define mmBIF_MST_TRANS_PENDING_VF_BASE_IDX 0 -#define mmBIF_SLV_TRANS_PENDING_VF 0x0e2a // duplicate +#define mmBIF_SLV_TRANS_PENDING_VF 0x0e2a // duplicate #define mmBIF_SLV_TRANS_PENDING_VF_BASE_IDX 0 -#define mmBACO_CNTL 0x0e2b // duplicate +#define mmBACO_CNTL 0x0e2b // duplicate #define mmBACO_CNTL_BASE_IDX 0 -#define mmBIF_BACO_EXIT_TIME0 0x0e2c // duplicate +#define mmBIF_BACO_EXIT_TIME0 0x0e2c // duplicate #define mmBIF_BACO_EXIT_TIME0_BASE_IDX 0 -#define mmBIF_BACO_EXIT_TIMER1 0x0e2d // duplicate +#define mmBIF_BACO_EXIT_TIMER1 0x0e2d // duplicate #define mmBIF_BACO_EXIT_TIMER1_BASE_IDX 0 -#define mmBIF_BACO_EXIT_TIMER2 0x0e2e // duplicate +#define mmBIF_BACO_EXIT_TIMER2 0x0e2e // duplicate #define mmBIF_BACO_EXIT_TIMER2_BASE_IDX 0 -#define mmBIF_BACO_EXIT_TIMER3 0x0e2f // duplicate +#define mmBIF_BACO_EXIT_TIMER3 0x0e2f // duplicate #define mmBIF_BACO_EXIT_TIMER3_BASE_IDX 0 -#define mmBIF_BACO_EXIT_TIMER4 0x0e30 // duplicate +#define mmBIF_BACO_EXIT_TIMER4 0x0e30 // duplicate #define mmBIF_BACO_EXIT_TIMER4_BASE_IDX 0 -#define mmMEM_TYPE_CNTL 0x0e31 // duplicate +#define mmMEM_TYPE_CNTL 0x0e31 // duplicate #define mmMEM_TYPE_CNTL_BASE_IDX 0 -#define mmSMU_BIF_VDDGFX_PWR_STATUS 0x0e33 // duplicate +#define mmSMU_BIF_VDDGFX_PWR_STATUS 0x0e33 // duplicate #define mmSMU_BIF_VDDGFX_PWR_STATUS_BASE_IDX 0 -#define mmBIF_VDDGFX_GFX0_LOWER 0x0e34 // duplicate +#define mmBIF_VDDGFX_GFX0_LOWER 0x0e34 // duplicate #define mmBIF_VDDGFX_GFX0_LOWER_BASE_IDX 0 -#define mmBIF_VDDGFX_GFX0_UPPER 0x0e35 // duplicate +#define mmBIF_VDDGFX_GFX0_UPPER 0x0e35 // duplicate #define mmBIF_VDDGFX_GFX0_UPPER_BASE_IDX 0 -#define mmBIF_VDDGFX_GFX1_LOWER 0x0e36 // duplicate +#define mmBIF_VDDGFX_GFX1_LOWER 0x0e36 // duplicate #define mmBIF_VDDGFX_GFX1_LOWER_BASE_IDX 0 -#define mmBIF_VDDGFX_GFX1_UPPER 0x0e37 // duplicate +#define mmBIF_VDDGFX_GFX1_UPPER 0x0e37 // duplicate #define mmBIF_VDDGFX_GFX1_UPPER_BASE_IDX 0 -#define mmBIF_VDDGFX_GFX2_LOWER 0x0e38 // duplicate +#define mmBIF_VDDGFX_GFX2_LOWER 0x0e38 // duplicate #define mmBIF_VDDGFX_GFX2_LOWER_BASE_IDX 0 -#define mmBIF_VDDGFX_GFX2_UPPER 0x0e39 // duplicate +#define mmBIF_VDDGFX_GFX2_UPPER 0x0e39 // duplicate #define mmBIF_VDDGFX_GFX2_UPPER_BASE_IDX 0 -#define mmBIF_VDDGFX_GFX3_LOWER 0x0e3a // duplicate +#define mmBIF_VDDGFX_GFX3_LOWER 0x0e3a // duplicate #define mmBIF_VDDGFX_GFX3_LOWER_BASE_IDX 0 -#define mmBIF_VDDGFX_GFX3_UPPER 0x0e3b // duplicate +#define mmBIF_VDDGFX_GFX3_UPPER 0x0e3b // duplicate #define mmBIF_VDDGFX_GFX3_UPPER_BASE_IDX 0 -#define mmBIF_VDDGFX_GFX4_LOWER 0x0e3c // duplicate +#define mmBIF_VDDGFX_GFX4_LOWER 0x0e3c // duplicate #define mmBIF_VDDGFX_GFX4_LOWER_BASE_IDX 0 -#define mmBIF_VDDGFX_GFX4_UPPER 0x0e3d // duplicate +#define mmBIF_VDDGFX_GFX4_UPPER 0x0e3d // duplicate #define mmBIF_VDDGFX_GFX4_UPPER_BASE_IDX 0 -#define mmBIF_VDDGFX_GFX5_LOWER 0x0e3e // duplicate +#define mmBIF_VDDGFX_GFX5_LOWER 0x0e3e // duplicate #define mmBIF_VDDGFX_GFX5_LOWER_BASE_IDX 0 -#define mmBIF_VDDGFX_GFX5_UPPER 0x0e3f // duplicate +#define mmBIF_VDDGFX_GFX5_UPPER 0x0e3f // duplicate #define mmBIF_VDDGFX_GFX5_UPPER_BASE_IDX 0 -#define mmBIF_VDDGFX_RSV1_LOWER 0x0e40 // duplicate +#define mmBIF_VDDGFX_RSV1_LOWER 0x0e40 // duplicate #define mmBIF_VDDGFX_RSV1_LOWER_BASE_IDX 0 -#define mmBIF_VDDGFX_RSV1_UPPER 0x0e41 // duplicate +#define mmBIF_VDDGFX_RSV1_UPPER 0x0e41 // duplicate #define mmBIF_VDDGFX_RSV1_UPPER_BASE_IDX 0 -#define mmBIF_VDDGFX_RSV2_LOWER 0x0e42 // duplicate +#define mmBIF_VDDGFX_RSV2_LOWER 0x0e42 // duplicate #define mmBIF_VDDGFX_RSV2_LOWER_BASE_IDX 0 -#define mmBIF_VDDGFX_RSV2_UPPER 0x0e43 // duplicate +#define mmBIF_VDDGFX_RSV2_UPPER 0x0e43 // duplicate #define mmBIF_VDDGFX_RSV2_UPPER_BASE_IDX 0 -#define mmBIF_VDDGFX_RSV3_LOWER 0x0e44 // duplicate +#define mmBIF_VDDGFX_RSV3_LOWER 0x0e44 // duplicate #define mmBIF_VDDGFX_RSV3_LOWER_BASE_IDX 0 -#define mmBIF_VDDGFX_RSV3_UPPER 0x0e45 // duplicate +#define mmBIF_VDDGFX_RSV3_UPPER 0x0e45 // duplicate #define mmBIF_VDDGFX_RSV3_UPPER_BASE_IDX 0 -#define mmBIF_VDDGFX_RSV4_LOWER 0x0e46 // duplicate +#define mmBIF_VDDGFX_RSV4_LOWER 0x0e46 // duplicate #define mmBIF_VDDGFX_RSV4_LOWER_BASE_IDX 0 -#define mmBIF_VDDGFX_RSV4_UPPER 0x0e47 // duplicate +#define mmBIF_VDDGFX_RSV4_UPPER 0x0e47 // duplicate #define mmBIF_VDDGFX_RSV4_UPPER_BASE_IDX 0 -#define mmBIF_VDDGFX_FB_CMP 0x0e48 // duplicate +#define mmBIF_VDDGFX_FB_CMP 0x0e48 // duplicate #define mmBIF_VDDGFX_FB_CMP_BASE_IDX 0 -#define mmBIF_DOORBELL_GBLAPER1_LOWER 0x0e49 // duplicate +#define mmBIF_DOORBELL_GBLAPER1_LOWER 0x0e49 // duplicate #define mmBIF_DOORBELL_GBLAPER1_LOWER_BASE_IDX 0 -#define mmBIF_DOORBELL_GBLAPER1_UPPER 0x0e4a // duplicate +#define mmBIF_DOORBELL_GBLAPER1_UPPER 0x0e4a // duplicate #define mmBIF_DOORBELL_GBLAPER1_UPPER_BASE_IDX 0 -#define mmBIF_DOORBELL_GBLAPER2_LOWER 0x0e4b // duplicate +#define mmBIF_DOORBELL_GBLAPER2_LOWER 0x0e4b // duplicate #define mmBIF_DOORBELL_GBLAPER2_LOWER_BASE_IDX 0 -#define mmBIF_DOORBELL_GBLAPER2_UPPER 0x0e4c // duplicate +#define mmBIF_DOORBELL_GBLAPER2_UPPER 0x0e4c // duplicate #define mmBIF_DOORBELL_GBLAPER2_UPPER_BASE_IDX 0 -#define mmREMAP_HDP_MEM_FLUSH_CNTL 0x0e4d // duplicate +#define mmREMAP_HDP_MEM_FLUSH_CNTL 0x0e4d // duplicate #define mmREMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX 0 -#define mmREMAP_HDP_REG_FLUSH_CNTL 0x0e4e // duplicate +#define mmREMAP_HDP_REG_FLUSH_CNTL 0x0e4e // duplicate #define mmREMAP_HDP_REG_FLUSH_CNTL_BASE_IDX 0 -#define mmBIF_RB_CNTL 0x0e4f // duplicate +#define mmBIF_RB_CNTL 0x0e4f // duplicate #define mmBIF_RB_CNTL_BASE_IDX 0 -#define mmBIF_RB_BASE 0x0e50 // duplicate +#define mmBIF_RB_BASE 0x0e50 // duplicate #define mmBIF_RB_BASE_BASE_IDX 0 -#define mmBIF_RB_RPTR 0x0e51 // duplicate +#define mmBIF_RB_RPTR 0x0e51 // duplicate #define mmBIF_RB_RPTR_BASE_IDX 0 -#define mmBIF_RB_WPTR 0x0e52 // duplicate +#define mmBIF_RB_WPTR 0x0e52 // duplicate #define mmBIF_RB_WPTR_BASE_IDX 0 -#define mmBIF_RB_WPTR_ADDR_HI 0x0e53 // duplicate +#define mmBIF_RB_WPTR_ADDR_HI 0x0e53 // duplicate #define mmBIF_RB_WPTR_ADDR_HI_BASE_IDX 0 -#define mmBIF_RB_WPTR_ADDR_LO 0x0e54 // duplicate +#define mmBIF_RB_WPTR_ADDR_LO 0x0e54 // duplicate #define mmBIF_RB_WPTR_ADDR_LO_BASE_IDX 0 -#define mmMAILBOX_INDEX 0x0e55 // duplicate +#define mmMAILBOX_INDEX 0x0e55 // duplicate #define mmMAILBOX_INDEX_BASE_IDX 0 -#define mmBIF_GPUIOV_RESET_NOTIFICATION 0x0e62 // duplicate +#define mmBIF_GPUIOV_RESET_NOTIFICATION 0x0e62 // duplicate #define mmBIF_GPUIOV_RESET_NOTIFICATION_BASE_IDX 0 -#define mmBIF_UVD_GPUIOV_CFG_SIZE 0x0e63 // duplicate +#define mmBIF_UVD_GPUIOV_CFG_SIZE 0x0e63 // duplicate #define mmBIF_UVD_GPUIOV_CFG_SIZE_BASE_IDX 0 -#define mmBIF_VCE_GPUIOV_CFG_SIZE 0x0e64 // duplicate +#define mmBIF_VCE_GPUIOV_CFG_SIZE 0x0e64 // duplicate #define mmBIF_VCE_GPUIOV_CFG_SIZE_BASE_IDX 0 -#define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE 0x0e65 // duplicate +#define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE 0x0e65 // duplicate #define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE_BASE_IDX 0 -#define mmBIF_GMI_WRR_WEIGHT 0x0e66 // duplicate +#define mmBIF_GMI_WRR_WEIGHT 0x0e66 // duplicate #define mmBIF_GMI_WRR_WEIGHT_BASE_IDX 0 -#define mmNBIF_STRAP_WRITE_CTRL 0x0e67 // duplicate +#define mmNBIF_STRAP_WRITE_CTRL 0x0e67 // duplicate #define mmNBIF_STRAP_WRITE_CTRL_BASE_IDX 0 -#define mmBIF_PERSTB_PAD_CNTL 0x0e68 // duplicate +#define mmBIF_PERSTB_PAD_CNTL 0x0e68 // duplicate #define mmBIF_PERSTB_PAD_CNTL_BASE_IDX 0 -#define mmBIF_PX_EN_PAD_CNTL 0x0e69 // duplicate +#define mmBIF_PX_EN_PAD_CNTL 0x0e69 // duplicate #define mmBIF_PX_EN_PAD_CNTL_BASE_IDX 0 -#define mmBIF_REFPADKIN_PAD_CNTL 0x0e6a // duplicate +#define mmBIF_REFPADKIN_PAD_CNTL 0x0e6a // duplicate #define mmBIF_REFPADKIN_PAD_CNTL_BASE_IDX 0 -#define mmBIF_CLKREQB_PAD_CNTL 0x0e6b // duplicate +#define mmBIF_CLKREQB_PAD_CNTL 0x0e6b // duplicate #define mmBIF_CLKREQB_PAD_CNTL_BASE_IDX 0 // addressBlock: rcc_pf_0_BIFDEC1 // base address: 0x0 -#define mmRCC_BACO_CNTL_MISC 0x0da7 // duplicate +#define mmRCC_BACO_CNTL_MISC 0x0da7 // duplicate #define mmRCC_BACO_CNTL_MISC_BASE_IDX 0 -#define mmRCC_RESET_EN 0x0da8 // duplicate +#define mmRCC_RESET_EN 0x0da8 // duplicate #define mmRCC_RESET_EN_BASE_IDX 0 -#define mmRCC_VDM_SUPPORT 0x0da9 // duplicate +#define mmRCC_VDM_SUPPORT 0x0da9 // duplicate #define mmRCC_VDM_SUPPORT_BASE_IDX 0 -#define mmRCC_PEER_REG_RANGE0 0x0dde // duplicate +#define mmRCC_PEER_REG_RANGE0 0x0dde // duplicate #define mmRCC_PEER_REG_RANGE0_BASE_IDX 0 -#define mmRCC_PEER_REG_RANGE1 0x0ddf // duplicate +#define mmRCC_PEER_REG_RANGE1 0x0ddf // duplicate #define mmRCC_PEER_REG_RANGE1_BASE_IDX 0 -#define mmRCC_BUS_CNTL 0x0de1 // duplicate +#define mmRCC_BUS_CNTL 0x0de1 // duplicate #define mmRCC_BUS_CNTL_BASE_IDX 0 -#define mmRCC_CONFIG_CNTL 0x0de2 // duplicate +#define mmRCC_CONFIG_CNTL 0x0de2 // duplicate #define mmRCC_CONFIG_CNTL_BASE_IDX 0 -#define mmRCC_CONFIG_F0_BASE 0x0de6 // duplicate +#define mmRCC_CONFIG_F0_BASE 0x0de6 // duplicate #define mmRCC_CONFIG_F0_BASE_BASE_IDX 0 -#define mmRCC_CONFIG_APER_SIZE 0x0de7 // duplicate +#define mmRCC_CONFIG_APER_SIZE 0x0de7 // duplicate #define mmRCC_CONFIG_APER_SIZE_BASE_IDX 0 -#define mmRCC_CONFIG_REG_APER_SIZE 0x0de8 // duplicate +#define mmRCC_CONFIG_REG_APER_SIZE 0x0de8 // duplicate #define mmRCC_CONFIG_REG_APER_SIZE_BASE_IDX 0 -#define mmRCC_XDMA_LO 0x0de9 // duplicate +#define mmRCC_XDMA_LO 0x0de9 // duplicate #define mmRCC_XDMA_LO_BASE_IDX 0 -#define mmRCC_XDMA_HI 0x0dea // duplicate +#define mmRCC_XDMA_HI 0x0dea // duplicate #define mmRCC_XDMA_HI_BASE_IDX 0 -#define mmRCC_FEATURES_CONTROL_MISC 0x0deb // duplicate +#define mmRCC_FEATURES_CONTROL_MISC 0x0deb // duplicate #define mmRCC_FEATURES_CONTROL_MISC_BASE_IDX 0 -#define mmRCC_BUSNUM_CNTL1 0x0dec // duplicate +#define mmRCC_BUSNUM_CNTL1 0x0dec // duplicate #define mmRCC_BUSNUM_CNTL1_BASE_IDX 0 -#define mmRCC_BUSNUM_LIST0 0x0ded // duplicate +#define mmRCC_BUSNUM_LIST0 0x0ded // duplicate #define mmRCC_BUSNUM_LIST0_BASE_IDX 0 -#define mmRCC_BUSNUM_LIST1 0x0dee // duplicate +#define mmRCC_BUSNUM_LIST1 0x0dee // duplicate #define mmRCC_BUSNUM_LIST1_BASE_IDX 0 -#define mmRCC_BUSNUM_CNTL2 0x0def // duplicate +#define mmRCC_BUSNUM_CNTL2 0x0def // duplicate #define mmRCC_BUSNUM_CNTL2_BASE_IDX 0 -#define mmRCC_CAPTURE_HOST_BUSNUM 0x0df0 // duplicate +#define mmRCC_CAPTURE_HOST_BUSNUM 0x0df0 // duplicate #define mmRCC_CAPTURE_HOST_BUSNUM_BASE_IDX 0 -#define mmRCC_HOST_BUSNUM 0x0df1 // duplicate +#define mmRCC_HOST_BUSNUM 0x0df1 // duplicate #define mmRCC_HOST_BUSNUM_BASE_IDX 0 -#define mmRCC_PEER0_FB_OFFSET_HI 0x0df2 // duplicate +#define mmRCC_PEER0_FB_OFFSET_HI 0x0df2 // duplicate #define mmRCC_PEER0_FB_OFFSET_HI_BASE_IDX 0 -#define mmRCC_PEER0_FB_OFFSET_LO 0x0df3 // duplicate +#define mmRCC_PEER0_FB_OFFSET_LO 0x0df3 // duplicate #define mmRCC_PEER0_FB_OFFSET_LO_BASE_IDX 0 -#define mmRCC_PEER1_FB_OFFSET_HI 0x0df4 // duplicate +#define mmRCC_PEER1_FB_OFFSET_HI 0x0df4 // duplicate #define mmRCC_PEER1_FB_OFFSET_HI_BASE_IDX 0 -#define mmRCC_PEER1_FB_OFFSET_LO 0x0df5 // duplicate +#define mmRCC_PEER1_FB_OFFSET_LO 0x0df5 // duplicate #define mmRCC_PEER1_FB_OFFSET_LO_BASE_IDX 0 -#define mmRCC_PEER2_FB_OFFSET_HI 0x0df6 // duplicate +#define mmRCC_PEER2_FB_OFFSET_HI 0x0df6 // duplicate #define mmRCC_PEER2_FB_OFFSET_HI_BASE_IDX 0 -#define mmRCC_PEER2_FB_OFFSET_LO 0x0df7 // duplicate +#define mmRCC_PEER2_FB_OFFSET_LO 0x0df7 // duplicate #define mmRCC_PEER2_FB_OFFSET_LO_BASE_IDX 0 -#define mmRCC_PEER3_FB_OFFSET_HI 0x0df8 // duplicate +#define mmRCC_PEER3_FB_OFFSET_HI 0x0df8 // duplicate #define mmRCC_PEER3_FB_OFFSET_HI_BASE_IDX 0 -#define mmRCC_PEER3_FB_OFFSET_LO 0x0df9 // duplicate +#define mmRCC_PEER3_FB_OFFSET_LO 0x0df9 // duplicate #define mmRCC_PEER3_FB_OFFSET_LO_BASE_IDX 0 -#define mmRCC_DEVFUNCNUM_LIST0 0x0dfa // duplicate +#define mmRCC_DEVFUNCNUM_LIST0 0x0dfa // duplicate #define mmRCC_DEVFUNCNUM_LIST0_BASE_IDX 0 -#define mmRCC_DEVFUNCNUM_LIST1 0x0dfb // duplicate +#define mmRCC_DEVFUNCNUM_LIST1 0x0dfb // duplicate #define mmRCC_DEVFUNCNUM_LIST1_BASE_IDX 0 -#define mmRCC_DEV0_LINK_CNTL 0x0dfd // duplicate +#define mmRCC_DEV0_LINK_CNTL 0x0dfd // duplicate #define mmRCC_DEV0_LINK_CNTL_BASE_IDX 0 -#define mmRCC_CMN_LINK_CNTL 0x0dfe // duplicate +#define mmRCC_CMN_LINK_CNTL 0x0dfe // duplicate #define mmRCC_CMN_LINK_CNTL_BASE_IDX 0 -#define mmRCC_EP_REQUESTERID_RESTORE 0x0dff // duplicate +#define mmRCC_EP_REQUESTERID_RESTORE 0x0dff // duplicate #define mmRCC_EP_REQUESTERID_RESTORE_BASE_IDX 0 -#define mmRCC_LTR_LSWITCH_CNTL 0x0e00 // duplicate +#define mmRCC_LTR_LSWITCH_CNTL 0x0e00 // duplicate #define mmRCC_LTR_LSWITCH_CNTL_BASE_IDX 0 -#define mmRCC_MH_ARB_CNTL 0x0e01 // duplicate +#define mmRCC_MH_ARB_CNTL 0x0e01 // duplicate #define mmRCC_MH_ARB_CNTL_BASE_IDX 0 // addressBlock: rcc_pf_0_BIFDEC2 // base address: 0x0 -#define mmGFXMSIX_VECT0_ADDR_LO 0x10800 // duplicate +#define mmGFXMSIX_VECT0_ADDR_LO 0x10800 // duplicate #define mmGFXMSIX_VECT0_ADDR_LO_BASE_IDX 0 -#define mmGFXMSIX_VECT0_ADDR_HI 0x10801 // duplicate +#define mmGFXMSIX_VECT0_ADDR_HI 0x10801 // duplicate #define mmGFXMSIX_VECT0_ADDR_HI_BASE_IDX 0 -#define mmGFXMSIX_VECT0_MSG_DATA 0x10802 // duplicate +#define mmGFXMSIX_VECT0_MSG_DATA 0x10802 // duplicate #define mmGFXMSIX_VECT0_MSG_DATA_BASE_IDX 0 -#define mmGFXMSIX_VECT0_CONTROL 0x10803 // duplicate +#define mmGFXMSIX_VECT0_CONTROL 0x10803 // duplicate #define mmGFXMSIX_VECT0_CONTROL_BASE_IDX 0 -#define mmGFXMSIX_VECT1_ADDR_LO 0x10804 // duplicate +#define mmGFXMSIX_VECT1_ADDR_LO 0x10804 // duplicate #define mmGFXMSIX_VECT1_ADDR_LO_BASE_IDX 0 -#define mmGFXMSIX_VECT1_ADDR_HI 0x10805 // duplicate +#define mmGFXMSIX_VECT1_ADDR_HI 0x10805 // duplicate #define mmGFXMSIX_VECT1_ADDR_HI_BASE_IDX 0 -#define mmGFXMSIX_VECT1_MSG_DATA 0x10806 // duplicate +#define mmGFXMSIX_VECT1_MSG_DATA 0x10806 // duplicate #define mmGFXMSIX_VECT1_MSG_DATA_BASE_IDX 0 -#define mmGFXMSIX_VECT1_CONTROL 0x10807 // duplicate +#define mmGFXMSIX_VECT1_CONTROL 0x10807 // duplicate #define mmGFXMSIX_VECT1_CONTROL_BASE_IDX 0 -#define mmGFXMSIX_VECT2_ADDR_LO 0x10808 // duplicate +#define mmGFXMSIX_VECT2_ADDR_LO 0x10808 // duplicate #define mmGFXMSIX_VECT2_ADDR_LO_BASE_IDX 0 -#define mmGFXMSIX_VECT2_ADDR_HI 0x10809 // duplicate +#define mmGFXMSIX_VECT2_ADDR_HI 0x10809 // duplicate #define mmGFXMSIX_VECT2_ADDR_HI_BASE_IDX 0 -#define mmGFXMSIX_VECT2_MSG_DATA 0x1080a // duplicate +#define mmGFXMSIX_VECT2_MSG_DATA 0x1080a // duplicate #define mmGFXMSIX_VECT2_MSG_DATA_BASE_IDX 0 -#define mmGFXMSIX_VECT2_CONTROL 0x1080b // duplicate +#define mmGFXMSIX_VECT2_CONTROL 0x1080b // duplicate #define mmGFXMSIX_VECT2_CONTROL_BASE_IDX 0 -#define mmGFXMSIX_PBA 0x10c00 // duplicate +#define mmGFXMSIX_PBA 0x10c00 // duplicate #define mmGFXMSIX_PBA_BASE_IDX 0 // addressBlock: rcc_strap_BIFDEC1 // base address: 0x0 -#define mmRCC_DEV0_PORT_STRAP0 0x0d27 // duplicate +#define mmRCC_DEV0_PORT_STRAP0 0x0d27 // duplicate #define mmRCC_DEV0_PORT_STRAP0_BASE_IDX 0 -#define mmRCC_DEV0_PORT_STRAP1 0x0d28 // duplicate +#define mmRCC_DEV0_PORT_STRAP1 0x0d28 // duplicate #define mmRCC_DEV0_PORT_STRAP1_BASE_IDX 0 -#define mmRCC_DEV0_PORT_STRAP2 0x0d29 // duplicate +#define mmRCC_DEV0_PORT_STRAP2 0x0d29 // duplicate #define mmRCC_DEV0_PORT_STRAP2_BASE_IDX 0 -#define mmRCC_DEV0_PORT_STRAP3 0x0d2a // duplicate +#define mmRCC_DEV0_PORT_STRAP3 0x0d2a // duplicate #define mmRCC_DEV0_PORT_STRAP3_BASE_IDX 0 -#define mmRCC_DEV0_PORT_STRAP4 0x0d2b // duplicate +#define mmRCC_DEV0_PORT_STRAP4 0x0d2b // duplicate #define mmRCC_DEV0_PORT_STRAP4_BASE_IDX 0 -#define mmRCC_DEV0_PORT_STRAP5 0x0d2c // duplicate +#define mmRCC_DEV0_PORT_STRAP5 0x0d2c // duplicate #define mmRCC_DEV0_PORT_STRAP5_BASE_IDX 0 -#define mmRCC_DEV0_PORT_STRAP6 0x0d2d // duplicate +#define mmRCC_DEV0_PORT_STRAP6 0x0d2d // duplicate #define mmRCC_DEV0_PORT_STRAP6_BASE_IDX 0 -#define mmRCC_DEV0_PORT_STRAP7 0x0d2e // duplicate +#define mmRCC_DEV0_PORT_STRAP7 0x0d2e // duplicate #define mmRCC_DEV0_PORT_STRAP7_BASE_IDX 0 -#define mmRCC_DEV0_EPF0_STRAP0 0x0d2f // duplicate +#define mmRCC_DEV0_EPF0_STRAP0 0x0d2f // duplicate #define mmRCC_DEV0_EPF0_STRAP0_BASE_IDX 0 -#define mmRCC_DEV0_EPF0_STRAP1 0x0d30 // duplicate +#define mmRCC_DEV0_EPF0_STRAP1 0x0d30 // duplicate #define mmRCC_DEV0_EPF0_STRAP1_BASE_IDX 0 -#define mmRCC_DEV0_EPF0_STRAP13 0x0d31 // duplicate +#define mmRCC_DEV0_EPF0_STRAP13 0x0d31 // duplicate #define mmRCC_DEV0_EPF0_STRAP13_BASE_IDX 0 -#define mmRCC_DEV0_EPF0_STRAP2 0x0d32 // duplicate +#define mmRCC_DEV0_EPF0_STRAP2 0x0d32 // duplicate #define mmRCC_DEV0_EPF0_STRAP2_BASE_IDX 0 -#define mmRCC_DEV0_EPF0_STRAP3 0x0d33 // duplicate +#define mmRCC_DEV0_EPF0_STRAP3 0x0d33 // duplicate #define mmRCC_DEV0_EPF0_STRAP3_BASE_IDX 0 -#define mmRCC_DEV0_EPF0_STRAP4 0x0d34 // duplicate +#define mmRCC_DEV0_EPF0_STRAP4 0x0d34 // duplicate #define mmRCC_DEV0_EPF0_STRAP4_BASE_IDX 0 -#define mmRCC_DEV0_EPF0_STRAP5 0x0d35 // duplicate +#define mmRCC_DEV0_EPF0_STRAP5 0x0d35 // duplicate #define mmRCC_DEV0_EPF0_STRAP5_BASE_IDX 0 -#define mmRCC_DEV0_EPF0_STRAP8 0x0d36 // duplicate +#define mmRCC_DEV0_EPF0_STRAP8 0x0d36 // duplicate #define mmRCC_DEV0_EPF0_STRAP8_BASE_IDX 0 -#define mmRCC_DEV0_EPF0_STRAP9 0x0d37 // duplicate +#define mmRCC_DEV0_EPF0_STRAP9 0x0d37 // duplicate #define mmRCC_DEV0_EPF0_STRAP9_BASE_IDX 0 -#define mmRCC_DEV0_EPF1_STRAP0 0x0d38 // duplicate +#define mmRCC_DEV0_EPF1_STRAP0 0x0d38 // duplicate #define mmRCC_DEV0_EPF1_STRAP0_BASE_IDX 0 -#define mmRCC_DEV0_EPF1_STRAP10 0x0d39 // duplicate +#define mmRCC_DEV0_EPF1_STRAP10 0x0d39 // duplicate #define mmRCC_DEV0_EPF1_STRAP10_BASE_IDX 0 -#define mmRCC_DEV0_EPF1_STRAP11 0x0d3a // duplicate +#define mmRCC_DEV0_EPF1_STRAP11 0x0d3a // duplicate #define mmRCC_DEV0_EPF1_STRAP11_BASE_IDX 0 -#define mmRCC_DEV0_EPF1_STRAP12 0x0d3b // duplicate +#define mmRCC_DEV0_EPF1_STRAP12 0x0d3b // duplicate #define mmRCC_DEV0_EPF1_STRAP12_BASE_IDX 0 -#define mmRCC_DEV0_EPF1_STRAP13 0x0d3c // duplicate +#define mmRCC_DEV0_EPF1_STRAP13 0x0d3c // duplicate #define mmRCC_DEV0_EPF1_STRAP13_BASE_IDX 0 -#define mmRCC_DEV0_EPF1_STRAP2 0x0d3d // duplicate +#define mmRCC_DEV0_EPF1_STRAP2 0x0d3d // duplicate #define mmRCC_DEV0_EPF1_STRAP2_BASE_IDX 0 -#define mmRCC_DEV0_EPF1_STRAP3 0x0d3e // duplicate +#define mmRCC_DEV0_EPF1_STRAP3 0x0d3e // duplicate #define mmRCC_DEV0_EPF1_STRAP3_BASE_IDX 0 -#define mmRCC_DEV0_EPF1_STRAP4 0x0d3f // duplicate +#define mmRCC_DEV0_EPF1_STRAP4 0x0d3f // duplicate #define mmRCC_DEV0_EPF1_STRAP4_BASE_IDX 0 -#define mmRCC_DEV0_EPF1_STRAP5 0x0d40 // duplicate +#define mmRCC_DEV0_EPF1_STRAP5 0x0d40 // duplicate #define mmRCC_DEV0_EPF1_STRAP5_BASE_IDX 0 -#define mmRCC_DEV0_EPF1_STRAP6 0x0d41 // duplicate +#define mmRCC_DEV0_EPF1_STRAP6 0x0d41 // duplicate #define mmRCC_DEV0_EPF1_STRAP6_BASE_IDX 0 -#define mmRCC_DEV0_EPF1_STRAP7 0x0d42 // duplicate +#define mmRCC_DEV0_EPF1_STRAP7 0x0d42 // duplicate #define mmRCC_DEV0_EPF1_STRAP7_BASE_IDX 0 // addressBlock: bif_bx_pf_BIFPFVFDEC1 // base address: 0x0 -#define mmBIF_BME_STATUS 0x0e0b // duplicate +#define mmBIF_BME_STATUS 0x0e0b // duplicate #define mmBIF_BME_STATUS_BASE_IDX 0 -#define mmBIF_ATOMIC_ERR_LOG 0x0e0c // duplicate +#define mmBIF_ATOMIC_ERR_LOG 0x0e0c // duplicate #define mmBIF_ATOMIC_ERR_LOG_BASE_IDX 0 -#define mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x0e13 // duplicate +#define mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x0e13 // duplicate #define mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 0 -#define mmDOORBELL_SELFRING_GPA_APER_BASE_LOW 0x0e14 // duplicate +#define mmDOORBELL_SELFRING_GPA_APER_BASE_LOW 0x0e14 // duplicate #define mmDOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 0 -#define mmDOORBELL_SELFRING_GPA_APER_CNTL 0x0e15 // duplicate +#define mmDOORBELL_SELFRING_GPA_APER_CNTL 0x0e15 // duplicate #define mmDOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 0 -#define mmHDP_REG_COHERENCY_FLUSH_CNTL 0x0e16 // duplicate +#define mmHDP_REG_COHERENCY_FLUSH_CNTL 0x0e16 // duplicate #define mmHDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 0 -#define mmHDP_MEM_COHERENCY_FLUSH_CNTL 0x0e17 // duplicate +#define mmHDP_MEM_COHERENCY_FLUSH_CNTL 0x0e17 // duplicate #define mmHDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 0 -#define mmGPU_HDP_FLUSH_REQ 0x0e26 // duplicate +#define mmGPU_HDP_FLUSH_REQ 0x0e26 // duplicate #define mmGPU_HDP_FLUSH_REQ_BASE_IDX 0 -#define mmGPU_HDP_FLUSH_DONE 0x0e27 // duplicate +#define mmGPU_HDP_FLUSH_DONE 0x0e27 // duplicate #define mmGPU_HDP_FLUSH_DONE_BASE_IDX 0 -#define mmBIF_TRANS_PENDING 0x0e28 // duplicate +#define mmBIF_TRANS_PENDING 0x0e28 // duplicate #define mmBIF_TRANS_PENDING_BASE_IDX 0 -#define mmMAILBOX_MSGBUF_TRN_DW0 0x0e56 // duplicate +#define mmMAILBOX_MSGBUF_TRN_DW0 0x0e56 // duplicate #define mmMAILBOX_MSGBUF_TRN_DW0_BASE_IDX 0 -#define mmMAILBOX_MSGBUF_TRN_DW1 0x0e57 // duplicate +#define mmMAILBOX_MSGBUF_TRN_DW1 0x0e57 // duplicate #define mmMAILBOX_MSGBUF_TRN_DW1_BASE_IDX 0 -#define mmMAILBOX_MSGBUF_TRN_DW2 0x0e58 // duplicate +#define mmMAILBOX_MSGBUF_TRN_DW2 0x0e58 // duplicate #define mmMAILBOX_MSGBUF_TRN_DW2_BASE_IDX 0 -#define mmMAILBOX_MSGBUF_TRN_DW3 0x0e59 // duplicate +#define mmMAILBOX_MSGBUF_TRN_DW3 0x0e59 // duplicate #define mmMAILBOX_MSGBUF_TRN_DW3_BASE_IDX 0 -#define mmMAILBOX_MSGBUF_RCV_DW0 0x0e5a // duplicate +#define mmMAILBOX_MSGBUF_RCV_DW0 0x0e5a // duplicate #define mmMAILBOX_MSGBUF_RCV_DW0_BASE_IDX 0 -#define mmMAILBOX_MSGBUF_RCV_DW1 0x0e5b // duplicate +#define mmMAILBOX_MSGBUF_RCV_DW1 0x0e5b // duplicate #define mmMAILBOX_MSGBUF_RCV_DW1_BASE_IDX 0 -#define mmMAILBOX_MSGBUF_RCV_DW2 0x0e5c // duplicate +#define mmMAILBOX_MSGBUF_RCV_DW2 0x0e5c // duplicate #define mmMAILBOX_MSGBUF_RCV_DW2_BASE_IDX 0 -#define mmMAILBOX_MSGBUF_RCV_DW3 0x0e5d // duplicate +#define mmMAILBOX_MSGBUF_RCV_DW3 0x0e5d // duplicate #define mmMAILBOX_MSGBUF_RCV_DW3_BASE_IDX 0 -#define mmMAILBOX_CONTROL 0x0e5e // duplicate +#define mmMAILBOX_CONTROL 0x0e5e // duplicate #define mmMAILBOX_CONTROL_BASE_IDX 0 -#define mmMAILBOX_INT_CNTL 0x0e5f // duplicate +#define mmMAILBOX_INT_CNTL 0x0e5f // duplicate #define mmMAILBOX_INT_CNTL_BASE_IDX 0 -#define mmBIF_VMHV_MAILBOX 0x0e60 // duplicate +#define mmBIF_VMHV_MAILBOX 0x0e60 // duplicate #define mmBIF_VMHV_MAILBOX_BASE_IDX 0 // addressBlock: rcc_pf_0_BIFPFVFDEC1 // base address: 0x0 -#define mmRCC_DOORBELL_APER_EN 0x0de0 // duplicate +#define mmRCC_DOORBELL_APER_EN 0x0de0 // duplicate #define mmRCC_DOORBELL_APER_EN_BASE_IDX 0 -#define mmRCC_CONFIG_MEMSIZE 0x0de3 // duplicate +#define mmRCC_CONFIG_MEMSIZE 0x0de3 // duplicate #define mmRCC_CONFIG_MEMSIZE_BASE_IDX 0 -#define mmRCC_CONFIG_RESERVED 0x0de4 // duplicate +#define mmRCC_CONFIG_RESERVED 0x0de4 // duplicate #define mmRCC_CONFIG_RESERVED_BASE_IDX 0 #ifndef mmRCC_IOV_FUNC_IDENTIFIER -#define mmRCC_IOV_FUNC_IDENTIFIER 0x0de5 // duplicate +#define mmRCC_IOV_FUNC_IDENTIFIER 0x0de5 // duplicate #define mmRCC_IOV_FUNC_IDENTIFIER_BASE_IDX 0 #endif // addressBlock: syshub_mmreg_ind_syshubdec // base address: 0x0 -#define mmSYSHUB_INDEX 0x0008 +#define mmSYSHUB_INDEX 0x0008 #define mmSYSHUB_INDEX_BASE_IDX 0 -#define mmSYSHUB_DATA 0x0009 +#define mmSYSHUB_DATA 0x0009 #define mmSYSHUB_DATA_BASE_IDX 0 // addressBlock: rcc_strap_rcc_strap_internal // base address: 0x10100000 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0 0x403c000 // duplicate +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0 0x403c000 // duplicate #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0_BASE_IDX 3 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1 0x403c001 // duplicate +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1 0x403c001 // duplicate #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1_BASE_IDX 3 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2 0x403c002 // duplicate +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2 0x403c002 // duplicate #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2_BASE_IDX 3 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3 0x403c003 // duplicate +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3 0x403c003 // duplicate #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3_BASE_IDX 3 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4 0x403c004 // duplicate +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4 0x403c004 // duplicate #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4_BASE_IDX 3 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5 0x403c005 // duplicate +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5 0x403c005 // duplicate #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5_BASE_IDX 3 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6 0x403c006 // duplicate +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6 0x403c006 // duplicate #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6_BASE_IDX 3 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7 0x403c007 // duplicate +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7 0x403c007 // duplicate #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7_BASE_IDX 3 -#define mmRCC_DEV1_PORT_STRAP0 0x403c080 +#define mmRCC_DEV1_PORT_STRAP0 0x403c080 #define mmRCC_DEV1_PORT_STRAP0_BASE_IDX 3 -#define mmRCC_DEV1_PORT_STRAP1 0x403c081 +#define mmRCC_DEV1_PORT_STRAP1 0x403c081 #define mmRCC_DEV1_PORT_STRAP1_BASE_IDX 3 -#define mmRCC_DEV1_PORT_STRAP2 0x403c082 +#define mmRCC_DEV1_PORT_STRAP2 0x403c082 #define mmRCC_DEV1_PORT_STRAP2_BASE_IDX 3 -#define mmRCC_DEV1_PORT_STRAP3 0x403c083 +#define mmRCC_DEV1_PORT_STRAP3 0x403c083 #define mmRCC_DEV1_PORT_STRAP3_BASE_IDX 3 -#define mmRCC_DEV1_PORT_STRAP4 0x403c084 +#define mmRCC_DEV1_PORT_STRAP4 0x403c084 #define mmRCC_DEV1_PORT_STRAP4_BASE_IDX 3 -#define mmRCC_DEV1_PORT_STRAP5 0x403c085 +#define mmRCC_DEV1_PORT_STRAP5 0x403c085 #define mmRCC_DEV1_PORT_STRAP5_BASE_IDX 3 -#define mmRCC_DEV1_PORT_STRAP6 0x403c086 +#define mmRCC_DEV1_PORT_STRAP6 0x403c086 #define mmRCC_DEV1_PORT_STRAP6_BASE_IDX 3 -#define mmRCC_DEV1_PORT_STRAP7 0x403c087 +#define mmRCC_DEV1_PORT_STRAP7 0x403c087 #define mmRCC_DEV1_PORT_STRAP7_BASE_IDX 3 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0 0x403cc00 // duplicate +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0 0x403cc00 // duplicate #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0_BASE_IDX 3 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1 0x403cc01 // duplicate +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1 0x403cc01 // duplicate #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1_BASE_IDX 3 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2 0x403cc02 // duplicate +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2 0x403cc02 // duplicate #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2_BASE_IDX 3 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3 0x403cc03 // duplicate +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3 0x403cc03 // duplicate #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3_BASE_IDX 3 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4 0x403cc04 // duplicate +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4 0x403cc04 // duplicate #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4_BASE_IDX 3 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5 0x403cc05 // duplicate +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5 0x403cc05 // duplicate #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5_BASE_IDX 3 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8 0x403cc08 // duplicate +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8 0x403cc08 // duplicate #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8_BASE_IDX 3 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP9 0x403cc09 // duplicate +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP9 0x403cc09 // duplicate #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP9_BASE_IDX 3 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13 0x403cc0d // duplicate +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13 0x403cc0d // duplicate #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13_BASE_IDX 3 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0 0x403cc80 // duplicate +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0 0x403cc80 // duplicate #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0_BASE_IDX 3 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2 0x403cc82 // duplicate +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2 0x403cc82 // duplicate #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2_BASE_IDX 3 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3 0x403cc83 // duplicate +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3 0x403cc83 // duplicate #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3_BASE_IDX 3 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4 0x403cc84 // duplicate +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4 0x403cc84 // duplicate #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4_BASE_IDX 3 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5 0x403cc85 // duplicate +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5 0x403cc85 // duplicate #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5_BASE_IDX 3 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6 0x403cc86 // duplicate +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6 0x403cc86 // duplicate #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6_BASE_IDX 3 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7 0x403cc87 // duplicate +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7 0x403cc87 // duplicate #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7_BASE_IDX 3 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10 0x403cc8a // duplicate +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10 0x403cc8a // duplicate #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10_BASE_IDX 3 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11 0x403cc8b // duplicate +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11 0x403cc8b // duplicate #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11_BASE_IDX 3 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12 0x403cc8c // duplicate +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12 0x403cc8c // duplicate #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12_BASE_IDX 3 -#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13 0x403cc8d // duplicate +#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13 0x403cc8d // duplicate #define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13_BASE_IDX 3 -#define mmRCC_DEV0_EPF2_STRAP0 0x403cd00 +#define mmRCC_DEV0_EPF2_STRAP0 0x403cd00 #define mmRCC_DEV0_EPF2_STRAP0_BASE_IDX 3 -#define mmRCC_DEV0_EPF2_STRAP2 0x403cd02 +#define mmRCC_DEV0_EPF2_STRAP2 0x403cd02 #define mmRCC_DEV0_EPF2_STRAP2_BASE_IDX 3 -#define mmRCC_DEV0_EPF2_STRAP3 0x403cd03 +#define mmRCC_DEV0_EPF2_STRAP3 0x403cd03 #define mmRCC_DEV0_EPF2_STRAP3_BASE_IDX 3 -#define mmRCC_DEV0_EPF2_STRAP4 0x403cd04 +#define mmRCC_DEV0_EPF2_STRAP4 0x403cd04 #define mmRCC_DEV0_EPF2_STRAP4_BASE_IDX 3 -#define mmRCC_DEV0_EPF2_STRAP5 0x403cd05 +#define mmRCC_DEV0_EPF2_STRAP5 0x403cd05 #define mmRCC_DEV0_EPF2_STRAP5_BASE_IDX 3 -#define mmRCC_DEV0_EPF2_STRAP6 0x403cd06 +#define mmRCC_DEV0_EPF2_STRAP6 0x403cd06 #define mmRCC_DEV0_EPF2_STRAP6_BASE_IDX 3 -#define mmRCC_DEV0_EPF2_STRAP13 0x403cd0d +#define mmRCC_DEV0_EPF2_STRAP13 0x403cd0d #define mmRCC_DEV0_EPF2_STRAP13_BASE_IDX 3 -#define mmRCC_DEV0_EPF3_STRAP0 0x403cd80 +#define mmRCC_DEV0_EPF3_STRAP0 0x403cd80 #define mmRCC_DEV0_EPF3_STRAP0_BASE_IDX 3 -#define mmRCC_DEV0_EPF3_STRAP2 0x403cd82 +#define mmRCC_DEV0_EPF3_STRAP2 0x403cd82 #define mmRCC_DEV0_EPF3_STRAP2_BASE_IDX 3 -#define mmRCC_DEV0_EPF3_STRAP3 0x403cd83 +#define mmRCC_DEV0_EPF3_STRAP3 0x403cd83 #define mmRCC_DEV0_EPF3_STRAP3_BASE_IDX 3 -#define mmRCC_DEV0_EPF3_STRAP4 0x403cd84 +#define mmRCC_DEV0_EPF3_STRAP4 0x403cd84 #define mmRCC_DEV0_EPF3_STRAP4_BASE_IDX 3 -#define mmRCC_DEV0_EPF3_STRAP5 0x403cd85 +#define mmRCC_DEV0_EPF3_STRAP5 0x403cd85 #define mmRCC_DEV0_EPF3_STRAP5_BASE_IDX 3 -#define mmRCC_DEV0_EPF3_STRAP6 0x403cd86 +#define mmRCC_DEV0_EPF3_STRAP6 0x403cd86 #define mmRCC_DEV0_EPF3_STRAP6_BASE_IDX 3 -#define mmRCC_DEV0_EPF3_STRAP13 0x403cd8d +#define mmRCC_DEV0_EPF3_STRAP13 0x403cd8d #define mmRCC_DEV0_EPF3_STRAP13_BASE_IDX 3 -#define mmRCC_DEV0_EPF4_STRAP0 0x403ce00 +#define mmRCC_DEV0_EPF4_STRAP0 0x403ce00 #define mmRCC_DEV0_EPF4_STRAP0_BASE_IDX 3 -#define mmRCC_DEV0_EPF4_STRAP2 0x403ce02 +#define mmRCC_DEV0_EPF4_STRAP2 0x403ce02 #define mmRCC_DEV0_EPF4_STRAP2_BASE_IDX 3 -#define mmRCC_DEV0_EPF4_STRAP3 0x403ce03 +#define mmRCC_DEV0_EPF4_STRAP3 0x403ce03 #define mmRCC_DEV0_EPF4_STRAP3_BASE_IDX 3 -#define mmRCC_DEV0_EPF4_STRAP4 0x403ce04 +#define mmRCC_DEV0_EPF4_STRAP4 0x403ce04 #define mmRCC_DEV0_EPF4_STRAP4_BASE_IDX 3 -#define mmRCC_DEV0_EPF4_STRAP5 0x403ce05 +#define mmRCC_DEV0_EPF4_STRAP5 0x403ce05 #define mmRCC_DEV0_EPF4_STRAP5_BASE_IDX 3 -#define mmRCC_DEV0_EPF4_STRAP6 0x403ce06 +#define mmRCC_DEV0_EPF4_STRAP6 0x403ce06 #define mmRCC_DEV0_EPF4_STRAP6_BASE_IDX 3 -#define mmRCC_DEV0_EPF4_STRAP13 0x403ce0d +#define mmRCC_DEV0_EPF4_STRAP13 0x403ce0d #define mmRCC_DEV0_EPF4_STRAP13_BASE_IDX 3 -#define mmRCC_DEV0_EPF5_STRAP0 0x403ce80 +#define mmRCC_DEV0_EPF5_STRAP0 0x403ce80 #define mmRCC_DEV0_EPF5_STRAP0_BASE_IDX 3 -#define mmRCC_DEV0_EPF5_STRAP2 0x403ce82 +#define mmRCC_DEV0_EPF5_STRAP2 0x403ce82 #define mmRCC_DEV0_EPF5_STRAP2_BASE_IDX 3 -#define mmRCC_DEV0_EPF5_STRAP3 0x403ce83 +#define mmRCC_DEV0_EPF5_STRAP3 0x403ce83 #define mmRCC_DEV0_EPF5_STRAP3_BASE_IDX 3 -#define mmRCC_DEV0_EPF5_STRAP4 0x403ce84 +#define mmRCC_DEV0_EPF5_STRAP4 0x403ce84 #define mmRCC_DEV0_EPF5_STRAP4_BASE_IDX 3 -#define mmRCC_DEV0_EPF5_STRAP5 0x403ce85 +#define mmRCC_DEV0_EPF5_STRAP5 0x403ce85 #define mmRCC_DEV0_EPF5_STRAP5_BASE_IDX 3 -#define mmRCC_DEV0_EPF5_STRAP6 0x403ce86 +#define mmRCC_DEV0_EPF5_STRAP6 0x403ce86 #define mmRCC_DEV0_EPF5_STRAP6_BASE_IDX 3 -#define mmRCC_DEV0_EPF5_STRAP13 0x403ce8d +#define mmRCC_DEV0_EPF5_STRAP13 0x403ce8d #define mmRCC_DEV0_EPF5_STRAP13_BASE_IDX 3 -#define mmRCC_DEV0_EPF6_STRAP0 0x403cf00 +#define mmRCC_DEV0_EPF6_STRAP0 0x403cf00 #define mmRCC_DEV0_EPF6_STRAP0_BASE_IDX 3 -#define mmRCC_DEV0_EPF6_STRAP2 0x403cf02 +#define mmRCC_DEV0_EPF6_STRAP2 0x403cf02 #define mmRCC_DEV0_EPF6_STRAP2_BASE_IDX 3 -#define mmRCC_DEV0_EPF6_STRAP3 0x403cf03 +#define mmRCC_DEV0_EPF6_STRAP3 0x403cf03 #define mmRCC_DEV0_EPF6_STRAP3_BASE_IDX 3 -#define mmRCC_DEV0_EPF6_STRAP4 0x403cf04 +#define mmRCC_DEV0_EPF6_STRAP4 0x403cf04 #define mmRCC_DEV0_EPF6_STRAP4_BASE_IDX 3 -#define mmRCC_DEV0_EPF6_STRAP5 0x403cf05 +#define mmRCC_DEV0_EPF6_STRAP5 0x403cf05 #define mmRCC_DEV0_EPF6_STRAP5_BASE_IDX 3 -#define mmRCC_DEV0_EPF6_STRAP6 0x403cf06 +#define mmRCC_DEV0_EPF6_STRAP6 0x403cf06 #define mmRCC_DEV0_EPF6_STRAP6_BASE_IDX 3 -#define mmRCC_DEV0_EPF6_STRAP13 0x403cf0d +#define mmRCC_DEV0_EPF6_STRAP13 0x403cf0d #define mmRCC_DEV0_EPF6_STRAP13_BASE_IDX 3 -#define mmRCC_DEV0_EPF7_STRAP0 0x403cf80 +#define mmRCC_DEV0_EPF7_STRAP0 0x403cf80 #define mmRCC_DEV0_EPF7_STRAP0_BASE_IDX 3 -#define mmRCC_DEV0_EPF7_STRAP2 0x403cf82 +#define mmRCC_DEV0_EPF7_STRAP2 0x403cf82 #define mmRCC_DEV0_EPF7_STRAP2_BASE_IDX 3 -#define mmRCC_DEV0_EPF7_STRAP3 0x403cf83 +#define mmRCC_DEV0_EPF7_STRAP3 0x403cf83 #define mmRCC_DEV0_EPF7_STRAP3_BASE_IDX 3 -#define mmRCC_DEV0_EPF7_STRAP4 0x403cf84 +#define mmRCC_DEV0_EPF7_STRAP4 0x403cf84 #define mmRCC_DEV0_EPF7_STRAP4_BASE_IDX 3 -#define mmRCC_DEV0_EPF7_STRAP5 0x403cf85 +#define mmRCC_DEV0_EPF7_STRAP5 0x403cf85 #define mmRCC_DEV0_EPF7_STRAP5_BASE_IDX 3 -#define mmRCC_DEV0_EPF7_STRAP6 0x403cf86 +#define mmRCC_DEV0_EPF7_STRAP6 0x403cf86 #define mmRCC_DEV0_EPF7_STRAP6_BASE_IDX 3 -#define mmRCC_DEV0_EPF7_STRAP13 0x403cf8d +#define mmRCC_DEV0_EPF7_STRAP13 0x403cf8d #define mmRCC_DEV0_EPF7_STRAP13_BASE_IDX 3 -#define mmRCC_DEV1_EPF0_STRAP0 0x403d000 +#define mmRCC_DEV1_EPF0_STRAP0 0x403d000 #define mmRCC_DEV1_EPF0_STRAP0_BASE_IDX 3 -#define mmRCC_DEV1_EPF0_STRAP2 0x403d002 +#define mmRCC_DEV1_EPF0_STRAP2 0x403d002 #define mmRCC_DEV1_EPF0_STRAP2_BASE_IDX 3 -#define mmRCC_DEV1_EPF0_STRAP3 0x403d003 +#define mmRCC_DEV1_EPF0_STRAP3 0x403d003 #define mmRCC_DEV1_EPF0_STRAP3_BASE_IDX 3 -#define mmRCC_DEV1_EPF0_STRAP4 0x403d004 +#define mmRCC_DEV1_EPF0_STRAP4 0x403d004 #define mmRCC_DEV1_EPF0_STRAP4_BASE_IDX 3 -#define mmRCC_DEV1_EPF0_STRAP5 0x403d005 +#define mmRCC_DEV1_EPF0_STRAP5 0x403d005 #define mmRCC_DEV1_EPF0_STRAP5_BASE_IDX 3 -#define mmRCC_DEV1_EPF0_STRAP6 0x403d006 +#define mmRCC_DEV1_EPF0_STRAP6 0x403d006 #define mmRCC_DEV1_EPF0_STRAP6_BASE_IDX 3 -#define mmRCC_DEV1_EPF0_STRAP13 0x403d00d +#define mmRCC_DEV1_EPF0_STRAP13 0x403d00d #define mmRCC_DEV1_EPF0_STRAP13_BASE_IDX 3 -#define mmRCC_DEV1_EPF1_STRAP0 0x403d080 +#define mmRCC_DEV1_EPF1_STRAP0 0x403d080 #define mmRCC_DEV1_EPF1_STRAP0_BASE_IDX 3 -#define mmRCC_DEV1_EPF1_STRAP2 0x403d082 +#define mmRCC_DEV1_EPF1_STRAP2 0x403d082 #define mmRCC_DEV1_EPF1_STRAP2_BASE_IDX 3 -#define mmRCC_DEV1_EPF1_STRAP3 0x403d083 +#define mmRCC_DEV1_EPF1_STRAP3 0x403d083 #define mmRCC_DEV1_EPF1_STRAP3_BASE_IDX 3 -#define mmRCC_DEV1_EPF1_STRAP4 0x403d084 +#define mmRCC_DEV1_EPF1_STRAP4 0x403d084 #define mmRCC_DEV1_EPF1_STRAP4_BASE_IDX 3 -#define mmRCC_DEV1_EPF1_STRAP5 0x403d085 +#define mmRCC_DEV1_EPF1_STRAP5 0x403d085 #define mmRCC_DEV1_EPF1_STRAP5_BASE_IDX 3 -#define mmRCC_DEV1_EPF1_STRAP6 0x403d086 +#define mmRCC_DEV1_EPF1_STRAP6 0x403d086 #define mmRCC_DEV1_EPF1_STRAP6_BASE_IDX 3 -#define mmRCC_DEV1_EPF1_STRAP13 0x403d08d +#define mmRCC_DEV1_EPF1_STRAP13 0x403d08d #define mmRCC_DEV1_EPF1_STRAP13_BASE_IDX 3 -#define mmRCC_DEV1_EPF2_STRAP0 0x403d100 +#define mmRCC_DEV1_EPF2_STRAP0 0x403d100 #define mmRCC_DEV1_EPF2_STRAP0_BASE_IDX 3 -#define mmRCC_DEV1_EPF2_STRAP2 0x403d102 +#define mmRCC_DEV1_EPF2_STRAP2 0x403d102 #define mmRCC_DEV1_EPF2_STRAP2_BASE_IDX 3 -#define mmRCC_DEV1_EPF2_STRAP3 0x403d103 +#define mmRCC_DEV1_EPF2_STRAP3 0x403d103 #define mmRCC_DEV1_EPF2_STRAP3_BASE_IDX 3 -#define mmRCC_DEV1_EPF2_STRAP4 0x403d104 +#define mmRCC_DEV1_EPF2_STRAP4 0x403d104 #define mmRCC_DEV1_EPF2_STRAP4_BASE_IDX 3 -#define mmRCC_DEV1_EPF2_STRAP5 0x403d105 +#define mmRCC_DEV1_EPF2_STRAP5 0x403d105 #define mmRCC_DEV1_EPF2_STRAP5_BASE_IDX 3 -#define mmRCC_DEV1_EPF2_STRAP6 0x403d106 +#define mmRCC_DEV1_EPF2_STRAP6 0x403d106 #define mmRCC_DEV1_EPF2_STRAP6_BASE_IDX 3 -#define mmRCC_DEV1_EPF2_STRAP13 0x403d10d +#define mmRCC_DEV1_EPF2_STRAP13 0x403d10d #define mmRCC_DEV1_EPF2_STRAP13_BASE_IDX 3 // addressBlock: bif_rst_bif_rst_regblk // base address: 0x10100000 -#define ixHARD_RST_CTRL 0x38000 -#define ixRSMU_SOFT_RST_CTRL 0x38004 -#define ixSELF_SOFT_RST 0x38008 -#define ixGFX_DRV_MODE1_RST_CTRL 0x3800c -#define ixBIF_RST_MISC_CTRL 0x38010 -#define ixBIF_RST_MISC_CTRL2 0x38014 -#define ixBIF_RST_MISC_CTRL3 0x38018 -#define ixBIF_RST_GFXVF_FLR_IDLE 0x3801c -#define ixDEV0_PF0_FLR_RST_CTRL 0x38020 -#define ixDEV0_PF1_FLR_RST_CTRL 0x38024 -#define ixDEV0_PF2_FLR_RST_CTRL 0x38028 -#define ixDEV0_PF3_FLR_RST_CTRL 0x3802c -#define ixDEV0_PF4_FLR_RST_CTRL 0x38030 -#define ixDEV0_PF5_FLR_RST_CTRL 0x38034 -#define ixDEV0_PF6_FLR_RST_CTRL 0x38038 -#define ixDEV0_PF7_FLR_RST_CTRL 0x3803c -#define ixBIF_INST_RESET_INTR_STS 0x38040 -#define ixBIF_PF_FLR_INTR_STS 0x38044 -#define ixBIF_D3HOTD0_INTR_STS 0x38048 -#define ixBIF_POWER_INTR_STS 0x38050 -#define ixBIF_PF_DSTATE_INTR_STS 0x38054 -#define ixBIF_PF0_VF_FLR_INTR_STS 0x38060 -#define ixBIF_INST_RESET_INTR_MASK 0x38080 -#define ixBIF_PF_FLR_INTR_MASK 0x38084 -#define ixBIF_D3HOTD0_INTR_MASK 0x38088 -#define ixBIF_POWER_INTR_MASK 0x38090 -#define ixBIF_PF_DSTATE_INTR_MASK 0x38094 -#define ixBIF_PF0_VF_FLR_INTR_MASK 0x380a0 -#define ixBIF_PF_FLR_RST 0x38100 -#define ixBIF_PF0_VF_FLR_RST 0x38120 -#define ixBIF_DEV0_PF0_DSTATE_VALUE 0x38140 -#define ixBIF_DEV0_PF1_DSTATE_VALUE 0x38144 -#define ixBIF_DEV0_PF2_DSTATE_VALUE 0x38148 -#define ixBIF_DEV0_PF3_DSTATE_VALUE 0x3814c -#define ixBIF_DEV0_PF4_DSTATE_VALUE 0x38150 -#define ixBIF_DEV0_PF5_DSTATE_VALUE 0x38154 -#define ixBIF_DEV0_PF6_DSTATE_VALUE 0x38158 -#define ixBIF_DEV0_PF7_DSTATE_VALUE 0x3815c -#define ixDEV0_PF0_D3HOTD0_RST_CTRL 0x381e0 -#define ixDEV0_PF1_D3HOTD0_RST_CTRL 0x381e4 -#define ixDEV0_PF2_D3HOTD0_RST_CTRL 0x381e8 -#define ixDEV0_PF3_D3HOTD0_RST_CTRL 0x381ec -#define ixDEV0_PF4_D3HOTD0_RST_CTRL 0x381f0 -#define ixDEV0_PF5_D3HOTD0_RST_CTRL 0x381f4 -#define ixDEV0_PF6_D3HOTD0_RST_CTRL 0x381f8 -#define ixDEV0_PF7_D3HOTD0_RST_CTRL 0x381fc -#define ixBIF_PORT0_DSTATE_VALUE 0x388c0 +#define ixHARD_RST_CTRL 0x38000 +#define ixRSMU_SOFT_RST_CTRL 0x38004 +#define ixSELF_SOFT_RST 0x38008 +#define ixGFX_DRV_MODE1_RST_CTRL 0x3800c +#define ixBIF_RST_MISC_CTRL 0x38010 +#define ixBIF_RST_MISC_CTRL2 0x38014 +#define ixBIF_RST_MISC_CTRL3 0x38018 +#define ixBIF_RST_GFXVF_FLR_IDLE 0x3801c +#define ixDEV0_PF0_FLR_RST_CTRL 0x38020 +#define ixDEV0_PF1_FLR_RST_CTRL 0x38024 +#define ixDEV0_PF2_FLR_RST_CTRL 0x38028 +#define ixDEV0_PF3_FLR_RST_CTRL 0x3802c +#define ixDEV0_PF4_FLR_RST_CTRL 0x38030 +#define ixDEV0_PF5_FLR_RST_CTRL 0x38034 +#define ixDEV0_PF6_FLR_RST_CTRL 0x38038 +#define ixDEV0_PF7_FLR_RST_CTRL 0x3803c +#define ixBIF_INST_RESET_INTR_STS 0x38040 +#define ixBIF_PF_FLR_INTR_STS 0x38044 +#define ixBIF_D3HOTD0_INTR_STS 0x38048 +#define ixBIF_POWER_INTR_STS 0x38050 +#define ixBIF_PF_DSTATE_INTR_STS 0x38054 +#define ixBIF_PF0_VF_FLR_INTR_STS 0x38060 +#define ixBIF_INST_RESET_INTR_MASK 0x38080 +#define ixBIF_PF_FLR_INTR_MASK 0x38084 +#define ixBIF_D3HOTD0_INTR_MASK 0x38088 +#define ixBIF_POWER_INTR_MASK 0x38090 +#define ixBIF_PF_DSTATE_INTR_MASK 0x38094 +#define ixBIF_PF0_VF_FLR_INTR_MASK 0x380a0 +#define ixBIF_PF_FLR_RST 0x38100 +#define ixBIF_PF0_VF_FLR_RST 0x38120 +#define ixBIF_DEV0_PF0_DSTATE_VALUE 0x38140 +#define ixBIF_DEV0_PF1_DSTATE_VALUE 0x38144 +#define ixBIF_DEV0_PF2_DSTATE_VALUE 0x38148 +#define ixBIF_DEV0_PF3_DSTATE_VALUE 0x3814c +#define ixBIF_DEV0_PF4_DSTATE_VALUE 0x38150 +#define ixBIF_DEV0_PF5_DSTATE_VALUE 0x38154 +#define ixBIF_DEV0_PF6_DSTATE_VALUE 0x38158 +#define ixBIF_DEV0_PF7_DSTATE_VALUE 0x3815c +#define ixDEV0_PF0_D3HOTD0_RST_CTRL 0x381e0 +#define ixDEV0_PF1_D3HOTD0_RST_CTRL 0x381e4 +#define ixDEV0_PF2_D3HOTD0_RST_CTRL 0x381e8 +#define ixDEV0_PF3_D3HOTD0_RST_CTRL 0x381ec +#define ixDEV0_PF4_D3HOTD0_RST_CTRL 0x381f0 +#define ixDEV0_PF5_D3HOTD0_RST_CTRL 0x381f4 +#define ixDEV0_PF6_D3HOTD0_RST_CTRL 0x381f8 +#define ixDEV0_PF7_D3HOTD0_RST_CTRL 0x381fc +#define ixBIF_PORT0_DSTATE_VALUE 0x388c0 // addressBlock: bif_misc_bif_misc_regblk // base address: 0x10100000 -#define ixMISC_SCRATCH 0x3a000 -#define ixINTR_LINE_POLARITY 0x3a004 -#define ixINTR_LINE_ENABLE 0x3a008 -#define ixOUTSTANDING_VC_ALLOC 0x3a00c -#define ixBIFC_MISC_CTRL0 0x3a010 -#define ixBIFC_MISC_CTRL1 0x3a014 -#define ixBIFC_BME_ERR_LOG 0x3a018 -#define ixBIFC_RCCBIH_BME_ERR_LOG 0x3a01c -#define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1 0x3a020 -#define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3 0x3a024 -#define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5 0x3a028 -#define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7 0x3a02c -#define ixNBIF_VWIRE_CTRL 0x3a040 -#define ixNBIF_SMN_VWR_VCHG_DIS_CTRL 0x3a044 -#define ixNBIF_SMN_VWR_VCHG_RST_CTRL0 0x3a048 -#define ixNBIF_SMN_VWR_VCHG_TRIG 0x3a050 -#define ixNBIF_SMN_VWR_WTRIG_CNTL 0x3a054 -#define ixNBIF_SMN_VWR_VCHG_DIS_CTRL_1 0x3a058 -#define ixNBIF_MGCG_CTRL 0x3a05c -#define ixNBIF_DS_CTRL_LCLK 0x3a060 -#define ixSMN_MST_CNTL0 0x3a064 -#define ixSMN_MST_EP_CNTL1 0x3a068 -#define ixSMN_MST_EP_CNTL2 0x3a06c -#define ixNBIF_SDP_VWR_VCHG_DIS_CTRL 0x3a070 -#define ixNBIF_SDP_VWR_VCHG_RST_CTRL0 0x3a074 -#define ixNBIF_SDP_VWR_VCHG_RST_CTRL1 0x3a078 -#define ixNBIF_SDP_VWR_VCHG_TRIG 0x3a07c -#define ixBME_DUMMY_CNTL_0 0x3a098 -#define ixBIFC_THT_CNTL 0x3a09c -#define ixBIFC_HSTARB_CNTL 0x3a0a0 -#define ixBIFC_GSI_CNTL 0x3a0a4 -#define ixBIFC_PCIEFUNC_CNTL 0x3a0a8 -#define ixBIFC_SDP_CNTL_0 0x3a0b0 -#define ixBIFC_PERF_CNTL_0 0x3a0c0 -#define ixBIFC_PERF_CNTL_1 0x3a0c4 -#define ixBIFC_PERF_CNT_MMIO_RD 0x3a0c8 -#define ixBIFC_PERF_CNT_MMIO_WR 0x3a0cc -#define ixBIFC_PERF_CNT_DMA_RD 0x3a0d0 -#define ixBIFC_PERF_CNT_DMA_WR 0x3a0d4 -#define ixNBIF_REGIF_ERRSET_CTRL 0x3a0d8 -#define ixSMN_MST_EP_CNTL3 0x3a0f0 -#define ixSMN_MST_EP_CNTL4 0x3a0f4 -#define ixBIF_SELFRING_BUFFER_VID 0x3a100 -#define ixBIF_SELFRING_VECTOR_CNTL 0x3a104 +#define ixMISC_SCRATCH 0x3a000 +#define ixINTR_LINE_POLARITY 0x3a004 +#define ixINTR_LINE_ENABLE 0x3a008 +#define ixOUTSTANDING_VC_ALLOC 0x3a00c +#define ixBIFC_MISC_CTRL0 0x3a010 +#define ixBIFC_MISC_CTRL1 0x3a014 +#define ixBIFC_BME_ERR_LOG 0x3a018 +#define ixBIFC_RCCBIH_BME_ERR_LOG 0x3a01c +#define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1 0x3a020 +#define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3 0x3a024 +#define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5 0x3a028 +#define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7 0x3a02c +#define ixNBIF_VWIRE_CTRL 0x3a040 +#define ixNBIF_SMN_VWR_VCHG_DIS_CTRL 0x3a044 +#define ixNBIF_SMN_VWR_VCHG_RST_CTRL0 0x3a048 +#define ixNBIF_SMN_VWR_VCHG_TRIG 0x3a050 +#define ixNBIF_SMN_VWR_WTRIG_CNTL 0x3a054 +#define ixNBIF_SMN_VWR_VCHG_DIS_CTRL_1 0x3a058 +#define ixNBIF_MGCG_CTRL 0x3a05c +#define ixNBIF_DS_CTRL_LCLK 0x3a060 +#define ixSMN_MST_CNTL0 0x3a064 +#define ixSMN_MST_EP_CNTL1 0x3a068 +#define ixSMN_MST_EP_CNTL2 0x3a06c +#define ixNBIF_SDP_VWR_VCHG_DIS_CTRL 0x3a070 +#define ixNBIF_SDP_VWR_VCHG_RST_CTRL0 0x3a074 +#define ixNBIF_SDP_VWR_VCHG_RST_CTRL1 0x3a078 +#define ixNBIF_SDP_VWR_VCHG_TRIG 0x3a07c +#define ixBME_DUMMY_CNTL_0 0x3a098 +#define ixBIFC_THT_CNTL 0x3a09c +#define ixBIFC_HSTARB_CNTL 0x3a0a0 +#define ixBIFC_GSI_CNTL 0x3a0a4 +#define ixBIFC_PCIEFUNC_CNTL 0x3a0a8 +#define ixBIFC_SDP_CNTL_0 0x3a0b0 +#define ixBIFC_PERF_CNTL_0 0x3a0c0 +#define ixBIFC_PERF_CNTL_1 0x3a0c4 +#define ixBIFC_PERF_CNT_MMIO_RD 0x3a0c8 +#define ixBIFC_PERF_CNT_MMIO_WR 0x3a0cc +#define ixBIFC_PERF_CNT_DMA_RD 0x3a0d0 +#define ixBIFC_PERF_CNT_DMA_WR 0x3a0d4 +#define ixNBIF_REGIF_ERRSET_CTRL 0x3a0d8 +#define ixSMN_MST_EP_CNTL3 0x3a0f0 +#define ixSMN_MST_EP_CNTL4 0x3a0f4 +#define ixBIF_SELFRING_BUFFER_VID 0x3a100 +#define ixBIF_SELFRING_VECTOR_CNTL 0x3a104 // addressBlock: bif_ras_bif_ras_regblk // base address: 0x10100000 -#define ixBIF_RAS_LEAF0_CTRL 0x39000 -#define ixBIF_RAS_LEAF1_CTRL 0x39004 -#define ixBIF_RAS_LEAF2_CTRL 0x39008 -#define ixBIF_RAS_MISC_CTRL 0x39100 -#define ixBIF_IOHUB_RAS_IH_CNTL 0x39ff8 -#define ixBIF_RAS_VWR_FROM_IOHUB 0x39ffc +#define ixBIF_RAS_LEAF0_CTRL 0x39000 +#define ixBIF_RAS_LEAF1_CTRL 0x39004 +#define ixBIF_RAS_LEAF2_CTRL 0x39008 +#define ixBIF_RAS_MISC_CTRL 0x39100 +#define ixBIF_IOHUB_RAS_IH_CNTL 0x39ff8 +#define ixBIF_RAS_VWR_FROM_IOHUB 0x39ffc // addressBlock: rcc_pfc_amdgfx_RCCPFCDEC // base address: 0x10134000 -#define ixRCC_PFC_LTR_CNTL 0x0100 // duplicate -#define ixRCC_PFC_PME_RESTORE 0x0104 // duplicate -#define ixRCC_PFC_STICKY_RESTORE_0 0x0108 // duplicate -#define ixRCC_PFC_STICKY_RESTORE_1 0x010c // duplicate -#define ixRCC_PFC_STICKY_RESTORE_2 0x0110 // duplicate -#define ixRCC_PFC_STICKY_RESTORE_3 0x0114 // duplicate -#define ixRCC_PFC_STICKY_RESTORE_4 0x0118 // duplicate -#define ixRCC_PFC_STICKY_RESTORE_5 0x011c // duplicate -#define ixRCC_PFC_AUXPWR_CNTL 0x0120 // duplicate +#define ixRCC_PFC_LTR_CNTL 0x0100 // duplicate +#define ixRCC_PFC_PME_RESTORE 0x0104 // duplicate +#define ixRCC_PFC_STICKY_RESTORE_0 0x0108 // duplicate +#define ixRCC_PFC_STICKY_RESTORE_1 0x010c // duplicate +#define ixRCC_PFC_STICKY_RESTORE_2 0x0110 // duplicate +#define ixRCC_PFC_STICKY_RESTORE_3 0x0114 // duplicate +#define ixRCC_PFC_STICKY_RESTORE_4 0x0118 // duplicate +#define ixRCC_PFC_STICKY_RESTORE_5 0x011c // duplicate +#define ixRCC_PFC_AUXPWR_CNTL 0x0120 // duplicate // addressBlock: rcc_pfc_amdgfxaz_RCCPFCDEC // base address: 0x10134200 -#define ixRCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL 0x0100 // duplicate -#define ixRCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE 0x0104 // duplicate -#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0 0x0108 // duplicate -#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_1 0x010c // duplicate -#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_2 0x0110 // duplicate -#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_3 0x0114 // duplicate -#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_4 0x0118 // duplicate -#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_5 0x011c // duplicate -#define ixRCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL 0x0120 // duplicate +#define ixRCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL 0x0100 // duplicate +#define ixRCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE 0x0104 // duplicate +#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0 0x0108 // duplicate +#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_1 0x010c // duplicate +#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_2 0x0110 // duplicate +#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_3 0x0114 // duplicate +#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_4 0x0118 // duplicate +#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_5 0x011c // duplicate +#define ixRCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL 0x0120 // duplicate // addressBlock: pciemsix_amdgfx_MSIXTDEC // base address: 0x10170000 -#define ixPCIEMSIX_VECT0_ADDR_LO 0x0000 -#define ixPCIEMSIX_VECT0_ADDR_HI 0x0004 -#define ixPCIEMSIX_VECT0_MSG_DATA 0x0008 -#define ixPCIEMSIX_VECT0_CONTROL 0x000c -#define ixPCIEMSIX_VECT1_ADDR_LO 0x0010 -#define ixPCIEMSIX_VECT1_ADDR_HI 0x0014 -#define ixPCIEMSIX_VECT1_MSG_DATA 0x0018 -#define ixPCIEMSIX_VECT1_CONTROL 0x001c -#define ixPCIEMSIX_VECT2_ADDR_LO 0x0020 -#define ixPCIEMSIX_VECT2_ADDR_HI 0x0024 -#define ixPCIEMSIX_VECT2_MSG_DATA 0x0028 -#define ixPCIEMSIX_VECT2_CONTROL 0x002c -#define ixPCIEMSIX_VECT3_ADDR_LO 0x0030 -#define ixPCIEMSIX_VECT3_ADDR_HI 0x0034 -#define ixPCIEMSIX_VECT3_MSG_DATA 0x0038 -#define ixPCIEMSIX_VECT3_CONTROL 0x003c -#define ixPCIEMSIX_VECT4_ADDR_LO 0x0040 -#define ixPCIEMSIX_VECT4_ADDR_HI 0x0044 -#define ixPCIEMSIX_VECT4_MSG_DATA 0x0048 -#define ixPCIEMSIX_VECT4_CONTROL 0x004c -#define ixPCIEMSIX_VECT5_ADDR_LO 0x0050 -#define ixPCIEMSIX_VECT5_ADDR_HI 0x0054 -#define ixPCIEMSIX_VECT5_MSG_DATA 0x0058 -#define ixPCIEMSIX_VECT5_CONTROL 0x005c -#define ixPCIEMSIX_VECT6_ADDR_LO 0x0060 -#define ixPCIEMSIX_VECT6_ADDR_HI 0x0064 -#define ixPCIEMSIX_VECT6_MSG_DATA 0x0068 -#define ixPCIEMSIX_VECT6_CONTROL 0x006c -#define ixPCIEMSIX_VECT7_ADDR_LO 0x0070 -#define ixPCIEMSIX_VECT7_ADDR_HI 0x0074 -#define ixPCIEMSIX_VECT7_MSG_DATA 0x0078 -#define ixPCIEMSIX_VECT7_CONTROL 0x007c -#define ixPCIEMSIX_VECT8_ADDR_LO 0x0080 -#define ixPCIEMSIX_VECT8_ADDR_HI 0x0084 -#define ixPCIEMSIX_VECT8_MSG_DATA 0x0088 -#define ixPCIEMSIX_VECT8_CONTROL 0x008c -#define ixPCIEMSIX_VECT9_ADDR_LO 0x0090 -#define ixPCIEMSIX_VECT9_ADDR_HI 0x0094 -#define ixPCIEMSIX_VECT9_MSG_DATA 0x0098 -#define ixPCIEMSIX_VECT9_CONTROL 0x009c -#define ixPCIEMSIX_VECT10_ADDR_LO 0x00a0 -#define ixPCIEMSIX_VECT10_ADDR_HI 0x00a4 -#define ixPCIEMSIX_VECT10_MSG_DATA 0x00a8 -#define ixPCIEMSIX_VECT10_CONTROL 0x00ac -#define ixPCIEMSIX_VECT11_ADDR_LO 0x00b0 -#define ixPCIEMSIX_VECT11_ADDR_HI 0x00b4 -#define ixPCIEMSIX_VECT11_MSG_DATA 0x00b8 -#define ixPCIEMSIX_VECT11_CONTROL 0x00bc -#define ixPCIEMSIX_VECT12_ADDR_LO 0x00c0 -#define ixPCIEMSIX_VECT12_ADDR_HI 0x00c4 -#define ixPCIEMSIX_VECT12_MSG_DATA 0x00c8 -#define ixPCIEMSIX_VECT12_CONTROL 0x00cc -#define ixPCIEMSIX_VECT13_ADDR_LO 0x00d0 -#define ixPCIEMSIX_VECT13_ADDR_HI 0x00d4 -#define ixPCIEMSIX_VECT13_MSG_DATA 0x00d8 -#define ixPCIEMSIX_VECT13_CONTROL 0x00dc -#define ixPCIEMSIX_VECT14_ADDR_LO 0x00e0 -#define ixPCIEMSIX_VECT14_ADDR_HI 0x00e4 -#define ixPCIEMSIX_VECT14_MSG_DATA 0x00e8 -#define ixPCIEMSIX_VECT14_CONTROL 0x00ec -#define ixPCIEMSIX_VECT15_ADDR_LO 0x00f0 -#define ixPCIEMSIX_VECT15_ADDR_HI 0x00f4 -#define ixPCIEMSIX_VECT15_MSG_DATA 0x00f8 -#define ixPCIEMSIX_VECT15_CONTROL 0x00fc -#define ixPCIEMSIX_VECT16_ADDR_LO 0x0100 -#define ixPCIEMSIX_VECT16_ADDR_HI 0x0104 -#define ixPCIEMSIX_VECT16_MSG_DATA 0x0108 -#define ixPCIEMSIX_VECT16_CONTROL 0x010c -#define ixPCIEMSIX_VECT17_ADDR_LO 0x0110 -#define ixPCIEMSIX_VECT17_ADDR_HI 0x0114 -#define ixPCIEMSIX_VECT17_MSG_DATA 0x0118 -#define ixPCIEMSIX_VECT17_CONTROL 0x011c -#define ixPCIEMSIX_VECT18_ADDR_LO 0x0120 -#define ixPCIEMSIX_VECT18_ADDR_HI 0x0124 -#define ixPCIEMSIX_VECT18_MSG_DATA 0x0128 -#define ixPCIEMSIX_VECT18_CONTROL 0x012c -#define ixPCIEMSIX_VECT19_ADDR_LO 0x0130 -#define ixPCIEMSIX_VECT19_ADDR_HI 0x0134 -#define ixPCIEMSIX_VECT19_MSG_DATA 0x0138 -#define ixPCIEMSIX_VECT19_CONTROL 0x013c -#define ixPCIEMSIX_VECT20_ADDR_LO 0x0140 -#define ixPCIEMSIX_VECT20_ADDR_HI 0x0144 -#define ixPCIEMSIX_VECT20_MSG_DATA 0x0148 -#define ixPCIEMSIX_VECT20_CONTROL 0x014c -#define ixPCIEMSIX_VECT21_ADDR_LO 0x0150 -#define ixPCIEMSIX_VECT21_ADDR_HI 0x0154 -#define ixPCIEMSIX_VECT21_MSG_DATA 0x0158 -#define ixPCIEMSIX_VECT21_CONTROL 0x015c -#define ixPCIEMSIX_VECT22_ADDR_LO 0x0160 -#define ixPCIEMSIX_VECT22_ADDR_HI 0x0164 -#define ixPCIEMSIX_VECT22_MSG_DATA 0x0168 -#define ixPCIEMSIX_VECT22_CONTROL 0x016c -#define ixPCIEMSIX_VECT23_ADDR_LO 0x0170 -#define ixPCIEMSIX_VECT23_ADDR_HI 0x0174 -#define ixPCIEMSIX_VECT23_MSG_DATA 0x0178 -#define ixPCIEMSIX_VECT23_CONTROL 0x017c -#define ixPCIEMSIX_VECT24_ADDR_LO 0x0180 -#define ixPCIEMSIX_VECT24_ADDR_HI 0x0184 -#define ixPCIEMSIX_VECT24_MSG_DATA 0x0188 -#define ixPCIEMSIX_VECT24_CONTROL 0x018c -#define ixPCIEMSIX_VECT25_ADDR_LO 0x0190 -#define ixPCIEMSIX_VECT25_ADDR_HI 0x0194 -#define ixPCIEMSIX_VECT25_MSG_DATA 0x0198 -#define ixPCIEMSIX_VECT25_CONTROL 0x019c -#define ixPCIEMSIX_VECT26_ADDR_LO 0x01a0 -#define ixPCIEMSIX_VECT26_ADDR_HI 0x01a4 -#define ixPCIEMSIX_VECT26_MSG_DATA 0x01a8 -#define ixPCIEMSIX_VECT26_CONTROL 0x01ac -#define ixPCIEMSIX_VECT27_ADDR_LO 0x01b0 -#define ixPCIEMSIX_VECT27_ADDR_HI 0x01b4 -#define ixPCIEMSIX_VECT27_MSG_DATA 0x01b8 -#define ixPCIEMSIX_VECT27_CONTROL 0x01bc -#define ixPCIEMSIX_VECT28_ADDR_LO 0x01c0 -#define ixPCIEMSIX_VECT28_ADDR_HI 0x01c4 -#define ixPCIEMSIX_VECT28_MSG_DATA 0x01c8 -#define ixPCIEMSIX_VECT28_CONTROL 0x01cc -#define ixPCIEMSIX_VECT29_ADDR_LO 0x01d0 -#define ixPCIEMSIX_VECT29_ADDR_HI 0x01d4 -#define ixPCIEMSIX_VECT29_MSG_DATA 0x01d8 -#define ixPCIEMSIX_VECT29_CONTROL 0x01dc -#define ixPCIEMSIX_VECT30_ADDR_LO 0x01e0 -#define ixPCIEMSIX_VECT30_ADDR_HI 0x01e4 -#define ixPCIEMSIX_VECT30_MSG_DATA 0x01e8 -#define ixPCIEMSIX_VECT30_CONTROL 0x01ec -#define ixPCIEMSIX_VECT31_ADDR_LO 0x01f0 -#define ixPCIEMSIX_VECT31_ADDR_HI 0x01f4 -#define ixPCIEMSIX_VECT31_MSG_DATA 0x01f8 -#define ixPCIEMSIX_VECT31_CONTROL 0x01fc +#define ixPCIEMSIX_VECT0_ADDR_LO 0x0000 +#define ixPCIEMSIX_VECT0_ADDR_HI 0x0004 +#define ixPCIEMSIX_VECT0_MSG_DATA 0x0008 +#define ixPCIEMSIX_VECT0_CONTROL 0x000c +#define ixPCIEMSIX_VECT1_ADDR_LO 0x0010 +#define ixPCIEMSIX_VECT1_ADDR_HI 0x0014 +#define ixPCIEMSIX_VECT1_MSG_DATA 0x0018 +#define ixPCIEMSIX_VECT1_CONTROL 0x001c +#define ixPCIEMSIX_VECT2_ADDR_LO 0x0020 +#define ixPCIEMSIX_VECT2_ADDR_HI 0x0024 +#define ixPCIEMSIX_VECT2_MSG_DATA 0x0028 +#define ixPCIEMSIX_VECT2_CONTROL 0x002c +#define ixPCIEMSIX_VECT3_ADDR_LO 0x0030 +#define ixPCIEMSIX_VECT3_ADDR_HI 0x0034 +#define ixPCIEMSIX_VECT3_MSG_DATA 0x0038 +#define ixPCIEMSIX_VECT3_CONTROL 0x003c +#define ixPCIEMSIX_VECT4_ADDR_LO 0x0040 +#define ixPCIEMSIX_VECT4_ADDR_HI 0x0044 +#define ixPCIEMSIX_VECT4_MSG_DATA 0x0048 +#define ixPCIEMSIX_VECT4_CONTROL 0x004c +#define ixPCIEMSIX_VECT5_ADDR_LO 0x0050 +#define ixPCIEMSIX_VECT5_ADDR_HI 0x0054 +#define ixPCIEMSIX_VECT5_MSG_DATA 0x0058 +#define ixPCIEMSIX_VECT5_CONTROL 0x005c +#define ixPCIEMSIX_VECT6_ADDR_LO 0x0060 +#define ixPCIEMSIX_VECT6_ADDR_HI 0x0064 +#define ixPCIEMSIX_VECT6_MSG_DATA 0x0068 +#define ixPCIEMSIX_VECT6_CONTROL 0x006c +#define ixPCIEMSIX_VECT7_ADDR_LO 0x0070 +#define ixPCIEMSIX_VECT7_ADDR_HI 0x0074 +#define ixPCIEMSIX_VECT7_MSG_DATA 0x0078 +#define ixPCIEMSIX_VECT7_CONTROL 0x007c +#define ixPCIEMSIX_VECT8_ADDR_LO 0x0080 +#define ixPCIEMSIX_VECT8_ADDR_HI 0x0084 +#define ixPCIEMSIX_VECT8_MSG_DATA 0x0088 +#define ixPCIEMSIX_VECT8_CONTROL 0x008c +#define ixPCIEMSIX_VECT9_ADDR_LO 0x0090 +#define ixPCIEMSIX_VECT9_ADDR_HI 0x0094 +#define ixPCIEMSIX_VECT9_MSG_DATA 0x0098 +#define ixPCIEMSIX_VECT9_CONTROL 0x009c +#define ixPCIEMSIX_VECT10_ADDR_LO 0x00a0 +#define ixPCIEMSIX_VECT10_ADDR_HI 0x00a4 +#define ixPCIEMSIX_VECT10_MSG_DATA 0x00a8 +#define ixPCIEMSIX_VECT10_CONTROL 0x00ac +#define ixPCIEMSIX_VECT11_ADDR_LO 0x00b0 +#define ixPCIEMSIX_VECT11_ADDR_HI 0x00b4 +#define ixPCIEMSIX_VECT11_MSG_DATA 0x00b8 +#define ixPCIEMSIX_VECT11_CONTROL 0x00bc +#define ixPCIEMSIX_VECT12_ADDR_LO 0x00c0 +#define ixPCIEMSIX_VECT12_ADDR_HI 0x00c4 +#define ixPCIEMSIX_VECT12_MSG_DATA 0x00c8 +#define ixPCIEMSIX_VECT12_CONTROL 0x00cc +#define ixPCIEMSIX_VECT13_ADDR_LO 0x00d0 +#define ixPCIEMSIX_VECT13_ADDR_HI 0x00d4 +#define ixPCIEMSIX_VECT13_MSG_DATA 0x00d8 +#define ixPCIEMSIX_VECT13_CONTROL 0x00dc +#define ixPCIEMSIX_VECT14_ADDR_LO 0x00e0 +#define ixPCIEMSIX_VECT14_ADDR_HI 0x00e4 +#define ixPCIEMSIX_VECT14_MSG_DATA 0x00e8 +#define ixPCIEMSIX_VECT14_CONTROL 0x00ec +#define ixPCIEMSIX_VECT15_ADDR_LO 0x00f0 +#define ixPCIEMSIX_VECT15_ADDR_HI 0x00f4 +#define ixPCIEMSIX_VECT15_MSG_DATA 0x00f8 +#define ixPCIEMSIX_VECT15_CONTROL 0x00fc +#define ixPCIEMSIX_VECT16_ADDR_LO 0x0100 +#define ixPCIEMSIX_VECT16_ADDR_HI 0x0104 +#define ixPCIEMSIX_VECT16_MSG_DATA 0x0108 +#define ixPCIEMSIX_VECT16_CONTROL 0x010c +#define ixPCIEMSIX_VECT17_ADDR_LO 0x0110 +#define ixPCIEMSIX_VECT17_ADDR_HI 0x0114 +#define ixPCIEMSIX_VECT17_MSG_DATA 0x0118 +#define ixPCIEMSIX_VECT17_CONTROL 0x011c +#define ixPCIEMSIX_VECT18_ADDR_LO 0x0120 +#define ixPCIEMSIX_VECT18_ADDR_HI 0x0124 +#define ixPCIEMSIX_VECT18_MSG_DATA 0x0128 +#define ixPCIEMSIX_VECT18_CONTROL 0x012c +#define ixPCIEMSIX_VECT19_ADDR_LO 0x0130 +#define ixPCIEMSIX_VECT19_ADDR_HI 0x0134 +#define ixPCIEMSIX_VECT19_MSG_DATA 0x0138 +#define ixPCIEMSIX_VECT19_CONTROL 0x013c +#define ixPCIEMSIX_VECT20_ADDR_LO 0x0140 +#define ixPCIEMSIX_VECT20_ADDR_HI 0x0144 +#define ixPCIEMSIX_VECT20_MSG_DATA 0x0148 +#define ixPCIEMSIX_VECT20_CONTROL 0x014c +#define ixPCIEMSIX_VECT21_ADDR_LO 0x0150 +#define ixPCIEMSIX_VECT21_ADDR_HI 0x0154 +#define ixPCIEMSIX_VECT21_MSG_DATA 0x0158 +#define ixPCIEMSIX_VECT21_CONTROL 0x015c +#define ixPCIEMSIX_VECT22_ADDR_LO 0x0160 +#define ixPCIEMSIX_VECT22_ADDR_HI 0x0164 +#define ixPCIEMSIX_VECT22_MSG_DATA 0x0168 +#define ixPCIEMSIX_VECT22_CONTROL 0x016c +#define ixPCIEMSIX_VECT23_ADDR_LO 0x0170 +#define ixPCIEMSIX_VECT23_ADDR_HI 0x0174 +#define ixPCIEMSIX_VECT23_MSG_DATA 0x0178 +#define ixPCIEMSIX_VECT23_CONTROL 0x017c +#define ixPCIEMSIX_VECT24_ADDR_LO 0x0180 +#define ixPCIEMSIX_VECT24_ADDR_HI 0x0184 +#define ixPCIEMSIX_VECT24_MSG_DATA 0x0188 +#define ixPCIEMSIX_VECT24_CONTROL 0x018c +#define ixPCIEMSIX_VECT25_ADDR_LO 0x0190 +#define ixPCIEMSIX_VECT25_ADDR_HI 0x0194 +#define ixPCIEMSIX_VECT25_MSG_DATA 0x0198 +#define ixPCIEMSIX_VECT25_CONTROL 0x019c +#define ixPCIEMSIX_VECT26_ADDR_LO 0x01a0 +#define ixPCIEMSIX_VECT26_ADDR_HI 0x01a4 +#define ixPCIEMSIX_VECT26_MSG_DATA 0x01a8 +#define ixPCIEMSIX_VECT26_CONTROL 0x01ac +#define ixPCIEMSIX_VECT27_ADDR_LO 0x01b0 +#define ixPCIEMSIX_VECT27_ADDR_HI 0x01b4 +#define ixPCIEMSIX_VECT27_MSG_DATA 0x01b8 +#define ixPCIEMSIX_VECT27_CONTROL 0x01bc +#define ixPCIEMSIX_VECT28_ADDR_LO 0x01c0 +#define ixPCIEMSIX_VECT28_ADDR_HI 0x01c4 +#define ixPCIEMSIX_VECT28_MSG_DATA 0x01c8 +#define ixPCIEMSIX_VECT28_CONTROL 0x01cc +#define ixPCIEMSIX_VECT29_ADDR_LO 0x01d0 +#define ixPCIEMSIX_VECT29_ADDR_HI 0x01d4 +#define ixPCIEMSIX_VECT29_MSG_DATA 0x01d8 +#define ixPCIEMSIX_VECT29_CONTROL 0x01dc +#define ixPCIEMSIX_VECT30_ADDR_LO 0x01e0 +#define ixPCIEMSIX_VECT30_ADDR_HI 0x01e4 +#define ixPCIEMSIX_VECT30_MSG_DATA 0x01e8 +#define ixPCIEMSIX_VECT30_CONTROL 0x01ec +#define ixPCIEMSIX_VECT31_ADDR_LO 0x01f0 +#define ixPCIEMSIX_VECT31_ADDR_HI 0x01f4 +#define ixPCIEMSIX_VECT31_MSG_DATA 0x01f8 +#define ixPCIEMSIX_VECT31_CONTROL 0x01fc // addressBlock: pciemsix_amdgfx_MSIXPDEC // base address: 0x10171000 -#define ixPCIEMSIX_PBA 0x0000 +#define ixPCIEMSIX_PBA 0x0000 // addressBlock: syshub_mmreg_ind_syshubind // base address: 0x0 -#define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK 0x10000 // duplicate -#define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL2_SOCCLK 0x10004 // duplicate -#define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK 0x10008 // duplicate -#define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK 0x1000c // duplicate -#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL 0x10010 // duplicate -#define ixSYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL 0x10014 // duplicate -#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL 0x10018 // duplicate -#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL 0x1001c // duplicate -#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL 0x10020 // duplicate -#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL 0x10024 // duplicate -#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL 0x10028 // duplicate -#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL 0x1002c // duplicate -#define ixSYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL 0x10030 // duplicate -#define ixSYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL 0x10034 // duplicate -#define ixSYSHUBMMREGIND_SYSHUB_CG_CNTL 0x10300 // duplicate -#define ixSYSHUBMMREGIND_SYSHUB_TRANS_IDLE 0x10308 // duplicate -#define ixSYSHUBMMREGIND_SYSHUB_HP_TIMER 0x1030c // duplicate -#define ixSYSHUBMMREGIND_SYSHUB_SCRATCH 0x10f00 // duplicate -#define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK 0x11000 // duplicate -#define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL2_SHUBCLK 0x11004 // duplicate -#define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK 0x11008 // duplicate -#define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK 0x1100c // duplicate -#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL 0x11010 // duplicate -#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL 0x11014 // duplicate -#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL 0x11018 // duplicate -#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL 0x1101c // duplicate -#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL 0x11020 // duplicate -#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL 0x11024 // duplicate -#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL 0x11028 // duplicate -#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL 0x1102c // duplicate -#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL 0x11030 // duplicate -#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL 0x11034 // duplicate -#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL 0x11038 // duplicate -#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL 0x1103c // duplicate +#define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK 0x10000 // duplicate +#define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL2_SOCCLK 0x10004 // duplicate +#define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK 0x10008 // duplicate +#define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK 0x1000c // duplicate +#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL 0x10010 // duplicate +#define ixSYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL 0x10014 // duplicate +#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL 0x10018 // duplicate +#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL 0x1001c // duplicate +#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL 0x10020 // duplicate +#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL 0x10024 // duplicate +#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL 0x10028 // duplicate +#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL 0x1002c // duplicate +#define ixSYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL 0x10030 // duplicate +#define ixSYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL 0x10034 // duplicate +#define ixSYSHUBMMREGIND_SYSHUB_CG_CNTL 0x10300 // duplicate +#define ixSYSHUBMMREGIND_SYSHUB_TRANS_IDLE 0x10308 // duplicate +#define ixSYSHUBMMREGIND_SYSHUB_HP_TIMER 0x1030c // duplicate +#define ixSYSHUBMMREGIND_SYSHUB_SCRATCH 0x10f00 // duplicate +#define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK 0x11000 // duplicate +#define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL2_SHUBCLK 0x11004 // duplicate +#define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK 0x11008 // duplicate +#define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK 0x1100c // duplicate +#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL 0x11010 // duplicate +#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL 0x11014 // duplicate +#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL 0x11018 // duplicate +#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL 0x1101c // duplicate +#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL 0x11020 // duplicate +#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL 0x11024 // duplicate +#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL 0x11028 // duplicate +#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL 0x1102c // duplicate +#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL 0x11030 // duplicate +#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL 0x11034 // duplicate +#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL 0x11038 // duplicate +#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL 0x1103c // duplicate #endif diff --git a/sys/dev/pci/drm/amd/include/atomfirmware.h b/sys/dev/pci/drm/amd/include/atomfirmware.h index bbe1337a8..c26a2801b 100644 --- a/sys/dev/pci/drm/amd/include/atomfirmware.h +++ b/sys/dev/pci/drm/amd/include/atomfirmware.h @@ -1,5 +1,5 @@ /****************************************************************************\ -* +* * File Name atomfirmware.h * Project This is an interface header file between atombios and OS GPU drivers for SoC15 products * @@ -7,7 +7,7 @@ * * Copyright 2014 Advanced Micro Devices, Inc. * -* Permission is hereby granted, free of charge, to any person obtaining a copy of this software +* Permission is hereby granted, free of charge, to any person obtaining a copy of this software * and associated documentation files (the "Software"), to deal in the Software without restriction, * including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, @@ -49,7 +49,7 @@ enum atom_bios_header_version_def{ typedef unsigned short uint16_t; #endif - #ifndef uint8_t + #ifndef uint8_t typedef unsigned char uint8_t; #endif #endif @@ -203,7 +203,7 @@ enum atom_dp_vs_preemph_def{ /* enum atom_string_def{ -asic_bus_type_pcie_string = "PCI_EXPRESS", +asic_bus_type_pcie_string = "PCI_EXPRESS", atom_fire_gl_string = "FGL", atom_bios_string = "ATOM" }; @@ -222,26 +222,26 @@ enum atombios_image_offset{ OFFSET_TO_VBIOS_DATE = 0x50, }; -/**************************************************************************** +/**************************************************************************** * Common header for all tables (Data table, Command function). -* Every table pointed in _ATOM_MASTER_DATA_TABLE has this common header. +* Every table pointed in _ATOM_MASTER_DATA_TABLE has this common header. * And the pointer actually points to this header. -****************************************************************************/ +****************************************************************************/ struct atom_common_table_header { uint16_t structuresize; - uint8_t format_revision; //mainly used for a hw function, when the parser is not backward compatible - uint8_t content_revision; //change it when a data table has a structure change, or a hw function has a input/output parameter change + uint8_t format_revision; //mainly used for a hw function, when the parser is not backward compatible + uint8_t content_revision; //change it when a data table has a structure change, or a hw function has a input/output parameter change }; -/**************************************************************************** +/**************************************************************************** * Structure stores the ROM header. -****************************************************************************/ +****************************************************************************/ struct atom_rom_header_v2_2 { struct atom_common_table_header table_header; - uint8_t atom_bios_string[4]; //enum atom_string_def atom_bios_string; //Signature to distinguish between Atombios and non-atombios, + uint8_t atom_bios_string[4]; //enum atom_string_def atom_bios_string; //Signature to distinguish between Atombios and non-atombios, uint16_t bios_segment_address; uint16_t protectedmodeoffset; uint16_t configfilenameoffset; @@ -262,33 +262,33 @@ struct atom_rom_header_v2_2 /*==============================hw function portion======================================================================*/ -/**************************************************************************** +/**************************************************************************** * Structures used in Command.mtb, each function name is not given here since those function could change from time to time * The real functionality of each function is associated with the parameter structure version when defined * For all internal cmd function definitions, please reference to atomstruct.h -****************************************************************************/ +****************************************************************************/ struct atom_master_list_of_command_functions_v2_1{ uint16_t asic_init; //Function uint16_t cmd_function1; //used as an internal one uint16_t cmd_function2; //used as an internal one uint16_t cmd_function3; //used as an internal one - uint16_t digxencodercontrol; //Function + uint16_t digxencodercontrol; //Function uint16_t cmd_function5; //used as an internal one - uint16_t cmd_function6; //used as an internal one + uint16_t cmd_function6; //used as an internal one uint16_t cmd_function7; //used as an internal one uint16_t cmd_function8; //used as an internal one uint16_t cmd_function9; //used as an internal one uint16_t setengineclock; //Function uint16_t setmemoryclock; //Function uint16_t setpixelclock; //Function - uint16_t enabledisppowergating; //Function - uint16_t cmd_function14; //used as an internal one + uint16_t enabledisppowergating; //Function + uint16_t cmd_function14; //used as an internal one uint16_t cmd_function15; //used as an internal one uint16_t cmd_function16; //used as an internal one uint16_t cmd_function17; //used as an internal one uint16_t cmd_function18; //used as an internal one - uint16_t cmd_function19; //used as an internal one - uint16_t cmd_function20; //used as an internal one + uint16_t cmd_function19; //used as an internal one + uint16_t cmd_function20; //used as an internal one uint16_t cmd_function21; //used as an internal one uint16_t cmd_function22; //used as an internal one uint16_t cmd_function23; //used as an internal one @@ -315,20 +315,20 @@ struct atom_master_list_of_command_functions_v2_1{ uint16_t cmd_function44; //used as an internal one uint16_t cmd_function45; //used as an internal one uint16_t setdceclock; //Function - uint16_t getmemoryclock; //Function - uint16_t getengineclock; //Function + uint16_t getmemoryclock; //Function + uint16_t getengineclock; //Function uint16_t setcrtc_usingdtdtiming; //Function - uint16_t externalencodercontrol; //Function + uint16_t externalencodercontrol; //Function uint16_t cmd_function51; //used as an internal one uint16_t cmd_function52; //used as an internal one uint16_t cmd_function53; //used as an internal one - uint16_t processi2cchanneltransaction;//Function + uint16_t processi2cchanneltransaction;//Function uint16_t cmd_function55; //used as an internal one uint16_t cmd_function56; //used as an internal one uint16_t cmd_function57; //used as an internal one uint16_t cmd_function58; //used as an internal one uint16_t cmd_function59; //used as an internal one - uint16_t computegpuclockparam; //Function + uint16_t computegpuclockparam; //Function uint16_t cmd_function61; //used as an internal one uint16_t cmd_function62; //used as an internal one uint16_t dynamicmemorysettings; //Function function @@ -338,7 +338,7 @@ struct atom_master_list_of_command_functions_v2_1{ uint16_t setvoltage; //Function uint16_t cmd_function68; //used as an internal one uint16_t readefusevalue; //Function - uint16_t cmd_function70; //used as an internal one + uint16_t cmd_function70; //used as an internal one uint16_t cmd_function71; //used as an internal one uint16_t cmd_function72; //used as an internal one uint16_t cmd_function73; //used as an internal one @@ -357,26 +357,26 @@ struct atom_master_command_function_v2_1 struct atom_master_list_of_command_functions_v2_1 listofcmdfunctions; }; -/**************************************************************************** +/**************************************************************************** * Structures used in every command function -****************************************************************************/ +****************************************************************************/ struct atom_function_attribute { - uint16_t ws_in_bytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), - uint16_t ps_in_bytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), + uint16_t ws_in_bytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), + uint16_t ps_in_bytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), uint16_t updated_by_util:1; //[15]=flag to indicate the function is updated by util }; -/**************************************************************************** +/**************************************************************************** * Common header for all hw functions. -* Every function pointed by _master_list_of_hw_function has this common header. +* Every function pointed by _master_list_of_hw_function has this common header. * And the pointer actually points to this header. -****************************************************************************/ +****************************************************************************/ struct atom_rom_hw_function_header { struct atom_common_table_header func_header; - struct atom_function_attribute func_attrib; + struct atom_function_attribute func_attrib; }; @@ -387,25 +387,25 @@ struct atom_rom_hw_function_header ****************************************************************************/ struct atom_master_list_of_data_tables_v2_1{ uint16_t utilitypipeline; /* Offest for the utility to get parser info,Don't change this position!*/ - uint16_t multimedia_info; + uint16_t multimedia_info; uint16_t smc_dpm_info; - uint16_t sw_datatable3; + uint16_t sw_datatable3; uint16_t firmwareinfo; /* Shared by various SW components */ uint16_t sw_datatable5; uint16_t lcd_info; /* Shared by various SW components */ uint16_t sw_datatable7; - uint16_t smu_info; + uint16_t smu_info; uint16_t sw_datatable9; - uint16_t sw_datatable10; + uint16_t sw_datatable10; uint16_t vram_usagebyfirmware; /* Shared by various SW components */ uint16_t gpio_pin_lut; /* Shared by various SW components */ - uint16_t sw_datatable13; + uint16_t sw_datatable13; uint16_t gfx_info; uint16_t powerplayinfo; /* Shared by various SW components */ - uint16_t sw_datatable16; + uint16_t sw_datatable16; uint16_t sw_datatable17; uint16_t sw_datatable18; - uint16_t sw_datatable19; + uint16_t sw_datatable19; uint16_t sw_datatable20; uint16_t sw_datatable21; uint16_t displayobjectinfo; /* Shared by various SW components */ @@ -425,7 +425,7 @@ struct atom_master_list_of_data_tables_v2_1{ struct atom_master_data_table_v2_1 -{ +{ struct atom_common_table_header table_header; struct atom_master_list_of_data_tables_v2_1 listOfdatatables; }; @@ -468,7 +468,7 @@ enum atom_dtd_format_modemiscinfo{ */ -/* +/* *************************************************************************** Data Table firmwareinfo structure *************************************************************************** @@ -482,12 +482,12 @@ struct atom_firmware_info_v3_1 uint32_t bootup_mclk_in10khz; uint32_t firmware_capability; // enum atombios_firmware_capability uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ - uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address + uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address uint16_t bootup_vddc_mv; - uint16_t bootup_vddci_mv; + uint16_t bootup_vddci_mv; uint16_t bootup_mvddc_mv; uint16_t bootup_vddgfx_mv; - uint8_t mem_module_id; + uint8_t mem_module_id; uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ uint8_t reserved1[2]; uint32_t mc_baseaddr_high; @@ -609,7 +609,7 @@ struct atom_firmware_info_v3_4 { uint32_t reserved[2]; }; -/* +/* *************************************************************************** Data Table lcd_info structure *************************************************************************** @@ -652,13 +652,13 @@ enum atom_lcd_info_panel_misc{ //uceDPToLVDSRxId enum atom_lcd_info_dptolvds_rx_id { - eDP_TO_LVDS_RX_DISABLE = 0x00, // no eDP->LVDS translator chip + eDP_TO_LVDS_RX_DISABLE = 0x00, // no eDP->LVDS translator chip eDP_TO_LVDS_COMMON_ID = 0x01, // common eDP->LVDS translator chip without AMD SW init eDP_TO_LVDS_REALTEK_ID = 0x02, // Realtek tansaltor which require AMD SW init }; - -/* + +/* *************************************************************************** Data Table gpio_pin_lut structure *************************************************************************** @@ -676,7 +676,7 @@ struct atom_gpio_pin_assignment /* atom_gpio_pin_assignment.gpio_id definition */ enum atom_gpio_pin_assignment_gpio_id { I2C_HW_LANE_MUX =0x0f, /* only valid when bit7=1 */ - I2C_HW_ENGINE_ID_MASK =0x70, /* only valid when bit7=1 */ + I2C_HW_ENGINE_ID_MASK =0x70, /* only valid when bit7=1 */ I2C_HW_CAP =0x80, /*only when the I2C_HW_CAP is set, the pin ID is assigned to an I2C pin pair, otherwise, it's an generic GPIO pin */ /* gpio_id pre-define id for multiple usage */ @@ -765,7 +765,7 @@ struct vram_usagebyfirmware_v2_2 { uint32_t reserved32[7]; }; -/* +/* *************************************************************************** Data Table displayobjectinfo structure *************************************************************************** @@ -796,14 +796,14 @@ struct atom_common_record_header struct atom_i2c_record { struct atom_common_record_header record_header; //record_type = ATOM_I2C_RECORD_TYPE - uint8_t i2c_id; + uint8_t i2c_id; uint8_t i2c_slave_addr; //The slave address, it's 0 when the record is attached to connector for DDC }; struct atom_hpd_int_record { struct atom_common_record_header record_header; //record_type = ATOM_HPD_INT_RECORD_TYPE - uint8_t pin_id; //Corresponding block in GPIO_PIN_INFO table gives the pin info + uint8_t pin_id; //Corresponding block in GPIO_PIN_INFO table gives the pin info uint8_t plugin_pin_state; }; @@ -824,10 +824,10 @@ struct atom_connector_speed_record { enum atom_encoder_caps_def { ATOM_ENCODER_CAP_RECORD_HBR2 =0x01, // DP1.2 HBR2 is supported by HW encoder, it is retired in NI. the real meaning from SI is MST_EN - ATOM_ENCODER_CAP_RECORD_MST_EN =0x01, // from SI, this bit means DP MST is enable or not. - ATOM_ENCODER_CAP_RECORD_HBR2_EN =0x02, // DP1.2 HBR2 setting is qualified and HBR2 can be enabled - ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN =0x04, // HDMI2.0 6Gbps enable or not. - ATOM_ENCODER_CAP_RECORD_HBR3_EN =0x08, // DP1.3 HBR3 is supported by board. + ATOM_ENCODER_CAP_RECORD_MST_EN =0x01, // from SI, this bit means DP MST is enable or not. + ATOM_ENCODER_CAP_RECORD_HBR2_EN =0x02, // DP1.2 HBR2 setting is qualified and HBR2 can be enabled + ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN =0x04, // HDMI2.0 6Gbps enable or not. + ATOM_ENCODER_CAP_RECORD_HBR3_EN =0x08, // DP1.3 HBR3 is supported by board. ATOM_ENCODER_CAP_RECORD_DP2 =0x10, // DP2 is supported by ASIC/board. ATOM_ENCODER_CAP_RECORD_UHBR10_EN =0x20, // DP2.0 UHBR10 settings is supported by board ATOM_ENCODER_CAP_RECORD_UHBR13_5_EN =0x40, // DP2.0 UHBR13.5 settings is supported by board @@ -844,13 +844,13 @@ struct atom_encoder_caps_record enum atom_connector_caps_def { ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY = 0x01, //a cap bit to indicate that this non-embedded display connector is an internal display - ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL = 0x02, //a cap bit to indicate that this internal display requires BL control from GPU, refers to lcd_info for BL PWM freq + ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL = 0x02, //a cap bit to indicate that this internal display requires BL control from GPU, refers to lcd_info for BL PWM freq }; struct atom_disp_connector_caps_record { struct atom_common_record_header record_header; - uint32_t connectcaps; + uint32_t connectcaps; }; //The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually @@ -868,21 +868,21 @@ struct atom_object_gpio_cntl_record struct atom_gpio_pin_control_pair gpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins }; -//Definitions for GPIO pin state +//Definitions for GPIO pin state enum atom_gpio_pin_control_pinstate_def { GPIO_PIN_TYPE_INPUT = 0x00, GPIO_PIN_TYPE_OUTPUT = 0x10, GPIO_PIN_TYPE_HW_CONTROL = 0x20, -//For GPIO_PIN_TYPE_OUTPUT the following is defined +//For GPIO_PIN_TYPE_OUTPUT the following is defined GPIO_PIN_OUTPUT_STATE_MASK = 0x01, GPIO_PIN_OUTPUT_STATE_SHIFT = 0, GPIO_PIN_STATE_ACTIVE_LOW = 0x0, GPIO_PIN_STATE_ACTIVE_HIGH = 0x1, }; -// Indexes to GPIO array in GLSync record +// Indexes to GPIO array in GLSync record // GLSync record is for Frame Lock/Gen Lock feature. enum atom_glsync_record_gpio_index_def { @@ -902,7 +902,7 @@ enum atom_glsync_record_gpio_index_def struct atom_connector_hpdpin_lut_record //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE { struct atom_common_record_header record_header; - uint8_t hpd_pin_map[8]; + uint8_t hpd_pin_map[8]; }; struct atom_connector_auxddc_lut_record //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE @@ -917,7 +917,7 @@ struct atom_connector_forced_tmds_cap_record // override TMDS capability on this connector when it operate in TMDS mode. usMaxTmdsClkRate = max TMDS Clock in Mhz/2.5 uint8_t maxtmdsclkrate_in2_5mhz; uint8_t reserved; -}; +}; struct atom_connector_layout_info { @@ -930,7 +930,7 @@ struct atom_connector_layout_info enum atom_connector_layout_info_connector_type_def { CONNECTOR_TYPE_DVI_D = 1, - + CONNECTOR_TYPE_HDMI = 4, CONNECTOR_TYPE_DISPLAY_PORT = 5, CONNECTOR_TYPE_MINI_DISPLAY_PORT = 6, @@ -981,7 +981,7 @@ struct atom_display_object_path_v2 uint16_t extencoderobjid; //2nd encoder after the first encoder, from the connector point of view; uint16_t encoder_recordoffset; uint16_t extencoder_recordoffset; - uint16_t device_tag; //a supported device vector, each display path starts with this.the paths are enumerated in the way of priority, a path appears first + uint16_t device_tag; //a supported device vector, each display path starts with this.the paths are enumerated in the way of priority, a path appears first uint8_t priority_id; uint8_t reserved; }; @@ -1018,7 +1018,7 @@ struct display_object_info_table_v1_5 { struct atom_display_object_path_v3 display_path[8]; }; -/* +/* *************************************************************************** Data Table dce_info structure *************************************************************************** @@ -1031,18 +1031,18 @@ struct atom_display_controller_info_v4_1 uint16_t dce_refclk_10khz; uint16_t i2c_engine_refclk_10khz; uint16_t dvi_ss_percentage; // in unit of 0.001% - uint16_t dvi_ss_rate_10hz; + uint16_t dvi_ss_rate_10hz; uint16_t hdmi_ss_percentage; // in unit of 0.001% uint16_t hdmi_ss_rate_10hz; uint16_t dp_ss_percentage; // in unit of 0.001% uint16_t dp_ss_rate_10hz; uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode - uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode + uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode uint8_t ss_reserved; uint8_t hardcode_mode_num; // a hardcode mode number defined in StandardVESA_TimingTable when a CRT or DFP EDID is not available uint8_t reserved1[3]; - uint16_t dpphy_refclk_10khz; + uint16_t dpphy_refclk_10khz; uint16_t reserved2; uint8_t dceip_min_ver; uint8_t dceip_max_ver; @@ -1058,11 +1058,11 @@ struct atom_display_controller_info_v4_1 struct atom_display_controller_info_v4_2 { struct atom_common_table_header table_header; - uint32_t display_caps; + uint32_t display_caps; uint32_t bootup_dispclk_10khz; uint16_t dce_refclk_10khz; uint16_t i2c_engine_refclk_10khz; - uint16_t dvi_ss_percentage; // in unit of 0.001% + uint16_t dvi_ss_percentage; // in unit of 0.001% uint16_t dvi_ss_rate_10hz; uint16_t hdmi_ss_percentage; // in unit of 0.001% uint16_t hdmi_ss_rate_10hz; @@ -1070,13 +1070,13 @@ struct atom_display_controller_info_v4_2 uint16_t dp_ss_rate_10hz; uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode - uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode + uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode uint8_t ss_reserved; uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable - uint16_t dpphy_refclk_10khz; + uint16_t dpphy_refclk_10khz; uint16_t reserved2; uint8_t dcnip_min_ver; uint8_t dcnip_max_ver; @@ -1246,15 +1246,15 @@ struct atom_display_controller_info_v4_5 uint32_t reserved[26]; }; -/* +/* *************************************************************************** Data Table ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO structure *************************************************************************** */ struct atom_ext_display_path { - uint16_t device_tag; //A bit vector to show what devices are supported - uint16_t device_acpi_enum; //16bit device ACPI id. + uint16_t device_tag; //A bit vector to show what devices are supported + uint16_t device_acpi_enum; //16bit device ACPI id. uint16_t connectorobjid; //A physical connector for displays to plug in, using object connector definitions uint8_t auxddclut_index; //An index into external AUX/DDC channel LUT uint8_t hpdlut_index; //An index into external HPD pin LUT @@ -1262,7 +1262,7 @@ struct atom_ext_display_path uint8_t channelmapping; // if ucChannelMapping=0, using default one to one mapping uint8_t chpninvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted uint16_t caps; - uint16_t reserved; + uint16_t reserved; }; //usCaps @@ -1280,7 +1280,7 @@ struct atom_external_display_connection_info struct atom_common_table_header table_header; uint8_t guid[16]; // a GUID is a 16 byte long string struct atom_ext_display_path path[7]; // total of fixed 7 entries. - uint8_t checksum; // a simple Checksum of the sum of whole structure equal to 0x0. + uint8_t checksum; // a simple Checksum of the sum of whole structure equal to 0x0. uint8_t stereopinid; // use for eDP panel uint8_t remotedisplayconfig; uint8_t edptolvdsrxid; @@ -1288,7 +1288,7 @@ struct atom_external_display_connection_info uint8_t reserved[3]; // for potential expansion }; -/* +/* *************************************************************************** Data Table integratedsysteminfo structure *************************************************************************** @@ -1332,7 +1332,7 @@ struct atom_14nm_dpphy_dvihdmi_tuningset { uint32_t max_symclk_in10khz; uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode - uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf + uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset @@ -1348,16 +1348,16 @@ struct atom_14nm_dpphy_dp_setting{ }; struct atom_14nm_dpphy_dp_tuningset{ - uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf + uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf uint8_t version; uint16_t table_size; // size of atom_14nm_dpphy_dp_tuningset uint16_t reserved; struct atom_14nm_dpphy_dp_setting dptuning[10]; }; -struct atom_14nm_dig_transmitter_info_header_v4_0{ - struct atom_common_table_header table_header; - uint16_t pcie_phy_tmds_hdmi_macro_settings_offset; // offset of PCIEPhyTMDSHDMIMacroSettingsTbl +struct atom_14nm_dig_transmitter_info_header_v4_0{ + struct atom_common_table_header table_header; + uint16_t pcie_phy_tmds_hdmi_macro_settings_offset; // offset of PCIEPhyTMDSHDMIMacroSettingsTbl uint16_t uniphy_vs_emph_lookup_table_offset; // offset of UniphyVSEmphLookUpTbl uint16_t uniphy_xbar_settings_table_offset; // offset of UniphyXbarSettingsTbl }; @@ -1371,14 +1371,14 @@ struct atom_14nm_combphy_tmds_vs_set uint8_t common_seldeemph60__deemph_6db_4_val; uint8_t cmd_bus_global_for_tx_lane0__boostadj_val ; uint8_t common_zcalcode_ctrl__tx_driver_fifty_ohms_val; - uint8_t margin_deemph_lane0__deemph_sel_val; + uint8_t margin_deemph_lane0__deemph_sel_val; }; struct atom_DCN_dpphy_dvihdmi_tuningset { uint32_t max_symclk_in10khz; uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode - uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf + uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf uint8_t tx_eq_main; // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN) uint8_t tx_eq_pre; // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE) uint8_t tx_eq_post; // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST) @@ -1396,7 +1396,7 @@ struct atom_DCN_dpphy_dp_setting{ }; struct atom_DCN_dpphy_dp_tuningset{ - uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf + uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf uint8_t version; uint16_t table_size; // size of atom_14nm_dpphy_dp_setting uint16_t reserved; @@ -1420,10 +1420,10 @@ struct atom_integrated_system_info_v1_11 { struct atom_common_table_header table_header; uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def - uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def - uint32_t system_config; + uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def + uint32_t system_config; uint32_t cpucapinfo; - uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1% + uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1% uint16_t gpuclk_ss_type; uint16_t lvds_ss_percentage; //unit of 0.001%, 1000 mean 1% uint16_t lvds_ss_rate_10hz; @@ -1469,10 +1469,10 @@ struct atom_integrated_system_info_v1_12 { struct atom_common_table_header table_header; uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def - uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def - uint32_t system_config; + uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def + uint32_t system_config; uint32_t cpucapinfo; - uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1% + uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1% uint16_t gpuclk_ss_type; uint16_t lvds_ss_percentage; //unit of 0.001%, 1000 mean 1% uint16_t lvds_ss_rate_10hz; @@ -1502,7 +1502,7 @@ struct atom_integrated_system_info_v1_12 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK5_tuningset; struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK8_tuningset; struct atom_DCN_dpphy_dp_tuningset rbr_tuningset; // rbr 1.62G dp tuning set - struct atom_DCN_dpphy_dp_tuningset hbr3_tuningset; // HBR3 dp tuning set + struct atom_DCN_dpphy_dp_tuningset hbr3_tuningset; // HBR3 dp tuning set struct atom_camera_data camera_info; struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0 struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1 @@ -1641,7 +1641,7 @@ enum atom_sysinfo_dpphy_override_def{ ATOM_ENABLE_HDMI_TUNINGSET = 0x02, ATOM_ENABLE_HDMI6G_TUNINGSET = 0x04, ATOM_ENABLE_DP_TUNINGSET = 0x08, - ATOM_ENABLE_DP_HBR3_TUNINGSET = 0x10, + ATOM_ENABLE_DP_HBR3_TUNINGSET = 0x10, }; //lvds_misc @@ -1690,15 +1690,15 @@ enum atom_dmi_t17_mem_type_def{ }; -// this Table is used starting from NL/AM, used by SBIOS and pass the IntegratedSystemInfoTable/PowerPlayInfoTable/SystemCameraInfoTable +// this Table is used starting from NL/AM, used by SBIOS and pass the IntegratedSystemInfoTable/PowerPlayInfoTable/SystemCameraInfoTable struct atom_fusion_system_info_v4 { struct atom_integrated_system_info_v1_11 sysinfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition uint32_t powerplayinfo[256]; // Reserve 1024 bytes space for PowerPlayInfoTable -}; +}; -/* +/* *************************************************************************** Data Table gfx_info structure *************************************************************************** @@ -1719,10 +1719,10 @@ struct atom_gfx_info_v2_2 uint32_t regaddr_cp_dma_src_addr_hi; uint32_t regaddr_cp_dma_dst_addr; uint32_t regaddr_cp_dma_dst_addr_hi; - uint32_t regaddr_cp_dma_command; + uint32_t regaddr_cp_dma_command; uint32_t regaddr_cp_status; uint32_t regaddr_rlc_gpu_clock_32; - uint32_t rlc_gpu_timer_refclk; + uint32_t rlc_gpu_timer_refclk; }; struct atom_gfx_info_v2_3 { @@ -1859,7 +1859,7 @@ struct atom_gfx_info_v3_0 { uint32_t reserved[8]; }; -/* +/* *************************************************************************** Data Table smu_info structure *************************************************************************** @@ -1881,7 +1881,7 @@ struct atom_smu_info_v3_1 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid - uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event + uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid uint8_t fw_ctf_polarity; // GPIO polarity for CTF }; @@ -2491,8 +2491,8 @@ struct atom_smc_dpm_info_v4_5 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event - uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event - uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event + uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event + uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event uint8_t GthrGpio; // GPIO pin configured for GTHR Event uint8_t GthrPolarity; // replace GPIO polarity for GTHR @@ -2524,11 +2524,11 @@ struct atom_smc_dpm_info_v4_5 // Total board power uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power - uint16_t BoardPadding; + uint16_t BoardPadding; // Mvdd Svi2 Div Ratio Setting uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16) - + uint32_t BoardReserved[9]; }; @@ -2741,7 +2741,7 @@ struct atom_smc_dpm_info_v4_9 //uint32_t GamingClk[6]; // SECTION: I2C Control - struct smudpm_i2c_controller_config_v3 I2cControllers[16]; + struct smudpm_i2c_controller_config_v3 I2cControllers[16]; uint8_t GpioScl; // GPIO Number for SCL Line, used only for CKSVII2C1 uint8_t GpioSda; // GPIO Number for SDA Line, used only for CKSVII2C1 @@ -2771,21 +2771,21 @@ struct atom_smc_dpm_info_v4_9 uint16_t Mem0MaxCurrent; // in Amps uint8_t Mem0Offset; // in Amps uint8_t Padding_TelemetryMem0; - + uint16_t Mem1MaxCurrent; // in Amps uint8_t Mem1Offset; // in Amps uint8_t Padding_TelemetryMem1; uint32_t MvddRatio; // This is used for MVDD Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16) - + // SECTION: GPIO Settings uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event - uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event - uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event + uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event + uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event uint8_t GthrGpio; // GPIO pin configured for GTHR Event uint8_t GthrPolarity; // replace GPIO polarity for GTHR @@ -2800,7 +2800,7 @@ struct atom_smc_dpm_info_v4_9 uint8_t LedSpare1[2]; // SECTION: Clock Spread Spectrum - + // GFXCLK PLL Spread Spectrum uint8_t PllGfxclkSpreadEnabled; // on or off uint8_t PllGfxclkSpreadPercent; // Q4.4 @@ -2810,7 +2810,7 @@ struct atom_smc_dpm_info_v4_9 uint8_t DfllGfxclkSpreadEnabled; // on or off uint8_t DfllGfxclkSpreadPercent; // Q4.4 uint16_t DfllGfxclkSpreadFreq; // kHz - + // UCLK Spread Spectrum uint8_t UclkSpreadEnabled; // on or off uint8_t UclkSpreadPercent; // Q4.4 @@ -2820,17 +2820,17 @@ struct atom_smc_dpm_info_v4_9 uint8_t FclkSpreadEnabled; // on or off uint8_t FclkSpreadPercent; // Q4.4 uint16_t FclkSpreadFreq; // kHz - + // Section: Memory Config - uint32_t MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask. - + uint32_t MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask. + uint8_t DramBitWidth; // For DRAM use only. See Dram Bit width type defines uint8_t PaddingMem1[3]; // Section: Total Board Power uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power - uint16_t BoardPowerPadding; - + uint16_t BoardPowerPadding; + // SECTION: XGMI Training uint8_t XgmiLinkSpeed [4]; uint8_t XgmiLinkWidth [4]; @@ -2897,7 +2897,7 @@ struct atom_smc_dpm_info_v4_10 uint32_t reserved[16]; }; -/* +/* *************************************************************************** Data Table asic_profiling_info structure *************************************************************************** @@ -2905,8 +2905,8 @@ struct atom_smc_dpm_info_v4_10 struct atom_asic_profiling_info_v4_1 { struct atom_common_table_header table_header; - uint32_t maxvddc; - uint32_t minvddc; + uint32_t maxvddc; + uint32_t minvddc; uint32_t avfs_meannsigma_acontant0; uint32_t avfs_meannsigma_acontant1; uint32_t avfs_meannsigma_acontant2; @@ -2922,7 +2922,7 @@ struct atom_asic_profiling_info_v4_1 uint32_t avfsgb_fuse_table_cksoff_m1; uint32_t avfsgb_fuse_table_cksoff_m2; uint32_t avfsgb_fuse_table_cksoff_b; - uint32_t avfsgb_fuse_table_ckson_m1; + uint32_t avfsgb_fuse_table_ckson_m1; uint32_t avfsgb_fuse_table_ckson_m2; uint32_t avfsgb_fuse_table_ckson_b; uint16_t max_voltage_0_25mv; @@ -3011,7 +3011,7 @@ struct atom_asic_profiling_info_v4_2 { uint32_t acg_phyclk2gfxclk_c; }; -/* +/* *************************************************************************** Data Table multimedia_info structure *************************************************************************** @@ -3026,13 +3026,13 @@ struct atom_multimedia_info_v2_1 uint16_t uvd_enc_max_input_width_pixels; uint16_t uvd_enc_max_input_height_pixels; uint16_t vce_enc_max_input_width_pixels; - uint16_t vce_enc_max_input_height_pixels; + uint16_t vce_enc_max_input_height_pixels; uint32_t uvd_enc_max_bandwidth; // 16x16 pixels/sec, codec independent uint32_t vce_enc_max_bandwidth; // 16x16 pixels/sec, codec independent }; -/* +/* *************************************************************************** Data Table umc_info structure *************************************************************************** @@ -3116,7 +3116,7 @@ enum atom_umc_config1_def { UMC_CONFIG1__ENABLE_ECC_CAPABLE = 0x00010000, }; -/* +/* *************************************************************************** Data Table vram_info structure *************************************************************************** @@ -3134,12 +3134,12 @@ struct atom_vram_module_v9 { uint8_t channel_num; // Number of mem. channels supported in this module uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 - uint8_t tunningset_id; // MC phy registers set per. + uint8_t tunningset_id; // MC phy registers set per. uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) uint8_t hbm_ven_rev_id; // hbm_ven_rev_id uint8_t vram_rsd2; // reserved - char dram_pnstring[20]; // part number end with '0'. + char dram_pnstring[20]; // part number end with '0'. }; struct atom_vram_info_header_v2_3 { @@ -3234,12 +3234,12 @@ union atom_umc_reg_setting_id_config_access struct atom_umc_reg_setting_data_block{ union atom_umc_reg_setting_id_config_access block_id; - uint32_t u32umc_reg_data[1]; + uint32_t u32umc_reg_data[1]; }; struct atom_umc_init_reg_block{ uint16_t umc_reg_num; - uint16_t reserved; + uint16_t reserved; union atom_umc_register_addr_info_access umc_reg_list[1]; //for allocation purpose, the real number come from umc_reg_num; struct atom_umc_reg_setting_data_block umc_reg_setting_list[1]; }; @@ -3426,7 +3426,7 @@ struct atom_vram_info_header_v2_6 { uint8_t mc_phy_tile_num; struct atom_vram_module_v9 vram_module[16]; }; -/* +/* *************************************************************************** Data Table voltageobject_info structure *************************************************************************** @@ -3439,18 +3439,18 @@ struct atom_i2c_data_entry struct atom_voltage_object_header_v4{ uint8_t voltage_type; //enum atom_voltage_type - uint8_t voltage_mode; //enum atom_voltage_object_mode + uint8_t voltage_mode; //enum atom_voltage_object_mode uint16_t object_size; //Size of Object }; // atom_voltage_object_header_v4.voltage_mode -enum atom_voltage_object_mode +enum atom_voltage_object_mode { VOLTAGE_OBJ_GPIO_LUT = 0, //VOLTAGE and GPIO Lookup table ->atom_gpio_voltage_object_v4 VOLTAGE_OBJ_VR_I2C_INIT_SEQ = 3, //VOLTAGE REGULATOR INIT sequece through I2C -> atom_i2c_voltage_object_v4 VOLTAGE_OBJ_PHASE_LUT = 4, //Set Vregulator Phase lookup table ->atom_gpio_voltage_object_v4 VOLTAGE_OBJ_SVID2 = 7, //Indicate voltage control by SVID2 ->atom_svid2_voltage_object_v4 - VOLTAGE_OBJ_EVV = 8, + VOLTAGE_OBJ_EVV = 8, VOLTAGE_OBJ_MERGED_POWER = 9, }; @@ -3460,9 +3460,9 @@ struct atom_i2c_voltage_object_v4 uint8_t regulator_id; //Indicate Voltage Regulator Id uint8_t i2c_id; uint8_t i2c_slave_addr; - uint8_t i2c_control_offset; + uint8_t i2c_control_offset; uint8_t i2c_flag; // Bit0: 0 - One byte data; 1 - Two byte data - uint8_t i2c_speed; // =0, use default i2c speed, otherwise use it in unit of kHz. + uint8_t i2c_speed; // =0, use default i2c speed, otherwise use it in unit of kHz. uint8_t reserved[2]; struct atom_i2c_data_entry i2cdatalut[1]; // end with 0xff }; @@ -3484,10 +3484,10 @@ struct atom_voltage_gpio_map_lut struct atom_gpio_voltage_object_v4 { struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT - uint8_t gpio_control_id; // default is 0 which indicate control through CG VID mode + uint8_t gpio_control_id; // default is 0 which indicate control through CG VID mode uint8_t gpio_entry_num; // indiate the entry numbers of Votlage/Gpio value Look up table uint8_t phase_delay_us; // phase delay in unit of micro second - uint8_t reserved; + uint8_t reserved; uint32_t gpio_mask_val; // GPIO Mask value struct atom_voltage_gpio_map_lut voltage_gpio_lut[1]; }; @@ -3497,10 +3497,10 @@ struct atom_svid2_voltage_object_v4 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_SVID2 uint8_t loadline_psi1; // bit4:0= loadline setting ( Core Loadline trim and offset trim ), bit5=0:PSI1_L disable =1: PSI1_L enable uint8_t psi0_l_vid_thresd; // VR PSI0_L VID threshold - uint8_t psi0_enable; // + uint8_t psi0_enable; // uint8_t maxvstep; uint8_t telemetry_offset; - uint8_t telemetry_gain; + uint8_t telemetry_gain; uint16_t reserved1; }; @@ -3520,22 +3520,22 @@ union atom_voltage_object_v4{ struct atom_voltage_objects_info_v4_1 { - struct atom_common_table_header table_header; + struct atom_common_table_header table_header; union atom_voltage_object_v4 voltage_object[1]; //Info for Voltage control }; -/* +/* *************************************************************************** - All Command Function structure definition - *************************************************************************** -*/ + All Command Function structure definition + *************************************************************************** +*/ -/* +/* *************************************************************************** Structures used by asic_init - *************************************************************************** -*/ + *************************************************************************** +*/ struct asic_init_engine_parameters { @@ -3575,11 +3575,11 @@ enum atom_asic_init_mem_flag b3DRAM_SELF_REFRESH_EXIT =0x20, }; -/* +/* *************************************************************************** Structures used by setengineclock - *************************************************************************** -*/ + *************************************************************************** +*/ struct set_engine_clock_parameters_v2_1 { @@ -3602,22 +3602,22 @@ enum atom_set_engine_mem_clock_flag b3STORE_DPM_TRAINGING = 0x40, //Applicable to memory clock change,when set, it store specific DPM mode training result }; -/* +/* *************************************************************************** Structures used by getengineclock - *************************************************************************** -*/ + *************************************************************************** +*/ struct get_engine_clock_parameter { uint32_t sclk_10khz; // current engine speed in 10KHz unit uint32_t reserved; }; -/* +/* *************************************************************************** Structures used by setmemoryclock - *************************************************************************** -*/ + *************************************************************************** +*/ struct set_memory_clock_parameters_v2_1 { uint32_t mclkfreqin10khz:24; @@ -3632,11 +3632,11 @@ struct set_memory_clock_ps_allocation_v2_1 }; -/* +/* *************************************************************************** Structures used by getmemoryclock - *************************************************************************** -*/ + *************************************************************************** +*/ struct get_memory_clock_parameter { uint32_t mclk_10khz; // current engine speed in 10KHz unit @@ -3645,11 +3645,11 @@ struct get_memory_clock_parameter -/* +/* *************************************************************************** Structures used by setvoltage - *************************************************************************** -*/ + *************************************************************************** +*/ struct set_voltage_parameters_v1_4 { @@ -3673,14 +3673,14 @@ struct set_voltage_ps_allocation_v1_4 }; -/* +/* *************************************************************************** Structures used by computegpuclockparam - *************************************************************************** -*/ + *************************************************************************** +*/ //ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag -enum atom_gpu_clock_type +enum atom_gpu_clock_type { COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK =0x00, COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK =0x01, @@ -3689,7 +3689,7 @@ enum atom_gpu_clock_type struct compute_gpu_clock_input_parameter_v1_8 { - uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock + uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock uint32_t gpu_clock_type:8; //Input indicate clock type: enum atom_gpu_clock_type uint32_t reserved[5]; }; @@ -3697,7 +3697,7 @@ struct compute_gpu_clock_input_parameter_v1_8 struct compute_gpu_clock_output_parameter_v1_8 { - uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock + uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock uint32_t dfs_did:8; //return parameter: DFS divider which is used to program to register directly uint32_t pll_fb_mult; //Feedback Multiplier, bit 8:0 int, bit 15:12 post_div, bit 31:16 frac uint32_t pll_ss_fbsmult; // Spread FB Mult: bit 8:0 int, bit 31:16 frac @@ -3709,11 +3709,11 @@ struct compute_gpu_clock_output_parameter_v1_8 -/* +/* *************************************************************************** Structures used by ReadEfuseValue - *************************************************************************** -*/ + *************************************************************************** +*/ struct read_efuse_input_parameters_v3_1 { @@ -3730,20 +3730,20 @@ union read_efuse_value_parameters_v3_1 }; -/* +/* *************************************************************************** Structures used by getsmuclockinfo - *************************************************************************** -*/ + *************************************************************************** +*/ struct atom_get_smu_clock_info_parameters_v3_1 { - uint8_t syspll_id; // 0= syspll0, 1=syspll1, 2=syspll2 + uint8_t syspll_id; // 0= syspll0, 1=syspll1, 2=syspll2 uint8_t clk_id; // atom_smu9_syspll0_clock_id (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ ) uint8_t command; // enum of atom_get_smu_clock_info_command uint8_t dfsdid; // =0: get DFS DID from register, >0, give DFS divider, (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ ) }; -enum atom_get_smu_clock_info_command +enum atom_get_smu_clock_info_command { GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ = 0, GET_SMU_CLOCK_INFO_V3_1_GET_PLLVCO_FREQ = 1, @@ -3864,13 +3864,13 @@ struct atom_get_smu_clock_info_output_parameters_v3_1 -/* +/* *************************************************************************** Structures used by dynamicmemorysettings - *************************************************************************** -*/ + *************************************************************************** +*/ -enum atom_dynamic_memory_setting_command +enum atom_dynamic_memory_setting_command { COMPUTE_MEMORY_PLL_PARAM = 1, COMPUTE_ENGINE_PLL_PARAM = 2, @@ -3902,11 +3902,11 @@ union dynamic_memory_settings_parameters_v2_1 -/* +/* *************************************************************************** Structures used by memorytraining - *************************************************************************** -*/ + *************************************************************************** +*/ enum atom_umc6_0_ucode_function_call_enum_id { @@ -3924,24 +3924,24 @@ struct memory_training_parameters_v2_1 }; -/* +/* *************************************************************************** Structures used by setpixelclock - *************************************************************************** -*/ + *************************************************************************** +*/ struct set_pixel_clock_parameter_v1_7 { - uint32_t pixclk_100hz; // target the pixel clock to drive the CRTC timing in unit of 100Hz. + uint32_t pixclk_100hz; // target the pixel clock to drive the CRTC timing in unit of 100Hz. uint8_t pll_id; // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0 - uint8_t encoderobjid; // ASIC encoder id defined in objectId.h, - // indicate which graphic encoder will be used. - uint8_t encoder_mode; // Encoder mode: + uint8_t encoderobjid; // ASIC encoder id defined in objectId.h, + // indicate which graphic encoder will be used. + uint8_t encoder_mode; // Encoder mode: uint8_t miscinfo; // enum atom_set_pixel_clock_v1_7_misc_info uint8_t crtc_id; // enum of atom_crtc_def uint8_t deep_color_ratio; // HDMI panel bit depth: enum atom_set_pixel_clock_v1_7_deepcolor_ratio - uint8_t reserved1[2]; + uint8_t reserved1[2]; uint32_t reserved2; }; @@ -3956,7 +3956,7 @@ enum atom_set_pixel_clock_v1_7_misc_info PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN = 0x00, PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_PCIE = 0x10, PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK = 0x20, - PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_REFPAD = 0x30, + PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_REFPAD = 0x30, PIXEL_CLOCK_V7_MISC_ATOMIC_UPDATE = 0x40, PIXEL_CLOCK_V7_MISC_FORCE_SS_DIS = 0x80, }; @@ -3964,22 +3964,22 @@ enum atom_set_pixel_clock_v1_7_misc_info /* deep_color_ratio */ enum atom_set_pixel_clock_v1_7_deepcolor_ratio { - PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO - PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4 - PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2 - PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1 + PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO + PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4 + PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2 + PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1 }; -/* +/* *************************************************************************** Structures used by setdceclock - *************************************************************************** -*/ + *************************************************************************** +*/ -// SetDCEClock input parameter for DCE11.2( ELM and BF ) and above +// SetDCEClock input parameter for DCE11.2( ELM and BF ) and above struct set_dce_clock_parameters_v2_1 { - uint32_t dceclk_10khz; // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency. + uint32_t dceclk_10khz; // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency. uint8_t dceclktype; // =0: DISPCLK =1: DPREFCLK =2: PIXCLK uint8_t dceclksrc; // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK or ATOM_COMBOPHY_PLLx uint8_t dceclkflag; // Bit [1:0] = PPLL ref clock source ( when ucDCEClkSrc= ATOM_PPLL0 ) @@ -3991,10 +3991,10 @@ enum atom_set_dce_clock_clock_type { DCE_CLOCK_TYPE_DISPCLK = 0, DCE_CLOCK_TYPE_DPREFCLK = 1, - DCE_CLOCK_TYPE_PIXELCLK = 2, // used by VBIOS internally, called by SetPixelClock + DCE_CLOCK_TYPE_PIXELCLK = 2, // used by VBIOS internally, called by SetPixelClock }; -//ucDCEClkFlag when ucDCEClkType == DPREFCLK +//ucDCEClkFlag when ucDCEClkType == DPREFCLK enum atom_set_dce_clock_dprefclk_flag { DCE_CLOCK_FLAG_PLL_REFCLK_SRC_MASK = 0x03, @@ -4004,14 +4004,14 @@ enum atom_set_dce_clock_dprefclk_flag DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN = 0x03, }; -//ucDCEClkFlag when ucDCEClkType == PIXCLK +//ucDCEClkFlag when ucDCEClkType == PIXCLK enum atom_set_dce_clock_pixclk_flag { DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_MASK = 0x03, - DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO - DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4 - DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2 - DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1 + DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO + DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4 + DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2 + DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1 DCE_CLOCK_FLAG_PIXCLK_YUV420_MODE = 0x04, }; @@ -4022,9 +4022,9 @@ struct set_dce_clock_ps_allocation_v2_1 }; -/****************************************************************************/ +/****************************************************************************/ // Structures used by BlankCRTC -/****************************************************************************/ +/****************************************************************************/ struct blank_crtc_parameters { uint8_t crtc_id; // enum atom_crtc_def @@ -4039,20 +4039,20 @@ enum atom_blank_crtc_command ATOM_BLANKING_OFF = 0, }; -/****************************************************************************/ +/****************************************************************************/ // Structures used by enablecrtc -/****************************************************************************/ +/****************************************************************************/ struct enable_crtc_parameters { uint8_t crtc_id; // enum atom_crtc_def - uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE + uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE uint8_t padding[2]; }; -/****************************************************************************/ +/****************************************************************************/ // Structure used by EnableDispPowerGating -/****************************************************************************/ +/****************************************************************************/ struct enable_disp_power_gating_parameters_v2_1 { uint8_t disp_pipe_id; // ATOM_CRTC1, ATOM_CRTC2, ... @@ -4060,15 +4060,15 @@ struct enable_disp_power_gating_parameters_v2_1 uint8_t padding[2]; }; -struct enable_disp_power_gating_ps_allocation +struct enable_disp_power_gating_ps_allocation { struct enable_disp_power_gating_parameters_v2_1 param; uint32_t ulReserved[4]; }; -/****************************************************************************/ +/****************************************************************************/ // Structure used in setcrtc_usingdtdtiming -/****************************************************************************/ +/****************************************************************************/ struct set_crtc_using_dtd_timing_parameters { uint16_t h_size; @@ -4079,7 +4079,7 @@ struct set_crtc_using_dtd_timing_parameters uint16_t h_syncwidth; uint16_t v_syncoffset; uint16_t v_syncwidth; - uint16_t modemiscinfo; + uint16_t modemiscinfo; uint8_t h_border; uint8_t v_border; uint8_t crtc_id; // enum atom_crtc_def @@ -4088,9 +4088,9 @@ struct set_crtc_using_dtd_timing_parameters }; -/****************************************************************************/ +/****************************************************************************/ // Structures used by processi2cchanneltransaction -/****************************************************************************/ +/****************************************************************************/ struct process_i2c_channel_transaction_parameters { uint8_t i2cspeed_khz; @@ -4122,9 +4122,9 @@ enum atom_process_i2c_status }; -/****************************************************************************/ +/****************************************************************************/ // Structures used by processauxchanneltransaction -/****************************************************************************/ +/****************************************************************************/ struct process_aux_channel_transaction_parameters_v1_2 { @@ -4140,9 +4140,9 @@ struct process_aux_channel_transaction_parameters_v1_2 }; -/****************************************************************************/ +/****************************************************************************/ // Structures used by selectcrtc_source -/****************************************************************************/ +/****************************************************************************/ struct select_crtc_source_parameters_v2_3 { @@ -4153,9 +4153,9 @@ struct select_crtc_source_parameters_v2_3 }; -/****************************************************************************/ +/****************************************************************************/ // Structures used by digxencodercontrol -/****************************************************************************/ +/****************************************************************************/ // ucAction: enum atom_dig_encoder_control_action @@ -4171,8 +4171,8 @@ enum atom_dig_encoder_control_action ATOM_ENCODER_CMD_DP_VIDEO_ON = 0x0d, ATOM_ENCODER_CMD_SETUP_PANEL_MODE = 0x10, ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4 = 0x14, - ATOM_ENCODER_CMD_STREAM_SETUP = 0x0F, - ATOM_ENCODER_CMD_LINK_SETUP = 0x11, + ATOM_ENCODER_CMD_STREAM_SETUP = 0x0F, + ATOM_ENCODER_CMD_LINK_SETUP = 0x11, ATOM_ENCODER_CMD_ENCODER_BLANK = 0x12, }; @@ -4202,7 +4202,7 @@ struct dig_encoder_stream_setup_parameters_v1_5 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid uint8_t action; // = ATOM_ENOCODER_CMD_STREAM_SETUP uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI - uint8_t lanenum; // Lane number + uint8_t lanenum; // Lane number uint32_t pclk_10khz; // Pixel Clock in 10Khz uint8_t bitpercolor; uint8_t dplinkrate_270mhz;//= DP link rate/270Mhz, =6: 1.62G = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz etc @@ -4212,12 +4212,12 @@ struct dig_encoder_stream_setup_parameters_v1_5 struct dig_encoder_link_setup_parameters_v1_5 { uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid - uint8_t action; // = ATOM_ENOCODER_CMD_LINK_SETUP + uint8_t action; // = ATOM_ENOCODER_CMD_LINK_SETUP uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI - uint8_t lanenum; // Lane number + uint8_t lanenum; // Lane number uint8_t symclk_10khz; // Symbol Clock in 10Khz uint8_t hpd_sel; - uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable, + uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable, uint8_t reserved[2]; }; @@ -4226,15 +4226,15 @@ struct dp_panel_mode_set_parameters_v1_5 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid uint8_t action; // = ATOM_ENCODER_CMD_DPLINK_SETUP uint8_t panelmode; // enum atom_dig_encoder_control_panelmode - uint8_t reserved1; + uint8_t reserved1; uint32_t reserved2[2]; }; -struct dig_encoder_generic_cmd_parameters_v1_5 +struct dig_encoder_generic_cmd_parameters_v1_5 { uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid uint8_t action; // = rest of generic encoder command which does not carry any parameters - uint8_t reserved1[2]; + uint8_t reserved1[2]; uint32_t reserved2[2]; }; @@ -4246,11 +4246,11 @@ union dig_encoder_control_parameters_v1_5 struct dp_panel_mode_set_parameters_v1_5 dppanel_param; }; -/* +/* *************************************************************************** Structures used by dig1transmittercontrol - *************************************************************************** -*/ + *************************************************************************** +*/ struct dig_transmitter_control_parameters_v1_6 { uint8_t phyid; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF @@ -4259,10 +4259,10 @@ struct dig_transmitter_control_parameters_v1_6 uint8_t digmode; // enum atom_encode_mode_def uint8_t dplaneset; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP_LANE_SET__xDB_y_zV" } mode_laneset; - uint8_t lanenum; // Lane number 1, 2, 4, 8 + uint8_t lanenum; // Lane number 1, 2, 4, 8 uint32_t symclk_10khz; // Symbol Clock in 10Khz uint8_t hpdsel; // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned - uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable, + uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable, uint8_t connobj_id; // Connector Object Id defined in ObjectId.h uint8_t reserved; uint32_t reserved1; @@ -4325,29 +4325,29 @@ enum atom_dig_transmitter_control_dplaneset DP_LANE_SET__0DB_0_6V = 0x01, DP_LANE_SET__0DB_0_8V = 0x02, DP_LANE_SET__0DB_1_2V = 0x03, - DP_LANE_SET__3_5DB_0_4V = 0x08, + DP_LANE_SET__3_5DB_0_4V = 0x08, DP_LANE_SET__3_5DB_0_6V = 0x09, DP_LANE_SET__3_5DB_0_8V = 0x0a, DP_LANE_SET__6DB_0_4V = 0x10, DP_LANE_SET__6DB_0_6V = 0x11, - DP_LANE_SET__9_5DB_0_4V = 0x18, + DP_LANE_SET__9_5DB_0_4V = 0x18, }; -/****************************************************************************/ +/****************************************************************************/ // Structures used by ExternalEncoderControl V2.4 -/****************************************************************************/ +/****************************************************************************/ struct external_encoder_control_parameters_v2_4 { - uint16_t pixelclock_10khz; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT - uint8_t config; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT - uint8_t action; // + uint16_t pixelclock_10khz; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT + uint8_t config; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT + uint8_t action; // uint8_t encodermode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT - uint8_t lanenum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT + uint8_t lanenum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT uint8_t bitpercolor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP - uint8_t hpd_id; + uint8_t hpd_id; }; @@ -4371,7 +4371,7 @@ enum external_encoder_control_v2_4_config_def EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ = 0x00, EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ = 0x01, EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ = 0x02, - EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_3_24GHZ = 0x03, + EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_3_24GHZ = 0x03, EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MAKS = 0x70, EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 = 0x00, EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 = 0x10, @@ -4385,12 +4385,12 @@ struct external_encoder_control_ps_allocation_v2_4 }; -/* +/* *************************************************************************** AMD ACPI Table - - *************************************************************************** -*/ + + *************************************************************************** +*/ struct amd_acpi_description_header{ uint32_t signature; @@ -4437,13 +4437,13 @@ struct gop_lib1_content { -/* +/* *************************************************************************** Scratch Register definitions - Each number below indicates which scratch regiser request, Active and + Each number below indicates which scratch register request, Active and Connect all share the same definitions as display_device_tag defines - *************************************************************************** -*/ + *************************************************************************** +*/ enum scratch_register_def{ ATOM_DEVICE_CONNECT_INFO_DEF = 0, @@ -4525,12 +4525,12 @@ enum scratch_pre_os_mode_info_bits_def{ -/* +/* *************************************************************************** ATOM firmware ID header file !! Please keep it at end of the atomfirmware.h !! - *************************************************************************** -*/ + *************************************************************************** +*/ #include "atomfirmwareid.h" #pragma pack() diff --git a/sys/dev/pci/drm/amd/include/atomfirmwareid.h b/sys/dev/pci/drm/amd/include/atomfirmwareid.h index e6256efd0..a64fb1173 100644 --- a/sys/dev/pci/drm/amd/include/atomfirmwareid.h +++ b/sys/dev/pci/drm/amd/include/atomfirmwareid.h @@ -1,12 +1,12 @@ /****************************************************************************\ -* +* * File Name atomfirmwareid.h * * Description ATOM BIOS command/data table ID definition header file * * Copyright 2016 Advanced Micro Devices, Inc. * -* Permission is hereby granted, free of charge, to any person obtaining a copy of this software +* Permission is hereby granted, free of charge, to any person obtaining a copy of this software * and associated documentation files (the "Software"), to deal in the Software without restriction, * including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, diff --git a/sys/dev/pci/drm/amd/include/displayobject.h b/sys/dev/pci/drm/amd/include/displayobject.h index 67e23ff9c..687be3437 100644 --- a/sys/dev/pci/drm/amd/include/displayobject.h +++ b/sys/dev/pci/drm/amd/include/displayobject.h @@ -1,14 +1,14 @@ /****************************************************************************\ -* +* * Module Name displayobjectsoc15.h -* Project -* Device +* Project +* Device * * Description Contains the common definitions for display objects for SoC15 products. * * Copyright 2014 Advanced Micro Devices, Inc. * -* Permission is hereby granted, free of charge, to any person obtaining a copy of this software +* Permission is hereby granted, free of charge, to any person obtaining a copy of this software * and associated documentation files (the "Software"), to deal in the Software without restriction, * including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, @@ -35,7 +35,7 @@ /**************************************************** -* Display Object Type Definition +* Display Object Type Definition *****************************************************/ enum display_object_type{ DISPLAY_OBJECT_TYPE_NONE =0x00, @@ -45,7 +45,7 @@ DISPLAY_OBJECT_TYPE_CONNECTOR =0x03 }; /**************************************************** -* Encorder Object Type Definition +* Encorder Object Type Definition *****************************************************/ enum encoder_object_type{ ENCODER_OBJECT_ID_NONE =0x00, @@ -56,11 +56,11 @@ ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 =0x03, /**************************************************** -* Connector Object ID Definition +* Connector Object ID Definition *****************************************************/ enum connector_object_type{ -CONNECTOR_OBJECT_ID_NONE =0x00, +CONNECTOR_OBJECT_ID_NONE =0x00, CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D =0x01, CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D =0x02, CONNECTOR_OBJECT_ID_HDMI_TYPE_A =0x03, @@ -72,12 +72,12 @@ CONNECTOR_OBJECT_ID_OPM =0x07 /**************************************************** -* Protection Object ID Definition +* Protection Object ID Definition *****************************************************/ //No need /**************************************************** -* Object ENUM ID Definition +* Object ENUM ID Definition *****************************************************/ enum object_enum_id{ @@ -90,7 +90,7 @@ OBJECT_ENUM_ID6 =0x06 }; /**************************************************** -*Object ID Bit definition +*Object ID Bit definition *****************************************************/ enum object_id_bit{ OBJECT_ID_MASK =0x00FF, diff --git a/sys/dev/pci/drm/amd/include/ivsrcid/dcn/irqsrcs_dcn_1_0.h b/sys/dev/pci/drm/amd/include/ivsrcid/dcn/irqsrcs_dcn_1_0.h index 754170a86..3dcde7d21 100644 --- a/sys/dev/pci/drm/amd/include/ivsrcid/dcn/irqsrcs_dcn_1_0.h +++ b/sys/dev/pci/drm/amd/include/ivsrcid/dcn/irqsrcs_dcn_1_0.h @@ -27,538 +27,538 @@ #define __IRQSRCS_DCN_1_0_H__ -#define DCN_1_0__SRCID__DC_I2C_SW_DONE 1 // DC_I2C SW done DC_I2C_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS Level +#define DCN_1_0__SRCID__DC_I2C_SW_DONE 1 // DC_I2C SW done DC_I2C_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS Level #define DCN_1_0__CTXID__DC_I2C_SW_DONE 0 -#define DCN_1_0__SRCID__DC_I2C_DDC1_HW_DONE 1 // DC_I2C DDC1 HW done DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level +#define DCN_1_0__SRCID__DC_I2C_DDC1_HW_DONE 1 // DC_I2C DDC1 HW done DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level #define DCN_1_0__CTXID__DC_I2C_DDC1_HW_DONE 1 -#define DCN_1_0__SRCID__DC_I2C_DDC2_HW_DONE 1 // DC_I2C DDC2 HW done DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level +#define DCN_1_0__SRCID__DC_I2C_DDC2_HW_DONE 1 // DC_I2C DDC2 HW done DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level #define DCN_1_0__CTXID__DC_I2C_DDC2_HW_DONE 2 -#define DCN_1_0__SRCID__DC_I2C_DDC3_HW_DONE 1 // DC_I2C DDC3 HW done DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level +#define DCN_1_0__SRCID__DC_I2C_DDC3_HW_DONE 1 // DC_I2C DDC3 HW done DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level #define DCN_1_0__CTXID__DC_I2C_DDC3_HW_DONE 3 -#define DCN_1_0__SRCID__DC_I2C_DDC4_HW_DONE 1 // DC_I2C_DDC4 HW done DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level +#define DCN_1_0__SRCID__DC_I2C_DDC4_HW_DONE 1 // DC_I2C_DDC4 HW done DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level #define DCN_1_0__CTXID__DC_I2C_DDC4_HW_DONE 4 -#define DCN_1_0__SRCID__DC_I2C_DDC5_HW_DONE 1 // DC_I2C_DDC5 HW done DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level +#define DCN_1_0__SRCID__DC_I2C_DDC5_HW_DONE 1 // DC_I2C_DDC5 HW done DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level #define DCN_1_0__CTXID__DC_I2C_DDC5_HW_DONE 5 -#define DCN_1_0__SRCID__DC_I2C_DDC6_HW_DONE 1 // DC_I2C_DDC6 HW done DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level +#define DCN_1_0__SRCID__DC_I2C_DDC6_HW_DONE 1 // DC_I2C_DDC6 HW done DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level #define DCN_1_0__CTXID__DC_I2C_DDC6_HW_DONE 6 -#define DCN_1_0__SRCID__DC_I2C_DDCVGA_HW_DONE 1 // DC_I2C_DDCVGA HW done DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level +#define DCN_1_0__SRCID__DC_I2C_DDCVGA_HW_DONE 1 // DC_I2C_DDCVGA HW done DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level #define DCN_1_0__CTXID__DC_I2C_DDCVGA_HW_DONE 7 -#define DCN_1_0__SRCID__DC_I2C_DDC1_READ_REQUEST 1 // DC_I2C DDC1 read request DC_I2C_DDC1_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse +#define DCN_1_0__SRCID__DC_I2C_DDC1_READ_REQUEST 1 // DC_I2C DDC1 read request DC_I2C_DDC1_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse #define DCN_1_0__CTXID__DC_I2C_DDC1_READ_REQUEST 8 -#define DCN_1_0__SRCID__DC_I2C_DDC2_READ_REQUEST 1 // DC_I2C DDC2 read request DC_I2C_DDC2_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse +#define DCN_1_0__SRCID__DC_I2C_DDC2_READ_REQUEST 1 // DC_I2C DDC2 read request DC_I2C_DDC2_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse #define DCN_1_0__CTXID__DC_I2C_DDC2_READ_REQUEST 9 -#define DCN_1_0__SRCID__DC_I2C_DDC3_READ_REQUEST 1 // DC_I2C DDC3 read request DC_I2C_DDC3_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse +#define DCN_1_0__SRCID__DC_I2C_DDC3_READ_REQUEST 1 // DC_I2C DDC3 read request DC_I2C_DDC3_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse #define DCN_1_0__CTXID__DC_I2C_DDC3_READ_REQUEST 10 -#define DCN_1_0__SRCID__DC_I2C_DDC4_READ_REQUEST 1 // DC_I2C_DDC4 read request DC_I2C_DDC4_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse +#define DCN_1_0__SRCID__DC_I2C_DDC4_READ_REQUEST 1 // DC_I2C_DDC4 read request DC_I2C_DDC4_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse #define DCN_1_0__CTXID__DC_I2C_DDC4_READ_REQUEST 11 -#define DCN_1_0__SRCID__DC_I2C_DDC5_READ_REQUEST 1 // DC_I2C_DDC5 read request DC_I2C_DDC5_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse +#define DCN_1_0__SRCID__DC_I2C_DDC5_READ_REQUEST 1 // DC_I2C_DDC5 read request DC_I2C_DDC5_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse #define DCN_1_0__CTXID__DC_I2C_DDC5_READ_REQUEST 12 -#define DCN_1_0__SRCID__DC_I2C_DDC6_READ_REQUEST 1 // DC_I2C_DDC6 read request DC_I2C_DDC6_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse +#define DCN_1_0__SRCID__DC_I2C_DDC6_READ_REQUEST 1 // DC_I2C_DDC6 read request DC_I2C_DDC6_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse #define DCN_1_0__CTXID__DC_I2C_DDC6_READ_REQUEST 13 -#define DCN_1_0__SRCID__DC_I2C_DDCVGA_READ_REQUEST 1 // DC_I2C_DDCVGA read request DC_I2C_VGA_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse +#define DCN_1_0__SRCID__DC_I2C_DDCVGA_READ_REQUEST 1 // DC_I2C_DDCVGA read request DC_I2C_VGA_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse #define DCN_1_0__CTXID__DC_I2C_DDCVGA_READ_REQUEST 14 -#define DCN_1_0__SRCID__GENERIC_I2C_DDC_READ_REQUEST 1 // GENERIC_I2C_DDC read request GENERIC_I2C_DDC_READ_REUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse +#define DCN_1_0__SRCID__GENERIC_I2C_DDC_READ_REQUEST 1 // GENERIC_I2C_DDC read request GENERIC_I2C_DDC_READ_REUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse #define DCN_1_0__CTXID__GENERIC_I2C_DDC_READ_REQUEST 15 -#define DCN_1_0__SRCID__DCCG_PERFCOUNTER_INT0_STATUS 2 // DCCG perfmon counter0 interrupt DCCG_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level / Pulse +#define DCN_1_0__SRCID__DCCG_PERFCOUNTER_INT0_STATUS 2 // DCCG perfmon counter0 interrupt DCCG_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level / Pulse #define DCN_1_0__CTXID__DCCG_PERFCOUNTER_INT0_STATUS 7 -#define DCN_1_0__SRCID__DCCG_PERFCOUNTER_INT1_STATUS 2 // DCCG perfmon counter1 interrupt DCCG_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level +#define DCN_1_0__SRCID__DCCG_PERFCOUNTER_INT1_STATUS 2 // DCCG perfmon counter1 interrupt DCCG_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level #define DCN_1_0__CTXID__DCCG_PERFCOUNTER_INT1_STATUS 8 -#define DCN_1_0__SRCID__DMU_PERFCOUNTER_INT0_STATUS 3 // DMU perfmon counter0 interrupt DMU_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level / Pulse +#define DCN_1_0__SRCID__DMU_PERFCOUNTER_INT0_STATUS 3 // DMU perfmon counter0 interrupt DMU_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level / Pulse #define DCN_1_0__CTXID__DMU_PERFCOUNTER_INT0_STATUS 7 -#define DCN_1_0__SRCID__DMU_PERFCOUNTER_INT1_STATUS 3 // DMU perfmon counter1 interrupt DMU_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level +#define DCN_1_0__SRCID__DMU_PERFCOUNTER_INT1_STATUS 3 // DMU perfmon counter1 interrupt DMU_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level #define DCN_1_0__CTXID__DMU_PERFCOUNTER_INT1_STATUS 8 -#define DCN_1_0__SRCID__DIO_PERFCOUNTER_INT0_STATUS 4 // DIO perfmon counter0 interrupt DIO_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level / Pulse +#define DCN_1_0__SRCID__DIO_PERFCOUNTER_INT0_STATUS 4 // DIO perfmon counter0 interrupt DIO_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level / Pulse #define DCN_1_0__CTXID__DIO_PERFCOUNTER_INT0_STATUS 7 -#define DCN_1_0__SRCID__DIO_PERFCOUNTER_INT1_STATUS 4 // DIO perfmon counter1 interrupt DIO_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level +#define DCN_1_0__SRCID__DIO_PERFCOUNTER_INT1_STATUS 4 // DIO perfmon counter1 interrupt DIO_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level #define DCN_1_0__CTXID__DIO_PERFCOUNTER_INT1_STATUS 8 -#define DCN_1_0__SRCID__RBBMIF_TIMEOUT_INT 5 // RBBMIF timeout interrupt RBBMIF_IHC_TIMEOUT_INTERRUPT DISP_INTERRUPT_STATUS Level +#define DCN_1_0__SRCID__RBBMIF_TIMEOUT_INT 5 // RBBMIF timeout interrupt RBBMIF_IHC_TIMEOUT_INTERRUPT DISP_INTERRUPT_STATUS Level #define DCN_1_0__CTXID__RBBMIF_TIMEOUT_INT 12 -#define DCN_1_0__SRCID__DMCU_INTERNAL_INT 5 // DMCU execution exception DMCU_UC_INTERNAL_INT DISP_INTERRUPT_STATUS Level +#define DCN_1_0__SRCID__DMCU_INTERNAL_INT 5 // DMCU execution exception DMCU_UC_INTERNAL_INT DISP_INTERRUPT_STATUS Level #define DCN_1_0__CTXID__DMCU_INTERNAL_INT 13 -#define DCN_1_0__SRCID__DMCU_SCP_INT 5 // DMCU Slave Communication Port Interrupt DMCU_SCP_INT DISP_INTERRUPT_STATUS Level +#define DCN_1_0__SRCID__DMCU_SCP_INT 5 // DMCU Slave Communication Port Interrupt DMCU_SCP_INT DISP_INTERRUPT_STATUS Level #define DCN_1_0__CTXID__DMCU_SCP_INT 14 -#define DCN_1_0__SRCID__DMCU_ABM0_HG_READY_INT 6 // ABM histogram ready interrupt ABM0_HG_READY_INT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__SRCID__DMCU_ABM0_HG_READY_INT 6 // ABM histogram ready interrupt ABM0_HG_READY_INT DISP_INTERRUPT_STATUS_CONTINUE22 Level #define DCN_1_0__CTXID__DMCU_ABM0_HG_READY_INT 0 -#define DCN_1_0__SRCID__DMCU_ABM0_LS_READY_INT 6 // ABM luma stat ready interrupt ABM0_LS_READY_INT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__SRCID__DMCU_ABM0_LS_READY_INT 6 // ABM luma stat ready interrupt ABM0_LS_READY_INT DISP_INTERRUPT_STATUS_CONTINUE22 Level #define DCN_1_0__CTXID__DMCU_ABM0_LS_READY_INT 1 -#define DCN_1_0__SRCID__DMCU_ABM0_BL_UPDATE_INT 6 // ABM Backlight update interrupt ABM0_BL_UPDATE_INT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__SRCID__DMCU_ABM0_BL_UPDATE_INT 6 // ABM Backlight update interrupt ABM0_BL_UPDATE_INT DISP_INTERRUPT_STATUS_CONTINUE22 Level #define DCN_1_0__CTXID__DMCU_ABM0_BL_UPDATE_INT 2 -#define DCN_1_0__SRCID__DMCU_ABM1_HG_READY_INT 6 // ABM histogram ready interrupt ABM1_HG_READY_INT DISP_INTERRUPT_STATUS Level +#define DCN_1_0__SRCID__DMCU_ABM1_HG_READY_INT 6 // ABM histogram ready interrupt ABM1_HG_READY_INT DISP_INTERRUPT_STATUS Level #define DCN_1_0__CTXID__DMCU_ABM1_HG_READY_INT 3 -#define DCN_1_0__SRCID__DMCU_ABM1_LS_READY_INT 6 // ABM luma stat ready interrupt ABM1_LS_READY_INT DISP_INTERRUPT_STATUS Level +#define DCN_1_0__SRCID__DMCU_ABM1_LS_READY_INT 6 // ABM luma stat ready interrupt ABM1_LS_READY_INT DISP_INTERRUPT_STATUS Level #define DCN_1_0__CTXID__DMCU_ABM1_LS_READY_INT 4 -#define DCN_1_0__SRCID__DMCU_ABM1_BL_UPDATE_INT 6 // ABM Backlight update interrupt ABM1_BL_UPDATE_INT DISP_INTERRUPT_STATUS Level +#define DCN_1_0__SRCID__DMCU_ABM1_BL_UPDATE_INT 6 // ABM Backlight update interrupt ABM1_BL_UPDATE_INT DISP_INTERRUPT_STATUS Level #define DCN_1_0__CTXID__DMCU_ABM1_BL_UPDATE_INT 5 -#define DCN_1_0__SRCID__WB0_PERFCOUNTER_INT0_STATUS 6 // WB0 perfmon counter0 interrupt WB0_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level / Pulse +#define DCN_1_0__SRCID__WB0_PERFCOUNTER_INT0_STATUS 6 // WB0 perfmon counter0 interrupt WB0_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level / Pulse #define DCN_1_0__CTXID__WB0_PERFCOUNTER_INT0_STATUS 6 -#define DCN_1_0__SRCID__WB0_PERFCOUNTER_INT1_STATUS 6 // WB0 perfmon counter1 interrupt WB0_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level +#define DCN_1_0__SRCID__WB0_PERFCOUNTER_INT1_STATUS 6 // WB0 perfmon counter1 interrupt WB0_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level #define DCN_1_0__CTXID__WB0_PERFCOUNTER_INT1_STATUS 7 -#define DCN_1_0__SRCID__DPDBG_FIFO_OVERFLOW_INT 7 // DP debug FIFO overflow interrupt DPDBG_IHC_FIFO_OVERFLOW_INT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse +#define DCN_1_0__SRCID__DPDBG_FIFO_OVERFLOW_INT 7 // DP debug FIFO overflow interrupt DPDBG_IHC_FIFO_OVERFLOW_INT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse #define DCN_1_0__CTXID__DPDBG_FIFO_OVERFLOW_INT 1 -#define DCN_1_0__SRCID__DCIO_DPCS_TXA_ERROR_INT 8 // DPCS TXA error interrupt DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse +#define DCN_1_0__SRCID__DCIO_DPCS_TXA_ERROR_INT 8 // DPCS TXA error interrupt DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse #define DCN_1_0__CTXID__DCIO_DPCS_TXA_ERROR_INT 0 -#define DCN_1_0__SRCID__DCIO_DPCS_TXB_ERROR_INT 8 // DPCS TXB error interrupt DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse +#define DCN_1_0__SRCID__DCIO_DPCS_TXB_ERROR_INT 8 // DPCS TXB error interrupt DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse #define DCN_1_0__CTXID__DCIO_DPCS_TXB_ERROR_INT 1 -#define DCN_1_0__SRCID__DCIO_DPCS_TXC_ERROR_INT 8 // DPCS TXC error interrupt DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse +#define DCN_1_0__SRCID__DCIO_DPCS_TXC_ERROR_INT 8 // DPCS TXC error interrupt DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse #define DCN_1_0__CTXID__DCIO_DPCS_TXC_ERROR_INT 2 -#define DCN_1_0__SRCID__DCIO_DPCS_TXD_ERROR_INT 8 // DPCS TXD error interrupt DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse +#define DCN_1_0__SRCID__DCIO_DPCS_TXD_ERROR_INT 8 // DPCS TXD error interrupt DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse #define DCN_1_0__CTXID__DCIO_DPCS_TXD_ERROR_INT 3 -#define DCN_1_0__SRCID__DCIO_DPCS_TXE_ERROR_INT 8 // DPCS TXE error interrupt DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse +#define DCN_1_0__SRCID__DCIO_DPCS_TXE_ERROR_INT 8 // DPCS TXE error interrupt DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse #define DCN_1_0__CTXID__DCIO_DPCS_TXE_ERROR_INT 4 -#define DCN_1_0__SRCID__DCIO_DPCS_TXF_ERROR_INT 8 // DPCS TXF error interrupt DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse +#define DCN_1_0__SRCID__DCIO_DPCS_TXF_ERROR_INT 8 // DPCS TXF error interrupt DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse #define DCN_1_0__CTXID__DCIO_DPCS_TXF_ERROR_INT 5 -#define DCN_1_0__SRCID__DCIO_DPCS_TXG_ERROR_INT 8 // DPCS TXG error interrupt DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse +#define DCN_1_0__SRCID__DCIO_DPCS_TXG_ERROR_INT 8 // DPCS TXG error interrupt DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse #define DCN_1_0__CTXID__DCIO_DPCS_TXG_ERROR_INT 6 -#define DCN_1_0__SRCID__DCIO_DPCS_RXA_ERROR_INT 8 // DPCS RXA error interrupt DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse +#define DCN_1_0__SRCID__DCIO_DPCS_RXA_ERROR_INT 8 // DPCS RXA error interrupt DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse #define DCN_1_0__CTXID__DCIO_DPCS_RXA_ERROR_INT 7 -#define DCN_1_0__SRCID__DC_HPD1_INT 9 // Hot Plug Detection 1 DC_HPD1_INTERRUPT DISP_INTERRUPT_STATUS Level +#define DCN_1_0__SRCID__DC_HPD1_INT 9 // Hot Plug Detection 1 DC_HPD1_INTERRUPT DISP_INTERRUPT_STATUS Level #define DCN_1_0__CTXID__DC_HPD1_INT 0 -#define DCN_1_0__SRCID__DC_HPD2_INT 9 // Hot Plug Detection 2 DC_HPD2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level +#define DCN_1_0__SRCID__DC_HPD2_INT 9 // Hot Plug Detection 2 DC_HPD2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level #define DCN_1_0__CTXID__DC_HPD2_INT 1 -#define DCN_1_0__SRCID__DC_HPD3_INT 9 // Hot Plug Detection 3 DC_HPD3_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level +#define DCN_1_0__SRCID__DC_HPD3_INT 9 // Hot Plug Detection 3 DC_HPD3_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level #define DCN_1_0__CTXID__DC_HPD3_INT 2 -#define DCN_1_0__SRCID__DC_HPD4_INT 9 // Hot Plug Detection 4 DC_HPD4_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level +#define DCN_1_0__SRCID__DC_HPD4_INT 9 // Hot Plug Detection 4 DC_HPD4_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level #define DCN_1_0__CTXID__DC_HPD4_INT 3 -#define DCN_1_0__SRCID__DC_HPD5_INT 9 // Hot Plug Detection 5 DC_HPD5_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level +#define DCN_1_0__SRCID__DC_HPD5_INT 9 // Hot Plug Detection 5 DC_HPD5_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level #define DCN_1_0__CTXID__DC_HPD5_INT 4 -#define DCN_1_0__SRCID__DC_HPD6_INT 9 // Hot Plug Detection 6 DC_HPD6_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level -#define DCN_1_0__CTXID__DC_HPD6_INT 5 +#define DCN_1_0__SRCID__DC_HPD6_INT 9 // Hot Plug Detection 6 DC_HPD6_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level +#define DCN_1_0__CTXID__DC_HPD6_INT 5 -#define DCN_1_0__SRCID__DC_HPD1_RX_INT 9 // Hot Plug Detection RX interrupt 1 DC_HPD1_RX_INTERRUPT DISP_INTERRUPT_STATUS Level +#define DCN_1_0__SRCID__DC_HPD1_RX_INT 9 // Hot Plug Detection RX interrupt 1 DC_HPD1_RX_INTERRUPT DISP_INTERRUPT_STATUS Level #define DCN_1_0__CTXID__DC_HPD1_RX_INT 6 -#define DCN_1_0__SRCID__DC_HPD2_RX_INT 9 // Hot Plug Detection RX interrupt 2 DC_HPD2_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level +#define DCN_1_0__SRCID__DC_HPD2_RX_INT 9 // Hot Plug Detection RX interrupt 2 DC_HPD2_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level #define DCN_1_0__CTXID__DC_HPD2_RX_INT 7 -#define DCN_1_0__SRCID__DC_HPD3_RX_INT 9 // Hot Plug Detection RX interrupt 3 DC_HPD3_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level +#define DCN_1_0__SRCID__DC_HPD3_RX_INT 9 // Hot Plug Detection RX interrupt 3 DC_HPD3_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level #define DCN_1_0__CTXID__DC_HPD3_RX_INT 8 -#define DCN_1_0__SRCID__DC_HPD4_RX_INT 9 // Hot Plug Detection RX interrupt 4 DC_HPD4_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level +#define DCN_1_0__SRCID__DC_HPD4_RX_INT 9 // Hot Plug Detection RX interrupt 4 DC_HPD4_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level #define DCN_1_0__CTXID__DC_HPD4_RX_INT 9 -#define DCN_1_0__SRCID__DC_HPD5_RX_INT 9 // Hot Plug Detection RX interrupt 5 DC_HPD5_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level +#define DCN_1_0__SRCID__DC_HPD5_RX_INT 9 // Hot Plug Detection RX interrupt 5 DC_HPD5_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level #define DCN_1_0__CTXID__DC_HPD5_RX_INT 10 -#define DCN_1_0__SRCID__DC_HPD6_RX_INT 9 // Hot Plug Detection RX interrupt 6 DC_HPD6_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level +#define DCN_1_0__SRCID__DC_HPD6_RX_INT 9 // Hot Plug Detection RX interrupt 6 DC_HPD6_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level #define DCN_1_0__CTXID__DC_HPD6_RX_INT 11 -#define DCN_1_0__SRCID__DC_DAC_A_AUTO_DET 0xA // DAC A auto - detection DACA_AUTODETECT_GENERITE_INTERRUPT DISP_INTERRUPT_STATUS Level +#define DCN_1_0__SRCID__DC_DAC_A_AUTO_DET 0xA // DAC A auto - detection DACA_AUTODETECT_GENERITE_INTERRUPT DISP_INTERRUPT_STATUS Level #define DCN_1_0__CTXID__DC_DAC_A_AUTO_DET 0 -#define DCN_1_0__SRCID__AZ_ENDPOINT0_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint0 format changed AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__SRCID__AZ_ENDPOINT0_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint0 format changed AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse #define DCN_1_0__CTXID__AZ_ENDPOINT0_AUDIO_FMT_CHANGED_INT 2 -#define DCN_1_0__SRCID__AZ_ENDPOINT1_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint1 format changed AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__SRCID__AZ_ENDPOINT1_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint1 format changed AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse #define DCN_1_0__CTXID__AZ_ENDPOINT1_AUDIO_FMT_CHANGED_INT 3 -#define DCN_1_0__SRCID__AZ_ENDPOINT2_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint2 format changed AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__SRCID__AZ_ENDPOINT2_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint2 format changed AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse #define DCN_1_0__CTXID__AZ_ENDPOINT2_AUDIO_FMT_CHANGED_INT 4 -#define DCN_1_0__SRCID__AZ_ENDPOINT3_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint3 format changed AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__SRCID__AZ_ENDPOINT3_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint3 format changed AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse #define DCN_1_0__CTXID__AZ_ENDPOINT3_AUDIO_FMT_CHANGED_INT 5 -#define DCN_1_0__SRCID__AZ_ENDPOINT4_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint4 format changed AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__SRCID__AZ_ENDPOINT4_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint4 format changed AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse #define DCN_1_0__CTXID__AZ_ENDPOINT4_AUDIO_FMT_CHANGED_INT 6 -#define DCN_1_0__SRCID__AZ_ENDPOINT5_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint5 format changed AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__SRCID__AZ_ENDPOINT5_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint5 format changed AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse #define DCN_1_0__CTXID__AZ_ENDPOINT5_AUDIO_FMT_CHANGED_INT 7 -#define DCN_1_0__SRCID__AZ_ENDPOINT6_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint6 format changed AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__SRCID__AZ_ENDPOINT6_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint6 format changed AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse #define DCN_1_0__CTXID__AZ_ENDPOINT6_AUDIO_FMT_CHANGED_INT 8 -#define DCN_1_0__SRCID__AZ_ENDPOINT7_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint7 format changed AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__SRCID__AZ_ENDPOINT7_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint7 format changed AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse #define DCN_1_0__CTXID__AZ_ENDPOINT7_AUDIO_FMT_CHANGED_INT 9 -#define DCN_1_0__SRCID__AZ_ENDPOINT0_AUDIO_ENABLED_INT 0xB // AZ Endpoint0 enabled AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__SRCID__AZ_ENDPOINT0_AUDIO_ENABLED_INT 0xB // AZ Endpoint0 enabled AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse #define DCN_1_0__CTXID__AZ_ENDPOINT0_AUDIO_ENABLED_INT 0 -#define DCN_1_0__SRCID__AZ_ENDPOINT1_AUDIO_ENABLED_INT 0xB // AZ Endpoint1 enabled AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__SRCID__AZ_ENDPOINT1_AUDIO_ENABLED_INT 0xB // AZ Endpoint1 enabled AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse #define DCN_1_0__CTXID__AZ_ENDPOINT1_AUDIO_ENABLED_INT 1 -#define DCN_1_0__SRCID__AZ_ENDPOINT2_AUDIO_ENABLED_INT 0xB // AZ Endpoint2 enabled AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__SRCID__AZ_ENDPOINT2_AUDIO_ENABLED_INT 0xB // AZ Endpoint2 enabled AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse #define DCN_1_0__CTXID__AZ_ENDPOINT2_AUDIO_ENABLED_INT 2 -#define DCN_1_0__SRCID__AZ_ENDPOINT3_AUDIO_ENABLED_INT 0xB // AZ Endpoint3 enabled AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__SRCID__AZ_ENDPOINT3_AUDIO_ENABLED_INT 0xB // AZ Endpoint3 enabled AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse #define DCN_1_0__CTXID__AZ_ENDPOINT3_AUDIO_ENABLED_INT 3 -#define DCN_1_0__SRCID__AZ_ENDPOINT4_AUDIO_ENABLED_INT 0xB // AZ Endpoint4 enabled AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__SRCID__AZ_ENDPOINT4_AUDIO_ENABLED_INT 0xB // AZ Endpoint4 enabled AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse #define DCN_1_0__CTXID__AZ_ENDPOINT4_AUDIO_ENABLED_INT 4 -#define DCN_1_0__SRCID__AZ_ENDPOINT5_AUDIO_ENABLED_INT 0xB // AZ Endpoint5 enabled AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__SRCID__AZ_ENDPOINT5_AUDIO_ENABLED_INT 0xB // AZ Endpoint5 enabled AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse #define DCN_1_0__CTXID__AZ_ENDPOINT5_AUDIO_ENABLED_INT 5 -#define DCN_1_0__SRCID__AZ_ENDPOINT6_AUDIO_ENABLED_INT 0xB // AZ Endpoint6 enabled AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__SRCID__AZ_ENDPOINT6_AUDIO_ENABLED_INT 0xB // AZ Endpoint6 enabled AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse #define DCN_1_0__CTXID__AZ_ENDPOINT6_AUDIO_ENABLED_INT 6 -#define DCN_1_0__SRCID__AZ_ENDPOINT7_AUDIO_ENABLED_INT 0xB // AZ Endpoint7 enabled AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__SRCID__AZ_ENDPOINT7_AUDIO_ENABLED_INT 0xB // AZ Endpoint7 enabled AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse #define DCN_1_0__CTXID__AZ_ENDPOINT7_AUDIO_ENABLED_INT 7 -#define DCN_1_0__SRCID__AZ_ENDPOINT0_AUDIO_DISABLED_INT 0xC // AZ Endpoint0 disabled AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__SRCID__AZ_ENDPOINT0_AUDIO_DISABLED_INT 0xC // AZ Endpoint0 disabled AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse #define DCN_1_0__CTXID__AZ_ENDPOINT0_AUDIO_DISABLED_INT 0 -#define DCN_1_0__SRCID__AZ_ENDPOINT1_AUDIO_DISABLED_INT 0xC // AZ Endpoint1 disabled AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__SRCID__AZ_ENDPOINT1_AUDIO_DISABLED_INT 0xC // AZ Endpoint1 disabled AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse #define DCN_1_0__CTXID__AZ_ENDPOINT1_AUDIO_DISABLED_INT 1 -#define DCN_1_0__SRCID__AZ_ENDPOINT2_AUDIO_DISABLED_INT 0xC // AZ Endpoint2 disabled AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__SRCID__AZ_ENDPOINT2_AUDIO_DISABLED_INT 0xC // AZ Endpoint2 disabled AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse #define DCN_1_0__CTXID__AZ_ENDPOINT2_AUDIO_DISABLED_INT 2 -#define DCN_1_0__SRCID__AZ_ENDPOINT3_AUDIO_DISABLED_INT 0xC // AZ Endpoint3 disabled AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__SRCID__AZ_ENDPOINT3_AUDIO_DISABLED_INT 0xC // AZ Endpoint3 disabled AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse #define DCN_1_0__CTXID__AZ_ENDPOINT3_AUDIO_DISABLED_INT 3 -#define DCN_1_0__SRCID__AZ_ENDPOINT4_AUDIO_DISABLED_INT 0xC // AZ Endpoint4 disabled AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__SRCID__AZ_ENDPOINT4_AUDIO_DISABLED_INT 0xC // AZ Endpoint4 disabled AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse #define DCN_1_0__CTXID__AZ_ENDPOINT4_AUDIO_DISABLED_INT 4 -#define DCN_1_0__SRCID__AZ_ENDPOINT5_AUDIO_DISABLED_INT 0xC // AZ Endpoint5 disabled AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__SRCID__AZ_ENDPOINT5_AUDIO_DISABLED_INT 0xC // AZ Endpoint5 disabled AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse #define DCN_1_0__CTXID__AZ_ENDPOINT5_AUDIO_DISABLED_INT 5 -#define DCN_1_0__SRCID__AZ_ENDPOINT6_AUDIO_DISABLED_INT 0xC // AZ Endpoint6 disabled AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__SRCID__AZ_ENDPOINT6_AUDIO_DISABLED_INT 0xC // AZ Endpoint6 disabled AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse #define DCN_1_0__CTXID__AZ_ENDPOINT6_AUDIO_DISABLED_INT 6 -#define DCN_1_0__SRCID__AZ_ENDPOINT7_AUDIO_DISABLED_INT 0xC // AZ Endpoint7 disabled AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__SRCID__AZ_ENDPOINT7_AUDIO_DISABLED_INT 0xC // AZ Endpoint7 disabled AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse #define DCN_1_0__CTXID__AZ_ENDPOINT7_AUDIO_DISABLED_INT 7 -#define DCN_1_0__SRCID__DC_AUX1_GTC_SYNC_LOCK_DONE 0xD // AUX1 GTC sync lock complete AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level +#define DCN_1_0__SRCID__DC_AUX1_GTC_SYNC_LOCK_DONE 0xD // AUX1 GTC sync lock complete AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level #define DCN_1_0__CTXID__DC_AUX1_GTC_SYNC_LOCK_DONE 0 -#define DCN_1_0__SRCID__DC_AUX1_GTC_SYNC_ERROR 0xD // AUX1 GTC sync error occurred AUX1_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level +#define DCN_1_0__SRCID__DC_AUX1_GTC_SYNC_ERROR 0xD // AUX1 GTC sync error occurred AUX1_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level #define DCN_1_0__CTXID__DC_AUX1_GTC_SYNC_ERROR 1 -#define DCN_1_0__SRCID__DC_AUX2_GTC_SYNC_LOCK_DONE 0xD // AUX2 GTC sync lock complete AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level +#define DCN_1_0__SRCID__DC_AUX2_GTC_SYNC_LOCK_DONE 0xD // AUX2 GTC sync lock complete AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level #define DCN_1_0__CTXID__DC_AUX2_GTC_SYNC_LOCK_DONE 2 -#define DCN_1_0__SRCID__DC_AUX2_GTC_SYNC_ERROR 0xD // AUX2 GTC sync error occurred AUX2_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level +#define DCN_1_0__SRCID__DC_AUX2_GTC_SYNC_ERROR 0xD // AUX2 GTC sync error occurred AUX2_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level #define DCN_1_0__CTXID__DC_AUX2_GTC_SYNC_ERROR 3 -#define DCN_1_0__SRCID__DC_AUX3_GTC_SYNC_LOCK_DONE 0xD // AUX3 GTC sync lock complete AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level +#define DCN_1_0__SRCID__DC_AUX3_GTC_SYNC_LOCK_DONE 0xD // AUX3 GTC sync lock complete AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level #define DCN_1_0__CTXID__DC_AUX3_GTC_SYNC_LOCK_DONE 4 -#define DCN_1_0__SRCID__DC_AUX3_GTC_SYNC_ERROR 0xD // AUX3 GTC sync error occurred AUX3_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level +#define DCN_1_0__SRCID__DC_AUX3_GTC_SYNC_ERROR 0xD // AUX3 GTC sync error occurred AUX3_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level #define DCN_1_0__CTXID__DC_AUX3_GTC_SYNC_ERROR 5 -#define DCN_1_0__SRCID__DC_DIGA_VID_STRM_DISABLE 0xE // DIGA vid stream disable DIGA_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS Level +#define DCN_1_0__SRCID__DC_DIGA_VID_STRM_DISABLE 0xE // DIGA vid stream disable DIGA_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS Level #define DCN_1_0__CTXID__DC_DIGA_VID_STRM_DISABLE 0 -#define DCN_1_0__SRCID__DC_DIGB_VID_STRM_DISABLE 0xE // DIGB vid stream disable DIGB_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level +#define DCN_1_0__SRCID__DC_DIGB_VID_STRM_DISABLE 0xE // DIGB vid stream disable DIGB_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level #define DCN_1_0__CTXID__DC_DIGB_VID_STRM_DISABLE 1 -#define DCN_1_0__SRCID__DC_DIGC_VID_STRM_DISABLE 0xE // DIGC vid stream disable DIGC_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level +#define DCN_1_0__SRCID__DC_DIGC_VID_STRM_DISABLE 0xE // DIGC vid stream disable DIGC_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level #define DCN_1_0__CTXID__DC_DIGC_VID_STRM_DISABLE 2 -#define DCN_1_0__SRCID__DC_DIGD_VID_STRM_DISABLE 0xE // DIGD vid stream disable DIGD_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level +#define DCN_1_0__SRCID__DC_DIGD_VID_STRM_DISABLE 0xE // DIGD vid stream disable DIGD_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level #define DCN_1_0__CTXID__DC_DIGD_VID_STRM_DISABLE 3 -#define DCN_1_0__SRCID__DC_DIGE_VID_STRM_DISABLE 0xE // DIGE vid stream disable DIGE_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level +#define DCN_1_0__SRCID__DC_DIGE_VID_STRM_DISABLE 0xE // DIGE vid stream disable DIGE_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level #define DCN_1_0__CTXID__DC_DIGE_VID_STRM_DISABLE 4 -#define DCN_1_0__SRCID__DC_DIGF_VID_STRM_DISABLE 0xE // DIGF vid stream disable DIGF_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level +#define DCN_1_0__SRCID__DC_DIGF_VID_STRM_DISABLE 0xE // DIGF vid stream disable DIGF_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level #define DCN_1_0__CTXID__DC_DIGF_VID_STRM_DISABLE 5 -#define DCN_1_0__SRCID__DC_DIGG_VID_STRM_DISABLE 0xE // DIGF vid stream disable DIGG_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE19 Level +#define DCN_1_0__SRCID__DC_DIGG_VID_STRM_DISABLE 0xE // DIGF vid stream disable DIGG_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE19 Level #define DCN_1_0__CTXID__DC_DIGG_VID_STRM_DISABLE 6 -#define DCN_1_0__SRCID__DC_DIGH_VID_STRM_DISABLE 0xE // DIGH_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level +#define DCN_1_0__SRCID__DC_DIGH_VID_STRM_DISABLE 0xE // DIGH_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level #define DCN_1_0__CTXID__DC_DIGH_VID_STRM_DISABLE 7 -#define DCN_1_0__SRCID__DC_DIGA_FAST_TRAINING_COMPLETE_INT 0xF // DIGA - Fast Training Complete DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS Level +#define DCN_1_0__SRCID__DC_DIGA_FAST_TRAINING_COMPLETE_INT 0xF // DIGA - Fast Training Complete DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS Level #define DCN_1_0__CTXID__DC_DIGA_FAST_TRAINING_COMPLETE_INT 0 -#define DCN_1_0__SRCID__DC_DIGB_FAST_TRAINING_COMPLETE_INT 0xF // DIGB - Fast Training Complete DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level +#define DCN_1_0__SRCID__DC_DIGB_FAST_TRAINING_COMPLETE_INT 0xF // DIGB - Fast Training Complete DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level #define DCN_1_0__CTXID__DC_DIGB_FAST_TRAINING_COMPLETE_INT 1 -#define DCN_1_0__SRCID__DC_DIGC_FAST_TRAINING_COMPLETE_INT 0xF // DIGC - Fast Training Complete DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level +#define DCN_1_0__SRCID__DC_DIGC_FAST_TRAINING_COMPLETE_INT 0xF // DIGC - Fast Training Complete DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level #define DCN_1_0__CTXID__DC_DIGC_FAST_TRAINING_COMPLETE_INT 2 -#define DCN_1_0__SRCID__DC_DIGD_FAST_TRAINING_COMPLETE_INT 0xF // DIGD - Fast Training Complete DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level +#define DCN_1_0__SRCID__DC_DIGD_FAST_TRAINING_COMPLETE_INT 0xF // DIGD - Fast Training Complete DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level #define DCN_1_0__CTXID__DC_DIGD_FAST_TRAINING_COMPLETE_INT 3 -#define DCN_1_0__SRCID__DC_DIGE_FAST_TRAINING_COMPLETE_INT 0xF // DIGE - Fast Training Complete DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level +#define DCN_1_0__SRCID__DC_DIGE_FAST_TRAINING_COMPLETE_INT 0xF // DIGE - Fast Training Complete DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level #define DCN_1_0__CTXID__DC_DIGE_FAST_TRAINING_COMPLETE_INT 4 -#define DCN_1_0__SRCID__DC_DIGF_FAST_TRAINING_COMPLETE_INT 0xF // DIGF - Fast Training Complete DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level +#define DCN_1_0__SRCID__DC_DIGF_FAST_TRAINING_COMPLETE_INT 0xF // DIGF - Fast Training Complete DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level #define DCN_1_0__CTXID__DC_DIGF_FAST_TRAINING_COMPLETE_INT 5 -#define DCN_1_0__SRCID__DC_DIGG_FAST_TRAINING_COMPLETE_INT 0xF // DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE19 Level +#define DCN_1_0__SRCID__DC_DIGG_FAST_TRAINING_COMPLETE_INT 0xF // DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE19 Level #define DCN_1_0__CTXID__DC_DIGG_FAST_TRAINING_COMPLETE_INT 6 -#define DCN_1_0__SRCID__DC_DIGH_FAST_TRAINING_COMPLETE_INT 0xF // DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level +#define DCN_1_0__SRCID__DC_DIGH_FAST_TRAINING_COMPLETE_INT 0xF // DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level #define DCN_1_0__CTXID__DC_DIGH_FAST_TRAINING_COMPLETE_INT 7 -#define DCN_1_0__SRCID__DC_AUX1_SW_DONE 0x10 // AUX1 sw done AUX1_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS Level +#define DCN_1_0__SRCID__DC_AUX1_SW_DONE 0x10 // AUX1 sw done AUX1_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS Level #define DCN_1_0__CTXID__DC_AUX1_SW_DONE 0 -#define DCN_1_0__SRCID__DC_AUX1_LS_DONE 0x10 // AUX1 ls done AUX1_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS Level +#define DCN_1_0__SRCID__DC_AUX1_LS_DONE 0x10 // AUX1 ls done AUX1_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS Level #define DCN_1_0__CTXID__DC_AUX1_LS_DONE 1 -#define DCN_1_0__SRCID__DC_AUX2_SW_DONE 0x10 // AUX2 sw done AUX2_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level +#define DCN_1_0__SRCID__DC_AUX2_SW_DONE 0x10 // AUX2 sw done AUX2_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level #define DCN_1_0__CTXID__DC_AUX2_SW_DONE 2 -#define DCN_1_0__SRCID__DC_AUX2_LS_DONE 0x10 // AUX2 ls done AUX2_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level +#define DCN_1_0__SRCID__DC_AUX2_LS_DONE 0x10 // AUX2 ls done AUX2_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level #define DCN_1_0__CTXID__DC_AUX2_LS_DONE 3 -#define DCN_1_0__SRCID__DC_AUX3_SW_DONE 0x10 // AUX3 sw done AUX3_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level +#define DCN_1_0__SRCID__DC_AUX3_SW_DONE 0x10 // AUX3 sw done AUX3_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level #define DCN_1_0__CTXID__DC_AUX3_SW_DONE 4 -#define DCN_1_0__SRCID__DC_AUX3_LS_DONE 0x10 // AUX3 ls done AUX3_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level +#define DCN_1_0__SRCID__DC_AUX3_LS_DONE 0x10 // AUX3 ls done AUX3_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level #define DCN_1_0__CTXID__DC_AUX3_LS_DONE 5 -#define DCN_1_0__SRCID__DC_AUX4_SW_DONE 0x10 // AUX4 sw done AUX4_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level +#define DCN_1_0__SRCID__DC_AUX4_SW_DONE 0x10 // AUX4 sw done AUX4_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level #define DCN_1_0__CTXID__DC_AUX4_SW_DONE 6 -#define DCN_1_0__SRCID__DC_AUX4_LS_DONE 0x10 // AUX4 ls done AUX4_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level +#define DCN_1_0__SRCID__DC_AUX4_LS_DONE 0x10 // AUX4 ls done AUX4_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level #define DCN_1_0__CTXID__DC_AUX4_LS_DONE 7 -#define DCN_1_0__SRCID__DC_AUX5_SW_DONE 0x10 // AUX5 sw done AUX5_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level +#define DCN_1_0__SRCID__DC_AUX5_SW_DONE 0x10 // AUX5 sw done AUX5_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level #define DCN_1_0__CTXID__DC_AUX5_SW_DONE 8 -#define DCN_1_0__SRCID__DC_AUX5_LS_DONE 0x10 // AUX5 ls done AUX5_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level +#define DCN_1_0__SRCID__DC_AUX5_LS_DONE 0x10 // AUX5 ls done AUX5_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level #define DCN_1_0__CTXID__DC_AUX5_LS_DONE 9 -#define DCN_1_0__SRCID__DC_AUX6_SW_DONE 0x10 // AUX6 sw done AUX6_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level +#define DCN_1_0__SRCID__DC_AUX6_SW_DONE 0x10 // AUX6 sw done AUX6_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level #define DCN_1_0__CTXID__DC_AUX6_SW_DONE 10 -#define DCN_1_0__SRCID__DC_AUX6_LS_DONE 0x10 // AUX6 ls done AUX6_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level +#define DCN_1_0__SRCID__DC_AUX6_LS_DONE 0x10 // AUX6 ls done AUX6_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level #define DCN_1_0__CTXID__DC_AUX6_LS_DONE 11 -#define DCN_1_0__SRCID__VGA_CRT_INT 0x10 // VGA Vblank VGA_IHC_VGA_CRT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level +#define DCN_1_0__SRCID__VGA_CRT_INT 0x10 // VGA Vblank VGA_IHC_VGA_CRT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level #define DCN_1_0__CTXID__VGA_CRT_INT 12 -#define DCN_1_0__SRCID__DCCG_PERFCOUNTER2_INT0_STATUS 0x11 // DCCG perfmon2 counter0 interrupt DCCG_PERFMON2_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse +#define DCN_1_0__SRCID__DCCG_PERFCOUNTER2_INT0_STATUS 0x11 // DCCG perfmon2 counter0 interrupt DCCG_PERFMON2_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse #define DCN_1_0__CTXID__DCCG_PERFCOUNTER2_INT0_STATUS 0 -#define DCN_1_0__SRCID__DCCG_PERFCOUNTER2_INT1_STATUS 0x11 // DCCG perfmon2 counter1 interrupt DCCG_PERFMON2_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE10 Level +#define DCN_1_0__SRCID__DCCG_PERFCOUNTER2_INT1_STATUS 0x11 // DCCG perfmon2 counter1 interrupt DCCG_PERFMON2_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE10 Level #define DCN_1_0__CTXID__DCCG_PERFCOUNTER2_INT1_STATUS 1 -#define DCN_1_0__SRCID__BUFMGR_CWB0_IHIF_interrupt 0x12 // mcif_wb_client(buffer manager) MCIF_CWB0_IHIF_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level +#define DCN_1_0__SRCID__BUFMGR_CWB0_IHIF_interrupt 0x12 // mcif_wb_client(buffer manager) MCIF_CWB0_IHIF_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level #define DCN_1_0__CTXID__BUFMGR_CWB0_IHIF_interrupt 0 -#define DCN_1_0__SRCID__BUFMGR_CWB1_IHIF_interrupt 0x12 // mcif_wb_client(buffer manager) MCIF_CWB1_IHIF_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level +#define DCN_1_0__SRCID__BUFMGR_CWB1_IHIF_interrupt 0x12 // mcif_wb_client(buffer manager) MCIF_CWB1_IHIF_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level #define DCN_1_0__CTXID__BUFMGR_CWB1_IHIF_interrupt 1 -#define DCN_1_0__SRCID__MCIF0_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT 0x12 // MCIF WB client(buffer manager) MCIF_DWB0_IHIF_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level +#define DCN_1_0__SRCID__MCIF0_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT 0x12 // MCIF WB client(buffer manager) MCIF_DWB0_IHIF_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level #define DCN_1_0__CTXID__MCIF0_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT 2 -#define DCN_1_0__SRCID__MCIF1_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT 0x12 // MCIF WB client(buffer manager) MCIF_DWB1_IHIF_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level +#define DCN_1_0__SRCID__MCIF1_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT 0x12 // MCIF WB client(buffer manager) MCIF_DWB1_IHIF_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level #define DCN_1_0__CTXID__MCIF1_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT 3 -#define DCN_1_0__SRCID__SISCL0_COEF_RAM_CONFLICT_STATUS 0x12 // WB host conflict interrupt WBSCL0_HOST_CONFLICT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level +#define DCN_1_0__SRCID__SISCL0_COEF_RAM_CONFLICT_STATUS 0x12 // WB host conflict interrupt WBSCL0_HOST_CONFLICT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level #define DCN_1_0__CTXID__SISCL0_COEF_RAM_CONFLICT_STATUS 4 -#define DCN_1_0__SRCID__SISCL0_OVERFLOW_STATUS 0x12 // WB data overflow interrupt WBSCL0_DATA_OVERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level +#define DCN_1_0__SRCID__SISCL0_OVERFLOW_STATUS 0x12 // WB data overflow interrupt WBSCL0_DATA_OVERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level #define DCN_1_0__CTXID__SISCL0_OVERFLOW_STATUS 5 -#define DCN_1_0__SRCID__SISCL1_COEF_RAM_CONFLICT_STATUS 0x12 // WB host conflict interrupt WBSCL1_HOST_CONFLICT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level +#define DCN_1_0__SRCID__SISCL1_COEF_RAM_CONFLICT_STATUS 0x12 // WB host conflict interrupt WBSCL1_HOST_CONFLICT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level #define DCN_1_0__CTXID__SISCL1_COEF_RAM_CONFLICT_STATUS 6 -#define DCN_1_0__SRCID__SISCL1_OVERFLOW_STATUS 0x12 // WB data overflow interrupt WBSCL1_DATA_OVERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level +#define DCN_1_0__SRCID__SISCL1_OVERFLOW_STATUS 0x12 // WB data overflow interrupt WBSCL1_DATA_OVERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level #define DCN_1_0__CTXID__SISCL1_OVERFLOW_STATUS 7 #define DCN_1_0__SRCID__DC_AUX4_GTC_SYNC_LOCK_DONE 0x13 // AUX4 GTC sync lock complete AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level #define DCN_1_0__CTXID__DC_AUX4_GTC_SYNC_LOCK_DONE 0 -#define DCN_1_0__SRCID__DC_AUX4_GTC_SYNC_ERROR 0x13 // AUX4 GTC sync error occurred AUX4_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level +#define DCN_1_0__SRCID__DC_AUX4_GTC_SYNC_ERROR 0x13 // AUX4 GTC sync error occurred AUX4_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level #define DCN_1_0__CTXID__DC_AUX4_GTC_SYNC_ERROR 1 -#define DCN_1_0__SRCID__DC_AUX5_GTC_SYNC_LOCK_DONE 0x13 // AUX5 GTC sync lock complete AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level +#define DCN_1_0__SRCID__DC_AUX5_GTC_SYNC_LOCK_DONE 0x13 // AUX5 GTC sync lock complete AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level #define DCN_1_0__CTXID__DC_AUX5_GTC_SYNC_LOCK_DONE 2 -#define DCN_1_0__SRCID__DC_AUX5_GTC_SYNC_ERROR 0x13 // AUX5 GTC sync error occurred AUX5_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level +#define DCN_1_0__SRCID__DC_AUX5_GTC_SYNC_ERROR 0x13 // AUX5 GTC sync error occurred AUX5_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level #define DCN_1_0__CTXID__DC_AUX5_GTC_SYNC_ERROR 3 -#define DCN_1_0__SRCID__DC_AUX6_GTC_SYNC_LOCK_DONE 0x13 // AUX6 GTC sync lock complete AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level +#define DCN_1_0__SRCID__DC_AUX6_GTC_SYNC_LOCK_DONE 0x13 // AUX6 GTC sync lock complete AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level #define DCN_1_0__CTXID__DC_AUX6_GTC_SYNC_LOCK_DONE 4 -#define DCN_1_0__SRCID__DC_AUX6_GTC_SYNC_ERROR 0x13 // AUX6 GTC sync error occurred AUX6_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level +#define DCN_1_0__SRCID__DC_AUX6_GTC_SYNC_ERROR 0x13 // AUX6 GTC sync error occurred AUX6_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level #define DCN_1_0__CTXID__DC_AUX6_GTC_SYNC_ERROR 5 -#define DCN_1_0__SRCID__DCPG_DCFE0_POWER_UP_INT 0x14 // Display pipe0 power up interrupt DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level +#define DCN_1_0__SRCID__DCPG_DCFE0_POWER_UP_INT 0x14 // Display pipe0 power up interrupt DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level #define DCN_1_0__CTXID__DCPG_DCFE0_POWER_UP_INT 0 -#define DCN_1_0__SRCID__DCPG_DCFE1_POWER_UP_INT 0x14 // Display pipe1 power up interrupt DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level +#define DCN_1_0__SRCID__DCPG_DCFE1_POWER_UP_INT 0x14 // Display pipe1 power up interrupt DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level #define DCN_1_0__CTXID__DCPG_DCFE1_POWER_UP_INT 1 -#define DCN_1_0__SRCID__DCPG_DCFE2_POWER_UP_INT 0x14 // Display pipe2 power up interrupt DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level +#define DCN_1_0__SRCID__DCPG_DCFE2_POWER_UP_INT 0x14 // Display pipe2 power up interrupt DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level #define DCN_1_0__CTXID__DCPG_DCFE2_POWER_UP_INT 2 -#define DCN_1_0__SRCID__DCPG_DCFE3_POWER_UP_INT 0x14 // Display pipe3 power up interrupt DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level +#define DCN_1_0__SRCID__DCPG_DCFE3_POWER_UP_INT 0x14 // Display pipe3 power up interrupt DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level #define DCN_1_0__CTXID__DCPG_DCFE3_POWER_UP_INT 3 -#define DCN_1_0__SRCID__DCPG_DCFE4_POWER_UP_INT 0x14 // Display pipe4 power up interrupt DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level +#define DCN_1_0__SRCID__DCPG_DCFE4_POWER_UP_INT 0x14 // Display pipe4 power up interrupt DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level #define DCN_1_0__CTXID__DCPG_DCFE4_POWER_UP_INT 4 -#define DCN_1_0__SRCID__DCPG_DCFE5_POWER_UP_INT 0x14 // Display pipe5 power up interrupt DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level +#define DCN_1_0__SRCID__DCPG_DCFE5_POWER_UP_INT 0x14 // Display pipe5 power up interrupt DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level #define DCN_1_0__CTXID__DCPG_DCFE5_POWER_UP_INT 5 -#define DCN_1_0__SRCID__DCPG_DCFE6_POWER_UP_INT 0x14 // Display pipe6 power up interrupt DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level +#define DCN_1_0__SRCID__DCPG_DCFE6_POWER_UP_INT 0x14 // Display pipe6 power up interrupt DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level #define DCN_1_0__CTXID__DCPG_DCFE6_POWER_UP_INT 6 -#define DCN_1_0__SRCID__DCPG_DCFE7_POWER_UP_INT 0x14 // Display pipe7 power up interrupt DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level +#define DCN_1_0__SRCID__DCPG_DCFE7_POWER_UP_INT 0x14 // Display pipe7 power up interrupt DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level #define DCN_1_0__CTXID__DCPG_DCFE7_POWER_UP_INT 7 -#define DCN_1_0__SRCID__DCPG_DCFE0_POWER_DOWN_INT 0x14 // Display pipe0 power down interrupt DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level +#define DCN_1_0__SRCID__DCPG_DCFE0_POWER_DOWN_INT 0x14 // Display pipe0 power down interrupt DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level #define DCN_1_0__CTXID__DCPG_DCFE0_POWER_DOWN_INT 8 -#define DCN_1_0__SRCID__DCPG_DCFE1_POWER_DOWN_INT 0x14 // Display pipe1 power down interrupt DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level +#define DCN_1_0__SRCID__DCPG_DCFE1_POWER_DOWN_INT 0x14 // Display pipe1 power down interrupt DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level #define DCN_1_0__CTXID__DCPG_DCFE1_POWER_DOWN_INT 9 -#define DCN_1_0__SRCID__DCPG_DCFE2_POWER_DOWN_INT 0x14 // Display pipe2 power down interrupt DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level +#define DCN_1_0__SRCID__DCPG_DCFE2_POWER_DOWN_INT 0x14 // Display pipe2 power down interrupt DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level #define DCN_1_0__CTXID__DCPG_DCFE2_POWER_DOWN_INT 10 -#define DCN_1_0__SRCID__DCPG_DCFE3_POWER_DOWN_INT 0x14 // Display pipe3 power down interrupt DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level +#define DCN_1_0__SRCID__DCPG_DCFE3_POWER_DOWN_INT 0x14 // Display pipe3 power down interrupt DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level #define DCN_1_0__CTXID__DCPG_DCFE3_POWER_DOWN_INT 11 -#define DCN_1_0__SRCID__DCPG_DCFE4_POWER_DOWN_INT 0x14 // Display pipe4 power down interrupt DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level +#define DCN_1_0__SRCID__DCPG_DCFE4_POWER_DOWN_INT 0x14 // Display pipe4 power down interrupt DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level #define DCN_1_0__CTXID__DCPG_DCFE4_POWER_DOWN_INT 12 -#define DCN_1_0__SRCID__DCPG_DCFE5_POWER_DOWN_INT 0x14 // Display pipe5 power down interrupt DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level +#define DCN_1_0__SRCID__DCPG_DCFE5_POWER_DOWN_INT 0x14 // Display pipe5 power down interrupt DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level #define DCN_1_0__CTXID__DCPG_DCFE5_POWER_DOWN_INT 13 -#define DCN_1_0__SRCID__DCPG_DCFE6_POWER_DOWN_INT 0x14 // Display pipe6 power down interrupt DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level +#define DCN_1_0__SRCID__DCPG_DCFE6_POWER_DOWN_INT 0x14 // Display pipe6 power down interrupt DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level #define DCN_1_0__CTXID__DCPG_DCFE6_POWER_DOWN_INT 14 -#define DCN_1_0__SRCID__DCPG_DCFE7_POWER_DOWN_INT 0x14 // Display pipe7 power down interrupt DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level +#define DCN_1_0__SRCID__DCPG_DCFE7_POWER_DOWN_INT 0x14 // Display pipe7 power down interrupt DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level #define DCN_1_0__CTXID__DCPG_DCFE7_POWER_DOWN_INT 15 -#define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg0_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG0_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level +#define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg0_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG0_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level #define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg0_latch_int 0 -#define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg1_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG1_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level +#define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg1_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG1_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level #define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg1_latch_int 1 -#define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg2_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG2_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level +#define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg2_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG2_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level #define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg2_latch_int 2 -#define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg3_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG3_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level +#define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg3_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG3_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level #define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg3_latch_int 3 -#define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg4_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG4_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level +#define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg4_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG4_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level #define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg4_latch_int 4 -#define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg5_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG5_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level +#define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg5_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG5_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level #define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg5_latch_int 5 -#define DCN_1_0__SRCID__OPTC0_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC1_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS Level +#define DCN_1_0__SRCID__OPTC0_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC1_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS Level #define DCN_1_0__CTXID__OPTC0_DATA_UNDERFLOW_INT 6 -#define DCN_1_0__SRCID__OPTC1_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC2_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level +#define DCN_1_0__SRCID__OPTC1_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC2_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level #define DCN_1_0__CTXID__OPTC1_DATA_UNDERFLOW_INT 7 -#define DCN_1_0__SRCID__OPTC2_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC3_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level +#define DCN_1_0__SRCID__OPTC2_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC3_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level #define DCN_1_0__CTXID__OPTC2_DATA_UNDERFLOW_INT 8 -#define DCN_1_0__SRCID__OPTC3_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC4_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level +#define DCN_1_0__SRCID__OPTC3_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC4_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level #define DCN_1_0__CTXID__OPTC3_DATA_UNDERFLOW_INT 9 -#define DCN_1_0__SRCID__OPTC4_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC5_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level +#define DCN_1_0__SRCID__OPTC4_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC5_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level #define DCN_1_0__CTXID__OPTC4_DATA_UNDERFLOW_INT 10 -#define DCN_1_0__SRCID__OPTC5_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC6_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level +#define DCN_1_0__SRCID__OPTC5_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC6_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level #define DCN_1_0__CTXID__OPTC5_DATA_UNDERFLOW_INT 11 -#define DCN_1_0__SRCID__MPCC0_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC0_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level +#define DCN_1_0__SRCID__MPCC0_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC0_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level #define DCN_1_0__CTXID__MPCC0_STALL_INTERRUPT 0 -#define DCN_1_0__SRCID__MPCC1_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC1_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level +#define DCN_1_0__SRCID__MPCC1_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC1_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level #define DCN_1_0__CTXID__MPCC1_STALL_INTERRUPT 1 -#define DCN_1_0__SRCID__MPCC2_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC2_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level +#define DCN_1_0__SRCID__MPCC2_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC2_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level #define DCN_1_0__CTXID__MPCC2_STALL_INTERRUPT 2 -#define DCN_1_0__SRCID__MPCC3_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC3_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level +#define DCN_1_0__SRCID__MPCC3_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC3_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level #define DCN_1_0__CTXID__MPCC3_STALL_INTERRUPT 3 -#define DCN_1_0__SRCID__MPCC4_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC4_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level +#define DCN_1_0__SRCID__MPCC4_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC4_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level #define DCN_1_0__CTXID__MPCC4_STALL_INTERRUPT 4 -#define DCN_1_0__SRCID__MPCC5_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC5_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level +#define DCN_1_0__SRCID__MPCC5_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC5_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level #define DCN_1_0__CTXID__MPCC5_STALL_INTERRUPT 5 -#define DCN_1_0__SRCID__MPCC6_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC6_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level +#define DCN_1_0__SRCID__MPCC6_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC6_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level #define DCN_1_0__CTXID__MPCC6_STALL_INTERRUPT 6 -#define DCN_1_0__SRCID__MPCC7_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC7_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level +#define DCN_1_0__SRCID__MPCC7_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC7_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level #define DCN_1_0__CTXID__MPCC7_STALL_INTERRUPT 7 -#define DCN_1_0__SRCID__OTG1_CPU_SS_INT 0x17 // D1: OTG Static Screen interrupt OTG1_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__SRCID__OTG1_CPU_SS_INT 0x17 // D1: OTG Static Screen interrupt OTG1_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse #define DCN_1_0__CTXID__OTG1_CPU_SS_INT 0 -#define DCN_1_0__SRCID__OTG1_RANGE_TIMING_UPDATE 0x17 // D1 : OTG range timing OTG1_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse +#define DCN_1_0__SRCID__OTG1_RANGE_TIMING_UPDATE 0x17 // D1 : OTG range timing OTG1_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse #define DCN_1_0__CTXID__OTG1_RANGE_TIMING_UPDATE 1 -#define DCN_1_0__SRCID__OTG2_CPU_SS_INT 0x17 // D2 : OTG Static Screen interrupt OTG2_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__SRCID__OTG2_CPU_SS_INT 0x17 // D2 : OTG Static Screen interrupt OTG2_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse #define DCN_1_0__CTXID__OTG2_CPU_SS_INT 2 -#define DCN_1_0__SRCID__OTG2_RANGE_TIMING_UPDATE 0x17 // D2 : OTG range timing OTG2_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse +#define DCN_1_0__SRCID__OTG2_RANGE_TIMING_UPDATE 0x17 // D2 : OTG range timing OTG2_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse #define DCN_1_0__CTXID__OTG2_RANGE_TIMING_UPDATE 3 -#define DCN_1_0__SRCID__OTG3_CPU_SS_INT 0x17 // D3 : OTG Static Screen interrupt OTG3_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__SRCID__OTG3_CPU_SS_INT 0x17 // D3 : OTG Static Screen interrupt OTG3_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse #define DCN_1_0__CTXID__OTG3_CPU_SS_INT 4 -#define DCN_1_0__SRCID__OTG3_RANGE_TIMING_UPDATE 0x17 // D3 : OTG range timing OTG3_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse +#define DCN_1_0__SRCID__OTG3_RANGE_TIMING_UPDATE 0x17 // D3 : OTG range timing OTG3_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse #define DCN_1_0__CTXID__OTG3_RANGE_TIMING_UPDATE 5 -#define DCN_1_0__SRCID__OTG4_CPU_SS_INT 0x17 // D4 : OTG Static Screen interrupt OTG4_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__SRCID__OTG4_CPU_SS_INT 0x17 // D4 : OTG Static Screen interrupt OTG4_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse #define DCN_1_0__CTXID__OTG4_CPU_SS_INT 6 -#define DCN_1_0__SRCID__OTG4_RANGE_TIMING_UPDATE 0x17 // D4 : OTG range timing OTG4_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse +#define DCN_1_0__SRCID__OTG4_RANGE_TIMING_UPDATE 0x17 // D4 : OTG range timing OTG4_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse #define DCN_1_0__CTXID__OTG4_RANGE_TIMING_UPDATE 7 -#define DCN_1_0__SRCID__OTG5_CPU_SS_INT 0x17 // D5 : OTG Static Screen interrupt OTG5_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__SRCID__OTG5_CPU_SS_INT 0x17 // D5 : OTG Static Screen interrupt OTG5_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse #define DCN_1_0__CTXID__OTG5_CPU_SS_INT 8 -#define DCN_1_0__SRCID__OTG5_RANGE_TIMING_UPDATE 0x17 // D5 : OTG range timing OTG5_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse +#define DCN_1_0__SRCID__OTG5_RANGE_TIMING_UPDATE 0x17 // D5 : OTG range timing OTG5_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse #define DCN_1_0__CTXID__OTG5_RANGE_TIMING_UPDATE 9 -#define DCN_1_0__SRCID__OTG6_CPU_SS_INT 0x17 // D6 : OTG Static Screen interrupt OTG6_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__SRCID__OTG6_CPU_SS_INT 0x17 // D6 : OTG Static Screen interrupt OTG6_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse #define DCN_1_0__CTXID__OTG6_CPU_SS_INT 10 -#define DCN_1_0__SRCID__OTG6_RANGE_TIMING_UPDATE 0x17 // D6 : OTG range timing OTG6_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse +#define DCN_1_0__SRCID__OTG6_RANGE_TIMING_UPDATE 0x17 // D6 : OTG range timing OTG6_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse #define DCN_1_0__CTXID__OTG6_RANGE_TIMING_UPDATE 11 #define DCN_1_0__SRCID__DC_D1_OTG_V_UPDATE 0x18 // D1 : OTG V_update OTG1_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse @@ -568,472 +568,472 @@ #define DCN_1_0__SRCID__DC_D5_OTG_V_UPDATE 0x1C // D5 : OTG V_update OTG5_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse #define DCN_1_0__SRCID__DC_D6_OTG_V_UPDATE 0x1D // D6 : OTG V_update OTG6_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse -#define DCN_1_0__SRCID__DC_D1_OTG_SNAPSHOT 0x1E // D1 : OTG snapshot OTG1_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse +#define DCN_1_0__SRCID__DC_D1_OTG_SNAPSHOT 0x1E // D1 : OTG snapshot OTG1_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse #define DCN_1_0__CTXID__DC_D1_OTG_SNAPSHOT 0 -#define DCN_1_0__SRCID__DC_D1_FORCE_CNT_W 0x1E // D1 : Force - count--w OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse +#define DCN_1_0__SRCID__DC_D1_FORCE_CNT_W 0x1E // D1 : Force - count--w OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse #define DCN_1_0__CTXID__DC_D1_FORCE_CNT_W 1 -#define DCN_1_0__SRCID__DC_D1_FORCE_VSYNC_NXT_LINE 0x1E // D1 : Force - Vsync - next - line OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse +#define DCN_1_0__SRCID__DC_D1_FORCE_VSYNC_NXT_LINE 0x1E // D1 : Force - Vsync - next - line OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse #define DCN_1_0__CTXID__DC_D1_FORCE_VSYNC_NXT_LINE 2 -#define DCN_1_0__SRCID__DC_D1_OTG_EXTT_TRG_A 0x1E // D1 : OTG external trigger A OTG1_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse +#define DCN_1_0__SRCID__DC_D1_OTG_EXTT_TRG_A 0x1E // D1 : OTG external trigger A OTG1_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse #define DCN_1_0__CTXID__DC_D1_OTG_EXTT_TRG_A 3 -#define DCN_1_0__SRCID__DC_D1_OTG_EXTT_TRG_B 0x1E // D1 : OTG external trigger B OTG1_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse +#define DCN_1_0__SRCID__DC_D1_OTG_EXTT_TRG_B 0x1E // D1 : OTG external trigger B OTG1_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse #define DCN_1_0__CTXID__DC_D1_OTG_EXTT_TRG_B 4 -#define DCN_1_0__SRCID__DC_D1_OTG_GSL_VSYNC_GAP 0x1E // D1 : gsl_vsync_gap_interrupt_frame_delay OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__SRCID__DC_D1_OTG_GSL_VSYNC_GAP 0x1E // D1 : gsl_vsync_gap_interrupt_frame_delay OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse #define DCN_1_0__CTXID__DC_D1_OTG_GSL_VSYNC_GAP 5 -#define DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL 0x1E // D1 : OTG vertical interrupt 0 OTG1_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse +#define DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL 0x1E // D1 : OTG vertical interrupt 0 OTG1_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse #define DCN_1_0__CTXID__OTG1_VERTICAL_INTERRUPT0_CONTROL 6 -#define DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT1_CONTROL 0x1E // D1 : OTG vertical interrupt 1 OTG1_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse +#define DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT1_CONTROL 0x1E // D1 : OTG vertical interrupt 1 OTG1_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse #define DCN_1_0__CTXID__OTG1_VERTICAL_INTERRUPT1_CONTROL 7 -#define DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT2_CONTROL 0x1E // D1 : OTG vertical interrupt 2 OTG1_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse +#define DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT2_CONTROL 0x1E // D1 : OTG vertical interrupt 2 OTG1_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse #define DCN_1_0__CTXID__OTG1_VERTICAL_INTERRUPT2_CONTROL 8 -#define DCN_1_0__SRCID__OTG1_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1E // D1 : OTG ext sync loss interrupt OTG1_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse +#define DCN_1_0__SRCID__OTG1_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1E // D1 : OTG ext sync loss interrupt OTG1_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse #define DCN_1_0__CTXID__OTG1_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 -#define DCN_1_0__SRCID__OTG1_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1E // D1 : OTG ext sync interrupt OTG1_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse +#define DCN_1_0__SRCID__OTG1_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1E // D1 : OTG ext sync interrupt OTG1_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse #define DCN_1_0__CTXID__OTG1_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 -#define DCN_1_0__SRCID__OTG1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1E // D1 : OTG ext sync signal interrupt OTG1_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse +#define DCN_1_0__SRCID__OTG1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1E // D1 : OTG ext sync signal interrupt OTG1_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse #define DCN_1_0__CTXID__OTG1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 -#define DCN_1_0__SRCID__OTG1_SET_VTOTAL_MIN_EVENT_INT 0x1E // D1 : OTG DRR event occurred interrupt OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS Level / Pulse +#define DCN_1_0__SRCID__OTG1_SET_VTOTAL_MIN_EVENT_INT 0x1E // D1 : OTG DRR event occurred interrupt OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS Level / Pulse #define DCN_1_0__CTXID__OTG1_SET_VTOTAL_MIN_EVENT_INT 12 -#define DCN_1_0__SRCID__DC_D2_OTG_SNAPSHOT 0x1F // D2 : OTG snapshot OTG2_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse +#define DCN_1_0__SRCID__DC_D2_OTG_SNAPSHOT 0x1F // D2 : OTG snapshot OTG2_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse #define DCN_1_0__CTXID__DC_D2_OTG_SNAPSHOT 0 -#define DCN_1_0__SRCID__DC_D2_FORCE_CNT_W 0x1F // D2 : Force - count--w OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse +#define DCN_1_0__SRCID__DC_D2_FORCE_CNT_W 0x1F // D2 : Force - count--w OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse #define DCN_1_0__CTXID__DC_D2_FORCE_CNT_W 1 -#define DCN_1_0__SRCID__DC_D2_FORCE_VSYNC_NXT_LINE 0x1F // D2 : Force - Vsync - next - line OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse +#define DCN_1_0__SRCID__DC_D2_FORCE_VSYNC_NXT_LINE 0x1F // D2 : Force - Vsync - next - line OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse #define DCN_1_0__CTXID__DC_D2_FORCE_VSYNC_NXT_LINE 2 -#define DCN_1_0__SRCID__DC_D2_OTG_EXTT_TRG_A 0x1F // D2 : OTG external trigger A OTG2_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse +#define DCN_1_0__SRCID__DC_D2_OTG_EXTT_TRG_A 0x1F // D2 : OTG external trigger A OTG2_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse #define DCN_1_0__CTXID__DC_D2_OTG_EXTT_TRG_A 3 -#define DCN_1_0__SRCID__DC_D2_OTG_EXTT_TRG_B 0x1F // D2 : OTG external trigger B OTG2_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse +#define DCN_1_0__SRCID__DC_D2_OTG_EXTT_TRG_B 0x1F // D2 : OTG external trigger B OTG2_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse #define DCN_1_0__CTXID__DC_D2_OTG_EXTT_TRG_B 4 -#define DCN_1_0__SRCID__DC_D2_OTG_GSL_VSYNC_GAP 0x1F // D2 : gsl_vsync_gap_interrupt_frame_delay OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__SRCID__DC_D2_OTG_GSL_VSYNC_GAP 0x1F // D2 : gsl_vsync_gap_interrupt_frame_delay OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse #define DCN_1_0__CTXID__DC_D2_OTG_GSL_VSYNC_GAP 5 -#define DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL 0x1F // D2 : OTG vertical interrupt 0 OTG2_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse +#define DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL 0x1F // D2 : OTG vertical interrupt 0 OTG2_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse #define DCN_1_0__CTXID__OTG2_VERTICAL_INTERRUPT0_CONTROL 6 -#define DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT1_CONTROL 0x1F // D2 : OTG vertical interrupt 1 OTG2_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse +#define DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT1_CONTROL 0x1F // D2 : OTG vertical interrupt 1 OTG2_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse #define DCN_1_0__CTXID__OTG2_VERTICAL_INTERRUPT1_CONTROL 7 -#define DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT2_CONTROL 0x1F // D2 : OTG vertical interrupt 2 OTG2_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse +#define DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT2_CONTROL 0x1F // D2 : OTG vertical interrupt 2 OTG2_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse #define DCN_1_0__CTXID__OTG2_VERTICAL_INTERRUPT2_CONTROL 8 -#define DCN_1_0__SRCID__OTG2_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1F // D2 : OTG ext sync loss interrupt OTG2_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse +#define DCN_1_0__SRCID__OTG2_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1F // D2 : OTG ext sync loss interrupt OTG2_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse #define DCN_1_0__CTXID__OTG2_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 -#define DCN_1_0__SRCID__OTG2_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1F // D2 : OTG ext sync interrupt OTG2_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse +#define DCN_1_0__SRCID__OTG2_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1F // D2 : OTG ext sync interrupt OTG2_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse #define DCN_1_0__CTXID__OTG2_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 -#define DCN_1_0__SRCID__OTG2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1F // D2 : OTG ext sync signal interrupt OTG2_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse +#define DCN_1_0__SRCID__OTG2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1F // D2 : OTG ext sync signal interrupt OTG2_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse #define DCN_1_0__CTXID__OTG2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 -#define DCN_1_0__SRCID__OTG2_SET_VTOTAL_MIN_EVENT_INT 0x1F // D2 : OTG DRR event occurred interrupt OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse +#define DCN_1_0__SRCID__OTG2_SET_VTOTAL_MIN_EVENT_INT 0x1F // D2 : OTG DRR event occurred interrupt OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse #define DCN_1_0__CTXID__OTG2_SET_VTOTAL_MIN_EVENT_INT 12 -#define DCN_1_0__SRCID__DC_D3_OTG_SNAPSHOT 0x20 // D3 : OTG snapshot OTG3_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse +#define DCN_1_0__SRCID__DC_D3_OTG_SNAPSHOT 0x20 // D3 : OTG snapshot OTG3_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse #define DCN_1_0__CTXID__DC_D3_OTG_SNAPSHOT 0 -#define DCN_1_0__SRCID__DC_D3_FORCE_CNT_W 0x20 // D3 : Force - count--w OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse +#define DCN_1_0__SRCID__DC_D3_FORCE_CNT_W 0x20 // D3 : Force - count--w OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse #define DCN_1_0__CTXID__DC_D3_FORCE_CNT_W 1 -#define DCN_1_0__SRCID__DC_D3_FORCE_VSYNC_NXT_LINE 0x20 // D3 : Force - Vsync - next - line OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse +#define DCN_1_0__SRCID__DC_D3_FORCE_VSYNC_NXT_LINE 0x20 // D3 : Force - Vsync - next - line OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse #define DCN_1_0__CTXID__DC_D3_FORCE_VSYNC_NXT_LINE 2 -#define DCN_1_0__SRCID__DC_D3_OTG_EXTT_TRG_A 0x20 // D3 : OTG external trigger A OTG3_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse +#define DCN_1_0__SRCID__DC_D3_OTG_EXTT_TRG_A 0x20 // D3 : OTG external trigger A OTG3_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse #define DCN_1_0__CTXID__DC_D3_OTG_EXTT_TRG_A 3 -#define DCN_1_0__SRCID__DC_D3_OTG_EXTT_TRG_B 0x20 // D3 : OTG external trigger B OTG3_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse +#define DCN_1_0__SRCID__DC_D3_OTG_EXTT_TRG_B 0x20 // D3 : OTG external trigger B OTG3_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse #define DCN_1_0__CTXID__DC_D3_OTG_EXTT_TRG_B 4 -#define DCN_1_0__SRCID__DC_D3_OTG_GSL_VSYNC_GAP 0x20 // D3 : gsl_vsync_gap_interrupt_frame_delay OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__SRCID__DC_D3_OTG_GSL_VSYNC_GAP 0x20 // D3 : gsl_vsync_gap_interrupt_frame_delay OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse #define DCN_1_0__CTXID__DC_D3_OTG_GSL_VSYNC_GAP 5 -#define DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL 0x20 // D3 : OTG vertical interrupt 0 OTG3_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse +#define DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL 0x20 // D3 : OTG vertical interrupt 0 OTG3_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse #define DCN_1_0__CTXID__OTG3_VERTICAL_INTERRUPT0_CONTROL 6 -#define DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT1_CONTROL 0x20 // D3 : OTG vertical interrupt 1 OTG3_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse +#define DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT1_CONTROL 0x20 // D3 : OTG vertical interrupt 1 OTG3_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse #define DCN_1_0__CTXID__OTG3_VERTICAL_INTERRUPT1_CONTROL 7 -#define DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT2_CONTROL 0x20 // D3 : OTG vertical interrupt 2 OTG3_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse +#define DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT2_CONTROL 0x20 // D3 : OTG vertical interrupt 2 OTG3_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse #define DCN_1_0__CTXID__OTG3_VERTICAL_INTERRUPT2_CONTROL 8 -#define DCN_1_0__SRCID__OTG3_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x20 // D3 : OTG ext sync loss interrupt OTG3_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse +#define DCN_1_0__SRCID__OTG3_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x20 // D3 : OTG ext sync loss interrupt OTG3_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse #define DCN_1_0__CTXID__OTG3_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 -#define DCN_1_0__SRCID__OTG3_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x20 // D3 : OTG ext sync interrupt OTG3_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse +#define DCN_1_0__SRCID__OTG3_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x20 // D3 : OTG ext sync interrupt OTG3_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse #define DCN_1_0__CTXID__OTG3_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 -#define DCN_1_0__SRCID__OTG3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x20 // D3 : OTG ext sync signal interrupt OTG3_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse +#define DCN_1_0__SRCID__OTG3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x20 // D3 : OTG ext sync signal interrupt OTG3_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse #define DCN_1_0__CTXID__OTG3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 -#define DCN_1_0__SRCID__OTG3_SET_VTOTAL_MIN_EVENT_INT 0x20 // D3 : OTG DRR event occurred interrupt OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse +#define DCN_1_0__SRCID__OTG3_SET_VTOTAL_MIN_EVENT_INT 0x20 // D3 : OTG DRR event occurred interrupt OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse #define DCN_1_0__CTXID__OTG3_SET_VTOTAL_MIN_EVENT_INT 12 -#define DCN_1_0__SRCID__DC_D4_OTG_SNAPSHOT 0x21 // D4 : OTG snapshot OTG4_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse +#define DCN_1_0__SRCID__DC_D4_OTG_SNAPSHOT 0x21 // D4 : OTG snapshot OTG4_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse #define DCN_1_0__CTXID__DC_D4_OTG_SNAPSHOT 0 -#define DCN_1_0__SRCID__DC_D4_FORCE_CNT_W 0x21 // D4 : Force - count--w OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse +#define DCN_1_0__SRCID__DC_D4_FORCE_CNT_W 0x21 // D4 : Force - count--w OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse #define DCN_1_0__CTXID__DC_D4_FORCE_CNT_W 1 -#define DCN_1_0__SRCID__DC_D4_FORCE_VSYNC_NXT_LINE 0x21 // D4 : Force - Vsync - next - line OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse +#define DCN_1_0__SRCID__DC_D4_FORCE_VSYNC_NXT_LINE 0x21 // D4 : Force - Vsync - next - line OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse #define DCN_1_0__CTXID__DC_D4_FORCE_VSYNC_NXT_LINE 2 -#define DCN_1_0__SRCID__DC_D4_OTG_EXTT_TRG_A 0x21 // D4 : OTG external trigger A OTG4_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse +#define DCN_1_0__SRCID__DC_D4_OTG_EXTT_TRG_A 0x21 // D4 : OTG external trigger A OTG4_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse #define DCN_1_0__CTXID__DC_D4_OTG_EXTT_TRG_A 3 -#define DCN_1_0__SRCID__DC_D4_OTG_EXTT_TRG_B 0x21 // D4 : OTG external trigger B OTG4_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse +#define DCN_1_0__SRCID__DC_D4_OTG_EXTT_TRG_B 0x21 // D4 : OTG external trigger B OTG4_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse #define DCN_1_0__CTXID__DC_D4_OTG_EXTT_TRG_B 4 -#define DCN_1_0__SRCID__DC_D4_OTG_GSL_VSYNC_GAP 0x21 // D4 : gsl_vsync_gap_interrupt_frame_delay OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__SRCID__DC_D4_OTG_GSL_VSYNC_GAP 0x21 // D4 : gsl_vsync_gap_interrupt_frame_delay OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse #define DCN_1_0__CTXID__DC_D4_OTG_GSL_VSYNC_GAP 5 -#define DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL 0x21 // D4 : OTG vertical interrupt 0 OTG4_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse +#define DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL 0x21 // D4 : OTG vertical interrupt 0 OTG4_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse #define DCN_1_0__CTXID__OTG4_VERTICAL_INTERRUPT0_CONTROL 6 -#define DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT1_CONTROL 0x21 // D4 : OTG vertical interrupt 1 OTG4_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse +#define DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT1_CONTROL 0x21 // D4 : OTG vertical interrupt 1 OTG4_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse #define DCN_1_0__CTXID__OTG4_VERTICAL_INTERRUPT1_CONTROL 7 -#define DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT2_CONTROL 0x21 // D4 : OTG vertical interrupt 2 OTG4_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse +#define DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT2_CONTROL 0x21 // D4 : OTG vertical interrupt 2 OTG4_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse #define DCN_1_0__CTXID__OTG4_VERTICAL_INTERRUPT2_CONTROL 8 -#define DCN_1_0__SRCID__OTG4_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x21 // D4 : OTG ext sync loss interrupt OTG4_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse +#define DCN_1_0__SRCID__OTG4_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x21 // D4 : OTG ext sync loss interrupt OTG4_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse #define DCN_1_0__CTXID__OTG4_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 -#define DCN_1_0__SRCID__OTG4_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x21 // D4 : OTG ext sync interrupt OTG4_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse +#define DCN_1_0__SRCID__OTG4_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x21 // D4 : OTG ext sync interrupt OTG4_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse #define DCN_1_0__CTXID__OTG4_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 -#define DCN_1_0__SRCID__OTG4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x21 // D4 : OTG ext sync signal interrupt OTG4_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse +#define DCN_1_0__SRCID__OTG4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x21 // D4 : OTG ext sync signal interrupt OTG4_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse #define DCN_1_0__CTXID__OTG4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 -#define DCN_1_0__SRCID__OTG4_SET_VTOTAL_MIN_EVENT_INT 0x21 // D4 : OTG DRR event occurred interrupt OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse +#define DCN_1_0__SRCID__OTG4_SET_VTOTAL_MIN_EVENT_INT 0x21 // D4 : OTG DRR event occurred interrupt OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse #define DCN_1_0__CTXID__OTG4_SET_VTOTAL_MIN_EVENT_INT 12 -#define DCN_1_0__SRCID__DC_D5_OTG_SNAPSHOT 0x22 // D5 : OTG snapshot OTG5_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse +#define DCN_1_0__SRCID__DC_D5_OTG_SNAPSHOT 0x22 // D5 : OTG snapshot OTG5_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse #define DCN_1_0__CTXID__DC_D5_OTG_SNAPSHOT 0 -#define DCN_1_0__SRCID__DC_D5_FORCE_CNT_W 0x22 // D5 : Force - count--w OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse +#define DCN_1_0__SRCID__DC_D5_FORCE_CNT_W 0x22 // D5 : Force - count--w OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse #define DCN_1_0__CTXID__DC_D5_FORCE_CNT_W 1 -#define DCN_1_0__SRCID__DC_D5_FORCE_VSYNC_NXT_LINE 0x22 // D5 : Force - Vsync - next - line OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse +#define DCN_1_0__SRCID__DC_D5_FORCE_VSYNC_NXT_LINE 0x22 // D5 : Force - Vsync - next - line OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse #define DCN_1_0__CTXID__DC_D5_FORCE_VSYNC_NXT_LINE 2 -#define DCN_1_0__SRCID__DC_D5_OTG_EXTT_TRG_A 0x22 // D5 : OTG external trigger A OTG5_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse +#define DCN_1_0__SRCID__DC_D5_OTG_EXTT_TRG_A 0x22 // D5 : OTG external trigger A OTG5_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse #define DCN_1_0__CTXID__DC_D5_OTG_EXTT_TRG_A 3 -#define DCN_1_0__SRCID__DC_D5_OTG_EXTT_TRG_B 0x22 // D5 : OTG external trigger B OTG5_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse +#define DCN_1_0__SRCID__DC_D5_OTG_EXTT_TRG_B 0x22 // D5 : OTG external trigger B OTG5_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse #define DCN_1_0__CTXID__DC_D5_OTG_EXTT_TRG_B 4 -#define DCN_1_0__SRCID__DC_D5_OTG_GSL_VSYNC_GAP 0x22 // D5 : gsl_vsync_gap_interrupt_frame_delay OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__SRCID__DC_D5_OTG_GSL_VSYNC_GAP 0x22 // D5 : gsl_vsync_gap_interrupt_frame_delay OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse #define DCN_1_0__CTXID__DC_D5_OTG_GSL_VSYNC_GAP 5 -#define DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL 0x22 // D5 : OTG vertical interrupt 0 OTG5_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse +#define DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL 0x22 // D5 : OTG vertical interrupt 0 OTG5_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse #define DCN_1_0__CTXID__OTG5_VERTICAL_INTERRUPT0_CONTROL 6 -#define DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT1_CONTROL 0x22 // D5 : OTG vertical interrupt 1 OTG5_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse +#define DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT1_CONTROL 0x22 // D5 : OTG vertical interrupt 1 OTG5_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse #define DCN_1_0__CTXID__OTG5_VERTICAL_INTERRUPT1_CONTROL 7 -#define DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT2_CONTROL 0x22 // D5 : OTG vertical interrupt 2 OTG5_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse +#define DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT2_CONTROL 0x22 // D5 : OTG vertical interrupt 2 OTG5_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse #define DCN_1_0__CTXID__OTG5_VERTICAL_INTERRUPT2_CONTROL 8 -#define DCN_1_0__SRCID__OTG5_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x22 // D5 : OTG ext sync loss interrupt OTG5_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse +#define DCN_1_0__SRCID__OTG5_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x22 // D5 : OTG ext sync loss interrupt OTG5_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse #define DCN_1_0__CTXID__OTG5_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 -#define DCN_1_0__SRCID__OTG5_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x22 // D5 : OTG ext sync interrupt OTG5_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse +#define DCN_1_0__SRCID__OTG5_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x22 // D5 : OTG ext sync interrupt OTG5_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse #define DCN_1_0__CTXID__OTG5_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 -#define DCN_1_0__SRCID__OTG5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x22 // D5 : OTG ext sync signal interrupt OTG5_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse +#define DCN_1_0__SRCID__OTG5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x22 // D5 : OTG ext sync signal interrupt OTG5_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse #define DCN_1_0__CTXID__OTG5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 -#define DCN_1_0__SRCID__OTG5_SET_VTOTAL_MIN_EVENT_INT 0x22 // D5 : OTG DRR event occurred interrupt OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse +#define DCN_1_0__SRCID__OTG5_SET_VTOTAL_MIN_EVENT_INT 0x22 // D5 : OTG DRR event occurred interrupt OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse #define DCN_1_0__CTXID__OTG5_SET_VTOTAL_MIN_EVENT_INT 12 -#define DCN_1_0__SRCID__DC_D1_VBLANK 0x23 // D1 : VBlank HUBP0_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse +#define DCN_1_0__SRCID__DC_D1_VBLANK 0x23 // D1 : VBlank HUBP0_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse #define DCN_1_0__CTXID__DC_D1_VBLANK 0 -#define DCN_1_0__SRCID__DC_D1_VLINE1 0x23 // D1 : Vline HUBP0_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse +#define DCN_1_0__SRCID__DC_D1_VLINE1 0x23 // D1 : Vline HUBP0_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse #define DCN_1_0__CTXID__DC_D1_VLINE1 1 -#define DCN_1_0__SRCID__DC_D1_VLINE2 0x23 // D1 : Vline2 HUBP0_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse +#define DCN_1_0__SRCID__DC_D1_VLINE2 0x23 // D1 : Vline2 HUBP0_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse #define DCN_1_0__CTXID__DC_D1_VLINE2 2 -#define DCN_1_0__SRCID__DC_D2_VBLANK 0x23 // D2 : Vblank HUBP1_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse +#define DCN_1_0__SRCID__DC_D2_VBLANK 0x23 // D2 : Vblank HUBP1_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse #define DCN_1_0__CTXID__DC_D2_VBLANK 3 -#define DCN_1_0__SRCID__DC_D2_VLINE1 0x23 // D2 : Vline HUBP1_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse +#define DCN_1_0__SRCID__DC_D2_VLINE1 0x23 // D2 : Vline HUBP1_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse #define DCN_1_0__CTXID__DC_D2_VLINE1 4 -#define DCN_1_0__SRCID__DC_D2_VLINE2 0x23 // D2 : Vline2 HUBP1_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse +#define DCN_1_0__SRCID__DC_D2_VLINE2 0x23 // D2 : Vline2 HUBP1_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse #define DCN_1_0__CTXID__DC_D2_VLINE2 5 -#define DCN_1_0__SRCID__HUBP0_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP0_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level +#define DCN_1_0__SRCID__HUBP0_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP0_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level #define DCN_1_0__CTXID__HUBP0_IHC_VM_CONTEXT_ERROR 6 -#define DCN_1_0__SRCID__HUBP1_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP1_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level +#define DCN_1_0__SRCID__HUBP1_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP1_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level #define DCN_1_0__CTXID__HUBP1_IHC_VM_CONTEXT_ERROR 7 -#define DCN_1_0__SRCID__HUBP2_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP2_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level +#define DCN_1_0__SRCID__HUBP2_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP2_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level #define DCN_1_0__CTXID__HUBP2_IHC_VM_CONTEXT_ERROR 8 -#define DCN_1_0__SRCID__HUBP3_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP3_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level +#define DCN_1_0__SRCID__HUBP3_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP3_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level #define DCN_1_0__CTXID__HUBP3_IHC_VM_CONTEXT_ERROR 9 -#define DCN_1_0__SRCID__HUBP4_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP4_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level +#define DCN_1_0__SRCID__HUBP4_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP4_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level #define DCN_1_0__CTXID__HUBP4_IHC_VM_CONTEXT_ERROR 10 -#define DCN_1_0__SRCID__HUBP5_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP5_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level +#define DCN_1_0__SRCID__HUBP5_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP5_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level #define DCN_1_0__CTXID__HUBP5_IHC_VM_CONTEXT_ERROR 11 -#define DCN_1_0__SRCID__HUBP6_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP6_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level +#define DCN_1_0__SRCID__HUBP6_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP6_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level #define DCN_1_0__CTXID__HUBP6_IHC_VM_CONTEXT_ERROR 12 -#define DCN_1_0__SRCID__HUBP7_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP7_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level +#define DCN_1_0__SRCID__HUBP7_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP7_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level #define DCN_1_0__CTXID__HUBP7_IHC_VM_CONTEXT_ERROR 13 -#define DCN_1_0__SRCID__DPP0_PERFCOUNTER_INT0_STATUS 0x24 // DPP0 perfmon counter0 interrupt DPP0_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level / Pulse +#define DCN_1_0__SRCID__DPP0_PERFCOUNTER_INT0_STATUS 0x24 // DPP0 perfmon counter0 interrupt DPP0_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level / Pulse #define DCN_1_0__CTXID__DPP0_PERFCOUNTER_INT0_STATUS 0 -#define DCN_1_0__SRCID__DPP0_PERFCOUNTER_INT1_STATUS 0x24 // DPP0 perfmon counter1 interrupt DPP0_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level +#define DCN_1_0__SRCID__DPP0_PERFCOUNTER_INT1_STATUS 0x24 // DPP0 perfmon counter1 interrupt DPP0_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level #define DCN_1_0__CTXID__DPP0_PERFCOUNTER_INT1_STATUS 1 -#define DCN_1_0__SRCID__DC_D3_VBLANK 0x24 // D3 : VBlank HUBP2_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse +#define DCN_1_0__SRCID__DC_D3_VBLANK 0x24 // D3 : VBlank HUBP2_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse #define DCN_1_0__CTXID__DC_D3_VBLANK 9 -#define DCN_1_0__SRCID__DC_D3_VLINE1 0x24 // D3 : Vline HUBP2_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse +#define DCN_1_0__SRCID__DC_D3_VLINE1 0x24 // D3 : Vline HUBP2_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse #define DCN_1_0__CTXID__DC_D3_VLINE1 10 -#define DCN_1_0__SRCID__DC_D3_VLINE2 0x24 // D3 : Vline2 HUBP2_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse +#define DCN_1_0__SRCID__DC_D3_VLINE2 0x24 // D3 : Vline2 HUBP2_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse #define DCN_1_0__CTXID__DC_D3_VLINE2 11 -#define DCN_1_0__SRCID__DC_D4_VBLANK 0x24 // D4 : Vblank HUBP3_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse +#define DCN_1_0__SRCID__DC_D4_VBLANK 0x24 // D4 : Vblank HUBP3_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse #define DCN_1_0__CTXID__DC_D4_VBLANK 12 -#define DCN_1_0__SRCID__DC_D4_VLINE1 0x24 // D4 : Vline HUBP3_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse +#define DCN_1_0__SRCID__DC_D4_VLINE1 0x24 // D4 : Vline HUBP3_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse #define DCN_1_0__CTXID__DC_D4_VLINE1 13 -#define DCN_1_0__SRCID__DC_D4_VLINE2 0x24 // D4 : Vline2 HUBP3_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse +#define DCN_1_0__SRCID__DC_D4_VLINE2 0x24 // D4 : Vline2 HUBP3_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse #define DCN_1_0__CTXID__DC_D4_VLINE2 14 -#define DCN_1_0__SRCID__DPP1_PERFCOUNTER_INT0_STATUS 0x25 // DPP1 perfmon counter0 interrupt DPP1_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level / Pulse +#define DCN_1_0__SRCID__DPP1_PERFCOUNTER_INT0_STATUS 0x25 // DPP1 perfmon counter0 interrupt DPP1_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level / Pulse #define DCN_1_0__CTXID__DPP1_PERFCOUNTER_INT0_STATUS 0 -#define DCN_1_0__SRCID__DPP1_PERFCOUNTER_INT1_STATUS 0x25 // DPP1 perfmon counter1 interrupt DPP1_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level +#define DCN_1_0__SRCID__DPP1_PERFCOUNTER_INT1_STATUS 0x25 // DPP1 perfmon counter1 interrupt DPP1_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level #define DCN_1_0__CTXID__DPP1_PERFCOUNTER_INT1_STATUS 1 -#define DCN_1_0__SRCID__DC_D5_VBLANK 0x25 // D5 : VBlank HUBP4_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse +#define DCN_1_0__SRCID__DC_D5_VBLANK 0x25 // D5 : VBlank HUBP4_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse #define DCN_1_0__CTXID__DC_D5_VBLANK 9 -#define DCN_1_0__SRCID__DC_D5_VLINE1 0x25 // D5 : Vline HUBP4_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse +#define DCN_1_0__SRCID__DC_D5_VLINE1 0x25 // D5 : Vline HUBP4_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse #define DCN_1_0__CTXID__DC_D5_VLINE1 10 -#define DCN_1_0__SRCID__DC_D5_VLINE2 0x25 // D5 : Vline2 HUBP4_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse +#define DCN_1_0__SRCID__DC_D5_VLINE2 0x25 // D5 : Vline2 HUBP4_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse #define DCN_1_0__CTXID__DC_D5_VLINE2 11 -#define DCN_1_0__SRCID__DC_D6_VBLANK 0x25 // D6 : Vblank HUBP5_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse +#define DCN_1_0__SRCID__DC_D6_VBLANK 0x25 // D6 : Vblank HUBP5_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse #define DCN_1_0__CTXID__DC_D6_VBLANK 12 -#define DCN_1_0__SRCID__DC_D6_VLINE1 0x25 // D6 : Vline HUBP5_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse +#define DCN_1_0__SRCID__DC_D6_VLINE1 0x25 // D6 : Vline HUBP5_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse #define DCN_1_0__CTXID__DC_D6_VLINE1 13 -#define DCN_1_0__SRCID__DC_D6_VLINE2 0x25 // D6 : Vline2 HUBP5_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse +#define DCN_1_0__SRCID__DC_D6_VLINE2 0x25 // D6 : Vline2 HUBP5_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse #define DCN_1_0__CTXID__DC_D6_VLINE2 14 -#define DCN_1_0__SRCID__DPP2_PERFCOUNTER_INT0_STATUS 0x26 // DPP2 perfmon counter0 interrupt DPP2_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level / Pulse +#define DCN_1_0__SRCID__DPP2_PERFCOUNTER_INT0_STATUS 0x26 // DPP2 perfmon counter0 interrupt DPP2_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level / Pulse #define DCN_1_0__CTXID__DPP2_PERFCOUNTER_INT0_STATUS 0 -#define DCN_1_0__SRCID__DPP2_PERFCOUNTER_INT1_STATUS 0x26 // DPP2 perfmon counter1 interrupt DPP2_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level +#define DCN_1_0__SRCID__DPP2_PERFCOUNTER_INT1_STATUS 0x26 // DPP2 perfmon counter1 interrupt DPP2_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level #define DCN_1_0__CTXID__DPP2_PERFCOUNTER_INT1_STATUS 1 -#define DCN_1_0__SRCID__DC_D7_VBLANK 0x26 // D7 : VBlank HUBP6_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse +#define DCN_1_0__SRCID__DC_D7_VBLANK 0x26 // D7 : VBlank HUBP6_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse #define DCN_1_0__CTXID__DC_D7_VBLANK 9 -#define DCN_1_0__SRCID__DC_D7_VLINE1 0x26 // D7 : Vline HUBP6_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse +#define DCN_1_0__SRCID__DC_D7_VLINE1 0x26 // D7 : Vline HUBP6_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse #define DCN_1_0__CTXID__DC_D7_VLINE1 10 -#define DCN_1_0__SRCID__DC_D7_VLINE2 0x26 // D7 : Vline2 HUBP6_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse +#define DCN_1_0__SRCID__DC_D7_VLINE2 0x26 // D7 : Vline2 HUBP6_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse #define DCN_1_0__CTXID__DC_D7_VLINE2 11 -#define DCN_1_0__SRCID__DC_D8_VBLANK 0x26 // D8 : Vblank HUBP7_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse +#define DCN_1_0__SRCID__DC_D8_VBLANK 0x26 // D8 : Vblank HUBP7_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse #define DCN_1_0__CTXID__DC_D8_VBLANK 12 -#define DCN_1_0__SRCID__DC_D8_VLINE1 0x26 // D8 : Vline HUBP7_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse +#define DCN_1_0__SRCID__DC_D8_VLINE1 0x26 // D8 : Vline HUBP7_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse #define DCN_1_0__CTXID__DC_D8_VLINE1 13 -#define DCN_1_0__SRCID__DC_D8_VLINE2 0x26 // D8 : Vline2 HUBP7_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse +#define DCN_1_0__SRCID__DC_D8_VLINE2 0x26 // D8 : Vline2 HUBP7_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse #define DCN_1_0__CTXID__DC_D8_VLINE2 14 -#define DCN_1_0__SRCID__DPP3_PERFCOUNTER_INT0_STATUS 0x27 // DPP3 perfmon counter0 interrupt DPP3_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level / Pulse +#define DCN_1_0__SRCID__DPP3_PERFCOUNTER_INT0_STATUS 0x27 // DPP3 perfmon counter0 interrupt DPP3_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level / Pulse #define DCN_1_0__CTXID__DPP3_PERFCOUNTER_INT0_STATUS 0 -#define DCN_1_0__SRCID__DPP3_PERFCOUNTER_INT1_STATUS 0x27 // DPP3 perfmon counter1 interrupt DPP3_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level +#define DCN_1_0__SRCID__DPP3_PERFCOUNTER_INT1_STATUS 0x27 // DPP3 perfmon counter1 interrupt DPP3_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level #define DCN_1_0__CTXID__DPP3_PERFCOUNTER_INT1_STATUS 1 -#define DCN_1_0__SRCID__DPP4_PERFCOUNTER_INT0_STATUS 0x28 // DPP4 perfmon counter0 interrupt DPP4_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level / Pulse +#define DCN_1_0__SRCID__DPP4_PERFCOUNTER_INT0_STATUS 0x28 // DPP4 perfmon counter0 interrupt DPP4_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level / Pulse #define DCN_1_0__CTXID__DPP4_PERFCOUNTER_INT0_STATUS 0 -#define DCN_1_0__SRCID__DPP4_PERFCOUNTER_INT1_STATUS 0x28 // DPP4 perfmon counter1 interrupt DPP4_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level +#define DCN_1_0__SRCID__DPP4_PERFCOUNTER_INT1_STATUS 0x28 // DPP4 perfmon counter1 interrupt DPP4_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level #define DCN_1_0__CTXID__DPP4_PERFCOUNTER_INT1_STATUS 1 -#define DCN_1_0__SRCID__DPP5_PERFCOUNTER_INT0_STATUS 0x29 // DPP5 perfmon counter0 interrupt DPP5_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level / Pulse +#define DCN_1_0__SRCID__DPP5_PERFCOUNTER_INT0_STATUS 0x29 // DPP5 perfmon counter0 interrupt DPP5_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level / Pulse #define DCN_1_0__CTXID__DPP5_PERFCOUNTER_INT0_STATUS 0 -#define DCN_1_0__SRCID__DPP5_PERFCOUNTER_INT1_STATUS 0x29 // DPP5 perfmon counter1 interrupt DPP5_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level +#define DCN_1_0__SRCID__DPP5_PERFCOUNTER_INT1_STATUS 0x29 // DPP5 perfmon counter1 interrupt DPP5_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level #define DCN_1_0__CTXID__DPP5_PERFCOUNTER_INT1_STATUS 1 -#define DCN_1_0__SRCID__DPP6_PERFCOUNTER_INT0_STATUS 0x2A // DPP6 perfmon counter0 interrupt DPP6_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level / Pulse +#define DCN_1_0__SRCID__DPP6_PERFCOUNTER_INT0_STATUS 0x2A // DPP6 perfmon counter0 interrupt DPP6_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level / Pulse #define DCN_1_0__CTXID__DPP6_PERFCOUNTER_INT0_STATUS 0 -#define DCN_1_0__SRCID__DPP6_PERFCOUNTER_INT1_STATUS 0x2A // DPP6 perfmon counter1 interrupt DPP6_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level +#define DCN_1_0__SRCID__DPP6_PERFCOUNTER_INT1_STATUS 0x2A // DPP6 perfmon counter1 interrupt DPP6_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level #define DCN_1_0__CTXID__DPP6_PERFCOUNTER_INT1_STATUS 1 -#define DCN_1_0__SRCID__DPP7_PERFCOUNTER_INT0_STATUS 0x2B // DPP7 perfmon counter0 interrupt DPP7_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level / Pulse +#define DCN_1_0__SRCID__DPP7_PERFCOUNTER_INT0_STATUS 0x2B // DPP7 perfmon counter0 interrupt DPP7_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level / Pulse #define DCN_1_0__CTXID__DPP7_PERFCOUNTER_INT0_STATUS 0 -#define DCN_1_0__SRCID__DPP7_PERFCOUNTER_INT1_STATUS 0x2B // DPP7 perfmon counter1 interrupt DPP7_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level +#define DCN_1_0__SRCID__DPP7_PERFCOUNTER_INT1_STATUS 0x2B // DPP7 perfmon counter1 interrupt DPP7_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level #define DCN_1_0__CTXID__DPP7_PERFCOUNTER_INT1_STATUS 1 -#define DCN_1_0__SRCID__HUBP0_PERFCOUNTER_INT0_STATUS 0x2C // HUBP0 perfmon counter0 interrupt HUBP0_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse +#define DCN_1_0__SRCID__HUBP0_PERFCOUNTER_INT0_STATUS 0x2C // HUBP0 perfmon counter0 interrupt HUBP0_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse #define DCN_1_0__CTXID__HUBP0_PERFCOUNTER_INT0_STATUS 0 -#define DCN_1_0__SRCID__HUBP0_PERFCOUNTER_INT1_STATUS 0x2C // HUBP0 perfmon counter1 interrupt HUBP0_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level +#define DCN_1_0__SRCID__HUBP0_PERFCOUNTER_INT1_STATUS 0x2C // HUBP0 perfmon counter1 interrupt HUBP0_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level #define DCN_1_0__CTXID__HUBP0_PERFCOUNTER_INT1_STATUS 1 -#define DCN_1_0__SRCID__HUBP1_PERFCOUNTER_INT0_STATUS 0x2D // HUBP1 perfmon counter0 interrupt HUBP1_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse +#define DCN_1_0__SRCID__HUBP1_PERFCOUNTER_INT0_STATUS 0x2D // HUBP1 perfmon counter0 interrupt HUBP1_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse #define DCN_1_0__CTXID__HUBP1_PERFCOUNTER_INT0_STATUS 0 -#define DCN_1_0__SRCID__HUBP1_PERFCOUNTER_INT1_STATUS 0x2D // HUBP1 perfmon counter1 interrupt HUBP1_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level +#define DCN_1_0__SRCID__HUBP1_PERFCOUNTER_INT1_STATUS 0x2D // HUBP1 perfmon counter1 interrupt HUBP1_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level #define DCN_1_0__CTXID__HUBP1_PERFCOUNTER_INT1_STATUS 1 -#define DCN_1_0__SRCID__HUBP2_PERFCOUNTER_INT0_STATUS 0x2E // HUBP2 perfmon counter0 interrupt HUBP2_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse +#define DCN_1_0__SRCID__HUBP2_PERFCOUNTER_INT0_STATUS 0x2E // HUBP2 perfmon counter0 interrupt HUBP2_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse #define DCN_1_0__CTXID__HUBP2_PERFCOUNTER_INT0_STATUS 0 -#define DCN_1_0__SRCID__HUBP2_PERFCOUNTER_INT1_STATUS 0x2E // HUBP2 perfmon counter1 interrupt HUBP2_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level +#define DCN_1_0__SRCID__HUBP2_PERFCOUNTER_INT1_STATUS 0x2E // HUBP2 perfmon counter1 interrupt HUBP2_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level #define DCN_1_0__CTXID__HUBP2_PERFCOUNTER_INT1_STATUS 1 -#define DCN_1_0__SRCID__HUBP3_PERFCOUNTER_INT0_STATUS 0x2F // HUBP3 perfmon counter0 interrupt HUBP3_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse +#define DCN_1_0__SRCID__HUBP3_PERFCOUNTER_INT0_STATUS 0x2F // HUBP3 perfmon counter0 interrupt HUBP3_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse #define DCN_1_0__CTXID__HUBP3_PERFCOUNTER_INT0_STATUS 0 -#define DCN_1_0__SRCID__HUBP3_PERFCOUNTER_INT1_STATUS 0x2F // HUBP3 perfmon counter1 interrupt HUBP3_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level +#define DCN_1_0__SRCID__HUBP3_PERFCOUNTER_INT1_STATUS 0x2F // HUBP3 perfmon counter1 interrupt HUBP3_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level #define DCN_1_0__CTXID__HUBP3_PERFCOUNTER_INT1_STATUS 1 -#define DCN_1_0__SRCID__HUBP4_PERFCOUNTER_INT0_STATUS 0x30 // HUBP4 perfmon counter0 interrupt HUBP4_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse +#define DCN_1_0__SRCID__HUBP4_PERFCOUNTER_INT0_STATUS 0x30 // HUBP4 perfmon counter0 interrupt HUBP4_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse #define DCN_1_0__CTXID__HUBP4_PERFCOUNTER_INT0_STATUS 0 -#define DCN_1_0__SRCID__HUBP4_PERFCOUNTER_INT1_STATUS 0x30 // HUBP4 perfmon counter1 interrupt HUBP4_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level +#define DCN_1_0__SRCID__HUBP4_PERFCOUNTER_INT1_STATUS 0x30 // HUBP4 perfmon counter1 interrupt HUBP4_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level #define DCN_1_0__CTXID__HUBP4_PERFCOUNTER_INT1_STATUS 1 -#define DCN_1_0__SRCID__HUBP5_PERFCOUNTER_INT0_STATUS 0x31 // HUBP5 perfmon counter0 interrupt HUBP5_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse +#define DCN_1_0__SRCID__HUBP5_PERFCOUNTER_INT0_STATUS 0x31 // HUBP5 perfmon counter0 interrupt HUBP5_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse #define DCN_1_0__CTXID__HUBP5_PERFCOUNTER_INT0_STATUS 0 -#define DCN_1_0__SRCID__HUBP5_PERFCOUNTER_INT1_STATUS 0x31 // HUBP5 perfmon counter1 interrupt HUBP5_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level +#define DCN_1_0__SRCID__HUBP5_PERFCOUNTER_INT1_STATUS 0x31 // HUBP5 perfmon counter1 interrupt HUBP5_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level #define DCN_1_0__CTXID__HUBP5_PERFCOUNTER_INT1_STATUS 1 -#define DCN_1_0__SRCID__HUBP6_PERFCOUNTER_INT0_STATUS 0x32 // HUBP6 perfmon counter0 interrupt HUBP6_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse +#define DCN_1_0__SRCID__HUBP6_PERFCOUNTER_INT0_STATUS 0x32 // HUBP6 perfmon counter0 interrupt HUBP6_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse #define DCN_1_0__CTXID__HUBP6_PERFCOUNTER_INT0_STATUS 0 -#define DCN_1_0__SRCID__HUBP6_PERFCOUNTER_INT1_STATUS 0x32 // HUBP6 perfmon counter1 interrupt HUBP6_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level +#define DCN_1_0__SRCID__HUBP6_PERFCOUNTER_INT1_STATUS 0x32 // HUBP6 perfmon counter1 interrupt HUBP6_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level #define DCN_1_0__CTXID__HUBP6_PERFCOUNTER_INT1_STATUS 1 -#define DCN_1_0__SRCID__HUBP7_PERFCOUNTER_INT0_STATUS 0x33 // HUBP7 perfmon counter0 interrupt HUBP7_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse +#define DCN_1_0__SRCID__HUBP7_PERFCOUNTER_INT0_STATUS 0x33 // HUBP7 perfmon counter0 interrupt HUBP7_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse #define DCN_1_0__CTXID__HUBP7_PERFCOUNTER_INT0_STATUS 0 -#define DCN_1_0__SRCID__HUBP7_PERFCOUNTER_INT1_STATUS 0x33 // HUBP7 perfmon counter1 interrupt HUBP7_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level +#define DCN_1_0__SRCID__HUBP7_PERFCOUNTER_INT1_STATUS 0x33 // HUBP7 perfmon counter1 interrupt HUBP7_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level #define DCN_1_0__CTXID__HUBP7_PERFCOUNTER_INT1_STATUS 1 -#define DCN_1_0__SRCID__WB1_PERFCOUNTER_INT0_STATUS 0x34 // WB1 perfmon counter0 interrupt WB1_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level / Pulse +#define DCN_1_0__SRCID__WB1_PERFCOUNTER_INT0_STATUS 0x34 // WB1 perfmon counter0 interrupt WB1_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level / Pulse #define DCN_1_0__CTXID__WB1_PERFCOUNTER_INT0_STATUS 0 -#define DCN_1_0__SRCID__WB1_PERFCOUNTER_INT1_STATUS 0x34 // WB1 perfmon counter1 interrupt WB1_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level +#define DCN_1_0__SRCID__WB1_PERFCOUNTER_INT1_STATUS 0x34 // WB1 perfmon counter1 interrupt WB1_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level #define DCN_1_0__CTXID__WB1_PERFCOUNTER_INT1_STATUS 1 -#define DCN_1_0__SRCID__HUBBUB_PERFCOUNTER_INT0_STATUS 0x35 // HUBBUB perfmon counter0 interrupt HUBBUB_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse +#define DCN_1_0__SRCID__HUBBUB_PERFCOUNTER_INT0_STATUS 0x35 // HUBBUB perfmon counter0 interrupt HUBBUB_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse #define DCN_1_0__CTXID__HUBBUB_PERFCOUNTER_INT0_STATUS 0 -#define DCN_1_0__SRCID__HUBBUB_PERFCOUNTER_INT1_STATUS 0x35 // HUBBUB perfmon counter1 interrupt HUBBUB_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level +#define DCN_1_0__SRCID__HUBBUB_PERFCOUNTER_INT1_STATUS 0x35 // HUBBUB perfmon counter1 interrupt HUBBUB_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level #define DCN_1_0__CTXID__HUBBUB_PERFCOUNTER_INT1_STATUS 1 -#define DCN_1_0__SRCID__MPC_PERFCOUNTER_INT0_STATUS 0x36 // MPC perfmon counter0 interrupt MPC_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level / Pulse +#define DCN_1_0__SRCID__MPC_PERFCOUNTER_INT0_STATUS 0x36 // MPC perfmon counter0 interrupt MPC_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level / Pulse #define DCN_1_0__CTXID__MPC_PERFCOUNTER_INT0_STATUS 0 -#define DCN_1_0__SRCID__MPC_PERFCOUNTER_INT1_STATUS 0x36 // MPC perfmon counter1 interrupt MPC_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level +#define DCN_1_0__SRCID__MPC_PERFCOUNTER_INT1_STATUS 0x36 // MPC perfmon counter1 interrupt MPC_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level #define DCN_1_0__CTXID__MPC_PERFCOUNTER_INT1_STATUS 1 -#define DCN_1_0__SRCID__OPP_PERFCOUNTER_INT0_STATUS 0x37 // OPP perfmon counter0 interrupt OPP_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse +#define DCN_1_0__SRCID__OPP_PERFCOUNTER_INT0_STATUS 0x37 // OPP perfmon counter0 interrupt OPP_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse #define DCN_1_0__CTXID__OPP_PERFCOUNTER_INT0_STATUS 0 -#define DCN_1_0__SRCID__OPP_PERFCOUNTER_INT1_STATUS 0x37 // OPP perfmon counter1 interrupt OPP_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level +#define DCN_1_0__SRCID__OPP_PERFCOUNTER_INT1_STATUS 0x37 // OPP perfmon counter1 interrupt OPP_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level #define DCN_1_0__CTXID__OPP_PERFCOUNTER_INT1_STATUS 1 -#define DCN_1_0__SRCID__DC_D6_OTG_SNAPSHOT 0x38 // D6: OTG snapshot OTG6_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse +#define DCN_1_0__SRCID__DC_D6_OTG_SNAPSHOT 0x38 // D6: OTG snapshot OTG6_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse #define DCN_1_0__CTXID__DC_D6_OTG_SNAPSHOT 0 -#define DCN_1_0__SRCID__DC_D6_FORCE_CNT_W 0x38 // D6 : Force - count--w OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse +#define DCN_1_0__SRCID__DC_D6_FORCE_CNT_W 0x38 // D6 : Force - count--w OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse #define DCN_1_0__CTXID__DC_D6_FORCE_CNT_W 1 -#define DCN_1_0__SRCID__DC_D6_FORCE_VSYNC_NXT_LINE 0x38 // D6 : Force - Vsync - next - line OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse +#define DCN_1_0__SRCID__DC_D6_FORCE_VSYNC_NXT_LINE 0x38 // D6 : Force - Vsync - next - line OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse #define DCN_1_0__CTXID__DC_D6_FORCE_VSYNC_NXT_LINE 2 -#define DCN_1_0__SRCID__DC_D6_OTG_EXTT_TRG_A 0x38 // D6 : OTG external trigger A OTG6_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse +#define DCN_1_0__SRCID__DC_D6_OTG_EXTT_TRG_A 0x38 // D6 : OTG external trigger A OTG6_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse #define DCN_1_0__CTXID__DC_D6_OTG_EXTT_TRG_A 3 -#define DCN_1_0__SRCID__DC_D6_OTG_EXTT_TRG_B 0x38 // D6 : OTG external trigger B OTG6_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse +#define DCN_1_0__SRCID__DC_D6_OTG_EXTT_TRG_B 0x38 // D6 : OTG external trigger B OTG6_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse #define DCN_1_0__CTXID__DC_D6_OTG_EXTT_TRG_B 4 -#define DCN_1_0__SRCID__DC_D6_OTG_GSL_VSYNC_GAP 0x38 // D6 : gsl_vsync_gap_interrupt_frame_delay OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__SRCID__DC_D6_OTG_GSL_VSYNC_GAP 0x38 // D6 : gsl_vsync_gap_interrupt_frame_delay OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse #define DCN_1_0__CTXID__DC_D6_OTG_GSL_VSYNC_GAP 5 -#define DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL 0x38 // D6 : OTG vertical interrupt 0 OTG6_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse +#define DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL 0x38 // D6 : OTG vertical interrupt 0 OTG6_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse #define DCN_1_0__CTXID__OTG6_VERTICAL_INTERRUPT0_CONTROL 6 -#define DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT1_CONTROL 0x38 // D6 : OTG vertical interrupt 1 OTG6_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse +#define DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT1_CONTROL 0x38 // D6 : OTG vertical interrupt 1 OTG6_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse #define DCN_1_0__CTXID__OTG6_VERTICAL_INTERRUPT1_CONTROL 7 -#define DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT2_CONTROL 0x38 // D6 : OTG vertical interrupt 2 OTG6_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse +#define DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT2_CONTROL 0x38 // D6 : OTG vertical interrupt 2 OTG6_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse #define DCN_1_0__CTXID__OTG6_VERTICAL_INTERRUPT2_CONTROL 8 -#define DCN_1_0__SRCID__OTG6_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x38 // D6 : OTG ext sync loss interrupt OTG6_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse +#define DCN_1_0__SRCID__OTG6_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x38 // D6 : OTG ext sync loss interrupt OTG6_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse #define DCN_1_0__CTXID__OTG6_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 -#define DCN_1_0__SRCID__OTG6_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x38 // D6 : OTG ext sync interrupt OTG6_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse +#define DCN_1_0__SRCID__OTG6_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x38 // D6 : OTG ext sync interrupt OTG6_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse #define DCN_1_0__CTXID__OTG6_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 -#define DCN_1_0__SRCID__OTG6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x38 // D6 : OTG ext sync signal interrupt OTG6_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse +#define DCN_1_0__SRCID__OTG6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x38 // D6 : OTG ext sync signal interrupt OTG6_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse #define DCN_1_0__CTXID__OTG6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 -#define DCN_1_0__SRCID__OTG6_SET_VTOTAL_MIN_EVENT_INT 0x38 // D : OTG DRR event occurred interrupt OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse +#define DCN_1_0__SRCID__OTG6_SET_VTOTAL_MIN_EVENT_INT 0x38 // D : OTG DRR event occurred interrupt OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse #define DCN_1_0__CTXID__OTG6_SET_VTOTAL_MIN_EVENT_INT 12 -#define DCN_1_0__SRCID__OPTC_PERFCOUNTER_INT0_STATUS 0x39 // OPTC perfmon counter0 interrupt OPTC_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse +#define DCN_1_0__SRCID__OPTC_PERFCOUNTER_INT0_STATUS 0x39 // OPTC perfmon counter0 interrupt OPTC_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse #define DCN_1_0__CTXID__OPTC_PERFCOUNTER_INT0_STATUS 0 -#define DCN_1_0__SRCID__OPTC_PERFCOUNTER_INT1_STATUS 0x39 // OPTC perfmon counter1 interrupt OPTC_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level +#define DCN_1_0__SRCID__OPTC_PERFCOUNTER_INT1_STATUS 0x39 // OPTC perfmon counter1 interrupt OPTC_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level #define DCN_1_0__CTXID__OPTC_PERFCOUNTER_INT1_STATUS 1 -#define DCN_1_0__SRCID__MMHUBBUB_PERFCOUNTER_INT0_STATUS 0x3A // MMHUBBUB perfmon counter0 interrupt MMHUBBUB_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse +#define DCN_1_0__SRCID__MMHUBBUB_PERFCOUNTER_INT0_STATUS 0x3A // MMHUBBUB perfmon counter0 interrupt MMHUBBUB_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse #define DCN_1_0__CTXID__MMHUBBUB_PERFCOUNTER_INT0_STATUS 0 -#define DCN_1_0__SRCID__MMHUBBUB_PERFCOUNTER_INT1_STATUS 0x3A // MMHUBBUB perfmon counter1 interrupt MMHUBBUB_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level +#define DCN_1_0__SRCID__MMHUBBUB_PERFCOUNTER_INT1_STATUS 0x3A // MMHUBBUB perfmon counter1 interrupt MMHUBBUB_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level #define DCN_1_0__CTXID__MMHUBBUB_PERFCOUNTER_INT1_STATUS 1 -#define DCN_1_0__SRCID__AZ_PERFCOUNTER_INT0_STATUS 0x3B // AZ perfmon counter0 interrupt AZ_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse +#define DCN_1_0__SRCID__AZ_PERFCOUNTER_INT0_STATUS 0x3B // AZ perfmon counter0 interrupt AZ_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse #define DCN_1_0__CTXID__AZ_PERFCOUNTER_INT0_STATUS 0 -#define DCN_1_0__SRCID__AZ_PERFCOUNTER_INT1_STATUS 0x3B // AZ perfmon counter1 interrupt AZ_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level +#define DCN_1_0__SRCID__AZ_PERFCOUNTER_INT1_STATUS 0x3B // AZ perfmon counter1 interrupt AZ_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level #define DCN_1_0__CTXID__AZ_PERFCOUNTER_INT1_STATUS 1 #define DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP 0x3C // "OTG0 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG1_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse @@ -1057,52 +1057,52 @@ #define DCN_1_0__SRCID__OTG4_VSYNC_NOM 0x4C // OTG4 vsync nom interrupt OTG5_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse #define DCN_1_0__SRCID__OTG5_VSYNC_NOM 0x4D // OTG5 vsync nom interrupt OTG6_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse -#define DCN_1_0__SRCID__DCPG_DCFE8_POWER_UP_INT 0x4E // Display pipe0 power up interrupt DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__SRCID__DCPG_DCFE8_POWER_UP_INT 0x4E // Display pipe0 power up interrupt DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level #define DCN_1_0__CTXID__DCPG_DCFE8_POWER_UP_INT 0 -#define DCN_1_0__SRCID__DCPG_DCFE9_POWER_UP_INT 0x4E // Display pipe1 power up interrupt DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__SRCID__DCPG_DCFE9_POWER_UP_INT 0x4E // Display pipe1 power up interrupt DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level #define DCN_1_0__CTXID__DCPG_DCFE9_POWER_UP_INT 1 -#define DCN_1_0__SRCID__DCPG_DCFE10_POWER_UP_INT 0x4E // Display pipe2 power up interrupt DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__SRCID__DCPG_DCFE10_POWER_UP_INT 0x4E // Display pipe2 power up interrupt DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level #define DCN_1_0__CTXID__DCPG_DCFE10_POWER_UP_INT 2 -#define DCN_1_0__SRCID__DCPG_DCFE11_POWER_UP_INT 0x4E // Display pipe3 power up interrupt DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__SRCID__DCPG_DCFE11_POWER_UP_INT 0x4E // Display pipe3 power up interrupt DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level #define DCN_1_0__CTXID__DCPG_DCFE11_POWER_UP_INT 3 -#define DCN_1_0__SRCID__DCPG_DCFE12_POWER_UP_INT 0x4E // Display pipe4 power up interrupt DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__SRCID__DCPG_DCFE12_POWER_UP_INT 0x4E // Display pipe4 power up interrupt DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level #define DCN_1_0__CTXID__DCPG_DCFE12_POWER_UP_INT 4 -#define DCN_1_0__SRCID__DCPG_DCFE13_POWER_UP_INT 0x4E // Display pipe5 power up interrupt DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__SRCID__DCPG_DCFE13_POWER_UP_INT 0x4E // Display pipe5 power up interrupt DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level #define DCN_1_0__CTXID__DCPG_DCFE13_POWER_UP_INT 5 -#define DCN_1_0__SRCID__DCPG_DCFE14_POWER_UP_INT 0x4E // Display pipe6 power up interrupt DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__SRCID__DCPG_DCFE14_POWER_UP_INT 0x4E // Display pipe6 power up interrupt DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level #define DCN_1_0__CTXID__DCPG_DCFE14_POWER_UP_INT 6 -#define DCN_1_0__SRCID__DCPG_DCFE15_POWER_UP_INT 0x4E // Display pipe7 power up interrupt DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__SRCID__DCPG_DCFE15_POWER_UP_INT 0x4E // Display pipe7 power up interrupt DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level #define DCN_1_0__CTXID__DCPG_DCFE15_POWER_UP_INT 7 -#define DCN_1_0__SRCID__DCPG_DCFE8_POWER_DOWN_INT 0x4E // Display pipe0 power down interrupt DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__SRCID__DCPG_DCFE8_POWER_DOWN_INT 0x4E // Display pipe0 power down interrupt DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level #define DCN_1_0__CTXID__DCPG_DCFE8_POWER_DOWN_INT 8 -#define DCN_1_0__SRCID__DCPG_DCFE9_POWER_DOWN_INT 0x4E // Display pipe1 power down interrupt DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__SRCID__DCPG_DCFE9_POWER_DOWN_INT 0x4E // Display pipe1 power down interrupt DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level #define DCN_1_0__CTXID__DCPG_DCFE9_POWER_DOWN_INT 9 -#define DCN_1_0__SRCID__DCPG_DCFE10_POWER_DOWN_INT 0x4E // Display pipe2 power down interrupt DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__SRCID__DCPG_DCFE10_POWER_DOWN_INT 0x4E // Display pipe2 power down interrupt DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level #define DCN_1_0__CTXID__DCPG_DCFE10_POWER_DOWN_INT 10 -#define DCN_1_0__SRCID__DCPG_DCFE11_POWER_DOWN_INT 0x4E // Display pipe3 power down interrupt DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__SRCID__DCPG_DCFE11_POWER_DOWN_INT 0x4E // Display pipe3 power down interrupt DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level #define DCN_1_0__CTXID__DCPG_DCFE11_POWER_DOWN_INT 11 -#define DCN_1_0__SRCID__DCPG_DCFE12_POWER_DOWN_INT 0x4E // Display pipe4 power down interrupt DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__SRCID__DCPG_DCFE12_POWER_DOWN_INT 0x4E // Display pipe4 power down interrupt DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level #define DCN_1_0__CTXID__DCPG_DCFE12_POWER_DOWN_INT 12 -#define DCN_1_0__SRCID__DCPG_DCFE13_POWER_DOWN_INT 0x4E // Display pipe5 power down interrupt DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__SRCID__DCPG_DCFE13_POWER_DOWN_INT 0x4E // Display pipe5 power down interrupt DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level #define DCN_1_0__CTXID__DCPG_DCFE13_POWER_DOWN_INT 13 -#define DCN_1_0__SRCID__DCPG_DCFE14_POWER_DOWN_INT 0x4E // Display pipe6 power down interrupt DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__SRCID__DCPG_DCFE14_POWER_DOWN_INT 0x4E // Display pipe6 power down interrupt DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level #define DCN_1_0__CTXID__DCPG_DCFE14_POWER_DOWN_INT 14 -#define DCN_1_0__SRCID__DCPG_DCFE15_POWER_DOWN_INT 0x4E // Display pipe7 power down interrupt DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__SRCID__DCPG_DCFE15_POWER_DOWN_INT 0x4E // Display pipe7 power down interrupt DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level #define DCN_1_0__CTXID__DCPG_DCFE15_POWER_DOWN_INT 15 #define DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT 0x4F // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP0_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse diff --git a/sys/dev/pci/drm/amd/include/ivsrcid/ivsrcid_vislands30.h b/sys/dev/pci/drm/amd/include/ivsrcid/ivsrcid_vislands30.h index aaed7f59e..dd136089f 100644 --- a/sys/dev/pci/drm/amd/include/ivsrcid/ivsrcid_vislands30.h +++ b/sys/dev/pci/drm/amd/include/ivsrcid/ivsrcid_vislands30.h @@ -27,40 +27,40 @@ // IV Source IDs -#define VISLANDS30_IV_SRCID_D1_V_UPDATE_INT 7 // 0x07 +#define VISLANDS30_IV_SRCID_D1_V_UPDATE_INT 7 // 0x07 #define VISLANDS30_IV_EXTID_D1_V_UPDATE_INT 0 -#define VISLANDS30_IV_SRCID_D1_GRPH_PFLIP 8 // 0x08 +#define VISLANDS30_IV_SRCID_D1_GRPH_PFLIP 8 // 0x08 #define VISLANDS30_IV_EXTID_D1_GRPH_PFLIP 0 -#define VISLANDS30_IV_SRCID_D2_V_UPDATE_INT 9 // 0x09 +#define VISLANDS30_IV_SRCID_D2_V_UPDATE_INT 9 // 0x09 #define VISLANDS30_IV_EXTID_D2_V_UPDATE_INT 0 -#define VISLANDS30_IV_SRCID_D2_GRPH_PFLIP 10 // 0x0a +#define VISLANDS30_IV_SRCID_D2_GRPH_PFLIP 10 // 0x0a #define VISLANDS30_IV_EXTID_D2_GRPH_PFLIP 0 -#define VISLANDS30_IV_SRCID_D3_V_UPDATE_INT 11 // 0x0b +#define VISLANDS30_IV_SRCID_D3_V_UPDATE_INT 11 // 0x0b #define VISLANDS30_IV_EXTID_D3_V_UPDATE_INT 0 -#define VISLANDS30_IV_SRCID_D3_GRPH_PFLIP 12 // 0x0c +#define VISLANDS30_IV_SRCID_D3_GRPH_PFLIP 12 // 0x0c #define VISLANDS30_IV_EXTID_D3_GRPH_PFLIP 0 -#define VISLANDS30_IV_SRCID_D4_V_UPDATE_INT 13 // 0x0d +#define VISLANDS30_IV_SRCID_D4_V_UPDATE_INT 13 // 0x0d #define VISLANDS30_IV_EXTID_D4_V_UPDATE_INT 0 -#define VISLANDS30_IV_SRCID_D4_GRPH_PFLIP 14 // 0x0e +#define VISLANDS30_IV_SRCID_D4_GRPH_PFLIP 14 // 0x0e #define VISLANDS30_IV_EXTID_D4_GRPH_PFLIP 0 -#define VISLANDS30_IV_SRCID_D5_V_UPDATE_INT 15 // 0x0f +#define VISLANDS30_IV_SRCID_D5_V_UPDATE_INT 15 // 0x0f #define VISLANDS30_IV_EXTID_D5_V_UPDATE_INT 0 -#define VISLANDS30_IV_SRCID_D5_GRPH_PFLIP 16 // 0x10 +#define VISLANDS30_IV_SRCID_D5_GRPH_PFLIP 16 // 0x10 #define VISLANDS30_IV_EXTID_D5_GRPH_PFLIP 0 -#define VISLANDS30_IV_SRCID_D6_V_UPDATE_INT 17 // 0x11 +#define VISLANDS30_IV_SRCID_D6_V_UPDATE_INT 17 // 0x11 #define VISLANDS30_IV_EXTID_D6_V_UPDATE_INT 0 -#define VISLANDS30_IV_SRCID_D6_GRPH_PFLIP 18 // 0x12 +#define VISLANDS30_IV_SRCID_D6_GRPH_PFLIP 18 // 0x12 #define VISLANDS30_IV_EXTID_D6_GRPH_PFLIP 0 #define VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 19 // 0x13 @@ -162,40 +162,40 @@ #define VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT2 24 // 0x18 #define VISLANDS30_IV_EXTID_D6_VERTICAL_INTERRUPT2 9 -#define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A 42 // 0x2a +#define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A 42 // 0x2a #define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_A 0 -#define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_B 42 // 0x2a +#define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_B 42 // 0x2a #define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_B 1 -#define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_C 42 // 0x2a +#define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_C 42 // 0x2a #define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_C 2 -#define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_D 42 // 0x2a +#define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_D 42 // 0x2a #define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_D 3 -#define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_E 42 // 0x2a +#define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_E 42 // 0x2a #define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_E 4 -#define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_F 42 // 0x2a +#define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_F 42 // 0x2a #define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_F 5 -#define VISLANDS30_IV_SRCID_HPD_RX_A 42 // 0x2a +#define VISLANDS30_IV_SRCID_HPD_RX_A 42 // 0x2a #define VISLANDS30_IV_EXTID_HPD_RX_A 6 -#define VISLANDS30_IV_SRCID_HPD_RX_B 42 // 0x2a +#define VISLANDS30_IV_SRCID_HPD_RX_B 42 // 0x2a #define VISLANDS30_IV_EXTID_HPD_RX_B 7 -#define VISLANDS30_IV_SRCID_HPD_RX_C 42 // 0x2a +#define VISLANDS30_IV_SRCID_HPD_RX_C 42 // 0x2a #define VISLANDS30_IV_EXTID_HPD_RX_C 8 -#define VISLANDS30_IV_SRCID_HPD_RX_D 42 // 0x2a +#define VISLANDS30_IV_SRCID_HPD_RX_D 42 // 0x2a #define VISLANDS30_IV_EXTID_HPD_RX_D 9 -#define VISLANDS30_IV_SRCID_HPD_RX_E 42 // 0x2a +#define VISLANDS30_IV_SRCID_HPD_RX_E 42 // 0x2a #define VISLANDS30_IV_EXTID_HPD_RX_E 10 -#define VISLANDS30_IV_SRCID_HPD_RX_F 42 // 0x2a +#define VISLANDS30_IV_SRCID_HPD_RX_F 42 // 0x2a #define VISLANDS30_IV_EXTID_HPD_RX_F 11 #define VISLANDS30_IV_SRCID_GPIO_19 0x00000053 /* 83 */ diff --git a/sys/dev/pci/drm/amd/include/ivsrcid/sdma1/irqsrcs_sdma1_5_0.h b/sys/dev/pci/drm/amd/include/ivsrcid/sdma1/irqsrcs_sdma1_5_0.h index 7b68c466c..b686136a8 100644 --- a/sys/dev/pci/drm/amd/include/ivsrcid/sdma1/irqsrcs_sdma1_5_0.h +++ b/sys/dev/pci/drm/amd/include/ivsrcid/sdma1/irqsrcs_sdma1_5_0.h @@ -22,8 +22,8 @@ #ifndef __IRQSRCS_SDMA1_5_0_H__ #define __IRQSRCS_SDMA1_5_0_H__ -#define SDMA1_5_0__SRCID__SDMA_ATOMIC_RTN_DONE 217 // 0xD9 SDMA atomic*_rtn ops complete -#define SDMA1_5_0__SRCID__SDMA_ATOMIC_TIMEOUT 218 // 0xDA SDMA atomic CMPSWAP loop timeout +#define SDMA1_5_0__SRCID__SDMA_ATOMIC_RTN_DONE 217 // 0xD9 SDMA atomic*_rtn ops complete +#define SDMA1_5_0__SRCID__SDMA_ATOMIC_TIMEOUT 218 // 0xDA SDMA atomic CMPSWAP loop timeout #define SDMA1_5_0__SRCID__SDMA_IB_PREEMPT 219 // 0xDB sdma mid-command buffer preempt interrupt #define SDMA1_5_0__SRCID__SDMA_ECC 220 // 0xDC ECC Error #define SDMA1_5_0__SRCID__SDMA_PAGE_FAULT 221 // 0xDD Page Fault Error from UTCL2 when nack=3 diff --git a/sys/dev/pci/drm/amd/include/navi10_ip_offset.h b/sys/dev/pci/drm/amd/include/navi10_ip_offset.h index d6824bb61..3a4723c4a 100644 --- a/sys/dev/pci/drm/amd/include/navi10_ip_offset.h +++ b/sys/dev/pci/drm/amd/include/navi10_ip_offset.h @@ -28,7 +28,7 @@ struct IP_BASE_INSTANCE { unsigned int segment[MAX_SEGMENT]; }; - + struct IP_BASE { struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; } __maybe_unused; diff --git a/sys/dev/pci/drm/amd/include/pptable.h b/sys/dev/pci/drm/amd/include/pptable.h index 0b6a057e0..e5d78f892 100644 --- a/sys/dev/pci/drm/amd/include/pptable.h +++ b/sys/dev/pci/drm/amd/include/pptable.h @@ -133,7 +133,7 @@ typedef struct _ATOM_PPLIB_EXTENDEDHEADER USHORT usUVDTableOffset; //points to ATOM_PPLIB_UVD_Table USHORT usSAMUTableOffset; //points to ATOM_PPLIB_SAMU_Table USHORT usPPMTableOffset; //points to ATOM_PPLIB_PPM_Table - USHORT usACPTableOffset; //points to ATOM_PPLIB_ACP_Table + USHORT usACPTableOffset; //points to ATOM_PPLIB_ACP_Table /* points to ATOM_PPLIB_POWERTUNE_Table */ USHORT usPowerTuneTableOffset; /* points to ATOM_PPLIB_CLOCK_Voltage_Dependency_Table for sclkVddgfxTable */ @@ -223,14 +223,14 @@ typedef struct _ATOM_PPLIB_POWERPLAYTABLE3 typedef struct _ATOM_PPLIB_POWERPLAYTABLE4 { ATOM_PPLIB_POWERPLAYTABLE3 basicTable3; - ULONG ulGoldenPPID; // PPGen use only + ULONG ulGoldenPPID; // PPGen use only ULONG ulGoldenRevision; // PPGen use only USHORT usVddcDependencyOnSCLKOffset; USHORT usVddciDependencyOnMCLKOffset; USHORT usVddcDependencyOnMCLKOffset; USHORT usMaxClockVoltageOnDCOffset; USHORT usVddcPhaseShedLimitsTableOffset; // Points to ATOM_PPLIB_PhaseSheddingLimits_Table - USHORT usMvddDependencyOnMCLKOffset; + USHORT usMvddDependencyOnMCLKOffset; } ATOM_PPLIB_POWERPLAYTABLE4, *LPATOM_PPLIB_POWERPLAYTABLE4; typedef struct _ATOM_PPLIB_POWERPLAYTABLE5 @@ -374,23 +374,23 @@ typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO UCHAR ucPadding; // For proper alignment and size. USHORT usVDDC; // For the 780, use: None, Low, High, Variable UCHAR ucMaxHTLinkWidth; // From SBIOS - {2, 4, 8, 16} - UCHAR ucMinHTLinkWidth; // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled. Minimum down stream width could + UCHAR ucMinHTLinkWidth; // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled. Minimum down stream width could USHORT usHTLinkFreq; // See definition ATOM_PPLIB_RS780_HTLINKFREQ_xxx or in MHz(>=200). - ULONG ulFlags; + ULONG ulFlags; } ATOM_PPLIB_RS780_CLOCK_INFO; -#define ATOM_PPLIB_RS780_VOLTAGE_NONE 0 -#define ATOM_PPLIB_RS780_VOLTAGE_LOW 1 -#define ATOM_PPLIB_RS780_VOLTAGE_HIGH 2 -#define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE 3 +#define ATOM_PPLIB_RS780_VOLTAGE_NONE 0 +#define ATOM_PPLIB_RS780_VOLTAGE_LOW 1 +#define ATOM_PPLIB_RS780_VOLTAGE_HIGH 2 +#define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE 3 #define ATOM_PPLIB_RS780_SPMCLK_NONE 0 // We cannot change the side port memory clock, leave it as it is. #define ATOM_PPLIB_RS780_SPMCLK_LOW 1 #define ATOM_PPLIB_RS780_SPMCLK_HIGH 2 -#define ATOM_PPLIB_RS780_HTLINKFREQ_NONE 0 -#define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1 -#define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2 +#define ATOM_PPLIB_RS780_HTLINKFREQ_NONE 0 +#define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1 +#define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2 typedef struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO { @@ -432,14 +432,14 @@ typedef struct _ATOM_PPLIB_CI_CLOCK_INFO USHORT usMemoryClockLow; UCHAR ucMemoryClockHigh; - + UCHAR ucPCIEGen; USHORT usPCIELane; } ATOM_PPLIB_CI_CLOCK_INFO; typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO{ USHORT usEngineClockLow; //clockfrequency & 0xFFFF. The unit is in 10khz - UCHAR ucEngineClockHigh; //clockfrequency >> 16. + UCHAR ucEngineClockHigh; //clockfrequency >> 16. UCHAR vddcIndex; //2-bit vddc index; USHORT tdpLimit; //please initalize to 0 @@ -464,10 +464,10 @@ typedef struct _ATOM_PPLIB_CZ_CLOCK_INFO { typedef struct _ATOM_PPLIB_STATE_V2 { - //number of valid dpm levels in this state; Driver uses it to calculate the whole + //number of valid dpm levels in this state; Driver uses it to calculate the whole //size of the state: sizeof(ATOM_PPLIB_STATE_V2) + (ucNumDPMLevels - 1) * sizeof(UCHAR) UCHAR ucNumDPMLevels; - + //a index to the array of nonClockInfos UCHAR nonClockInfoIndex; /** @@ -477,9 +477,9 @@ typedef struct _ATOM_PPLIB_STATE_V2 } ATOM_PPLIB_STATE_V2; typedef struct _StateArray{ - //how many states we have + //how many states we have UCHAR ucNumEntries; - + ATOM_PPLIB_STATE_V2 states[1]; }StateArray; @@ -487,10 +487,10 @@ typedef struct _StateArray{ typedef struct _ClockInfoArray{ //how many clock levels we have UCHAR ucNumEntries; - + //sizeof(ATOM_PPLIB_CLOCK_INFO) UCHAR ucEntrySize; - + UCHAR clockInfo[1]; }ClockInfoArray; @@ -500,7 +500,7 @@ typedef struct _NonClockInfoArray{ UCHAR ucNumEntries; //sizeof(ATOM_PPLIB_NONCLOCK_INFO) UCHAR ucEntrySize; - + ATOM_PPLIB_NONCLOCK_INFO nonClockInfo[1]; }NonClockInfoArray; @@ -722,7 +722,7 @@ typedef struct _ATOM_PPLIB_PPM_Table ULONG ulPlatformTDC; ULONG ulSmallACPlatformTDC; ULONG ulApuTDP; - ULONG ulDGpuTDP; + ULONG ulDGpuTDP; ULONG ulDGpuUlvPower; ULONG ulTjmax; } ATOM_PPLIB_PPM_Table; diff --git a/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.c b/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.c index a47a47238..83734e516 100644 --- a/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.c +++ b/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.c @@ -158,7 +158,7 @@ int pp_atomfwctrl_get_voltage_table_v4(struct pp_hwmgr *hwmgr, return result; } - + static struct atom_gpio_pin_lut_v2_1 *pp_atomfwctrl_get_gpio_lookup_table( struct pp_hwmgr *hwmgr) { diff --git a/sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h b/sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h index c2efc70ef..1af4c00d0 100644 --- a/sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h +++ b/sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h @@ -773,8 +773,8 @@ typedef struct { uint8_t Gfx_IdleHystLimit; uint8_t Gfx_FPS; uint8_t Gfx_MinActiveFreqType; - uint8_t Gfx_BoosterFreqType; - uint8_t Gfx_UseRlcBusy; + uint8_t Gfx_BoosterFreqType; + uint8_t Gfx_UseRlcBusy; uint16_t Gfx_MinActiveFreq; uint16_t Gfx_BoosterFreq; uint16_t Gfx_PD_Data_time_constant; @@ -788,7 +788,7 @@ typedef struct { uint8_t Soc_IdleHystLimit; uint8_t Soc_FPS; uint8_t Soc_MinActiveFreqType; - uint8_t Soc_BoosterFreqType; + uint8_t Soc_BoosterFreqType; uint8_t Soc_UseRlcBusy; uint16_t Soc_MinActiveFreq; uint16_t Soc_BoosterFreq; @@ -804,7 +804,7 @@ typedef struct { uint8_t Mem_FPS; uint8_t Mem_MinActiveFreqType; uint8_t Mem_BoosterFreqType; - uint8_t Mem_UseRlcBusy; + uint8_t Mem_UseRlcBusy; uint16_t Mem_MinActiveFreq; uint16_t Mem_BoosterFreq; uint16_t Mem_PD_Data_time_constant; diff --git a/sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h b/sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h index 5916be08a..c1544c9b8 100644 --- a/sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h +++ b/sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h @@ -127,7 +127,7 @@ typedef struct SMU73_Discrete_MemoryLevel SMU73_Discrete_MemoryLevel; struct SMU73_Discrete_LinkLevel { uint8_t PcieGenSpeed; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 - uint8_t PcieLaneCount; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 + uint8_t PcieLaneCount; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 uint8_t EnabledForActivity; uint8_t SPC; uint32_t DownThreshold; diff --git a/sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h b/sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h index 350889e40..8582062f9 100644 --- a/sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h +++ b/sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h @@ -809,7 +809,7 @@ typedef struct SMU7_GfxCuPgScoreboard SMU7_GfxCuPgScoreboard; #define DB_Enable_MASK 0x1000000 #define DB_IR_MASK 0x2000000 -#define DB_PCC_MASK 0x4000000 +#define DB_PCC_MASK 0x4000000 #define DB_EDC_MASK 0x8000000 #define SQ_Enable_SHIFT 0 @@ -829,7 +829,7 @@ typedef struct SMU7_GfxCuPgScoreboard SMU7_GfxCuPgScoreboard; #define DB_Enable_SHIFT 24 #define DB_IR_SHIFT 25 -#define DB_PCC_SHIFT 26 +#define DB_PCC_SHIFT 26 #define DB_EDC_SHIFT 27 #define BTCGB0_Vdroop_Enable_MASK 0x1 diff --git a/sys/dev/pci/drm/amd/pm/powerplay/inc/smu_ucode_xfer_cz.h b/sys/dev/pci/drm/amd/pm/powerplay/inc/smu_ucode_xfer_cz.h index 701aae598..ed3c4b01f 100644 --- a/sys/dev/pci/drm/amd/pm/powerplay/inc/smu_ucode_xfer_cz.h +++ b/sys/dev/pci/drm/amd/pm/powerplay/inc/smu_ucode_xfer_cz.h @@ -56,7 +56,7 @@ #define END_OF_TASK_LIST (uint16_t)0xffff // Size of DRAM regions (in bytes) requested by SMU: -#define SMU_DRAM_REQ_MM_PWR_LOG 48 +#define SMU_DRAM_REQ_MM_PWR_LOG 48 #define UCODE_ID_SDMA0 0 #define UCODE_ID_SDMA1 1 @@ -73,35 +73,35 @@ #define UCODE_ID_DMCU_ERAM 12 #define UCODE_ID_DMCU_IRAM 13 -#define UCODE_ID_SDMA0_MASK 0x00000001 -#define UCODE_ID_SDMA1_MASK 0x00000002 -#define UCODE_ID_CP_CE_MASK 0x00000004 -#define UCODE_ID_CP_PFP_MASK 0x00000008 -#define UCODE_ID_CP_ME_MASK 0x00000010 -#define UCODE_ID_CP_MEC_JT1_MASK 0x00000020 -#define UCODE_ID_CP_MEC_JT2_MASK 0x00000040 -#define UCODE_ID_GMCON_RENG_MASK 0x00000080 -#define UCODE_ID_RLC_G_MASK 0x00000100 -#define UCODE_ID_RLC_SCRATCH_MASK 0x00000200 -#define UCODE_ID_RLC_SRM_ARAM_MASK 0x00000400 -#define UCODE_ID_RLC_SRM_DRAM_MASK 0x00000800 -#define UCODE_ID_DMCU_ERAM_MASK 0x00001000 -#define UCODE_ID_DMCU_IRAM_MASK 0x00002000 +#define UCODE_ID_SDMA0_MASK 0x00000001 +#define UCODE_ID_SDMA1_MASK 0x00000002 +#define UCODE_ID_CP_CE_MASK 0x00000004 +#define UCODE_ID_CP_PFP_MASK 0x00000008 +#define UCODE_ID_CP_ME_MASK 0x00000010 +#define UCODE_ID_CP_MEC_JT1_MASK 0x00000020 +#define UCODE_ID_CP_MEC_JT2_MASK 0x00000040 +#define UCODE_ID_GMCON_RENG_MASK 0x00000080 +#define UCODE_ID_RLC_G_MASK 0x00000100 +#define UCODE_ID_RLC_SCRATCH_MASK 0x00000200 +#define UCODE_ID_RLC_SRM_ARAM_MASK 0x00000400 +#define UCODE_ID_RLC_SRM_DRAM_MASK 0x00000800 +#define UCODE_ID_DMCU_ERAM_MASK 0x00001000 +#define UCODE_ID_DMCU_IRAM_MASK 0x00002000 -#define UCODE_ID_SDMA0_SIZE_BYTE 10368 -#define UCODE_ID_SDMA1_SIZE_BYTE 10368 -#define UCODE_ID_CP_CE_SIZE_BYTE 8576 -#define UCODE_ID_CP_PFP_SIZE_BYTE 16768 -#define UCODE_ID_CP_ME_SIZE_BYTE 16768 -#define UCODE_ID_CP_MEC_JT1_SIZE_BYTE 384 -#define UCODE_ID_CP_MEC_JT2_SIZE_BYTE 384 -#define UCODE_ID_GMCON_RENG_SIZE_BYTE 4096 -#define UCODE_ID_RLC_G_SIZE_BYTE 2048 -#define UCODE_ID_RLC_SCRATCH_SIZE_BYTE 132 -#define UCODE_ID_RLC_SRM_ARAM_SIZE_BYTE 8192 -#define UCODE_ID_RLC_SRM_DRAM_SIZE_BYTE 4096 -#define UCODE_ID_DMCU_ERAM_SIZE_BYTE 24576 -#define UCODE_ID_DMCU_IRAM_SIZE_BYTE 1024 +#define UCODE_ID_SDMA0_SIZE_BYTE 10368 +#define UCODE_ID_SDMA1_SIZE_BYTE 10368 +#define UCODE_ID_CP_CE_SIZE_BYTE 8576 +#define UCODE_ID_CP_PFP_SIZE_BYTE 16768 +#define UCODE_ID_CP_ME_SIZE_BYTE 16768 +#define UCODE_ID_CP_MEC_JT1_SIZE_BYTE 384 +#define UCODE_ID_CP_MEC_JT2_SIZE_BYTE 384 +#define UCODE_ID_GMCON_RENG_SIZE_BYTE 4096 +#define UCODE_ID_RLC_G_SIZE_BYTE 2048 +#define UCODE_ID_RLC_SCRATCH_SIZE_BYTE 132 +#define UCODE_ID_RLC_SRM_ARAM_SIZE_BYTE 8192 +#define UCODE_ID_RLC_SRM_DRAM_SIZE_BYTE 4096 +#define UCODE_ID_DMCU_ERAM_SIZE_BYTE 24576 +#define UCODE_ID_DMCU_IRAM_SIZE_BYTE 1024 #define NUM_UCODES 14 @@ -125,9 +125,9 @@ struct TOC { }; // META DATA COMMAND Definitions -#define METADATA_CMD_MODE0 0x00000103 -#define METADATA_CMD_MODE1 0x00000113 -#define METADATA_CMD_MODE2 0x00000123 +#define METADATA_CMD_MODE0 0x00000103 +#define METADATA_CMD_MODE1 0x00000113 +#define METADATA_CMD_MODE2 0x00000123 #define METADATA_CMD_MODE3 0x00000133 #define METADATA_CMD_DELAY 0x00000203 #define METADATA_CMD_CHNG_REGSPACE 0x00000303 diff --git a/sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h b/sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h index 6456bea5d..5cf62a929 100644 --- a/sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h +++ b/sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h @@ -365,7 +365,7 @@ typedef struct { uint16_t FanMaximumRpm; uint16_t FanTargetTemperature; uint16_t FanTargetGfxclk; - uint8_t FanZeroRpmEnable; + uint8_t FanZeroRpmEnable; uint8_t FanTachEdgePerRev; @@ -659,8 +659,8 @@ typedef struct { uint8_t Gfx_IdleHystLimit; uint8_t Gfx_FPS; uint8_t Gfx_MinActiveFreqType; - uint8_t Gfx_BoosterFreqType; - uint8_t Gfx_UseRlcBusy; + uint8_t Gfx_BoosterFreqType; + uint8_t Gfx_UseRlcBusy; uint16_t Gfx_MinActiveFreq; uint16_t Gfx_BoosterFreq; uint16_t Gfx_PD_Data_time_constant; @@ -674,7 +674,7 @@ typedef struct { uint8_t Soc_IdleHystLimit; uint8_t Soc_FPS; uint8_t Soc_MinActiveFreqType; - uint8_t Soc_BoosterFreqType; + uint8_t Soc_BoosterFreqType; uint8_t Soc_UseRlcBusy; uint16_t Soc_MinActiveFreq; uint16_t Soc_BoosterFreq; @@ -690,7 +690,7 @@ typedef struct { uint8_t Mem_FPS; uint8_t Mem_MinActiveFreqType; uint8_t Mem_BoosterFreqType; - uint8_t Mem_UseRlcBusy; + uint8_t Mem_UseRlcBusy; uint16_t Mem_MinActiveFreq; uint16_t Mem_BoosterFreq; uint16_t Mem_PD_Data_time_constant; diff --git a/sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h index d070ce60f..7a6c8adf5 100644 --- a/sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h +++ b/sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h @@ -1315,8 +1315,8 @@ struct pptable_funcs { * @get_ecc_table: message SMU to get ECC INFO table. */ ssize_t (*get_ecc_info)(struct smu_context *smu, void *table); - - + + /** * @stb_collect_info: Collects Smart Trace Buffers data. */ diff --git a/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h b/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h index c5c1943fb..32fbab419 100644 --- a/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h +++ b/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h @@ -24,7 +24,7 @@ #define __SMU11_DRIVER_IF_NAVI10_H__ // *** IMPORTANT *** -// SMU TEAM: Always increment the interface version if +// SMU TEAM: Always increment the interface version if // any structure is changed in this file // Be aware of that the version should be updated in // smu_v11_0.h, maybe rename is also needed. @@ -42,7 +42,7 @@ #define NUM_PHYCLK_DPM_LEVELS 8 #define NUM_DISPCLK_DPM_LEVELS 8 #define NUM_PIXCLK_DPM_LEVELS 8 -#define NUM_UCLK_DPM_LEVELS 4 +#define NUM_UCLK_DPM_LEVELS 4 #define NUM_MP1CLK_DPM_LEVELS 2 #define NUM_LINK_LEVELS 2 @@ -76,24 +76,24 @@ #define FEATURE_DPM_MP0CLK_BIT 5 #define FEATURE_DPM_LINK_BIT 6 #define FEATURE_DPM_DCEFCLK_BIT 7 -#define FEATURE_MEM_VDDCI_SCALING_BIT 8 +#define FEATURE_MEM_VDDCI_SCALING_BIT 8 #define FEATURE_MEM_MVDD_SCALING_BIT 9 - -//Idle + +//Idle #define FEATURE_DS_GFXCLK_BIT 10 #define FEATURE_DS_SOCCLK_BIT 11 #define FEATURE_DS_LCLK_BIT 12 #define FEATURE_DS_DCEFCLK_BIT 13 #define FEATURE_DS_UCLK_BIT 14 -#define FEATURE_GFX_ULV_BIT 15 -#define FEATURE_FW_DSTATE_BIT 16 +#define FEATURE_GFX_ULV_BIT 15 +#define FEATURE_FW_DSTATE_BIT 16 #define FEATURE_GFXOFF_BIT 17 #define FEATURE_BACO_BIT 18 -#define FEATURE_VCN_PG_BIT 19 +#define FEATURE_VCN_PG_BIT 19 #define FEATURE_JPEG_PG_BIT 20 #define FEATURE_USB_PG_BIT 21 #define FEATURE_RSMU_SMN_CG_BIT 22 -//Throttler/Response +//Throttler/Response #define FEATURE_PPT_BIT 23 #define FEATURE_TDC_BIT 24 #define FEATURE_GFX_EDC_BIT 25 @@ -101,15 +101,15 @@ #define FEATURE_GTHR_BIT 27 #define FEATURE_ACDC_BIT 28 #define FEATURE_VR0HOT_BIT 29 -#define FEATURE_VR1HOT_BIT 30 +#define FEATURE_VR1HOT_BIT 30 #define FEATURE_FW_CTF_BIT 31 #define FEATURE_FAN_CONTROL_BIT 32 #define FEATURE_THERMAL_BIT 33 #define FEATURE_GFX_DCS_BIT 34 -//VF +//VF #define FEATURE_RM_BIT 35 #define FEATURE_LED_DISPLAY_BIT 36 -//Other +//Other #define FEATURE_GFX_SS_BIT 37 #define FEATURE_OUT_OF_BAND_MONITOR_BIT 38 #define FEATURE_TEMP_DEPENDENT_VMIN_BIT 39 @@ -202,13 +202,13 @@ #define FW_DSTATE_MP1_DS_BIT 5 #define FW_DSTATE_MP1_WHISPER_MODE_BIT 6 #define FW_DSTATE_LIV_MIN_BIT 7 -#define FW_DSTATE_SOC_PLL_PWRDN_BIT 8 +#define FW_DSTATE_SOC_PLL_PWRDN_BIT 8 #define FW_DSTATE_SOC_ULV_MASK (1 << FW_DSTATE_SOC_ULV_BIT ) #define FW_DSTATE_G6_HSR_MASK (1 << FW_DSTATE_G6_HSR_BIT ) #define FW_DSTATE_G6_PHY_VDDCI_OFF_MASK (1 << FW_DSTATE_G6_PHY_VDDCI_OFF_BIT ) -#define FW_DSTATE_MP1_DS_MASK (1 << FW_DSTATE_MP1_DS_BIT ) -#define FW_DSTATE_MP0_DS_MASK (1 << FW_DSTATE_MP0_DS_BIT ) +#define FW_DSTATE_MP1_DS_MASK (1 << FW_DSTATE_MP1_DS_BIT ) +#define FW_DSTATE_MP0_DS_MASK (1 << FW_DSTATE_MP0_DS_BIT ) #define FW_DSTATE_SMN_DS_MASK (1 << FW_DSTATE_SMN_DS_BIT ) #define FW_DSTATE_MP1_WHISPER_MODE_MASK (1 << FW_DSTATE_MP1_WHISPER_MODE_BIT ) #define FW_DSTATE_LIV_MIN_MASK (1 << FW_DSTATE_LIV_MIN_BIT ) @@ -235,10 +235,10 @@ typedef enum { I2C_CONTROLLER_NAME_VR_VDDCI, I2C_CONTROLLER_NAME_VR_MVDD, I2C_CONTROLLER_NAME_LIQUID0, - I2C_CONTROLLER_NAME_LIQUID1, + I2C_CONTROLLER_NAME_LIQUID1, I2C_CONTROLLER_NAME_PLX, I2C_CONTROLLER_NAME_SPARE, - I2C_CONTROLLER_NAME_COUNT, + I2C_CONTROLLER_NAME_COUNT, } I2cControllerName_e; typedef enum { @@ -248,9 +248,9 @@ typedef enum { I2C_CONTROLLER_THROTTLER_VR_VDDCI, I2C_CONTROLLER_THROTTLER_VR_MVDD, I2C_CONTROLLER_THROTTLER_LIQUID0, - I2C_CONTROLLER_THROTTLER_LIQUID1, + I2C_CONTROLLER_THROTTLER_LIQUID1, I2C_CONTROLLER_THROTTLER_PLX, - I2C_CONTROLLER_THROTTLER_COUNT, + I2C_CONTROLLER_THROTTLER_COUNT, } I2cControllerThrottler_e; typedef enum { @@ -260,7 +260,7 @@ typedef enum { I2C_CONTROLLER_PROTOCOL_TMP_1, I2C_CONTROLLER_PROTOCOL_SPARE_0, I2C_CONTROLLER_PROTOCOL_SPARE_1, - I2C_CONTROLLER_PROTOCOL_COUNT, + I2C_CONTROLLER_PROTOCOL_COUNT, } I2cControllerProtocol_e; typedef struct { @@ -275,9 +275,9 @@ typedef struct { } I2cControllerConfig_t; typedef enum { - I2C_PORT_SVD_SCL = 0, - I2C_PORT_GPIO, -} I2cPort_e; + I2C_PORT_SVD_SCL = 0, + I2C_PORT_GPIO, +} I2cPort_e; typedef enum { I2C_SPEED_FAST_50K = 0, //50 Kbits/s @@ -285,14 +285,14 @@ typedef enum { I2C_SPEED_FAST_400K, //400 Kbits/s I2C_SPEED_FAST_PLUS_1M, //1 Mbits/s (in fast mode) I2C_SPEED_HIGH_1M, //1 Mbits/s (in high speed mode) - I2C_SPEED_HIGH_2M, //2.3 Mbits/s - I2C_SPEED_COUNT, + I2C_SPEED_HIGH_2M, //2.3 Mbits/s + I2C_SPEED_COUNT, } I2cSpeed_e; typedef enum { I2C_CMD_READ = 0, I2C_CMD_WRITE, - I2C_CMD_COUNT, + I2C_CMD_COUNT, } I2cCmdType_e; #define CMDCONFIG_STOP_BIT 0 @@ -303,7 +303,7 @@ typedef enum { typedef struct { uint8_t RegisterAddr; ////only valid for write, ignored for read - uint8_t Cmd; //Read(0) or Write(1) + uint8_t Cmd; //Read(0) or Write(1) uint8_t Data; //Return data for read. Data to send for write uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command } SwI2cCmd_t; //SW I2C Command Table @@ -318,7 +318,7 @@ typedef struct { SwI2cCmd_t SwI2cCmds[MAX_SW_I2C_COMMANDS]; uint32_t MmHubPadding[8]; // SMU internal use - + } SwI2cRequest_t; // SW I2C Request Table //D3HOT sequences @@ -342,30 +342,30 @@ typedef enum { PG_POWER_UP, } PowerGatingSettings_e; -typedef struct { +typedef struct { uint32_t a; // store in IEEE float format in this variable uint32_t b; // store in IEEE float format in this variable uint32_t c; // store in IEEE float format in this variable } QuadraticInt_t; -typedef struct { +typedef struct { uint32_t m; // store in IEEE float format in this variable uint32_t b; // store in IEEE float format in this variable } LinearInt_t; -typedef struct { +typedef struct { uint32_t a; // store in IEEE float format in this variable uint32_t b; // store in IEEE float format in this variable uint32_t c; // store in IEEE float format in this variable } DroopInt_t; typedef enum { - GFXCLK_SOURCE_PLL = 0, - GFXCLK_SOURCE_DFLL, - GFXCLK_SOURCE_COUNT, -} GfxclkSrc_e; + GFXCLK_SOURCE_PLL = 0, + GFXCLK_SOURCE_DFLL, + GFXCLK_SOURCE_COUNT, +} GfxclkSrc_e; -//Only Clks that have DPM descriptors are listed here +//Only Clks that have DPM descriptors are listed here typedef enum { PPCLK_GFXCLK = 0, PPCLK_SOCCLK, @@ -389,7 +389,7 @@ typedef enum { PPT_THROTTLER_PPT0, PPT_THROTTLER_PPT1, PPT_THROTTLER_PPT2, - PPT_THROTTLER_PPT3, + PPT_THROTTLER_PPT3, PPT_THROTTLER_COUNT } PPT_THROTTLER_e; @@ -435,7 +435,7 @@ typedef struct { uint8_t VoltageMode; // 0 - AVFS only, 1- min(AVFS,SS), 2-SS only uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM uint8_t NumDiscreteLevels; // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used - uint8_t Padding; + uint8_t Padding; LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz) QuadraticInt_t SsCurve; // Slow-slow curve (GHz->V) } DpmDescriptor_t; @@ -447,9 +447,9 @@ typedef enum { TEMP_VR_GFX, TEMP_VR_MEM0, TEMP_VR_MEM1, - TEMP_VR_SOC, + TEMP_VR_SOC, TEMP_LIQUID0, - TEMP_LIQUID1, + TEMP_LIQUID1, TEMP_PLX, TEMP_COUNT } TEMP_e; @@ -468,14 +468,14 @@ typedef enum { #define HBM_TEMPERATURE_EXCEEDING_TEMPERATURE_LIMIT_BIT 13 #define HBM_TEMPERATURE_EXCEEDING_MAX_MEMORY_TEMPERATURE_BIT 14 -#define POWER_MANAGER_CONTROLLER_MASK (1 << POWER_MANAGER_CONTROLLER_BIT ) +#define POWER_MANAGER_CONTROLLER_MASK (1 << POWER_MANAGER_CONTROLLER_BIT ) #define MAXIMUM_DPM_STATE_GFX_ENGINE_RESTRICTED_MASK (1 << MAXIMUM_DPM_STATE_GFX_ENGINE_RESTRICTED_BIT ) -#define GPU_DIE_TEMPERATURE_THROTTLING_MASK (1 << GPU_DIE_TEMPERATURE_THROTTLING_BIT ) +#define GPU_DIE_TEMPERATURE_THROTTLING_MASK (1 << GPU_DIE_TEMPERATURE_THROTTLING_BIT ) #define HBM_DIE_TEMPERATURE_THROTTLING_MASK (1 << HBM_DIE_TEMPERATURE_THROTTLING_BIT ) #define TGP_THROTTLING_MASK (1 << TGP_THROTTLING_BIT ) #define PCC_THROTTLING_MASK (1 << PCC_THROTTLING_BIT ) #define HBM_TEMPERATURE_EXCEEDING_TEMPERATURE_LIMIT_MASK (1 << HBM_TEMPERATURE_EXCEEDING_TEMPERATURE_LIMIT_BIT ) -#define HBM_TEMPERATURE_EXCEEDING_MAX_MEMORY_TEMPERATURE_MASK (1 << HBM_TEMPERATURE_EXCEEDING_MAX_MEMORY_TEMPERATURE_BIT) +#define HBM_TEMPERATURE_EXCEEDING_MAX_MEMORY_TEMPERATURE_MASK (1 << HBM_TEMPERATURE_EXCEEDING_MAX_MEMORY_TEMPERATURE_BIT) //This structure to be DMA to SMBUS Config register space typedef struct { @@ -500,7 +500,7 @@ typedef struct { uint32_t DieTemperatureRegisterOffset; uint32_t Reserved2; - + uint32_t Reserved3; uint32_t Status; @@ -512,7 +512,7 @@ typedef struct { uint8_t MemoryHotspotPosition; uint8_t Reserved4; - uint32_t BoardLevelEnergyAccumulator; + uint32_t BoardLevelEnergyAccumulator; } OutOfBandMonitor_t; #pragma pack(push, 1) @@ -526,19 +526,19 @@ typedef struct { uint16_t SocketPowerLimitAc[PPT_THROTTLER_COUNT]; uint16_t SocketPowerLimitAcTau[PPT_THROTTLER_COUNT]; uint16_t SocketPowerLimitDc[PPT_THROTTLER_COUNT]; - uint16_t SocketPowerLimitDcTau[PPT_THROTTLER_COUNT]; + uint16_t SocketPowerLimitDcTau[PPT_THROTTLER_COUNT]; uint16_t TdcLimitSoc; // Amps uint16_t TdcLimitSocTau; // Time constant of LPF in ms uint16_t TdcLimitGfx; // Amps uint16_t TdcLimitGfxTau; // Time constant of LPF in ms - + uint16_t TedgeLimit; // Celcius uint16_t ThotspotLimit; // Celcius uint16_t TmemLimit; // Celcius uint16_t Tvr_gfxLimit; // Celcius uint16_t Tvr_mem0Limit; // Celcius - uint16_t Tvr_mem1Limit; // Celcius + uint16_t Tvr_mem1Limit; // Celcius uint16_t Tvr_socLimit; // Celcius uint16_t Tliquid0Limit; // Celcius uint16_t Tliquid1Limit; // Celcius @@ -547,11 +547,11 @@ typedef struct { uint16_t PpmPowerLimit; // Switch this this power limit when temperature is above PpmTempThreshold uint16_t PpmTemperatureThreshold; - + // SECTION: Throttler settings uint32_t ThrottlerControlMask; // See Throtter masks defines - // SECTION: FW DSTATE Settings + // SECTION: FW DSTATE Settings uint32_t FwDStateMask; // See FW DState masks defines // SECTION: ULV Settings @@ -560,13 +560,13 @@ typedef struct { uint8_t GceaLinkMgrIdleThreshold; //Set by SMU FW during enablment of SOC_ULV. Controls delay for GFX SDP port disconnection during idle events uint8_t paddingRlcUlvParams[3]; - + uint8_t UlvSmnclkDid; //DID for ULV mode. 0 means CLK will not be modified in ULV. uint8_t UlvMp1clkDid; //DID for ULV mode. 0 means CLK will not be modified in ULV. uint8_t UlvGfxclkBypass; // 1 to turn off/bypass Gfxclk during ULV, 0 to leave Gfxclk on during ULV uint8_t Padding234; - uint16_t MinVoltageUlvGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX in ULV mode + uint16_t MinVoltageUlvGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX in ULV mode uint16_t MinVoltageUlvSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC in ULV mode @@ -595,7 +595,7 @@ typedef struct { uint16_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz uint16_t Padding8_Clks; - + uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:Div-1/8 // SECTION: DPM Config 2 @@ -605,11 +605,11 @@ typedef struct { uint16_t MemMvddVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) // GFXCLK DPM uint16_t GfxclkFgfxoffEntry; // in Mhz - uint16_t GfxclkFinit; // in Mhz + uint16_t GfxclkFinit; // in Mhz uint16_t GfxclkFidle; // in MHz uint16_t GfxclkSlewRate; // for PLL babystepping??? uint16_t GfxclkFopt; // in Mhz - uint8_t Padding567[2]; + uint8_t Padding567[2]; uint16_t GfxclkDsMaxFreq; // in MHz uint8_t GfxclkSource; // 0 = PLL, 1 = DFLL uint8_t Padding456; @@ -617,7 +617,7 @@ typedef struct { // UCLK section uint8_t LowestUclkReservedForUlv; // Set this to 1 if UCLK DPM0 is reserved for ULV-mode only uint8_t paddingUclk[3]; - + uint8_t MemoryType; // 0-GDDR6, 1-HBM uint8_t MemoryChannels; uint8_t PaddingMem[2]; @@ -625,14 +625,14 @@ typedef struct { // Link DPM Settings uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 - uint16_t LclkFreq[NUM_LINK_LEVELS]; + uint16_t LclkFreq[NUM_LINK_LEVELS]; // GFXCLK Thermal DPM (formerly 'Boost' Settings) - uint16_t EnableTdpm; + uint16_t EnableTdpm; uint16_t TdpmHighHystTemperature; uint16_t TdpmLowHystTemperature; uint16_t GfxclkFreqHighTempLimit; // High limit on GFXCLK when temperature is high, for reliability. - + // SECTION: Fan Control uint16_t FanStopTemp; //Celcius uint16_t FanStartTemp; //Celcius @@ -640,11 +640,11 @@ typedef struct { uint16_t FanGainEdge; uint16_t FanGainHotspot; uint16_t FanGainLiquid0; - uint16_t FanGainLiquid1; + uint16_t FanGainLiquid1; uint16_t FanGainVrGfx; uint16_t FanGainVrSoc; uint16_t FanGainVrMem0; - uint16_t FanGainVrMem1; + uint16_t FanGainVrMem1; uint16_t FanGainPlx; uint16_t FanGainMem; uint16_t FanPwmMin; @@ -655,10 +655,10 @@ typedef struct { uint16_t FanTargetGfxclk; uint8_t FanTempInputSelect; uint8_t FanPadding; - uint8_t FanZeroRpmEnable; + uint8_t FanZeroRpmEnable; uint8_t FanTachEdgePerRev; //uint8_t padding8_Fan[2]; - + // The following are AFC override parameters. Leave at 0 to use FW defaults. int16_t FuzzyFan_ErrorSetDelta; int16_t FuzzyFan_ErrorRateSetDelta; @@ -666,18 +666,18 @@ typedef struct { uint16_t FuzzyFan_Reserved; - // SECTION: AVFS + // SECTION: AVFS // Overrides uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT]; uint8_t Padding8_Avfs[2]; - QuadraticInt_t qAvfsGb[AVFS_VOLTAGE_COUNT]; // GHz->V Override of fused curve + QuadraticInt_t qAvfsGb[AVFS_VOLTAGE_COUNT]; // GHz->V Override of fused curve DroopInt_t dBtcGbGfxPll; // GHz->V BtcGb DroopInt_t dBtcGbGfxDfll; // GHz->V BtcGb DroopInt_t dBtcGbSoc; // GHz->V BtcGb - LinearInt_t qAgingGb[AVFS_VOLTAGE_COUNT]; // GHz->V + LinearInt_t qAgingGb[AVFS_VOLTAGE_COUNT]; // GHz->V - QuadraticInt_t qStaticVoltageOffset[AVFS_VOLTAGE_COUNT]; // GHz->V + QuadraticInt_t qStaticVoltageOffset[AVFS_VOLTAGE_COUNT]; // GHz->V uint16_t DcTol[AVFS_VOLTAGE_COUNT]; // mV Q2 @@ -689,14 +689,14 @@ typedef struct { // SECTION: Advanced Options uint32_t DebugOverrides; - QuadraticInt_t ReservedEquation0; - QuadraticInt_t ReservedEquation1; - QuadraticInt_t ReservedEquation2; - QuadraticInt_t ReservedEquation3; - + QuadraticInt_t ReservedEquation0; + QuadraticInt_t ReservedEquation1; + QuadraticInt_t ReservedEquation2; + QuadraticInt_t ReservedEquation3; + // Total Power configuration, use defines from PwrConfig_e uint8_t TotalPowerConfig; //0-TDP, 1-TGP, 2-TCP Estimated, 3-TCP Measured - uint8_t TotalPowerSpare1; + uint8_t TotalPowerSpare1; uint16_t TotalPowerSpare2; // APCC Settings @@ -712,13 +712,13 @@ typedef struct { uint16_t VDDGFX_Vmin_LoTemp; // mV Q2 uint16_t VDDSOC_Vmin_HiTemp; // mV Q2 uint16_t VDDSOC_Vmin_LoTemp; // mV Q2 - + uint16_t VDDGFX_TVminHystersis; // Celcius uint16_t VDDSOC_TVminHystersis; // Celcius // BTC Setting uint32_t BtcConfig; - + uint16_t SsFmin[10]; // PPtable value to function similar to VFTFmin for SS Curve; Size is PPCLK_COUNT rounded to nearest multiple of 2 uint16_t DcBtcGb[AVFS_VOLTAGE_COUNT]; @@ -727,12 +727,12 @@ typedef struct { // SECTION: BOARD PARAMETERS // I2C Control - I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS]; + I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS]; // SVI2 Board Parameters uint16_t MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. uint16_t MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. - + uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields @@ -741,7 +741,7 @@ typedef struct { uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN) - uint8_t Padding8_V; + uint8_t Padding8_V; // Telemetry Settings uint16_t GfxMaxCurrent; // in Amps @@ -755,19 +755,19 @@ typedef struct { uint16_t Mem0MaxCurrent; // in Amps int8_t Mem0Offset; // in Amps uint8_t Padding_TelemetryMem0; - + uint16_t Mem1MaxCurrent; // in Amps int8_t Mem1Offset; // in Amps uint8_t Padding_TelemetryMem1; - + // GPIO Settings uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event - uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event - uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event + uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event + uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event uint8_t GthrGpio; // GPIO pin configured for GTHR Event uint8_t GthrPolarity; // replace GPIO polarity for GTHR @@ -776,7 +776,7 @@ typedef struct { uint8_t LedPin1; // GPIO number for LedPin[1] uint8_t LedPin2; // GPIO number for LedPin[2] uint8_t padding8_4; - + // GFXCLK PLL Spread Spectrum uint8_t PllGfxclkSpreadEnabled; // on or off uint8_t PllGfxclkSpreadPercent; // Q4.4 @@ -786,7 +786,7 @@ typedef struct { uint8_t DfllGfxclkSpreadEnabled; // on or off uint8_t DfllGfxclkSpreadPercent; // Q4.4 uint16_t DfllGfxclkSpreadFreq; // kHz - + // UCLK Spread Spectrum uint8_t UclkSpreadEnabled; // on or off uint8_t UclkSpreadPercent; // Q4.4 @@ -799,7 +799,7 @@ typedef struct { // Total board power uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power - uint16_t BoardPadding; + uint16_t BoardPadding; // Mvdd Svi2 Div Ratio Setting uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16) @@ -831,7 +831,7 @@ typedef struct { } DriverSmuConfig_t; typedef struct { - + uint16_t GfxclkFmin; // MHz uint16_t GfxclkFmax; // MHz uint16_t GfxclkFreq1; // MHz @@ -844,7 +844,7 @@ typedef struct { int16_t OverDrivePct; // % uint16_t FanMaximumRpm; uint16_t FanMinimumPwm; - uint16_t FanTargetTemperature; // Degree Celcius + uint16_t FanTargetTemperature; // Degree Celcius uint16_t FanMode; uint16_t FanMaxPwm; uint16_t FanMinPwm; @@ -855,7 +855,7 @@ typedef struct { uint32_t MmHubPadding[6]; // SMU internal use -} OverDriveTable_t; +} OverDriveTable_t; typedef struct { uint16_t CurrClock[PPCLK_COUNT]; @@ -874,14 +874,14 @@ typedef struct { uint16_t TemperatureMem ; uint16_t TemperatureVrGfx ; uint16_t TemperatureVrMem0 ; - uint16_t TemperatureVrMem1 ; - uint16_t TemperatureVrSoc ; + uint16_t TemperatureVrMem1 ; + uint16_t TemperatureVrSoc ; uint16_t TemperatureLiquid0 ; - uint16_t TemperatureLiquid1 ; + uint16_t TemperatureLiquid1 ; uint16_t TemperaturePlx ; uint16_t Padding16 ; - uint32_t ThrottlerStatus ; - + uint32_t ThrottlerStatus ; + uint8_t LinkDpmLevel; uint8_t Padding8_2; uint16_t CurrFanSpeed; @@ -907,14 +907,14 @@ typedef struct { uint16_t TemperatureMem ; uint16_t TemperatureVrGfx ; uint16_t TemperatureVrMem0 ; - uint16_t TemperatureVrMem1 ; - uint16_t TemperatureVrSoc ; + uint16_t TemperatureVrMem1 ; + uint16_t TemperatureVrSoc ; uint16_t TemperatureLiquid0 ; - uint16_t TemperatureLiquid1 ; + uint16_t TemperatureLiquid1 ; uint16_t TemperaturePlx ; uint16_t Padding16 ; - uint32_t ThrottlerStatus ; - + uint32_t ThrottlerStatus ; + uint8_t LinkDpmLevel; uint8_t Padding8_2; uint16_t CurrFanSpeed; @@ -1024,11 +1024,11 @@ typedef struct { uint16_t MaxClock; // This is either DCEFCLK or SOCCLK (in MHz) uint16_t MinUclk; uint16_t MaxUclk; - + uint8_t WmSetting; uint8_t Padding[3]; - uint32_t MmHubPadding[8]; // SMU internal use + uint32_t MmHubPadding[8]; // SMU internal use } WatermarkRowGeneric_t; #define NUM_WM_RANGES 4 @@ -1058,7 +1058,7 @@ typedef struct { typedef struct { uint16_t avgPsmCount[36]; uint16_t minPsmCount[36]; - float avgPsmVoltage[36]; + float avgPsmVoltage[36]; float minPsmVoltage[36]; uint32_t MmHubPadding[8]; // SMU internal use @@ -1069,7 +1069,7 @@ typedef struct { uint8_t Padding; uint8_t AvfsEn[AVFS_VOLTAGE_COUNT]; - + uint8_t OverrideVFT[AVFS_VOLTAGE_COUNT]; uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT]; @@ -1122,7 +1122,7 @@ typedef struct { uint8_t Gfx_IdleHystLimit; uint8_t Gfx_FPS; uint8_t Gfx_MinActiveFreqType; - uint8_t Gfx_BoosterFreqType; + uint8_t Gfx_BoosterFreqType; uint8_t Gfx_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock. uint16_t Gfx_MinActiveFreq; // MHz uint16_t Gfx_BoosterFreq; // MHz @@ -1132,12 +1132,12 @@ typedef struct { uint32_t Gfx_PD_Data_limit_c; // Q16 uint32_t Gfx_PD_Data_error_coeff; // Q16 uint32_t Gfx_PD_Data_error_rate_coeff; // Q16 - + uint8_t Soc_ActiveHystLimit; uint8_t Soc_IdleHystLimit; uint8_t Soc_FPS; uint8_t Soc_MinActiveFreqType; - uint8_t Soc_BoosterFreqType; + uint8_t Soc_BoosterFreqType; uint8_t Soc_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock. uint16_t Soc_MinActiveFreq; // MHz uint16_t Soc_BoosterFreq; // MHz @@ -1147,7 +1147,7 @@ typedef struct { uint32_t Soc_PD_Data_limit_c; // Q16 uint32_t Soc_PD_Data_error_coeff; // Q16 uint32_t Soc_PD_Data_error_rate_coeff; // Q16 - + uint8_t Mem_ActiveHystLimit; uint8_t Mem_IdleHystLimit; uint8_t Mem_FPS; @@ -1168,20 +1168,20 @@ typedef struct { uint8_t Mem_DownHystLimit; uint16_t Mem_Fps; - uint32_t MmHubPadding[8]; // SMU internal use + uint32_t MmHubPadding[8]; // SMU internal use } DpmActivityMonitorCoeffInt_t; // Workload bits -#define WORKLOAD_PPLIB_DEFAULT_BIT 0 -#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1 -#define WORKLOAD_PPLIB_POWER_SAVING_BIT 2 -#define WORKLOAD_PPLIB_VIDEO_BIT 3 -#define WORKLOAD_PPLIB_VR_BIT 4 -#define WORKLOAD_PPLIB_COMPUTE_BIT 5 -#define WORKLOAD_PPLIB_CUSTOM_BIT 6 -#define WORKLOAD_PPLIB_COUNT 7 +#define WORKLOAD_PPLIB_DEFAULT_BIT 0 +#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1 +#define WORKLOAD_PPLIB_POWER_SAVING_BIT 2 +#define WORKLOAD_PPLIB_VIDEO_BIT 3 +#define WORKLOAD_PPLIB_VR_BIT 4 +#define WORKLOAD_PPLIB_COMPUTE_BIT 5 +#define WORKLOAD_PPLIB_CUSTOM_BIT 6 +#define WORKLOAD_PPLIB_COUNT 7 // These defines are used with the following messages: @@ -1212,8 +1212,8 @@ typedef struct { typedef struct { float FlopsPerByteTable[RLC_PACE_TABLE_NUM_LEVELS]; - - uint32_t MmHubPadding[8]; // SMU internal use + + uint32_t MmHubPadding[8]; // SMU internal use } RlcPaceFlopsPerByteOverride_t; // These defines are used with the SMC_MSG_SetUclkFastSwitch message. diff --git a/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h b/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h index aa6d29de4..63de29ca3 100644 --- a/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h +++ b/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h @@ -25,7 +25,7 @@ #define __SMU11_DRIVER_IF_SIENNA_CICHLID_H__ // *** IMPORTANT *** -// SMU TEAM: Always increment the interface version if +// SMU TEAM: Always increment the interface version if // any structure is changed in this file #define SMU11_DRIVER_IF_VERSION 0x40 @@ -42,10 +42,10 @@ #define NUM_DISPCLK_DPM_LEVELS 8 #define NUM_PIXCLK_DPM_LEVELS 8 #define NUM_DTBCLK_DPM_LEVELS 8 -#define NUM_UCLK_DPM_LEVELS 4 +#define NUM_UCLK_DPM_LEVELS 4 #define NUM_MP1CLK_DPM_LEVELS 2 #define NUM_LINK_LEVELS 2 -#define NUM_FCLK_DPM_LEVELS 8 +#define NUM_FCLK_DPM_LEVELS 8 #define NUM_XGMI_LEVELS 2 #define NUM_XGMI_PSTATE_LEVELS 4 #define NUM_OD_FAN_MAX_POINTS 6 @@ -83,43 +83,43 @@ #define FEATURE_DPM_LINK_BIT 7 #define FEATURE_DPM_DCEFCLK_BIT 8 #define FEATURE_DPM_XGMI_BIT 9 -#define FEATURE_MEM_VDDCI_SCALING_BIT 10 +#define FEATURE_MEM_VDDCI_SCALING_BIT 10 #define FEATURE_MEM_MVDD_SCALING_BIT 11 - -//Idle + +//Idle #define FEATURE_DS_GFXCLK_BIT 12 #define FEATURE_DS_SOCCLK_BIT 13 #define FEATURE_DS_FCLK_BIT 14 #define FEATURE_DS_LCLK_BIT 15 #define FEATURE_DS_DCEFCLK_BIT 16 #define FEATURE_DS_UCLK_BIT 17 -#define FEATURE_GFX_ULV_BIT 18 -#define FEATURE_FW_DSTATE_BIT 19 +#define FEATURE_GFX_ULV_BIT 18 +#define FEATURE_FW_DSTATE_BIT 19 #define FEATURE_GFXOFF_BIT 20 #define FEATURE_BACO_BIT 21 -#define FEATURE_MM_DPM_PG_BIT 22 +#define FEATURE_MM_DPM_PG_BIT 22 #define FEATURE_SPARE_23_BIT 23 -//Throttler/Response +//Throttler/Response #define FEATURE_PPT_BIT 24 #define FEATURE_TDC_BIT 25 #define FEATURE_APCC_PLUS_BIT 26 #define FEATURE_GTHR_BIT 27 #define FEATURE_ACDC_BIT 28 #define FEATURE_VR0HOT_BIT 29 -#define FEATURE_VR1HOT_BIT 30 +#define FEATURE_VR1HOT_BIT 30 #define FEATURE_FW_CTF_BIT 31 #define FEATURE_FAN_CONTROL_BIT 32 #define FEATURE_THERMAL_BIT 33 #define FEATURE_GFX_DCS_BIT 34 -//VF +//VF #define FEATURE_RM_BIT 35 #define FEATURE_LED_DISPLAY_BIT 36 -//Other +//Other #define FEATURE_GFX_SS_BIT 37 #define FEATURE_OUT_OF_BAND_MONITOR_BIT 38 #define FEATURE_TEMP_DEPENDENT_VMIN_BIT 39 -#define FEATURE_MMHUB_PG_BIT 40 +#define FEATURE_MMHUB_PG_BIT 40 #define FEATURE_ATHUB_PG_BIT 41 #define FEATURE_APCC_DFLL_BIT 42 #define FEATURE_DF_SUPERV_BIT 43 @@ -225,7 +225,7 @@ typedef enum { #define FW_DSTATE_MP1_WHISPER_MODE_BIT 6 #define FW_DSTATE_SOC_LIV_MIN_BIT 7 #define FW_DSTATE_SOC_PLL_PWRDN_BIT 8 -#define FW_DSTATE_MEM_PLL_PWRDN_BIT 9 +#define FW_DSTATE_MEM_PLL_PWRDN_BIT 9 #define FW_DSTATE_OPTIMIZE_MALL_REFRESH_BIT 10 #define FW_DSTATE_MEM_PSI_BIT 11 #define FW_DSTATE_HSR_NON_STROBE_BIT 12 @@ -234,8 +234,8 @@ typedef enum { #define FW_DSTATE_SOC_ULV_MASK (1 << FW_DSTATE_SOC_ULV_BIT ) #define FW_DSTATE_G6_HSR_MASK (1 << FW_DSTATE_G6_HSR_BIT ) #define FW_DSTATE_G6_PHY_VDDCI_OFF_MASK (1 << FW_DSTATE_G6_PHY_VDDCI_OFF_BIT ) -#define FW_DSTATE_MP1_DS_MASK (1 << FW_DSTATE_MP1_DS_BIT ) -#define FW_DSTATE_MP0_DS_MASK (1 << FW_DSTATE_MP0_DS_BIT ) +#define FW_DSTATE_MP1_DS_MASK (1 << FW_DSTATE_MP1_DS_BIT ) +#define FW_DSTATE_MP0_DS_MASK (1 << FW_DSTATE_MP0_DS_BIT ) #define FW_DSTATE_SMN_DS_MASK (1 << FW_DSTATE_SMN_DS_BIT ) #define FW_DSTATE_MP1_WHISPER_MODE_MASK (1 << FW_DSTATE_MP1_WHISPER_MODE_BIT ) #define FW_DSTATE_SOC_LIV_MIN_MASK (1 << FW_DSTATE_SOC_LIV_MIN_BIT ) @@ -312,10 +312,10 @@ typedef enum { I2C_CONTROLLER_NAME_VR_VDDCI, I2C_CONTROLLER_NAME_VR_MVDD, I2C_CONTROLLER_NAME_LIQUID0, - I2C_CONTROLLER_NAME_LIQUID1, + I2C_CONTROLLER_NAME_LIQUID1, I2C_CONTROLLER_NAME_PLX, I2C_CONTROLLER_NAME_OTHER, - I2C_CONTROLLER_NAME_COUNT, + I2C_CONTROLLER_NAME_COUNT, } I2cControllerName_e; typedef enum { @@ -325,10 +325,10 @@ typedef enum { I2C_CONTROLLER_THROTTLER_VR_VDDCI, I2C_CONTROLLER_THROTTLER_VR_MVDD, I2C_CONTROLLER_THROTTLER_LIQUID0, - I2C_CONTROLLER_THROTTLER_LIQUID1, + I2C_CONTROLLER_THROTTLER_LIQUID1, I2C_CONTROLLER_THROTTLER_PLX, I2C_CONTROLLER_THROTTLER_INA3221, - I2C_CONTROLLER_THROTTLER_COUNT, + I2C_CONTROLLER_THROTTLER_COUNT, } I2cControllerThrottler_e; typedef enum { @@ -336,24 +336,24 @@ typedef enum { I2C_CONTROLLER_PROTOCOL_VR_IR35217, I2C_CONTROLLER_PROTOCOL_TMP_TMP102A, I2C_CONTROLLER_PROTOCOL_INA3221, - I2C_CONTROLLER_PROTOCOL_COUNT, + I2C_CONTROLLER_PROTOCOL_COUNT, } I2cControllerProtocol_e; typedef struct { uint8_t Enabled; uint8_t Speed; - uint8_t SlaveAddress; + uint8_t SlaveAddress; uint8_t ControllerPort; uint8_t ControllerName; uint8_t ThermalThrotter; uint8_t I2cProtocol; - uint8_t PaddingConfig; + uint8_t PaddingConfig; } I2cControllerConfig_t; typedef enum { - I2C_PORT_SVD_SCL = 0, - I2C_PORT_GPIO, -} I2cPort_e; + I2C_PORT_SVD_SCL = 0, + I2C_PORT_GPIO, +} I2cPort_e; typedef enum { I2C_SPEED_FAST_50K = 0, //50 Kbits/s @@ -361,14 +361,14 @@ typedef enum { I2C_SPEED_FAST_400K, //400 Kbits/s I2C_SPEED_FAST_PLUS_1M, //1 Mbits/s (in fast mode) I2C_SPEED_HIGH_1M, //1 Mbits/s (in high speed mode) - I2C_SPEED_HIGH_2M, //2.3 Mbits/s - I2C_SPEED_COUNT, + I2C_SPEED_HIGH_2M, //2.3 Mbits/s + I2C_SPEED_COUNT, } I2cSpeed_e; typedef enum { I2C_CMD_READ = 0, I2C_CMD_WRITE, - I2C_CMD_COUNT, + I2C_CMD_COUNT, } I2cCmdType_e; typedef enum { @@ -426,36 +426,36 @@ typedef enum { PG_POWER_UP, } PowerGatingSettings_e; -typedef struct { +typedef struct { uint32_t a; // store in IEEE float format in this variable uint32_t b; // store in IEEE float format in this variable uint32_t c; // store in IEEE float format in this variable } QuadraticInt_t; -typedef struct { +typedef struct { uint32_t a; // store in fixed point, [31:20] signed integer, [19:0] fractional bits uint32_t b; // store in fixed point, [31:20] signed integer, [19:0] fractional bits uint32_t c; // store in fixed point, [31:20] signed integer, [19:0] fractional bits } QuadraticFixedPoint_t; -typedef struct { +typedef struct { uint32_t m; // store in IEEE float format in this variable uint32_t b; // store in IEEE float format in this variable } LinearInt_t; -typedef struct { +typedef struct { uint32_t a; // store in IEEE float format in this variable uint32_t b; // store in IEEE float format in this variable uint32_t c; // store in IEEE float format in this variable } DroopInt_t; -//Piecewise linear droop model, Sienna_Cichlid currently used only for GFX DFLL +//Piecewise linear droop model, Sienna_Cichlid currently used only for GFX DFLL #define NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS 5 typedef enum { PIECEWISE_LINEAR_FUSED_MODEL = 0, PIECEWISE_LINEAR_PP_MODEL, QUADRATIC_PP_MODEL, - PERPART_PIECEWISE_LINEAR_PP_MODEL, + PERPART_PIECEWISE_LINEAR_PP_MODEL, } DfllDroopModelSelect_e; typedef struct { @@ -464,17 +464,17 @@ typedef struct { }PiecewiseLinearDroopInt_t; typedef enum { - GFXCLK_SOURCE_PLL = 0, - GFXCLK_SOURCE_DFLL, - GFXCLK_SOURCE_COUNT, -} GFXCLK_SOURCE_e; + GFXCLK_SOURCE_PLL = 0, + GFXCLK_SOURCE_DFLL, + GFXCLK_SOURCE_COUNT, +} GFXCLK_SOURCE_e; -//Only Clks that have DPM descriptors are listed here +//Only Clks that have DPM descriptors are listed here typedef enum { PPCLK_GFXCLK = 0, PPCLK_SOCCLK, PPCLK_UCLK, - PPCLK_FCLK, + PPCLK_FCLK, PPCLK_DCLK_0, PPCLK_VCLK_0, PPCLK_DCLK_1, @@ -552,18 +552,18 @@ typedef struct { uint8_t VoltageMode; // 0 - AVFS only, 1- min(AVFS,SS), 2-SS only uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM uint8_t NumDiscreteLevels; // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used - uint8_t Padding; + uint8_t Padding; LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz) QuadraticInt_t SsCurve; // Slow-slow curve (GHz->V) uint16_t SsFmin; // Fmin for SS curve. If SS curve is selected, will use V@SSFmin for F <= Fmin - uint16_t Padding16; + uint16_t Padding16; } DpmDescriptor_t; typedef enum { PPT_THROTTLER_PPT0, PPT_THROTTLER_PPT1, PPT_THROTTLER_PPT2, - PPT_THROTTLER_PPT3, + PPT_THROTTLER_PPT3, PPT_THROTTLER_COUNT } PPT_THROTTLER_e; @@ -574,9 +574,9 @@ typedef enum { TEMP_VR_GFX, TEMP_VR_MEM0, TEMP_VR_MEM1, - TEMP_VR_SOC, + TEMP_VR_SOC, TEMP_LIQUID0, - TEMP_LIQUID1, + TEMP_LIQUID1, TEMP_PLX, TEMP_COUNT, } TEMP_e; @@ -592,7 +592,7 @@ typedef enum { CUSTOMER_VARIANT_FALCON, CUSTOMER_VARIANT_COUNT, } CUSTOMER_VARIANT_e; - + // Used for 2-step UCLK DPM change workaround typedef struct { uint16_t Fmin; @@ -618,12 +618,12 @@ typedef struct { uint16_t TdcLimitTau[TDC_THROTTLER_COUNT]; // Time constant of LPF in ms uint16_t TemperatureLimit[TEMP_COUNT]; // Celcius - + uint32_t FitLimit; // Failures in time (failures per million parts over the defined lifetime) // SECTION: Power Configuration uint8_t TotalPowerConfig; //0-TDP, 1-TGP, 2-TCP Estimated, 3-TCP Measured. Use defines from PwrConfig_e - uint8_t TotalPowerPadding[3]; + uint8_t TotalPowerPadding[3]; // SECTION: APCC Settings uint32_t ApccPlusResidencyLimit; @@ -639,14 +639,14 @@ typedef struct { // SECTION: Throttler settings uint32_t ThrottlerControlMask; // See Throtter masks defines - // SECTION: FW DSTATE Settings + // SECTION: FW DSTATE Settings uint32_t FwDStateMask; // See FW DState masks defines // SECTION: ULV Settings uint16_t UlvVoltageOffsetSoc; // In mV(Q2) uint16_t UlvVoltageOffsetGfx; // In mV(Q2) - uint16_t MinVoltageUlvGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX in ULV mode + uint16_t MinVoltageUlvGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX in ULV mode uint16_t MinVoltageUlvSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC in ULV mode uint16_t SocLIVmin; // In mV(Q2) Long Idle Vmin (deep ULV), for VDD_SOC @@ -671,7 +671,7 @@ typedef struct { uint16_t VDDGFX_Vmin_LoTemp; // mV Q2 uint16_t VDDSOC_Vmin_HiTemp; // mV Q2 uint16_t VDDSOC_Vmin_LoTemp; // mV Q2 - + uint16_t VDDGFX_TVminHystersis; // Celcius uint16_t VDDSOC_TVminHystersis; // Celcius @@ -694,9 +694,9 @@ typedef struct { DroopInt_t PerPartDroopModelGfxDfll[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //GHz ->Vstore in IEEE float format uint32_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz - + uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:Div-1/8 - + // Used for MALL performance boost uint16_t FclkBoostFreq; // In Mhz uint16_t FclkParamPadding; @@ -708,32 +708,32 @@ typedef struct { uint16_t MemMvddVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) // GFXCLK DPM uint16_t GfxclkFgfxoffEntry; // in Mhz - uint16_t GfxclkFinit; // in Mhz - uint16_t GfxclkFidle; // in MHz + uint16_t GfxclkFinit; // in Mhz + uint16_t GfxclkFidle; // in MHz uint8_t GfxclkSource; // 0 = PLL, 1 = DFLL uint8_t GfxclkPadding; - // GFX GPO + // GFX GPO uint8_t GfxGpoSubFeatureMask; // bit 0 = PACE, bit 1 = DEM uint8_t GfxGpoEnabledWorkPolicyMask; //Any policy that GPO can be enabled uint8_t GfxGpoDisabledWorkPolicyMask; //Any policy that GPO can be disabled uint8_t GfxGpoPadding[1]; uint32_t GfxGpoVotingAllow; //For indicating which feature changes should result in a GPO table recalculation - uint32_t GfxGpoPadding32[4]; + uint32_t GfxGpoPadding32[4]; uint16_t GfxDcsFopt; // Optimal GFXCLK for DCS in Mhz uint16_t GfxDcsFclkFopt; // Optimal FCLK for DCS in Mhz uint16_t GfxDcsUclkFopt; // Optimal UCLK for DCS in Mhz - - uint16_t DcsGfxOffVoltage; //Voltage in mV(Q2) applied to VDDGFX when entering DCS GFXOFF phase + + uint16_t DcsGfxOffVoltage; //Voltage in mV(Q2) applied to VDDGFX when entering DCS GFXOFF phase uint16_t DcsMinGfxOffTime; //Minimum amount of time PMFW shuts GFX OFF as part of GFX DCS phase uint16_t DcsMaxGfxOffTime; //Maximum amount of time PMFW can shut GFX OFF as part of GFX DCS phase at a stretch. uint32_t DcsMinCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS. - uint16_t DcsExitHysteresis; //The min amount of time power credit accumulator should have a value > 0 before SMU exits the DCS throttling phase. + uint16_t DcsExitHysteresis; //The min amount of time power credit accumulator should have a value > 0 before SMU exits the DCS throttling phase. uint16_t DcsTimeout; //This is the amount of time SMU FW waits for RLC to put GFX into GFXOFF before reverting to the fallback mechanism of throttling GFXCLK to Fmin. uint32_t DcsParamPadding[5]; @@ -743,9 +743,9 @@ typedef struct { // UCLK section uint8_t LowestUclkReservedForUlv; // Set this to 1 if UCLK DPM0 is reserved for ULV-mode only uint8_t PaddingMem[3]; - + uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 4 DPM states, 0-P0, 1-P1, 2-P2, 3-P3. - + // Used for 2-Step UCLK change workaround UclkDpmChangeRange_t UclkDpmSrcFreqRange; // In Mhz UclkDpmChangeRange_t UclkDpmTargFreqRange; // In Mhz @@ -755,8 +755,8 @@ typedef struct { // Link DPM Settings uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 - uint16_t LclkFreq[NUM_LINK_LEVELS]; - + uint16_t LclkFreq[NUM_LINK_LEVELS]; + // SECTION: Fan Control uint16_t FanStopTemp; //Celcius uint16_t FanStartTemp; //Celcius @@ -767,36 +767,36 @@ typedef struct { uint16_t FanAcousticLimitRpm; uint16_t FanThrottlingRpm; uint16_t FanMaximumRpm; - uint16_t MGpuFanBoostLimitRpm; + uint16_t MGpuFanBoostLimitRpm; uint16_t FanTargetTemperature; uint16_t FanTargetGfxclk; uint16_t FanPadding16; uint8_t FanTempInputSelect; uint8_t FanPadding; - uint8_t FanZeroRpmEnable; + uint8_t FanZeroRpmEnable; uint8_t FanTachEdgePerRev; - + // The following are AFC override parameters. Leave at 0 to use FW defaults. int16_t FuzzyFan_ErrorSetDelta; int16_t FuzzyFan_ErrorRateSetDelta; int16_t FuzzyFan_PwmSetDelta; uint16_t FuzzyFan_Reserved; - // SECTION: AVFS + // SECTION: AVFS // Overrides uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT]; - uint8_t dBtcGbGfxDfllModelSelect; //0 -> fused piece-wise model, 1 -> piece-wise linear(PPTable), 2 -> quadratic model(PPTable) + uint8_t dBtcGbGfxDfllModelSelect; //0 -> fused piece-wise model, 1 -> piece-wise linear(PPTable), 2 -> quadratic model(PPTable) uint8_t Padding8_Avfs; - QuadraticInt_t qAvfsGb[AVFS_VOLTAGE_COUNT]; // GHz->V Override of fused curve + QuadraticInt_t qAvfsGb[AVFS_VOLTAGE_COUNT]; // GHz->V Override of fused curve DroopInt_t dBtcGbGfxPll; // GHz->V BtcGb DroopInt_t dBtcGbGfxDfll; // GHz->V BtcGb DroopInt_t dBtcGbSoc; // GHz->V BtcGb - LinearInt_t qAgingGb[AVFS_VOLTAGE_COUNT]; // GHz->V + LinearInt_t qAgingGb[AVFS_VOLTAGE_COUNT]; // GHz->V PiecewiseLinearDroopInt_t PiecewiseLinearDroopIntGfxDfll; //GHz ->Vstore in IEEE float format - QuadraticInt_t qStaticVoltageOffset[AVFS_VOLTAGE_COUNT]; // GHz->V + QuadraticInt_t qStaticVoltageOffset[AVFS_VOLTAGE_COUNT]; // GHz->V uint16_t DcTol[AVFS_VOLTAGE_COUNT]; // mV Q2 @@ -807,17 +807,17 @@ typedef struct { uint16_t DcBtcMax[AVFS_VOLTAGE_COUNT]; // mV Q2 uint16_t DcBtcGb[AVFS_VOLTAGE_COUNT]; // mV Q2 - + // SECTION: XGMI uint8_t XgmiDpmPstates[NUM_XGMI_LEVELS]; // 2 DPM states, high and low. 0-P0, 1-P1, 2-P2, 3-P3. uint8_t XgmiDpmSpare[2]; // SECTION: Advanced Options uint32_t DebugOverrides; - QuadraticInt_t ReservedEquation0; - QuadraticInt_t ReservedEquation1; - QuadraticInt_t ReservedEquation2; - QuadraticInt_t ReservedEquation3; + QuadraticInt_t ReservedEquation0; + QuadraticInt_t ReservedEquation1; + QuadraticInt_t ReservedEquation2; + QuadraticInt_t ReservedEquation3; // SECTION: Sku Reserved uint8_t CustomerVariant; @@ -825,17 +825,17 @@ typedef struct { //VC BTC parameters are only applicable to VDD_GFX domain uint8_t VcBtcEnabled; uint16_t VcBtcVminT0; // T0_VMIN - uint16_t VcBtcFixedVminAgingOffset; // FIXED_VMIN_AGING_OFFSET - uint16_t VcBtcVmin2PsmDegrationGb; // VMIN_TO_PSM_DEGRADATION_GB + uint16_t VcBtcFixedVminAgingOffset; // FIXED_VMIN_AGING_OFFSET + uint16_t VcBtcVmin2PsmDegrationGb; // VMIN_TO_PSM_DEGRADATION_GB uint32_t VcBtcPsmA; // A_PSM uint32_t VcBtcPsmB; // B_PSM uint32_t VcBtcVminA; // A_VMIN - uint32_t VcBtcVminB; // B_VMIN - + uint32_t VcBtcVminB; // B_VMIN + //GPIO Board feature uint16_t LedGpio; //GeneriA GPIO flag used to control the radeon LEDs - uint16_t GfxPowerStagesGpio; //Genlk_vsync GPIO flag used to control gfx power stages - + uint16_t GfxPowerStagesGpio; //Genlk_vsync GPIO flag used to control gfx power stages + uint32_t SkuReserved[8]; @@ -845,7 +845,7 @@ typedef struct { uint32_t GamingClk[6]; // SECTION: I2C Control - I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS]; + I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS]; uint8_t GpioScl; // GPIO Number for SCL Line, used only for CKSVII2C1 uint8_t GpioSda; // GPIO Number for SDA Line, used only for CKSVII2C1 @@ -875,21 +875,21 @@ typedef struct { uint16_t Mem0MaxCurrent; // in Amps int8_t Mem0Offset; // in Amps uint8_t Padding_TelemetryMem0; - + uint16_t Mem1MaxCurrent; // in Amps int8_t Mem1Offset; // in Amps uint8_t Padding_TelemetryMem1; uint32_t MvddRatio; // This is used for MVDD Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16) - + // SECTION: GPIO Settings uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event - uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event - uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event + uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event + uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event uint8_t GthrGpio; // GPIO pin configured for GTHR Event uint8_t GthrPolarity; // replace GPIO polarity for GTHR @@ -904,7 +904,7 @@ typedef struct { uint8_t LedSpare1[2]; // SECTION: Clock Spread Spectrum - + // GFXCLK PLL Spread Spectrum uint8_t PllGfxclkSpreadEnabled; // on or off uint8_t PllGfxclkSpreadPercent; // Q4.4 @@ -914,7 +914,7 @@ typedef struct { uint8_t DfllGfxclkSpreadEnabled; // on or off uint8_t DfllGfxclkSpreadPercent; // Q4.4 uint16_t DfllGfxclkSpreadFreq; // kHz - + // UCLK Spread Spectrum uint16_t UclkSpreadPadding; uint16_t UclkSpreadFreq; // kHz @@ -923,17 +923,17 @@ typedef struct { uint8_t FclkSpreadEnabled; // on or off uint8_t FclkSpreadPercent; // Q4.4 uint16_t FclkSpreadFreq; // kHz - + // Section: Memory Config - uint32_t MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask. - + uint32_t MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask. + uint8_t DramBitWidth; // For DRAM use only. See Dram Bit width type defines uint8_t PaddingMem1[3]; // Section: Total Board Power uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power - uint16_t BoardPowerPadding; - + uint16_t BoardPowerPadding; + // SECTION: XGMI Training uint8_t XgmiLinkSpeed [NUM_XGMI_PSTATE_LEVELS]; uint8_t XgmiLinkWidth [NUM_XGMI_PSTATE_LEVELS]; @@ -947,7 +947,7 @@ typedef struct { uint8_t PaddingUmcFlags[2]; // UCLK Spread Spectrum - uint8_t UclkSpreadPercent[16]; + uint8_t UclkSpreadPercent[16]; // SECTION: Board Reserved uint32_t BoardReserved[11]; @@ -983,7 +983,7 @@ typedef struct { // SECTION: Power Configuration uint8_t TotalPowerConfig; //0-TDP, 1-TGP, 2-TCP Estimated, 3-TCP Measured. Use defines from PwrConfig_e - uint8_t TotalPowerPadding[3]; + uint8_t TotalPowerPadding[3]; // SECTION: APCC Settings uint32_t ApccPlusResidencyLimit; @@ -999,14 +999,14 @@ typedef struct { // SECTION: Throttler settings uint32_t ThrottlerControlMask; // See Throtter masks defines - // SECTION: FW DSTATE Settings + // SECTION: FW DSTATE Settings uint32_t FwDStateMask; // See FW DState masks defines // SECTION: ULV Settings uint16_t UlvVoltageOffsetSoc; // In mV(Q2) uint16_t UlvVoltageOffsetGfx; // In mV(Q2) - uint16_t MinVoltageUlvGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX in ULV mode + uint16_t MinVoltageUlvGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX in ULV mode uint16_t MinVoltageUlvSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC in ULV mode uint16_t SocLIVmin; @@ -1068,12 +1068,12 @@ typedef struct { uint16_t MemMvddVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2) // GFXCLK DPM uint16_t GfxclkFgfxoffEntry; // in Mhz - uint16_t GfxclkFinit; // in Mhz - uint16_t GfxclkFidle; // in MHz + uint16_t GfxclkFinit; // in Mhz + uint16_t GfxclkFidle; // in MHz uint8_t GfxclkSource; // 0 = PLL, 1 = DFLL uint8_t GfxclkPadding; - // GFX GPO + // GFX GPO uint8_t GfxGpoSubFeatureMask; // bit 0 = PACE, bit 1 = DEM uint8_t GfxGpoEnabledWorkPolicyMask; //Any policy that GPO can be enabled uint8_t GfxGpoDisabledWorkPolicyMask; //Any policy that GPO can be disabled @@ -1086,14 +1086,14 @@ typedef struct { uint16_t GfxDcsFclkFopt; // Optimal FCLK for DCS in Mhz uint16_t GfxDcsUclkFopt; // Optimal UCLK for DCS in Mhz - uint16_t DcsGfxOffVoltage; //Voltage in mV(Q2) applied to VDDGFX when entering DCS GFXOFF phase + uint16_t DcsGfxOffVoltage; //Voltage in mV(Q2) applied to VDDGFX when entering DCS GFXOFF phase uint16_t DcsMinGfxOffTime; //Minimum amount of time PMFW shuts GFX OFF as part of GFX DCS phase uint16_t DcsMaxGfxOffTime; //Maximum amount of time PMFW can shut GFX OFF as part of GFX DCS phase at a stretch. uint32_t DcsMinCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS. - uint16_t DcsExitHysteresis; //The min amount of time power credit accumulator should have a value > 0 before SMU exits the DCS throttling phase. + uint16_t DcsExitHysteresis; //The min amount of time power credit accumulator should have a value > 0 before SMU exits the DCS throttling phase. uint16_t DcsTimeout; //This is the amount of time SMU FW waits for RLC to put GFX into GFXOFF before reverting to the fallback mechanism of throttling GFXCLK to Fmin. uint32_t DcsParamPadding[5]; @@ -1115,7 +1115,7 @@ typedef struct { // Link DPM Settings uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 - uint16_t LclkFreq[NUM_LINK_LEVELS]; + uint16_t LclkFreq[NUM_LINK_LEVELS]; // SECTION: Fan Control uint16_t FanStopTemp; //Celcius @@ -1127,13 +1127,13 @@ typedef struct { uint16_t FanAcousticLimitRpm; uint16_t FanThrottlingRpm; uint16_t FanMaximumRpm; - uint16_t MGpuFanBoostLimitRpm; + uint16_t MGpuFanBoostLimitRpm; uint16_t FanTargetTemperature; uint16_t FanTargetGfxclk; uint16_t FanPadding16; uint8_t FanTempInputSelect; uint8_t FanPadding; - uint8_t FanZeroRpmEnable; + uint8_t FanZeroRpmEnable; uint8_t FanTachEdgePerRev; // The following are AFC override parameters. Leave at 0 to use FW defaults. @@ -1142,21 +1142,21 @@ typedef struct { int16_t FuzzyFan_PwmSetDelta; uint16_t FuzzyFan_Reserved; - // SECTION: AVFS + // SECTION: AVFS // Overrides uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT]; - uint8_t dBtcGbGfxDfllModelSelect; //0 -> fused piece-wise model, 1 -> piece-wise linear(PPTable), 2 -> quadratic model(PPTable) + uint8_t dBtcGbGfxDfllModelSelect; //0 -> fused piece-wise model, 1 -> piece-wise linear(PPTable), 2 -> quadratic model(PPTable) uint8_t Padding8_Avfs; - QuadraticInt_t qAvfsGb[AVFS_VOLTAGE_COUNT]; // GHz->V Override of fused curve + QuadraticInt_t qAvfsGb[AVFS_VOLTAGE_COUNT]; // GHz->V Override of fused curve DroopInt_t dBtcGbGfxPll; // GHz->V BtcGb DroopInt_t dBtcGbGfxDfll; // GHz->V BtcGb DroopInt_t dBtcGbSoc; // GHz->V BtcGb - LinearInt_t qAgingGb[AVFS_VOLTAGE_COUNT]; // GHz->V + LinearInt_t qAgingGb[AVFS_VOLTAGE_COUNT]; // GHz->V PiecewiseLinearDroopInt_t PiecewiseLinearDroopIntGfxDfll; //GHz ->Vstore in IEEE float format - QuadraticInt_t qStaticVoltageOffset[AVFS_VOLTAGE_COUNT]; // GHz->V + QuadraticInt_t qStaticVoltageOffset[AVFS_VOLTAGE_COUNT]; // GHz->V uint16_t DcTol[AVFS_VOLTAGE_COUNT]; // mV Q2 @@ -1185,16 +1185,16 @@ typedef struct { //VC BTC parameters are only applicable to VDD_GFX domain uint8_t VcBtcEnabled; uint16_t VcBtcVminT0; // T0_VMIN - uint16_t VcBtcFixedVminAgingOffset; // FIXED_VMIN_AGING_OFFSET - uint16_t VcBtcVmin2PsmDegrationGb; // VMIN_TO_PSM_DEGRADATION_GB + uint16_t VcBtcFixedVminAgingOffset; // FIXED_VMIN_AGING_OFFSET + uint16_t VcBtcVmin2PsmDegrationGb; // VMIN_TO_PSM_DEGRADATION_GB uint32_t VcBtcPsmA; // A_PSM uint32_t VcBtcPsmB; // B_PSM uint32_t VcBtcVminA; // A_VMIN - uint32_t VcBtcVminB; // B_VMIN + uint32_t VcBtcVminB; // B_VMIN //GPIO Board feature uint16_t LedGpio; //GeneriA GPIO flag used to control the radeon LEDs - uint16_t GfxPowerStagesGpio; //Genlk_vsync GPIO flag used to control gfx power stages + uint16_t GfxPowerStagesGpio; //Genlk_vsync GPIO flag used to control gfx power stages uint32_t SkuReserved[63]; @@ -1206,7 +1206,7 @@ typedef struct { uint32_t GamingClk[6]; // SECTION: I2C Control - I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS]; + I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS]; uint8_t GpioScl; // GPIO Number for SCL Line, used only for CKSVII2C1 uint8_t GpioSda; // GPIO Number for SDA Line, used only for CKSVII2C1 @@ -1249,8 +1249,8 @@ typedef struct { uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event - uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event - uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event + uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event + uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event uint8_t GthrGpio; // GPIO pin configured for GTHR Event uint8_t GthrPolarity; // replace GPIO polarity for GTHR @@ -1286,14 +1286,14 @@ typedef struct { uint16_t FclkSpreadFreq; // kHz // Section: Memory Config - uint32_t MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask. + uint32_t MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask. uint8_t DramBitWidth; // For DRAM use only. See Dram Bit width type defines uint8_t PaddingMem1[3]; // Section: Total Board Power uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power - uint16_t BoardPowerPadding; + uint16_t BoardPowerPadding; // SECTION: XGMI Training uint8_t XgmiLinkSpeed [NUM_XGMI_PSTATE_LEVELS]; @@ -1308,7 +1308,7 @@ typedef struct { uint8_t PaddingUmcFlags[2]; // UCLK Spread Spectrum - uint8_t UclkSpreadPercent[16]; + uint8_t UclkSpreadPercent[16]; // SECTION: Board Reserved uint32_t BoardReserved[11]; @@ -1328,15 +1328,15 @@ typedef struct { uint16_t UclkAverageLpfTau; uint16_t GfxActivityLpfTau; uint16_t UclkActivityLpfTau; - uint16_t SocketPowerLpfTau; + uint16_t SocketPowerLpfTau; uint16_t VcnClkAverageLpfTau; - uint16_t padding16; + uint16_t padding16; } DriverSmuConfig_t; typedef struct { DriverSmuConfig_t DriverSmuConfig; - uint32_t Spare[7]; + uint32_t Spare[7]; // Padding - ignore uint32_t MmHubPadding[8]; // SMU internal use } DriverSmuConfigExternal_t; @@ -1345,14 +1345,14 @@ typedef struct { uint16_t GfxclkFmin; // MHz uint16_t GfxclkFmax; // MHz QuadraticInt_t CustomGfxVfCurve; // a: mV/MHz^2, b: mv/MHz, c: mV - uint16_t CustomCurveFmin; // MHz - uint16_t UclkFmin; // MHz + uint16_t CustomCurveFmin; // MHz + uint16_t UclkFmin; // MHz uint16_t UclkFmax; // MHz int16_t OverDrivePct; // % uint16_t FanMaximumRpm; uint16_t FanMinimumPwm; uint16_t FanAcousticLimitRpm; - uint16_t FanTargetTemperature; // Degree Celcius + uint16_t FanTargetTemperature; // Degree Celcius uint8_t FanLinearPwmPoints[NUM_OD_FAN_MAX_POINTS]; uint8_t FanLinearTempPoints[NUM_OD_FAN_MAX_POINTS]; uint16_t MaxOpTemp; // Degree Celcius @@ -1361,13 +1361,13 @@ typedef struct { uint8_t FanZeroRpmStopTemp; uint8_t FanMode; uint8_t Padding[1]; -} OverDriveTable_t; +} OverDriveTable_t; typedef struct { OverDriveTable_t OverDriveTable; - uint32_t Spare[8]; + uint32_t Spare[8]; - uint32_t MmHubPadding[8]; // SMU internal use + uint32_t MmHubPadding[8]; // SMU internal use } OverDriveTableExternal_t; typedef struct { @@ -1380,7 +1380,7 @@ typedef struct { uint16_t AverageUclkFrequencyPreDs ; uint16_t AverageUclkFrequencyPostDs ; - + uint16_t AverageGfxActivity ; uint16_t AverageUclkActivity ; uint8_t CurrSocVoltageOffset ; @@ -1393,14 +1393,14 @@ typedef struct { uint16_t TemperatureMem ; uint16_t TemperatureVrGfx ; uint16_t TemperatureVrMem0 ; - uint16_t TemperatureVrMem1 ; - uint16_t TemperatureVrSoc ; + uint16_t TemperatureVrMem1 ; + uint16_t TemperatureVrSoc ; uint16_t TemperatureLiquid0 ; - uint16_t TemperatureLiquid1 ; + uint16_t TemperatureLiquid1 ; uint16_t TemperaturePlx ; uint16_t Padding16 ; - uint32_t ThrottlerStatus ; - + uint32_t ThrottlerStatus ; + uint8_t LinkDpmLevel; uint8_t CurrFanPwm; uint16_t CurrFanSpeed; @@ -1414,9 +1414,9 @@ typedef struct { //PMFW-4362 uint32_t EnergyAccumulator; uint16_t AverageVclk0Frequency ; - uint16_t AverageDclk0Frequency ; + uint16_t AverageDclk0Frequency ; uint16_t AverageVclk1Frequency ; - uint16_t AverageDclk1Frequency ; + uint16_t AverageDclk1Frequency ; uint16_t VcnActivityPercentage ; //place holder, David N. to provide full sequence uint8_t PcieRate ; uint8_t PcieWidth ; @@ -1614,7 +1614,7 @@ typedef struct { uint32_t Spare[1]; // Padding - ignore - uint32_t MmHubPadding[8]; // SMU internal use + uint32_t MmHubPadding[8]; // SMU internal use } SmuMetricsExternal_t; typedef struct { @@ -1622,7 +1622,7 @@ typedef struct { uint16_t MaxClock; // This is either DCEFCLK or SOCCLK (in MHz) uint16_t MinUclk; uint16_t MaxUclk; - + uint8_t WmSetting; uint8_t Flags; uint8_t Padding[2]; @@ -1658,7 +1658,7 @@ typedef struct { typedef struct { uint16_t avgPsmCount[67]; uint16_t minPsmCount[67]; - float avgPsmVoltage[67]; + float avgPsmVoltage[67]; float minPsmVoltage[67]; } AvfsDebugTable_t; @@ -1673,7 +1673,7 @@ typedef struct { uint8_t Padding; uint8_t AvfsEn[AVFS_VOLTAGE_COUNT]; - + uint8_t OverrideVFT[AVFS_VOLTAGE_COUNT]; uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT]; @@ -1729,7 +1729,7 @@ typedef struct { uint8_t Gfx_IdleHystLimit; uint8_t Gfx_FPS; uint8_t Gfx_MinActiveFreqType; - uint8_t Gfx_BoosterFreqType; + uint8_t Gfx_BoosterFreqType; uint8_t Gfx_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock. uint16_t Gfx_MinActiveFreq; // MHz uint16_t Gfx_BoosterFreq; // MHz @@ -1739,12 +1739,12 @@ typedef struct { uint32_t Gfx_PD_Data_limit_c; // Q16 uint32_t Gfx_PD_Data_error_coeff; // Q16 uint32_t Gfx_PD_Data_error_rate_coeff; // Q16 - + uint8_t Fclk_ActiveHystLimit; uint8_t Fclk_IdleHystLimit; uint8_t Fclk_FPS; uint8_t Fclk_MinActiveFreqType; - uint8_t Fclk_BoosterFreqType; + uint8_t Fclk_BoosterFreqType; uint8_t Fclk_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock. uint16_t Fclk_MinActiveFreq; // MHz uint16_t Fclk_BoosterFreq; // MHz @@ -1754,7 +1754,7 @@ typedef struct { uint32_t Fclk_PD_Data_limit_c; // Q16 uint32_t Fclk_PD_Data_error_coeff; // Q16 uint32_t Fclk_PD_Data_error_rate_coeff; // Q16 - + uint8_t Mem_ActiveHystLimit; uint8_t Mem_IdleHystLimit; uint8_t Mem_FPS; @@ -1780,19 +1780,19 @@ typedef struct { typedef struct { DpmActivityMonitorCoeffInt_t DpmActivityMonitorCoeffInt; - uint32_t MmHubPadding[8]; // SMU internal use + uint32_t MmHubPadding[8]; // SMU internal use } DpmActivityMonitorCoeffIntExternal_t; // Workload bits -#define WORKLOAD_PPLIB_DEFAULT_BIT 0 -#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1 -#define WORKLOAD_PPLIB_POWER_SAVING_BIT 2 -#define WORKLOAD_PPLIB_VIDEO_BIT 3 -#define WORKLOAD_PPLIB_VR_BIT 4 -#define WORKLOAD_PPLIB_COMPUTE_BIT 5 -#define WORKLOAD_PPLIB_CUSTOM_BIT 6 -#define WORKLOAD_PPLIB_W3D_BIT 7 -#define WORKLOAD_PPLIB_COUNT 8 +#define WORKLOAD_PPLIB_DEFAULT_BIT 0 +#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1 +#define WORKLOAD_PPLIB_POWER_SAVING_BIT 2 +#define WORKLOAD_PPLIB_VIDEO_BIT 3 +#define WORKLOAD_PPLIB_VR_BIT 4 +#define WORKLOAD_PPLIB_COMPUTE_BIT 5 +#define WORKLOAD_PPLIB_CUSTOM_BIT 6 +#define WORKLOAD_PPLIB_W3D_BIT 7 +#define WORKLOAD_PPLIB_COUNT 8 // These defines are used with the following messages: @@ -1824,8 +1824,8 @@ typedef struct { typedef struct { RlcPaceFlopsPerByteOverride_t RlcPaceFlopsPerByteOverride; - - uint32_t MmHubPadding[8]; // SMU internal use + + uint32_t MmHubPadding[8]; // SMU internal use } RlcPaceFlopsPerByteOverrideExternal_t; // These defines are used with the SMC_MSG_SetUclkFastSwitch message. diff --git a/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu12_driver_if.h b/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu12_driver_if.h index e9315eb5b..59bbc68b0 100644 --- a/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu12_driver_if.h +++ b/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu12_driver_if.h @@ -25,7 +25,7 @@ #define SMU12_DRIVER_IF_H // *** IMPORTANT *** -// SMU TEAM: Always increment the interface version if +// SMU TEAM: Always increment the interface version if // any structure is changed in this file #define SMU12_DRIVER_IF_VERSION 14 diff --git a/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_0_7_ppsmc.h b/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_0_7_ppsmc.h index 82cf9e563..d9179106e 100644 --- a/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_0_7_ppsmc.h +++ b/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_0_7_ppsmc.h @@ -95,7 +95,7 @@ //Resets #define PPSMC_MSG_PrepareMp1ForUnload 0x2E -//DramLog Set DramLog SetDramSize +//DramLog Set DramLog SetDramSize #define PPSMC_MSG_DramLogSetDramSize 0x2F #define PPSMC_MSG_Mode1Reset 0x30 diff --git a/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_0_ppsmc.h b/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_0_ppsmc.h index 26181b679..5aeb0ac13 100644 --- a/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_0_ppsmc.h +++ b/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_0_ppsmc.h @@ -66,14 +66,14 @@ #define PPSMC_MSG_SetSoftMinByFreq 0x1A #define PPSMC_MSG_SetSoftMaxByFreq 0x1B #define PPSMC_MSG_SetHardMinByFreq 0x1C -#define PPSMC_MSG_SetHardMaxByFreq 0x1D +#define PPSMC_MSG_SetHardMaxByFreq 0x1D #define PPSMC_MSG_GetMinDpmFreq 0x1E #define PPSMC_MSG_GetMaxDpmFreq 0x1F #define PPSMC_MSG_GetDpmFreqByIndex 0x20 #define PPSMC_MSG_OverridePcieParameters 0x21 #define PPSMC_MSG_SetMinDeepSleepDcefclk 0x22 -#define PPSMC_MSG_SetWorkloadMask 0x24 +#define PPSMC_MSG_SetWorkloadMask 0x24 #define PPSMC_MSG_SetUclkFastSwitch 0x25 #define PPSMC_MSG_GetVoltageByDpm 0x26 #define PPSMC_MSG_SetVideoFps 0x27 @@ -83,7 +83,7 @@ #define PPSMC_MSG_AllowGfxOff 0x29 #define PPSMC_MSG_DisallowGfxOff 0x2A #define PPSMC_MSG_PowerUpVcn 0x2B -#define PPSMC_MSG_PowerDownVcn 0x2C +#define PPSMC_MSG_PowerDownVcn 0x2C #define PPSMC_MSG_PowerUpJpeg 0x2D #define PPSMC_MSG_PowerDownJpeg 0x2E //reserve 0x29 to 0x30 for PG harvesting TBD @@ -112,7 +112,7 @@ #define PPSMC_MSG_ConfigureGfxDidt 0x3F #define PPSMC_MSG_NumOfDisplays 0x40 -#define PPSMC_MSG_SetMemoryChannelConfig 0x41 +#define PPSMC_MSG_SetMemoryChannelConfig 0x41 #define PPSMC_MSG_SetGeminiMode 0x42 #define PPSMC_MSG_SetGeminiApertureHigh 0x43 #define PPSMC_MSG_SetGeminiApertureLow 0x44 diff --git a/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h b/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h index c5e26d619..8ec588248 100644 --- a/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h +++ b/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h @@ -30,7 +30,7 @@ #define ENABLE_DEBUG_FEATURES -// Firmware features +// Firmware features // Feature Control Defines #define FEATURE_CCLK_DPM_BIT 0 #define FEATURE_FAN_CONTROLLER_BIT 1 @@ -92,7 +92,7 @@ #define FEATURE_ZSTATES_ECO_BIT 57 #define FEATURE_CC6_BIT 58 #define FEATURE_DS_UMCCLK_BIT 59 -#define FEATURE_DS_HSPCLK_BIT 60 +#define FEATURE_DS_HSPCLK_BIT 60 #define NUM_FEATURES 61 typedef struct { diff --git a/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_ppsmc.h b/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_ppsmc.h index fc9198846..05ad7d4b2 100644 --- a/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_ppsmc.h +++ b/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_ppsmc.h @@ -24,17 +24,17 @@ #ifndef SMU_13_0_1_PPSMC_H #define SMU_13_0_1_PPSMC_H -/** @def PPS_PMFW_IF_VER +/** @def PPS_PMFW_IF_VER * PPS (PPLib) to PMFW IF version 1.0 */ -#define PPS_PMFW_IF_VER "1.0" ///< Major.Minor +#define PPS_PMFW_IF_VER "1.0" ///< Major.Minor -/** @defgroup ResponseCodes PMFW Response Codes: +/** @defgroup ResponseCodes PMFW Response Codes: * @{ */ -#define PPSMC_Result_OK 0x1 ///< Message Response OK -#define PPSMC_Result_Failed 0xFF ///< Message Response Failed -#define PPSMC_Result_UnknownCmd 0xFE ///< Message Response Unknown Command +#define PPSMC_Result_OK 0x1 ///< Message Response OK +#define PPSMC_Result_Failed 0xFF ///< Message Response Failed +#define PPSMC_Result_UnknownCmd 0xFE ///< Message Response Unknown Command #define PPSMC_Result_CmdRejectedPrereq 0xFD ///< Message Response Command Failed Prerequisite #define PPSMC_Result_CmdRejectedBusy 0xFC ///< Message Response Command Rejected due to PMFW is busy. Sender should retry sending this message /** @}*/ @@ -42,7 +42,7 @@ /** @defgroup definitions Message definitions * @{ */ -#define PPSMC_MSG_TestMessage 0x01 ///< To check if PMFW is alive and responding. Requirement specified by PMFW team +#define PPSMC_MSG_TestMessage 0x01 ///< To check if PMFW is alive and responding. Requirement specified by PMFW team #define PPSMC_MSG_GetSmuVersion 0x02 ///< Get PMFW version #define PPSMC_MSG_GetDriverIfVersion 0x03 ///< Get PMFW_DRIVER_IF version #define PPSMC_MSG_EnableGfxOff 0x04 ///< Enable GFXOFF @@ -55,7 +55,7 @@ #define PPSMC_MSG_ForcePowerDownGfx 0x0B ///< Force power down GFX, i.e. enter GFXOFF #define PPSMC_MSG_PrepareMp1ForUnload 0x0C ///< Prepare PMFW for GFX driver unload #define PPSMC_MSG_SetDriverDramAddrHigh 0x0D ///< Set high 32 bits of DRAM address for Driver table transfer -#define PPSMC_MSG_SetDriverDramAddrLow 0x0E ///< Set low 32 bits of DRAM address for Driver table transfer +#define PPSMC_MSG_SetDriverDramAddrLow 0x0E ///< Set low 32 bits of DRAM address for Driver table transfer #define PPSMC_MSG_TransferTableSmu2Dram 0x0F ///< Transfer driver interface table from PMFW SRAM to DRAM #define PPSMC_MSG_TransferTableDram2Smu 0x10 ///< Transfer driver interface table from DRAM to PMFW SRAM #define PPSMC_MSG_GfxDeviceDriverReset 0x11 ///< Request GFX mode 2 reset @@ -84,14 +84,14 @@ #define PPSMC_MSG_QueryActiveWgp 0x28 ///< Query the anumber of active WGP number #define PPSMC_Message_Count 0x29 ///< Total number of PPS messages /** @}*/ - -/** @enum Mode_Reset_e -* Mode reset type, argument for PPSMC_MSG_GfxDeviceDriverReset -*/ + +/** @enum Mode_Reset_e +* Mode reset type, argument for PPSMC_MSG_GfxDeviceDriverReset +*/ typedef enum { MODE1_RESET = 1, ///< Mode reset type 1 MODE2_RESET = 2 ///< Mode reset type 2 -} Mode_Reset_e; +} Mode_Reset_e; /** @}*/ #endif diff --git a/sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0_7_pptable.h b/sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0_7_pptable.h index 1cb399dbc..fbd088483 100644 --- a/sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0_7_pptable.h +++ b/sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0_7_pptable.h @@ -42,23 +42,23 @@ #define SMU_11_0_7_PP_POWERSAVINGCLOCK_VERSION 0x01 // Power Saving Clock Table Version 1.00 enum SMU_11_0_7_ODFEATURE_CAP { - SMU_11_0_7_ODCAP_GFXCLK_LIMITS = 0, - SMU_11_0_7_ODCAP_GFXCLK_CURVE, - SMU_11_0_7_ODCAP_UCLK_LIMITS, - SMU_11_0_7_ODCAP_POWER_LIMIT, - SMU_11_0_7_ODCAP_FAN_ACOUSTIC_LIMIT, - SMU_11_0_7_ODCAP_FAN_SPEED_MIN, - SMU_11_0_7_ODCAP_TEMPERATURE_FAN, - SMU_11_0_7_ODCAP_TEMPERATURE_SYSTEM, - SMU_11_0_7_ODCAP_MEMORY_TIMING_TUNE, - SMU_11_0_7_ODCAP_FAN_ZERO_RPM_CONTROL, - SMU_11_0_7_ODCAP_AUTO_UV_ENGINE, - SMU_11_0_7_ODCAP_AUTO_OC_ENGINE, - SMU_11_0_7_ODCAP_AUTO_OC_MEMORY, + SMU_11_0_7_ODCAP_GFXCLK_LIMITS = 0, + SMU_11_0_7_ODCAP_GFXCLK_CURVE, + SMU_11_0_7_ODCAP_UCLK_LIMITS, + SMU_11_0_7_ODCAP_POWER_LIMIT, + SMU_11_0_7_ODCAP_FAN_ACOUSTIC_LIMIT, + SMU_11_0_7_ODCAP_FAN_SPEED_MIN, + SMU_11_0_7_ODCAP_TEMPERATURE_FAN, + SMU_11_0_7_ODCAP_TEMPERATURE_SYSTEM, + SMU_11_0_7_ODCAP_MEMORY_TIMING_TUNE, + SMU_11_0_7_ODCAP_FAN_ZERO_RPM_CONTROL, + SMU_11_0_7_ODCAP_AUTO_UV_ENGINE, + SMU_11_0_7_ODCAP_AUTO_OC_ENGINE, + SMU_11_0_7_ODCAP_AUTO_OC_MEMORY, SMU_11_0_7_ODCAP_FAN_CURVE, SMU_11_0_ODCAP_AUTO_FAN_ACOUSTIC_LIMIT, - SMU_11_0_7_ODCAP_POWER_MODE, - SMU_11_0_7_ODCAP_COUNT, + SMU_11_0_7_ODCAP_POWER_MODE, + SMU_11_0_7_ODCAP_COUNT, }; enum SMU_11_0_7_ODFEATURE_ID { @@ -178,7 +178,7 @@ struct smu_11_0_7_powerplay_table uint32_t golden_revision; //PPGen use only: PP Table Revision on the Golden Data Base uint16_t format_id; //PPGen use only: PPTable for different ASICs. For sienna_cichlid this should be 0x80 uint32_t platform_caps; //POWERPLAYABLE::ulPlatformCaps - + uint8_t thermal_controller_type; //one of SMU_11_0_7_PP_THERMALCONTROLLER uint16_t small_power_limit1; diff --git a/sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0_pptable.h b/sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0_pptable.h index 0116e3d04..46d5c702a 100644 --- a/sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0_pptable.h +++ b/sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0_pptable.h @@ -145,14 +145,14 @@ struct smu_11_0_powerplay_table uint32_t golden_revision; uint16_t format_id; uint32_t platform_caps; //POWERPLAYABLE::ulPlatformCaps - + uint8_t thermal_controller_type; //one of SMU_11_0_PP_THERMALCONTROLLER uint16_t small_power_limit1; uint16_t small_power_limit2; uint16_t boost_power_limit; - uint16_t od_turbo_power_limit; //Power limit setting for Turbo mode in Performance UI Tuning. - uint16_t od_power_save_power_limit; //Power limit setting for PowerSave/Optimal mode in Performance UI Tuning. + uint16_t od_turbo_power_limit; //Power limit setting for Turbo mode in Performance UI Tuning. + uint16_t od_power_save_power_limit; //Power limit setting for PowerSave/Optimal mode in Performance UI Tuning. uint16_t software_shutdown_temp; uint16_t reserve[6]; //Zero filled field reserved for future use diff --git a/sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c b/sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c index 798f36cfc..668a29eee 100644 --- a/sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c +++ b/sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c @@ -139,7 +139,7 @@ static struct cmn2asic_mapping yellow_carp_table_map[SMU_TABLE_COUNT] = { TAB_MAP_VALID(CUSTOM_DPM), TAB_MAP_VALID(DPMCLOCKS), }; - + static int yellow_carp_init_smc_tables(struct smu_context *smu) { struct smu_table_context *smu_table = &smu->smu_table; diff --git a/sys/dev/pci/drm/include/linux/types.h b/sys/dev/pci/drm/include/linux/types.h index 6b3de73cd..de79e778b 100644 --- a/sys/dev/pci/drm/include/linux/types.h +++ b/sys/dev/pci/drm/include/linux/types.h @@ -30,12 +30,12 @@ typedef uint32_t u32; typedef int64_t s64; typedef uint64_t u64; -typedef uint16_t __le16; -typedef uint16_t __be16; -typedef uint32_t __le32; +typedef uint16_t __le16; +typedef uint16_t __be16; +typedef uint32_t __le32; typedef uint32_t __be32; -typedef uint64_t __le64; -typedef uint64_t __be64; +typedef uint64_t __le64; +typedef uint64_t __be64; typedef bus_addr_t dma_addr_t; typedef paddr_t phys_addr_t; diff --git a/sys/dev/pci/drm/radeon/atombios.h b/sys/dev/pci/drm/radeon/atombios.h index f48283ced..3feffa4dc 100644 --- a/sys/dev/pci/drm/radeon/atombios.h +++ b/sys/dev/pci/drm/radeon/atombios.h @@ -4865,7 +4865,7 @@ ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. sDISPCLK_Voltage: Report Display clock voltage requirement. - + ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Liano/Ontaio projects: ATOM_DEVICE_CRT1_SUPPORT 0x0001 ATOM_DEVICE_CRT2_SUPPORT 0x0010 diff --git a/sys/dev/pci/drm/ttm/ttm_resource.c b/sys/dev/pci/drm/ttm/ttm_resource.c index 802a724f6..a373c5498 100644 --- a/sys/dev/pci/drm/ttm/ttm_resource.c +++ b/sys/dev/pci/drm/ttm/ttm_resource.c @@ -717,7 +717,7 @@ ttm_kmap_iter_linear_io_init(struct ttm_kmap_iter_linear_io *iter_io, &iter_io->dmap.bsh)) { ret = -ENOMEM; goto out_io_free; - } + } iter_io->dmap.size = bus_size; iosys_map_set_vaddr(&iter_io->dmap, bus_space_vaddr(bdev->memt, iter_io->dmap.bsh)); diff --git a/sys/dev/pci/eap.c b/sys/dev/pci/eap.c index dd7e2c258..517c7934d 100644 --- a/sys/dev/pci/eap.c +++ b/sys/dev/pci/eap.c @@ -38,11 +38,11 @@ * ES1371/AC97: Ezra Story */ -/* +/* * Ensoniq ES1370 + AK4531 and ES1371/ES1373 + AC97 * * Documentation links: - * + * * ftp://ftp.alsa-project.org/pub/manuals/ensoniq/ * ftp://ftp.alsa-project.org/pub/manuals/asahi_kasei/4531.pdf */ @@ -387,7 +387,7 @@ eap1371_src_wait(struct eap_softc *sc) { int to; u_int32_t src = 0; - + for (to = 0; to < EAP_READ_TIMEOUT; to++) { src = EREAD4(sc, E1371_SRC); if (!(src & E1371_SRC_RBUSY)) @@ -407,7 +407,7 @@ eap1371_src_write(struct eap_softc *sc, int a, int d) r |= E1371_SRC_RAMWE | E1371_SRC_ADDR(a) | E1371_SRC_DATA(d); EWRITE4(sc, E1371_SRC, r); } - + void eap_attach(struct device *parent, struct device *self, void *aux) { @@ -559,7 +559,7 @@ eap_attach(struct device *parent, struct device *self, void *aux) sc->host_if.reset = eap1371_reset_codec; sc->host_if.flags = eap_flags_codec; sc->flags = AC97_HOST_DONT_READ; - + if (ac97_attach(&sc->host_if) == 0) { /* Interrupt enable */ EWRITE4(sc, EAP_SIC, EAP_P2_INTR_EN | EAP_R1_INTR_EN); @@ -638,7 +638,7 @@ int eap1371_attach_codec(void *sc_, struct ac97_codec_if *codec_if) { struct eap_softc *sc = sc_; - + sc->codec_if = codec_if; return (0); } @@ -723,7 +723,7 @@ eap_intr(void *p) if (EREAD1(sc, EAP_UART_STATUS) & EAP_US_TXINT) { sc->sc_uctrl &= ~EAP_UC_TXINTEN; EWRITE1(sc, EAP_UART_CONTROL, sc->sc_uctrl); - if (sc->sc_ointr) + if (sc->sc_ointr) sc->sc_ointr(sc->sc_arg); } } @@ -792,7 +792,7 @@ void eap_close(void *addr) { struct eap_softc *sc = addr; - + eap_halt_output(sc); eap_halt_input(sc); @@ -1034,7 +1034,7 @@ eap_halt_output(void *addr) { struct eap_softc *sc = addr; u_int32_t icsc; - + DPRINTF(("eap: eap_halt_output\n")); mtx_enter(&audio_lock); icsc = EREAD4(sc, EAP_ICSC); @@ -1051,7 +1051,7 @@ eap_halt_input(void *addr) { struct eap_softc *sc = addr; u_int32_t icsc; - + DPRINTF(("eap: eap_halt_input\n")); mtx_enter(&audio_lock); icsc = EREAD4(sc, EAP_ICSC); diff --git a/sys/dev/pci/eapreg.h b/sys/dev/pci/eapreg.h index dbc46d45b..0b2a620c2 100644 --- a/sys/dev/pci/eapreg.h +++ b/sys/dev/pci/eapreg.h @@ -250,7 +250,7 @@ /* Futzable parms */ #define EAP_MASTER_VOL 0 #define EAP_VOICE_VOL 1 -#define EAP_FM_VOL 2 +#define EAP_FM_VOL 2 #define EAP_VIDEO_VOL 2 /* ES1371 */ #define EAP_CD_VOL 3 #define EAP_LINE_VOL 4 @@ -258,7 +258,7 @@ #define EAP_MIC_VOL 6 #define EAP_RECORD_SOURCE 7 #define EAP_INPUT_SOURCE 8 -#define EAP_MIC_PREAMP 9 +#define EAP_MIC_PREAMP 9 #define EAP_OUTPUT_CLASS 10 #define EAP_RECORD_CLASS 11 #define EAP_INPUT_CLASS 12 diff --git a/sys/dev/pci/ehci_pci.c b/sys/dev/pci/ehci_pci.c index 70ec084a5..f7847f696 100644 --- a/sys/dev/pci/ehci_pci.c +++ b/sys/dev/pci/ehci_pci.c @@ -94,7 +94,7 @@ ehci_pci_match(struct device *parent, void *match, void *aux) PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_USB && PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_EHCI) return (1); - + return (0); } diff --git a/sys/dev/pci/emuxki.c b/sys/dev/pci/emuxki.c index e1d2d7cd2..1230dd8bc 100644 --- a/sys/dev/pci/emuxki.c +++ b/sys/dev/pci/emuxki.c @@ -32,7 +32,7 @@ /* * Driver for Creative Labs SBLive! series and probably PCI512. - * + * * Known bugs: * - inversed stereo at ac97 codec level * (XXX jdolecek - don't see the problem? maybe because auvia(4) has @@ -297,7 +297,7 @@ emuxki_dmamem_alloc(bus_dma_tag_t dmat, size_t size, bus_size_t align, return (NULL); } - if (bus_dmamap_load(dmat, mem->map, mem->kaddr, + if (bus_dmamap_load(dmat, mem->map, mem->kaddr, mem->size, NULL, bus_dma_flags)) { bus_dmamap_destroy(dmat, mem->map); bus_dmamem_unmap(dmat, mem->kaddr, mem->size); @@ -849,7 +849,7 @@ emuxki_init(struct emuxki_softc *sc, int resuming) emuxki_write(sc, 0, EMU_A2_SPDIF_SAMPLERATE, EMU_A2_SPDIF_UNKNOWN); bus_space_write_4(sc->sc_iot, sc->sc_ioh, EMU_A2_PTR, EMU_A2_SRCSEL); - bus_space_write_4(sc->sc_iot, sc->sc_ioh, EMU_A2_DATA, + bus_space_write_4(sc->sc_iot, sc->sc_ioh, EMU_A2_DATA, EMU_A2_SRCSEL_ENABLE_SPDIF | EMU_A2_SRCSEL_ENABLE_SRCMULTI); bus_space_write_4(sc->sc_iot, sc->sc_ioh, EMU_A2_PTR, EMU_A2_SRCMULTI); @@ -1204,7 +1204,7 @@ emuxki_channel_commit_fx(struct emuxki_channel *chan) { struct emuxki_softc *sc = chan->voice->sc; u_int8_t chano = chan->num; - + if (sc->sc_flags & EMUXKI_AUDIGY) { emuxki_write(sc, chano, EMU_A_CHAN_FXRT1, (chan->fxsend.d.dest << 24) | @@ -1228,7 +1228,7 @@ emuxki_channel_commit_fx(struct emuxki_channel *chan) (chan->fxsend.b.dest << 20) | (chan->fxsend.a.dest << 16)); } - + emuxki_write(sc, chano, 0x10000000 | EMU_CHAN_PTRX, (chan->fxsend.a.level << 8) | chan->fxsend.b.level); emuxki_write(sc, chano, EMU_CHAN_DSL, @@ -1474,7 +1474,7 @@ emuxki_voice_new(struct emuxki_softc *sc, u_int8_t use) if (!voice) { if (!(voice = malloc(sizeof(*voice), M_DEVBUF, M_WAITOK))) return (NULL); - } else if (voice->use != use) + } else if (voice->use != use) emuxki_voice_dataloc_destroy(voice); else goto skip_initialize; @@ -1563,7 +1563,7 @@ emuxki_voice_set_stereo(struct emuxki_voice *voice, u_int8_t stereo) fxsend.f.level = fxsend.h.level = 0xc0; emuxki_channel_set_fxsend(voice->dataloc.chan[1], &fxsend); - } /* No else : default is good for mono */ + } /* No else : default is good for mono */ } return (0); } @@ -1623,10 +1623,10 @@ emuxki_voice_set_audioparms(struct emuxki_voice *voice, u_int8_t stereo, (voice->use & EMU_VOICE_USE_PLAY) ? "play" : "record", stereo ? "stereo" : "mono", (b16 + 1) * 8, srate); #endif - + voice->b16 = b16; - /* sample rate must be set after any channel number changes */ + /* sample rate must be set after any channel number changes */ if ((voice->stereo != stereo) || (voice->sample_rate != srate)) { if (voice->stereo != stereo) { if ((error = emuxki_voice_set_stereo(voice, stereo))) @@ -2222,7 +2222,7 @@ emuxki_round_blocksize(void *addr, int blksize) return bufsize; } - + size_t emuxki_round_buffersize(void *addr, int direction, size_t bsize) { diff --git a/sys/dev/pci/emuxkireg.h b/sys/dev/pci/emuxkireg.h index 375b66ac6..3559d24ac 100644 --- a/sys/dev/pci/emuxkireg.h +++ b/sys/dev/pci/emuxkireg.h @@ -33,7 +33,7 @@ #ifndef _DEV_PCI_EMUXKIREG_H_ #define _DEV_PCI_EMUXKIREG_H_ -/* +/* * Register values for Creative EMU10000. The register values have been * taken from GPLed SBLive! header file published by Creative. The comments * have been stripped to avoid GPL pollution in kernel. The Creative version diff --git a/sys/dev/pci/envy.c b/sys/dev/pci/envy.c index b230961c8..987e20961 100644 --- a/sys/dev/pci/envy.c +++ b/sys/dev/pci/envy.c @@ -1394,7 +1394,7 @@ void envy_midi_wait(struct envy_softc *sc) { int i, st; - + for (i = 100;; i--) { st = envy_ccs_read(sc, ENVY_CCS_MIDISTAT0); if (!(st & ENVY_MIDISTAT_OBUSY(sc))) @@ -1904,7 +1904,7 @@ envy_set_params(void *self, int setmode, int usemode, /* only HT model supports rates above 96kHz */ if (!sc->isht && rate > 96000) - rate = 96000; + rate = 96000; for (i = 0; envy_rates[i].rate < rate; i++) { if (envy_rates[i].rate == -1) { @@ -1963,7 +1963,7 @@ envy_pintr(struct envy_softc *sc) int i; if (sc->spurious > 0 || envydebug >= 2) { - printf("%s: spurious = %u, start = %lld.%ld\n", + printf("%s: spurious = %u, start = %lld.%ld\n", DEVNAME(sc), sc->spurious, (long long)sc->start_ts.tv_sec, sc->start_ts.tv_nsec); for (i = 0; i < sc->nintr; i++) { @@ -2492,7 +2492,7 @@ envy_midi_output(void *self, int data) { struct envy_softc *sc = (struct envy_softc *)self; int st; - + st = envy_ccs_read(sc, ENVY_CCS_MIDISTAT0); if (st & ENVY_MIDISTAT_OBUSY(sc)) return 0; diff --git a/sys/dev/pci/esareg.h b/sys/dev/pci/esareg.h index 101a50bea..18a5bb60e 100644 --- a/sys/dev/pci/esareg.h +++ b/sys/dev/pci/esareg.h @@ -28,7 +28,7 @@ /* * ESS Allegro-1 / Maestro3 Audio Driver - * + * * Lots of magic based on the FreeBSD maestro3 driver and * reverse engineering. * Original driver by Don Kim. @@ -423,7 +423,7 @@ #define ESA_KDATA_ADC2_LEFT_SUR_VOL (ESA_KDATA_BASE_ADDR + 0x0045) #define ESA_KDATA_ADC2_RIGHT_SUR_VOL (ESA_KDATA_BASE_ADDR + 0x0046) -#define ESA_KDATA_CD_XFER0 (ESA_KDATA_BASE_ADDR + 0x0047) +#define ESA_KDATA_CD_XFER0 (ESA_KDATA_BASE_ADDR + 0x0047) #define ESA_KDATA_CD_XFER_ENDMARK (ESA_KDATA_BASE_ADDR + 0x0048) #define ESA_KDATA_CD_LEFT_VOLUME (ESA_KDATA_BASE_ADDR + 0x0049) #define ESA_KDATA_CD_RIGHT_VOLUME (ESA_KDATA_BASE_ADDR + 0x004A) diff --git a/sys/dev/pci/esavar.h b/sys/dev/pci/esavar.h index f7e6299d8..14e7204f1 100644 --- a/sys/dev/pci/esavar.h +++ b/sys/dev/pci/esavar.h @@ -28,7 +28,7 @@ /* * ESS Allegro-1 / Maestro3 Audio Driver - * + * * Based on the FreeBSD maestro3 driver * */ @@ -82,7 +82,7 @@ struct esa_channel { /* mode settings */ struct audio_params mode; - + void (*intr)(void *); void *arg; }; diff --git a/sys/dev/pci/eso.c b/sys/dev/pci/eso.c index 27dde7265..a18c426a4 100644 --- a/sys/dev/pci/eso.c +++ b/sys/dev/pci/eso.c @@ -260,7 +260,7 @@ eso_attach(struct device *parent, struct device *self, void *aux) * in the VC BAR to be useless. To work around this, we defer this * part until all autoconfiguration on our parent bus is completed * and then try to map it ourselves in fulfillment of the constraint. - * + * * According to the register map we may write to the low 16 bits * only, but experimenting has shown we're safe. * -kjk @@ -271,7 +271,7 @@ eso_attach(struct device *parent, struct device *self, void *aux) vcbase | ESO_PCI_DDMAC_DE); sc->sc_dmac_configured = 1; sc->sc_dmac_addr = vcbase; - + printf("%s: mapping Audio 1 DMA using VC I/O space at 0x%lx\n", sc->sc_dev.dv_xname, (unsigned long)vcbase); } else { @@ -279,7 +279,7 @@ eso_attach(struct device *parent, struct device *self, void *aux) sc->sc_dev.dv_xname, (unsigned long)vcbase)); config_defer((struct device *)sc, eso_defer); } - + audio_attach_mi(&eso_hw_if, sc, NULL, &sc->sc_dev); aa.type = AUDIODEV_TYPE_OPL; @@ -302,16 +302,16 @@ eso_attach(struct device *parent, struct device *self, void *aux) void eso_setup(struct eso_softc *sc, int verbose, int resuming) { - struct pci_attach_args *pa = &sc->sc_pa; + struct pci_attach_args *pa = &sc->sc_pa; uint8_t a2mode, tmp; - int idx; + int idx; /* Reset the device; bail out upon failure. */ if (eso_reset(sc) != 0) { if (verbose) printf(", can't reset\n"); return; } - + /* Select the DMA/IRQ policy: DDMA, ISA IRQ emulation disabled. */ pci_conf_write(pa->pa_pc, pa->pa_tag, ESO_PCI_S1C, pci_conf_read(pa->pa_pc, pa->pa_tag, ESO_PCI_S1C) & @@ -341,7 +341,7 @@ eso_setup(struct eso_softc *sc, int verbose, int resuming) eso_set_preamp(sc, 1); for (idx = 0; idx < ESO_NGAINDEVS; idx++) { int v; - + switch (idx) { case ESO_MIC_PLAY_VOL: case ESO_LINE_PLAY_VOL: @@ -400,7 +400,7 @@ eso_setup(struct eso_softc *sc, int verbose, int resuming) eso_write_mixreg(sc, ESO_MIXREG_RMVM, eso_read_mixreg(sc, ESO_MIXREG_RMVM) | ESO_MIXREG_RMVM_MUTE); - } else { + } else { eso_write_mixreg(sc, ESO_MIXREG_LMVM, eso_read_mixreg(sc, ESO_MIXREG_LMVM) & ~ESO_MIXREG_LMVM_MUTE); @@ -446,7 +446,7 @@ eso_defer(struct device *self) return; } - + printf("can't map Audio 1 DMA into I/O space\n"); } @@ -476,7 +476,7 @@ eso_write_ctlreg(struct eso_softc *sc, uint8_t reg, uint8_t val) { /* DPRINTF(("ctlreg 0x%02x = 0x%02x\n", reg, val)); */ - + eso_write_cmd(sc, reg); eso_write_cmd(sc, val); } @@ -514,7 +514,7 @@ void eso_write_mixreg(struct eso_softc *sc, uint8_t reg, uint8_t val) { /* DPRINTF(("mixreg 0x%02x = 0x%02x\n", reg, val)); */ - + bus_space_write_1(sc->sc_sb_iot, sc->sc_sb_ioh, ESO_SB_MIXERADDR, reg); bus_space_write_1(sc->sc_sb_iot, sc->sc_sb_ioh, ESO_SB_MIXERDATA, val); } @@ -544,12 +544,12 @@ eso_intr(void *hdl) mtx_leave(&audio_lock); return (0); } - + if (irqctl & ESO_IO_IRQCTL_A1IRQ) { /* Clear interrupt. */ (void)bus_space_read_1(sc->sc_sb_iot, sc->sc_sb_ioh, ESO_SB_RBSR); - + if (sc->sc_rintr) sc->sc_rintr(sc->sc_rarg); else @@ -586,7 +586,7 @@ eso_intr(void *hdl) if ((irqctl & ESO_IO_IRQCTL_MPUIRQ) && sc->sc_mpudev != NULL) mpu_intr(sc->sc_mpudev); #endif - + mtx_leave(&audio_lock); return (1); } @@ -622,7 +622,7 @@ eso_reset(struct eso_softc *sc) delay(1000); } } - + printf("%s: reset timeout\n", sc->sc_dev.dv_xname); return (-1); } @@ -648,7 +648,7 @@ eso_set_params(void *hdl, int setmode, int usemode, int mode, r[2], rd[2], ar[2], clk; uint srg, fltdiv; - for (mode = AUMODE_RECORD; mode != -1; + for (mode = AUMODE_RECORD; mode != -1; mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { if ((setmode & mode) == 0) continue; @@ -699,7 +699,7 @@ eso_set_params(void *hdl, int setmode, int usemode, /* Update to reflect the possibly inexact rate. */ p->sample_rate = r[clk]; - + if (mode == AUMODE_RECORD) { /* Audio 1 */ DPRINTF(("A1 srg 0x%02x fdiv 0x%02x\n", srg, fltdiv)); @@ -729,7 +729,7 @@ eso_halt_output(void *hdl) { struct eso_softc *sc = hdl; int error; - + DPRINTF(("%s: halt_output\n", sc->sc_dev.dv_xname)); /* @@ -752,11 +752,11 @@ eso_halt_output(void *hdl) sc->sc_pintr = NULL; error = msleep_nsec(&sc->sc_pintr, &audio_lock, PWAIT | PNORELOCK, "esoho", MSEC_TO_NSEC(sc->sc_pdrain)); - + /* Shut down DMA completely. */ eso_write_mixreg(sc, ESO_MIXREG_A2C1, 0); bus_space_write_1(sc->sc_iot, sc->sc_ioh, ESO_IO_A2DMAM, 0); - + return (error == EWOULDBLOCK ? 0 : error); } @@ -765,7 +765,7 @@ eso_halt_input(void *hdl) { struct eso_softc *sc = hdl; int error; - + DPRINTF(("%s: halt_input\n", sc->sc_dev.dv_xname)); /* Just like eso_halt_output(), but for Audio 1. */ @@ -930,7 +930,7 @@ eso_set_port(void *hdl, mixer_ctrl_t *cp) eso_write_mixreg(sc, ESO_MIXREG_RMVM, eso_read_mixreg(sc, ESO_MIXREG_RMVM) | ESO_MIXREG_RMVM_MUTE); - } else { + } else { eso_write_mixreg(sc, ESO_MIXREG_LMVM, eso_read_mixreg(sc, ESO_MIXREG_LMVM) & ~ESO_MIXREG_LMVM_MUTE); @@ -1462,7 +1462,7 @@ eso_freemem(struct eso_dma *ed) bus_dmamem_unmap(ed->ed_dmat, ed->ed_addr, ed->ed_size); bus_dmamem_free(ed->ed_dmat, ed->ed_segs, ed->ed_nsegs); } - + void * eso_allocm(void *hdl, int direction, size_t size, int type, int flags) { @@ -1588,7 +1588,7 @@ eso_trigger_output(void *hdl, void *start, void *end, int blksize, sc->sc_parg = arg; /* Compute drain timeout (milliseconds). */ - sc->sc_pdrain = 1000 * (blksize * 3 / 2) / + sc->sc_pdrain = 1000 * (blksize * 3 / 2) / (param->sample_rate * param->channels * param->bps); /* DMA transfer count (in `words'!) reload using 2's complement. */ @@ -1671,7 +1671,7 @@ eso_trigger_input(void *hdl, void *start, void *end, int blksize, sc->sc_rarg = arg; /* Compute drain timeout (milliseconds). */ - sc->sc_rdrain = 1000 * (blksize * 3 / 2) / + sc->sc_rdrain = 1000 * (blksize * 3 / 2) / (param->sample_rate * param->channels * param->bps); /* Set up ADC DMA converter parameters. */ @@ -1940,13 +1940,13 @@ eso_set_gain(struct eso_softc *sc, uint port) sc->sc_gain[port][ESO_LEFT], sc->sc_gain[port][ESO_RIGHT])); return; default: -#ifdef DIAGNOSTIC +#ifdef DIAGNOSTIC printf("eso_set_gain: bad port %u", port); return; /* NOTREACHED */ #else return; -#endif +#endif } eso_write_mixreg(sc, mixreg, ESO_4BIT_GAIN_TO_STEREO( diff --git a/sys/dev/pci/esoreg.h b/sys/dev/pci/esoreg.h index 124e89ab9..5d6663bcd 100644 --- a/sys/dev/pci/esoreg.h +++ b/sys/dev/pci/esoreg.h @@ -129,7 +129,7 @@ #define ESO_MIXREG_PVR_SYNTH 0x36 /* Playback mixer: FM/Synth */ #define ESO_MIXREG_PVR_CD 0x38 /* Playback mixer: AuxA/CD */ #define ESO_MIXREG_PVR_AUXB 0x3a /* Playback mixer: AuxB */ -#define ESO_MIXREG_PCSPKR_VOL 0x3c /* PC speaker volume */ +#define ESO_MIXREG_PCSPKR_VOL 0x3c /* PC speaker volume */ #define ESO_MIXREG_PVR_LINE 0x3e /* Playback mixer: Line */ #define ESO_MIXREG_SPAT 0x50 /* Spatializer Enable and Mode */ #define ESO_MIXREG_SPAT_MONO 0x02 /* 0 = Stereo in, 1 = Mono in */ diff --git a/sys/dev/pci/esovar.h b/sys/dev/pci/esovar.h index 50b3c45be..8cf8fdcf5 100644 --- a/sys/dev/pci/esovar.h +++ b/sys/dev/pci/esovar.h @@ -135,7 +135,7 @@ struct eso_softc { /* Audio 2 state */ uint8_t sc_a2c2; /* Audio 2 Control 2 */ - + /* Mixer state */ uint8_t sc_gain[ESO_NGAINDEVS][2]; #define ESO_LEFT 0 diff --git a/sys/dev/pci/fms.c b/sys/dev/pci/fms.c index f3238126d..98f2469d8 100644 --- a/sys/dev/pci/fms.c +++ b/sys/dev/pci/fms.c @@ -75,7 +75,7 @@ int fms_intr(void *); int fms_open(void *, int); void fms_close(void *); -int fms_set_params(void *, int, int, struct audio_params *, +int fms_set_params(void *, int, int, struct audio_params *, struct audio_params *); int fms_round_blocksize(void *, int); int fms_halt_output(void *); @@ -147,13 +147,13 @@ fms_attach(struct device *parent, struct device *self, void *aux) const char *intrstr; u_int16_t k1; int i; - + if (pci_mapreg_map(pa, 0x10, PCI_MAPREG_TYPE_IO, 0, &sc->sc_iot, &sc->sc_ioh, NULL, &iosize, 0)) { printf(": can't map i/o space\n"); return; } - + if (bus_space_subregion(sc->sc_iot, sc->sc_ioh, 0x30, 2, &sc->sc_mpu_ioh)) { printf(": can't get mpu subregion handle\n"); @@ -167,14 +167,14 @@ fms_attach(struct device *parent, struct device *self, void *aux) bus_space_unmap(sc->sc_iot, sc->sc_ioh, iosize); return; } - + if (pci_intr_map(pa, &ih)) { printf(": couldn't map interrupt\n"); bus_space_unmap(sc->sc_iot, sc->sc_ioh, iosize); return; } intrstr = pci_intr_string(pc, ih); - + sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO | IPL_MPSAFE, fms_intr, sc, sc->sc_dev.dv_xname); if (sc->sc_ih == NULL) { @@ -185,40 +185,40 @@ fms_attach(struct device *parent, struct device *self, void *aux) bus_space_unmap(sc->sc_iot, sc->sc_ioh, iosize); return; } - + printf(": %s\n", intrstr); sc->sc_dmat = pa->pa_dmat; /* Disable legacy audio (SBPro compatibility) */ pci_conf_write(pc, pt, 0x40, 0); - + /* Reset codec and AC'97 */ bus_space_write_2(sc->sc_iot, sc->sc_ioh, FM_CODEC_CTL, 0x0020); delay(2); /* > 1us according to AC'97 documentation */ bus_space_write_2(sc->sc_iot, sc->sc_ioh, FM_CODEC_CTL, 0x0000); delay(1); /* > 168.2ns according to AC'97 documentation */ - + /* Set up volume */ bus_space_write_2(sc->sc_iot, sc->sc_ioh, FM_PCM_VOLUME, 0x0808); bus_space_write_2(sc->sc_iot, sc->sc_ioh, FM_FM_VOLUME, 0x0808); bus_space_write_2(sc->sc_iot, sc->sc_ioh, FM_I2S_VOLUME, 0x0808); - + bus_space_write_2(sc->sc_iot, sc->sc_ioh, FM_RECORD_SOURCE, 0x0000); - + /* Unmask playback, record and mpu interrupts, mask the rest */ k1 = bus_space_read_2(sc->sc_iot, sc->sc_ioh, FM_INTMASK); - bus_space_write_2(sc->sc_iot, sc->sc_ioh, FM_INTMASK, + bus_space_write_2(sc->sc_iot, sc->sc_ioh, FM_INTMASK, (k1 & ~(FM_INTMASK_PLAY | FM_INTMASK_REC | FM_INTMASK_MPU)) | FM_INTMASK_VOL); - bus_space_write_2(sc->sc_iot, sc->sc_ioh, FM_INTSTATUS, - FM_INTSTATUS_PLAY | FM_INTSTATUS_REC | FM_INTSTATUS_MPU | + bus_space_write_2(sc->sc_iot, sc->sc_ioh, FM_INTSTATUS, + FM_INTSTATUS_PLAY | FM_INTSTATUS_REC | FM_INTSTATUS_MPU | FM_INTSTATUS_VOL); #if NRADIO > 0 fmsradio_attach(sc); #endif /* NRADIO > 0 */ - + sc->host_if.arg = sc; sc->host_if.attach = fms_attach_codec; sc->host_if.read = fms_read_codec; @@ -227,7 +227,7 @@ fms_attach(struct device *parent, struct device *self, void *aux) if (ac97_attach(&sc->host_if) != 0) return; - + /* Turn mute off */ for (i = 0; i < 3; i++) { static struct { @@ -238,7 +238,7 @@ fms_attach(struct device *parent, struct device *self, void *aux) { AudioCrecord, AudioNvolume } }; struct mixer_ctrl ctl; - + ctl.type = AUDIO_MIXER_ENUM; ctl.un.ord = 0; ctl.dev = sc->codec_if->vtbl->get_portnum_by_name(sc->codec_if, @@ -271,7 +271,7 @@ fms_read_codec(void *addr, u_int8_t reg, u_int16_t *val) int i; /* Poll until codec is ready */ - for (i = 0; i < TIMO && bus_space_read_2(sc->sc_iot, sc->sc_ioh, + for (i = 0; i < TIMO && bus_space_read_2(sc->sc_iot, sc->sc_ioh, FM_CODEC_CMD) & FM_CODEC_CMD_BUSY; i++) delay(1); if (i >= TIMO) { @@ -280,18 +280,18 @@ fms_read_codec(void *addr, u_int8_t reg, u_int16_t *val) } /* Write register index, read access */ - bus_space_write_2(sc->sc_iot, sc->sc_ioh, FM_CODEC_CMD, + bus_space_write_2(sc->sc_iot, sc->sc_ioh, FM_CODEC_CMD, reg | FM_CODEC_CMD_READ); - + /* Poll until we have valid data */ - for (i = 0; i < TIMO && !(bus_space_read_2(sc->sc_iot, sc->sc_ioh, + for (i = 0; i < TIMO && !(bus_space_read_2(sc->sc_iot, sc->sc_ioh, FM_CODEC_CMD) & FM_CODEC_CMD_VALID); i++) delay(1); if (i >= TIMO) { printf("fms: no data from codec\n"); return 1; } - + /* Read data */ *val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, FM_CODEC_DATA); return 0; @@ -302,9 +302,9 @@ fms_write_codec(void *addr, u_int8_t reg, u_int16_t val) { struct fms_softc *sc = addr; int i; - + /* Poll until codec is ready */ - for (i = 0; i < TIMO && bus_space_read_2(sc->sc_iot, sc->sc_ioh, + for (i = 0; i < TIMO && bus_space_read_2(sc->sc_iot, sc->sc_ioh, FM_CODEC_CMD) & FM_CODEC_CMD_BUSY; i++) delay(1); if (i >= TIMO) { @@ -345,17 +345,17 @@ fms_intr(void *arg) { struct fms_softc *sc = arg; u_int16_t istat; - + mtx_enter(&audio_lock); istat = bus_space_read_2(sc->sc_iot, sc->sc_ioh, FM_INTSTATUS); if (istat & FM_INTSTATUS_PLAY) { - if ((sc->sc_play_nextblk += sc->sc_play_blksize) >= + if ((sc->sc_play_nextblk += sc->sc_play_blksize) >= sc->sc_play_end) sc->sc_play_nextblk = sc->sc_play_start; - bus_space_write_4(sc->sc_iot, sc->sc_ioh, - sc->sc_play_flip++ & 1 ? + bus_space_write_4(sc->sc_iot, sc->sc_ioh, + sc->sc_play_flip++ & 1 ? FM_PLAY_DMABUF2 : FM_PLAY_DMABUF1, sc->sc_play_nextblk); if (sc->sc_pintr) @@ -365,12 +365,12 @@ fms_intr(void *arg) } if (istat & FM_INTSTATUS_REC) { - if ((sc->sc_rec_nextblk += sc->sc_rec_blksize) >= + if ((sc->sc_rec_nextblk += sc->sc_rec_blksize) >= sc->sc_rec_end) sc->sc_rec_nextblk = sc->sc_rec_start; - bus_space_write_4(sc->sc_iot, sc->sc_ioh, - sc->sc_rec_flip++ & 1 ? + bus_space_write_4(sc->sc_iot, sc->sc_ioh, + sc->sc_rec_flip++ & 1 ? FM_REC_DMABUF2 : FM_REC_DMABUF1, sc->sc_rec_nextblk); if (sc->sc_rintr) @@ -378,13 +378,13 @@ fms_intr(void *arg) else printf("unexpected rec intr\n"); } - + #if 0 if (istat & FM_INTSTATUS_MPU) mpu_intr(sc->sc_mpu_dev); #endif - bus_space_write_2(sc->sc_iot, sc->sc_ioh, FM_INTSTATUS, + bus_space_write_2(sc->sc_iot, sc->sc_ioh, FM_INTSTATUS, istat & (FM_INTSTATUS_PLAY | FM_INTSTATUS_REC)); mtx_leave(&audio_lock); return 1; @@ -478,16 +478,16 @@ fms_set_params(void *addr, int setmode, int usemode, struct audio_params *play, rec->bps = AUDIO_BPS(rec->precision); rec->msb = 1; - for (i = 0; i < 10 && rec->sample_rate > fms_rates[i].limit; + for (i = 0; i < 10 && rec->sample_rate > fms_rates[i].limit; i++) ; rec->sample_rate = fms_rates[i].rate; - sc->sc_rec_reg = - (rec->channels == 2 ? FM_REC_STEREO : 0) | + sc->sc_rec_reg = + (rec->channels == 2 ? FM_REC_STEREO : 0) | (rec->precision == 16 ? FM_REC_16BIT : 0) | (i << 8); } - + return 0; } @@ -505,8 +505,8 @@ fms_halt_output(void *addr) mtx_enter(&audio_lock); k1 = bus_space_read_2(sc->sc_iot, sc->sc_ioh, FM_PLAY_CTL); - bus_space_write_2(sc->sc_iot, sc->sc_ioh, FM_PLAY_CTL, - (k1 & ~(FM_PLAY_STOPNOW | FM_PLAY_START)) | + bus_space_write_2(sc->sc_iot, sc->sc_ioh, FM_PLAY_CTL, + (k1 & ~(FM_PLAY_STOPNOW | FM_PLAY_START)) | FM_PLAY_BUF1_LAST | FM_PLAY_BUF2_LAST); mtx_leave(&audio_lock); return 0; @@ -520,7 +520,7 @@ fms_halt_input(void *addr) mtx_enter(&audio_lock); k1 = bus_space_read_2(sc->sc_iot, sc->sc_ioh, FM_REC_CTL); - bus_space_write_2(sc->sc_iot, sc->sc_ioh, FM_REC_CTL, + bus_space_write_2(sc->sc_iot, sc->sc_ioh, FM_REC_CTL, (k1 & ~(FM_REC_STOPNOW | FM_REC_START)) | FM_REC_BUF1_LAST | FM_REC_BUF2_LAST); mtx_leave(&audio_lock); @@ -539,7 +539,7 @@ int fms_get_port(void *addr, mixer_ctrl_t *cp) { struct fms_softc *sc = addr; - + return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp)); } @@ -550,40 +550,40 @@ fms_malloc(void *addr, int direction, size_t size, int pool, int flags) struct fms_dma *p; int error; int rseg; - + p = malloc(sizeof(*p), pool, flags); if (!p) return 0; - + p->size = size; - if ((error = bus_dmamem_alloc(sc->sc_dmat, size, NBPG, 0, &p->seg, 1, + if ((error = bus_dmamem_alloc(sc->sc_dmat, size, NBPG, 0, &p->seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { - printf("%s: unable to allocate dma, error = %d\n", + printf("%s: unable to allocate dma, error = %d\n", sc->sc_dev.dv_xname, error); goto fail_alloc; } - + if ((error = bus_dmamem_map(sc->sc_dmat, &p->seg, rseg, size, &p->addr, BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { - printf("%s: unable to map dma, error = %d\n", + printf("%s: unable to map dma, error = %d\n", sc->sc_dev.dv_xname, error); goto fail_map; } - - if ((error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, + + if ((error = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0, BUS_DMA_NOWAIT, &p->map)) != 0) { printf("%s: unable to create dma map, error = %d\n", sc->sc_dev.dv_xname, error); goto fail_create; } - + if ((error = bus_dmamap_load(sc->sc_dmat, p->map, p->addr, size, NULL, BUS_DMA_NOWAIT)) != 0) { printf("%s: unable to load dma map, error = %d\n", sc->sc_dev.dv_xname, error); goto fail_load; } - + p->next = sc->sc_dmas; sc->sc_dmas = p; @@ -613,7 +613,7 @@ fms_free(void *addr, void *ptr, int pool) bus_dmamap_destroy(sc->sc_dmat, p->map); bus_dmamem_unmap(sc->sc_dmat, p->addr, p->size); bus_dmamem_free(sc->sc_dmat, &p->seg, 1); - + *pp = p->next; free(p, pool, sizeof(*p)); return; @@ -636,13 +636,13 @@ fms_trigger_output(void *addr, void *start, void *end, int blksize, { struct fms_softc *sc = addr; struct fms_dma *p; - + sc->sc_pintr = intr; sc->sc_parg = arg; - + for (p = sc->sc_dmas; p && p->addr != start; p = p->next) ; - + if (!p) panic("fms_trigger_output: request with bad start " "address (%p)", start); @@ -650,15 +650,15 @@ fms_trigger_output(void *addr, void *start, void *end, int blksize, sc->sc_play_start = p->map->dm_segs[0].ds_addr; sc->sc_play_end = sc->sc_play_start + ((char *)end - (char *)start); sc->sc_play_blksize = blksize; - sc->sc_play_nextblk = sc->sc_play_start + sc->sc_play_blksize; + sc->sc_play_nextblk = sc->sc_play_start + sc->sc_play_blksize; sc->sc_play_flip = 0; mtx_enter(&audio_lock); bus_space_write_2(sc->sc_iot, sc->sc_ioh, FM_PLAY_DMALEN, blksize - 1); - bus_space_write_4(sc->sc_iot, sc->sc_ioh, FM_PLAY_DMABUF1, + bus_space_write_4(sc->sc_iot, sc->sc_ioh, FM_PLAY_DMABUF1, sc->sc_play_start); - bus_space_write_4(sc->sc_iot, sc->sc_ioh, FM_PLAY_DMABUF2, + bus_space_write_4(sc->sc_iot, sc->sc_ioh, FM_PLAY_DMABUF2, sc->sc_play_nextblk); - bus_space_write_2(sc->sc_iot, sc->sc_ioh, FM_PLAY_CTL, + bus_space_write_2(sc->sc_iot, sc->sc_ioh, FM_PLAY_CTL, FM_PLAY_START | FM_PLAY_STOPNOW | sc->sc_play_reg); mtx_leave(&audio_lock); return 0; @@ -671,13 +671,13 @@ fms_trigger_input(void *addr, void *start, void *end, int blksize, { struct fms_softc *sc = addr; struct fms_dma *p; - + sc->sc_rintr = intr; sc->sc_rarg = arg; - + for (p = sc->sc_dmas; p && p->addr != start; p = p->next) ; - + if (!p) panic("fms_trigger_input: request with bad start " "address (%p)", start); @@ -685,15 +685,15 @@ fms_trigger_input(void *addr, void *start, void *end, int blksize, sc->sc_rec_start = p->map->dm_segs[0].ds_addr; sc->sc_rec_end = sc->sc_rec_start + ((char *)end - (char *)start); sc->sc_rec_blksize = blksize; - sc->sc_rec_nextblk = sc->sc_rec_start + sc->sc_rec_blksize; + sc->sc_rec_nextblk = sc->sc_rec_start + sc->sc_rec_blksize; sc->sc_rec_flip = 0; mtx_enter(&audio_lock); bus_space_write_2(sc->sc_iot, sc->sc_ioh, FM_REC_DMALEN, blksize - 1); - bus_space_write_4(sc->sc_iot, sc->sc_ioh, FM_REC_DMABUF1, + bus_space_write_4(sc->sc_iot, sc->sc_ioh, FM_REC_DMABUF1, sc->sc_rec_start); - bus_space_write_4(sc->sc_iot, sc->sc_ioh, FM_REC_DMABUF2, + bus_space_write_4(sc->sc_iot, sc->sc_ioh, FM_REC_DMABUF2, sc->sc_rec_nextblk); - bus_space_write_2(sc->sc_iot, sc->sc_ioh, FM_REC_CTL, + bus_space_write_2(sc->sc_iot, sc->sc_ioh, FM_REC_CTL, FM_REC_START | FM_REC_STOPNOW | sc->sc_rec_reg); mtx_leave(&audio_lock); return 0; diff --git a/sys/dev/pci/fmsvar.h b/sys/dev/pci/fmsvar.h index 68b72f174..b21f4bcdf 100644 --- a/sys/dev/pci/fmsvar.h +++ b/sys/dev/pci/fmsvar.h @@ -29,8 +29,8 @@ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ - - + + #ifndef _DEV_PCI_FMSVAR_H_ #define _DEV_PCI_FMSVAR_H_ diff --git a/sys/dev/pci/gcu.c b/sys/dev/pci/gcu.c index 70b9d6ea4..eda31705e 100644 --- a/sys/dev/pci/gcu.c +++ b/sys/dev/pci/gcu.c @@ -16,9 +16,9 @@ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ -/* +/* * Driver for a GCU device that appears on embedded intel systems, like 80579 - */ + */ #include #include @@ -37,7 +37,7 @@ int gcu_detach(struct device *, int); const struct pci_matchid gcu_devices[] = { { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EP80579_GCU } }; - + struct cfdriver gcu_cd = { NULL, "gcu", DV_IFNET }; @@ -66,7 +66,7 @@ gcu_attach(struct device *parent, struct device *self, void *aux) return; } - if (pci_mapreg_map(pa, 0x10, PCI_MAPREG_MEM_TYPE(val), 0, &sc->tag, + if (pci_mapreg_map(pa, 0x10, PCI_MAPREG_MEM_TYPE(val), 0, &sc->tag, &sc->handle, &sc->addr, &sc->size, 0)) { printf(": cannot find mem space\n"); return; diff --git a/sys/dev/pci/gcu_reg.h b/sys/dev/pci/gcu_reg.h index 970f84b3b..24aa0a412 100644 --- a/sys/dev/pci/gcu_reg.h +++ b/sys/dev/pci/gcu_reg.h @@ -3,37 +3,37 @@ /* * Copyright(c) 2007,2008,2009 Intel Corporation. All rights reserved. * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions * are met: - * - * * Redistributions of source code must retain the above copyright + * + * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the * distribution. - * * Neither the name of Intel Corporation nor the names of its - * contributors may be used to endorse or promote products derived + * * Neither the name of Intel Corporation nor the names of its + * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * * version: Embedded.B.1.0.3-146 */ -/* +/* * gcu_reg.h * Macros and constants related to the registers available on the GCU */ @@ -64,7 +64,7 @@ #define MDIO_COMMAND_WRITE_DATA_OFFSET 0 #define MDIO_COMMAND_PHY_ADDR_MAX 2 /* total phys supported by GCU */ -#define MDIO_COMMAND_PHY_REG_MAX 31 /* total registers available on +#define MDIO_COMMAND_PHY_REG_MAX 31 /* total registers available on * the M88 Phy used on truxton */ #endif /* ifndef GCU_REG_H */ diff --git a/sys/dev/pci/glxpcib.c b/sys/dev/pci/glxpcib.c index 08f23f3ed..31622d13c 100644 --- a/sys/dev/pci/glxpcib.c +++ b/sys/dev/pci/glxpcib.c @@ -257,7 +257,7 @@ const struct pci_matchid glxpcib_devices[] = { int glxpcib_match(struct device *parent, void *match, void *aux) -{ +{ if (pci_matchbyid((struct pci_attach_args *)aux, glxpcib_devices, nitems(glxpcib_devices))) { /* needs to win over pcib */ diff --git a/sys/dev/pci/i82365_pcivar.h b/sys/dev/pci/i82365_pcivar.h index a38e47f58..c9cf0c5a1 100644 --- a/sys/dev/pci/i82365_pcivar.h +++ b/sys/dev/pci/i82365_pcivar.h @@ -32,7 +32,7 @@ struct pcic_pci_softc { void *intr_est; /* XXX */ }; -/* +/* * Establish/disestablish interrupts for PCMCIA functions. */ diff --git a/sys/dev/pci/ichwdt.c b/sys/dev/pci/ichwdt.c index 81e66b18d..b1f0a917c 100644 --- a/sys/dev/pci/ichwdt.c +++ b/sys/dev/pci/ichwdt.c @@ -135,7 +135,7 @@ ichwdt_attach(struct device *parent, struct device *self, void *aux) /* Disable watchdog */ pci_conf_write(sc->sc_pc, sc->sc_tag, ICH_WDT_LOCK, 0); sc->sc_period = 0; - + printf("\n"); /* Register new watchdog */ diff --git a/sys/dev/pci/if_age.c b/sys/dev/pci/if_age.c index f035023bf..e21a09049 100644 --- a/sys/dev/pci/if_age.c +++ b/sys/dev/pci/if_age.c @@ -187,7 +187,7 @@ age_attach(struct device *parent, struct device *self, void *aux) /* Get PCI and chip id/revision. */ sc->age_rev = PCI_REVISION(pa->pa_class); - sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >> + sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >> MASTER_CHIP_REV_SHIFT; if (agedebug) { printf("%s: PCI device revision : 0x%04x\n", @@ -538,7 +538,7 @@ age_get_macaddr(struct age_softc *sc) sc->sc_dev.dv_xname); } else { if (agedebug) - printf("%s: PCI VPD capability not found!\n", + printf("%s: PCI VPD capability not found!\n", sc->sc_dev.dv_xname); } @@ -640,14 +640,14 @@ age_dma_alloc(struct age_softc *sc) /* * Create DMA stuffs for TX ring */ - error = bus_dmamap_create(sc->sc_dmat, AGE_TX_RING_SZ, 1, + error = bus_dmamap_create(sc->sc_dmat, AGE_TX_RING_SZ, 1, AGE_TX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_tx_ring_map); if (error) return (ENOBUFS); /* Allocate DMA'able memory for TX ring */ - error = bus_dmamem_alloc(sc->sc_dmat, AGE_TX_RING_SZ, - ETHER_ALIGN, 0, &sc->age_rdata.age_tx_ring_seg, 1, + error = bus_dmamem_alloc(sc->sc_dmat, AGE_TX_RING_SZ, + ETHER_ALIGN, 0, &sc->age_rdata.age_tx_ring_seg, 1, &nsegs, BUS_DMA_WAITOK | BUS_DMA_ZERO); if (error) { printf("%s: could not allocate DMA'able memory for Tx ring.\n", @@ -658,7 +658,7 @@ age_dma_alloc(struct age_softc *sc) error = bus_dmamem_map(sc->sc_dmat, &sc->age_rdata.age_tx_ring_seg, nsegs, AGE_TX_RING_SZ, (caddr_t *)&sc->age_rdata.age_tx_ring, BUS_DMA_NOWAIT); - if (error) + if (error) return (ENOBUFS); /* Load the DMA map for Tx ring. */ @@ -667,25 +667,25 @@ age_dma_alloc(struct age_softc *sc) if (error) { printf("%s: could not load DMA'able memory for Tx ring.\n", sc->sc_dev.dv_xname); - bus_dmamem_free(sc->sc_dmat, + bus_dmamem_free(sc->sc_dmat, (bus_dma_segment_t *)&sc->age_rdata.age_tx_ring, 1); return error; } - sc->age_rdata.age_tx_ring_paddr = + sc->age_rdata.age_tx_ring_paddr = sc->age_cdata.age_tx_ring_map->dm_segs[0].ds_addr; /* * Create DMA stuffs for RX ring */ - error = bus_dmamap_create(sc->sc_dmat, AGE_RX_RING_SZ, 1, + error = bus_dmamap_create(sc->sc_dmat, AGE_RX_RING_SZ, 1, AGE_RX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_rx_ring_map); - if (error) + if (error) return (ENOBUFS); /* Allocate DMA'able memory for RX ring */ - error = bus_dmamem_alloc(sc->sc_dmat, AGE_RX_RING_SZ, - ETHER_ALIGN, 0, &sc->age_rdata.age_rx_ring_seg, 1, + error = bus_dmamem_alloc(sc->sc_dmat, AGE_RX_RING_SZ, + ETHER_ALIGN, 0, &sc->age_rdata.age_rx_ring_seg, 1, &nsegs, BUS_DMA_WAITOK | BUS_DMA_ZERO); if (error) { printf("%s: could not allocate DMA'able memory for Rx ring.\n", @@ -710,20 +710,20 @@ age_dma_alloc(struct age_softc *sc) return error; } - sc->age_rdata.age_rx_ring_paddr = + sc->age_rdata.age_rx_ring_paddr = sc->age_cdata.age_rx_ring_map->dm_segs[0].ds_addr; /* * Create DMA stuffs for RX return ring */ - error = bus_dmamap_create(sc->sc_dmat, AGE_RR_RING_SZ, 1, + error = bus_dmamap_create(sc->sc_dmat, AGE_RR_RING_SZ, 1, AGE_RR_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_rr_ring_map); if (error) return (ENOBUFS); /* Allocate DMA'able memory for RX return ring */ - error = bus_dmamem_alloc(sc->sc_dmat, AGE_RR_RING_SZ, - ETHER_ALIGN, 0, &sc->age_rdata.age_rr_ring_seg, 1, + error = bus_dmamem_alloc(sc->sc_dmat, AGE_RR_RING_SZ, + ETHER_ALIGN, 0, &sc->age_rdata.age_rr_ring_seg, 1, &nsegs, BUS_DMA_WAITOK | BUS_DMA_ZERO); if (error) { printf("%s: could not allocate DMA'able memory for Rx " @@ -748,21 +748,21 @@ age_dma_alloc(struct age_softc *sc) return error; } - sc->age_rdata.age_rr_ring_paddr = + sc->age_rdata.age_rr_ring_paddr = sc->age_cdata.age_rr_ring_map->dm_segs[0].ds_addr; /* - * Create DMA stuffs for CMB block + * Create DMA stuffs for CMB block */ - error = bus_dmamap_create(sc->sc_dmat, AGE_CMB_BLOCK_SZ, 1, - AGE_CMB_BLOCK_SZ, 0, BUS_DMA_NOWAIT, + error = bus_dmamap_create(sc->sc_dmat, AGE_CMB_BLOCK_SZ, 1, + AGE_CMB_BLOCK_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_cmb_block_map); - if (error) + if (error) return (ENOBUFS); /* Allocate DMA'able memory for CMB block */ - error = bus_dmamem_alloc(sc->sc_dmat, AGE_CMB_BLOCK_SZ, - ETHER_ALIGN, 0, &sc->age_rdata.age_cmb_block_seg, 1, + error = bus_dmamem_alloc(sc->sc_dmat, AGE_CMB_BLOCK_SZ, + ETHER_ALIGN, 0, &sc->age_rdata.age_cmb_block_seg, 1, &nsegs, BUS_DMA_WAITOK | BUS_DMA_ZERO); if (error) { printf("%s: could not allocate DMA'able memory for " @@ -778,7 +778,7 @@ age_dma_alloc(struct age_softc *sc) /* Load the DMA map for CMB block. */ error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_cmb_block_map, - sc->age_rdata.age_cmb_block, AGE_CMB_BLOCK_SZ, NULL, + sc->age_rdata.age_cmb_block, AGE_CMB_BLOCK_SZ, NULL, BUS_DMA_WAITOK); if (error) { printf("%s: could not load DMA'able memory for CMB block\n", @@ -788,21 +788,21 @@ age_dma_alloc(struct age_softc *sc) return error; } - sc->age_rdata.age_cmb_block_paddr = + sc->age_rdata.age_cmb_block_paddr = sc->age_cdata.age_cmb_block_map->dm_segs[0].ds_addr; /* * Create DMA stuffs for SMB block */ - error = bus_dmamap_create(sc->sc_dmat, AGE_SMB_BLOCK_SZ, 1, - AGE_SMB_BLOCK_SZ, 0, BUS_DMA_NOWAIT, + error = bus_dmamap_create(sc->sc_dmat, AGE_SMB_BLOCK_SZ, 1, + AGE_SMB_BLOCK_SZ, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_smb_block_map); if (error) return (ENOBUFS); /* Allocate DMA'able memory for SMB block */ - error = bus_dmamem_alloc(sc->sc_dmat, AGE_SMB_BLOCK_SZ, - ETHER_ALIGN, 0, &sc->age_rdata.age_smb_block_seg, 1, + error = bus_dmamem_alloc(sc->sc_dmat, AGE_SMB_BLOCK_SZ, + ETHER_ALIGN, 0, &sc->age_rdata.age_smb_block_seg, 1, &nsegs, BUS_DMA_WAITOK | BUS_DMA_ZERO); if (error) { printf("%s: could not allocate DMA'able memory for " @@ -818,7 +818,7 @@ age_dma_alloc(struct age_softc *sc) /* Load the DMA map for SMB block */ error = bus_dmamap_load(sc->sc_dmat, sc->age_cdata.age_smb_block_map, - sc->age_rdata.age_smb_block, AGE_SMB_BLOCK_SZ, NULL, + sc->age_rdata.age_smb_block, AGE_SMB_BLOCK_SZ, NULL, BUS_DMA_WAITOK); if (error) { printf("%s: could not load DMA'able memory for SMB block\n", @@ -828,7 +828,7 @@ age_dma_alloc(struct age_softc *sc) return error; } - sc->age_rdata.age_smb_block_paddr = + sc->age_rdata.age_smb_block_paddr = sc->age_cdata.age_smb_block_map->dm_segs[0].ds_addr; /* Create DMA maps for Tx buffers. */ @@ -850,7 +850,7 @@ age_dma_alloc(struct age_softc *sc) error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0, BUS_DMA_NOWAIT, &sc->age_cdata.age_rx_sparemap); if (error) { - printf("%s: could not create spare Rx dmamap.\n", + printf("%s: could not create spare Rx dmamap.\n", sc->sc_dev.dv_xname); return error; } @@ -909,11 +909,11 @@ age_dma_free(struct age_softc *sc) sc->age_cdata.age_tx_ring_map = NULL; /* Rx ring. */ - if (sc->age_cdata.age_rx_ring_map != NULL) + if (sc->age_cdata.age_rx_ring_map != NULL) bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_rx_ring_map); if (sc->age_cdata.age_rx_ring_map != NULL && sc->age_rdata.age_rx_ring != NULL) - bus_dmamem_free(sc->sc_dmat, + bus_dmamem_free(sc->sc_dmat, (bus_dma_segment_t *)sc->age_rdata.age_rx_ring, 1); sc->age_rdata.age_rx_ring = NULL; sc->age_cdata.age_rx_ring_map = NULL; @@ -923,7 +923,7 @@ age_dma_free(struct age_softc *sc) bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_rr_ring_map); if (sc->age_cdata.age_rr_ring_map != NULL && sc->age_rdata.age_rr_ring != NULL) - bus_dmamem_free(sc->sc_dmat, + bus_dmamem_free(sc->sc_dmat, (bus_dma_segment_t *)sc->age_rdata.age_rr_ring, 1); sc->age_rdata.age_rr_ring = NULL; sc->age_cdata.age_rr_ring_map = NULL; @@ -943,7 +943,7 @@ age_dma_free(struct age_softc *sc) bus_dmamap_unload(sc->sc_dmat, sc->age_cdata.age_smb_block_map); if (sc->age_cdata.age_smb_block_map != NULL && sc->age_rdata.age_smb_block != NULL) - bus_dmamem_free(sc->sc_dmat, + bus_dmamem_free(sc->sc_dmat, (bus_dma_segment_t *)sc->age_rdata.age_smb_block, 1); sc->age_rdata.age_smb_block = NULL; sc->age_cdata.age_smb_block_map = NULL; @@ -1166,7 +1166,7 @@ age_encap(struct age_softc *sc, struct mbuf *m) for (i = 0; i < map->dm_nsegs; i++) { desc = &sc->age_rdata.age_tx_ring[prod]; desc->addr = htole64(map->dm_segs[i].ds_addr); - desc->len = + desc->len = htole32(AGE_TX_BYTES(map->dm_segs[i].ds_len) | vtag); desc->flags = htole32(cflags); sc->age_cdata.age_tx_cnt++; @@ -1371,7 +1371,7 @@ age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd) */ if (status & AGE_RRD_IPV4) { if ((status & AGE_RRD_IPCSUM_NOK) == 0) - m->m_pkthdr.csum_flags |= + m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; if ((status & (AGE_RRD_TCP | AGE_RRD_UDP)) && (status & AGE_RRD_TCP_UDPCSUM_NOK) == 0) { @@ -1421,7 +1421,7 @@ age_rxintr(struct age_softc *sc, int rr_prod) return; bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rr_ring_map, 0, - sc->age_cdata.age_rr_ring_map->dm_mapsize, + sc->age_cdata.age_rr_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); bus_dmamap_sync(sc->sc_dmat, sc->age_cdata.age_rx_ring_map, 0, sc->age_cdata.age_rx_ring_map->dm_mapsize, @@ -1613,7 +1613,7 @@ age_init(struct ifnet *ifp) reg |= MASTER_ITIMER_ENB; CSR_WRITE_4(sc, AGE_MASTER_CFG, reg); if (agedebug) - printf("%s: interrupt moderation is %d us.\n", + printf("%s: interrupt moderation is %d us.\n", sc->sc_dev.dv_xname, sc->age_int_mod); CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000)); @@ -2137,7 +2137,7 @@ age_newbuf(struct age_softc *sc, struct age_rxdesc *rxd) desc = rxd->rx_desc; desc->addr = htole64(rxd->rx_dmamap->dm_segs[0].ds_addr); - desc->len = + desc->len = htole32((rxd->rx_dmamap->dm_segs[0].ds_len & AGE_RD_LEN_MASK) << AGE_RD_LEN_SHIFT); @@ -2190,7 +2190,7 @@ age_iff(struct age_softc *sc) ETHER_FIRST_MULTI(step, ac, enm); while (enm != NULL) { - crc = ether_crc32_be(enm->enm_addrlo, + crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); diff --git a/sys/dev/pci/if_alc.c b/sys/dev/pci/if_alc.c index ae30a9810..06e037345 100644 --- a/sys/dev/pci/if_alc.c +++ b/sys/dev/pci/if_alc.c @@ -605,7 +605,7 @@ alc_get_macaddr_813x(struct alc_softc *sc) break; } if (i == 0) - printf("%s: reloading EEPROM timeout!\n", + printf("%s: reloading EEPROM timeout!\n", sc->sc_dev.dv_xname); } else { if (alcdebug) @@ -959,7 +959,7 @@ alc_phy_down(struct alc_softc *sc) default: /* Force PHY down. */ CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | - GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | + GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW); DELAY(1000); break; @@ -1342,7 +1342,7 @@ alc_attach(struct device *parent, struct device *self, void *aux) sc->alc_dma_wr_burst = (burst & 0x00e0) >> 5; if (alcdebug) { printf("%s: Read request size : %u bytes.\n", - sc->sc_dev.dv_xname, + sc->sc_dev.dv_xname, alc_dma_burst[sc->alc_dma_rd_burst]); printf("%s: TLP payload size : %u bytes.\n", sc->sc_dev.dv_xname, @@ -1416,7 +1416,7 @@ alc_attach(struct device *parent, struct device *self, void *aux) ifmedia_add(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL, 0, NULL); ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_MANUAL); - } else + } else ifmedia_set(&sc->sc_miibus.mii_media, IFM_ETHER | IFM_AUTO); if_attach(ifp); @@ -1523,12 +1523,12 @@ alc_dma_alloc(struct alc_softc *sc) if (error) { printf("%s: could not load DMA'able memory for Tx ring.\n", sc->sc_dev.dv_xname); - bus_dmamem_free(sc->sc_dmat, + bus_dmamem_free(sc->sc_dmat, (bus_dma_segment_t *)&sc->alc_rdata.alc_tx_ring, 1); return (error); } - sc->alc_rdata.alc_tx_ring_paddr = + sc->alc_rdata.alc_tx_ring_paddr = sc->alc_cdata.alc_tx_ring_map->dm_segs[0].ds_addr; /* @@ -1538,7 +1538,7 @@ alc_dma_alloc(struct alc_softc *sc) ALC_RX_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rx_ring_map); if (error) return (ENOBUFS); - + /* Allocate DMA'able memory for RX ring */ error = bus_dmamem_alloc(sc->sc_dmat, ALC_RX_RING_SZ, ETHER_ALIGN, 0, &sc->alc_rdata.alc_rx_ring_seg, 1, @@ -1572,14 +1572,14 @@ alc_dma_alloc(struct alc_softc *sc) /* * Create DMA stuffs for RX return ring */ - error = bus_dmamap_create(sc->sc_dmat, ALC_RR_RING_SZ, 1, + error = bus_dmamap_create(sc->sc_dmat, ALC_RR_RING_SZ, 1, ALC_RR_RING_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_rr_ring_map); if (error) return (ENOBUFS); /* Allocate DMA'able memory for RX return ring */ - error = bus_dmamem_alloc(sc->sc_dmat, ALC_RR_RING_SZ, - ETHER_ALIGN, 0, &sc->alc_rdata.alc_rr_ring_seg, 1, + error = bus_dmamem_alloc(sc->sc_dmat, ALC_RR_RING_SZ, + ETHER_ALIGN, 0, &sc->alc_rdata.alc_rr_ring_seg, 1, &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); if (error) { printf("%s: could not allocate DMA'able memory for Rx " @@ -1604,21 +1604,21 @@ alc_dma_alloc(struct alc_softc *sc) return (error); } - sc->alc_rdata.alc_rr_ring_paddr = + sc->alc_rdata.alc_rr_ring_paddr = sc->alc_cdata.alc_rr_ring_map->dm_segs[0].ds_addr; /* - * Create DMA stuffs for CMB block + * Create DMA stuffs for CMB block */ - error = bus_dmamap_create(sc->sc_dmat, ALC_CMB_SZ, 1, - ALC_CMB_SZ, 0, BUS_DMA_NOWAIT, + error = bus_dmamap_create(sc->sc_dmat, ALC_CMB_SZ, 1, + ALC_CMB_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_cmb_map); - if (error) + if (error) return (ENOBUFS); /* Allocate DMA'able memory for CMB block */ - error = bus_dmamem_alloc(sc->sc_dmat, ALC_CMB_SZ, - ETHER_ALIGN, 0, &sc->alc_rdata.alc_cmb_seg, 1, + error = bus_dmamem_alloc(sc->sc_dmat, ALC_CMB_SZ, + ETHER_ALIGN, 0, &sc->alc_rdata.alc_cmb_seg, 1, &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); if (error) { printf("%s: could not allocate DMA'able memory for " @@ -1634,7 +1634,7 @@ alc_dma_alloc(struct alc_softc *sc) /* Load the DMA map for CMB block. */ error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, - sc->alc_rdata.alc_cmb, ALC_CMB_SZ, NULL, + sc->alc_rdata.alc_cmb, ALC_CMB_SZ, NULL, BUS_DMA_WAITOK); if (error) { printf("%s: could not load DMA'able memory for CMB block\n", @@ -1644,21 +1644,21 @@ alc_dma_alloc(struct alc_softc *sc) return (error); } - sc->alc_rdata.alc_cmb_paddr = + sc->alc_rdata.alc_cmb_paddr = sc->alc_cdata.alc_cmb_map->dm_segs[0].ds_addr; /* * Create DMA stuffs for SMB block */ - error = bus_dmamap_create(sc->sc_dmat, ALC_SMB_SZ, 1, - ALC_SMB_SZ, 0, BUS_DMA_NOWAIT, + error = bus_dmamap_create(sc->sc_dmat, ALC_SMB_SZ, 1, + ALC_SMB_SZ, 0, BUS_DMA_NOWAIT, &sc->alc_cdata.alc_smb_map); if (error) return (ENOBUFS); /* Allocate DMA'able memory for SMB block */ - error = bus_dmamem_alloc(sc->sc_dmat, ALC_SMB_SZ, - ETHER_ALIGN, 0, &sc->alc_rdata.alc_smb_seg, 1, + error = bus_dmamem_alloc(sc->sc_dmat, ALC_SMB_SZ, + ETHER_ALIGN, 0, &sc->alc_rdata.alc_smb_seg, 1, &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO); if (error) { printf("%s: could not allocate DMA'able memory for " @@ -1674,7 +1674,7 @@ alc_dma_alloc(struct alc_softc *sc) /* Load the DMA map for SMB block */ error = bus_dmamap_load(sc->sc_dmat, sc->alc_cdata.alc_smb_map, - sc->alc_rdata.alc_smb, ALC_SMB_SZ, NULL, + sc->alc_rdata.alc_smb, ALC_SMB_SZ, NULL, BUS_DMA_WAITOK); if (error) { printf("%s: could not load DMA'able memory for SMB block\n", @@ -1684,7 +1684,7 @@ alc_dma_alloc(struct alc_softc *sc) return (error); } - sc->alc_rdata.alc_smb_paddr = + sc->alc_rdata.alc_smb_paddr = sc->alc_cdata.alc_smb_map->dm_segs[0].ds_addr; @@ -1767,11 +1767,11 @@ alc_dma_free(struct alc_softc *sc) sc->alc_cdata.alc_tx_ring_map = NULL; /* Rx ring. */ - if (sc->alc_cdata.alc_rx_ring_map != NULL) + if (sc->alc_cdata.alc_rx_ring_map != NULL) bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_rx_ring_map); if (sc->alc_cdata.alc_rx_ring_map != NULL && sc->alc_rdata.alc_rx_ring != NULL) - bus_dmamem_free(sc->sc_dmat, + bus_dmamem_free(sc->sc_dmat, (bus_dma_segment_t *)sc->alc_rdata.alc_rx_ring, 1); sc->alc_rdata.alc_rx_ring = NULL; sc->alc_cdata.alc_rx_ring_map = NULL; @@ -1781,7 +1781,7 @@ alc_dma_free(struct alc_softc *sc) bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_rr_ring_map); if (sc->alc_cdata.alc_rr_ring_map != NULL && sc->alc_rdata.alc_rr_ring != NULL) - bus_dmamem_free(sc->sc_dmat, + bus_dmamem_free(sc->sc_dmat, (bus_dma_segment_t *)sc->alc_rdata.alc_rr_ring, 1); sc->alc_rdata.alc_rr_ring = NULL; sc->alc_cdata.alc_rr_ring_map = NULL; @@ -1801,7 +1801,7 @@ alc_dma_free(struct alc_softc *sc) bus_dmamap_unload(sc->sc_dmat, sc->alc_cdata.alc_smb_map); if (sc->alc_cdata.alc_smb_map != NULL && sc->alc_rdata.alc_smb != NULL) - bus_dmamem_free(sc->sc_dmat, + bus_dmamem_free(sc->sc_dmat, (bus_dma_segment_t *)sc->alc_rdata.alc_smb, 1); sc->alc_rdata.alc_smb = NULL; sc->alc_cdata.alc_smb_map = NULL; @@ -1925,7 +1925,7 @@ alc_start(struct ifnet *ifp) continue; } enq++; - + #if NBPFILTER > 0 /* * If there's a BPF listener, bounce a copy of this frame @@ -1939,7 +1939,7 @@ alc_start(struct ifnet *ifp) if (enq > 0) { /* Sync descriptors. */ bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, - sc->alc_cdata.alc_tx_ring_map->dm_mapsize, + sc->alc_cdata.alc_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); /* Kick. Assume we're using normal Tx priority queue. */ if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) @@ -2067,13 +2067,13 @@ alc_stats_clear(struct alc_softc *sc) if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, - sc->alc_cdata.alc_smb_map->dm_mapsize, + sc->alc_cdata.alc_smb_map->dm_mapsize, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); smb = sc->alc_rdata.alc_smb; /* Update done, clear. */ smb->updated = 0; bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_smb_map, 0, - sc->alc_cdata.alc_smb_map->dm_mapsize, + sc->alc_cdata.alc_smb_map->dm_mapsize, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); } else { for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; @@ -2270,7 +2270,7 @@ alc_txeof(struct alc_softc *sc) BUS_DMASYNC_POSTWRITE); if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_cmb_map, 0, - sc->alc_cdata.alc_cmb_map->dm_mapsize, + sc->alc_cdata.alc_cmb_map->dm_mapsize, BUS_DMASYNC_POSTREAD); prod = sc->alc_rdata.alc_cmb->cons; } else { @@ -2648,7 +2648,7 @@ alc_reset(struct alc_softc *sc) } if (i == 0) - printf("%s: reset timeout(0x%08x)!\n", sc->sc_dev.dv_xname, + printf("%s: reset timeout(0x%08x)!\n", sc->sc_dev.dv_xname, reg); if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { diff --git a/sys/dev/pci/if_ale.c b/sys/dev/pci/if_ale.c index c1998c8bd..72eb01101 100644 --- a/sys/dev/pci/if_ale.c +++ b/sys/dev/pci/if_ale.c @@ -278,7 +278,7 @@ ale_get_macaddr(struct ale_softc *sc) CSR_WRITE_4(sc, ALE_SPI_CTRL, reg); } - if (pci_get_capability(sc->sc_pct, sc->sc_pcitag, PCI_CAP_VPD, + if (pci_get_capability(sc->sc_pct, sc->sc_pcitag, PCI_CAP_VPD, &vpdc, NULL)) { /* * PCI VPD capability found, let TWSI reload EEPROM. @@ -626,7 +626,7 @@ ale_dma_alloc(struct ale_softc *sc) return (ENOBUFS); /* Allocate DMA'able memory for TX ring */ - error = bus_dmamem_alloc(sc->sc_dmat, ALE_TX_RING_SZ, + error = bus_dmamem_alloc(sc->sc_dmat, ALE_TX_RING_SZ, ETHER_ALIGN, 0, &sc->ale_cdata.ale_tx_ring_seg, 1, &nsegs, BUS_DMA_WAITOK | BUS_DMA_ZERO); if (error) { @@ -642,16 +642,16 @@ ale_dma_alloc(struct ale_softc *sc) return (ENOBUFS); /* Load the DMA map for Tx ring. */ - error = bus_dmamap_load(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, + error = bus_dmamap_load(sc->sc_dmat, sc->ale_cdata.ale_tx_ring_map, sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ, NULL, BUS_DMA_WAITOK); if (error) { printf("%s: could not load DMA'able memory for Tx ring.\n", sc->sc_dev.dv_xname); - bus_dmamem_free(sc->sc_dmat, + bus_dmamem_free(sc->sc_dmat, (bus_dma_segment_t *)&sc->ale_cdata.ale_tx_ring, 1); return error; } - sc->ale_cdata.ale_tx_ring_paddr = + sc->ale_cdata.ale_tx_ring_paddr = sc->ale_cdata.ale_tx_ring_map->dm_segs[0].ds_addr; for (i = 0; i < ALE_RX_PAGES; i++) { @@ -659,7 +659,7 @@ ale_dma_alloc(struct ale_softc *sc) * Create DMA stuffs for RX pages */ error = bus_dmamap_create(sc->sc_dmat, sc->ale_pagesize, 1, - sc->ale_pagesize, 0, BUS_DMA_NOWAIT, + sc->ale_pagesize, 0, BUS_DMA_NOWAIT, &sc->ale_cdata.ale_rx_page[i].page_map); if (error) return (ENOBUFS); @@ -673,9 +673,9 @@ ale_dma_alloc(struct ale_softc *sc) "Rx ring.\n", sc->sc_dev.dv_xname); return error; } - error = bus_dmamem_map(sc->sc_dmat, + error = bus_dmamem_map(sc->sc_dmat, &sc->ale_cdata.ale_rx_page[i].page_seg, nsegs, - sc->ale_pagesize, + sc->ale_pagesize, (caddr_t *)&sc->ale_cdata.ale_rx_page[i].page_addr, BUS_DMA_NOWAIT); if (error) @@ -719,11 +719,11 @@ ale_dma_alloc(struct ale_softc *sc) error = bus_dmamem_map(sc->sc_dmat, &sc->ale_cdata.ale_tx_cmb_seg, nsegs, ALE_TX_CMB_SZ, (caddr_t *)&sc->ale_cdata.ale_tx_cmb, BUS_DMA_NOWAIT); - if (error) + if (error) return (ENOBUFS); /* Load the DMA map for Tx CMB. */ - error = bus_dmamap_load(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, + error = bus_dmamap_load(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ, NULL, BUS_DMA_WAITOK); if (error) { printf("%s: could not load DMA'able memory for Tx CMB.\n", @@ -733,7 +733,7 @@ ale_dma_alloc(struct ale_softc *sc) return error; } - sc->ale_cdata.ale_tx_cmb_paddr = + sc->ale_cdata.ale_tx_cmb_paddr = sc->ale_cdata.ale_tx_cmb_map->dm_segs[0].ds_addr; for (i = 0; i < ALE_RX_PAGES; i++) { @@ -755,9 +755,9 @@ ale_dma_alloc(struct ale_softc *sc) "Rx CMB\n", sc->sc_dev.dv_xname); return error; } - error = bus_dmamem_map(sc->sc_dmat, + error = bus_dmamem_map(sc->sc_dmat, &sc->ale_cdata.ale_rx_page[i].cmb_seg, nsegs, - ALE_RX_CMB_SZ, + ALE_RX_CMB_SZ, (caddr_t *)&sc->ale_cdata.ale_rx_page[i].cmb_addr, BUS_DMA_NOWAIT); if (error) @@ -937,7 +937,7 @@ ale_encap(struct ale_softc *sc, struct mbuf *m) for (i = 0; i < map->dm_nsegs; i++) { desc = &sc->ale_cdata.ale_tx_ring[prod]; desc->addr = htole64(map->dm_segs[i].ds_addr); - desc->len = + desc->len = htole32(ALE_TX_BYTES(map->dm_segs[i].ds_len) | vtag); desc->flags = htole32(cflags); sc->ale_cdata.ale_tx_cnt++; @@ -1298,7 +1298,7 @@ ale_txeof(struct ale_softc *sc) sc->ale_cdata.ale_tx_ring_map->dm_mapsize, BUS_DMASYNC_POSTREAD); if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) { bus_dmamap_sync(sc->sc_dmat, sc->ale_cdata.ale_tx_cmb_map, 0, - sc->ale_cdata.ale_tx_cmb_map->dm_mapsize, + sc->ale_cdata.ale_tx_cmb_map->dm_mapsize, BUS_DMASYNC_POSTREAD); prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK; } else diff --git a/sys/dev/pci/if_aq_pci.c b/sys/dev/pci/if_aq_pci.c index 246406c2a..7632ea7a0 100644 --- a/sys/dev/pci/if_aq_pci.c +++ b/sys/dev/pci/if_aq_pci.c @@ -2548,7 +2548,7 @@ aq_hw_init_rx_path(struct aq_softc *sc) bits = 0x11111111; break; case 4: - bits = 0x22222222; + bits = 0x22222222; break; case 8: bits = 0x33333333; @@ -2806,7 +2806,7 @@ aq_init_rss(struct aq_softc *sc) int bits, queue; int error; int i; - + if (sc->sc_nqueues == 1) return 0; diff --git a/sys/dev/pci/if_ath_pci.c b/sys/dev/pci/if_ath_pci.c index 8944d4d8d..87989697d 100644 --- a/sys/dev/pci/if_ath_pci.c +++ b/sys/dev/pci/if_ath_pci.c @@ -127,7 +127,7 @@ ath_pci_attach(struct device *parent, struct device *self, void *aux) psc->sc_pc = pc; psc->sc_pcitag = pt; - /* + /* * Setup memory-mapping of PCI registers. */ mem_type = pci_mapreg_type(pc, pa->pa_tag, ATH_BAR0); diff --git a/sys/dev/pci/if_athn_pci.c b/sys/dev/pci/if_athn_pci.c index 35db06649..445544d8c 100644 --- a/sys/dev/pci/if_athn_pci.c +++ b/sys/dev/pci/if_athn_pci.c @@ -137,7 +137,7 @@ athn_pci_attach(struct device *parent, struct device *self, void *aux) sc->sc_disable_aspm = athn_pci_disable_aspm; sc->flags |= ATHN_FLAG_PCIE; } - /* + /* * Clear device-specific "PCI retry timeout" register (41h) to prevent * PCI Tx retries from interfering with C3 CPU state. */ @@ -145,7 +145,7 @@ athn_pci_attach(struct device *parent, struct device *self, void *aux) if (reg & 0xff00) pci_conf_write(pa->pa_pc, pa->pa_tag, 0x40, reg & ~0xff00); - /* + /* * Set the cache line size to a reasonable value if it is 0. * Change latency timer; default value yields poor results. */ diff --git a/sys/dev/pci/if_atw_pci.c b/sys/dev/pci/if_atw_pci.c index 899c1d5dd..7eca1e037 100644 --- a/sys/dev/pci/if_atw_pci.c +++ b/sys/dev/pci/if_atw_pci.c @@ -38,8 +38,8 @@ */ #include -#include -#include +#include +#include #include #include #include @@ -47,7 +47,7 @@ #include #include #include - + #include #include #include @@ -219,7 +219,7 @@ atw_pci_attach(struct device *parent, struct device *self, void *aux) printf(": unable to map interrupt\n"); return; } - intrstr = pci_intr_string(pc, psc->psc_ih); + intrstr = pci_intr_string(pc, psc->psc_ih); psc->psc_intrcookie = pci_intr_establish(pc, psc->psc_ih, IPL_NET, atw_intr, sc, sc->sc_dev.dv_xname); if (psc->psc_intrcookie == NULL) { diff --git a/sys/dev/pci/if_bge.c b/sys/dev/pci/if_bge.c index d8fa5c8e1..f116276c8 100644 --- a/sys/dev/pci/if_bge.c +++ b/sys/dev/pci/if_bge.c @@ -3077,7 +3077,7 @@ bge_attach(struct device *parent, struct device *self, void *aux) * to hardware bugs. * * It seems all controllers have a bug that can generate UDP - * datagrams with a checksum value 0 when TX UDP checksum + * datagrams with a checksum value 0 when TX UDP checksum * offloading is enabled. Generating UDP checksum value 0 is * a violation of RFC 768. */ @@ -3692,7 +3692,7 @@ bge_txeof(struct bge_softc *sc) struct mbuf *m; /* Nothing to do */ - cons = sc->bge_tx_saved_considx; + cons = sc->bge_tx_saved_considx; newcons = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx; if (cons == newcons) return; @@ -3882,7 +3882,7 @@ bge_stats_update_regs(struct bge_softc *sc) * bit of BGE_HDD_MODE, BGE_BMANMODE_LOMBUF_ATTN bit of BGE_BMAN_MODE * and BGE_MODECTL_FLOWCTL_ATTN_INTR bit of BGE_MODE_CTL. However * that change would generate more interrupts and there are still - * possibilities of losing multiple frames during + * possibilities of losing multiple frames during * BGE_MODECTL_FLOWCTL_ATTN_INTR interrupt handling. Given that * the workaround still would not get correct counter I don't think * it's worth to implement it. So ignore reading the counter on @@ -4092,7 +4092,7 @@ bge_cksum_pad(struct mbuf *m) last = n; } } - + /* Now zero the pad area, to avoid the bge cksum-assist bug. */ memset(mtod(last, caddr_t) + last->m_len, 0, padlen); last->m_len += padlen; @@ -4128,7 +4128,7 @@ bge_encap(struct bge_softc *sc, struct mbuf *m, int *txinc) } } - if (sc->bge_flags & BGE_JUMBO_FRAME && + if (sc->bge_flags & BGE_JUMBO_FRAME && m->m_pkthdr.len > ETHER_MAX_LEN) csum_flags |= BGE_TXBDFLAG_JUMBO_FRAME; @@ -4196,7 +4196,7 @@ doit: sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; sc->bge_cdata.bge_tx_chain[cur] = m; sc->bge_cdata.bge_tx_map[cur] = dmamap; - + *txinc += dmamap->dm_nsegs; return (0); diff --git a/sys/dev/pci/if_bgereg.h b/sys/dev/pci/if_bgereg.h index 105643a86..45cf46f85 100644 --- a/sys/dev/pci/if_bgereg.h +++ b/sys/dev/pci/if_bgereg.h @@ -2290,7 +2290,7 @@ /* * This magic number is written to the firmware mailbox at 0xb50 * before a software reset is issued. After the internal firmware - * has completed its initialization it will write the opposite of + * has completed its initialization it will write the opposite of * this value, ~BGE_MAGIC_NUMBER, to the same location, allowing the * driver to synchronize with the firmware. */ @@ -2651,7 +2651,7 @@ struct bge_stats { /* Statistics maintained by Transmit MAC. */ struct bge_tx_mac_stats txstats; - + bge_hostaddr Unused2[31]; /* Statistics maintained by Receive List Placement. */ @@ -2719,7 +2719,7 @@ struct bge_gib { * Vital product data and structures. */ #define BGE_VPD_FLAG 0x8000 - + #define VPD_RES_ID 0x82 /* ID string */ #define VPD_RES_READ 0x90 /* start of read only area */ #define VPD_RES_WRITE 0x81 /* start of read/write area */ @@ -2796,7 +2796,7 @@ struct bge_ring_data { * chosen to make the total struct size an even power of two. It's * critical that no TxCB be split across a page boundary since * no attempt is made to allocate physically contiguous memory. - * + * */ #ifdef __LP64__ #define BGE_NTXSEG 30 diff --git a/sys/dev/pci/if_bnx.c b/sys/dev/pci/if_bnx.c index ffc84023c..ce4bf3f22 100644 --- a/sys/dev/pci/if_bnx.c +++ b/sys/dev/pci/if_bnx.c @@ -616,7 +616,7 @@ bnx_read_rv2p(struct bnx_softc *sc, int idx) rv2p->bnx_rv2p_proc2 = (u_int32_t *)q; q += hdr->bnx_rv2p_proc2len; nswaph(rv2p->bnx_rv2p_proc2, hdr->bnx_rv2p_proc2len); - + if (q - p != size) { free(p, M_DEVBUF, size); return EINVAL; @@ -653,7 +653,7 @@ bnx_attach(struct device *parent, struct device *self, void *aux) /* * Map control/status registers. */ - memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BNX_PCI_BAR0); + memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BNX_PCI_BAR0); if (pci_mapreg_map(pa, BNX_PCI_BAR0, memtype, 0, &sc->bnx_btag, &sc->bnx_bhandle, NULL, &sc->bnx_size, 0)) { printf(": can't find mem space\n"); @@ -817,7 +817,7 @@ bnx_attachhook(struct device *self) * should be ready before generating an * interrupt while ticks control how long * a BD can sit in the chain before - * generating an interrupt. Set the default + * generating an interrupt. Set the default * values for the RX and TX rings. */ @@ -1244,8 +1244,8 @@ bnx_miibus_statchg(struct device *dev) int val; val = REG_RD(sc, BNX_EMAC_MODE); - val &= ~(BNX_EMAC_MODE_PORT | BNX_EMAC_MODE_HALF_DUPLEX | - BNX_EMAC_MODE_MAC_LOOP | BNX_EMAC_MODE_FORCE_LINK | + val &= ~(BNX_EMAC_MODE_PORT | BNX_EMAC_MODE_HALF_DUPLEX | + BNX_EMAC_MODE_MAC_LOOP | BNX_EMAC_MODE_FORCE_LINK | BNX_EMAC_MODE_25G); /* @@ -1715,7 +1715,7 @@ bnx_init_nvram(struct bnx_softc *sc) if (val & 0x40000000) { /* Flash interface reconfigured by bootcode. */ - DBPRINT(sc,BNX_INFO_LOAD, + DBPRINT(sc,BNX_INFO_LOAD, "bnx_init_nvram(): Flash WAS reconfigured.\n"); for (j = 0, flash = &flash_table[0]; j < entry_count; @@ -1730,7 +1730,7 @@ bnx_init_nvram(struct bnx_softc *sc) /* Flash interface not yet reconfigured. */ u_int32_t mask; - DBPRINT(sc,BNX_INFO_LOAD, + DBPRINT(sc,BNX_INFO_LOAD, "bnx_init_nvram(): Flash was NOT reconfigured.\n"); if (val & (1 << 23)) @@ -2165,9 +2165,9 @@ void bnx_get_media(struct bnx_softc *sc) { u_int32_t val; - + sc->bnx_phy_addr = 1; - + if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { u_int32_t val = REG_RD(sc, BNX_MISC_DUAL_MEDIA_CTRL); u_int32_t bond_id = val & BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID; @@ -2200,12 +2200,12 @@ bnx_get_media(struct bnx_softc *sc) case 0x4: case 0x5: case 0x6: - DBPRINT(sc, BNX_INFO_LOAD, + DBPRINT(sc, BNX_INFO_LOAD, "BCM5709 s/w configured for SerDes.\n"); sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; break; default: - DBPRINT(sc, BNX_INFO_LOAD, + DBPRINT(sc, BNX_INFO_LOAD, "BCM5709 s/w configured for Copper.\n"); } } else { @@ -2213,12 +2213,12 @@ bnx_get_media(struct bnx_softc *sc) case 0x1: case 0x2: case 0x4: - DBPRINT(sc, BNX_INFO_LOAD, + DBPRINT(sc, BNX_INFO_LOAD, "BCM5709 s/w configured for SerDes.\n"); sc->bnx_phy_flags |= BNX_PHY_SERDES_FLAG; break; default: - DBPRINT(sc, BNX_INFO_LOAD, + DBPRINT(sc, BNX_INFO_LOAD, "BCM5709 s/w configured for Copper.\n"); } } @@ -2251,7 +2251,7 @@ bnx_get_media(struct bnx_softc *sc) sc->bnx_phy_flags |= BNX_PHY_CRC_FIX_FLAG; bnx_get_media_exit: - DBPRINT(sc, (BNX_INFO_LOAD | BNX_INFO_PHY), + DBPRINT(sc, (BNX_INFO_LOAD | BNX_INFO_PHY), "Using PHY address %d.\n", sc->bnx_phy_addr); } @@ -2307,7 +2307,7 @@ bnx_dma_free(struct bnx_softc *sc) sc->status_map->dm_mapsize, BUS_DMASYNC_POSTREAD); bus_dmamap_unload(sc->bnx_dmatag, sc->status_map); bus_dmamem_unmap(sc->bnx_dmatag, (caddr_t)sc->status_block, - BNX_STATUS_BLK_SZ); + BNX_STATUS_BLK_SZ); bus_dmamem_free(sc->bnx_dmatag, &sc->status_seg, sc->status_rseg); bus_dmamap_destroy(sc->bnx_dmatag, sc->status_map); @@ -2319,7 +2319,7 @@ bnx_dma_free(struct bnx_softc *sc) if (sc->stats_block != NULL && sc->stats_map != NULL) { bus_dmamap_unload(sc->bnx_dmatag, sc->stats_map); bus_dmamem_unmap(sc->bnx_dmatag, (caddr_t)sc->stats_block, - BNX_STATS_BLK_SZ); + BNX_STATS_BLK_SZ); bus_dmamem_free(sc->bnx_dmatag, &sc->stats_seg, sc->stats_rseg); bus_dmamap_destroy(sc->bnx_dmatag, sc->stats_map); @@ -2552,7 +2552,7 @@ bnx_dma_alloc(struct bnx_softc *sc) sc->stats_block_paddr = sc->stats_map->dm_segs[0].ds_addr; /* DRC - Fix for 64 bit address. */ - DBPRINT(sc,BNX_INFO, "stats_block_paddr = 0x%08X\n", + DBPRINT(sc,BNX_INFO, "stats_block_paddr = 0x%08X\n", (u_int32_t) sc->stats_block_paddr); /* @@ -2597,7 +2597,7 @@ bnx_dma_alloc(struct bnx_softc *sc) sc->tx_bd_chain_map[i]->dm_segs[0].ds_addr; /* DRC - Fix for 64 bit systems. */ - DBPRINT(sc, BNX_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n", + DBPRINT(sc, BNX_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n", i, (u_int32_t) sc->tx_bd_chain_paddr[i]); } @@ -2617,7 +2617,7 @@ bnx_dma_alloc(struct bnx_softc *sc) if (bus_dmamem_alloc(sc->bnx_dmatag, BNX_RX_CHAIN_PAGE_SZ, BCM_PAGE_SIZE, BNX_DMA_BOUNDARY, &sc->rx_bd_chain_seg[i], 1, &sc->rx_bd_chain_rseg[i], BUS_DMA_NOWAIT | BUS_DMA_ZERO)) { - printf(": Could not allocate Rx desc %d DMA memory!\n", + printf(": Could not allocate Rx desc %d DMA memory!\n", i); rc = ENOMEM; goto bnx_dma_alloc_exit; @@ -2643,7 +2643,7 @@ bnx_dma_alloc(struct bnx_softc *sc) sc->rx_bd_chain_map[i]->dm_segs[0].ds_addr; /* DRC - Fix for 64 bit systems. */ - DBPRINT(sc, BNX_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n", + DBPRINT(sc, BNX_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n", i, (u_int32_t) sc->rx_bd_chain_paddr[i]); } @@ -2759,7 +2759,7 @@ bnx_fw_sync_exit: /* Nothing. */ /****************************************************************************/ void -bnx_load_rv2p_fw(struct bnx_softc *sc, u_int32_t *rv2p_code, +bnx_load_rv2p_fw(struct bnx_softc *sc, u_int32_t *rv2p_code, u_int32_t rv2p_code_len, u_int32_t rv2p_proc) { int i; @@ -3106,7 +3106,7 @@ bnx_init_context(struct bnx_softc *sc) /* DRC: Replace this constant value with a #define. */ int i, retry_cnt = 10; u_int32_t val; - + /* * BCM5709 context memory may be cached * in host memory so prepare the host memory @@ -3126,7 +3126,7 @@ bnx_init_context(struct bnx_softc *sc) } /* ToDo: Consider returning an error here. */ - + for (i = 0; i < sc->ctx_pages; i++) { int j; @@ -3166,7 +3166,7 @@ bnx_init_context(struct bnx_softc *sc) REG_WR(sc, BNX_CTX_VIRT_ADDR, 0); REG_WR(sc, BNX_CTX_PAGE_TBL, vcid_addr); - + for(offset = 0; offset < PHY_CTX_SIZE; offset += 4) { CTX_WR(sc, 0x00, offset, 0); } @@ -3620,7 +3620,7 @@ bnx_blockinit(struct bnx_softc *sc) if (BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5709) { REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, BNX_MISC_ENABLE_DEFAULT_XI); - } else + } else REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, BNX_MISC_ENABLE_DEFAULT); /* Enable all remaining blocks in the MAC. */ @@ -3658,7 +3658,7 @@ bnx_get_buf(struct bnx_softc *sc, u_int16_t *prod, #endif u_int16_t first_chain_prod; - DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Entering %s()\n", + DBPRINT(sc, (BNX_VERBOSE_RESET | BNX_VERBOSE_RECV), "Entering %s()\n", __FUNCTION__); /* Make sure the inputs are valid. */ @@ -3703,7 +3703,7 @@ bnx_get_buf(struct bnx_softc *sc, u_int16_t *prod, for (i = 1; i < map->dm_nsegs; i++) { *prod = NEXT_RX_BD(*prod); - *chain_prod = RX_CHAIN_IDX(*prod); + *chain_prod = RX_CHAIN_IDX(*prod); rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)]; @@ -3728,7 +3728,7 @@ bnx_get_buf(struct bnx_softc *sc, u_int16_t *prod, sc->rx_mbuf_map[first_chain_prod] = sc->rx_mbuf_map[*chain_prod]; sc->rx_mbuf_map[*chain_prod] = map; - DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_mbuf_chain(sc, debug_chain_prod, + DBRUN(BNX_VERBOSE_RECV, bnx_dump_rx_mbuf_chain(sc, debug_chain_prod, map->dm_nsegs)); return (map->dm_nsegs); @@ -3968,7 +3968,7 @@ bnx_fill_rx_chain(struct bnx_softc *sc) slots = if_rxr_get(&sc->rx_ring, sc->max_rx_bd); while (slots > 0) { chain_prod = RX_CHAIN_IDX(prod); - + used = bnx_get_buf(sc, &prod, &chain_prod, &prod_bseq); if (used == 0) { /* Bail out if we can't add an mbuf to the chain. */ @@ -4262,8 +4262,8 @@ bnx_rx_intr(struct bnx_softc *sc) bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, BUS_SPACE_BARRIER_READ); - /* - * Scan through the receive chain as long + /* + * Scan through the receive chain as long * as there is work to do. */ while (sw_cons != hw_cons) { @@ -4284,8 +4284,8 @@ bnx_rx_intr(struct bnx_softc *sc) /* Get the used rx_bd. */ rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)][RX_IDX(sw_chain_cons)]; if_rxr_put(&sc->rx_ring, 1); - - DBRUN(BNX_VERBOSE_RECV, printf("%s(): ", __FUNCTION__); + + DBRUN(BNX_VERBOSE_RECV, printf("%s(): ", __FUNCTION__); bnx_dump_rxbd(sc, sw_chain_cons, rxbd)); /* The mbuf is stored with the last rx_bd entry of a packet. */ @@ -4315,12 +4315,12 @@ bnx_rx_intr(struct bnx_softc *sc) sc->rx_mbuf_ptr[sw_chain_cons] = NULL; /* - * Frames received on the NetXteme II are prepended + * Frames received on the NetXteme II are prepended * with the l2_fhdr structure which provides status * information about the received frame (including * VLAN tags and checksum info) and are also * automatically adjusted to align the IP header - * (i.e. two null bytes are inserted before the + * (i.e. two null bytes are inserted before the * Ethernet header). */ l2fhdr = mtod(m, struct l2_fhdr *); @@ -4345,9 +4345,9 @@ bnx_rx_intr(struct bnx_softc *sc) len -= ETHER_CRC_LEN; /* Check the received frame for errors. */ - if (status & (L2_FHDR_ERRORS_BAD_CRC | + if (status & (L2_FHDR_ERRORS_BAD_CRC | L2_FHDR_ERRORS_PHY_DECODE | - L2_FHDR_ERRORS_ALIGNMENT | + L2_FHDR_ERRORS_ALIGNMENT | L2_FHDR_ERRORS_TOO_SHORT | L2_FHDR_ERRORS_GIANT_FRAME)) { /* Log the error and release the mbuf. */ @@ -4371,7 +4371,7 @@ bnx_rx_intr(struct bnx_softc *sc) struct ether_header *eh; eh = mtod(m, struct ether_header *); printf("%s: to: %6D, from: %6D, type: 0x%04X\n", - __FUNCTION__, eh->ether_dhost, ":", + __FUNCTION__, eh->ether_dhost, ":", eh->ether_shost, ":", htons(eh->ether_type))); /* Validate the checksum. */ @@ -4384,7 +4384,7 @@ bnx_rx_intr(struct bnx_softc *sc) m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; else - DBPRINT(sc, BNX_WARN_SEND, + DBPRINT(sc, BNX_WARN_SEND, "%s(): Invalid IP checksum " "= 0x%04X!\n", __FUNCTION__, @@ -4403,7 +4403,7 @@ bnx_rx_intr(struct bnx_softc *sc) M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK; } else { - DBPRINT(sc, BNX_WARN_SEND, + DBPRINT(sc, BNX_WARN_SEND, "%s(): Invalid TCP/UDP " "checksum = 0x%04X!\n", __FUNCTION__, @@ -4430,7 +4430,7 @@ bnx_rx_intr(struct bnx_softc *sc) m_freem(m); m = NULL; goto bnx_rx_int_next_rx; -#endif +#endif } bnx_rx_int_next_rx: @@ -4463,7 +4463,7 @@ bnx_rx_int_next_rx: /* Prevent speculative reads from getting ahead of * the status block. */ - bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, + bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, BUS_SPACE_BARRIER_READ); } @@ -4513,7 +4513,7 @@ bnx_tx_intr(struct bnx_softc *sc) sw_tx_cons = sc->tx_cons; /* Prevent speculative reads from getting ahead of the status block. */ - bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, + bus_space_barrier(sc->bnx_btag, sc->bnx_bhandle, 0, 0, BUS_SPACE_BARRIER_READ); /* Cycle through any completed TX chain page entries. */ @@ -4535,9 +4535,9 @@ bnx_tx_intr(struct bnx_softc *sc) DBRUNIF(1, txbd = &sc->tx_bd_chain [TX_PAGE(sw_tx_chain_cons)][TX_IDX(sw_tx_chain_cons)]); - + DBRUNIF((txbd == NULL), - printf("%s: Unexpected NULL tx_bd[0x%04X]!\n", + printf("%s: Unexpected NULL tx_bd[0x%04X]!\n", sw_tx_chain_cons); bnx_breakpoint(sc)); @@ -4566,7 +4566,7 @@ bnx_tx_intr(struct bnx_softc *sc) m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]); sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL; } - + freed++; sw_tx_cons = NEXT_TX_BD(sw_tx_cons); } @@ -4610,7 +4610,7 @@ bnx_enable_intr(struct bnx_softc *sc) REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | BNX_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx); - REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | + REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx); val = REG_RD(sc, BNX_HC_COMMAND); @@ -4847,7 +4847,7 @@ bnx_tx_encap(struct bnx_softc *sc, struct mbuf *m, int *used) DBRUNIF(1, sc->tx_mbuf_alloc++); - DBRUN(BNX_VERBOSE_SEND, bnx_dump_tx_mbuf_chain(sc, chain_prod, + DBRUN(BNX_VERBOSE_SEND, bnx_dump_tx_mbuf_chain(sc, chain_prod, map->dm_nsegs)); bus_dmamap_sync(sc->bnx_dmatag, map, 0, map->dm_mapsize, @@ -5042,7 +5042,7 @@ bnx_watchdog(struct ifnet *ifp) * If we are in this routine because of pause frames, then * don't reset the hardware. */ - if (REG_RD(sc, BNX_EMAC_TX_STATUS) & BNX_EMAC_TX_STATUS_XOFFED) + if (REG_RD(sc, BNX_EMAC_TX_STATUS) & BNX_EMAC_TX_STATUS_XOFFED) return; printf("%s: Watchdog timeout occurred, resetting!\n", @@ -5090,7 +5090,7 @@ bnx_intr(void *xsc) * interrupt then there's nothing to do. */ status_idx = sc->status_block->status_idx; - if (status_idx != sc->last_status_idx || + if (status_idx != sc->last_status_idx || !ISSET(REG_RD(sc, BNX_PCICFG_MISC_STATUS), BNX_PCICFG_MISC_STATUS_INTA_VALUE)) { rv = 1; @@ -5117,7 +5117,7 @@ bnx_intr(void *xsc) /* If any other attention is asserted then the chip is toast. */ if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) != - (sc->status_block->status_attn_bits_ack & + (sc->status_block->status_attn_bits_ack & ~STATUS_ATTN_BITS_LINK_STATE))) { KERNEL_LOCK(); DBRUN(1, sc->unexpected_attentions++); @@ -5237,7 +5237,7 @@ bnx_iff(struct bnx_softc *sc) /* Only make changes if the receive mode has actually changed. */ if (rx_mode != sc->rx_mode) { - DBPRINT(sc, BNX_VERBOSE, "Enabling new receive mode: 0x%08X\n", + DBPRINT(sc, BNX_VERBOSE, "Enabling new receive mode: 0x%08X\n", rx_mode); sc->rx_mode = rx_mode; @@ -5267,7 +5267,7 @@ bnx_stats_update(struct bnx_softc *sc) stats = (struct statistics_block *)sc->stats_block; - /* + /* * Update the interface statistics from the * hardware statistics. */ @@ -5284,10 +5284,10 @@ bnx_stats_update(struct bnx_softc *sc) (u_long)stats->stat_Dot3StatsExcessiveCollisions + (u_long)stats->stat_Dot3StatsLateCollisions; - /* - * Certain controllers don't report + /* + * Certain controllers don't report * carrier sense errors correctly. - * See errata E11_5708CA0_1165. + * See errata E11_5708CA0_1165. */ if (!(BNX_CHIP_NUM(sc) == BNX_CHIP_NUM_5706) && !(BNX_CHIP_ID(sc) == BNX_CHIP_ID_5708_A0)) @@ -5301,7 +5301,7 @@ bnx_stats_update(struct bnx_softc *sc) (u_int64_t) stats->stat_IfHCInOctets_lo; sc->stat_IfHCInBadOctets = - ((u_int64_t) stats->stat_IfHCInBadOctets_hi << 32) + + ((u_int64_t) stats->stat_IfHCInBadOctets_hi << 32) + (u_int64_t) stats->stat_IfHCInBadOctets_lo; sc->stat_IfHCOutOctets = @@ -5517,7 +5517,7 @@ bnx_dump_mbuf(struct bnx_softc *sc, struct mbuf *m) } while (mp) { - printf("mbuf: vaddr = %p, m_len = %d, m_flags = ", + printf("mbuf: vaddr = %p, m_len = %d, m_flags = ", mp, mp->m_len); if (mp->m_flags & M_EXT) @@ -5527,7 +5527,7 @@ bnx_dump_mbuf(struct bnx_softc *sc, struct mbuf *m) printf("\n"); if (mp->m_flags & M_EXT) - printf("- m_ext: vaddr = %p, ext_size = 0x%04X\n", + printf("- m_ext: vaddr = %p, ext_size = 0x%04X\n", mp, mp->m_ext.ext_size); mp = mp->m_next; @@ -5604,7 +5604,7 @@ bnx_dump_txbd(struct bnx_softc *sc, int idx, struct tx_bd *txbd) else /* Normal tx_bd entry. */ BNX_PRINTF(sc, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " - "0x%08X, vlan tag = 0x%4X, flags = 0x%08X\n", idx, + "0x%08X, vlan tag = 0x%4X, flags = 0x%08X\n", idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo, txbd->tx_bd_mss_nbytes, txbd->tx_bd_vlan_tag, txbd->tx_bd_flags); @@ -5624,7 +5624,7 @@ bnx_dump_rxbd(struct bnx_softc *sc, int idx, struct rx_bd *rxbd) else /* Normal tx_bd entry. */ BNX_PRINTF(sc, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = " - "0x%08X, flags = 0x%08X\n", idx, + "0x%08X, flags = 0x%08X\n", idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo, rxbd->rx_bd_len, rxbd->rx_bd_flags); } @@ -5753,61 +5753,61 @@ bnx_dump_status_block(struct bnx_softc *sc) BNX_PRINTF(sc, "status_idx = 0x%04X\n", sblk->status_idx); /* Theses indices are not used for normal L2 drivers. */ - if (sblk->status_rx_quick_consumer_index1 || + if (sblk->status_rx_quick_consumer_index1 || sblk->status_tx_quick_consumer_index1) BNX_PRINTF(sc, "rx_cons1 = 0x%08X, tx_cons1 = 0x%08X\n", sblk->status_rx_quick_consumer_index1, sblk->status_tx_quick_consumer_index1); - if (sblk->status_rx_quick_consumer_index2 || + if (sblk->status_rx_quick_consumer_index2 || sblk->status_tx_quick_consumer_index2) BNX_PRINTF(sc, "rx_cons2 = 0x%08X, tx_cons2 = 0x%08X\n", sblk->status_rx_quick_consumer_index2, sblk->status_tx_quick_consumer_index2); - if (sblk->status_rx_quick_consumer_index3 || + if (sblk->status_rx_quick_consumer_index3 || sblk->status_tx_quick_consumer_index3) BNX_PRINTF(sc, "rx_cons3 = 0x%08X, tx_cons3 = 0x%08X\n", sblk->status_rx_quick_consumer_index3, sblk->status_tx_quick_consumer_index3); - if (sblk->status_rx_quick_consumer_index4 || + if (sblk->status_rx_quick_consumer_index4 || sblk->status_rx_quick_consumer_index5) BNX_PRINTF(sc, "rx_cons4 = 0x%08X, rx_cons5 = 0x%08X\n", sblk->status_rx_quick_consumer_index4, sblk->status_rx_quick_consumer_index5); - if (sblk->status_rx_quick_consumer_index6 || + if (sblk->status_rx_quick_consumer_index6 || sblk->status_rx_quick_consumer_index7) BNX_PRINTF(sc, "rx_cons6 = 0x%08X, rx_cons7 = 0x%08X\n", sblk->status_rx_quick_consumer_index6, sblk->status_rx_quick_consumer_index7); - if (sblk->status_rx_quick_consumer_index8 || + if (sblk->status_rx_quick_consumer_index8 || sblk->status_rx_quick_consumer_index9) BNX_PRINTF(sc, "rx_cons8 = 0x%08X, rx_cons9 = 0x%08X\n", sblk->status_rx_quick_consumer_index8, sblk->status_rx_quick_consumer_index9); - if (sblk->status_rx_quick_consumer_index10 || + if (sblk->status_rx_quick_consumer_index10 || sblk->status_rx_quick_consumer_index11) BNX_PRINTF(sc, "rx_cons10 = 0x%08X, rx_cons11 = 0x%08X\n", sblk->status_rx_quick_consumer_index10, sblk->status_rx_quick_consumer_index11); - if (sblk->status_rx_quick_consumer_index12 || + if (sblk->status_rx_quick_consumer_index12 || sblk->status_rx_quick_consumer_index13) BNX_PRINTF(sc, "rx_cons12 = 0x%08X, rx_cons13 = 0x%08X\n", sblk->status_rx_quick_consumer_index12, sblk->status_rx_quick_consumer_index13); - if (sblk->status_rx_quick_consumer_index14 || + if (sblk->status_rx_quick_consumer_index14 || sblk->status_rx_quick_consumer_index15) BNX_PRINTF(sc, "rx_cons14 = 0x%08X, rx_cons15 = 0x%08X\n", sblk->status_rx_quick_consumer_index14, sblk->status_rx_quick_consumer_index15); - if (sblk->status_completion_producer_index || + if (sblk->status_completion_producer_index || sblk->status_cmd_consumer_index) BNX_PRINTF(sc, "com_prod = 0x%08X, cmd_cons = 0x%08X\n", sblk->status_completion_producer_index, @@ -5864,7 +5864,7 @@ bnx_dump_stats_block(struct bnx_softc *sc) if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) BNX_PRINTF(sc, "0x%08X : " - "emac_tx_stat_dot3statsinternalmactransmiterrors\n", + "emac_tx_stat_dot3statsinternalmactransmiterrors\n", sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors); if (sblk->stat_Dot3StatsCarrierSenseErrors) @@ -5886,7 +5886,7 @@ bnx_dump_stats_block(struct bnx_softc *sc) if (sblk->stat_Dot3StatsMultipleCollisionFrames) BNX_PRINTF(sc, "0x%08X : Dot3StatsMultipleCollisionFrames\n", sblk->stat_Dot3StatsMultipleCollisionFrames); - + if (sblk->stat_Dot3StatsDeferredTransmissions) BNX_PRINTF(sc, "0x%08X : Dot3StatsDeferredTransmissions\n", sblk->stat_Dot3StatsDeferredTransmissions); @@ -5903,7 +5903,7 @@ bnx_dump_stats_block(struct bnx_softc *sc) BNX_PRINTF(sc, "0x%08X : EtherStatsCollisions\n", sblk->stat_EtherStatsCollisions); - if (sblk->stat_EtherStatsFragments) + if (sblk->stat_EtherStatsFragments) BNX_PRINTF(sc, "0x%08X : EtherStatsFragments\n", sblk->stat_EtherStatsFragments); @@ -6087,7 +6087,7 @@ bnx_dump_driver_state(struct bnx_softc *sc) BNX_PRINTF(sc, " 0x%08X - (sc->interrupts_generated) h/w intrs\n", sc->interrupts_generated); - + BNX_PRINTF(sc, " 0x%08X - (sc->rx_interrupts) rx interrupts handled\n", sc->rx_interrupts); @@ -6195,12 +6195,12 @@ bnx_dump_hw_state(struct bnx_softc *sc) val1 = REG_RD(sc, BNX_HC_STATUS); BNX_PRINTF(sc, "0x%08X : (0x%04X) hc_status\n", val1, BNX_HC_STATUS); - BNX_PRINTF(sc, + BNX_PRINTF(sc, "----------------------------" "----------------" "----------------------------\n"); - BNX_PRINTF(sc, + BNX_PRINTF(sc, "----------------------------" " Register Dump " "----------------------------\n"); @@ -6210,7 +6210,7 @@ bnx_dump_hw_state(struct bnx_softc *sc) i, REG_RD(sc, i), REG_RD(sc, i + 0x4), REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC)); - BNX_PRINTF(sc, + BNX_PRINTF(sc, "----------------------------" "----------------" "----------------------------\n"); diff --git a/sys/dev/pci/if_bnxreg.h b/sys/dev/pci/if_bnxreg.h index 7b3ca3242..e09345caa 100644 --- a/sys/dev/pci/if_bnxreg.h +++ b/sys/dev/pci/if_bnxreg.h @@ -350,19 +350,19 @@ struct flash_spec { /* information which can be accessed by the driver. */ /****************************************************************************/ -/* +/* * This value (in milliseconds) determines the frequency of the driver * issuing the PULSE message code. The firmware monitors this periodic - * pulse to determine when to switch to an OS-absent mode. + * pulse to determine when to switch to an OS-absent mode. */ #define DRV_PULSE_PERIOD_MS 250 -/* +/* * This value (in milliseconds) determines how long the driver should * wait for an acknowledgement from the firmware before timing out. Once * the firmware has timed out, the driver will assume there is no firmware * running and there won't be any firmware-driver synchronization during a - * driver reset. + * driver reset. */ #define FW_ACK_TIME_OUT_MS 1000 @@ -4579,7 +4579,7 @@ struct l2_fhdr { #define DMA_WRITE_CHANS 3 /* Use the natural page size of the host CPU. */ -#define BCM_PAGE_BITS PAGE_SHIFT +#define BCM_PAGE_BITS PAGE_SHIFT #define BCM_PAGE_SIZE PAGE_SIZE #define TX_PAGES 2 @@ -4895,7 +4895,7 @@ struct bnx_softc { int ctx_rsegs[4]; bus_dmamap_t ctx_map[4]; void *ctx_block[4]; - + /* Driver maintained status block values. */ u_int16_t last_status_idx; @@ -5049,7 +5049,7 @@ struct bnx_firmware_header { int bnx_RXP_FwBssLen; u_int32_t bnx_RXP_FwSbssAddr; int bnx_RXP_FwSbssLen; - + int bnx_TPAT_FwReleaseMajor; int bnx_TPAT_FwReleaseMinor; int bnx_TPAT_FwReleaseFix; @@ -5085,13 +5085,13 @@ struct bnx_firmware_header { * * bnx_COM_FwText, bnx_COM_FwData, bnx_COM_FwRodata, * bnx_COM_FwBss, bnx_COM_FwSbss, - * + * * bnx_RXP_FwText, bnx_RXP_FwData, bnx_RXP_FwRodata, * bnx_RXP_FwBss, bnx_RXP_FwSbss, - * + * * bnx_TPAT_FwText, bnx_TPAT_FwData, bnx_TPAT_FwRodata, * bnx_TPAT_FwBss, bnx_TPAT_FwSbss, - * + * * bnx_TXP_FwText, bnx_TXP_FwData, bnx_TXP_FwRodata, * bnx_TXP_FwBss, bnx_TXP_FwSbss, */ diff --git a/sys/dev/pci/if_bnxt.c b/sys/dev/pci/if_bnxt.c index 4eb58b16c..dcb95b7f9 100644 --- a/sys/dev/pci/if_bnxt.c +++ b/sys/dev/pci/if_bnxt.c @@ -2712,7 +2712,7 @@ fail: } -int +int bnxt_hwrm_func_qcfg(struct bnxt_softc *softc) { struct hwrm_func_qcfg_input req = {0}; @@ -3214,7 +3214,7 @@ int bnxt_cfg_async_cr(struct bnxt_softc *softc, struct bnxt_cp_ring *cpr) { int rc = 0; - + if (1 /* BNXT_PF(softc) */) { struct hwrm_func_cfg_input req = {0}; @@ -3273,12 +3273,12 @@ bnxt_hwrm_vnic_tpa_cfg(struct bnxt_softc *softc) HWRM_VNIC_TPA_CFG_INPUT_FLAGS_ENCAP_TPA | HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_ECN | HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_WITH_SAME_GRE_SEQ; - + if (softc->hw_lro.is_mode_gro) flags |= HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO; else flags |= HWRM_VNIC_TPA_CFG_INPUT_FLAGS_RSC_WND_UPDATE; - + req.flags = htole32(flags); req.enables = htole32(HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_SEGS | @@ -3494,7 +3494,7 @@ bnxt_get_sffpage(struct bnxt_softc *softc, struct if_sffpage *sff) req.page_offset = htole16(offset); req.data_length = sizeof(out->data); req.enables = htole32(HWRM_PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET); - + if (hwrm_send_message(softc, &req, sizeof(req))) { printf("%s: failed to read i2c data\n", DEVNAME(softc)); return 1; diff --git a/sys/dev/pci/if_cas.c b/sys/dev/pci/if_cas.c index 3de0a376f..6c9f41c21 100644 --- a/sys/dev/pci/if_cas.c +++ b/sys/dev/pci/if_cas.c @@ -253,14 +253,14 @@ next: desc = buf + sizeof(*vpd); - /* + /* * ...which is an instance property... */ if (desc[0] != 'I') continue; desc += 3; - /* + /* * ...that's a byte array with the proper * length for a MAC address... */ @@ -274,7 +274,7 @@ next: if (strcmp(desc, "local-mac-address") != 0) continue; desc += strlen("local-mac-address") + 1; - + bcopy(desc, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN); sc->sc_arpcom.ac_enaddr[5] += pa->pa_device; rv = 0; @@ -521,7 +521,7 @@ cas_config(struct cas_softc *sc) child = LIST_FIRST(&mii->mii_phys); if (child == NULL && sc->sc_mif_config & (CAS_MIF_CONFIG_MDI0|CAS_MIF_CONFIG_MDI1)) { - /* + /* * Try the external PCS SERDES if we didn't find any * MII devices. */ @@ -1148,11 +1148,11 @@ cas_init_regs(struct cas_softc *sc) /* * Set the station address. */ - bus_space_write_4(t, h, CAS_MAC_ADDR0, + bus_space_write_4(t, h, CAS_MAC_ADDR0, (sc->sc_arpcom.ac_enaddr[4]<<8) | sc->sc_arpcom.ac_enaddr[5]); - bus_space_write_4(t, h, CAS_MAC_ADDR1, + bus_space_write_4(t, h, CAS_MAC_ADDR1, (sc->sc_arpcom.ac_enaddr[2]<<8) | sc->sc_arpcom.ac_enaddr[3]); - bus_space_write_4(t, h, CAS_MAC_ADDR2, + bus_space_write_4(t, h, CAS_MAC_ADDR2, (sc->sc_arpcom.ac_enaddr[0]<<8) | sc->sc_arpcom.ac_enaddr[1]); } diff --git a/sys/dev/pci/if_dc_pci.c b/sys/dev/pci/if_dc_pci.c index 771154ccd..9ac64842b 100644 --- a/sys/dev/pci/if_dc_pci.c +++ b/sys/dev/pci/if_dc_pci.c @@ -478,16 +478,16 @@ dc_pci_attach(struct device *parent, struct device *self, void *aux) command = pci_conf_read(pc, pa->pa_tag, DC_PCI_CFDD); command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); switch ((command >> 8) & 0xff) { - case 3: + case 3: sc->dc_srm_media = IFM_10_T; break; - case 4: + case 4: sc->dc_srm_media = IFM_10_T | IFM_FDX; break; - case 5: + case 5: sc->dc_srm_media = IFM_100_TX; break; - case 6: + case 6: sc->dc_srm_media = IFM_100_TX | IFM_FDX; break; } @@ -513,7 +513,7 @@ dc_pci_detach(struct device *self, int flags) struct dc_softc *sc = &psc->psc_softc; if (sc->sc_ih != NULL) - pci_intr_disestablish(psc->psc_pc, sc->sc_ih); + pci_intr_disestablish(psc->psc_pc, sc->sc_ih); dc_detach(sc); bus_space_unmap(sc->dc_btag, sc->dc_bhandle, psc->psc_mapsize); diff --git a/sys/dev/pci/if_devar.h b/sys/dev/pci/if_devar.h index 0ecadf3bf..bd0a34e4a 100644 --- a/sys/dev/pci/if_devar.h +++ b/sys/dev/pci/if_devar.h @@ -848,7 +848,7 @@ TULIP_PERFREAD( #define TULIP_PERFDIFF(s, f) ((unsigned int) ((f) - (s))) #endif #else -#define TULIP_PERFSTART(name) +#define TULIP_PERFSTART(name) #define TULIP_PERFEND(name) do { } while (0) #define TULIP_PERFMERGE(s,n) do { } while (0) #endif /* TULIP_PERFSTATS */ diff --git a/sys/dev/pci/if_em.c b/sys/dev/pci/if_em.c index e29b12e0b..84003058e 100644 --- a/sys/dev/pci/if_em.c +++ b/sys/dev/pci/if_em.c @@ -377,14 +377,14 @@ em_defer_attach(struct device *self) return; } - + sc->hw.gcu = gcu; - - em_attach_miibus(self); - em_setup_interface(sc); + em_attach_miibus(self); - em_setup_link(&sc->hw); + em_setup_interface(sc); + + em_setup_link(&sc->hw); em_update_link_status(sc); } @@ -398,13 +398,13 @@ em_defer_attach(struct device *self) * *********************************************************************/ -void +void em_attach(struct device *parent, struct device *self, void *aux) { struct pci_attach_args *pa = aux; struct em_softc *sc; int defer = 0; - + INIT_DEBUGOUT("em_attach: begin"); sc = (struct em_softc *)self; @@ -455,7 +455,7 @@ em_attach(struct device *parent, struct device *self, void *aux) /* * This controls when hardware reports transmit completion - * status. + * status. */ sc->hw.report_tx_early = 1; @@ -521,7 +521,7 @@ em_attach(struct device *parent, struct device *self, void *aux) MAX_JUMBO_FRAME_SIZE; } - sc->hw.min_frame_size = + sc->hw.min_frame_size = ETHER_MIN_LEN + ETHER_CRC_LEN; if (em_allocate_desc_rings(sc) != 0) { @@ -703,7 +703,7 @@ em_start(struct ifqueue *ifq) bus_dmamap_sync(sc->sc_dmat, que->tx.sc_tx_dma.dma_map, 0, que->tx.sc_tx_dma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); - /* + /* * Advance the Transmit Descriptor Tail (Tdt), * this tells the E1000 that this frame is * available to transmit. @@ -933,7 +933,7 @@ em_init(void *arg) /* Initialize the hardware */ if (em_hardware_init(sc)) { - printf("%s: Unable to initialize the hardware\n", + printf("%s: Unable to initialize the hardware\n", DEVNAME(sc)); splx(s); return; @@ -946,7 +946,7 @@ em_init(void *arg) /* Prepare transmit descriptors and buffers */ if (em_setup_transmit_structures(sc)) { - printf("%s: Could not setup transmit structures\n", + printf("%s: Could not setup transmit structures\n", DEVNAME(sc)); em_stop(sc, 0); splx(s); @@ -956,7 +956,7 @@ em_init(void *arg) /* Prepare receive descriptors and buffers */ if (em_setup_receive_structures(sc)) { - printf("%s: Could not setup receive structures\n", + printf("%s: Could not setup receive structures\n", DEVNAME(sc)); em_stop(sc, 0); splx(s); @@ -995,7 +995,7 @@ em_init(void *arg) * Interrupt Service routine * **********************************************************************/ -int +int em_intr(void *arg) { struct em_softc *sc = arg; @@ -1297,7 +1297,7 @@ em_encap(struct em_queue *que, struct mbuf *m) que->tx.sc_tx_desc_head = head; - /* + /* * Last Descriptor of Packet * needs End Of Packet (EOP) * and Report Status (RS) @@ -1563,7 +1563,7 @@ em_update_link_status(struct em_softc *sc) /********************************************************************* * * This routine disables all traffic on the adapter by issuing a - * global reset on the MAC and deallocates TX/RX buffers. + * global reset on the MAC and deallocates TX/RX buffers. * **********************************************************************/ @@ -1649,7 +1649,7 @@ em_legacy_irq_quirk_spt(struct em_softc *sc) /* Legacy interrupt: SPT needs a quirk. */ if (sc->hw.mac_type != em_pch_spt && sc->hw.mac_type != em_pch_cnp && - sc->hw.mac_type != em_pch_tgp && sc->hw.mac_type != em_pch_adp) + sc->hw.mac_type != em_pch_tgp && sc->hw.mac_type != em_pch_adp) return; if (sc->legacy_irq == 0) return; @@ -1768,8 +1768,8 @@ em_allocate_pci_resources(struct em_softc *sc) if(sc->hw.mac_type == em_icp_xxxx) { int offset; pcireg_t val; - - if (!pci_get_capability(sc->osdep.em_pa.pa_pc, + + if (!pci_get_capability(sc->osdep.em_pa.pa_pc, sc->osdep.em_pa.pa_tag, PCI_CAP_ID_ST, &offset, &val)) { return (0); } @@ -1898,7 +1898,7 @@ em_hardware_init(struct em_softc *sc) em_legacy_irq_quirk_spt(sc); /* - * These parameters control the automatic generation (Tx) and + * These parameters control the automatic generation (Tx) and * response (Rx) to Ethernet PAUSE frames. * - High water mark should allow for at least two frames to be * received after sending an XOFF. @@ -1979,7 +1979,7 @@ em_setup_interface(struct em_softc *sc) ifp->if_capabilities |= IFCAP_CSUM_TCPv6 | IFCAP_CSUM_UDPv6; } - /* + /* * Specify the media types supported by this adapter and register * callbacks to update media and link information */ @@ -1989,20 +1989,20 @@ em_setup_interface(struct em_softc *sc) sc->hw.media_type == em_media_type_internal_serdes) { if (sc->hw.mac_type == em_82545) fiber_type = IFM_1000_LX; - ifmedia_add(&sc->media, IFM_ETHER | fiber_type | IFM_FDX, + ifmedia_add(&sc->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL); - ifmedia_add(&sc->media, IFM_ETHER | fiber_type, + ifmedia_add(&sc->media, IFM_ETHER | fiber_type, 0, NULL); } else { ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL); - ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, + ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); - ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, + ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL); - ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, + ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); if (sc->hw.phy_type != em_phy_ife) { - ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX, + ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_T, 0, NULL); } @@ -2066,13 +2066,13 @@ em_activate(struct device *self, int act) * * Workaround for SmartSpeed on 82541 and 82547 controllers * - **********************************************************************/ + **********************************************************************/ void em_smartspeed(struct em_softc *sc) { uint16_t phy_tmp; - - if (sc->link_active || (sc->hw.phy_type != em_phy_igp) || + + if (sc->link_active || (sc->hw.phy_type != em_phy_igp) || !sc->hw.autoneg || !(sc->hw.autoneg_advertised & ADVERTISE_1000_FULL)) return; @@ -2095,7 +2095,7 @@ em_smartspeed(struct em_softc *sc) !em_phy_setup_autoneg(&sc->hw) && !em_read_phy_reg(&sc->hw, PHY_CTRL, &phy_tmp)) { - phy_tmp |= (MII_CR_AUTO_NEG_EN | + phy_tmp |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); em_write_phy_reg(&sc->hw, PHY_CTRL, phy_tmp); @@ -2190,7 +2190,7 @@ em_allocate_transmit_structures(struct em_softc *sc) que->tx.sc_tx_pkts_ring = mallocarray(sc->sc_tx_slots, sizeof(*que->tx.sc_tx_pkts_ring), M_DEVBUF, M_NOWAIT | M_ZERO); if (que->tx.sc_tx_pkts_ring == NULL) { - printf("%s: Unable to allocate tx_buffer memory\n", + printf("%s: Unable to allocate tx_buffer memory\n", DEVNAME(sc)); return (ENOMEM); } @@ -2201,7 +2201,7 @@ em_allocate_transmit_structures(struct em_softc *sc) /********************************************************************* * - * Allocate and initialize transmit structures. + * Allocate and initialize transmit structures. * **********************************************************************/ int @@ -2407,7 +2407,7 @@ em_tx_ctx_setup(struct em_queue *que, struct mbuf *mp, u_int head, *olinfo_status = 0; *cmd_type_len = 0; TD = (struct e1000_adv_tx_context_desc *)&que->tx.sc_tx_desc_ring[head]; - + #if NVLAN > 0 if (ISSET(mp->m_flags, M_VLANTAG)) { uint32_t vtag = mp->m_pkthdr.ether_vtag; @@ -2513,22 +2513,22 @@ em_transmit_checksum_setup(struct em_queue *que, struct mbuf *mp, u_int head, TXD = (struct em_context_desc *)&que->tx.sc_tx_desc_ring[head]; TXD->lower_setup.ip_fields.ipcss = ETHER_HDR_LEN; - TXD->lower_setup.ip_fields.ipcso = + TXD->lower_setup.ip_fields.ipcso = ETHER_HDR_LEN + offsetof(struct ip, ip_sum); - TXD->lower_setup.ip_fields.ipcse = + TXD->lower_setup.ip_fields.ipcse = htole16(ETHER_HDR_LEN + sizeof(struct ip) - 1); - TXD->upper_setup.tcp_fields.tucss = + TXD->upper_setup.tcp_fields.tucss = ETHER_HDR_LEN + sizeof(struct ip); TXD->upper_setup.tcp_fields.tucse = htole16(0); if (que->tx.active_checksum_context == OFFLOAD_TCP_IP) { - TXD->upper_setup.tcp_fields.tucso = - ETHER_HDR_LEN + sizeof(struct ip) + + TXD->upper_setup.tcp_fields.tucso = + ETHER_HDR_LEN + sizeof(struct ip) + offsetof(struct tcphdr, th_sum); } else if (que->tx.active_checksum_context == OFFLOAD_UDP_IP) { - TXD->upper_setup.tcp_fields.tucso = - ETHER_HDR_LEN + sizeof(struct ip) + + TXD->upper_setup.tcp_fields.tucso = + ETHER_HDR_LEN + sizeof(struct ip) + offsetof(struct udphdr, uh_sum); } @@ -2542,7 +2542,7 @@ em_transmit_checksum_setup(struct em_queue *que, struct mbuf *mp, u_int head, * * Examine each tx_buffer in the used queue. If the hardware is done * processing the packet then free associated resources. The - * tx_buffer is put back on the free queue. + * tx_buffer is put back on the free queue. * **********************************************************************/ void @@ -2652,9 +2652,9 @@ em_get_buf(struct em_queue *que, int i) /********************************************************************* * - * Allocate memory for rx_buffer structures. Since we use one - * rx_buffer per received packet, the maximum number of rx_buffer's - * that we'll need is equal to the number of receive descriptors + * Allocate memory for rx_buffer structures. Since we use one + * rx_buffer per received packet, the maximum number of rx_buffer's + * that we'll need is equal to the number of receive descriptors * that we've allocated. * **********************************************************************/ @@ -2706,7 +2706,7 @@ fail: /********************************************************************* * * Allocate and initialize receive structures. - * + * **********************************************************************/ int em_setup_receive_structures(struct em_softc *sc) @@ -2742,7 +2742,7 @@ em_setup_receive_structures(struct em_softc *sc) /********************************************************************* * * Enable receive unit. - * + * **********************************************************************/ void em_initialize_receive_unit(struct em_softc *sc) @@ -2759,7 +2759,7 @@ em_initialize_receive_unit(struct em_softc *sc) E1000_WRITE_REG(&sc->hw, RCTL, 0); /* Set the Receive Delay Timer Register */ - E1000_WRITE_REG(&sc->hw, RDTR, + E1000_WRITE_REG(&sc->hw, RDTR, sc->rx_int_delay | E1000_RDT_FPDB); if (sc->hw.mac_type >= em_82540) { @@ -2794,7 +2794,7 @@ em_initialize_receive_unit(struct em_softc *sc) break; case EM_RXBUFFER_4096: reg_rctl |= E1000_RCTL_SZ_4096|E1000_RCTL_BSEX|E1000_RCTL_LPE; - break; + break; case EM_RXBUFFER_8192: reg_rctl |= E1000_RCTL_SZ_8192|E1000_RCTL_BSEX|E1000_RCTL_LPE; break; @@ -3123,7 +3123,7 @@ em_rxeof(struct em_queue *que) /********************************************************************* * - * Verify that the hardware indicated that the checksum is valid. + * Verify that the hardware indicated that the checksum is valid. * Inform the stack about the status of checksum so that stack * doesn't spend time verifying the checksum. * @@ -3151,7 +3151,7 @@ em_receive_checksum(struct em_softc *sc, struct em_rx_desc *rx_desc, } if (rx_desc->status & E1000_RXD_STAT_TCPCS) { - /* Did it pass? */ + /* Did it pass? */ if (!(rx_desc->errors & E1000_RXD_ERR_TCPE)) mp->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK; @@ -3162,7 +3162,7 @@ em_receive_checksum(struct em_softc *sc, struct em_rx_desc *rx_desc, * This turns on the hardware offload of the VLAN * tag insertion and strip */ -void +void em_enable_hw_vlans(struct em_softc *sc) { uint32_t ctrl; @@ -3681,7 +3681,7 @@ static const struct em_counter em_counters[em_stat_count] = { /********************************************************************** * - * Update the board statistics counters. + * Update the board statistics counters. * **********************************************************************/ int @@ -3714,9 +3714,9 @@ em_kstat_read(struct kstat *ks) kstat_kv_u64(&kvs[em_stat_tncrs]) += E1000_READ_REG(hw, TNCRS); #if 0 - sc->stats.tsctc += + sc->stats.tsctc += E1000_READ_REG(hw, TSCTC); - sc->stats.tsctfc += + sc->stats.tsctfc += E1000_READ_REG(hw, TSCTFC); #endif } @@ -3821,7 +3821,7 @@ em_tbi_adjust_stats(struct em_softc *sc, uint32_t frame_len, uint8_t *mac_addr) if (ETHER_IS_BROADCAST(mac_addr)) { /* Broadcast packet */ kstat_kv_u64(&kvs[em_stat_bprc])++; - } else if (ETHER_IS_MULTICAST(mac_addr)) { + } else if (ETHER_IS_MULTICAST(mac_addr)) { /* Multicast packet */ kstat_kv_u64(&kvs[em_stat_mprc])++; } diff --git a/sys/dev/pci/if_em_hw.c b/sys/dev/pci/if_em_hw.c index 5cd58ebf1..d0c231bc8 100644 --- a/sys/dev/pci/if_em_hw.c +++ b/sys/dev/pci/if_em_hw.c @@ -100,7 +100,7 @@ static int em_disable_ulp_lpt_lp(struct em_hw *hw, bool force); static boolean_t em_is_onboard_nvm_eeprom(struct em_hw *); static int32_t em_kumeran_lock_loss_workaround(struct em_hw *); static int32_t em_mng_enable_host_if(struct em_hw *); -static int32_t em_read_eeprom_eerd(struct em_hw *, uint16_t, uint16_t, +static int32_t em_read_eeprom_eerd(struct em_hw *, uint16_t, uint16_t, uint16_t *); static int32_t em_write_eeprom_eewr(struct em_hw *, uint16_t, uint16_t, uint16_t *data); @@ -189,7 +189,7 @@ int32_t em_valid_nvm_bank_detect_ich8lan(struct em_hw *, uint32_t *); int32_t em_initialize_M88E1512_phy(struct em_hw *); /* IGP cable length table */ -static const uint16_t +static const uint16_t em_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = {5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, @@ -202,7 +202,7 @@ em_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120}; -static const uint16_t +static const uint16_t em_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] = {0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, @@ -353,11 +353,11 @@ em_phy_init_script(struct em_hw *hw) if (hw->mac_type == em_82547) { uint16_t fused, fine, coarse; /* Move to analog registers page */ - em_read_phy_reg(hw, + em_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { - em_read_phy_reg(hw, + em_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused); fine = fused & @@ -365,28 +365,28 @@ em_phy_init_script(struct em_hw *hw) coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK; - if (coarse > + if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { - coarse -= + coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10; - fine -= + fine -= IGP01E1000_ANALOG_FUSE_FINE_1; - } else if (coarse == + } else if (coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH) fine -= IGP01E1000_ANALOG_FUSE_FINE_10; - fused = (fused & + fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) | - (fine & + (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) | - (coarse & + (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK); - em_write_phy_reg(hw, - IGP01E1000_ANALOG_FUSE_CONTROL, + em_write_phy_reg(hw, + IGP01E1000_ANALOG_FUSE_CONTROL, fused); - em_write_phy_reg(hw, + em_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS, IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); } @@ -955,7 +955,7 @@ em_reset_hw(struct em_hw *hw) hw->mac_type == em_82576 || hw->mac_type == em_i210 || hw->mac_type == em_i350) { ret_val = em_set_pciex_completion_timeout(hw); - if (ret_val) { + if (ret_val) { DEBUGOUT("PCI-E Set completion timeout has failed.\n"); } } @@ -1006,7 +1006,7 @@ em_reset_hw(struct em_hw *hw) if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) break; else - extcnf_ctrl |= + extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; msec_delay(2); @@ -1177,7 +1177,7 @@ em_reset_hw(struct em_hw *hw) */ if (hw->mac_type == em_pchlan) E1000_WRITE_REG(hw, CRC_OFFSET, 0x65656565); - + /* Clear interrupt mask to stop board from generating interrupts */ DEBUGOUT("Masking off all interrupts\n"); E1000_WRITE_REG(hw, IMC, 0xffffffff); @@ -1274,7 +1274,7 @@ em_initialize_hardware_bits(struct em_softc *sc) reg_tarc1 |= 0x07000000; /* Set TARC1 bits 24-26 */ if (reg_tctl & E1000_TCTL_MULR) - /* Clear bit 28 if MULR is 1b */ + /* Clear bit 28 if MULR is 1b */ reg_tarc1 &= ~0x10000000; else /* Set bit 28 if MULR is 0b */ @@ -1345,7 +1345,7 @@ em_initialize_hardware_bits(struct em_softc *sc) /* Set bit 28 if MULR is 0b */ reg_tarc1 |= 0x10000000; - reg_tarc1 |= 0x45000000; /* Set bit 24, 26 and + reg_tarc1 |= 0x45000000; /* Set bit 24, 26 and * 30 */ E1000_WRITE_REG(hw, TARC1, reg_tarc1); @@ -1711,21 +1711,21 @@ em_init_hw(struct em_softc *sc) * incorrectly. */ if (hw->bus_type == em_bus_type_pcix) { - em_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, + em_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word); em_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word); - cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) + cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >> PCIX_COMMAND_MMRBC_SHIFT; - stat_mmrbc = (pcix_stat_hi_word & - PCIX_STATUS_HI_MMRBC_MASK) >> + stat_mmrbc = (pcix_stat_hi_word & + PCIX_STATUS_HI_MMRBC_MASK) >> PCIX_STATUS_HI_MMRBC_SHIFT; if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; if (cmd_mmrbc > stat_mmrbc) { pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; - pcix_cmd_word |= stat_mmrbc << + pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; em_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word); @@ -1814,7 +1814,7 @@ em_init_hw(struct em_softc *sc) */ if (sc->num_queues == 1) { ctrl = E1000_READ_REG(hw, TXDCTL(1)); - ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | + ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; E1000_WRITE_REG(hw, TXDCTL(1), ctrl); } @@ -1842,7 +1842,7 @@ em_init_hw(struct em_softc *sc) snoop = PCI_EX_82566_SNOOP_ALL; else snoop = (u_int32_t) ~ (PCI_EX_NO_SNOOP_ALL); - + em_set_pci_ex_no_snoop(hw, snoop); } @@ -1897,7 +1897,7 @@ em_adjust_serdes_amplitude(struct em_hw *hw) if (eeprom_data != EEPROM_RESERVED_WORD) { /* Adjust SERDES output amplitude only. */ eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK; - ret_val = em_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, + ret_val = em_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data); if (ret_val) return ret_val; @@ -1961,7 +1961,7 @@ em_setup_link(struct em_hw *hw) hw->fc = E1000_FC_FULL; break; default: - ret_val = em_read_eeprom(hw, + ret_val = em_read_eeprom(hw, eeprom_control2_reg_offset, 1, &eeprom_data); if (ret_val) { DEBUGOUT("EEPROM Read Error\n"); @@ -2077,7 +2077,7 @@ em_setup_link(struct em_hw *hw) * XON frames. */ if (hw->fc_send_xon) { - E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water + E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE)); E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); } else { @@ -2149,7 +2149,7 @@ em_setup_fiber_serdes_link(struct em_hw *hw) if (hw->mac_type >= em_82575) em_power_up_serdes_link_82575(hw); - + /* * On adapters with a MAC newer than 82544, SWDP 1 will be set when * the optics detect a signal. On older adapters, it will be cleared @@ -2235,7 +2235,7 @@ em_setup_fiber_serdes_link(struct em_hw *hw) * PAUSE. Later, we will disable the adapter's ability to * send PAUSE frames. */ - txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | + txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); break; case E1000_FC_TX_PAUSE: @@ -2250,7 +2250,7 @@ em_setup_fiber_serdes_link(struct em_hw *hw) * Flow control (both RX and TX) is enabled by a software * over-ride. */ - txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | + txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); break; default: @@ -2342,7 +2342,7 @@ em_copper_link_preconfig(struct em_hw *hw) ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); E1000_WRITE_REG(hw, CTRL, ctrl); } else { - ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | + ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); E1000_WRITE_REG(hw, CTRL, ctrl); ret_val = em_phy_hw_reset(hw); @@ -2357,10 +2357,10 @@ em_copper_link_preconfig(struct em_hw *hw) if ((hw->mac_type == em_82545_rev_3) || (hw->mac_type == em_82546_rev_3)) { - ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, + ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); phy_data |= 0x00000008; - ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, + ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); } if (hw->mac_type <= em_82543 || @@ -2449,7 +2449,7 @@ em_copper_link_igp_setup(struct em_hw *hw) if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) { hw->dsp_config_state = em_dsp_config_disabled; /* Force MDI for earlier revs of the IGP PHY */ - phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | + phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX); hw->mdix = 1; @@ -2489,24 +2489,24 @@ em_copper_link_igp_setup(struct em_hw *hw) */ if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { /* Disable SmartSpeed */ - ret_val = em_read_phy_reg(hw, + ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); if (ret_val) return ret_val; phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; - ret_val = em_write_phy_reg(hw, + ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data); if (ret_val) return ret_val; /* Set auto Master/Slave resolution process */ - ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, + ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); if (ret_val) return ret_val; phy_data &= ~CR_1000T_MS_ENABLE; - ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, + ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); if (ret_val) return ret_val; @@ -2517,7 +2517,7 @@ em_copper_link_igp_setup(struct em_hw *hw) /* load defaults for future use */ hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? - ((phy_data & CR_1000T_MS_VALUE) ? em_ms_force_master : + ((phy_data & CR_1000T_MS_VALUE) ? em_ms_force_master : em_ms_force_slave) : em_ms_auto; switch (phy_ms_setting) { @@ -2618,20 +2618,20 @@ em_copper_link_ggp_setup(struct em_hw *hw) } /* phy_reset_disable */ if (hw->mac_type == em_80003es2lan) { /* Bypass RX and TX FIFO's */ - ret_val = em_write_kmrn_reg(hw, + ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL, E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS); if (ret_val) return ret_val; - ret_val = em_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, + ret_val = em_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &phy_data); if (ret_val) return ret_val; phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; - ret_val = em_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, + ret_val = em_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, phy_data); if (ret_val) @@ -2653,18 +2653,18 @@ em_copper_link_ggp_setup(struct em_hw *hw) if (em_check_mng_mode(hw) == FALSE) { /* Enable Electrical Idle on the PHY */ phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; - ret_val = em_write_phy_reg(hw, + ret_val = em_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, phy_data); if (ret_val) return ret_val; - ret_val = em_read_phy_reg(hw, + ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &phy_data); if (ret_val) return ret_val; phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; - ret_val = em_write_phy_reg(hw, + ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, phy_data); if (ret_val) @@ -2679,7 +2679,7 @@ em_copper_link_ggp_setup(struct em_hw *hw) if (ret_val) return ret_val; phy_data |= GG82563_ICR_DIS_PADDING; - ret_val = em_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL, + ret_val = em_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL, phy_data); if (ret_val) return ret_val; @@ -2719,12 +2719,12 @@ em_copper_link_mgp_setup(struct em_hw *hw) if (hw->phy_id == M88E1141_E_PHY_ID) { phy_data |= 0x00000008; - ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, + ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); if (ret_val) return ret_val; - ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, + ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); if (ret_val) return ret_val; @@ -3039,7 +3039,7 @@ em_copper_link_rtl8211_setup(struct em_hw *hw) } /* pulse streching= 42-84ms, blink rate=84mm */ - phy_data = 0x140 | RGEPHY_LC_PULSE_42MS | RGEPHY_LC_LINK | + phy_data = 0x140 | RGEPHY_LC_PULSE_42MS | RGEPHY_LC_LINK | RGEPHY_LC_DUPLEX | RGEPHY_LC_RX; ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC, phy_data); @@ -3192,12 +3192,12 @@ em_setup_copper_link(struct em_hw *hw) ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); if (ret_val) return ret_val; - ret_val = em_read_kmrn_reg(hw, GG82563_REG(0x34, 9), + ret_val = em_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data); if (ret_val) return ret_val; reg_data |= 0x3F; - ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 9), + ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data); if (ret_val) return ret_val; @@ -3213,10 +3213,10 @@ em_setup_copper_link(struct em_hw *hw) switch (hw->mac_type) { case em_80003es2lan: /* Kumeran registers are written-only */ - reg_data = + reg_data = E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT; reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING; - ret_val = em_write_kmrn_reg(hw, + ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data); if (ret_val) return ret_val; @@ -3398,7 +3398,7 @@ em_phy_setup_autoneg(struct em_hw *hw) if (hw->phy_type != em_phy_ife) { /* Read the MII 1000Base-T Control Register (Address 9). */ - ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, + ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); if (ret_val) return ret_val; @@ -4280,7 +4280,7 @@ em_check_for_link(struct em_hw *hw) rxcw = E1000_READ_REG(hw, RXCW); if (hw->media_type == em_media_type_fiber) { - signal = (hw->mac_type > em_82544) ? + signal = (hw->mac_type > em_82544) ? E1000_CTRL_SWDPIN1 : 0; if (status & E1000_STATUS_LU) hw->get_link_status = FALSE; @@ -4378,7 +4378,7 @@ em_check_for_link(struct em_hw *hw) E1000_WRITE_REG(hw, IMC, 0xffffffff); ret_val = em_polarity_reversal_workaround(hw); icr = E1000_READ_REG(hw, ICR); - E1000_WRITE_REG(hw, ICS, + E1000_WRITE_REG(hw, ICS, (icr & ~E1000_ICS_LSC)); E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK); } @@ -4546,7 +4546,7 @@ em_check_for_link(struct em_hw *hw) } if ((hw->media_type == em_media_type_internal_serdes) && (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { - hw->serdes_link_down = !(E1000_STATUS_LU & + hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS)); } return E1000_SUCCESS; @@ -4576,7 +4576,7 @@ em_get_pcs_speed_and_duplex_82575(struct em_hw *hw, uint16_t *speed, */ if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) { hw->serdes_link_down = FALSE; - + /* Detect and store PCS speed */ if (pcs & E1000_PCS_LSTS_SPEED_1000) { *speed = SPEED_1000; @@ -4659,9 +4659,9 @@ em_get_speed_and_duplex(struct em_hw *hw, uint16_t *speed, uint16_t *duplex) &phy_data); if (ret_val) return ret_val; - if ((*speed == SPEED_100 && + if ((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) || - (*speed == SPEED_10 && + (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS))) *duplex = HALF_DUPLEX; } @@ -4780,8 +4780,8 @@ em_shift_out_mdi_bits(struct em_hw *hw, uint32_t data, uint16_t count) ctrl = E1000_READ_REG(hw, CTRL); - /* Set MDIO_DIR and MDC_DIR direction bits to be used as output - * pins. + /* Set MDIO_DIR and MDC_DIR direction bits to be used as output + * pins. */ ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); @@ -4888,7 +4888,7 @@ em_swfw_sync_acquire(struct em_hw *hw, uint16_t mask) if (!(swfw_sync & (fwmask | swmask))) { break; } - /* + /* * firmware currently using resource (fwmask) * or other software thread currently using resource (swmask) */ @@ -5174,8 +5174,8 @@ em_read_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data) if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { ret_val = em_write_phy_reg_ex(hw, - GG82563_PHY_PAGE_SELECT, - (uint16_t) ((uint16_t) reg_addr >> + GG82563_PHY_PAGE_SELECT, + (uint16_t) ((uint16_t) reg_addr >> GG82563_PAGE_SHIFT)); } else { /* @@ -5184,7 +5184,7 @@ em_read_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data) */ ret_val = em_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT_ALT, - (uint16_t) ((uint16_t) reg_addr >> + (uint16_t) ((uint16_t) reg_addr >> GG82563_PAGE_SHIFT)); } @@ -5196,7 +5196,7 @@ em_read_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data) } else if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) { if (reg_addr > MAX_PHY_MULTI_PAGE_REG) { ret_val = em_write_phy_reg_ex(hw, BM_PHY_PAGE_SELECT, - (uint16_t) ((uint16_t) reg_addr >> + (uint16_t) ((uint16_t) reg_addr >> PHY_PAGE_SHIFT)); if (ret_val) return ret_val; @@ -5343,11 +5343,11 @@ em_write_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t phy_data) if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) || (hw->mac_type == em_80003es2lan)) { /* Select Configuration Page */ - if ((reg_addr & MAX_PHY_REG_ADDRESS) < + if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { - ret_val = em_write_phy_reg_ex(hw, + ret_val = em_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT, - (uint16_t) ((uint16_t) reg_addr >> + (uint16_t) ((uint16_t) reg_addr >> GG82563_PAGE_SHIFT)); } else { /* @@ -5356,7 +5356,7 @@ em_write_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t phy_data) */ ret_val = em_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT_ALT, - (uint16_t) ((uint16_t) reg_addr >> + (uint16_t) ((uint16_t) reg_addr >> GG82563_PAGE_SHIFT)); } @@ -5368,7 +5368,7 @@ em_write_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t phy_data) } else if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) { if (reg_addr > MAX_PHY_MULTI_PAGE_REG) { ret_val = em_write_phy_reg_ex(hw, BM_PHY_PAGE_SELECT, - (uint16_t) ((uint16_t) reg_addr >> + (uint16_t) ((uint16_t) reg_addr >> PHY_PAGE_SHIFT)); if (ret_val) return ret_val; @@ -5451,8 +5451,8 @@ em_write_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr, uint16_t phy_data) * as follows: . */ - mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | - (hw->phy_addr << 7) | (PHY_OP_WRITE << 12) | + mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | + (hw->phy_addr << 7) | (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); mdic <<= 16; mdic |= (uint32_t) phy_data; @@ -5914,7 +5914,7 @@ em_phy_reset(struct em_hw *hw) if (ret_val) return ret_val; } - + if (hw->mac_type >= em_pchlan) { ret_val = em_oem_bits_config_pchlan(hw, TRUE); if (ret_val) @@ -6421,7 +6421,7 @@ em_init_eeprom_params(struct em_hw *hw) case em_pch_lpt: { int32_t i = 0; - uint32_t flash_size = + uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG); eeprom->type = em_eeprom_ich8; eeprom->use_eerd = FALSE; @@ -6433,16 +6433,16 @@ em_init_eeprom_params(struct em_hw *hw) */ if (hw->eeprom_shadow_ram != NULL) { for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { - hw->eeprom_shadow_ram[i].modified = + hw->eeprom_shadow_ram[i].modified = FALSE; - hw->eeprom_shadow_ram[i].eeprom_word = + hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; } } - hw->flash_base_addr = (flash_size & + hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) * ICH_FLASH_SECTOR_SIZE; - hw->flash_bank_size = ((flash_size >> 16) & + hw->flash_bank_size = ((flash_size >> 16) & ICH_GFPREG_BASE_MASK) + 1; hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK); @@ -6471,9 +6471,9 @@ em_init_eeprom_params(struct em_hw *hw) */ if (hw->eeprom_shadow_ram != NULL) { for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { - hw->eeprom_shadow_ram[i].modified = + hw->eeprom_shadow_ram[i].modified = FALSE; - hw->eeprom_shadow_ram[i].eeprom_word = + hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; } } @@ -6499,7 +6499,7 @@ em_init_eeprom_params(struct em_hw *hw) &eeprom_size); if (ret_val) return ret_val; - eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> + eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT; /* * 256B eeprom size was not supported in earlier @@ -6520,7 +6520,7 @@ em_init_eeprom_params(struct em_hw *hw) EEPROM_WORD_SIZE_SHIFT_MAX) { eeprom->word_size = 1 << EEPROM_WORD_SIZE_SHIFT_MAX; } else { - eeprom->word_size = 1 << + eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT); } } @@ -6878,7 +6878,7 @@ em_read_eeprom(struct em_hw *hw, uint16_t offset, uint16_t words, * A check for invalid values: offset too large, too many words, and * not enough words. */ - if ((offset >= eeprom->word_size) || + if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) || (words == 0)) { DEBUGOUT2("\"words\" parameter out of bounds. Words = %d," @@ -6930,7 +6930,7 @@ em_read_eeprom(struct em_hw *hw, uint16_t offset, uint16_t words, /* Send the READ command (opcode + addr) */ em_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); - em_shift_out_ee_bits(hw, (uint16_t) (offset * 2), + em_shift_out_ee_bits(hw, (uint16_t) (offset * 2), eeprom->address_bits); /* * Read the data. The address of the eeprom internally @@ -6989,7 +6989,7 @@ em_read_eeprom_eerd(struct em_hw *hw, uint16_t offset, uint16_t words, if (error) { break; } - data[i] = (E1000_READ_REG(hw, EERD) >> + data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA); } @@ -7131,8 +7131,8 @@ em_validate_eeprom_checksum(struct em_hw *hw) uint16_t checksum_reg; DEBUGFUNC("em_validate_eeprom_checksum"); - checksum_reg = hw->mac_type != em_icp_xxxx ? - EEPROM_CHECKSUM_REG : + checksum_reg = hw->mac_type != em_icp_xxxx ? + EEPROM_CHECKSUM_REG : EEPROM_CHECKSUM_REG_ICP_xxxx; if (((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) && @@ -7161,7 +7161,7 @@ em_validate_eeprom_checksum(struct em_hw *hw) if (IS_ICH8(hw->mac_type)) { uint16_t word; uint16_t valid_csum_mask; - + /* * Drivers must allocate the shadow ram structure for the * EEPROM checksum to be updated. Otherwise, this bit as @@ -7496,7 +7496,7 @@ em_commit_shadow_ram(struct em_hw *hw) if (i == attempts) { return -E1000_ERR_EEPROM; } - /* + /* * If STM opcode located in bits 15:8 of flop, reset firmware */ if ((flop & 0xFF00) == E1000_STM_OPCODE) { @@ -7546,7 +7546,7 @@ em_commit_shadow_ram(struct em_hw *hw) * shadow RAM */ if (hw->eeprom_shadow_ram[i].modified == TRUE) { - low_byte = (uint8_t) + low_byte = (uint8_t) hw->eeprom_shadow_ram[i].eeprom_word; usec_delay(100); error = em_verify_write_ich8_byte(hw, @@ -7561,7 +7561,7 @@ em_commit_shadow_ram(struct em_hw *hw) usec_delay(100); } } else { - em_read_ich8_byte(hw, (i << 1) + + em_read_ich8_byte(hw, (i << 1) + old_bank_offset, &low_byte); usec_delay(100); error = em_verify_write_ich8_byte(hw, @@ -7955,11 +7955,11 @@ em_hash_mc_addr(struct em_hw *hw, uint8_t *mc_addr) case 0: if (IS_ICH8(hw->mac_type)) { /* [47:38] i.e. 0x158 for above example address */ - hash_value = ((mc_addr[4] >> 6) | + hash_value = ((mc_addr[4] >> 6) | (((uint16_t) mc_addr[5]) << 2)); } else { /* [47:36] i.e. 0x563 for above example address */ - hash_value = ((mc_addr[4] >> 4) | + hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4)); } break; @@ -8159,7 +8159,7 @@ em_clear_vfta_i350(struct em_hw *hw) { uint32_t offset; int i; - + for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { for (i = 0; i < 10; i++) E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0); @@ -8412,7 +8412,7 @@ em_get_bus_info(struct em_hw *hw) if (ret_val) hw->bus_width = em_bus_width_unknown; else - hw->bus_width = (pci_ex_link_status & + hw->bus_width = (pci_ex_link_status & PCI_EX_LINK_WIDTH_MASK) >> PCI_EX_LINK_WIDTH_SHIFT; break; case em_ich8lan: @@ -8578,7 +8578,7 @@ em_get_cable_length(struct em_hw *hw, uint16_t *min_length, } } else if (hw->phy_type == em_phy_igp) { /* For IGP PHY */ uint16_t cur_agc_value; - uint16_t min_agc_value = + uint16_t min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE; uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = {IGP01E1000_PHY_AGC_A, IGP01E1000_PHY_AGC_B, @@ -8586,7 +8586,7 @@ em_get_cable_length(struct em_hw *hw, uint16_t *min_length, /* Read the AGC registers for all channels */ for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { - ret_val = em_read_phy_reg(hw, agc_reg_array[i], + ret_val = em_read_phy_reg(hw, agc_reg_array[i], &phy_data); if (ret_val) return ret_val; @@ -8595,7 +8595,7 @@ em_get_cable_length(struct em_hw *hw, uint16_t *min_length, IGP01E1000_AGC_LENGTH_SHIFT; /* Value bound check. */ - if ((cur_agc_value >= + if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || (cur_agc_value == 0)) return -E1000_ERR_PHY; @@ -8608,7 +8608,7 @@ em_get_cable_length(struct em_hw *hw, uint16_t *min_length, } /* Remove the minimal AGC result for length < 50m */ - if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * + if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * em_igp_cable_length_50) { agc_value -= min_agc_value; @@ -9418,7 +9418,7 @@ em_enable_tx_pkt_filtering(struct em_hw *hw) hdr->checksum = 0; if ((hdr->signature == E1000_IAMT_SIGNATURE) && checksum == em_calculate_mng_checksum( - (char *) buffer, + (char *) buffer, E1000_MNG_DHCP_COOKIE_LENGTH)) { if (hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT) @@ -9545,7 +9545,7 @@ em_set_pci_express_master_disable(struct em_hw *hw) /****************************************************************************** * - * Disables PCI-Express master access and verifies there are no pending + * Disables PCI-Express master access and verifies there are no pending * requests * * hw: Struct containing variables accessed by shared code @@ -9567,7 +9567,7 @@ em_disable_pciex_master(struct em_hw *hw) em_set_pci_express_master_disable(hw); while (timeout) { - if (!(E1000_READ_REG(hw, STATUS) & + if (!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE)) break; else @@ -10868,7 +10868,7 @@ em_erase_ich8_4k_segment(struct em_hw *hw, uint32_t bank) * the overall size. */ sector_base_addr = gfpreg & ICH_GFPREG_BASE_MASK; - sector_end_addr = + sector_end_addr = ((gfpreg >> 16) & ICH_GFPREG_BASE_MASK) + 1; /* @@ -10879,7 +10879,7 @@ em_erase_ich8_4k_segment(struct em_hw *hw, uint32_t bank) << ICH_FLASH_SECT_ADDR_SHIFT; bank_size /= 2; /* Word align */ - bank_size = + bank_size = (bank_size / sizeof(uint16_t)) * sizeof(uint16_t); sub_sector_size = ICH_FLASH_SEG_SIZE_8K; @@ -10919,7 +10919,7 @@ em_erase_ich8_4k_segment(struct em_hw *hw, uint32_t bank) * here based off the on-chip erase sector size and * the software bank size (4, 8 or 64 KBytes) */ - flash_linear_address = + flash_linear_address = bank * bank_size + j * sub_sector_size; flash_linear_address += hw->flash_base_addr; flash_linear_address &= ICH_FLASH_LINEAR_ADDR_MASK; @@ -11227,7 +11227,7 @@ em_set_pciex_completion_timeout(struct em_hw *hw) pciex_devctl2 |= PCIE_DEVICE_CONTROL2_16ms; ret_val = em_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, - &pciex_devctl2); + &pciex_devctl2); #endif out: @@ -11534,7 +11534,7 @@ em_k1_workaround_lv(struct em_hw *hw) E1000_WRITE_REG(hw, FEXTNVM4, mac_reg); } - + return E1000_SUCCESS; } @@ -11740,7 +11740,7 @@ out: } int32_t -em_set_eee_i350(struct em_hw *hw) +em_set_eee_i350(struct em_hw *hw) { int32_t ret_val = E1000_SUCCESS; uint32_t ipcnfg, eeer; diff --git a/sys/dev/pci/if_em_hw.h b/sys/dev/pci/if_em_hw.h index 0b9f548d6..c1ab87790 100644 --- a/sys/dev/pci/if_em_hw.h +++ b/sys/dev/pci/if_em_hw.h @@ -1,31 +1,31 @@ /******************************************************************************* - Copyright (c) 2001-2005, Intel Corporation + Copyright (c) 2001-2005, Intel Corporation All rights reserved. - - Redistribution and use in source and binary forms, with or without + + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, + + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the + + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - - 3. Neither the name of the Intel Corporation nor the names of its - contributors may be used to endorse or promote products derived from + + 3. Neither the name of the Intel Corporation nor the names of its + contributors may be used to endorse or promote products derived from this software without specific prior written permission. - + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. @@ -2326,10 +2326,10 @@ struct em_host_command_info { #define E1000_MDALIGN 4096 -#define E1000_MDICNFG_EXT_MDIO 0x80000000 /* MDI ext/int destination */ -#define E1000_MDICNFG_COM_MDIO 0x40000000 /* MDI shared w/ lan 0 */ -#define E1000_MDICNFG_PHY_MASK 0x03E00000 -#define E1000_MDICNFG_PHY_SHIFT 21 +#define E1000_MDICNFG_EXT_MDIO 0x80000000 /* MDI ext/int destination */ +#define E1000_MDICNFG_COM_MDIO 0x40000000 /* MDI shared w/ lan 0 */ +#define E1000_MDICNFG_PHY_MASK 0x03E00000 +#define E1000_MDICNFG_PHY_SHIFT 21 /* I350 EEE defines */ #define E1000_IPCNFG_EEE_1G_AN 0x00000008 /* IPCNFG EEE Ena 1G AN */ @@ -3658,7 +3658,7 @@ union ich8_hws_flash_regacc { #define PCI_ST_SMIA_OFFSET 0x04 #define E1000_IMC1 0x008D8 /* Interrupt Mask Clear 1 - RW */ -#define E1000_IMC2 0x008F8 /* Interrupt Mask Clear 2 - RW */ +#define E1000_IMC2 0x008F8 /* Interrupt Mask Clear 2 - RW */ #define E1000_82542_IMC1 E1000_IMC1 #define E1000_82542_IMC2 E1000_IMC2 diff --git a/sys/dev/pci/if_em_soc.c b/sys/dev/pci/if_em_soc.c index 3c2ce60df..dec72d9b8 100644 --- a/sys/dev/pci/if_em_soc.c +++ b/sys/dev/pci/if_em_soc.c @@ -68,9 +68,9 @@ gcu_miibus_readreg(struct em_hw *hw, int phy, int reg) while (!done && (i++ < GCU_MAX_ATTEMPTS)) { DELAY(GCU_CMD_DELAY); - data = bus_space_read_4(gcu->tag, gcu->handle, + data = bus_space_read_4(gcu->tag, gcu->handle, MDIO_COMMAND_REG); - done = !((data & MDIO_COMMAND_GO_MASK) >> + done = !((data & MDIO_COMMAND_GO_MASK) >> MDIO_COMMAND_GO_OFFSET); } mtx_leave(&gcu->mdio_mtx); @@ -116,9 +116,9 @@ gcu_miibus_writereg(struct em_hw *hw, int phy, int reg, int val) while (!done && (i++ < GCU_MAX_ATTEMPTS)) { DELAY(GCU_CMD_DELAY); - data = bus_space_read_4(gcu->tag, gcu->handle, + data = bus_space_read_4(gcu->tag, gcu->handle, MDIO_COMMAND_REG); - done = !((data & MDIO_COMMAND_GO_MASK) >> + done = !((data & MDIO_COMMAND_GO_MASK) >> MDIO_COMMAND_GO_OFFSET); } mtx_leave(&gcu->mdio_mtx); diff --git a/sys/dev/pci/if_ep_pci.c b/sys/dev/pci/if_ep_pci.c index 93fed4ef8..77e6cf211 100644 --- a/sys/dev/pci/if_ep_pci.c +++ b/sys/dev/pci/if_ep_pci.c @@ -31,12 +31,12 @@ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include "bpfilter.h" - +#include "bpfilter.h" + #include #include -#include -#include +#include +#include #include #include #include @@ -48,7 +48,7 @@ #include #include - + #if NBPFILTER > 0 #include #endif diff --git a/sys/dev/pci/if_et.c b/sys/dev/pci/if_et.c index df844edba..e37cb85ca 100644 --- a/sys/dev/pci/if_et.c +++ b/sys/dev/pci/if_et.c @@ -1,14 +1,14 @@ /* $OpenBSD: if_et.c,v 1.42 2022/03/11 18:00:45 mpi Exp $ */ /* * Copyright (c) 2007 The DragonFly Project. All rights reserved. - * + * * This code is derived from software contributed to The DragonFly Project * by Sepherosa Ziehau - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: - * + * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright @@ -18,7 +18,7 @@ * 3. Neither the name of The DragonFly Project nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific, prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS @@ -31,7 +31,7 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. - * + * * $DragonFly: src/sys/dev/netif/et/if_et.c,v 1.1 2007/10/12 14:12:42 sephe Exp $ */ @@ -49,7 +49,7 @@ #include #include - + #include #include #include @@ -60,7 +60,7 @@ #if NBPFILTER > 0 #include #endif - + #include #include @@ -484,7 +484,7 @@ et_bus_config(struct et_softc *sc) */ pci_conf_read(sc->sc_pct, sc->sc_pcitag, ET_PCIR_EEPROM_MISC); val = pci_conf_read(sc->sc_pct, sc->sc_pcitag, ET_PCIR_EEPROM_MISC); - + if (val & ET_PCIM_EEPROM_STATUS_ERROR) { printf("%s: EEPROM status error 0x%02x\n", sc->sc_dev.dv_xname, val); @@ -713,7 +713,7 @@ et_dma_free(struct et_softc *sc) * Destroy RX stat ring DMA stuffs */ et_dma_mem_destroy(sc, rxst_ring->rsr_stat, rxst_ring->rsr_dmap); - + /* * Destroy RX status DMA stuffs */ @@ -806,7 +806,7 @@ et_dma_mbuf_destroy(struct et_softc *sc, int tx_done, const int rx_done[]) KASSERT(rb->rb_mbuf == NULL, ("RX mbuf in %d RX ring is not freed yet\n", i)); - bus_dmamap_destroy(sc->sc_dmat, rb->rb_dmap); + bus_dmamap_destroy(sc->sc_dmat, rb->rb_dmap); } } @@ -1741,7 +1741,7 @@ et_rxeof(struct et_softc *sc) if (buf_idx != rx_ring->rr_index) { printf("%s: WARNING!! ring %d, " - "buf_idx %d, rr_idx %d\n", sc->sc_dev.dv_xname, + "buf_idx %d, rr_idx %d\n", sc->sc_dev.dv_xname, ring_idx, buf_idx, rx_ring->rr_index); } @@ -1855,7 +1855,7 @@ et_encap(struct et_softc *sc, struct mbuf **m0) bus_dmamap_sync(sc->sc_dmat, tx_ring->tr_dmap, 0, tx_ring->tr_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE); - + tx_ready_pos = __SHIFTIN(tx_ring->tr_ready_index, ET_TX_READY_POS_INDEX); diff --git a/sys/dev/pci/if_etreg.h b/sys/dev/pci/if_etreg.h index 24fadca1b..c9602488c 100644 --- a/sys/dev/pci/if_etreg.h +++ b/sys/dev/pci/if_etreg.h @@ -2,14 +2,14 @@ /* * Copyright (c) 2007 The DragonFly Project. All rights reserved. - * + * * This code is derived from software contributed to The DragonFly Project * by Sepherosa Ziehau - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: - * + * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright @@ -19,7 +19,7 @@ * 3. Neither the name of The DragonFly Project nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific, prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS @@ -32,7 +32,7 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. - * + * * $DragonFly: src/sys/dev/netif/et/if_etreg.h,v 1.1 2007/10/12 14:12:42 sephe Exp $ */ diff --git a/sys/dev/pci/if_fxp_pci.c b/sys/dev/pci/if_fxp_pci.c index 6754ba4fc..7f98556ea 100644 --- a/sys/dev/pci/if_fxp_pci.c +++ b/sys/dev/pci/if_fxp_pci.c @@ -223,9 +223,9 @@ fxp_pci_attach(struct device *parent, struct device *self, void *aux) * killing people's eeproms. */ if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) && - (PCI_PRODUCT(pa->pa_id) == 0x2449 || - (PCI_PRODUCT(pa->pa_id) > 0x1030 && - PCI_PRODUCT(pa->pa_id) < 0x1039) || + (PCI_PRODUCT(pa->pa_id) == 0x2449 || + (PCI_PRODUCT(pa->pa_id) > 0x1030 && + PCI_PRODUCT(pa->pa_id) < 0x1039) || (PCI_PRODUCT(pa->pa_id) == 0x1229 && (sc->sc_revision >= 8 && sc->sc_revision <= 16)))) sc->sc_flags |= FXPF_DISABLE_STANDBY; diff --git a/sys/dev/pci/if_hme_pci.c b/sys/dev/pci/if_hme_pci.c index 3019ee18c..b3c5b2496 100644 --- a/sys/dev/pci/if_hme_pci.c +++ b/sys/dev/pci/if_hme_pci.c @@ -81,7 +81,7 @@ hmematch_pci(struct device *parent, void *vcf, void *aux) { struct pci_attach_args *pa = aux; - if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SUN && + if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SUN && PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SUN_HME) return (1); @@ -280,7 +280,7 @@ hmeattach_pci(struct device *parent, struct device *self, void *aux) printf(": couldn't map interrupt\n"); bus_space_unmap(hsc->hsc_memt, hsc->hsc_memh, hsc->hsc_memsize); return; - } + } intrstr = pci_intr_string(pa->pa_pc, ih); hsc->hsc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_NET, hme_intr, sc, self->dv_xname); diff --git a/sys/dev/pci/if_iavf.c b/sys/dev/pci/if_iavf.c index d65769d78..39c8f9ec6 100644 --- a/sys/dev/pci/if_iavf.c +++ b/sys/dev/pci/if_iavf.c @@ -1988,7 +1988,7 @@ iavf_rxeof(struct iavf_softc *sc, struct ifiqueue *ifiq) bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, BUS_DMASYNC_POSTREAD); bus_dmamap_unload(sc->sc_dmat, map); - + m = rxm->rxm_m; rxm->rxm_m = NULL; diff --git a/sys/dev/pci/if_igc.c b/sys/dev/pci/if_igc.c index db84e23bb..23c7b7c86 100644 --- a/sys/dev/pci/if_igc.c +++ b/sys/dev/pci/if_igc.c @@ -380,7 +380,7 @@ igc_allocate_queues(struct igc_softc *sc) printf("%s: unable to allocate TX ring\n", DEVNAME(sc)); goto fail; } - + /* Allocate the RX ring. */ sc->rx_rings = mallocarray(sc->sc_nqueues, sizeof(struct rx_ring), M_DEVBUF, M_NOWAIT | M_ZERO); @@ -1233,7 +1233,7 @@ igc_rxfill(struct rx_ring *rxr) int i, post = 0; u_int slots; - bus_dmamap_sync(rxr->rxdma.dma_tag, rxr->rxdma.dma_map, 0, + bus_dmamap_sync(rxr->rxdma.dma_tag, rxr->rxdma.dma_map, 0, rxr->rxdma.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); i = rxr->last_desc_filled; @@ -1330,7 +1330,7 @@ igc_rxeof(struct rx_ring *rxr) IGC_PKTTYPE_MASK; hash = letoh32(rxdesc->wb.lower.hi_dword.rss); hashtype = le16toh(rxdesc->wb.lower.lo_dword.hs_rss.pkt_info) & - IGC_RXDADV_RSSTYPE_MASK; + IGC_RXDADV_RSSTYPE_MASK; if (staterr & IGC_RXDEXT_STATERR_RXE) { if (rxbuf->fmp) { diff --git a/sys/dev/pci/if_ipw.c b/sys/dev/pci/if_ipw.c index a9fc9d5ce..9f40c08fb 100644 --- a/sys/dev/pci/if_ipw.c +++ b/sys/dev/pci/if_ipw.c @@ -883,7 +883,7 @@ ipw_data_intr(struct ipw_softc *sc, struct ipw_status *status, } m = sbuf->m; - sbuf->m = mnew; + sbuf->m = mnew; sbd->bd->physaddr = htole32(sbuf->map->dm_segs[0].ds_addr); /* finalize mbuf */ diff --git a/sys/dev/pci/if_iwi.c b/sys/dev/pci/if_iwi.c index d086ade1e..5efd1a29c 100644 --- a/sys/dev/pci/if_iwi.c +++ b/sys/dev/pci/if_iwi.c @@ -1052,7 +1052,7 @@ iwi_notification_intr(struct iwi_softc *sc, struct iwi_rx_data *data, } break; } - case IWI_NOTIF_TYPE_BEACON: + case IWI_NOTIF_TYPE_BEACON: { struct iwi_notif_beacon *beacon = (struct iwi_notif_beacon *)(notif + 1); diff --git a/sys/dev/pci/if_iwm.c b/sys/dev/pci/if_iwm.c index fc4bc1adc..27bff09f1 100644 --- a/sys/dev/pci/if_iwm.c +++ b/sys/dev/pci/if_iwm.c @@ -598,7 +598,7 @@ iwm_is_mimo_ht_mcs(int mcs) { int ridx = iwm_ht_mcs2ridx[mcs]; return iwm_is_mimo_ht_plcp(iwm_rates[ridx].ht_plcp); - + } int @@ -681,7 +681,7 @@ iwm_fw_info_free(struct iwm_fw_info *fw) /* don't touch fw->fw_status */ memset(fw->fw_sects, 0, sizeof(fw->fw_sects)); } - + void iwm_fw_version_str(char *buf, size_t bufsize, uint32_t major, uint32_t minor, uint32_t api) @@ -1105,7 +1105,7 @@ iwm_read_mem(struct iwm_softc *sc, uint32_t addr, void *buf, int dwords) int iwm_write_mem(struct iwm_softc *sc, uint32_t addr, const void *buf, int dwords) { - int offs; + int offs; const uint32_t *vals = buf; if (iwm_nic_lock(sc)) { @@ -1709,7 +1709,7 @@ iwm_prepare_card_hw(struct iwm_softc *sc) IWM_SETBITS(sc, IWM_CSR_DBG_LINK_PWR_MGMT_REG, IWM_CSR_RESET_LINK_PWR_MGMT_DISABLED); DELAY(1000); - + for (ntries = 0; ntries < 10; ntries++) { /* If HW is not ready, prepare the conditions to check again */ IWM_SETBITS(sc, IWM_CSR_HW_IF_CONFIG_REG, @@ -2137,7 +2137,7 @@ iwm_stop_device(struct iwm_softc *sc) */ iwm_conf_msix_hw(sc, 1); - /* + /* * Upon stop, the APM issues an interrupt if HW RF kill is set. * Clear the interrupt again. */ @@ -3444,7 +3444,7 @@ iwm_mac_ctxt_task(void *arg) err = iwm_mac_ctxt_cmd(sc, in, IWM_FW_CTXT_ACTION_MODIFY, 1); if (err) printf("%s: failed to update MAC\n", DEVNAME(sc)); - + iwm_unprotect_session(sc, in); refcnt_rele_wake(&sc->task_refs); @@ -3607,7 +3607,7 @@ iwm_sta_tx_agg(struct iwm_softc *sc, struct ieee80211_node *ni, uint8_t tid, if (start && (sc->qenablemsk & (1 << qid)) == 0) { if (!iwm_nic_lock(sc)) { if (start) - ieee80211_addba_resp_refuse(ic, ni, tid, + ieee80211_addba_resp_refuse(ic, ni, tid, IEEE80211_STATUS_UNSPECIFIED); return EBUSY; } @@ -3618,7 +3618,7 @@ iwm_sta_tx_agg(struct iwm_softc *sc, struct ieee80211_node *ni, uint8_t tid, printf("%s: could not enable Tx queue %d (error %d)\n", DEVNAME(sc), qid, err); if (start) - ieee80211_addba_resp_refuse(ic, ni, tid, + ieee80211_addba_resp_refuse(ic, ni, tid, IEEE80211_STATUS_UNSPECIFIED); return err; } @@ -3647,7 +3647,7 @@ iwm_sta_tx_agg(struct iwm_softc *sc, struct ieee80211_node *ni, uint8_t tid, printf("%s: could not update sta (error %d)\n", DEVNAME(sc), err); if (start) - ieee80211_addba_resp_refuse(ic, ni, tid, + ieee80211_addba_resp_refuse(ic, ni, tid, IEEE80211_STATUS_UNSPECIFIED); return err; } @@ -4803,7 +4803,7 @@ iwm_rx_frame(struct iwm_softc *sc, struct mbuf *m, int chanidx, struct ieee80211_frame *wh; struct ieee80211_node *ni; - if (chanidx < 0 || chanidx >= nitems(ic->ic_channels)) + if (chanidx < 0 || chanidx >= nitems(ic->ic_channels)) chanidx = ieee80211_chan2ieee(ic, ic->ic_ibss_chan); wh = mtod(m, struct ieee80211_frame *); @@ -5410,7 +5410,7 @@ iwm_rx_mpdu_mq(struct iwm_softc *sc, struct mbuf *m, void *pktdata, /* Padding is inserted after the IV. */ hdrlen += IEEE80211_CCMP_HDRLEN; } - + memmove(m->m_data + 2, m->m_data, hdrlen); m_adj(m, 2); } @@ -5446,7 +5446,7 @@ iwm_rx_mpdu_mq(struct iwm_softc *sc, struct mbuf *m, void *pktdata, /* HW reverses addr3. */ iwm_flip_address(qwh->i_addr3); - } + } } /* @@ -5500,7 +5500,7 @@ iwm_ra_choose(struct iwm_softc *sc, struct ieee80211_node *ni) else ieee80211_ra_choose(&in->in_rn, ic, ni); - /* + /* * If RA has chosen a new TX rate we must update * the firmware's LQ rate table. */ @@ -5628,7 +5628,7 @@ iwm_rx_tx_cmd_single(struct iwm_softc *sc, struct iwm_rx_packet *pkt, int status = le16toh(tx_resp->status.status) & IWM_TX_STATUS_MSK; uint32_t initial_rate = le32toh(tx_resp->initial_rate); int txfail; - + KASSERT(tx_resp->frame_count == 1); txfail = (status != IWM_TX_STATUS_SUCCESS && @@ -6439,7 +6439,7 @@ iwm_send_cmd(struct iwm_softc *sc, struct iwm_host_cmd *hcmd) } else if (generation == sc->sc_generation) { free(sc->sc_cmd_resp_pkt[idx], M_DEVBUF, sc->sc_cmd_resp_len[idx]); - sc->sc_cmd_resp_pkt[idx] = NULL; + sc->sc_cmd_resp_pkt[idx] = NULL; } } out: @@ -6540,7 +6540,7 @@ iwm_cmd_done(struct iwm_softc *sc, int qid, int idx, int code) DPRINTF(("%s: unexpected firmware response to command 0x%x\n", DEVNAME(sc), code)); } else if (--ring->queued == 0) { - /* + /* * 7000 family NICs are locked while commands are in progress. * All commands are now done so we may unlock the NIC again. */ @@ -6669,16 +6669,16 @@ iwm_tx_fill_cmd(struct iwm_softc *sc, struct iwm_node *in, ieee80211_node_supports_ht_chan40(ni)) sco = (ni->ni_htop0 & IEEE80211_HTOP0_SCO_MASK); if (ni->ni_flags & IEEE80211_NODE_VHT) - rate_flags |= IWM_RATE_MCS_VHT_MSK; + rate_flags |= IWM_RATE_MCS_VHT_MSK; else - rate_flags |= IWM_RATE_MCS_HT_MSK; + rate_flags |= IWM_RATE_MCS_HT_MSK; if (vht_chan_width == IEEE80211_VHTOP0_CHAN_WIDTH_80 && in->in_phyctxt != NULL && in->in_phyctxt->vht_chan_width == vht_chan_width) { rate_flags |= IWM_RATE_MCS_CHAN_WIDTH_80; if (ieee80211_node_supports_vht_sgi80(ni)) rate_flags |= IWM_RATE_MCS_SGI_MSK; - } else if ((sco == IEEE80211_HTOP0_SCO_SCA || + } else if ((sco == IEEE80211_HTOP0_SCO_SCA || sco == IEEE80211_HTOP0_SCO_SCB) && in->in_phyctxt != NULL && in->in_phyctxt->sco == sco) { rate_flags |= IWM_RATE_MCS_CHAN_WIDTH_40; @@ -7673,7 +7673,7 @@ iwm_fill_probe_req(struct iwm_softc *sc, struct iwm_scan_probe_req *preq) frm = ieee80211_add_xrates(frm, rs); remain -= frm - pos; - if (isset(sc->sc_enabled_capa, + if (isset(sc->sc_enabled_capa, IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT)) { if (remain < 3) return ENOBUFS; @@ -7777,9 +7777,9 @@ iwm_lmac_scan(struct iwm_softc *sc, int bgscan) else req->scan_flags |= htole32(IWM_LMAC_SCAN_FLAG_PRE_CONNECTION); - if (isset(sc->sc_enabled_capa, + if (isset(sc->sc_enabled_capa, IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT) && - isset(sc->sc_enabled_capa, + isset(sc->sc_enabled_capa, IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT)) req->scan_flags |= htole32(IWM_LMAC_SCAN_FLAGS_RRM_ENABLED); @@ -8090,9 +8090,9 @@ iwm_umac_scan(struct iwm_softc *sc, int bgscan) } else req->general_flags |= htole32(IWM_UMAC_SCAN_GEN_FLAGS_PASSIVE); - if (isset(sc->sc_enabled_capa, + if (isset(sc->sc_enabled_capa, IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT) && - isset(sc->sc_enabled_capa, + isset(sc->sc_enabled_capa, IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT)) req->general_flags |= htole32(IWM_UMAC_SCAN_GEN_FLAGS_RRM_ENABLED); @@ -8195,7 +8195,7 @@ iwm_ack_rates(struct iwm_softc *sc, struct iwm_node *in, int *cck_rates, } for (i = IWM_FIRST_OFDM_RATE; i <= IWM_LAST_NON_HT_RATE; i++) { if ((iwm_ridx2rate(rs, i) & IEEE80211_RATE_BASIC) == 0) - continue; + continue; ofdm |= (1 << (i - IWM_FIRST_OFDM_RATE)); if (lowest_present_ofdm == -1 || lowest_present_ofdm > i) lowest_present_ofdm = i; @@ -8394,7 +8394,7 @@ iwm_mac_ctxt_cmd(struct iwm_softc *sc, struct iwm_node *in, uint32_t action, IWM_MAC_FILTER_IN_PROBE_REQUEST | IWM_MAC_FILTER_IN_CRC32); } else if (!assoc || !ni->ni_associd || !ni->ni_dtimperiod) - /* + /* * Allow beacons to pass through as long as we are not * associated or we do not have dtim period information. */ @@ -8553,7 +8553,7 @@ iwm_scan(struct iwm_softc *sc) } int -iwm_bgscan(struct ieee80211com *ic) +iwm_bgscan(struct ieee80211com *ic) { struct iwm_softc *sc = IC2IFP(ic)->if_softc; int err; @@ -8771,7 +8771,7 @@ iwm_auth(struct iwm_softc *sc) return err; } in->in_phyctxt = &sc->sc_phyctxt[0]; - IEEE80211_ADDR_COPY(in->in_macaddr, in->in_ni.ni_macaddr); + IEEE80211_ADDR_COPY(in->in_macaddr, in->in_ni.ni_macaddr); iwm_setrates(in, 0); err = iwm_mac_ctxt_cmd(sc, in, IWM_FW_CTXT_ACTION_ADD, 0); @@ -8809,7 +8809,7 @@ iwm_auth(struct iwm_softc *sc) if (in->in_ni.ni_intval) duration = in->in_ni.ni_intval * 2; else - duration = IEEE80211_DUR_TU; + duration = IEEE80211_DUR_TU; iwm_protect_session(sc, in, duration, in->in_ni.ni_intval / 2); return 0; @@ -8975,7 +8975,7 @@ iwm_run(struct iwm_softc *sc) return err; } #ifdef notyet - /* + /* * Disabled for now. Default beacon filter settings * prevent net80211 from getting ERP and HT protection * updates from beacons. @@ -9240,7 +9240,7 @@ iwm_calib_timeout(void *arg) ic->ic_opmode == IEEE80211_M_STA && ic->ic_bss) { int old_txrate = ni->ni_txrate; ieee80211_amrr_choose(&sc->sc_amrr, &in->in_ni, &in->in_amn); - /* + /* * If AMRR has chosen a new TX rate we must update * the firwmare's LQ rate table. * ni_txrate may change again before the task runs so @@ -10405,7 +10405,7 @@ iwm_init(struct ifnet *ifp) ieee80211_begin_scan(ifp); - /* + /* * ieee80211_begin_scan() ends up scheduling iwm_newstate_task(). * Wait until the transition to SCAN state has completed. */ @@ -11298,7 +11298,7 @@ iwm_rx_pkt(struct iwm_softc *sc, struct iwm_rx_data *data, struct mbuf_list *ml) /* * uCode sets bit 0x80 when it originates the notification, * i.e. when the notification is not a direct response to a - * command sent by the driver. + * command sent by the driver. * For example, uCode issues IWM_REPLY_RX when it sends a * received frame to the driver. */ @@ -11827,7 +11827,7 @@ iwm_attach(struct device *parent, struct device *self, void *aux) sc->sc_hw_rev = (sc->sc_hw_rev & 0xfff0) | (IWM_CSR_HW_REV_STEP(sc->sc_hw_rev << 2) << 2); - + if (iwm_prepare_card_hw(sc) != 0) { printf("%s: could not initialize hardware\n", DEVNAME(sc)); @@ -11867,7 +11867,7 @@ iwm_attach(struct device *parent, struct device *self, void *aux) } } - /* + /* * Allocate DMA memory for firmware transfers. * Must be aligned on a 16-byte boundary. */ @@ -12041,7 +12041,7 @@ fail4: while (--txq_i >= 0) iwm_dma_contig_free(&sc->sched_dma); fail3: if (sc->ict_dma.vaddr != NULL) iwm_dma_contig_free(&sc->ict_dma); - + fail2: iwm_dma_contig_free(&sc->kw_dma); fail1: iwm_dma_contig_free(&sc->fw_dma); return; diff --git a/sys/dev/pci/if_iwmreg.h b/sys/dev/pci/if_iwmreg.h index af10511b1..ea05c7b2b 100644 --- a/sys/dev/pci/if_iwmreg.h +++ b/sys/dev/pci/if_iwmreg.h @@ -6382,7 +6382,7 @@ struct iwm_add_sta_cmd { * ( REPLY_ADD_STA_KEY = 0x17 ) * @sta_id: index of station in uCode's station table * @key_offset: key offset in key storage - * @key_flags: IWM_STA_KEY_FLG_* + * @key_flags: IWM_STA_KEY_FLG_* * @key: key material data * @rx_secur_seq_cnt: RX security sequence counter for the key */ @@ -6484,7 +6484,7 @@ struct iwm_wep_key_cmd { struct iwm_wep_key wep_key[0]; } __packed; /* SEC_CURR_WEP_KEY_CMD_API_S_VER_2 */ -/* +/* * BT coex */ diff --git a/sys/dev/pci/if_iwnreg.h b/sys/dev/pci/if_iwnreg.h index 110efd376..906908b91 100644 --- a/sys/dev/pci/if_iwnreg.h +++ b/sys/dev/pci/if_iwnreg.h @@ -1792,8 +1792,8 @@ static const struct iwn_chan_band { { 11, { 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157 } } }; -#define IWN1000_OTP_NBLOCKS 3 -#define IWN6000_OTP_NBLOCKS 4 +#define IWN1000_OTP_NBLOCKS 3 +#define IWN6000_OTP_NBLOCKS 4 #define IWN6050_OTP_NBLOCKS 7 /* HW rate indices. */ @@ -1809,7 +1809,7 @@ static const struct iwn_rate { uint8_t ht_plcp; uint8_t ht_flags; } iwn_rates[IWN_RIDX_MAX + 1] = { - /* Legacy */ /* HT */ + /* Legacy */ /* HT */ { 2, 10, IWN_RFLAG_CCK, IWN_PLCP_INVALID, 0 }, { 4, 20, IWN_RFLAG_CCK, IWN_PLCP_INVALID, 0 }, { 11, 55, IWN_RFLAG_CCK, IWN_PLCP_INVALID, 0 }, diff --git a/sys/dev/pci/if_iwxreg.h b/sys/dev/pci/if_iwxreg.h index 083ffb9e2..fba5b09a4 100644 --- a/sys/dev/pci/if_iwxreg.h +++ b/sys/dev/pci/if_iwxreg.h @@ -7483,7 +7483,7 @@ struct iwx_add_sta_cmd { * ( REPLY_ADD_STA_KEY = 0x17 ) * @sta_id: index of station in uCode's station table * @key_offset: key offset in key storage - * @key_flags: IWX_STA_KEY_FLG_* + * @key_flags: IWX_STA_KEY_FLG_* * @key: key material data * @rx_secur_seq_cnt: RX security sequence counter for the key */ @@ -7585,7 +7585,7 @@ struct iwx_wep_key_cmd { struct iwx_wep_key wep_key[0]; } __packed; /* SEC_CURR_WEP_KEY_CMD_API_S_VER_2 */ -/* +/* * BT coex */ diff --git a/sys/dev/pci/if_ix.c b/sys/dev/pci/if_ix.c index a832a9a42..09707108f 100644 --- a/sys/dev/pci/if_ix.c +++ b/sys/dev/pci/if_ix.c @@ -3944,12 +3944,12 @@ ix_kstats_read(struct kstat *ks) /* handle the exceptions */ if (sc->hw.mac.type == ixgbe_mac_82598EB) { - kstat_kv_u64(&kvs[ix_counter_lxonrxc]) += + kstat_kv_u64(&kvs[ix_counter_lxonrxc]) += IXGBE_READ_REG(hw, IXGBE_LXONRXC); kstat_kv_u64(&kvs[ix_counter_lxoffrxc]) += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); } else { - kstat_kv_u64(&kvs[ix_counter_lxonrxc]) += + kstat_kv_u64(&kvs[ix_counter_lxonrxc]) += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); kstat_kv_u64(&kvs[ix_counter_lxoffrxc]) += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); diff --git a/sys/dev/pci/if_ixgb.c b/sys/dev/pci/if_ixgb.c index 8ed13cf2f..631694a01 100644 --- a/sys/dev/pci/if_ixgb.c +++ b/sys/dev/pci/if_ixgb.c @@ -900,7 +900,7 @@ ixgb_identify_hardware(struct ixgb_softc *sc) int ixgb_allocate_pci_resources(struct ixgb_softc *sc) - + { int val; pci_intr_handle_t ih; @@ -1092,13 +1092,13 @@ ixgb_dma_malloc(struct ixgb_softc *sc, bus_size_t size, dma->dma_size = size; return (0); -fail_3: +fail_3: bus_dmamem_unmap(dma->dma_tag, dma->dma_vaddr, size); -fail_2: +fail_2: bus_dmamem_free(dma->dma_tag, &dma->dma_seg, dma->dma_nseg); -fail_1: +fail_1: bus_dmamap_destroy(dma->dma_tag, dma->dma_map); -fail_0: +fail_0: dma->dma_map = NULL; dma->dma_tag = NULL; @@ -1813,17 +1813,17 @@ ixgb_rxeof(struct ixgb_softc *sc, int count) * descriptor back to hardware. * * if(Last written back descriptor == EOP bit set descriptor) - * then avoid re-submitting the most recently received RX descriptor + * then avoid re-submitting the most recently received RX descriptor * back to hardware. * if(Last written back descriptor != EOP bit set descriptor) * then avoid re-submitting the most recently received RX descriptors - * till last EOP bit set descriptor. + * till last EOP bit set descriptor. */ if (eop_desc != i) { if (++eop_desc == sc->num_rx_desc) eop_desc = 0; i = eop_desc; - } + } /* Replenish the descriptors with new mbufs till last EOP bit set descriptor */ while (next_to_use != i) { current_desc = &sc->rx_desc_base[next_to_use]; @@ -1837,7 +1837,7 @@ ixgb_rxeof(struct ixgb_softc *sc, int count) break; } /* Advance our pointers to the next descriptor */ - if (++next_to_use == sc->num_rx_desc) + if (++next_to_use == sc->num_rx_desc) next_to_use = 0; } sc->next_rx_desc_to_use = next_to_use; diff --git a/sys/dev/pci/if_ixgb.h b/sys/dev/pci/if_ixgb.h index 358049216..555f6579e 100644 --- a/sys/dev/pci/if_ixgb.h +++ b/sys/dev/pci/if_ixgb.h @@ -126,22 +126,22 @@ typedef int boolean_t; */ #define IXGB_TX_CLEANUP_THRESHOLD (sc->num_tx_desc / 8) -/* - * Flow Control Types. - * 1. ixgb_fc_none - Flow Control Disabled +/* + * Flow Control Types. + * 1. ixgb_fc_none - Flow Control Disabled * 2. ixgb_fc_rx_pause - Flow Control Receive Only * 3. ixgb_fc_tx_pause - Flow Control Transmit Only * 4. ixgb_fc_full - Flow Control Enabled */ -#define FLOW_CONTROL_NONE ixgb_fc_none +#define FLOW_CONTROL_NONE ixgb_fc_none #define FLOW_CONTROL_RX_PAUSE ixgb_fc_rx_pause #define FLOW_CONTROL_TX_PAUSE ixgb_fc_tx_pause #define FLOW_CONTROL_FULL ixgb_fc_full /* * Set the flow control type. Assign one of the above flow control types to be enabled. - * Default Value: FLOW_CONTROL_FULL - */ + * Default Value: FLOW_CONTROL_FULL + */ #define FLOW_CONTROL FLOW_CONTROL_FULL /* @@ -252,7 +252,7 @@ struct ixgb_softc { /* * Transmit definitions - * + * * We have an array of num_tx_desc descriptors (handled by the * controller) paired with an array of tx_buffers (at * tx_buffer_area). The index of the next available descriptor is @@ -271,7 +271,7 @@ struct ixgb_softc { /* * Receive definitions - * + * * we have an array of num_rx_desc rx_desc (handled by the controller), * and paired with an array of rx_buffers (at rx_buffer_area). The * next pair to check on receive is at offset next_rx_desc_to_check diff --git a/sys/dev/pci/if_ixgb_osdep.h b/sys/dev/pci/if_ixgb_osdep.h index 39e0618b3..defc1d840 100644 --- a/sys/dev/pci/if_ixgb_osdep.h +++ b/sys/dev/pci/if_ixgb_osdep.h @@ -41,7 +41,7 @@ POSSIBILITY OF SUCH DAMAGE. #define usec_delay(x) DELAY(x) #define msec_delay(x) DELAY(1000*(x)) -#define DBG 0 +#define DBG 0 #define MSGOUT(S, A, B) printf(S "\n", A, B) #define DEBUGFUNC(F) DEBUGOUT(F); #if DBG diff --git a/sys/dev/pci/if_ixl.c b/sys/dev/pci/if_ixl.c index 5f42dd539..390f91d7e 100644 --- a/sys/dev/pci/if_ixl.c +++ b/sys/dev/pci/if_ixl.c @@ -2807,7 +2807,7 @@ ixl_tx_setup_offload(struct mbuf *m0) offload |= ISSET(m0->m_pkthdr.csum_flags, M_IPV4_CSUM_OUT) ? IXL_TX_DESC_CMD_IIPT_IPV4_CSUM : IXL_TX_DESC_CMD_IIPT_IPV4; - + hlen = ext.ip4->ip_hl << 2; #ifdef INET6 } else if (ext.ip6) { @@ -3232,7 +3232,7 @@ ixl_rxeof(struct ixl_softc *sc, struct ixl_rx_ring *rxr) bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, BUS_DMASYNC_POSTREAD); bus_dmamap_unload(sc->sc_dmat, map); - + m = rxm->rxm_m; rxm->rxm_m = NULL; diff --git a/sys/dev/pci/if_ixlreg.h b/sys/dev/pci/if_ixlreg.h index 3a2bf2474..441c57fec 100644 --- a/sys/dev/pci/if_ixlreg.h +++ b/sys/dev/pci/if_ixlreg.h @@ -2,32 +2,32 @@ /****************************************************************************** - Copyright (c) 2013-2015, Intel Corporation + Copyright (c) 2013-2015, Intel Corporation All rights reserved. - - Redistribution and use in source and binary forms, with or without + + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, + + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the + + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - - 3. Neither the name of the Intel Corporation nor the names of its - contributors may be used to endorse or promote products derived from + + 3. Neither the name of the Intel Corporation nor the names of its + contributors may be used to endorse or promote products derived from this software without specific prior written permission. - + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/sys/dev/pci/if_jme.c b/sys/dev/pci/if_jme.c index 5cab59e9d..4acbd3044 100644 --- a/sys/dev/pci/if_jme.c +++ b/sys/dev/pci/if_jme.c @@ -597,7 +597,7 @@ jme_attach(struct device *parent, struct device *self, void *aux) if (jmedebug) { printf("%s: FPGA revision : 0x%04x\n", - sc->sc_dev.dv_xname, + sc->sc_dev.dv_xname, (reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT); } @@ -1204,7 +1204,7 @@ jme_start(struct ifnet *ifp) if (!(ifp->if_flags & IFF_RUNNING) || ifq_is_oactive(&ifp->if_snd)) return; if ((sc->jme_flags & JME_FLAG_LINK) == 0) - return; + return; if (ifq_empty(&ifp->if_snd)) return; diff --git a/sys/dev/pci/if_lgereg.h b/sys/dev/pci/if_lgereg.h index e31f9aafc..816585075 100644 --- a/sys/dev/pci/if_lgereg.h +++ b/sys/dev/pci/if_lgereg.h @@ -448,7 +448,7 @@ struct lge_tx_desc { #define LGE_INC(x, y) (x) = (x + 1) % y #define LGE_FRAGCNT_1 (1<<16) -#define LGE_FRAGCNT_10 (10<<16) +#define LGE_FRAGCNT_10 (10<<16) #define LGE_FRAGCNT(x) (x<<16) #define LGE_RXBYTES(x) (x->lge_ctl & 0xFFFF) #define LGE_RXTAIL(x) \ diff --git a/sys/dev/pci/if_lii.c b/sys/dev/pci/if_lii.c index 3d0d2f75a..2e4bb600e 100644 --- a/sys/dev/pci/if_lii.c +++ b/sys/dev/pci/if_lii.c @@ -194,7 +194,7 @@ const struct pci_matchid lii_devices[] = { int lii_match(struct device *parent, void *match, void *aux) { - return (pci_matchbyid((struct pci_attach_args *)aux, lii_devices, + return (pci_matchbyid((struct pci_attach_args *)aux, lii_devices, nitems(lii_devices))); } @@ -212,7 +212,7 @@ lii_attach(struct device *parent, struct device *self, void *aux) sc->sc_dmat = pa->pa_dmat; memtype = pci_mapreg_type(sc->sc_pc, sc->sc_tag, PCI_MAPREG_START); - if (pci_mapreg_map(pa, PCI_MAPREG_START, memtype, 0, &sc->sc_mmiot, + if (pci_mapreg_map(pa, PCI_MAPREG_START, memtype, 0, &sc->sc_mmiot, &sc->sc_mmioh, NULL, &sc->sc_mmios, 0)) { printf(": can't map mem space\n"); return; @@ -697,7 +697,7 @@ lii_init(struct ifnet *ifp) } /* - * Initialise MAC. + * Initialise MAC. */ val = LII_READ_4(sc, LII_MACC) & MACC_FDX; diff --git a/sys/dev/pci/if_mcx.c b/sys/dev/pci/if_mcx.c index 1f0767928..9996d63d5 100644 --- a/sys/dev/pci/if_mcx.c +++ b/sys/dev/pci/if_mcx.c @@ -3996,7 +3996,7 @@ mcx_hca_max_caps(struct mcx_softc *sc) */ sc->sc_bf_size = (1 << hca->log_bf_reg_size) / 2; sc->sc_max_rqt_size = (1 << hca->log_max_rqt_size); - + if (hca->local_ca_ack_delay & MCX_CAP_DEVICE_MCAM_REG) sc->sc_mcam_reg = 1; diff --git a/sys/dev/pci/if_msk.c b/sys/dev/pci/if_msk.c index a32f431db..1e62fa73e 100644 --- a/sys/dev/pci/if_msk.c +++ b/sys/dev/pci/if_msk.c @@ -85,7 +85,7 @@ * XMAC registers. This driver takes advantage of these features to allow * both XMACs to operate as independent interfaces. */ - + #include "bpfilter.h" #include "kstat.h" @@ -389,7 +389,7 @@ msk_miibus_readreg(struct device *dev, int phy, int reg) SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) | YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ); - + for (i = 0; i < SK_TIMEOUT; i++) { DELAY(1); val = SK_YU_READ_2(sc_if, YUKON_SMICR); @@ -402,7 +402,7 @@ msk_miibus_readreg(struct device *dev, int phy, int reg) sc_if->sk_dev.dv_xname); return (0); } - + DPRINTFN(9, ("msk_miibus_readreg: i=%d, timeout=%d\n", i, SK_TIMEOUT)); @@ -1852,7 +1852,7 @@ msk_fill_rx_tick(void *xsc_if) void msk_tick(void *xsc_if) { - struct sk_if_softc *sc_if = xsc_if; + struct sk_if_softc *sc_if = xsc_if; struct mii_data *mii = &sc_if->sk_mii; int s; @@ -2049,7 +2049,7 @@ msk_init_yukon(struct sk_if_softc *sc_if) /* Setup Yukon's address */ for (i = 0; i < 3; i++) { /* Write Source Address 1 (unicast filter) */ - SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, + SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, sc_if->arpcom.ac_enaddr[i * 2] | sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8); } @@ -2477,7 +2477,7 @@ msk_dump_bytes(const char *data, int len) if ((j & 0xf) == 7 && j > 0) printf(" "); } - + for (; j < 16; j++) printf(" "); printf(" "); @@ -2486,9 +2486,9 @@ msk_dump_bytes(const char *data, int len) int ch = data[i + j] & 0xff; printf("%c", ' ' <= ch && ch <= '~' ? ch : ' '); } - + printf("\n"); - + if (c < 16) break; } diff --git a/sys/dev/pci/if_myx.c b/sys/dev/pci/if_myx.c index a4084487d..c76273ad5 100644 --- a/sys/dev/pci/if_myx.c +++ b/sys/dev/pci/if_myx.c @@ -2070,7 +2070,7 @@ myx_tx_empty(struct myx_softc *sc) while (cons != prod) { ms = &sc->sc_tx_slots[cons]; - + bus_dmamap_sync(sc->sc_dmat, ms->ms_map, 0, ms->ms_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); bus_dmamap_unload(sc->sc_dmat, ms->ms_map); diff --git a/sys/dev/pci/if_nep.c b/sys/dev/pci/if_nep.c index 64c8d6a48..8b4dd6a64 100644 --- a/sys/dev/pci/if_nep.c +++ b/sys/dev/pci/if_nep.c @@ -745,14 +745,14 @@ next: desc = buf + sizeof(*vpd); - /* + /* * ...which is an instance property... */ if (desc[0] != 'I') continue; desc += 3; - /* + /* * ...that's a byte array with the proper * length for a MAC address... */ @@ -766,7 +766,7 @@ next: if (strcmp(desc, "local-mac-address") != 0) continue; desc += strlen("local-mac-address") + 1; - + memcpy(sc->sc_ac.ac_enaddr, desc, ETHER_ADDR_LEN); sc->sc_ac.ac_enaddr[5] += pa->pa_function; rv = 0; @@ -995,7 +995,7 @@ nep_rx_proc(struct nep_softc *sc) bus_dmamap_sync(sc->sc_dmat, NEP_DMA_MAP(sc->sc_rcring), 0, NEP_DMA_LEN(sc->sc_rcring), BUS_DMASYNC_POSTREAD); - + count = nep_read(sc, RCRSTAT_A(sc->sc_port)); while (count > 0) { idx = sc->sc_rx_cons; @@ -1573,7 +1573,7 @@ nep_up(struct nep_softc *sc) sc->sc_rx_prod = 0; if_rxr_init(&sc->sc_rx_ring, 16, NEP_NRBDESC); - + /* Allocate Rx completion descriptor ring. */ sc->sc_rcring = nep_dmamem_alloc(sc, NEP_NRCDESC * sizeof(uint64_t)); if (sc->sc_rcring == NULL) @@ -2001,7 +2001,7 @@ nep_fill_rx_ring(struct nep_softc *sc) break; } rb->nb_block = block; - sc->sc_rbdesc[desc++] = + sc->sc_rbdesc[desc++] = htole32(rb->nb_map->dm_segs[0].ds_addr >> 12); count++; slots--; diff --git a/sys/dev/pci/if_ngbe.c b/sys/dev/pci/if_ngbe.c index 25f07ffe3..deed46de8 100644 --- a/sys/dev/pci/if_ngbe.c +++ b/sys/dev/pci/if_ngbe.c @@ -364,8 +364,8 @@ ngbe_detach(struct device *self, int flags) ngbe_free_pci_resources(sc); - ngbe_free_transmit_structures(sc); - ngbe_free_receive_structures(sc); + ngbe_free_transmit_structures(sc); + ngbe_free_receive_structures(sc); ngbe_free_isb(sc); free(sc->mta, M_DEVBUF, ETHER_ADDR_LEN * NGBE_SP_RAR_ENTRIES); @@ -416,7 +416,7 @@ ngbe_init(void *arg) ngbe_setup_isb(sc); - /* Setup the receive address. */ + /* Setup the receive address. */ hw->mac.ops.set_rar(sc, 0, hw->mac.addr, 0, NGBE_PSR_MAC_SWC_AD_H_AV); /* Get the latest mac address, user can use a LAA. */ @@ -642,7 +642,7 @@ ngbe_rxfill(struct rx_ring *rxr) int i, post = 0; u_int slots; - bus_dmamap_sync(rxr->rxdma.dma_tag, rxr->rxdma.dma_map, 0, + bus_dmamap_sync(rxr->rxdma.dma_tag, rxr->rxdma.dma_map, 0, rxr->rxdma.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); i = rxr->last_desc_filled; @@ -872,7 +872,7 @@ ngbe_update_link_status(struct ngbe_softc *sc) ~NGBE_MAC_TX_CFG_SPEED_MASK) | NGBE_MAC_TX_CFG_TE | NGBE_MAC_TX_CFG_SPEED_1G); } - + reg = NGBE_READ_REG(hw, NGBE_MAC_RX_CFG); NGBE_WRITE_REG(hw, NGBE_MAC_RX_CFG, reg); NGBE_WRITE_REG(hw, NGBE_MAC_PKT_FLT, NGBE_MAC_PKT_FLT_PR); @@ -1022,7 +1022,7 @@ ngbe_setup_interface(struct ngbe_softc *sc) ifp->if_ioctl = ngbe_ioctl; ifp->if_qstart = ngbe_start; ifp->if_watchdog = ngbe_watchdog; - ifp->if_hardmtu = NGBE_MAX_JUMBO_FRAME_SIZE - ETHER_HDR_LEN - + ifp->if_hardmtu = NGBE_MAX_JUMBO_FRAME_SIZE - ETHER_HDR_LEN - ETHER_CRC_LEN; ifq_set_maxlen(&ifp->if_snd, sc->num_tx_desc - 1); @@ -1184,7 +1184,7 @@ ngbe_allocate_queues(struct ngbe_softc *sc) printf("%s: unable to allocate Tx ring\n", DEVNAME(sc)); goto fail; } - + /* Allocate the Rx ring. */ sc->rx_rings = mallocarray(sc->sc_nqueues, sizeof(struct rx_ring), M_DEVBUF, M_NOWAIT | M_ZERO); @@ -1516,7 +1516,7 @@ ngbe_addr_list_itr(struct ngbe_hw *hw, uint8_t **mc_addr_ptr, uint32_t *vmdq) return addr; } -void +void ngbe_iff(struct ngbe_softc *sc) { struct ngbe_hw *hw = &sc->hw; @@ -1596,7 +1596,7 @@ ngbe_initialize_receive_unit(struct ngbe_softc *sc) mhadd = NGBE_READ_REG(hw, NGBE_PSR_MAX_SZ); if (mhadd != NGBE_MAX_JUMBO_FRAME_SIZE) NGBE_WRITE_REG(hw, NGBE_PSR_MAX_SZ, NGBE_MAX_JUMBO_FRAME_SIZE); - + bufsz = MCLBYTES >> NGBE_PX_RR_CFG_BSIZEPKT_SHIFT; for (i = 0; i < sc->sc_nqueues; i++, rxr++) { @@ -1831,7 +1831,7 @@ ngbe_init_hw(struct ngbe_softc *sc) /* Reset the hardware */ status = hw->mac.ops.reset_hw(sc); - + if (!status) status = hw->mac.ops.start_hw(sc); @@ -1956,7 +1956,7 @@ ngbe_init_shared_code(struct ngbe_softc *sc) struct ngbe_hw *hw = &sc->hw; hw->subsystem_device_id = PCI_PRODUCT(pci_conf_read(pa->pa_pc, - pa->pa_tag, PCI_SUBSYS_ID_REG)); + pa->pa_tag, PCI_SUBSYS_ID_REG)); hw->phy.type = ngbe_phy_internal; @@ -2312,7 +2312,7 @@ ngbe_check_mac_link(struct ngbe_hw *hw, uint32_t *speed, int *link_up, *speed = NGBE_LINK_SPEED_10_FULL; } else *speed = NGBE_LINK_SPEED_UNKNOWN; - + return status; } @@ -2418,7 +2418,7 @@ void ngbe_configure_pb(struct ngbe_softc *sc) { struct ngbe_hw *hw = &sc->hw; - + hw->mac.ops.setup_rxpba(hw, 0, 0, PBA_STRATEGY_EQUAL); ngbe_pbthresh_setup(sc); } @@ -2796,7 +2796,7 @@ ngbe_get_eeprom_semaphore(struct ngbe_softc *sc) if (!(swsm & NGBE_MIS_SWSM_SMBI)) { status = 0; break; - } + } DELAY(50); } @@ -2812,7 +2812,7 @@ ngbe_get_eeprom_semaphore(struct ngbe_softc *sc) ngbe_release_eeprom_semaphore(hw); DELAY(50); - /* + /* * One last try if the SMBI bit is 0 when we read it, * then the bit will be set and we have the semaphore. */ @@ -2977,8 +2977,8 @@ ngbe_host_interface_command(struct ngbe_softc *sc, uint32_t *buffer, dword_len = length >> 2; - /* - * The device driver writes the relevant command block + /* + * The device driver writes the relevant command block * into the ram area. */ for (i = 0; i < dword_len; i++) { @@ -2999,7 +2999,7 @@ ngbe_host_interface_command(struct ngbe_softc *sc, uint32_t *buffer, status = EINVAL; goto rel_out; } - + for (i = 0; i < timeout; i++) { if (ngbe_check_mng_access(hw)) { hicr = NGBE_READ_REG(hw, NGBE_MNG_MBOX_CTL); @@ -3025,7 +3025,7 @@ ngbe_host_interface_command(struct ngbe_softc *sc, uint32_t *buffer, /* Calculate length in DWORDs */ dword_len = hdr_size >> 2; - + /* First pull in the header so we know the buffer length */ for (bi = 0; bi < dword_len; bi++) { if (ngbe_check_mng_access(hw)) { @@ -3048,7 +3048,7 @@ ngbe_host_interface_command(struct ngbe_softc *sc, uint32_t *buffer, status = EINVAL; goto rel_out; } - + /* Calculate length in DWORDs, add 3 for odd lengths */ dword_len = (buf_len + 3) >> 2; @@ -3206,7 +3206,7 @@ ngbe_pbthresh_setup(struct ngbe_softc *sc) hw->fc.high_water = ngbe_hpbthresh(sc); hw->fc.low_water = ngbe_lpbthresh(sc); - + /* Low water marks must not be larger than high water marks */ if (hw->fc.low_water > hw->fc.high_water) hw->fc.low_water = 0; @@ -3549,7 +3549,7 @@ ngbe_phy_setup_link(struct ngbe_softc *sc, uint32_t speed, int need_restart) hw->phy.ops.read_reg(hw, 9, 0, &value); if (!(speed & NGBE_LINK_SPEED_1GB_FULL)) value &= 0xfdff; - else + else value |= 0x200; hw->phy.ops.write_reg(hw, 9, 0, value); @@ -3574,7 +3574,7 @@ ngbe_phy_setup_link(struct ngbe_softc *sc, uint32_t speed, int need_restart) skip_an: hw->phy.ops.phy_led_ctrl(sc); hw->phy.ops.check_event(sc); - + return 0; } @@ -3720,7 +3720,7 @@ ngbe_reset_hw(struct ngbe_softc *sc) break; msec_delay(100); } - + if (reset_status & NGBE_MIS_RST_ST_DEV_RST_ST_MASK) { status = ETIMEDOUT; printf("%s: software reset polling failed to " @@ -4006,7 +4006,7 @@ ngbe_set_rx_drop_en(struct ngbe_softc *sc) srrctl |= NGBE_PX_RR_CFG_DROP_EN; NGBE_WRITE_REG(&sc->hw, NGBE_PX_RR_CFG(i), srrctl); } - + } else { for (i = 0; i < sc->sc_nqueues; i++) { srrctl = NGBE_READ_REG(&sc->hw, NGBE_PX_RR_CFG(i)); @@ -4099,7 +4099,7 @@ ngbe_setup_fc(struct ngbe_softc *sc) /* Flow control completely disabled by software override. */ break; case ngbe_fc_tx_pause: - /* + /* * Tx Flow control is enabled, and Rx Flow control is * disabled by software override. */ diff --git a/sys/dev/pci/if_nge.c b/sys/dev/pci/if_nge.c index 2ea84b9e5..89dc0028e 100644 --- a/sys/dev/pci/if_nge.c +++ b/sys/dev/pci/if_nge.c @@ -551,7 +551,7 @@ nge_miibus_statchg(struct device *dev) } txcfg |= NGE_TXCFG_AUTOPAD; - + CSR_WRITE_4(sc, NGE_TX_CFG, txcfg); CSR_WRITE_4(sc, NGE_RX_CFG, rxcfg); @@ -810,7 +810,7 @@ nge_attach(struct device *parent, struct device *self, void *aux) DPRINTFN(5, ("%s: TBI mode\n", sc->sc_dv.dv_xname)); sc->nge_tbi = 1; - ifmedia_init(&sc->nge_ifmedia, 0, nge_ifmedia_tbi_upd, + ifmedia_init(&sc->nge_ifmedia, 0, nge_ifmedia_tbi_upd, nge_ifmedia_tbi_sts); ifmedia_add(&sc->nge_ifmedia, IFM_ETHER|IFM_NONE, 0, NULL), @@ -820,10 +820,10 @@ nge_attach(struct device *parent, struct device *self, void *aux) ifmedia_add(&sc->nge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); ifmedia_set(&sc->nge_ifmedia, IFM_ETHER|IFM_AUTO); - + CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) - | NGE_GPIO_GP4_OUT - | NGE_GPIO_GP1_OUTENB | NGE_GPIO_GP2_OUTENB + | NGE_GPIO_GP4_OUT + | NGE_GPIO_GP1_OUTENB | NGE_GPIO_GP2_OUTENB | NGE_GPIO_GP3_OUTENB | NGE_GPIO_GP4_OUTENB | NGE_GPIO_GP5_OUTENB); @@ -838,9 +838,9 @@ nge_attach(struct device *parent, struct device *self, void *aux) nge_ifmedia_mii_sts); mii_attach(&sc->sc_dv, &sc->nge_mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0); - + if (LIST_FIRST(&sc->nge_mii.mii_phys) == NULL) { - + printf("%s: no PHY found!\n", sc->sc_dv.dv_xname); ifmedia_add(&sc->nge_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); @@ -1193,15 +1193,15 @@ nge_tick(void *xsc) splx(s); return; } - + anlpar = CSR_READ_4(sc, NGE_TBI_ANLPAR); txcfg = CSR_READ_4(sc, NGE_TX_CFG); rxcfg = CSR_READ_4(sc, NGE_RX_CFG); - + DPRINTFN(2, ("%s: nge_tick: anlpar=%#x, txcfg=%#x, " "rxcfg=%#x\n", sc->sc_dv.dv_xname, anlpar, txcfg, rxcfg)); - + if (anlpar == 0 || anlpar & NGE_TBIANAR_FDX) { txcfg |= (NGE_TXCFG_IGN_HBEAT| NGE_TXCFG_IGN_CARR); @@ -1231,7 +1231,7 @@ nge_tick(void *xsc) if (!ifq_empty(&ifp->if_snd)) nge_start(ifp); } - + } splx(s); @@ -1295,7 +1295,7 @@ nge_intr(void *arg) } #if 0 - /* + /* * XXX: nge_tick() is not ready to be called this way * it screws up the aneg timeout because mii_tick() is * only to be called once per second. @@ -1577,7 +1577,7 @@ nge_init(void *xsc) } txcfg |= NGE_TXCFG_AUTOPAD; - + CSR_WRITE_4(sc, NGE_TX_CFG, txcfg); CSR_WRITE_4(sc, NGE_RX_CFG, rxcfg); @@ -1675,7 +1675,7 @@ nge_ifmedia_tbi_upd(struct ifnet *ifp) sc->nge_link = 0; - if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) + if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) == IFM_AUTO) { u_int32_t anar, bmcr; anar = CSR_READ_4(sc, NGE_TBI_ANAR); @@ -1706,7 +1706,7 @@ nge_ifmedia_tbi_upd(struct ifnet *ifp) CSR_WRITE_4(sc, NGE_TX_CFG, txcfg); CSR_WRITE_4(sc, NGE_RX_CFG, rxcfg); } - + NGE_CLRBIT(sc, NGE_GPIO, NGE_GPIO_GP3_OUT); return(0); @@ -1722,12 +1722,12 @@ nge_ifmedia_tbi_sts(struct ifnet *ifp, struct ifmediareq *ifmr) u_int32_t bmcr; bmcr = CSR_READ_4(sc, NGE_TBI_BMCR); - + if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) == IFM_AUTO) { u_int32_t bmsr = CSR_READ_4(sc, NGE_TBI_BMSR); DPRINTFN(2, ("%s: nge_ifmedia_tbi_sts bmsr=%#x, bmcr=%#x\n", sc->sc_dv.dv_xname, bmsr, bmcr)); - + if (!(bmsr & NGE_TBIBMSR_ANEG_DONE)) { ifmr->ifm_active = IFM_ETHER|IFM_NONE; ifmr->ifm_status = IFM_AVALID; @@ -1737,18 +1737,18 @@ nge_ifmedia_tbi_sts(struct ifnet *ifp, struct ifmediareq *ifmr) DPRINTFN(2, ("%s: nge_ifmedia_tbi_sts bmcr=%#x\n", sc->sc_dv.dv_xname, bmcr)); } - + ifmr->ifm_status = IFM_AVALID|IFM_ACTIVE; ifmr->ifm_active = IFM_ETHER|IFM_1000_SX; - + if (bmcr & NGE_TBIBMCR_LOOPBACK) ifmr->ifm_active |= IFM_LOOP; - + if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) == IFM_AUTO) { u_int32_t anlpar = CSR_READ_4(sc, NGE_TBI_ANLPAR); DPRINTFN(2, ("%s: nge_ifmedia_tbi_sts anlpar=%#x\n", sc->sc_dv.dv_xname, anlpar)); - + ifmr->ifm_active |= IFM_AUTO; if (anlpar & NGE_TBIANLPAR_FDX) { ifmr->ifm_active |= IFM_FDX; @@ -1756,12 +1756,12 @@ nge_ifmedia_tbi_sts(struct ifnet *ifp, struct ifmediareq *ifmr) ifmr->ifm_active |= IFM_HDX; } else ifmr->ifm_active |= IFM_FDX; - + } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) == IFM_FDX) ifmr->ifm_active |= IFM_FDX; else ifmr->ifm_active |= IFM_HDX; - + } int @@ -1811,7 +1811,7 @@ nge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) case SIOCGIFMEDIA: case SIOCSIFMEDIA: if (sc->nge_tbi) { - error = ifmedia_ioctl(ifp, ifr, &sc->nge_ifmedia, + error = ifmedia_ioctl(ifp, ifr, &sc->nge_ifmedia, command); } else { mii = &sc->nge_mii; diff --git a/sys/dev/pci/if_ngereg.h b/sys/dev/pci/if_ngereg.h index 7b92f0ec5..eb0a1f1b3 100644 --- a/sys/dev/pci/if_ngereg.h +++ b/sys/dev/pci/if_ngereg.h @@ -470,7 +470,7 @@ * After this, we include some additional structure members for * use by the driver. Note that for this structure will be a different * size on the alpha, but that's okay as long as it's a multiple of 4 - * bytes in size. + * bytes in size. * */ struct nge_desc_64 { diff --git a/sys/dev/pci/if_pcn.c b/sys/dev/pci/if_pcn.c index f5661f45e..c3cd8106b 100644 --- a/sys/dev/pci/if_pcn.c +++ b/sys/dev/pci/if_pcn.c @@ -1911,9 +1911,9 @@ pcn_79c971_mediainit(struct pcn_softc *sc) /* * The built-in 10BASE-T interface is mapped to the MII * on the PCNet-FAST. Unfortunately, there's no EEPROM - * word that tells us which PHY to use. - * This driver used to ignore all but the first PHY to - * answer, but this code was removed to support multiple + * word that tells us which PHY to use. + * This driver used to ignore all but the first PHY to + * answer, but this code was removed to support multiple * external PHYs. As the default instance will be the first * one to answer, no harm is done by letting the possibly * non-connected internal PHY show up. diff --git a/sys/dev/pci/if_rge.c b/sys/dev/pci/if_rge.c index 51f316de3..f0b45d628 100644 --- a/sys/dev/pci/if_rge.c +++ b/sys/dev/pci/if_rge.c @@ -176,7 +176,7 @@ rge_attach(struct device *parent, struct device *self, void *aux) pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0); - /* + /* * Map control/status registers. */ if (pci_mapreg_map(pa, RGE_PCI_BAR2, PCI_MAPREG_TYPE_MEM | @@ -205,7 +205,7 @@ rge_attach(struct device *parent, struct device *self, void *aux) sc->sc_queues = q; sc->sc_nqueues = 1; - /* + /* * Allocate interrupt. */ if (pci_intr_map_msi(pa, &ih) == 0) @@ -252,7 +252,7 @@ rge_attach(struct device *parent, struct device *self, void *aux) rge_config_imtype(sc, RGE_IMTYPE_SIM); - /* + /* * PCI Express check. */ if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, @@ -960,7 +960,7 @@ rge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) } } -/* +/* * Allocate memory for RX/TX rings. */ int @@ -1213,7 +1213,7 @@ rge_rxeof(struct rge_queues *q) rxstat = letoh32(cur_rx->hi_qword1.rx_qword4.rge_cmdsts); extsts = letoh32(cur_rx->hi_qword1.rx_qword4.rge_extsts); - + total_len = RGE_RXBYTES(cur_rx); rxq = &q->q_rx.rge_rxq[i]; m = rxq->rxq_mbuf; @@ -1336,7 +1336,7 @@ rge_txeof(struct rge_queues *q) break; } - bus_dmamap_sync(sc->sc_dmat, txq->txq_dmamap, 0, + bus_dmamap_sync(sc->sc_dmat, txq->txq_dmamap, 0, txq->txq_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); bus_dmamap_unload(sc->sc_dmat, txq->txq_dmamap); m_freem(txq->txq_mbuf); @@ -1612,7 +1612,7 @@ rge_phy_config_mac_cfg3(struct rge_softc *sc) 0x00bb, 0x0058, 0x0029, 0x0013, 0x0009, 0x0004, 0x0002 }; static const uint16_t mac_cfg3_b88e_value[] = - { 0xc091, 0x6e12, 0xc092, 0x1214, 0xc094, 0x1516, 0xc096, 0x171b, + { 0xc091, 0x6e12, 0xc092, 0x1214, 0xc094, 0x1516, 0xc096, 0x171b, 0xc098, 0x1b1c, 0xc09a, 0x1f1f, 0xc09c, 0x2021, 0xc09e, 0x2224, 0xc0a0, 0x2424, 0xc0a2, 0x2424, 0xc0a4, 0x2424, 0xc018, 0x0af2, 0xc01a, 0x0d4a, 0xc01c, 0x0f26, 0xc01e, 0x118d, 0xc020, 0x14f3, @@ -1712,11 +1712,11 @@ rge_phy_config_mac_cfg4(struct rge_softc *sc) uint16_t val; int i; static const uint16_t mac_cfg4_b87c_value[] = - { 0x8013, 0x0700, 0x8fb9, 0x2801, 0x8fba, 0x0100, 0x8fbc, 0x1900, - 0x8fbe, 0xe100, 0x8fc0, 0x0800, 0x8fc2, 0xe500, 0x8fc4, 0x0f00, - 0x8fc6, 0xf100, 0x8fc8, 0x0400, 0x8fca, 0xf300, 0x8fcc, 0xfd00, - 0x8fce, 0xff00, 0x8fd0, 0xfb00, 0x8fd2, 0x0100, 0x8fd4, 0xf400, - 0x8fd6, 0xff00, 0x8fd8, 0xf600, 0x813d, 0x390e, 0x814f, 0x790e, + { 0x8013, 0x0700, 0x8fb9, 0x2801, 0x8fba, 0x0100, 0x8fbc, 0x1900, + 0x8fbe, 0xe100, 0x8fc0, 0x0800, 0x8fc2, 0xe500, 0x8fc4, 0x0f00, + 0x8fc6, 0xf100, 0x8fc8, 0x0400, 0x8fca, 0xf300, 0x8fcc, 0xfd00, + 0x8fce, 0xff00, 0x8fd0, 0xfb00, 0x8fd2, 0x0100, 0x8fd4, 0xf400, + 0x8fd6, 0xff00, 0x8fd8, 0xf600, 0x813d, 0x390e, 0x814f, 0x790e, 0x80b0, 0x0f31 }; for (i = 0; i < nitems(rtl8125_mac_cfg4_ephy); i++) @@ -1865,8 +1865,8 @@ rge_phy_config_mac_cfg4(struct rge_softc *sc) val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; rge_write_phy_ocp(sc, 0xa438, val | 0xc000); rge_patch_phy_mcu(sc, 1); - RGE_PHY_CLRBIT(sc, 0xb896, 0x0001); - RGE_PHY_CLRBIT(sc, 0xb892, 0xff00); + RGE_PHY_CLRBIT(sc, 0xb896, 0x0001); + RGE_PHY_CLRBIT(sc, 0xb892, 0xff00); rge_write_phy_ocp(sc, 0xb88e, 0xc23e); rge_write_phy_ocp(sc, 0xb890, 0x0000); rge_write_phy_ocp(sc, 0xb88e, 0xc240); @@ -1881,10 +1881,10 @@ rge_phy_config_mac_cfg4(struct rge_softc *sc) rge_write_phy_ocp(sc, 0xb890, 0x1012); rge_write_phy_ocp(sc, 0xb88e, 0xc24a); rge_write_phy_ocp(sc, 0xb890, 0x1416); - RGE_PHY_SETBIT(sc, 0xb896, 0x0001); + RGE_PHY_SETBIT(sc, 0xb896, 0x0001); rge_patch_phy_mcu(sc, 0); - RGE_PHY_SETBIT(sc, 0xa86a, 0x0001); - RGE_PHY_SETBIT(sc, 0xa6f0, 0x0001); + RGE_PHY_SETBIT(sc, 0xa86a, 0x0001); + RGE_PHY_SETBIT(sc, 0xa6f0, 0x0001); rge_write_phy_ocp(sc, 0xbfa0, 0xd70d); rge_write_phy_ocp(sc, 0xbfa2, 0x4100); rge_write_phy_ocp(sc, 0xbfa4, 0xe868); @@ -1892,7 +1892,7 @@ rge_phy_config_mac_cfg4(struct rge_softc *sc) rge_write_phy_ocp(sc, 0xb54c, 0x3c18); RGE_PHY_CLRBIT(sc, 0xbfa4, 0x0020); rge_write_phy_ocp(sc, 0xa436, 0x817d); - RGE_PHY_SETBIT(sc, 0xa438, 0x1000); + RGE_PHY_SETBIT(sc, 0xa438, 0x1000); } void diff --git a/sys/dev/pci/if_rgereg.h b/sys/dev/pci/if_rgereg.h index 6cedaf8e4..fdca231cf 100644 --- a/sys/dev/pci/if_rgereg.h +++ b/sys/dev/pci/if_rgereg.h @@ -81,7 +81,7 @@ #define RGE_ISR_TX_OK 0x00000004 #define RGE_ISR_TX_ERR 0x00000008 #define RGE_ISR_RX_DESC_UNAVAIL 0x00000010 -#define RGE_ISR_LINKCHG 0x00000020 +#define RGE_ISR_LINKCHG 0x00000020 #define RGE_ISR_RX_FIFO_OFLOW 0x00000040 #define RGE_ISR_TX_DESC_UNAVAIL 0x00000080 #define RGE_ISR_SWI 0x00000100 @@ -463,112 +463,112 @@ static const struct { uint16_t reg; uint16_t val; } rtl8125_mac_bps[] = { - { 0xf800, 0xe008 }, { 0xf802, 0xe01e }, { 0xf804, 0xe02e }, - { 0xf806, 0xe054 }, { 0xf808, 0xe057 }, { 0xf80a, 0xe059 }, - { 0xf80c, 0xe0c2 }, { 0xf80e, 0xe0cb }, { 0xf810, 0x9996 }, - { 0xf812, 0x49d1 }, { 0xf814, 0xf005 }, { 0xf816, 0x49d4 }, - { 0xf818, 0xf10a }, { 0xf81a, 0x49d8 }, { 0xf81c, 0xf108 }, - { 0xf81e, 0xc00f }, { 0xf820, 0x7100 }, { 0xf822, 0x209c }, - { 0xf824, 0x249c }, { 0xf826, 0xc009 }, { 0xf828, 0x9900 }, - { 0xf82a, 0xe004 }, { 0xf82c, 0xc006 }, { 0xf82e, 0x1900 }, - { 0xf830, 0x9900 }, { 0xf832, 0xc602 }, { 0xf834, 0xbe00 }, - { 0xf836, 0x5a48 }, { 0xf838, 0xe0c2 }, { 0xf83a, 0x0004 }, - { 0xf83c, 0xe10a }, { 0xf83e, 0xc60f }, { 0xf840, 0x73c4 }, - { 0xf842, 0x49b3 }, { 0xf844, 0xf106 }, { 0xf846, 0x73c2 }, - { 0xf848, 0xc608 }, { 0xf84a, 0xb406 }, { 0xf84c, 0xc609 }, - { 0xf84e, 0xff80 }, { 0xf850, 0xc605 }, { 0xf852, 0xb406 }, - { 0xf854, 0xc605 }, { 0xf856, 0xff80 }, { 0xf858, 0x0544 }, - { 0xf85a, 0x0568 }, { 0xf85c, 0xe906 }, { 0xf85e, 0xcde8 }, - { 0xf860, 0xc724 }, { 0xf862, 0xc624 }, { 0xf864, 0x9ee2 }, - { 0xf866, 0x1e01 }, { 0xf868, 0x9ee0 }, { 0xf86a, 0x76e0 }, - { 0xf86c, 0x49e0 }, { 0xf86e, 0xf1fe }, { 0xf870, 0x76e6 }, - { 0xf872, 0x486d }, { 0xf874, 0x4868 }, { 0xf876, 0x9ee4 }, - { 0xf878, 0x1e03 }, { 0xf87a, 0x9ee0 }, { 0xf87c, 0x76e0 }, - { 0xf87e, 0x49e0 }, { 0xf880, 0xf1fe }, { 0xf882, 0xc615 }, - { 0xf884, 0x9ee2 }, { 0xf886, 0x1e01 }, { 0xf888, 0x9ee0 }, - { 0xf88a, 0x76e0 }, { 0xf88c, 0x49e0 }, { 0xf88e, 0xf1fe }, - { 0xf890, 0x76e6 }, { 0xf892, 0x486f }, { 0xf894, 0x9ee4 }, - { 0xf896, 0x1e03 }, { 0xf898, 0x9ee0 }, { 0xf89a, 0x76e0 }, - { 0xf89c, 0x49e0 }, { 0xf89e, 0xf1fe }, { 0xf8a0, 0x7196 }, - { 0xf8a2, 0xc702 }, { 0xf8a4, 0xbf00 }, { 0xf8a6, 0x5a44 }, - { 0xf8a8, 0xeb0e }, { 0xf8aa, 0x0070 }, { 0xf8ac, 0x00c3 }, - { 0xf8ae, 0x1bc0 }, { 0xf8b0, 0xc602 }, { 0xf8b2, 0xbe00 }, - { 0xf8b4, 0x0e26 }, { 0xf8b6, 0xc602 }, { 0xf8b8, 0xbe00 }, - { 0xf8ba, 0x0eba }, { 0xf8bc, 0x1501 }, { 0xf8be, 0xf02a }, - { 0xf8c0, 0x1500 }, { 0xf8c2, 0xf15d }, { 0xf8c4, 0xc661 }, - { 0xf8c6, 0x75c8 }, { 0xf8c8, 0x49d5 }, { 0xf8ca, 0xf00a }, - { 0xf8cc, 0x49d6 }, { 0xf8ce, 0xf008 }, { 0xf8d0, 0x49d7 }, - { 0xf8d2, 0xf006 }, { 0xf8d4, 0x49d8 }, { 0xf8d6, 0xf004 }, - { 0xf8d8, 0x75d2 }, { 0xf8da, 0x49d9 }, { 0xf8dc, 0xf150 }, - { 0xf8de, 0xc553 }, { 0xf8e0, 0x77a0 }, { 0xf8e2, 0x75c8 }, - { 0xf8e4, 0x4855 }, { 0xf8e6, 0x4856 }, { 0xf8e8, 0x4857 }, - { 0xf8ea, 0x4858 }, { 0xf8ec, 0x48da }, { 0xf8ee, 0x48db }, - { 0xf8f0, 0x49fe }, { 0xf8f2, 0xf002 }, { 0xf8f4, 0x485a }, - { 0xf8f6, 0x49ff }, { 0xf8f8, 0xf002 }, { 0xf8fa, 0x485b }, - { 0xf8fc, 0x9dc8 }, { 0xf8fe, 0x75d2 }, { 0xf900, 0x4859 }, - { 0xf902, 0x9dd2 }, { 0xf904, 0xc643 }, { 0xf906, 0x75c0 }, - { 0xf908, 0x49d4 }, { 0xf90a, 0xf033 }, { 0xf90c, 0x49d0 }, - { 0xf90e, 0xf137 }, { 0xf910, 0xe030 }, { 0xf912, 0xc63a }, - { 0xf914, 0x75c8 }, { 0xf916, 0x49d5 }, { 0xf918, 0xf00e }, - { 0xf91a, 0x49d6 }, { 0xf91c, 0xf00c }, { 0xf91e, 0x49d7 }, - { 0xf920, 0xf00a }, { 0xf922, 0x49d8 }, { 0xf924, 0xf008 }, - { 0xf926, 0x75d2 }, { 0xf928, 0x49d9 }, { 0xf92a, 0xf005 }, - { 0xf92c, 0xc62e }, { 0xf92e, 0x75c0 }, { 0xf930, 0x49d7 }, - { 0xf932, 0xf125 }, { 0xf934, 0xc528 }, { 0xf936, 0x77a0 }, - { 0xf938, 0xc627 }, { 0xf93a, 0x75c8 }, { 0xf93c, 0x4855 }, - { 0xf93e, 0x4856 }, { 0xf940, 0x4857 }, { 0xf942, 0x4858 }, - { 0xf944, 0x48da }, { 0xf946, 0x48db }, { 0xf948, 0x49fe }, - { 0xf94a, 0xf002 }, { 0xf94c, 0x485a }, { 0xf94e, 0x49ff }, - { 0xf950, 0xf002 }, { 0xf952, 0x485b }, { 0xf954, 0x9dc8 }, - { 0xf956, 0x75d2 }, { 0xf958, 0x4859 }, { 0xf95a, 0x9dd2 }, - { 0xf95c, 0xc616 }, { 0xf95e, 0x75c0 }, { 0xf960, 0x4857 }, - { 0xf962, 0x9dc0 }, { 0xf964, 0xc613 }, { 0xf966, 0x75c0 }, - { 0xf968, 0x49da }, { 0xf96a, 0xf003 }, { 0xf96c, 0x49d0 }, - { 0xf96e, 0xf107 }, { 0xf970, 0xc60b }, { 0xf972, 0xc50e }, - { 0xf974, 0x48d9 }, { 0xf976, 0x9dc0 }, { 0xf978, 0x4859 }, - { 0xf97a, 0x9dc0 }, { 0xf97c, 0xc608 }, { 0xf97e, 0xc702 }, - { 0xf980, 0xbf00 }, { 0xf982, 0x3ae0 }, { 0xf984, 0xe860 }, - { 0xf986, 0xb400 }, { 0xf988, 0xb5d4 }, { 0xf98a, 0xe908 }, - { 0xf98c, 0xe86c }, { 0xf98e, 0x1200 }, { 0xf990, 0xc409 }, - { 0xf992, 0x6780 }, { 0xf994, 0x48f1 }, { 0xf996, 0x8f80 }, - { 0xf998, 0xc404 }, { 0xf99a, 0xc602 }, { 0xf99c, 0xbe00 }, - { 0xf99e, 0x10aa }, { 0xf9a0, 0xc010 }, { 0xf9a2, 0xea7c }, - { 0xf9a4, 0xc602 }, { 0xf9a6, 0xbe00 }, { 0xf9a8, 0x0000 }, + { 0xf800, 0xe008 }, { 0xf802, 0xe01e }, { 0xf804, 0xe02e }, + { 0xf806, 0xe054 }, { 0xf808, 0xe057 }, { 0xf80a, 0xe059 }, + { 0xf80c, 0xe0c2 }, { 0xf80e, 0xe0cb }, { 0xf810, 0x9996 }, + { 0xf812, 0x49d1 }, { 0xf814, 0xf005 }, { 0xf816, 0x49d4 }, + { 0xf818, 0xf10a }, { 0xf81a, 0x49d8 }, { 0xf81c, 0xf108 }, + { 0xf81e, 0xc00f }, { 0xf820, 0x7100 }, { 0xf822, 0x209c }, + { 0xf824, 0x249c }, { 0xf826, 0xc009 }, { 0xf828, 0x9900 }, + { 0xf82a, 0xe004 }, { 0xf82c, 0xc006 }, { 0xf82e, 0x1900 }, + { 0xf830, 0x9900 }, { 0xf832, 0xc602 }, { 0xf834, 0xbe00 }, + { 0xf836, 0x5a48 }, { 0xf838, 0xe0c2 }, { 0xf83a, 0x0004 }, + { 0xf83c, 0xe10a }, { 0xf83e, 0xc60f }, { 0xf840, 0x73c4 }, + { 0xf842, 0x49b3 }, { 0xf844, 0xf106 }, { 0xf846, 0x73c2 }, + { 0xf848, 0xc608 }, { 0xf84a, 0xb406 }, { 0xf84c, 0xc609 }, + { 0xf84e, 0xff80 }, { 0xf850, 0xc605 }, { 0xf852, 0xb406 }, + { 0xf854, 0xc605 }, { 0xf856, 0xff80 }, { 0xf858, 0x0544 }, + { 0xf85a, 0x0568 }, { 0xf85c, 0xe906 }, { 0xf85e, 0xcde8 }, + { 0xf860, 0xc724 }, { 0xf862, 0xc624 }, { 0xf864, 0x9ee2 }, + { 0xf866, 0x1e01 }, { 0xf868, 0x9ee0 }, { 0xf86a, 0x76e0 }, + { 0xf86c, 0x49e0 }, { 0xf86e, 0xf1fe }, { 0xf870, 0x76e6 }, + { 0xf872, 0x486d }, { 0xf874, 0x4868 }, { 0xf876, 0x9ee4 }, + { 0xf878, 0x1e03 }, { 0xf87a, 0x9ee0 }, { 0xf87c, 0x76e0 }, + { 0xf87e, 0x49e0 }, { 0xf880, 0xf1fe }, { 0xf882, 0xc615 }, + { 0xf884, 0x9ee2 }, { 0xf886, 0x1e01 }, { 0xf888, 0x9ee0 }, + { 0xf88a, 0x76e0 }, { 0xf88c, 0x49e0 }, { 0xf88e, 0xf1fe }, + { 0xf890, 0x76e6 }, { 0xf892, 0x486f }, { 0xf894, 0x9ee4 }, + { 0xf896, 0x1e03 }, { 0xf898, 0x9ee0 }, { 0xf89a, 0x76e0 }, + { 0xf89c, 0x49e0 }, { 0xf89e, 0xf1fe }, { 0xf8a0, 0x7196 }, + { 0xf8a2, 0xc702 }, { 0xf8a4, 0xbf00 }, { 0xf8a6, 0x5a44 }, + { 0xf8a8, 0xeb0e }, { 0xf8aa, 0x0070 }, { 0xf8ac, 0x00c3 }, + { 0xf8ae, 0x1bc0 }, { 0xf8b0, 0xc602 }, { 0xf8b2, 0xbe00 }, + { 0xf8b4, 0x0e26 }, { 0xf8b6, 0xc602 }, { 0xf8b8, 0xbe00 }, + { 0xf8ba, 0x0eba }, { 0xf8bc, 0x1501 }, { 0xf8be, 0xf02a }, + { 0xf8c0, 0x1500 }, { 0xf8c2, 0xf15d }, { 0xf8c4, 0xc661 }, + { 0xf8c6, 0x75c8 }, { 0xf8c8, 0x49d5 }, { 0xf8ca, 0xf00a }, + { 0xf8cc, 0x49d6 }, { 0xf8ce, 0xf008 }, { 0xf8d0, 0x49d7 }, + { 0xf8d2, 0xf006 }, { 0xf8d4, 0x49d8 }, { 0xf8d6, 0xf004 }, + { 0xf8d8, 0x75d2 }, { 0xf8da, 0x49d9 }, { 0xf8dc, 0xf150 }, + { 0xf8de, 0xc553 }, { 0xf8e0, 0x77a0 }, { 0xf8e2, 0x75c8 }, + { 0xf8e4, 0x4855 }, { 0xf8e6, 0x4856 }, { 0xf8e8, 0x4857 }, + { 0xf8ea, 0x4858 }, { 0xf8ec, 0x48da }, { 0xf8ee, 0x48db }, + { 0xf8f0, 0x49fe }, { 0xf8f2, 0xf002 }, { 0xf8f4, 0x485a }, + { 0xf8f6, 0x49ff }, { 0xf8f8, 0xf002 }, { 0xf8fa, 0x485b }, + { 0xf8fc, 0x9dc8 }, { 0xf8fe, 0x75d2 }, { 0xf900, 0x4859 }, + { 0xf902, 0x9dd2 }, { 0xf904, 0xc643 }, { 0xf906, 0x75c0 }, + { 0xf908, 0x49d4 }, { 0xf90a, 0xf033 }, { 0xf90c, 0x49d0 }, + { 0xf90e, 0xf137 }, { 0xf910, 0xe030 }, { 0xf912, 0xc63a }, + { 0xf914, 0x75c8 }, { 0xf916, 0x49d5 }, { 0xf918, 0xf00e }, + { 0xf91a, 0x49d6 }, { 0xf91c, 0xf00c }, { 0xf91e, 0x49d7 }, + { 0xf920, 0xf00a }, { 0xf922, 0x49d8 }, { 0xf924, 0xf008 }, + { 0xf926, 0x75d2 }, { 0xf928, 0x49d9 }, { 0xf92a, 0xf005 }, + { 0xf92c, 0xc62e }, { 0xf92e, 0x75c0 }, { 0xf930, 0x49d7 }, + { 0xf932, 0xf125 }, { 0xf934, 0xc528 }, { 0xf936, 0x77a0 }, + { 0xf938, 0xc627 }, { 0xf93a, 0x75c8 }, { 0xf93c, 0x4855 }, + { 0xf93e, 0x4856 }, { 0xf940, 0x4857 }, { 0xf942, 0x4858 }, + { 0xf944, 0x48da }, { 0xf946, 0x48db }, { 0xf948, 0x49fe }, + { 0xf94a, 0xf002 }, { 0xf94c, 0x485a }, { 0xf94e, 0x49ff }, + { 0xf950, 0xf002 }, { 0xf952, 0x485b }, { 0xf954, 0x9dc8 }, + { 0xf956, 0x75d2 }, { 0xf958, 0x4859 }, { 0xf95a, 0x9dd2 }, + { 0xf95c, 0xc616 }, { 0xf95e, 0x75c0 }, { 0xf960, 0x4857 }, + { 0xf962, 0x9dc0 }, { 0xf964, 0xc613 }, { 0xf966, 0x75c0 }, + { 0xf968, 0x49da }, { 0xf96a, 0xf003 }, { 0xf96c, 0x49d0 }, + { 0xf96e, 0xf107 }, { 0xf970, 0xc60b }, { 0xf972, 0xc50e }, + { 0xf974, 0x48d9 }, { 0xf976, 0x9dc0 }, { 0xf978, 0x4859 }, + { 0xf97a, 0x9dc0 }, { 0xf97c, 0xc608 }, { 0xf97e, 0xc702 }, + { 0xf980, 0xbf00 }, { 0xf982, 0x3ae0 }, { 0xf984, 0xe860 }, + { 0xf986, 0xb400 }, { 0xf988, 0xb5d4 }, { 0xf98a, 0xe908 }, + { 0xf98c, 0xe86c }, { 0xf98e, 0x1200 }, { 0xf990, 0xc409 }, + { 0xf992, 0x6780 }, { 0xf994, 0x48f1 }, { 0xf996, 0x8f80 }, + { 0xf998, 0xc404 }, { 0xf99a, 0xc602 }, { 0xf99c, 0xbe00 }, + { 0xf99e, 0x10aa }, { 0xf9a0, 0xc010 }, { 0xf9a2, 0xea7c }, + { 0xf9a4, 0xc602 }, { 0xf9a6, 0xbe00 }, { 0xf9a8, 0x0000 }, { 0xfc26, 0x8000 }, { 0xfc2a, 0x0540 }, { 0xfc2e, 0x0e24 }, { 0xfc30, 0x0eb8 }, { 0xfc32, 0x3a5c }, { 0xfc34, 0x10a8 }, { 0xfc48, 0x007a } }, rtl8125b_mac_bps[] = { - { 0xf800, 0xe008 }, { 0xf802, 0xe013 }, { 0xf804, 0xe01e }, - { 0xf806, 0xe02f }, { 0xf808, 0xe035 }, { 0xf80a, 0xe04f }, - { 0xf80c, 0xe053 }, { 0xf80e, 0xe055 }, { 0xf810, 0x740a }, - { 0xf812, 0x4846 }, { 0xf814, 0x4847 }, { 0xf816, 0x9c0a }, - { 0xf818, 0xc607 }, { 0xf81a, 0x74c0 }, { 0xf81c, 0x48c6 }, - { 0xf81e, 0x9cc0 }, { 0xf820, 0xc602 }, { 0xf822, 0xbe00 }, - { 0xf824, 0x13f0 }, { 0xf826, 0xe054 }, { 0xf828, 0x72ca }, - { 0xf82a, 0x4826 }, { 0xf82c, 0x4827 }, { 0xf82e, 0x9aca }, - { 0xf830, 0xc607 }, { 0xf832, 0x72c0 }, { 0xf834, 0x48a6 }, - { 0xf836, 0x9ac0 }, { 0xf838, 0xc602 }, { 0xf83a, 0xbe00 }, - { 0xf83c, 0x081c }, { 0xf83e, 0xe054 }, { 0xf840, 0xc60f }, - { 0xf842, 0x74c4 }, { 0xf844, 0x49cc }, { 0xf846, 0xf109 }, - { 0xf848, 0xc60c }, { 0xf84a, 0x74ca }, { 0xf84c, 0x48c7 }, - { 0xf84e, 0x9cca }, { 0xf850, 0xc609 }, { 0xf852, 0x74c0 }, - { 0xf854, 0x4846 }, { 0xf856, 0x9cc0 }, { 0xf858, 0xc602 }, - { 0xf85a, 0xbe00 }, { 0xf85c, 0x2494 }, { 0xf85e, 0xe092 }, - { 0xf860, 0xe0c0 }, { 0xf862, 0xe054 }, { 0xf864, 0x7420 }, - { 0xf866, 0x48c0 }, { 0xf868, 0x9c20 }, { 0xf86a, 0x7444 }, - { 0xf86c, 0xc602 }, { 0xf86e, 0xbe00 }, { 0xf870, 0x12dc }, - { 0xf872, 0x733a }, { 0xf874, 0x21b5 }, { 0xf876, 0x25bc }, - { 0xf878, 0x1304 }, { 0xf87a, 0xf111 }, { 0xf87c, 0x1b12 }, - { 0xf87e, 0x1d2a }, { 0xf880, 0x3168 }, { 0xf882, 0x3ada }, - { 0xf884, 0x31ab }, { 0xf886, 0x1a00 }, { 0xf888, 0x9ac0 }, - { 0xf88a, 0x1300 }, { 0xf88c, 0xf1fb }, { 0xf88e, 0x7620 }, - { 0xf890, 0x236e }, { 0xf892, 0x276f }, { 0xf894, 0x1a3c }, - { 0xf896, 0x22a1 }, { 0xf898, 0x41b5 }, { 0xf89a, 0x9ee2 }, - { 0xf89c, 0x76e4 }, { 0xf89e, 0x486f }, { 0xf8a0, 0x9ee4 }, - { 0xf8a2, 0xc602 }, { 0xf8a4, 0xbe00 }, { 0xf8a6, 0x4a26 }, - { 0xf8a8, 0x733a }, { 0xf8aa, 0x49bb }, { 0xf8ac, 0xc602 }, - { 0xf8ae, 0xbe00 }, { 0xf8b0, 0x47a2 }, { 0xf8b2, 0xc602 }, - { 0xf8b4, 0xbe00 }, { 0xf8b6, 0x0000 }, { 0xf8b8, 0xc602 }, + { 0xf800, 0xe008 }, { 0xf802, 0xe013 }, { 0xf804, 0xe01e }, + { 0xf806, 0xe02f }, { 0xf808, 0xe035 }, { 0xf80a, 0xe04f }, + { 0xf80c, 0xe053 }, { 0xf80e, 0xe055 }, { 0xf810, 0x740a }, + { 0xf812, 0x4846 }, { 0xf814, 0x4847 }, { 0xf816, 0x9c0a }, + { 0xf818, 0xc607 }, { 0xf81a, 0x74c0 }, { 0xf81c, 0x48c6 }, + { 0xf81e, 0x9cc0 }, { 0xf820, 0xc602 }, { 0xf822, 0xbe00 }, + { 0xf824, 0x13f0 }, { 0xf826, 0xe054 }, { 0xf828, 0x72ca }, + { 0xf82a, 0x4826 }, { 0xf82c, 0x4827 }, { 0xf82e, 0x9aca }, + { 0xf830, 0xc607 }, { 0xf832, 0x72c0 }, { 0xf834, 0x48a6 }, + { 0xf836, 0x9ac0 }, { 0xf838, 0xc602 }, { 0xf83a, 0xbe00 }, + { 0xf83c, 0x081c }, { 0xf83e, 0xe054 }, { 0xf840, 0xc60f }, + { 0xf842, 0x74c4 }, { 0xf844, 0x49cc }, { 0xf846, 0xf109 }, + { 0xf848, 0xc60c }, { 0xf84a, 0x74ca }, { 0xf84c, 0x48c7 }, + { 0xf84e, 0x9cca }, { 0xf850, 0xc609 }, { 0xf852, 0x74c0 }, + { 0xf854, 0x4846 }, { 0xf856, 0x9cc0 }, { 0xf858, 0xc602 }, + { 0xf85a, 0xbe00 }, { 0xf85c, 0x2494 }, { 0xf85e, 0xe092 }, + { 0xf860, 0xe0c0 }, { 0xf862, 0xe054 }, { 0xf864, 0x7420 }, + { 0xf866, 0x48c0 }, { 0xf868, 0x9c20 }, { 0xf86a, 0x7444 }, + { 0xf86c, 0xc602 }, { 0xf86e, 0xbe00 }, { 0xf870, 0x12dc }, + { 0xf872, 0x733a }, { 0xf874, 0x21b5 }, { 0xf876, 0x25bc }, + { 0xf878, 0x1304 }, { 0xf87a, 0xf111 }, { 0xf87c, 0x1b12 }, + { 0xf87e, 0x1d2a }, { 0xf880, 0x3168 }, { 0xf882, 0x3ada }, + { 0xf884, 0x31ab }, { 0xf886, 0x1a00 }, { 0xf888, 0x9ac0 }, + { 0xf88a, 0x1300 }, { 0xf88c, 0xf1fb }, { 0xf88e, 0x7620 }, + { 0xf890, 0x236e }, { 0xf892, 0x276f }, { 0xf894, 0x1a3c }, + { 0xf896, 0x22a1 }, { 0xf898, 0x41b5 }, { 0xf89a, 0x9ee2 }, + { 0xf89c, 0x76e4 }, { 0xf89e, 0x486f }, { 0xf8a0, 0x9ee4 }, + { 0xf8a2, 0xc602 }, { 0xf8a4, 0xbe00 }, { 0xf8a6, 0x4a26 }, + { 0xf8a8, 0x733a }, { 0xf8aa, 0x49bb }, { 0xf8ac, 0xc602 }, + { 0xf8ae, 0xbe00 }, { 0xf8b0, 0x47a2 }, { 0xf8b2, 0xc602 }, + { 0xf8b4, 0xbe00 }, { 0xf8b6, 0x0000 }, { 0xf8b8, 0xc602 }, { 0xf8ba, 0xbe00 }, { 0xf8bc, 0x0000 }, { 0xfc26, 0x8000 }, { 0xfc28, 0x13e6 }, { 0xfc2a, 0x0812 }, { 0xfc2c, 0x248c }, { 0xfc2e, 0x12da }, { 0xfc30, 0x4a20 }, { 0xfc32, 0x47a0 }, diff --git a/sys/dev/pci/if_rtw_pci.c b/sys/dev/pci/if_rtw_pci.c index 7f8c1f516..c0f0788a2 100644 --- a/sys/dev/pci/if_rtw_pci.c +++ b/sys/dev/pci/if_rtw_pci.c @@ -40,8 +40,8 @@ */ #include -#include -#include +#include +#include #include #include #include @@ -49,7 +49,7 @@ #include #include #include - + #include #include #include @@ -205,7 +205,7 @@ rtw_pci_attach(struct device *parent, struct device *self, void *aux) printf(": unable to map interrupt\n"); return; } - intrstr = pci_intr_string(pc, psc->psc_ih); + intrstr = pci_intr_string(pc, psc->psc_ih); psc->psc_intrcookie = pci_intr_establish(pc, psc->psc_ih, IPL_NET, rtw_intr, sc, sc->sc_dev.dv_xname); if (psc->psc_intrcookie == NULL) { diff --git a/sys/dev/pci/if_rtwn.c b/sys/dev/pci/if_rtwn.c index 121b5a3cd..ee548f934 100644 --- a/sys/dev/pci/if_rtwn.c +++ b/sys/dev/pci/if_rtwn.c @@ -513,7 +513,7 @@ rtwn_alloc_rx_list(struct rtwn_pci_softc *sc) } error = bus_dmamem_map(sc->sc_dmat, &rx_ring->seg, rx_ring->nsegs, - size, (caddr_t *)&rx_ring->desc, + size, (caddr_t *)&rx_ring->desc, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); if (error != 0) { bus_dmamem_free(sc->sc_dmat, &rx_ring->seg, rx_ring->nsegs); @@ -1236,7 +1236,7 @@ rtwn_tx_done(struct rtwn_pci_softc *sc, int qid) if (tx_ring->queued < (RTWN_TX_LIST_COUNT - 1)) sc->qfullmsk &= ~(1 << qid); - + if (sc->qfullmsk == 0) { ifq_clr_oactive(&ifp->if_snd); (*ifp->if_start)(ifp); @@ -1614,7 +1614,7 @@ int rtwn_is_oactive(void *cookie) { struct rtwn_pci_softc *sc = cookie; - + return (sc->qfullmsk != 0); } diff --git a/sys/dev/pci/if_sis.c b/sys/dev/pci/if_sis.c index 985eb0f3e..6819ff1c7 100644 --- a/sys/dev/pci/if_sis.c +++ b/sys/dev/pci/if_sis.c @@ -376,9 +376,9 @@ void sis_mii_sync(struct sis_softc *sc) { int i; - + SIO_SET(SIS_MII_DIR|SIS_MII_DATA); - + for (i = 0; i < 32; i++) { SIO_SET(SIS_MII_CLK); DELAY(1); @@ -386,7 +386,7 @@ sis_mii_sync(struct sis_softc *sc) DELAY(1); } } - + /* * Clock a series of bits through the MII. */ @@ -394,9 +394,9 @@ void sis_mii_send(struct sis_softc *sc, u_int32_t bits, int cnt) { int i; - + SIO_CLR(SIS_MII_CLK); - + for (i = (0x1 << (cnt - 1)); i; i >>= 1) { if (bits & i) SIO_SET(SIS_MII_DATA); @@ -408,7 +408,7 @@ sis_mii_send(struct sis_softc *sc, u_int32_t bits, int cnt) SIO_SET(SIS_MII_CLK); } } - + /* * Read an PHY register through the MII. */ @@ -416,9 +416,9 @@ int sis_mii_readreg(struct sis_softc *sc, struct sis_mii_frame *frame) { int i, ack, s; - + s = splnet(); - + /* * Set up frame for RX. */ @@ -426,14 +426,14 @@ sis_mii_readreg(struct sis_softc *sc, struct sis_mii_frame *frame) frame->mii_opcode = SIS_MII_READOP; frame->mii_turnaround = 0; frame->mii_data = 0; - + /* * Turn on data xmit. */ SIO_SET(SIS_MII_DIR); sis_mii_sync(sc); - + /* * Send command/address info. */ @@ -441,23 +441,23 @@ sis_mii_readreg(struct sis_softc *sc, struct sis_mii_frame *frame) sis_mii_send(sc, frame->mii_opcode, 2); sis_mii_send(sc, frame->mii_phyaddr, 5); sis_mii_send(sc, frame->mii_regaddr, 5); - + /* Idle bit */ SIO_CLR((SIS_MII_CLK|SIS_MII_DATA)); DELAY(1); SIO_SET(SIS_MII_CLK); DELAY(1); - + /* Turn off xmit. */ SIO_CLR(SIS_MII_DIR); - + /* Check for ack */ SIO_CLR(SIS_MII_CLK); DELAY(1); ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA; SIO_SET(SIS_MII_CLK); DELAY(1); - + /* * Now try reading data bits. If the ack failed, we still * need to clock through 16 cycles to keep the PHY(s) in sync. @@ -471,7 +471,7 @@ sis_mii_readreg(struct sis_softc *sc, struct sis_mii_frame *frame) } goto fail; } - + for (i = 0x8000; i; i >>= 1) { SIO_CLR(SIS_MII_CLK); DELAY(1); @@ -497,7 +497,7 @@ fail: return (1); return (0); } - + /* * Write to a PHY register through the MII. */ @@ -505,43 +505,43 @@ int sis_mii_writereg(struct sis_softc *sc, struct sis_mii_frame *frame) { int s; - + s = splnet(); /* * Set up frame for TX. */ - + frame->mii_stdelim = SIS_MII_STARTDELIM; frame->mii_opcode = SIS_MII_WRITEOP; frame->mii_turnaround = SIS_MII_TURNAROUND; - + /* * Turn on data output. */ SIO_SET(SIS_MII_DIR); - + sis_mii_sync(sc); - + sis_mii_send(sc, frame->mii_stdelim, 2); sis_mii_send(sc, frame->mii_opcode, 2); sis_mii_send(sc, frame->mii_phyaddr, 5); sis_mii_send(sc, frame->mii_regaddr, 5); sis_mii_send(sc, frame->mii_turnaround, 2); sis_mii_send(sc, frame->mii_data, 16); - + /* Idle bit. */ SIO_SET(SIS_MII_CLK); DELAY(1); SIO_CLR(SIS_MII_CLK); DELAY(1); - + /* * Turn off xmit. */ SIO_CLR(SIS_MII_DIR); - + splx(s); - + return (0); } @@ -1534,7 +1534,7 @@ sis_tick(void *xsc) if (!sc->sis_link) sis_miibus_statchg(&sc->sc_dev); - + timeout_add_sec(&sc->sis_timeout, 1); splx(s); @@ -1654,7 +1654,7 @@ sis_encap(struct sis_softc *sc, struct mbuf *m_head, u_int32_t *txidx) bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap, offsetof(struct sis_list_data, sis_tx_list[0]), - sizeof(struct sis_desc) * SIS_TX_LIST_CNT, + sizeof(struct sis_desc) * SIS_TX_LIST_CNT, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); return (0); diff --git a/sys/dev/pci/if_sk.c b/sys/dev/pci/if_sk.c index 898576a5a..584f7e101 100644 --- a/sys/dev/pci/if_sk.c +++ b/sys/dev/pci/if_sk.c @@ -1497,7 +1497,7 @@ sk_start(struct ifnet *ifp) ifq_set_oactive(&ifp->if_snd); break; } - + m_head = ifq_dequeue(&ifp->if_snd); if (m_head == NULL) break; diff --git a/sys/dev/pci/if_ste.c b/sys/dev/pci/if_ste.c index d1407e5e9..7fb7350bb 100644 --- a/sys/dev/pci/if_ste.c +++ b/sys/dev/pci/if_ste.c @@ -131,7 +131,7 @@ void ste_init_tx_list(struct ste_softc *); #define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) -#define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) +#define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) const struct pci_matchid ste_devices[] = { { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DFE550TX }, @@ -205,7 +205,7 @@ ste_mii_readreg(struct ste_softc *sc, struct ste_mii_frame *frame) frame->mii_opcode = STE_MII_READOP; frame->mii_turnaround = 0; frame->mii_data = 0; - + CSR_WRITE_2(sc, STE_PHYCTL, 0); /* * Turn on data xmit. @@ -294,7 +294,7 @@ ste_mii_writereg(struct ste_softc *sc, struct ste_mii_frame *frame) frame->mii_stdelim = STE_MII_STARTDELIM; frame->mii_opcode = STE_MII_WRITEOP; frame->mii_turnaround = STE_MII_TURNAROUND; - + /* * Turn on data output. */ @@ -385,7 +385,7 @@ ste_miibus_statchg(struct device *self) STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL | STE_DMACTL_TXDMA_UNSTALL); } - + int ste_ifmedia_upd(struct ifnet *ifp) { @@ -483,7 +483,7 @@ ste_read_eeprom(struct ste_softc *sc, caddr_t dest, int off, int cnt, int swap) if (swap) *ptr = ntohs(word); else - *ptr = word; + *ptr = word; } return(err ? 1 : 0); @@ -666,7 +666,7 @@ ste_rxeof(struct ste_softc *sc) continue; } - /* No errors; receive the packet. */ + /* No errors; receive the packet. */ m = cur_rx->ste_mbuf; total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; @@ -1138,8 +1138,8 @@ ste_stop(struct ste_softc *sc) STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); ste_wait(sc); - /* - * Try really hard to stop the RX engine or under heavy RX + /* + * Try really hard to stop the RX engine or under heavy RX * data chip will write into de-allocated memory. */ ste_reset(sc); @@ -1261,7 +1261,7 @@ encap_retry: if (m != NULL) { struct mbuf *mn; - + /* * We ran out of segments. We have to recopy this * mbuf chain first. Bail out if we can't get the @@ -1346,7 +1346,7 @@ ste_start(struct ifnet *ifp) /* Set TX polling interval to start TX engine */ CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); - + STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); ste_wait(sc); }else{ diff --git a/sys/dev/pci/if_stereg.h b/sys/dev/pci/if_stereg.h index a05fcef8f..c40a3e2cd 100644 --- a/sys/dev/pci/if_stereg.h +++ b/sys/dev/pci/if_stereg.h @@ -96,7 +96,7 @@ #define STE_LATE_COLLS 0x75 #define STE_MULTI_COLLS 0x76 -#define STE_SINGLE_COLLS 0x77 +#define STE_SINGLE_COLLS 0x77 #define STE_DMACTL_RXDMA_STOPPED 0x00000001 #define STE_DMACTL_TXDMA_CMPREQ 0x00000002 diff --git a/sys/dev/pci/if_stge.c b/sys/dev/pci/if_stge.c index 06d0379d4..5a93cf5ac 100644 --- a/sys/dev/pci/if_stge.c +++ b/sys/dev/pci/if_stge.c @@ -317,7 +317,7 @@ stge_attach(struct device *parent, struct device *self, void *aux) } else { uint16_t myaddr[ETHER_ADDR_LEN / 2]; for (i = 0; i < ETHER_ADDR_LEN / 2; i++) { - stge_read_eeprom(sc, STGE_EEPROM_StationAddress0 + i, + stge_read_eeprom(sc, STGE_EEPROM_StationAddress0 + i, &myaddr[i]); myaddr[i] = letoh16(myaddr[i]); } diff --git a/sys/dev/pci/if_stgereg.h b/sys/dev/pci/if_stgereg.h index 3b7b8d83d..a191249d2 100644 --- a/sys/dev/pci/if_stgereg.h +++ b/sys/dev/pci/if_stgereg.h @@ -473,7 +473,7 @@ struct stge_rfd { #define STGE_NTXDESC 256 #define STGE_NTXDESC_MASK (STGE_NTXDESC - 1) #define STGE_NEXTTX(x) (((x) + 1) & STGE_NTXDESC_MASK) - + /* * Receive descriptor list size. */ @@ -483,7 +483,7 @@ struct stge_rfd { /* * Only interrupt every N frames. Must be a power-of-two. - */ + */ #define STGE_TXINTR_SPACING 16 #define STGE_TXINTR_SPACING_MASK (STGE_TXINTR_SPACING - 1) @@ -526,16 +526,16 @@ struct stge_descsoft { struct stge_softc { struct device sc_dev; /* generic device information */ bus_space_tag_t sc_st; /* bus space tag */ - bus_space_handle_t sc_sh; /* bus space handle */ - bus_dma_tag_t sc_dmat; /* bus DMA tag */ + bus_space_handle_t sc_sh; /* bus space handle */ + bus_dma_tag_t sc_dmat; /* bus DMA tag */ struct arpcom sc_arpcom; /* ethernet common data */ - int sc_rev; /* silicon revision */ + int sc_rev; /* silicon revision */ void *sc_ih; /* interrupt cookie */ struct mii_data sc_mii; /* MII/media information */ struct timeout sc_timeout; /* tick timeout */ - + bus_dmamap_t sc_cddmamap; /* control data DMA map */ #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr @@ -579,7 +579,7 @@ do { \ *(sc)->sc_rxtailp = NULL; \ (sc)->sc_rxlen = 0; \ } while (/*CONSTCOND*/0) - + #define STGE_RXCHAIN_LINK(sc, m) \ do { \ *(sc)->sc_rxtailp = (sc)->sc_rxtail = (m); \ diff --git a/sys/dev/pci/if_tht.c b/sys/dev/pci/if_tht.c index e07be120e..1007e7605 100644 --- a/sys/dev/pci/if_tht.c +++ b/sys/dev/pci/if_tht.c @@ -966,7 +966,7 @@ tht_up(struct tht_softc *sc) ifp->if_flags |= IFF_RUNNING; ifq_clr_oactive(&ifp->if_snd); - + /* enable interrupts */ sc->sc_imr = THT_IMR_UP(sc->sc_port); tht_write(sc, THT_REG_IMR, sc->sc_imr); diff --git a/sys/dev/pci/if_tl.c b/sys/dev/pci/if_tl.c index bea6f1ba0..da73423d2 100644 --- a/sys/dev/pci/if_tl.c +++ b/sys/dev/pci/if_tl.c @@ -46,7 +46,7 @@ * National Semiconductor DP83840A data sheet (www.national.com) * Microchip Technology 24C02C data sheet (www.microchip.com) * Micro Linear ML6692 100BaseTX only PHY data sheet (www.microlinear.com) - * + * * Written by Bill Paul * Electrical Engineering Department * Columbia University, New York City @@ -82,7 +82,7 @@ * depending on how the card is configured during the PCI probing * phase. It is even possible to have both PIO and memory mapped * access turned on at the same time. - * + * * Frame reception and transmission with the ThunderLAN chip is done * using frame 'lists.' A list structure looks more or less like this: * @@ -549,7 +549,7 @@ tl_mii_readreg(struct tl_softc *sc, struct tl_mii_frame *frame) frame->mii_opcode = TL_MII_READOP; frame->mii_turnaround = 0; frame->mii_data = 0; - + /* * Turn off MII interrupt by forcing MINTEN low. */ @@ -639,7 +639,7 @@ tl_mii_writereg(struct tl_softc *sc, struct tl_mii_frame *frame) frame->mii_stdelim = TL_MII_STARTDELIM; frame->mii_opcode = TL_MII_WRITEOP; frame->mii_turnaround = TL_MII_TURNAROUND; - + /* * Turn off MII interrupt by forcing MINTEN low. */ @@ -1405,7 +1405,7 @@ tl_encap(struct tl_softc *sc, struct tl_chain *c, struct mbuf *m_head) return(1); } } - m_copydata(m_head, 0, m_head->m_pkthdr.len, + m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t)); m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; m_freem(m_head); @@ -1919,7 +1919,7 @@ tl_attach(struct device *parent, struct device *self, void *aux) sc->tl_product->tp_prod == PCI_PRODUCT(pa->pa_id)) break; } - + if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_COMPAQ || PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TI) sc->tl_eeaddr = TL_EEPROM_EADDR; diff --git a/sys/dev/pci/if_tlreg.h b/sys/dev/pci/if_tlreg.h index 6e577203d..eb3dbe198 100644 --- a/sys/dev/pci/if_tlreg.h +++ b/sys/dev/pci/if_tlreg.h @@ -543,7 +543,7 @@ struct tl_stats { * 3) To read a bit from the EEPROM, clear the TXENABLE bit, * then set ECLOK. The bit can then be read by reading EDATA. * ECLOCK should then be cleared again. This can be repeated - * 8 times to read a whole byte, after which the + * 8 times to read a whole byte, after which the * * 4) We need to send the address byte to the EEPROM. For this * we have to send the write control byte to the EEPROM to diff --git a/sys/dev/pci/if_txp.c b/sys/dev/pci/if_txp.c index 6d2199cc2..c22a6454a 100644 --- a/sys/dev/pci/if_txp.c +++ b/sys/dev/pci/if_txp.c @@ -753,7 +753,7 @@ txp_rxbuf_reclaim(struct txp_softc *sc) bus_dmamap_sync(sc->sc_dmat, sc->sc_rxbufring_dma.dma_map, i * sizeof(struct txp_rxbuf_desc), sizeof(struct txp_rxbuf_desc), BUS_DMASYNC_POSTWRITE); - + /* stash away pointer */ bcopy(&sd, (u_long *)&rbd->rb_vaddrlo, sizeof(sd)); @@ -1572,7 +1572,7 @@ txp_rsp_fixup(struct txp_softc *sc, struct txp_rsp_desc *rsp, sc->sc_rspring.lastwrite = ridx; hv->hv_resp_read_idx = htole32(ridx); } - + hv->hv_resp_read_idx = htole32(ridx); } diff --git a/sys/dev/pci/if_vic.c b/sys/dev/pci/if_vic.c index 8a5f9d31d..a0ba691f7 100644 --- a/sys/dev/pci/if_vic.c +++ b/sys/dev/pci/if_vic.c @@ -409,7 +409,7 @@ vic_attach(struct device *parent, struct device *self, void *aux) break; case PCI_ID_CODE(PCI_VENDOR_AMD, PCI_PRODUCT_AMD_PCNET_PCI): - if (bus_space_subregion(sc->sc_iot, ioh, + if (bus_space_subregion(sc->sc_iot, ioh, VIC_LANCE_SIZE + VIC_MORPH_SIZE, VIC_VMXNET_SIZE, &sc->sc_ioh) != 0) { printf(": unable to map register window\n"); diff --git a/sys/dev/pci/if_vmxreg.h b/sys/dev/pci/if_vmxreg.h index 44f5e4315..c5338b720 100644 --- a/sys/dev/pci/if_vmxreg.h +++ b/sys/dev/pci/if_vmxreg.h @@ -131,7 +131,7 @@ struct vmxnet3_txdesc { #define VMXNET3_OM_TSO 3 struct vmxnet3_txcompdesc { - u_int32_t txc_word0; + u_int32_t txc_word0; #define VMXNET3_TXC_EOPIDX_M 0x00000fff /* eop index in Tx ring */ #define VMXNET3_TXC_EOPIDX_S 0 #define VMXNET3_TXC_RES0_M 0x000fffff diff --git a/sys/dev/pci/if_vr.c b/sys/dev/pci/if_vr.c index babef2d86..5e453a874 100644 --- a/sys/dev/pci/if_vr.c +++ b/sys/dev/pci/if_vr.c @@ -898,7 +898,7 @@ vr_rxeof(struct vr_softc *sc) continue; } m = m0; - } + } #else m->m_pkthdr.len = m->m_len = total_len; #endif diff --git a/sys/dev/pci/if_vrreg.h b/sys/dev/pci/if_vrreg.h index d082bf09f..4259f0081 100644 --- a/sys/dev/pci/if_vrreg.h +++ b/sys/dev/pci/if_vrreg.h @@ -315,7 +315,7 @@ #define VR_BCR0_DMA_512BYTES 0x04 #define VR_BCR0_DMA_1024BYTES 0x05 #define VR_BCR0_DMA_STORENFWD 0x07 - + #define VR_BCR0_RX_THRESH 0x38 #define VR_BCR0_RXTHRESHCFG 0x00 @@ -500,7 +500,7 @@ struct vr_mii_frame { #define VR_FLAG_FORCEDELAY 1 #define VR_FLAG_SCHEDDELAY 2 -#define VR_FLAG_DELAYTIMEO 3 +#define VR_FLAG_DELAYTIMEO 3 struct vr_dmamem { bus_dmamap_t vrm_map; diff --git a/sys/dev/pci/if_vte.c b/sys/dev/pci/if_vte.c index 0db92d449..c07aeade6 100644 --- a/sys/dev/pci/if_vte.c +++ b/sys/dev/pci/if_vte.c @@ -355,7 +355,7 @@ vte_attach(struct device *parent, struct device *self, void *aux) sc->sc_miibus.mii_readreg = vte_miibus_readreg; sc->sc_miibus.mii_writereg = vte_miibus_writereg; sc->sc_miibus.mii_statchg = vte_miibus_statchg; - + ifmedia_init(&sc->sc_miibus.mii_media, 0, vte_mediachange, vte_mediastatus); mii_attach(self, &sc->sc_miibus, 0xffffffff, MII_PHY_ANY, @@ -393,7 +393,7 @@ vte_detach(struct device *self, int flags) /* Delete all remaining media. */ ifmedia_delete_instance(&sc->sc_miibus.mii_media, IFM_INST_ANY); - + ether_ifdetach(ifp); if_detach(ifp); vte_dma_free(sc); @@ -421,7 +421,7 @@ vte_dma_alloc(struct vte_softc *sc) /* Allocate DMA'able memory for TX ring */ error = bus_dmamem_alloc(sc->sc_dmat, VTE_TX_RING_SZ, ETHER_ALIGN, - 0, &sc->vte_cdata.vte_tx_ring_seg, 1, &nsegs, + 0, &sc->vte_cdata.vte_tx_ring_seg, 1, &nsegs, BUS_DMA_WAITOK | BUS_DMA_ZERO); if (error) { printf("%s: could not allocate DMA'able memory for Tx ring.\n", @@ -446,7 +446,7 @@ vte_dma_alloc(struct vte_softc *sc) return (error); } - sc->vte_cdata.vte_tx_ring_paddr = + sc->vte_cdata.vte_tx_ring_paddr = sc->vte_cdata.vte_tx_ring_map->dm_segs[0].ds_addr; /* Create DMA stuffs for RX ring */ @@ -622,7 +622,7 @@ vte_encap(struct vte_softc *sc, struct mbuf **m_head) m->m_len = m->m_pkthdr.len; } - error = bus_dmamap_load_mbuf(sc->sc_dmat, txd->tx_dmamap, m, + error = bus_dmamap_load_mbuf(sc->sc_dmat, txd->tx_dmamap, m, BUS_DMA_NOWAIT); if (error != 0) { @@ -630,10 +630,10 @@ vte_encap(struct vte_softc *sc, struct mbuf **m_head) return (NULL); } - bus_dmamap_sync(sc->sc_dmat, txd->tx_dmamap, 0, + bus_dmamap_sync(sc->sc_dmat, txd->tx_dmamap, 0, txd->tx_dmamap->dm_mapsize, BUS_DMASYNC_PREWRITE); - txd->tx_desc->dtlen = + txd->tx_desc->dtlen = htole16(VTE_TX_LEN(txd->tx_dmamap->dm_segs[0].ds_len)); txd->tx_desc->dtbp = htole32(txd->tx_dmamap->dm_segs[0].ds_addr); sc->vte_cdata.vte_tx_cnt++; @@ -955,7 +955,7 @@ vte_newbuf(struct vte_softc *sc, struct vte_rxdesc *rxd, int init) bus_dmamap_unload(sc->sc_dmat, sc->vte_cdata.vte_rx_sparemap); error = EFBIG; - printf("%s: too many segments?!\n", + printf("%s: too many segments?!\n", sc->sc_dev.dv_xname); } m_freem(m); @@ -976,7 +976,7 @@ vte_newbuf(struct vte_softc *sc, struct vte_rxdesc *rxd, int init) rxd->rx_m = m; rxd->rx_desc->drbp = htole32(rxd->rx_dmamap->dm_segs[0].ds_addr); - rxd->rx_desc->drlen = + rxd->rx_desc->drlen = htole16(VTE_RX_LEN(rxd->rx_dmamap->dm_segs[0].ds_len)); rxd->rx_desc->drst = htole16(VTE_DRST_RX_OWN); @@ -1354,7 +1354,7 @@ vte_init_tx_ring(struct vte_softc *sc) /* Pre-allocate TX mbufs for deep copy. */ for (i = 0; i < VTE_TX_RING_CNT; i++) { - MGETHDR(sc->vte_cdata.vte_txmbufs[i], + MGETHDR(sc->vte_cdata.vte_txmbufs[i], M_DONTWAIT, MT_DATA); if (sc->vte_cdata.vte_txmbufs[i] == NULL) return (ENOBUFS); @@ -1463,11 +1463,11 @@ vte_iff(struct vte_softc *sc) */ if (nperf < VTE_RXFILT_PERFECT_CNT) { eaddr = enm->enm_addrlo; - rxfilt_perf[nperf][0] = + rxfilt_perf[nperf][0] = eaddr[1] << 8 | eaddr[0]; - rxfilt_perf[nperf][1] = + rxfilt_perf[nperf][1] = eaddr[3] << 8 | eaddr[2]; - rxfilt_perf[nperf][2] = + rxfilt_perf[nperf][2] = eaddr[5] << 8 | eaddr[4]; nperf++; continue; diff --git a/sys/dev/pci/if_wb.c b/sys/dev/pci/if_wb.c index f97a229f3..7a2cc82fb 100644 --- a/sys/dev/pci/if_wb.c +++ b/sys/dev/pci/if_wb.c @@ -54,7 +54,7 @@ * tulip registers are typically spaced 8 bytes apart, the Winbond * registers are spaced 4 bytes apart. The receiver filter is also * programmed differently. - * + * * Like the tulip, the Winbond chip uses small descriptors containing * a status word, a control word and 32-bit areas that can either be used * to point to two external data blocks, or to point to a single block @@ -329,7 +329,7 @@ wb_mii_readreg(struct wb_softc *sc, struct wb_mii_frame *frame) frame->mii_opcode = WB_MII_READOP; frame->mii_turnaround = 0; frame->mii_data = 0; - + CSR_WRITE_4(sc, WB_SIO, 0); /* @@ -422,7 +422,7 @@ wb_mii_writereg(struct wb_softc *sc, struct wb_mii_frame *frame) frame->mii_stdelim = WB_MII_STARTDELIM; frame->mii_opcode = WB_MII_WRITEOP; frame->mii_turnaround = WB_MII_TURNAROUND; - + /* * Turn on data output. */ @@ -857,7 +857,7 @@ wb_list_rx_init(struct wb_softc *sc) wb_newbuf(sc, &cd->wb_rx_chain[i]); if (i == (WB_RX_LIST_CNT - 1)) { cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; - ld->wb_rx_list[i].wb_next = + ld->wb_rx_list[i].wb_next = VTOPHYS(&ld->wb_rx_list[0]); } else { cd->wb_rx_chain[i].wb_nextdesc = @@ -925,7 +925,7 @@ wb_rxeof(struct wb_softc *sc) break; } - /* No errors; receive the packet. */ + /* No errors; receive the packet. */ total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); /* @@ -1200,7 +1200,7 @@ wb_encap(struct wb_softc *sc, struct wb_chain *c, struct mbuf *m_head) return(1); } } - m_copydata(m_head, 0, m_head->m_pkthdr.len, + m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t)); m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; m_freem(m_head); diff --git a/sys/dev/pci/if_wbreg.h b/sys/dev/pci/if_wbreg.h index 8ae824e2b..52d12f400 100644 --- a/sys/dev/pci/if_wbreg.h +++ b/sys/dev/pci/if_wbreg.h @@ -165,7 +165,7 @@ #define WB_TXTHRESH(x) ((x >> 5) << 14) #define WB_TXTHRESH_CHUNK 32 #define WB_TXTHRESH_INIT 0 /*72*/ - + /* * Interrupt mask bits. */ diff --git a/sys/dev/pci/if_wi_pci.c b/sys/dev/pci/if_wi_pci.c index 85f9f91a8..3c12c9cf6 100644 --- a/sys/dev/pci/if_wi_pci.c +++ b/sys/dev/pci/if_wi_pci.c @@ -123,7 +123,7 @@ wi_pci_lookup(struct pci_attach_args *pa) const struct wi_pci_product *pp; for (pp = wi_pci_products; pp->pp_product != 0; pp++) { - if (PCI_VENDOR(pa->pa_id) == pp->pp_vendor && + if (PCI_VENDOR(pa->pa_id) == pp->pp_vendor && PCI_PRODUCT(pa->pa_id) == pp->pp_product) return (pp); } @@ -280,7 +280,7 @@ wi_pci_acex_attach(struct pci_attach_args *pa, struct wi_softc *sc) return (ENXIO); } - /* + /* * Enable I/O mode and level interrupts on the embedded PCMCIA * card. */ @@ -474,7 +474,7 @@ wi_pci_tmd_attach(struct pci_attach_args *pa, struct wi_softc *sc) return (ENXIO); } - /* + /* * Enable I/O mode and level interrupts on the embedded PCMCIA * card. The PCMCIA card's COR is the first byte of BAR 0. */ diff --git a/sys/dev/pci/if_wpi.c b/sys/dev/pci/if_wpi.c index 30dcc8a1a..01d6ec618 100644 --- a/sys/dev/pci/if_wpi.c +++ b/sys/dev/pci/if_wpi.c @@ -504,7 +504,7 @@ wpi_mem_read(struct wpi_softc *sc, uint32_t addr) return WPI_READ(sc, WPI_MEM_RDATA); } -static __inline void +static __inline void wpi_mem_write(struct wpi_softc *sc, uint32_t addr, uint32_t data) { WPI_WRITE(sc, WPI_MEM_WADDR, addr); diff --git a/sys/dev/pci/if_wpireg.h b/sys/dev/pci/if_wpireg.h index 26fa72b88..9846e8d38 100644 --- a/sys/dev/pci/if_wpireg.h +++ b/sys/dev/pci/if_wpireg.h @@ -827,7 +827,7 @@ static const char * const wpi_fw_errmsg[] = { #define WPI_SETBITS(sc, reg, mask) \ WPI_WRITE(sc, reg, WPI_READ(sc, reg) | (mask)) - + #define WPI_CLRBITS(sc, reg, mask) \ WPI_WRITE(sc, reg, WPI_READ(sc, reg) & ~(mask)) diff --git a/sys/dev/pci/if_xge.c b/sys/dev/pci/if_xge.c index ed8cb9955..d4176cb06 100644 --- a/sys/dev/pci/if_xge.c +++ b/sys/dev/pci/if_xge.c @@ -423,7 +423,7 @@ xge_attach(struct device *parent, struct device *self, void *aux) if ((val = PIF_RCSR(XMSI_ADDRESS)) != SWAPPER_MAGIC) { printf(": failed configuring endian (write), %llx != %llx!\n", (unsigned long long)val, SWAPPER_MAGIC); - } + } /* * Fix for all "FFs" MAC address problems observed on diff --git a/sys/dev/pci/if_xgereg.h b/sys/dev/pci/if_xgereg.h index 730962a3e..01001447b 100644 --- a/sys/dev/pci/if_xgereg.h +++ b/sys/dev/pci/if_xgereg.h @@ -166,9 +166,9 @@ #define TX_FIFO_P3 TDMAB(0x0120) #define TX_FIFO_ENABLE (1ULL<<63) #define TX_FIFO_NUM0(x) ((uint64_t)(x) << 56) -#define TX_FIFO_LEN0(x) ((uint64_t)((x)-1) << 32) +#define TX_FIFO_LEN0(x) ((uint64_t)((x)-1) << 32) #define TX_FIFO_NUM1(x) ((uint64_t)(x) << 24) -#define TX_FIFO_LEN1(x) ((uint64_t)((x)-1) << 0) +#define TX_FIFO_LEN1(x) ((uint64_t)((x)-1) << 0) /* Transmit interrupts */ #define TTI_COMMAND_MEM TDMAB(0x150) @@ -298,7 +298,7 @@ struct txd { struct rxd1 { uint64_t rxd_hcontrol; uint64_t rxd_control1; - uint64_t rxd_control2; + uint64_t rxd_control2; uint64_t rxd_buf0; }; @@ -315,8 +315,8 @@ struct rxd3 { uint64_t rxd_control1; uint64_t rxd_control2; uint64_t rxd_buf0; - uint64_t rxd_buf1; - uint64_t rxd_buf2; + uint64_t rxd_buf1; + uint64_t rxd_buf2; }; struct rxd5 { diff --git a/sys/dev/pci/if_xl_pci.c b/sys/dev/pci/if_xl_pci.c index 963e1984c..a5f765dd3 100644 --- a/sys/dev/pci/if_xl_pci.c +++ b/sys/dev/pci/if_xl_pci.c @@ -307,7 +307,7 @@ xl_pci_detach(struct device *self, int flags) return (0); } -void +void xl_pci_intr_ack(struct xl_softc *sc) { bus_space_write_4(sc->xl_funct, sc->xl_funch, XL_PCI_INTR, diff --git a/sys/dev/pci/igc_mac.c b/sys/dev/pci/igc_mac.c index 32fd4ce8a..4e5e9101c 100644 --- a/sys/dev/pci/igc_mac.c +++ b/sys/dev/pci/igc_mac.c @@ -63,7 +63,7 @@ igc_write_vfta_generic(struct igc_hw *hw, uint32_t offset, uint32_t value) * register to the devices MAC address and clearing all the other receive * address registers to 0. **/ -void +void igc_init_rx_addrs_generic(struct igc_hw *hw, uint16_t rar_count) { uint32_t i; diff --git a/sys/dev/pci/igc_phy.c b/sys/dev/pci/igc_phy.c index fe050f240..815d382d5 100644 --- a/sys/dev/pci/igc_phy.c +++ b/sys/dev/pci/igc_phy.c @@ -59,7 +59,7 @@ igc_null_set_page(struct igc_hw IGC_UNUSEDARG *hw, uint16_t IGC_UNUSEDARG data) * @data: dummy variable **/ int -igc_null_read_reg(struct igc_hw IGC_UNUSEDARG *hw, +igc_null_read_reg(struct igc_hw IGC_UNUSEDARG *hw, uint32_t IGC_UNUSEDARG offset, uint16_t IGC_UNUSEDARG *data) { DEBUGFUNC("igc_null_read_reg"); diff --git a/sys/dev/pci/igc_regs.h b/sys/dev/pci/igc_regs.h index 715b4b3ec..72a5bfc7f 100644 --- a/sys/dev/pci/igc_regs.h +++ b/sys/dev/pci/igc_regs.h @@ -47,7 +47,7 @@ #define IGC_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */ #define IGC_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear * Mask */ -#define IGC_GPIE 0x01514 /* General Purpose Interrupt Enable +#define IGC_GPIE 0x01514 /* General Purpose Interrupt Enable * - RW */ #define IGC_IVAR0 0x01700 /* Interrupt Vector Allocation (array) * - RW */ diff --git a/sys/dev/pci/ixgb_ee.c b/sys/dev/pci/ixgb_ee.c index cde1ec402..0b7f17bbe 100644 --- a/sys/dev/pci/ixgb_ee.c +++ b/sys/dev/pci/ixgb_ee.c @@ -2,21 +2,21 @@ Copyright (c) 2001-2005, Intel Corporation All rights reserved. - + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - + 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - + 3. Neither the name of the Intel Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. - + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -53,8 +53,8 @@ #include #include -#include -#include +#include +#include /* Local prototypes */ static uint16_t ixgb_shift_in_bits(struct ixgb_hw *hw); diff --git a/sys/dev/pci/ixgb_ee.h b/sys/dev/pci/ixgb_ee.h index c99529b3f..df15f2d21 100644 --- a/sys/dev/pci/ixgb_ee.h +++ b/sys/dev/pci/ixgb_ee.h @@ -2,21 +2,21 @@ Copyright (c) 2001-2005, Intel Corporation All rights reserved. - + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - + 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - + 3. Neither the name of the Intel Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. - + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE diff --git a/sys/dev/pci/ixgb_hw.c b/sys/dev/pci/ixgb_hw.c index c65f3574d..82d806a35 100644 --- a/sys/dev/pci/ixgb_hw.c +++ b/sys/dev/pci/ixgb_hw.c @@ -2,21 +2,21 @@ Copyright (c) 2001-2005, Intel Corporation All rights reserved. - + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - + 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - + 3. Neither the name of the Intel Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. - + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -57,8 +57,8 @@ #include #include -#include -#include +#include +#include /* Local function prototypes */ @@ -280,7 +280,7 @@ ixgb_identify_phy(struct ixgb_hw *hw) /* update phy type for sun specific board */ if (hw->subsystem_vendor_id == SUN_SUBVENDOR_ID) - phy_type = ixgb_phy_type_bcm; + phy_type = ixgb_phy_type_bcm; return (phy_type); } @@ -1280,4 +1280,4 @@ ixgb_optics_reset_bcm(struct ixgb_hw *hw) msec_delay(IXGB_SUN_PHY_RESET_DELAY); return; -} +} diff --git a/sys/dev/pci/ixgb_hw.h b/sys/dev/pci/ixgb_hw.h index e1da95943..91e925ef1 100644 --- a/sys/dev/pci/ixgb_hw.h +++ b/sys/dev/pci/ixgb_hw.h @@ -2,21 +2,21 @@ Copyright (c) 2001-2005, Intel Corporation All rights reserved. - + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - + 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - + 3. Neither the name of the Intel Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. - + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -31,7 +31,7 @@ *******************************************************************************/ -/* $OpenBSD: ixgb_hw.h,v 1.3 2010/09/20 07:50:19 deraadt Exp $ */ +/* $OpenBSD: ixgb_hw.h,v 1.3 2010/09/20 07:50:19 deraadt Exp $ */ #ifndef _IXGB_HW_H_ #define _IXGB_HW_H_ @@ -176,7 +176,7 @@ typedef enum { #define IXGB_PCSC2 0x00708 /* PCS Control 2 - RW */ #define IXGB_PCSS1 0x00710 /* PCS Status 1 - RO */ #define IXGB_PCSS2 0x00718 /* PCS Status 2 - RO */ -#define IXGB_XPCSS 0x00720 /* 10GBASE-X PCS Status (or XGXS Lane Status) - +#define IXGB_XPCSS 0x00720 /* 10GBASE-X PCS Status (or XGXS Lane Status) - * RO */ #define IXGB_UCCR 0x00728 /* Unilink Circuit Control Register */ #define IXGB_XPCSTC 0x00730 /* 10GBASE-X PCS Test Control */ @@ -588,7 +588,7 @@ struct ixgb_rx_desc { #define IXGB_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ #define IXGB_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ -#define IXGB_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority is in upper 3 of 16 +#define IXGB_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority is in upper 3 of 16 */ /* Layout of a single transmit descriptor. */ @@ -723,7 +723,7 @@ struct ixgb_hw { uint32_t mc_filter_type; /* Multicast filter hash type */ uint32_t num_mc_addrs; /* Number of current Multicast addrs */ /* Individual address currently programmed in MAC */ - uint8_t curr_mac_addr[IXGB_ETH_LENGTH_OF_ADDRESS]; + uint8_t curr_mac_addr[IXGB_ETH_LENGTH_OF_ADDRESS]; uint32_t num_tx_desc; /* Number of Transmit descriptors */ uint32_t num_rx_desc; /* Number of Receive descriptors */ uint32_t rx_buffer_size; /* Size of Receive buffer */ @@ -741,7 +741,7 @@ struct ixgb_hw { uint32_t bar3; uint16_t pci_cmd_word; /* PCI command register id from PCI * configuration space */ - uint16_t eeprom[IXGB_EEPROM_SIZE]; /* EEPROM contents read at init + uint16_t eeprom[IXGB_EEPROM_SIZE]; /* EEPROM contents read at init * time */ unsigned long io_base; /* Our I/O mapped location */ uint32_t lastLFC; diff --git a/sys/dev/pci/ixgb_ids.h b/sys/dev/pci/ixgb_ids.h index 52febc46c..13b21f5a6 100644 --- a/sys/dev/pci/ixgb_ids.h +++ b/sys/dev/pci/ixgb_ids.h @@ -2,21 +2,21 @@ Copyright (c) 2001-2005, Intel Corporation All rights reserved. - + Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - + 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - + 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - + 3. Neither the name of the Intel Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. - + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -53,7 +53,7 @@ #define IXGB_DEVICE_ID_82597EX_CX4 0x109E #define IXGB_SUBDEVICE_ID_A00C 0xA00C -#define IXGB_SUBDEVICE_ID_A01C 0xA01C +#define IXGB_SUBDEVICE_ID_A01C 0xA01C #define IXGB_SUBDEVICE_ID_7036 0x7036 #endif /* #ifndef _IXGB_IDS_H_ */ diff --git a/sys/dev/pci/ixgbe.c b/sys/dev/pci/ixgbe.c index 0fd3b9b8f..965d70730 100644 --- a/sys/dev/pci/ixgbe.c +++ b/sys/dev/pci/ixgbe.c @@ -687,7 +687,7 @@ int32_t ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, uint8_t *mac_addr) #ifdef __sparc64__ struct ixgbe_osdep *os = hw->back; - + if (OF_getprop(PCITAG_NODE(os->os_pa.pa_tag), "local-mac-address", mac_addr, ETHER_ADDR_LEN) == ETHER_ADDR_LEN) return IXGBE_SUCCESS; diff --git a/sys/dev/pci/ixgbe_type.h b/sys/dev/pci/ixgbe_type.h index edc569b94..42551d056 100644 --- a/sys/dev/pci/ixgbe_type.h +++ b/sys/dev/pci/ixgbe_type.h @@ -3999,7 +3999,7 @@ struct ixgbe_phy_operations { int32_t (*write_i2c_eeprom)(struct ixgbe_hw *, uint8_t, uint8_t); void (*i2c_bus_clear)(struct ixgbe_hw *); /*depreatced*/ - int32_t (*read_i2c_combined)(struct ixgbe_hw *, uint8_t addr, uint16_t reg, uint16_t *val); + int32_t (*read_i2c_combined)(struct ixgbe_hw *, uint8_t addr, uint16_t reg, uint16_t *val); int32_t (*write_i2c_combined)(struct ixgbe_hw *, uint8_t addr, uint16_t reg, uint16_t val); int32_t (*read_i2c_combined_unlocked)(struct ixgbe_hw *, uint8_t addr, uint16_t reg, uint16_t *value); diff --git a/sys/dev/pci/kate.c b/sys/dev/pci/kate.c index 2bf8b92a8..254a3b039 100644 --- a/sys/dev/pci/kate.c +++ b/sys/dev/pci/kate.c @@ -47,7 +47,7 @@ /* - * Revision Guide for AMD NPT Family 0Fh Processors, + * Revision Guide for AMD NPT Family 0Fh Processors, * Publication # 33610, Revision 3.30, February 2008 */ static const struct { @@ -105,7 +105,7 @@ kate_match(struct device *parent, void *match, void *aux) return 0; /* - * First, let's probe for chips at or after Revision F, which is + * First, let's probe for chips at or after Revision F, which is * when the temperature readings were officially introduced. */ c = pci_conf_read(pa->pa_pc, pa->pa_tag, K_CPUID_FAMILY_MODEL_R); diff --git a/sys/dev/pci/maestro.c b/sys/dev/pci/maestro.c index bbd0a3b1e..27104101b 100644 --- a/sys/dev/pci/maestro.c +++ b/sys/dev/pci/maestro.c @@ -1,7 +1,7 @@ /* $OpenBSD: maestro.c,v 1.50 2022/10/28 15:09:46 kn Exp $ */ /* $FreeBSD: /c/ncvs/src/sys/dev/sound/pci/maestro.c,v 1.3 2000/11/21 12:22:11 julian Exp $ */ /* - * FreeBSD's ESS Agogo/Maestro driver + * FreeBSD's ESS Agogo/Maestro driver * Converted from FreeBSD's pcm to OpenBSD's audio. * Copyright (c) 2000, 2001 David Leonard & Marc Espie * All rights reserved. @@ -456,7 +456,7 @@ salloc_t salloc_new(caddr_t, size_t, int); void salloc_destroy(salloc_t); caddr_t salloc_alloc(salloc_t, size_t); void salloc_free(salloc_t, caddr_t); -void salloc_insert(salloc_t, struct salloc_head *, +void salloc_insert(salloc_t, struct salloc_head *, struct salloc_zone *, int); int maestro_match(struct device *, void *, void *); @@ -466,7 +466,7 @@ int maestro_intr(void *); int maestro_open(void *, int); void maestro_close(void *); -int maestro_set_params(void *, int, int, struct audio_params *, +int maestro_set_params(void *, int, int, struct audio_params *, struct audio_params *); int maestro_round_blocksize(void *, int); int maestro_halt_output(void *); @@ -624,7 +624,7 @@ maestro_attach(struct device *parent, struct device *self, void *aux) pci_set_powerstate(pc, sc->pt, PCI_PMCSR_STATE_D0); /* Map i/o */ - if ((error = pci_mapreg_map(pa, PCI_MAPS, PCI_MAPREG_TYPE_IO, + if ((error = pci_mapreg_map(pa, PCI_MAPS, PCI_MAPREG_TYPE_IO, 0, &sc->iot, &sc->ioh, NULL, NULL, 0)) != 0) { printf(", can't map i/o space\n"); goto bad; @@ -632,32 +632,32 @@ maestro_attach(struct device *parent, struct device *self, void *aux) /* Allocate fixed DMA segment :-( */ sc->dmasize = MAESTRO_BUFSIZ * 16; - if ((error = bus_dmamem_alloc(sc->dmat, sc->dmasize, NBPG, 0, + if ((error = bus_dmamem_alloc(sc->dmat, sc->dmasize, NBPG, 0, &sc->dmaseg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { printf(", unable to alloc dma, error %d\n", error); goto bad; } dmastage = 1; if ((error = bus_dmamem_map(sc->dmat, &sc->dmaseg, 1, - sc->dmasize, &sc->dmabase, BUS_DMA_NOWAIT | + sc->dmasize, &sc->dmabase, BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { printf(", unable to map dma, error %d\n", error); goto bad; } dmastage = 2; - if ((error = bus_dmamap_create(sc->dmat, sc->dmasize, 1, + if ((error = bus_dmamap_create(sc->dmat, sc->dmasize, 1, sc->dmasize, 0, BUS_DMA_NOWAIT, &sc->dmamap)) != 0) { printf(", unable to create dma map, error %d\n", error); goto bad; } dmastage = 3; - if ((error = bus_dmamap_load(sc->dmat, sc->dmamap, + if ((error = bus_dmamap_load(sc->dmat, sc->dmamap, sc->dmabase, sc->dmasize, NULL, BUS_DMA_NOWAIT)) != 0) { printf(", unable to load dma map, error %d\n", error); goto bad; } - /* XXX + /* XXX * The first byte of the allocated memory is not usable, * the WP sometimes uses it to store status. */ @@ -667,7 +667,7 @@ maestro_attach(struct device *parent, struct device *self, void *aux) printf(", unable to make dma pool\n"); goto bad; } - + sc->physaddr = sc->dmamap->dm_segs[0].ds_addr; printf("\n"); @@ -676,7 +676,7 @@ maestro_attach(struct device *parent, struct device *self, void *aux) maestro_init(sc); maestro_read_codec(sc, 0, &cdata); if (cdata == 0x80) { - printf("%s: PT101 codec unsupported, no mixer\n", + printf("%s: PT101 codec unsupported, no mixer\n", sc->dev.dv_xname); /* Init values from Linux, no idea what this does. */ maestro_write_codec(sc, 0x2a, 0x0001); @@ -773,7 +773,7 @@ maestro_init(struct maestro_softc *sc) WAVCACHE_ENABLED | WAVCACHE_WTSIZE_4MB); for (reg = WAVCACHE_PCMBAR; reg < WAVCACHE_PCMBAR + 4; reg++) - wc_reg_write(sc, reg, + wc_reg_write(sc, reg, sc->physaddr >> WAVCACHE_BASEADDR_SHIFT); /* Setup Codec/Ringbus. */ @@ -792,7 +792,7 @@ maestro_init(struct maestro_softc *sc) bus_space_write_1(sc->iot, sc->ioh, PORT_ASSP_CTRL_A, 0x03); bus_space_write_1(sc->iot, sc->ioh, PORT_ASSP_CTRL_C, 0x00); - /* + /* * Reset hw volume to a known value so that we may handle diffs * off to AC'97. */ @@ -802,11 +802,11 @@ maestro_init(struct maestro_softc *sc) if (sc->flags & MAESTRO_FLAG_SETUPGPIO) { /* Matthew Braithwaite reported that * NEC Versa LX doesn't need GPIO operation. */ - bus_space_write_2(sc->iot, sc->ioh, + bus_space_write_2(sc->iot, sc->ioh, PORT_GPIO_MASK, 0x9ff); bus_space_write_2(sc->iot, sc->ioh, PORT_GPIO_DIR, bus_space_read_2(sc->iot, sc->ioh, PORT_GPIO_DIR) | 0x600); - bus_space_write_2(sc->iot, sc->ioh, + bus_space_write_2(sc->iot, sc->ioh, PORT_GPIO_DATA, 0x200); } } @@ -893,7 +893,7 @@ maestro_set_speed(struct maestro_channel *ch, u_long *prate) ch->speed = *prate; if ((ch->mode & (MAESTRO_8BIT | MAESTRO_STEREO)) == MAESTRO_8BIT) ch->speed /= 2; - + /* special common case */ if (ch->speed == 48000) { ch->dv = 0x10000; @@ -903,7 +903,7 @@ maestro_set_speed(struct maestro_channel *ch, u_long *prate) ch->dv = (((ch->speed % 48000) << 16U) + 24000) / 48000 + ((ch->speed / 48000) << 16U); /* And this is the real rate obtained */ - ch->speed = (ch->dv >> 16U) * 48000 + + ch->speed = (ch->dv >> 16U) * 48000 + (((ch->dv & 0xffff)*48000)>>16U); } *prate = ch->speed; @@ -947,7 +947,7 @@ maestro_set_params(void *hdl, int setmode, int usemode, struct audio_params *play, struct audio_params *rec) { struct maestro_softc *sc = (struct maestro_softc *)hdl; - + if ((setmode & AUMODE_PLAY) == 0) return (0); @@ -1030,7 +1030,7 @@ maestro_channel_stop(struct maestro_channel *ch) if (ch->mode & MAESTRO_STEREO) wp_apu_write(ch->sc, ch->num+3, APUREG_APUTYPE, APUTYPE_INACTIVE << APU_APUTYPE_SHIFT); - + } int @@ -1132,10 +1132,10 @@ maestro_channel_start(struct maestro_channel *ch) | ((ch->dv & 0xff) << APU_FREQ_LOBYTE_SHIFT)); wp_apu_write(sc, n+1, APUREG_FREQ_HIWORD, ch->dv >> 8); if (ch->mode & MAESTRO_8BIT) - wp_apu_write(sc, n, APUREG_WAVESPACE, + wp_apu_write(sc, n, APUREG_WAVESPACE, ch->wpwa & 0xff00); else - wp_apu_write(sc, n, APUREG_WAVESPACE, + wp_apu_write(sc, n, APUREG_WAVESPACE, (ch->wpwa|(APU_STEREO >> 1)) & 0xff00); wp_apu_write(sc, n, APUREG_CURPTR, ch->current); wp_apu_write(sc, n, APUREG_ENDPTR, ch->end); @@ -1336,7 +1336,7 @@ maestro_initcodec(void *self) } /* Check the codec to see is still busy */ - if ((bus_space_read_1(sc->iot, sc->ioh, PORT_CODEC_STAT) & + if ((bus_space_read_1(sc->iot, sc->ioh, PORT_CODEC_STAT) & CODEC_STAT_MASK) != 0) { printf("%s: codec failure\n", sc->dev.dv_xname); } @@ -1398,7 +1398,7 @@ maestro_channel_advance_dma(struct maestro_channel *ch) for (;;) { pos = wp_apu_read(ch->sc, ch->num, APUREG_CURPTR); /* Are we still processing the current dma block ? */ - if (pos >= ch->threshold && + if (pos >= ch->threshold && pos < ch->threshold + ch->blocksize/2) break; ch->threshold += ch->blocksize/2; @@ -1412,7 +1412,7 @@ maestro_channel_advance_dma(struct maestro_channel *ch) #ifdef AUDIO_DEBUG if (maestrodebug && maestrointr_called % 64 == 0) - printf("maestro: dma advanced %lu for %lu calls\n", + printf("maestro: dma advanced %lu for %lu calls\n", maestrodma_effective, maestrointr_called); #endif } @@ -1460,7 +1460,7 @@ maestro_intr(void *arg) /* Special case: Mute key */ if (n & 0x11) { hwvol.type = AUDIO_MIXER_ENUM; - hwvol.dev = + hwvol.dev = sc->codec_if->vtbl->get_portnum_by_name(sc->codec_if, AudioCoutputs, AudioNmaster, AudioNmute); sc->codec_if->vtbl->mixer_get_port(sc->codec_if, &hwvol); @@ -1468,9 +1468,9 @@ maestro_intr(void *arg) } else { hwvol.type = AUDIO_MIXER_VALUE; hwvol.un.value.num_channels = 2; - hwvol.dev = + hwvol.dev = sc->codec_if->vtbl->get_portnum_by_name( - sc->codec_if, AudioCoutputs, AudioNmaster, + sc->codec_if, AudioCoutputs, AudioNmaster, NULL); sc->codec_if->vtbl->mixer_get_port(sc->codec_if, &hwvol); /* XXX AC'97 yields five bits for master volume. */ @@ -1486,7 +1486,7 @@ maestro_intr(void *arg) } sc->codec_if->vtbl->mixer_set_port(sc->codec_if, &hwvol); /* Reset to compute next diffs */ - bus_space_write_1(sc->iot, sc->ioh, PORT_HWVOL_MASTER, + bus_space_write_1(sc->iot, sc->ioh, PORT_HWVOL_MASTER, MIDDLE_VOLUME); } @@ -1686,13 +1686,13 @@ salloc_insert(salloc_t pool, struct salloc_head *head, struct salloc_zone *zone, { struct salloc_zone *prev, *next; - /* + /* * Insert a zone into an ordered list of zones, possibly * merging adjacent zones. */ prev = NULL; SLIST_FOREACH(next, head, link) { - if (next->addr > zone->addr) + if (next->addr > zone->addr) break; prev = next; } @@ -1717,7 +1717,7 @@ salloc_alloc(salloc_t pool, size_t size) { struct salloc_zone *zone, *uzone; - SLIST_FOREACH(zone, &pool->free, link) + SLIST_FOREACH(zone, &pool->free, link) if (zone->size >= size) break; if (zone == NULL) @@ -1744,7 +1744,7 @@ salloc_free(salloc_t pool, caddr_t addr) { struct salloc_zone *zone; - SLIST_FOREACH(zone, &pool->used, link) + SLIST_FOREACH(zone, &pool->used, link) if (zone->addr == addr) break; #ifdef DIAGNOSTIC diff --git a/sys/dev/pci/mbg.c b/sys/dev/pci/mbg.c index 417eff4ff..2bc465f40 100644 --- a/sys/dev/pci/mbg.c +++ b/sys/dev/pci/mbg.c @@ -48,7 +48,7 @@ struct mbg_softc { struct ksensordev sc_sensordev; struct timeout sc_timeout; /* invalidate sensor */ int sc_trust; /* trust time in seconds */ - + int (*sc_read)(struct mbg_softc *, int cmd, char *buf, size_t len, struct timespec *tstamp); diff --git a/sys/dev/pci/nviic.c b/sys/dev/pci/nviic.c index 8de553ab5..4d3c76dde 100644 --- a/sys/dev/pci/nviic.c +++ b/sys/dev/pci/nviic.c @@ -39,7 +39,7 @@ #define NVI_SMBASE(x) ((x) & 0xfffc) #define NVI_SMBASE_SIZE 8 -/* SMBus 2.0 registers */ +/* SMBus 2.0 registers */ #define NVI_SMB_PRTCL 0x00 /* protocol, PEC */ #define NVI_SMB_STS 0x01 /* status */ #define NVI_SMB_ADDR 0x02 /* address */ diff --git a/sys/dev/pci/ohci_pci.c b/sys/dev/pci/ohci_pci.c index d132b45ae..4ae71cb89 100644 --- a/sys/dev/pci/ohci_pci.c +++ b/sys/dev/pci/ohci_pci.c @@ -82,7 +82,7 @@ ohci_pci_match(struct device *parent, void *match, void *aux) PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_USB && PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_OHCI) return (1); - + return (0); } @@ -181,7 +181,7 @@ ohci_pci_attach_deferred(struct device *self) s = splusb(); sc->sc.sc_bus.dying = 0; - + r = ohci_init(&sc->sc); if (r != USBD_NORMAL_COMPLETION) { printf("%s: init failed, error=%d\n", diff --git a/sys/dev/pci/pci.c b/sys/dev/pci/pci.c index 36aff79bc..69dc8751e 100644 --- a/sys/dev/pci/pci.c +++ b/sys/dev/pci/pci.c @@ -500,7 +500,7 @@ pci_probe_device(struct pci_softc *sc, pcitag_t tag, } else addr = PCI_HT_MSI_FIXED_ADDR; - /* + /* * XXX This will fail to enable MSI on systems * that don't use the canonical address. */ @@ -907,7 +907,7 @@ pci_reserve_resources(struct pci_attach_args *pa) default: return (0); } - + for (reg = reg_start; reg < reg_end; reg += 4) { if (!pci_mapreg_probe(pc, tag, reg, &type)) continue; @@ -1186,7 +1186,7 @@ pci_disable_legacy_vga(struct device *dev) /* * This is the user interface to PCI configuration space. */ - + #include #include @@ -1206,7 +1206,7 @@ int pciclose(dev_t dev, int flag, int devtype, struct proc *p); int pciioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p); int -pciopen(dev_t dev, int oflags, int devtype, struct proc *p) +pciopen(dev_t dev, int oflags, int devtype, struct proc *p) { PCIDEBUG(("pciopen ndevs: %d\n" , pci_cd.cd_ndevs)); @@ -1278,7 +1278,7 @@ pciioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p) return ENXIO; /* Check bounds */ - if (pci->sc_bus >= 256 || + if (pci->sc_bus >= 256 || sel->pc_dev >= pci_bus_maxdevs(pci->sc_pc, pci->sc_bus) || sel->pc_func >= 8) return EINVAL; @@ -1308,7 +1308,7 @@ pciioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p) io->pi_reg >= pci_conf_size(pc, tag)) return EINVAL; /* Make sure the register is properly aligned */ - if (io->pi_reg & 0x3) + if (io->pi_reg & 0x3) return EINVAL; io->pi_data = pci_conf_read(pc, tag, io->pi_reg); error = 0; @@ -1676,7 +1676,7 @@ pci_suspend_msix(pci_chipset_tag_t pc, pcitag_t tag, } pci_msix_table_unmap(pc, tag, memt, memh); - + *mc = reg; } diff --git a/sys/dev/pci/pci_map.c b/sys/dev/pci/pci_map.c index dd469f797..8e75f86af 100644 --- a/sys/dev/pci/pci_map.c +++ b/sys/dev/pci/pci_map.c @@ -186,7 +186,7 @@ obsd_pci_mem_find(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t type, #endif return (EINVAL); } - if (type != -1 && + if (type != -1 && PCI_MAPREG_MEM_TYPE(address) != PCI_MAPREG_MEM_TYPE(type)) { #ifdef DEBUG printf("pci_mem_find: expected mem type %08x, found %08x\n", @@ -265,7 +265,7 @@ pci_mapreg_probe(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t *typep) { pcireg_t address, mask, csr; int s; - + s = splhigh(); csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); if (csr & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE)) diff --git a/sys/dev/pci/pcidevs b/sys/dev/pci/pcidevs index 5754dbf61..8c3d4e032 100644 --- a/sys/dev/pci/pcidevs +++ b/sys/dev/pci/pcidevs @@ -5738,7 +5738,7 @@ product INTEL EHL_PSE_LH2OSE 0x4bb3 Elkhart Lake LH2OSE product INTEL EHL_PSE_DMA_0 0x4bb4 Elkhart Lake DMA product INTEL EHL_PSE_DMA_1 0x4bb5 Elkhart Lake DMA product INTEL EHL_PSE_DMA_2 0x4bb6 Elkhart Lake DMA -product INTEL EHL_PSE_PWM 0x4bb7 Elkhart Lake PWM +product INTEL EHL_PSE_PWM 0x4bb7 Elkhart Lake PWM product INTEL EHL_PSE_I2C_0 0x4bb9 Elkhart Lake I2C product INTEL EHL_PSE_I2C_1 0x4bba Elkhart Lake I2C product INTEL EHL_PSE_I2C_2 0x4bbb Elkhart Lake I2C @@ -6964,7 +6964,7 @@ product INTEL RPL_HX_HB_4 0xa728 Core 13G Host product INTEL RPL_HX_HB_5 0xa729 Core 13G Host product INTEL RPL_HX_HB_6 0xa72a Core 13G Host product INTEL RPL_PCIE_2 0xa72d Core 13G PCIE -product INTEL RPL_TBT_PCIE2 0xa72f Core 13G PCIE +product INTEL RPL_TBT_PCIE2 0xa72f Core 13G PCIE product INTEL RPL_TBT_DMA0 0xa73e Core 13G TBT product INTEL RPL_TBT_PCIE1 0xa73f Core 13G PCIE product INTEL RPL_PCIE_3 0xa74d Core 13G PCIE diff --git a/sys/dev/pci/pciide.c b/sys/dev/pci/pciide.c index 53af79c8b..f10eee3eb 100644 --- a/sys/dev/pci/pciide.c +++ b/sys/dev/pci/pciide.c @@ -1664,7 +1664,7 @@ pciide_mapregs_compat(struct pci_attach_args *pa, struct pciide_channel *cp, csr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, csr | PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE); - + wdc_cp->cmd_iot = pa->pa_iot; if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), @@ -3465,7 +3465,7 @@ apollo_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) sc->sc_wdcdev.UDMA_cap = 6; break; default: - /* + /* * Determine the DMA capabilities by looking at the * ISA bridge. */ @@ -6837,7 +6837,7 @@ pdcsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) sc->sc_wdcdev.sc_dev.dv_xname); break; } - + if (sc->sc_pci_ih == NULL) { printf(": couldn't establish native-PCI interrupt"); if (intrstr != NULL) @@ -6902,10 +6902,10 @@ pdcsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) case PCI_PRODUCT_PROMISE_PDC20571: bus_space_write_4(ps->ba5_st, ps->ba5_sh, 0x60, 0x00ff00ff); sc->sc_wdcdev.nchannels = PDC40718_NCHANNELS; - + sc->sc_wdcdev.reset = pdc205xx_do_reset; sc->sc_wdcdev.drv_probe = pdc205xx_drv_probe; - + break; case PCI_PRODUCT_PROMISE_PDC20575: case PCI_PRODUCT_PROMISE_PDC20579: @@ -6916,7 +6916,7 @@ pdcsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) sc->sc_wdcdev.reset = pdc205xx_do_reset; sc->sc_wdcdev.drv_probe = pdc205xx_drv_probe; - + break; } @@ -7803,7 +7803,7 @@ svwsata_write_reg(struct channel_softc *chp, enum wdc_regs reg, u_int8_t val) (reg & _WDC_REGMASK) << 2, val); } } - + void svwsata_lba48_write_reg(struct channel_softc *chp, enum wdc_regs reg, u_int16_t val) { @@ -7815,7 +7815,7 @@ svwsata_lba48_write_reg(struct channel_softc *chp, enum wdc_regs reg, u_int16_t (reg & _WDC_REGMASK) << 2, val); } } - + #define ACARD_IS_850(sc) \ ((sc)->sc_pp->ide_product == PCI_PRODUCT_ACARD_ATP850U) diff --git a/sys/dev/pci/pciidevar.h b/sys/dev/pci/pciidevar.h index 2a3142a09..4bc13924f 100644 --- a/sys/dev/pci/pciidevar.h +++ b/sys/dev/pci/pciidevar.h @@ -72,7 +72,7 @@ struct pciide_softc { /* * Used as a register save space by pciide_activate() - * + * * sc_save[] is for the 6 pci regs starting at PCI_MAPREG_END + 0x18 -- * most IDE chipsets need a subset of those saved. sc_save2 is for * up to 6 other registers, which specific chips might need saved. diff --git a/sys/dev/pci/pcscp.c b/sys/dev/pci/pcscp.c index f1e862802..368a14f13 100644 --- a/sys/dev/pci/pcscp.c +++ b/sys/dev/pci/pcscp.c @@ -92,8 +92,8 @@ struct pcscp_softc { #define PCSCP_WRITE_REG(sc, reg, val) \ bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg) << 2, (val)) -int pcscp_match(struct device *, void *, void *); -void pcscp_attach(struct device *, struct device *, void *); +int pcscp_match(struct device *, void *, void *); +void pcscp_attach(struct device *, struct device *, void *); const struct cfattach pcscp_ca = { sizeof(struct pcscp_softc), pcscp_match, pcscp_attach @@ -216,7 +216,7 @@ pcscp_attach(struct device *parent, struct device *self, void *aux) * formula: 4 * period = (1000 / freq) * 4 */ - sc->sc_minsync = 1000 / sc->sc_freq; + sc->sc_minsync = 1000 / sc->sc_freq; /* Really no limit, but since we want to fit into the TCR... */ sc->sc_maxxfer = 16 * 1024 * 1024; @@ -253,7 +253,7 @@ pcscp_attach(struct device *parent, struct device *self, void *aux) sc->sc_dev.dv_xname, error); goto fail_1; } - if ((error = bus_dmamap_create(esc->sc_dmat, + if ((error = bus_dmamap_create(esc->sc_dmat, sizeof(u_int32_t) * MDL_SIZE, 1, sizeof(u_int32_t) * MDL_SIZE, 0, BUS_DMA_NOWAIT, &esc->sc_mdldmap)) != 0) { printf("%s: unable to map_create for the MDL, error = %d\n", @@ -433,7 +433,7 @@ pcscp_dma_intr(struct ncr53c9x_softc *sc) if (resid) p = *esc->sc_dmaaddr; } - + resid += PCSCP_READ_REG(esc, NCR_TCL) | (PCSCP_READ_REG(esc, NCR_TCM) << 8) | (PCSCP_READ_REG(esc, NCR_TCH) << 16); @@ -462,7 +462,7 @@ pcscp_dma_intr(struct ncr53c9x_softc *sc) * When this happens, the residual byte should be retrieved * via PIO following completion of the BLAST operation.' */ - + if (p) { p += trans; *p = PCSCP_READ_REG(esc, NCR_FIFO); @@ -536,7 +536,7 @@ pcscp_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len, } /* set transfer length */ - WRITE_DMAREG(esc, DMA_STC, *dmasize); + WRITE_DMAREG(esc, DMA_STC, *dmasize); /* set up MDL */ mdl = esc->sc_mdladdr; @@ -548,7 +548,7 @@ pcscp_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len, s_addr -= s_offset; /* set the first MDL and offset */ - WRITE_DMAREG(esc, DMA_SPA, s_offset); + WRITE_DMAREG(esc, DMA_SPA, s_offset); *mdl++ = htole32(s_addr); /* the rest dmamap segments are aligned with 4k boundary */ @@ -575,7 +575,7 @@ pcscp_dma_go(struct ncr53c9x_softc *sc) /* sync MDL */ bus_dmamap_sync(esc->sc_dmat, mdldmap, - 0, sizeof(u_int32_t) * dmap->dm_nsegs, BUS_DMASYNC_PREWRITE); + 0, sizeof(u_int32_t) * dmap->dm_nsegs, BUS_DMASYNC_PREWRITE); /* set Starting MDL Address */ WRITE_DMAREG(esc, DMA_SMDLA, mdldmap->dm_segs[0].ds_addr); diff --git a/sys/dev/pci/piixpm.c b/sys/dev/pci/piixpm.c index fa58f748c..c503d3c67 100644 --- a/sys/dev/pci/piixpm.c +++ b/sys/dev/pci/piixpm.c @@ -145,7 +145,7 @@ piixpm_attach(struct device *parent, struct device *self, void *aux) (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ATI && PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ATI_SBX00_SMB && PCI_REVISION(pa->pa_class) >= 0x40)) { - /* + /* * On the AMD SB800+, the SMBus I/O registers are well * hidden. We need to look at the "SMBus0En" Power * Management register to find out where they live. diff --git a/sys/dev/pci/ppb.c b/sys/dev/pci/ppb.c index cf7cb120c..e61c72f9f 100644 --- a/sys/dev/pci/ppb.c +++ b/sys/dev/pci/ppb.c @@ -514,8 +514,8 @@ ppbactivate(struct device *self, int act) break; case DVACT_POWERDOWN: rv = config_activate_children(self, act); - - if (pci_dopm) { + + if (pci_dopm) { /* * Place the bridge into the lowest possible * power state. @@ -555,7 +555,7 @@ ppb_alloc_busrange(struct ppb_softc *sc, struct pci_attach_args *pa, if (busrange == 0) { for (busrange = 16; busrange > 0; busrange >>= 1) { - if (extent_alloc(pa->pa_busex, busrange, 1, 0, 0, + if (extent_alloc(pa->pa_busex, busrange, 1, 0, 0, EX_NOWAIT, &busnum) == 0) break; } diff --git a/sys/dev/pci/ppbreg.h b/sys/dev/pci/ppbreg.h index 50a8b0a75..c111f4aca 100644 --- a/sys/dev/pci/ppbreg.h +++ b/sys/dev/pci/ppbreg.h @@ -96,7 +96,7 @@ #define PPB_MEM_SHIFT 16 #define PPB_MEM_MIN 0x00100000 -/* +/* * bridge control register (see table 3.9 of ppb rev. 1.1) * * Note these are in the *upper* 16 bits of the Bridge Control diff --git a/sys/dev/pci/qla_pci.c b/sys/dev/pci/qla_pci.c index 4102f6c97..56491c330 100644 --- a/sys/dev/pci/qla_pci.c +++ b/sys/dev/pci/qla_pci.c @@ -167,7 +167,7 @@ qla_pci_attach(struct device *parent, struct device *self, void *aux) sc->sc_isp_gen = QLA_GEN_ISP2200; sc->sc_isp_type = QLA_ISP2200; break; - + case PCI_PRODUCT_QLOGIC_ISP2300: sc->sc_isp_type = QLA_ISP2300; sc->sc_isp_gen = QLA_GEN_ISP23XX; diff --git a/sys/dev/pci/qlereg.h b/sys/dev/pci/qlereg.h index 74471e91e..dddc0895f 100644 --- a/sys/dev/pci/qlereg.h +++ b/sys/dev/pci/qlereg.h @@ -162,7 +162,7 @@ struct qle_nvram { u_int64_t port_name; u_int64_t node_name; - + u_int16_t login_retry; u_int16_t link_down_on_nos; u_int16_t int_delay_timer; @@ -574,7 +574,7 @@ struct qle_fcp_cmnd { u_int8_t fcp_task_attr; u_int8_t fcp_task_mgmt; u_int8_t fcp_add_cdb_len; - + u_int8_t fcp_cdb[52]; /* 64 bytes total */ } __packed __aligned(64); diff --git a/sys/dev/pci/rtsx_pci.c b/sys/dev/pci/rtsx_pci.c index 08b4ab7a1..dd36c6d74 100644 --- a/sys/dev/pci/rtsx_pci.c +++ b/sys/dev/pci/rtsx_pci.c @@ -48,7 +48,7 @@ rtsx_pci_match(struct device *parent, void *match, void *aux) { struct pci_attach_args *pa = aux; - /* + /* * Explicitly match the UNDEFINED device class only. Some RTS5209 * devices advertise a SYSTEM/SDHC class in addition to the UNDEFINED * device class. Let sdhc(4) handle the SYSTEM/SDHC ones. diff --git a/sys/dev/pci/sv.c b/sys/dev/pci/sv.c index 841738c45..fed0007e8 100644 --- a/sys/dev/pci/sv.c +++ b/sys/dev/pci/sv.c @@ -15,7 +15,7 @@ * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. The author's name or those of the contributors may be used to - * endorse or promote products derived from this software without + * endorse or promote products derived from this software without * specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR(S) AND CONTRIBUTORS @@ -239,7 +239,7 @@ sv_attach(struct device *parent, struct device *self, void *aux) pci_intr_handle_t ih; bus_size_t iosize; char const *intrstr; - u_int32_t dmareg, dmaio; + u_int32_t dmareg, dmaio; u_int8_t reg; sc->sc_pci_chipset_tag = pc; @@ -257,10 +257,10 @@ sv_attach(struct device *parent, struct device *self, void *aux) dmareg = pci_conf_read(pa->pa_pc, pa->pa_tag, SV_DMAA_CONFIG_OFF); iosize = 0x10; dmaio = dmareg & ~(iosize - 1); - + if (dmaio) { dmareg &= 0xF; - + if (bus_space_map(sc->sc_iot, dmaio, iosize, 0, &sc->sc_dmaa_ioh)) { /* The BIOS assigned us some bad I/O address! Make sure to clear and disable this DMA before we enable the device */ @@ -271,7 +271,7 @@ sv_attach(struct device *parent, struct device *self, void *aux) } pci_conf_write(pa->pa_pc, pa->pa_tag, SV_DMAA_CONFIG_OFF, - dmaio | dmareg | + dmaio | dmareg | SV_DMA_CHANNEL_ENABLE | SV_DMAA_EXTENDED_ADDR); sc->sc_dma_configured |= SV_DMAA_CONFIGURED; } @@ -284,13 +284,13 @@ sv_attach(struct device *parent, struct device *self, void *aux) if (bus_space_map(sc->sc_iot, dmaio, iosize, 0, &sc->sc_dmac_ioh)) { /* The BIOS assigned us some bad I/O address! Make sure to clear and disable this DMA before we enable the device */ - pci_conf_write (pa->pa_pc, pa->pa_tag, SV_DMAC_CONFIG_OFF, - dmareg & ~SV_DMA_CHANNEL_ENABLE); + pci_conf_write (pa->pa_pc, pa->pa_tag, SV_DMAC_CONFIG_OFF, + dmareg & ~SV_DMA_CHANNEL_ENABLE); printf (": can't map DMA i/o space\n"); goto enable; } - pci_conf_write(pa->pa_pc, pa->pa_tag, SV_DMAC_CONFIG_OFF, + pci_conf_write(pa->pa_pc, pa->pa_tag, SV_DMAC_CONFIG_OFF, dmaio | dmareg | SV_DMA_CHANNEL_ENABLE); sc->sc_dma_configured |= SV_DMAC_CONFIGURED; } @@ -374,7 +374,7 @@ sv_dumpregs(struct sv_softc *sc) } for (idx = 0; idx < 0x10; idx++) { - printf ("DMA %02x = %02x\n", idx, + printf ("DMA %02x = %02x\n", idx, bus_space_read_1(sc->sc_iot, sc->sc_dmaa_ioh, idx)); } @@ -421,7 +421,7 @@ sv_allocmem(struct sv_softc *sc, size_t size, size_t align, struct sv_dma *p) if (error) return (error); - error = bus_dmamem_map(sc->sc_dmatag, p->segs, p->nsegs, p->size, + error = bus_dmamem_map(sc->sc_dmatag, p->segs, p->nsegs, p->size, &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); if (error) goto free; @@ -431,7 +431,7 @@ sv_allocmem(struct sv_softc *sc, size_t size, size_t align, struct sv_dma *p) if (error) goto unmap; - error = bus_dmamap_load(sc->sc_dmatag, p->map, p->addr, p->size, NULL, + error = bus_dmamap_load(sc->sc_dmatag, p->map, p->addr, p->size, NULL, BUS_DMA_NOWAIT); if (error) goto destroy; @@ -475,7 +475,7 @@ sv_open(void *addr, int flags) return (ENXIO); for (dmaio = 0xa000; dmaio < 0xb000; dmaio += iosize) { - if (!bus_space_map(sc->sc_iot, dmaio, iosize, 0, + if (!bus_space_map(sc->sc_iot, dmaio, iosize, 0, &sc->sc_dmaa_ioh)) { goto found_dmaa; } @@ -484,10 +484,10 @@ sv_open(void *addr, int flags) sc->sc_dma_configured |= SV_DMAA_TRIED_CONFIGURE; return (ENXIO); found_dmaa: - + pci_conf_write(sc->sc_pci_chipset_tag, sc->sc_pci_tag, - SV_DMAA_CONFIG_OFF, - dmaio | SV_DMA_CHANNEL_ENABLE + SV_DMAA_CONFIG_OFF, + dmaio | SV_DMA_CHANNEL_ENABLE | SV_DMAA_EXTENDED_ADDR); sc->sc_dma_configured |= SV_DMAA_CONFIGURED; @@ -504,18 +504,18 @@ sv_open(void *addr, int flags) return (ENXIO); for (dmaio = 0xa000; dmaio < 0xb000; dmaio += iosize) { - if (!bus_space_map(sc->sc_iot, dmaio, iosize, 0, + if (!bus_space_map(sc->sc_iot, dmaio, iosize, 0, &sc->sc_dmac_ioh)) { goto found_dmac; } } - sc->sc_dma_configured |= SV_DMAC_TRIED_CONFIGURE; + sc->sc_dma_configured |= SV_DMAC_TRIED_CONFIGURE; return (ENXIO); found_dmac: - + pci_conf_write(sc->sc_pci_chipset_tag, sc->sc_pci_tag, - SV_DMAC_CONFIG_OFF, + SV_DMAC_CONFIG_OFF, dmaio | SV_DMA_CHANNEL_ENABLE); sc->sc_dma_configured |= SV_DMAC_CONFIGURED; @@ -543,7 +543,7 @@ void sv_close(void *addr) { struct sv_softc *sc = addr; - + sv_halt_in_dma(sc); sv_halt_out_dma(sc); @@ -558,7 +558,7 @@ sv_set_params(void *addr, int setmode, int usemode, struct sv_softc *sc = addr; u_int32_t mode, val; u_int8_t reg; - + switch (p->encoding) { case AUDIO_ENCODING_SLINEAR_LE: if (p->precision != 16) @@ -627,7 +627,7 @@ sv_set_params(void *addr, int setmode, int usemode, if ((goal_f_out * (1 << a)) >= 80000000) break; } - + /* a != 8 because sample_rate >= 2000 */ for (n = 33; n > 2; n--) { @@ -636,14 +636,14 @@ sv_set_params(void *addr, int setmode, int usemode, m = (goal_f_out * n * (1 << a)) / F_REF; if ((m > 257) || (m < 3)) continue; - + pll_sample = (m * F_REF) / (n * (1 << a)); pll_sample /= 512; /* Threshold might be good here */ error = pll_sample - r->sample_rate; error = abs(error); - + if (error < best_error) { best_error = error; best_n = n; @@ -651,11 +651,11 @@ sv_set_params(void *addr, int setmode, int usemode, if (error == 0) break; } } - + best_n -= 2; best_m -= 2; - + sv_write_indirect(sc, SV_ADC_PLL_M, best_m); sv_write_indirect(sc, SV_ADC_PLL_N, best_n | (a << SV_PLL_R_SHIFT)); } @@ -675,7 +675,7 @@ sv_dma_init_input(void *addr, void *buf, int cc) struct sv_dma *p; int dma_count; - DPRINTF(("sv_dma_init_input: dma start loop input addr=%p cc=%d\n", + DPRINTF(("sv_dma_init_input: dma start loop input addr=%p cc=%d\n", buf, cc)); for (p = sc->sc_dmas; p && KERNADDR(p) != buf; p = p->next) ; @@ -729,8 +729,8 @@ sv_dma_output(void *addr, void *p, int cc, void (*intr)(void *), void *arg) struct sv_softc *sc = addr; u_int8_t mode; - DPRINTFN(1, - ("sv_dma_output: sc=%p buf=%p cc=%d intr=%p(%p)\n", + DPRINTFN(1, + ("sv_dma_output: sc=%p buf=%p cc=%d intr=%p(%p)\n", addr, p, cc, intr, arg)); sc->sc_pintr = intr; sc->sc_parg = arg; @@ -754,7 +754,7 @@ sv_dma_input(void *addr, void *p, int cc, void (*intr)(void *), void *arg) struct sv_softc *sc = addr; u_int8_t mode; - DPRINTFN(1, ("sv_dma_input: sc=%p buf=%p cc=%d intr=%p(%p)\n", + DPRINTFN(1, ("sv_dma_input: sc=%p buf=%p cc=%d intr=%p(%p)\n", addr, p, cc, intr, arg)); sc->sc_rintr = intr; sc->sc_rarg = arg; @@ -777,7 +777,7 @@ sv_halt_out_dma(void *addr) { struct sv_softc *sc = addr; u_int8_t mode; - + DPRINTF(("sv: sv_halt_out_dma\n")); mtx_enter(&audio_lock); mode = sv_read_indirect(sc, SV_PLAY_RECORD_ENABLE); @@ -793,7 +793,7 @@ sv_halt_in_dma(void *addr) { struct sv_softc *sc = addr; u_int8_t mode; - + DPRINTF(("sv: sv_halt_in_dma\n")); mtx_enter(&audio_lock); mode = sv_read_indirect(sc, SV_PLAY_RECORD_ENABLE); @@ -826,18 +826,18 @@ static const struct { } ports[] = { { SV_LEFT_AUX1_INPUT_CONTROL, SV_RIGHT_AUX1_INPUT_CONTROL, SV_AUX1_MASK, SV_INPUT_CLASS, "aux1" }, - { SV_LEFT_CD_INPUT_CONTROL, SV_RIGHT_CD_INPUT_CONTROL, SV_CD_MASK, + { SV_LEFT_CD_INPUT_CONTROL, SV_RIGHT_CD_INPUT_CONTROL, SV_CD_MASK, SV_INPUT_CLASS, AudioNcd }, { SV_LEFT_LINE_IN_INPUT_CONTROL, SV_RIGHT_LINE_IN_INPUT_CONTROL, SV_LINE_IN_MASK, SV_INPUT_CLASS, AudioNline }, { SV_MIC_INPUT_CONTROL, 0, SV_MIC_MASK, SV_INPUT_CLASS, AudioNmicrophone }, - { SV_LEFT_SYNTH_INPUT_CONTROL, SV_RIGHT_SYNTH_INPUT_CONTROL, + { SV_LEFT_SYNTH_INPUT_CONTROL, SV_RIGHT_SYNTH_INPUT_CONTROL, SV_SYNTH_MASK, SV_INPUT_CLASS, AudioNfmsynth }, { SV_LEFT_AUX2_INPUT_CONTROL, SV_RIGHT_AUX2_INPUT_CONTROL, SV_AUX2_MASK, SV_INPUT_CLASS, "aux2" }, { SV_LEFT_PCM_INPUT_CONTROL, SV_RIGHT_PCM_INPUT_CONTROL, SV_PCM_MASK, SV_INPUT_CLASS, AudioNdac }, - { SV_LEFT_MIXER_OUTPUT_CONTROL, SV_RIGHT_MIXER_OUTPUT_CONTROL, + { SV_LEFT_MIXER_OUTPUT_CONTROL, SV_RIGHT_MIXER_OUTPUT_CONTROL, SV_MIXER_OUT_MASK, SV_OUTPUT_CLASS, AudioNmaster } }; @@ -864,7 +864,7 @@ static const struct { #define SV_RECORD_GAIN (SV_LAST_MIXER + 3) #define SV_SRS_MODE (SV_LAST_MIXER + 4) -int +int sv_query_devinfo(void *addr, mixer_devinfo_t *dip) { @@ -899,7 +899,7 @@ sv_query_devinfo(void *addr, mixer_devinfo_t *dip) dip->un.v.num_channels = 2; else dip->un.v.num_channels = 1; - + strlcpy(dip->un.v.units.name, AudioNvolume, sizeof dip->un.v.units.name); } else { @@ -992,11 +992,11 @@ sv_mixer_set_port(void *addr, mixer_ctrl_t *cp) idx = off / SV_DEVICES_PER_PORT; if (mute) { - if (cp->type != AUDIO_MIXER_ENUM) + if (cp->type != AUDIO_MIXER_ENUM) return (EINVAL); reg = sv_read_indirect(sc, ports[idx].l_port); - if (cp->un.ord) + if (cp->un.ord) reg |= SV_MUTE_BIT; else reg &= ~SV_MUTE_BIT; @@ -1004,7 +1004,7 @@ sv_mixer_set_port(void *addr, mixer_ctrl_t *cp) if (ports[idx].r_port) { reg = sv_read_indirect(sc, ports[idx].r_port); - if (cp->un.ord) + if (cp->un.ord) reg |= SV_MUTE_BIT; else reg &= ~SV_MUTE_BIT; @@ -1067,7 +1067,7 @@ sv_mixer_set_port(void *addr, mixer_ctrl_t *cp) if (record_sources[idx].idx == cp->un.ord) goto found; } - + return (EINVAL); found: @@ -1092,14 +1092,14 @@ sv_mixer_set_port(void *addr, mixer_ctrl_t *cp) if (cp->un.value.num_channels != 1) return (EINVAL); - val = (cp->un.value.level[AUDIO_MIXER_LEVEL_MONO] * SV_REC_GAIN_MASK) + val = (cp->un.value.level[AUDIO_MIXER_LEVEL_MONO] * SV_REC_GAIN_MASK) / AUDIO_MAX_GAIN; reg = sv_read_indirect(sc, SV_LEFT_ADC_INPUT_CONTROL); reg &= ~SV_REC_GAIN_MASK; reg |= val; sv_write_indirect(sc, SV_LEFT_ADC_INPUT_CONTROL, reg); - + reg = sv_read_indirect(sc, SV_RIGHT_ADC_INPUT_CONTROL); reg &= ~SV_REC_GAIN_MASK; reg |= val; @@ -1119,7 +1119,7 @@ sv_mixer_set_port(void *addr, mixer_ctrl_t *cp) } else { reg &= ~SV_MIC_BOOST_BIT; } - + sv_write_indirect(sc, SV_LEFT_ADC_INPUT_CONTROL, reg); return (0); @@ -1133,7 +1133,7 @@ sv_mixer_set_port(void *addr, mixer_ctrl_t *cp) } else { reg |= SV_SRS_SPACE_ONOFF; } - + sv_write_indirect(sc, SV_SRS_SPACE_CONTROL, reg); return (0); } @@ -1155,7 +1155,7 @@ sv_mixer_get_port(void *addr, mixer_ctrl_t *cp) int idx = off / 2; if (mute) { - if (cp->type != AUDIO_MIXER_ENUM) + if (cp->type != AUDIO_MIXER_ENUM) return (EINVAL); reg = sv_read_indirect(sc, ports[idx].l_port); @@ -1184,10 +1184,10 @@ sv_mixer_get_port(void *addr, mixer_ctrl_t *cp) reg = sv_read_indirect(sc, ports[idx].r_port); reg &= ports[idx].mask; - + val = AUDIO_MAX_GAIN - ((reg * AUDIO_MAX_GAIN) / ports[idx].mask); cp->un.value.level[AUDIO_MIXER_LEVEL_RIGHT] = val; - } else + } else cp->un.value.level[AUDIO_MIXER_LEVEL_MONO] = val; } @@ -1212,7 +1212,7 @@ sv_mixer_get_port(void *addr, mixer_ctrl_t *cp) return (EINVAL); reg = sv_read_indirect(sc, SV_LEFT_ADC_INPUT_CONTROL) & SV_REC_GAIN_MASK; - cp->un.value.level[AUDIO_MIXER_LEVEL_MONO] = + cp->un.value.level[AUDIO_MIXER_LEVEL_MONO] = (((unsigned int)reg) * AUDIO_MAX_GAIN) / SV_REC_GAIN_MASK; return (0); diff --git a/sys/dev/pci/tcpcib.c b/sys/dev/pci/tcpcib.c index 829341fe0..a6d600fac 100644 --- a/sys/dev/pci/tcpcib.c +++ b/sys/dev/pci/tcpcib.c @@ -270,7 +270,7 @@ tcpcib_activate(struct device *self, int act) { struct tcpcib_softc *sc = (struct tcpcib_softc *)self; int rv = 0; - + switch (act) { case DVACT_SUSPEND: rv = config_activate_children(self, act); diff --git a/sys/dev/pci/tga.c b/sys/dev/pci/tga.c index 222fa7778..dbf69c8b2 100644 --- a/sys/dev/pci/tga.c +++ b/sys/dev/pci/tga.c @@ -6,17 +6,17 @@ * All rights reserved. * * Author: Chris G. Demetriou - * + * * Permission to use, copy, modify and distribute this software and * its documentation is hereby granted, provided that both the copyright * notice and this permission notice appear in all copies of the * software, derivative works or modified versions, and any portions * thereof, and that both notices appear in supporting documentation. - * - * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" - * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. - * + * * Carnegie Mellon requests users of this software to return to * * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU @@ -236,7 +236,7 @@ tga_getdevconfig(memt, pc, tag, dc) dc->dc_paddr = ALPHA_K0SEG_TO_PHYS(dc->dc_vaddr); /* XXX */ #endif DPRINTF("tga_getdevconfig: allocating subregion\n"); - bus_space_subregion(dc->dc_memt, dc->dc_memh, + bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA_MEM_CREGS, TGA_CREGS_SIZE, &dc->dc_regs); @@ -274,7 +274,7 @@ tga_getdevconfig(memt, pc, tag, dc) if (dc->dc_tga2) { tga2_init(dc); } - + i = TGARREG(dc, TGA_REG_VHCR) & 0x1ff; DPRINTF("tga_getdevconfig: TGA_REG_VHCR & 0x1ff = %d\n", i); switch (i) { /* XXX */ @@ -319,14 +319,14 @@ tga_getdevconfig(memt, pc, tag, dc) 1 * tgac->tgac_vvbr_units; dc->dc_blanked = 1; tga_unblank(dc); - + DPRINTF("tga_getdevconfig: dc_videobase = 0x%016llx\n" " dc_vaddr = 0x%016llx\n" " tgac_dbuf[0] = %d\n" " tgac_vvbr_units = %d\n", dc->dc_videobase, dc->dc_vaddr, tgac->tgac_dbuf[0], tgac->tgac_vvbr_units); - + /* * Set all bits in the pixel mask, to enable writes to all pixels. * It seems that the console firmware clears some of them @@ -362,10 +362,10 @@ tga_getdevconfig(memt, pc, tag, dc) DPRINTF("tga_getdevconfig: wsfont_init\n"); wsfont_init(); - if (rip->ri_width > 80*12) + if (rip->ri_width > 80*12) /* High res screen, choose a big font */ cookie = wsfont_find(NULL, 12, 0, 0); - else + else /* lower res, choose a 8 pixel wide font */ cookie = wsfont_find(NULL, 8, 0, 0); if (cookie <= 0) @@ -384,17 +384,17 @@ tga_getdevconfig(memt, pc, tag, dc) rip->ri_wsfcookie = cookie; /* fill screen size */ rasops_init(rip, rip->ri_height / rip->ri_font->fontheight, - rip->ri_width / rip->ri_font->fontwidth); - + rip->ri_width / rip->ri_font->fontwidth); + /* add our accelerated functions */ - /* XXX shouldn't have to do this; rasops should leave non-NULL + /* XXX shouldn't have to do this; rasops should leave non-NULL * XXX entries alone. */ rip->ri_ops.copyrows = tga_copyrows; rip->ri_ops.eraserows = tga_eraserows; rip->ri_ops.erasecols = tga_erasecols; rip->ri_ops.copycols = tga_copycols; - rip->ri_ops.putchar = tga_putchar; + rip->ri_ops.putchar = tga_putchar; tga_stdscreen.nrows = rip->ri_rows; tga_stdscreen.ncols = rip->ri_cols; @@ -489,18 +489,18 @@ tgaattach(parent, self, aux) "bt485_funcs\n", (sc->sc_dc->dc_tgaconf->ramdac_funcs == bt485_funcs) ? "==" : "!="); - if (sc->sc_dc->dc_tgaconf->ramdac_funcs == bt485_funcs) - sc->sc_dc->dc_ramdac_cookie = + if (sc->sc_dc->dc_tgaconf->ramdac_funcs == bt485_funcs) + sc->sc_dc->dc_ramdac_cookie = sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, tga_sched_update, tga_ramdac_wr, tga_ramdac_rd); else - sc->sc_dc->dc_ramdac_cookie = + sc->sc_dc->dc_ramdac_cookie = sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, tga_sched_update, tga_bt463_wr, tga_bt463_rd); } else { DPRINTF("tgaattach: sc->sc_dc->dc_tga2\n"); - sc->sc_dc->dc_ramdac_cookie = - sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, + sc->sc_dc->dc_ramdac_cookie = + sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, tga_sched_update, tga2_ramdac_wr, tga2_ramdac_rd); /* XXX this is a bit of a hack, setting the dotclock here */ @@ -548,14 +548,14 @@ tgaattach(parent, self, aux) #endif } -void +void tga_config_interrupts (d) struct device *d; { struct tga_softc *sc = (struct tga_softc *)d; sc->sc_dc->dc_intrenabled = 1; } - + int tga_ioctl(v, cmd, data, flag, p) @@ -585,7 +585,7 @@ tga_ioctl(v, cmd, data, flag, p) default: /* XXX it this useful, except for not breaking Xtga? */ TGAWREG(dc, TGA_REG_VVBR, 1); - break; + break; } break; @@ -663,7 +663,7 @@ tga_sched_update(v, f) TGAWREG(dc, TGA_REG_SISR, 0x00000001); TGAREGWB(dc, TGA_REG_SISR, 1); } - + return 0; } @@ -685,7 +685,7 @@ tga_intr(v) TGAREGWB(dc, TGA_REG_SISR, 1); /* This was our interrupt, even if we're puzzled as to why * we got it. Don't make the interrupt handler think it - * was a stray. + * was a stray. */ return -1; } else { @@ -715,7 +715,7 @@ tga_mmap(v, offset, prot) return -1; if (sc->sc_mode == WSDISPLAYIO_MODE_DUMBFB) { - /* + /* * The framebuffer starts at the upper half of tga mem */ offset += dc->dc_tgaconf->tgac_cspace_size / 2; @@ -744,7 +744,7 @@ tga_alloc_screen(v, type, cookiep, curxp, curyp, attrp) *cookiep = &sc->sc_dc->dc_rinfo; /* one and only for now */ *curxp = 0; *curyp = 0; - sc->sc_dc->dc_rinfo.ri_ops.pack_attr(&sc->sc_dc->dc_rinfo, + sc->sc_dc->dc_rinfo.ri_ops.pack_attr(&sc->sc_dc->dc_rinfo, 0, 0, 0, &defattr); *attrp = defattr; sc->nscreens++; @@ -875,7 +875,7 @@ tga_cnattach(iot, memt, pc, bus, device, function) } dcp->dc_rinfo.ri_ops.pack_attr(&dcp->dc_rinfo, 0, 0, 0, &defattr); wsdisplay_cnattach(&tga_stdscreen, &dcp->dc_rinfo, 0, 0, defattr); - + return(0); } @@ -957,7 +957,7 @@ tga_builtin_set_cursor(dc, cursorp) TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) & ~0x04); } if (v & WSDISPLAY_CURSOR_DOPOS) { - TGAWREG(dc, TGA_REG_CXYR, + TGAWREG(dc, TGA_REG_CXYR, ((cursorp->pos.y & 0xfff) << 12) | (cursorp->pos.x & 0xfff)); } if (v & WSDISPLAY_CURSOR_DOCMAP) { @@ -1194,9 +1194,9 @@ tga_rop_vtov(dst, dx, dy, w, h, src, sx, sy) srcb = sy * src->ri_stride + sx * (src->ri_depth/8); dstb = dy * dst->ri_stride + dx * (dst->ri_depth/8); - tga_srcb = offset + (sy + src->ri_yorigin) * src->ri_stride + + tga_srcb = offset + (sy + src->ri_yorigin) * src->ri_stride + (sx + src->ri_xorigin) * (src->ri_depth/8); - tga_dstb = offset + (dy + dst->ri_yorigin) * dst->ri_stride + + tga_dstb = offset + (dy + dst->ri_yorigin) * dst->ri_stride + (dx + dst->ri_xorigin) * (dst->ri_depth/8); TGAWALREG(dc, TGA_REG_GMOR, 3, 0x0007); /* Copy mode */ @@ -1218,7 +1218,7 @@ tga_rop_vtov(dst, dx, dy, w, h, src, sx, sy) x <= xend && xleft >= 4*64; x += XINC256, xleft -= XINC256) { - /* XXX XXX Eight writes to different addresses should fill + /* XXX XXX Eight writes to different addresses should fill * XXX XXX up the write buffers on 21064 and 21164 chips, * XXX XXX but later CPUs might have larger write buffers which * XXX XXX require further unrolling of this loop, or the @@ -1265,7 +1265,7 @@ tga_rop_vtov(dst, dx, dy, w, h, src, sx, sy) x >= xend && xleft >= 4*64; x -= XINC256, xleft -= XINC256) { - /* XXX XXX Eight writes to different addresses should fill + /* XXX XXX Eight writes to different addresses should fill * XXX XXX up the write buffers on 21064 and 21164 chips, * XXX XXX but later CPUs might have larger write buffers which * XXX XXX require further unrolling of this loop, or the @@ -1339,7 +1339,7 @@ tga_putchar(c, row, col, uc, attr) ri->ri_ops.unpack_attr(c, attr, &fg, &bg, &ul); TGAWREG(dc, TGA_REG_GFGR, ri->ri_devcmap[fg]); TGAWREG(dc, TGA_REG_GBGR, ri->ri_devcmap[bg]); - + /* Set raster operation to "copy"... */ if (ri->ri_depth == 8) TGAWREG(dc, TGA_REG_GOPR, 0x3); @@ -1351,15 +1351,15 @@ tga_putchar(c, row, col, uc, attr) /* Set drawing mode to opaque stipple. */ TGAWREG(dc, TGA_REG_GMOR, 0x1); - + /* Insert write barrier before actually sending data */ /* XXX Abuses the fact that there is only one write barrier on Alphas */ TGAREGWB(dc, TGA_REG_GMOR, 1); while (height--) { /* The actual stipple write */ - *rp = fr[0] | (fr[1] << 8) | (fr[2] << 16) | (fr[3] << 24); - + *rp = fr[0] | (fr[1] << 8) | (fr[2] << 16) | (fr[3] << 24); + fr += fs; rp = (int32_t *)((caddr_t)rp + ri->ri_stride); } @@ -1418,7 +1418,7 @@ tga_eraserows(c, row, num, attr) /* Set drawing mode to block fill. */ TGAWREG(dc, TGA_REG_GMOR, 0x2d); - + /* Insert write barrier before actually sending data */ /* XXX Abuses the fact that there is only one write barrier on Alphas */ TGAREGWB(dc, TGA_REG_GMOR, 1); @@ -1430,7 +1430,7 @@ tga_eraserows(c, row, num, attr) /* Set graphics mode back to normal. */ TGAWREG(dc, TGA_REG_GMOR, 0); - + return 0; } @@ -1475,7 +1475,7 @@ tga_erasecols (c, row, col, num, attr) /* Set drawing mode to block fill. */ TGAWREG(dc, TGA_REG_GMOR, 0x2d); - + /* Insert write barrier before actually sending data */ /* XXX Abuses the fact that there is only one write barrier on Alphas */ TGAREGWB(dc, TGA_REG_GMOR, 1); @@ -1519,7 +1519,7 @@ tga2_ramdac_wr(v, btreg, val) if (btreg > BT485_REG_MAX) panic("tga_ramdac_wr: reg %d out of range", btreg); - bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC + + bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC + (0xe << 12) + (btreg << 8), 4, &ramdac); bus_space_write_4(dc->dc_memt, ramdac, 0, val & 0xff); bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_WRITE); @@ -1533,11 +1533,11 @@ tga_bt463_rd(v, btreg) struct tga_devconfig *dc = v; tga_reg_t rdval; - /* - * Strobe CE# (high->low->high) since status and data are latched on + /* + * Strobe CE# (high->low->high) since status and data are latched on * the falling and rising edges (respectively) of this active-low signal. */ - + TGAREGWB(dc, TGA_REG_EPSR, 1); TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1); TGAREGWB(dc, TGA_REG_EPSR, 1); @@ -1560,12 +1560,12 @@ tga_bt463_wr(v, btreg, val) { struct tga_devconfig *dc = v; - /* + /* * In spite of the 21030 documentation, to set the MPU bus bits for * a write, you set them in the upper bits of EPDR, not EPSR. */ - - /* + + /* * Strobe CE# (high->low->high) since status and data are latched on * the falling and rising edges of this active-low signal. */ @@ -1609,7 +1609,7 @@ tga2_ramdac_rd(v, btreg) if (btreg > BT485_REG_MAX) panic("tga_ramdac_rd: reg %d out of range", btreg); - bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC + + bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC + (0xe << 12) + (btreg << 8), 4, &ramdac); retval = bus_space_read_4(dc->dc_memt, ramdac, 0) & 0xff; bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_READ); @@ -1646,19 +1646,19 @@ tga2_init(dc) tga2_ics9110_wr(dc, m->dotclock); } #if 0 - TGAWREG(dc, TGA_REG_VHCR, + TGAWREG(dc, TGA_REG_VHCR, ((m->hbp / 4) << 21) | ((m->hsync / 4) << 14) | (((m->hfp - 4) / 4) << 9) | ((m->cols + 4) / 4)); #else - TGAWREG(dc, TGA_REG_VHCR, + TGAWREG(dc, TGA_REG_VHCR, ((m->hbp / 4) << 21) | ((m->hsync / 4) << 14) | (((m->hfp) / 4) << 9) | ((m->cols) / 4)); #endif - TGAWREG(dc, TGA_REG_VVCR, + TGAWREG(dc, TGA_REG_VVCR, (m->vbp << 22) | (m->vsync << 16) | (m->vfp << 11) | @@ -1730,14 +1730,14 @@ tga2_ics9110_wr(dc, dotclock) for (i = 24; i > 0; i--) { u_int32_t writeval; - + writeval = valU & 0x1; - if (i == 1) - writeval |= 0x2; + if (i == 1) + writeval |= 0x2; valU >>= 1; bus_space_write_4(dc->dc_memt, clock, 0, writeval); bus_space_barrier(dc->dc_memt, clock, 0, 4, BUS_SPACE_BARRIER_WRITE); - } + } bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV + TGA2_MEM_CLOCK + (0xe << 12) + (0x1 << 11) + (0x1 << 11), 4, &clock); /* XXX */ diff --git a/sys/dev/pci/tgareg.h b/sys/dev/pci/tgareg.h index 76f8c7e02..90693bc28 100644 --- a/sys/dev/pci/tgareg.h +++ b/sys/dev/pci/tgareg.h @@ -6,17 +6,17 @@ * All rights reserved. * * Author: Chris G. Demetriou - * + * * Permission to use, copy, modify and distribute this software and * its documentation is hereby granted, provided that both the copyright * notice and this permission notice appear in all copies of the * software, derivative works or modified versions, and any portions * thereof, and that both notices appear in supporting documentation. - * - * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" - * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. - * + * * Carnegie Mellon requests users of this software to return to * * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU diff --git a/sys/dev/pci/tgavar.h b/sys/dev/pci/tgavar.h index 968c53d1f..340eb7206 100644 --- a/sys/dev/pci/tgavar.h +++ b/sys/dev/pci/tgavar.h @@ -6,17 +6,17 @@ * All rights reserved. * * Author: Chris G. Demetriou - * + * * Permission to use, copy, modify and distribute this software and * its documentation is hereby granted, provided that both the copyright * notice and this permission notice appear in all copies of the * software, derivative works or modified versions, and any portions * thereof, and that both notices appear in supporting documentation. - * - * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" - * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. - * + * * Carnegie Mellon requests users of this software to return to * * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU @@ -92,7 +92,7 @@ struct tga_devconfig { void (*dc_ramdac_intr)(void *); int dc_intrenabled; /* can we depend on interrupts yet? */ }; - + struct tga_softc { struct device sc_dev; diff --git a/sys/dev/pci/uhci_pci.c b/sys/dev/pci/uhci_pci.c index 1142f3022..2a245ccf1 100644 --- a/sys/dev/pci/uhci_pci.c +++ b/sys/dev/pci/uhci_pci.c @@ -77,7 +77,7 @@ uhci_pci_match(struct device *parent, void *match, void *aux) PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_USB && PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_UHCI) return (1); - + return (0); } @@ -183,7 +183,7 @@ uhci_pci_attach(struct device *parent, struct device *self, void *aux) "vendor 0x%04x", PCI_VENDOR(pa->pa_id)); config_defer(self, uhci_pci_attach_deferred); - + /* Ignore interrupts for now */ sc->sc.sc_bus.dying = 1; @@ -206,7 +206,7 @@ uhci_pci_attach_deferred(struct device *self) int s; s = splhardusb(); - + sc->sc.sc_bus.dying = 0; r = uhci_init(&sc->sc); if (r != USBD_NORMAL_COMPLETION) { diff --git a/sys/dev/pci/vga_pci.c b/sys/dev/pci/vga_pci.c index 1e55723a5..d5b7c8cab 100644 --- a/sys/dev/pci/vga_pci.c +++ b/sys/dev/pci/vga_pci.c @@ -126,7 +126,7 @@ static const struct vga_device_description vga_devs[] = { * * The next entry is a list of corresponding masks. * - * Finally the last value indicates if we should repost via + * Finally the last value indicates if we should repost via * vga_pci (i.e. the x86emulator) * bios. */ { /* All machines with GMA500/Poulsbo */ diff --git a/sys/dev/pci/vga_pcivar.h b/sys/dev/pci/vga_pcivar.h index fedf1cf1a..7c27516a9 100644 --- a/sys/dev/pci/vga_pcivar.h +++ b/sys/dev/pci/vga_pcivar.h @@ -6,17 +6,17 @@ * All rights reserved. * * Author: Chris G. Demetriou - * + * * Permission to use, copy, modify and distribute this software and * its documentation is hereby granted, provided that both the copyright * notice and this permission notice appear in all copies of the * software, derivative works or modified versions, and any portions * thereof, and that both notices appear in supporting documentation. - * - * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" - * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. - * + * * Carnegie Mellon requests users of this software to return to * * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU @@ -51,7 +51,7 @@ struct vga_pci_bar { int flags; void *vaddr; }; - + struct vga_pci_softc { struct device sc_dev; struct vga_config *sc_vc; diff --git a/sys/dev/pci/yds.c b/sys/dev/pci/yds.c index 666f3b465..063a0f56b 100644 --- a/sys/dev/pci/yds.c +++ b/sys/dev/pci/yds.c @@ -26,7 +26,7 @@ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* +/* * Yamaha YMF724[B-F]/740[B-C]/744/754 * * Documentation links: @@ -234,7 +234,7 @@ static const struct { YDS_CAP_MCODE_1E|YDS_CAP_LEGACY_SELECTABLE }, { PCI_PRODUCT_YAMAHA_YMF724F, YDS_CAP_MCODE_1E|YDS_CAP_LEGACY_SELECTABLE }, - { PCI_PRODUCT_YAMAHA_YMF744, + { PCI_PRODUCT_YAMAHA_YMF744, YDS_CAP_MCODE_1E|YDS_CAP_LEGACY_FLEXIBLE }, { PCI_PRODUCT_YAMAHA_YMF754, YDS_CAP_MCODE_1E|YDS_CAP_LEGACY_FLEXIBLE|YDS_CAP_HAS_P44 }, @@ -288,7 +288,7 @@ yds_dump_play_slot(struct yds_softc *sc, int bank) printf(" 0x%02x: 0x%08x\n", j * sizeof(u_int32_t), *p++); delay(1); - } + } */ } } @@ -572,7 +572,7 @@ yds_configure_legacy(struct yds_softc *sc) YDS_PCI_FM_BA, opl_addrs[i]); if (bus_space_map(sc->sc_opl_iot, opl_addrs[i], 4, 0, &sc->sc_opl_ioh) == 0) { - struct audio_attach_args aa; + struct audio_attach_args aa; aa.type = AUDIODEV_TYPE_OPL; aa.hwif = aa.hdl = NULL; @@ -585,7 +585,7 @@ yds_configure_legacy(struct yds_softc *sc) reg |= (i << (0+16)); break; } - } + } } if (dev == 0) { reg &= ~YDS_PCI_LEGACY_FMEN; @@ -608,7 +608,7 @@ yds_configure_legacy(struct yds_softc *sc) YDS_PCI_MPU_BA, mpu_addrs[i]); if (bus_space_map(sc->sc_mpu_iot, mpu_addrs[i], 2, 0, &sc->sc_mpu_ioh) == 0) { - struct audio_attach_args aa; + struct audio_attach_args aa; aa.type = AUDIODEV_TYPE_MPU; aa.hwif = aa.hdl = NULL; @@ -629,7 +629,7 @@ yds_configure_legacy(struct yds_softc *sc) YDS_PCI_LEGACY, reg); } sc->sc_mpu = dev; -} +} #undef FLEXIBLE #undef SELECTABLE @@ -759,7 +759,7 @@ yds_attachhook(struct device *self) ctl.dev = yds_get_portnum_by_name(sc, AudioCrecord, AudioNvolume, AudioNmute); yds_mixer_set_port(sc, &ctl); - + ctl.dev = yds_get_portnum_by_name(sc, AudioCrecord, AudioNsource, NULL); ctl.type = AUDIO_MIXER_ENUM; @@ -1002,7 +1002,7 @@ yds_allocmem(struct yds_softc *sc, size_t size, size_t align, struct yds_dma *p) if (error) return (error); - error = bus_dmamem_map(sc->sc_dmatag, p->segs, p->nsegs, p->size, + error = bus_dmamem_map(sc->sc_dmatag, p->segs, p->nsegs, p->size, &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); if (error) goto free; @@ -1012,7 +1012,7 @@ yds_allocmem(struct yds_softc *sc, size_t size, size_t align, struct yds_dma *p) if (error) goto unmap; - error = bus_dmamap_load(sc->sc_dmatag, p->map, p->addr, p->size, NULL, + error = bus_dmamap_load(sc->sc_dmatag, p->map, p->addr, p->size, NULL, BUS_DMA_NOWAIT); if (error) goto destroy; @@ -1075,7 +1075,7 @@ yds_set_params(void *addr, int setmode, int usemode, struct audio_params *p; int mode; - for (mode = AUMODE_RECORD; mode != -1; + for (mode = AUMODE_RECORD; mode != -1; mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) { if ((setmode & mode) == 0) continue; @@ -1330,7 +1330,7 @@ yds_trigger_input(void *addr, void *start, void *end, int blksize, sc->sc_rec.blksize = blksize; DPRINTFN(1, ("yds_trigger_input: " - "sc=%p start=%p end=%p blksize=%d intr=%p(%p)\n", + "sc=%p start=%p end=%p blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg)); DPRINTFN(1, (" parameters: rate=%lu, precision=%u, channels=%u\n", param->sample_rate, param->precision, param->channels)); diff --git a/sys/dev/pckbc/pckbd.c b/sys/dev/pckbc/pckbd.c index 50d523f39..1a3e3977f 100644 --- a/sys/dev/pckbc/pckbd.c +++ b/sys/dev/pckbc/pckbd.c @@ -127,10 +127,10 @@ void pckbdattach(struct device *, struct device *, void *); int pckbdactivate(struct device *, int); const struct cfattach pckbd_ca = { - sizeof(struct pckbd_softc), - pckbdprobe, - pckbdattach, - NULL, + sizeof(struct pckbd_softc), + pckbdprobe, + pckbdattach, + NULL, pckbdactivate }; @@ -571,7 +571,7 @@ const u_int8_t pckbd_xtbl2[] = { RAWKEY_w, RAWKEY_2, RAWKEY_Meta_L, -/* 0x20 */ +/* 0x20 */ 0, RAWKEY_c, RAWKEY_x, @@ -860,7 +860,7 @@ const u_int8_t pckbd_xtbl3[] = { RAWKEY_w, RAWKEY_2, RAWKEY_f4, -/* 0x20 */ +/* 0x20 */ 0, RAWKEY_c, RAWKEY_x, diff --git a/sys/dev/pcmcia/cfxga.c b/sys/dev/pcmcia/cfxga.c index 2237db1fb..b4d8fdc7b 100644 --- a/sys/dev/pcmcia/cfxga.c +++ b/sys/dev/pcmcia/cfxga.c @@ -140,7 +140,7 @@ struct cfxga_screen { struct rasops_info scr_ri; /* raster op glue */ struct wsdisplay_charcell *scr_mem; /* backing memory */ }; - + int cfxga_copycols(void *, int, int, int, int); int cfxga_copyrows(void *, int, int, int); int cfxga_do_cursor(struct rasops_info *); @@ -260,7 +260,7 @@ cfxga_remove_function(struct pcmcia_function *pf) pf->pf_flags |= PFF_FAKE; } -int +int cfxga_match(struct device *parent, void *match, void *aux) { struct pcmcia_attach_args *pa = aux; @@ -330,7 +330,7 @@ cfxga_activate(struct device *dev, int act) return (rv); } -void +void cfxga_attach(struct device *parent, struct device *self, void *aux) { struct cfxga_softc *sc = (void *)self; @@ -540,7 +540,7 @@ cfxga_alloc_screen(void *v, const struct wsscreen_descr *type, void **cookiep, *cookiep = ri; *curxp = *curyp = 0; - + return (0); } diff --git a/sys/dev/pcmcia/if_an_pcmcia.c b/sys/dev/pcmcia/if_an_pcmcia.c index 17dbb537c..c6146cbcf 100644 --- a/sys/dev/pcmcia/if_an_pcmcia.c +++ b/sys/dev/pcmcia/if_an_pcmcia.c @@ -65,7 +65,7 @@ struct an_pcmcia_softc { #define AN_PCMCIA_ATTACHED 3 }; -const struct cfattach an_pcmcia_ca = { +const struct cfattach an_pcmcia_ca = { sizeof(struct an_pcmcia_softc), an_pcmcia_match, an_pcmcia_attach, an_pcmcia_detach, an_pcmcia_activate }; diff --git a/sys/dev/pcmcia/if_malo.c b/sys/dev/pcmcia/if_malo.c index 76ec8dd53..0403f2409 100644 --- a/sys/dev/pcmcia/if_malo.c +++ b/sys/dev/pcmcia/if_malo.c @@ -268,7 +268,7 @@ malo_pcmcia_wakeup(struct malo_softc *sc) struct ieee80211com *ic = &sc->sc_ic; struct ifnet *ifp = &ic->ic_if; int s; - + s = splnet(); while (sc->sc_flags & MALO_BUSY) tsleep_nsec(&sc->sc_flags, 0, "malopwr", INFSLP); @@ -921,7 +921,7 @@ cmalo_rx(struct malo_softc *sc) psize - 1); data = (uint8_t *)sc->sc_data; data[psize - 1] = MALO_READ_1(sc, MALO_REG_DATA_READ); - } else + } else MALO_READ_MULTI_2(sc, MALO_REG_DATA_READ, sc->sc_data, psize); MALO_WRITE_1(sc, MALO_REG_HOST_STATUS, MALO_VAL_RX_DL_OVER); MALO_WRITE_2(sc, MALO_REG_CARD_INTR_CAUSE, MALO_VAL_RX_DL_OVER); @@ -1895,7 +1895,7 @@ cmalo_cmd_set_80211d(struct malo_softc *sc) psize += sizeof(*body_80211d); hdr->size = htole16(psize - sizeof(*hdr)); - + /* process command request */ if (cmalo_cmd_request(sc, psize, 0) != 0) return (EIO); diff --git a/sys/dev/pcmcia/if_malovar.h b/sys/dev/pcmcia/if_malovar.h index 19361e138..30a78c5f1 100644 --- a/sys/dev/pcmcia/if_malovar.h +++ b/sys/dev/pcmcia/if_malovar.h @@ -147,7 +147,7 @@ struct malo_cmd_body_channel { struct malo_cmd_body_txpower { uint16_t action; - int16_t txpower; + int16_t txpower; } __packed; struct malo_cmd_body_antenna { diff --git a/sys/dev/pcmcia/if_xe.c b/sys/dev/pcmcia/if_xe.c index afc2b2d30..6df8473fc 100644 --- a/sys/dev/pcmcia/if_xe.c +++ b/sys/dev/pcmcia/if_xe.c @@ -185,7 +185,7 @@ int xe_pcmcia_match(struct device *parent, void *match, void *aux) { struct pcmcia_attach_args *pa = aux; - + if (pa->pf->function != PCMCIA_FUNCTION_NETWORK) return (0); @@ -632,7 +632,7 @@ xe_intr(void *arg) esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + ESR); isr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + ISR0); rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + RSR); - + /* Check to see if card has been ejected. */ if (isr == 0xff) { printf("%s: interrupt for dead card\n", sc->sc_dev.dv_xname); @@ -672,7 +672,7 @@ xe_intr(void *arg) rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + RSR); } - + /* Packet too long? */ if (rsr & RSR_TOO_LONG) { ifp->if_ierrors++; @@ -700,7 +700,7 @@ xe_intr(void *arg) CLR_RX_OVERRUN); DPRINTF(XED_INTR, ("overrun cleared\n")); } - + /* Try to start more packets transmitting. */ if (ifq_empty(&ifp->if_snd) == 0) xe_start(ifp); @@ -713,7 +713,7 @@ xe_intr(void *arg) RESTART_TX); ifp->if_oerrors++; } - + if (tx_status & TX_ABORT) ifp->if_oerrors++; @@ -735,7 +735,7 @@ xe_get(struct xe_softc *sc) struct ifnet *ifp = &sc->sc_arpcom.ac_if; u_int16_t pktlen, len, recvcount = 0; u_int8_t *data; - + PAGE(sc, 0); rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + RSR); @@ -758,7 +758,7 @@ xe_get(struct xe_softc *sc) len = MHLEN; top = 0; mp = ⊤ - + while (pktlen > 0) { if (top) { MGET(m, M_DONTWAIT, MT_DATA); @@ -998,12 +998,12 @@ xe_stop(struct xe_softc *sc) PAGE(sc, 1); bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + IMR0, 0); - + /* Power down, wait. */ PAGE(sc, 4); bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + GP1, 0); DELAY(40000); - + /* Cancel watchdog timer. */ sc->sc_arpcom.ac_if.if_timer = 0; } @@ -1128,7 +1128,7 @@ xe_ioctl(struct ifnet *ifp, u_long command, caddr_t data) case SIOCSIFFLAGS: sc->sc_all_mcasts = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; - + PAGE(sc, 0x42); if ((ifp->if_flags & IFF_PROMISC) || (ifp->if_flags & IFF_ALLMULTI)) @@ -1361,7 +1361,7 @@ xe_full_reset(struct xe_softc *sc) DELAY(20000); } else { PAGE(sc, 0); - + /* XXX Do we need to do this? */ PAGE(sc, 0x42); bus_space_write_1(bst, bsh, offset + SWC1, SWC1_AUTO_MEDIA); diff --git a/sys/dev/pcmcia/pcmcia_cis.c b/sys/dev/pcmcia/pcmcia_cis.c index cfff07afe..ef6b82278 100644 --- a/sys/dev/pcmcia/pcmcia_cis.c +++ b/sys/dev/pcmcia/pcmcia_cis.c @@ -703,7 +703,7 @@ pcmcia_parse_cis_tuple(struct pcmcia_tuple *tuple, void *arg) case PCMCIA_CISTPL_END: /* * If we've seen a LONGLINK_MFC, and this is the first - * END after it, reset the function list. + * END after it, reset the function list. * * XXX This might also be the right place to start a * new function, but that assumes that a function diff --git a/sys/dev/pcmcia/pcmcia_cis_quirks.c b/sys/dev/pcmcia/pcmcia_cis_quirks.c index 38aa709bd..2df39eb0b 100644 --- a/sys/dev/pcmcia/pcmcia_cis_quirks.c +++ b/sys/dev/pcmcia/pcmcia_cis_quirks.c @@ -182,24 +182,24 @@ static struct pcmcia_cis_quirk pcmcia_cis_quirks[] = { PCMCIA_CIS_INVALID, &pcmcia_3cxem556_func1, &pcmcia_3cxem556_func1_cfe0 }, { PCMCIA_VENDOR_MEGAHERTZ2, PCMCIA_PRODUCT_MEGAHERTZ2_XJEM1144, - PCMCIA_CIS_INVALID, + PCMCIA_CIS_INVALID, &pcmcia_megahertz_xjem1144_func0, &pcmcia_megahertz_xjem1144_func0_cfe0 }, { PCMCIA_VENDOR_MEGAHERTZ2, PCMCIA_PRODUCT_MEGAHERTZ2_XJEM1144, - PCMCIA_CIS_INVALID, + PCMCIA_CIS_INVALID, &pcmcia_megahertz_xjem1144_func1, &pcmcia_megahertz_xjem1144_func1_cfe0 }, { PCMCIA_VENDOR_SIERRA, PCMCIA_PRODUCT_SIERRA_A550, - PCMCIA_CIS_INVALID, + PCMCIA_CIS_INVALID, &pcmcia_sierra_a555_func1, &pcmcia_sierra_a555_func1_cfe0 }, { PCMCIA_VENDOR_SIERRA, PCMCIA_PRODUCT_SIERRA_A555, - PCMCIA_CIS_INVALID, + PCMCIA_CIS_INVALID, &pcmcia_sierra_a555_func1, &pcmcia_sierra_a555_func1_cfe0 }, { PCMCIA_VENDOR_SIERRA, PCMCIA_PRODUCT_SIERRA_A710, - PCMCIA_CIS_INVALID, + PCMCIA_CIS_INVALID, &pcmcia_sierra_a555_func1, &pcmcia_sierra_a555_func1_cfe0 }, { PCMCIA_VENDOR_SIERRA, PCMCIA_PRODUCT_SIERRA_AC710, - PCMCIA_CIS_INVALID, + PCMCIA_CIS_INVALID, &pcmcia_sierra_a555_func1, &pcmcia_sierra_a555_func1_cfe0 }, { PCMCIA_VENDOR_INVALID, PCMCIA_PRODUCT_INVALID, PCMCIA_CIS_SVEC_LANCARD, @@ -217,7 +217,7 @@ pcmcia_check_cis_quirks(struct pcmcia_softc *sc) pf = NULL; pf_last = NULL; - + for (i = 0; i < nitems(pcmcia_cis_quirks); i++) { if ((sc->card.manufacturer == pcmcia_cis_quirks[i].manufacturer) && diff --git a/sys/dev/pcmcia/pcmciachip.h b/sys/dev/pcmcia/pcmciachip.h index ef1864a6b..f799f9412 100644 --- a/sys/dev/pcmcia/pcmciachip.h +++ b/sys/dev/pcmcia/pcmciachip.h @@ -92,7 +92,7 @@ struct pcmcia_chip_functions { void (*socket_disable)(pcmcia_chipset_handle_t); /* card detection */ - int (*card_detect)(pcmcia_chipset_handle_t); + int (*card_detect)(pcmcia_chipset_handle_t); }; /* Memory space functions. */ diff --git a/sys/dev/pcmcia/pcmciadevs b/sys/dev/pcmcia/pcmciadevs index 9c0da3273..f040a2fc8 100644 --- a/sys/dev/pcmcia/pcmciadevs +++ b/sys/dev/pcmcia/pcmciadevs @@ -145,7 +145,7 @@ product AIRONET PC4800 0x0007 Aironet PC4800 product AIRONET 350 0x000a Aironet 350 /* AirVast */ -product AIRVAST WN_100 0x7300 AirVast WN-100 +product AIRVAST WN_100 0x7300 AirVast WN-100 /* Allied Telesis K.K. */ product ALLIEDTELESIS LA_PCM 0x0002 Allied Telesis LA-PCM @@ -333,7 +333,7 @@ product PANASONIC KME 0x2604 Panasonic CD-R/RW Interface /* Proxim */ product PROXIM ROAMABOUT_2400FH 0x1058 Digital RoamAbout 2400FH product PROXIM RANGELAN2_7401 0x1158 Proxim RangeLAN2 7401 -product PROXIM RANGELANDS_8430 0x8000 Proxim RangeLAN-DS 8430 +product PROXIM RANGELANDS_8430 0x8000 Proxim RangeLAN-DS 8430 product PROXIM HARMONY_80211B 0x0002 Proxim Harmony 802.11B /* Ericsson */ @@ -495,7 +495,7 @@ product AMD AM79C930 { "AMD", "Am79C930", NULL, NULL } product ICOM SL200 { "Icom", "SL-200", NULL, NULL } product XIRCOM CFE_10 { "Xircom", "CompactCard&spEthernet", "CFE-10", "1.00" } product BILLIONTON LNT10TN { "PCMCIA", "LNT-10TN", NULL, NULL } -product NDC ND5100_E { "NDC", "Ethernet", "A", NULL } +product NDC ND5100_E { "NDC", "Ethernet", "A", NULL } product PROXIM RL2_7200 { "PROXIM", "LAN&spCARD", "RANGELAN2", NULL } product PROXIM RL2_7400 { "PROXIM", "LAN&spPC&spCARD", "RANGELAN2", NULL } product PROXIM SYMPHONY { "PROXIM", "LAN&spPC&spCARD", "SYMPHONY", NULL } diff --git a/sys/dev/pcmcia/wdc_pcmcia.c b/sys/dev/pcmcia/wdc_pcmcia.c index d66fddd93..fe728c9bd 100644 --- a/sys/dev/pcmcia/wdc_pcmcia.c +++ b/sys/dev/pcmcia/wdc_pcmcia.c @@ -296,7 +296,7 @@ wdc_pcmcia_attach(struct device *parent, struct device *self, void *aux) sc->sc_pioh.size, &sc->sc_pioh, &sc->sc_iowindow)) { printf(": can't map first i/o space\n"); goto iomap_failed; - } + } /* * Currently, # of iospace is 1 except DIGITAL Mobile Media CD-ROM. @@ -385,8 +385,8 @@ wdc_pcmcia_detach(struct device *self, int flags) if (sc->sc_iowindow == -1) /* Nothing to detach */ return (0); - - if ((error = wdcdetach(&sc->wdc_channel, flags)) != 0) + + if ((error = wdcdetach(&sc->wdc_channel, flags)) != 0) return (error); if (sc->wdc_channel.ch_queue != NULL) @@ -423,7 +423,7 @@ wdc_pcmcia_activate(struct device *self, int act) break; case DVACT_RESUME: pcmcia_function_enable(sc->sc_pf); - sc->sc_ih = pcmcia_intr_establish(sc->sc_pf, IPL_BIO, + sc->sc_ih = pcmcia_intr_establish(sc->sc_pf, IPL_BIO, wdcintr, &sc->wdc_channel, sc->sc_wdcdev.sc_dev.dv_xname); wdcreset(&sc->wdc_channel, VERBOSE); rv = config_activate_children(self, act); diff --git a/sys/dev/puc/lpt_puc.c b/sys/dev/puc/lpt_puc.c index d30f9ae94..6698c4341 100644 --- a/sys/dev/puc/lpt_puc.c +++ b/sys/dev/puc/lpt_puc.c @@ -32,7 +32,7 @@ */ /* - * Machine-independent parallel port ('lpt') driver attachment to "PCI + * Machine-independent parallel port ('lpt') driver attachment to "PCI * Universal Communications" controller driver. * * Author: Christopher G. Demetriou, May 17, 1998. diff --git a/sys/dev/sbus/agten.c b/sys/dev/sbus/agten.c index 5fa76a2fa..93d328ded 100644 --- a/sys/dev/sbus/agten.c +++ b/sys/dev/sbus/agten.c @@ -209,7 +209,7 @@ agtenattach(struct device *parent, struct device *self, void *args) sc->sc_sunfb.sf_depth); sc->sc_sunfb.sf_ro.ri_bits = (void *)sc->sc_i128_fb; - + sc->sc_sunfb.sf_ro.ri_hw = sc; fbwscons_init(&sc->sc_sunfb, 0, isconsole); fbwscons_setcolormap(&sc->sc_sunfb, agten_setcolor); diff --git a/sys/dev/sbus/bwtwo.c b/sys/dev/sbus/bwtwo.c index 30d346bc3..157c0fa8f 100644 --- a/sys/dev/sbus/bwtwo.c +++ b/sys/dev/sbus/bwtwo.c @@ -134,7 +134,7 @@ bwtwomatch(struct device *parent, void *vcf, void *aux) return (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0); } -void +void bwtwoattach(struct device *parent, struct device *self, void *aux) { struct bwtwo_softc *sc = (struct bwtwo_softc *)self; @@ -186,7 +186,7 @@ bwtwoattach(struct device *parent, struct device *self, void *aux) sc->sc_vid_regs); sc->sc_sunfb.sf_ro.ri_hw = sc; fbwscons_init(&sc->sc_sunfb, 0, console); - + if (console) fbwscons_console_init(&sc->sc_sunfb, -1); diff --git a/sys/dev/sbus/cgsix.c b/sys/dev/sbus/cgsix.c index 9b4e8e669..1e2042bc5 100644 --- a/sys/dev/sbus/cgsix.c +++ b/sys/dev/sbus/cgsix.c @@ -99,7 +99,7 @@ cgsixmatch(struct device *parent, void *vcf, void *aux) return (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0); } -void +void cgsixattach(struct device *parent, struct device *self, void *aux) { struct cgsix_softc *sc = (struct cgsix_softc *)self; diff --git a/sys/dev/sbus/cgthree.c b/sys/dev/sbus/cgthree.c index 612720a5c..f2d53b765 100644 --- a/sys/dev/sbus/cgthree.c +++ b/sys/dev/sbus/cgthree.c @@ -192,7 +192,7 @@ cgthreematch(struct device *parent, void *vcf, void *aux) return (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0); } -void +void cgthreeattach(struct device *parent, struct device *self, void *aux) { struct cgthree_softc *sc = (struct cgthree_softc *)self; diff --git a/sys/dev/sbus/cgtwelve.c b/sys/dev/sbus/cgtwelve.c index a09a46aa7..9b3831d15 100644 --- a/sys/dev/sbus/cgtwelve.c +++ b/sys/dev/sbus/cgtwelve.c @@ -445,7 +445,7 @@ cgtwelve_mmap(void *v, off_t offset, int prot) * Simple Bt462 programming routines. */ -static __inline__ void +static __inline__ void cgtwelve_ramdac_wraddr(struct cgtwelve_softc *sc, u_int32_t addr) { sc->sc_ramdac->addr_lo = (addr & 0xff); diff --git a/sys/dev/sbus/cgtwelvereg.h b/sys/dev/sbus/cgtwelvereg.h index d6d95ab87..fc6cdf190 100644 --- a/sys/dev/sbus/cgtwelvereg.h +++ b/sys/dev/sbus/cgtwelvereg.h @@ -140,7 +140,7 @@ struct cgtwelve_dpu { }; /* APU */ -struct cgtwelve_apu { +struct cgtwelve_apu { u_int32_t imsg0; u_int32_t msg0; u_int32_t imsg1; diff --git a/sys/dev/sbus/cs4231.c b/sys/dev/sbus/cs4231.c index a9b0c3d68..60dc532ab 100644 --- a/sys/dev/sbus/cs4231.c +++ b/sys/dev/sbus/cs4231.c @@ -183,7 +183,7 @@ cs4231_match(struct device *parent, void *vcf, void *aux) return (strcmp("SUNW,CS4231", sa->sa_name) == 0); } -void +void cs4231_attach(struct device *parent, struct device *self, void *aux) { struct sbus_attach_args *sa = aux; diff --git a/sys/dev/sbus/dma_sbus.c b/sys/dev/sbus/dma_sbus.c index 5bd1fbcad..b8035d603 100644 --- a/sys/dev/sbus/dma_sbus.c +++ b/sys/dev/sbus/dma_sbus.c @@ -154,7 +154,7 @@ dmaattach_sbus(struct device *parent, struct device *self, void *aux) /* Map registers */ if (sa->sa_npromvaddrs != 0) { - if (sbus_bus_map(sa->sa_bustag, 0, + if (sbus_bus_map(sa->sa_bustag, 0, sa->sa_promvaddrs[0], sa->sa_size, /* ???? */ BUS_SPACE_MAP_PROMADDRESS, diff --git a/sys/dev/sbus/esp_sbus.c b/sys/dev/sbus/esp_sbus.c index 790493ea4..fb2f6e0ef 100644 --- a/sys/dev/sbus/esp_sbus.c +++ b/sys/dev/sbus/esp_sbus.c @@ -468,8 +468,8 @@ espattach(struct esp_softc *esc, struct ncr53c9x_glue *gluep) /* * Alas, we must now modify the value a bit, because it's - * only valid when can switch on FASTCLK and FASTSCSI bits - * in config register 3... + * only valid when can switch on FASTCLK and FASTSCSI bits + * in config register 3... */ switch (sc->sc_rev) { case NCR_VARIANT_ESP100: @@ -511,7 +511,7 @@ int esp_sbus_debug = 0; static struct { char *r_name; - int r_flag; + int r_flag; } esp__read_regnames [] = { { "TCL", 0}, /* 0/00 */ { "TCM", 0}, /* 1/04 */ @@ -678,7 +678,7 @@ db_esp(db_expr_t addr, int have_addr, db_expr_t count, char *modif) if (!sc) continue; db_printf("esp%d: nexus %p phase %x prev %x dp %p dleft %lx ify %x\n", - u, sc->sc_nexus, sc->sc_phase, sc->sc_prevphase, + u, sc->sc_nexus, sc->sc_phase, sc->sc_prevphase, sc->sc_dp, sc->sc_dleft, sc->sc_msgify); db_printf("\tmsgout %x msgpriq %x msgin %x:%x:%x:%x:%x\n", sc->sc_msgout, sc->sc_msgpriq, sc->sc_imess[0], @@ -693,7 +693,7 @@ db_esp(db_expr_t addr, int have_addr, db_expr_t count, char *modif) } } db_printf("\n"); - + for (t=0; tsc_tinfo[t].luns, link) { db_printf("t%d lun %d untagged %p busy %d used %x\n", diff --git a/sys/dev/sbus/spif.c b/sys/dev/sbus/spif.c index 76d5adca3..0c7fe596b 100644 --- a/sys/dev/sbus/spif.c +++ b/sys/dev/sbus/spif.c @@ -156,7 +156,7 @@ spifmatch(struct device *parent, void *vcf, void *aux) return (1); } -void +void spifattach(struct device *parent, struct device *self, void *aux) { struct spif_softc *sc = (struct spif_softc *)self; diff --git a/sys/dev/sbus/spifreg.h b/sys/dev/sbus/spifreg.h index 290dbb637..ab03e3076 100644 --- a/sys/dev/sbus/spifreg.h +++ b/sys/dev/sbus/spifreg.h @@ -62,7 +62,7 @@ /* * The 'stc' is a Cirrus Logic CL-CD180 (either revision B or revision C) */ -#define STC_CCR 0x01 /* channel command */ +#define STC_CCR 0x01 /* channel command */ #define STC_SRER 0x02 /* service request enable */ #define STC_COR1 0x03 /* channel option 1 */ #define STC_COR2 0x04 /* channel option 2 */ diff --git a/sys/dev/sbus/stp4020.c b/sys/dev/sbus/stp4020.c index 744e4313b..5dc25a6de 100644 --- a/sys/dev/sbus/stp4020.c +++ b/sys/dev/sbus/stp4020.c @@ -705,7 +705,7 @@ stp4020_chip_socket_enable(pcmcia_chipset_handle_t pch) /* * hold RESET at least 20us. */ - stp4020_wr_sockctl(h, STP4020_ICR0_IDX, + stp4020_wr_sockctl(h, STP4020_ICR0_IDX, stp4020_rd_sockctl(h, STP4020_ICR0_IDX) | STP4020_ICR0_RESET); delay(20); stp4020_wr_sockctl(h, STP4020_ICR0_IDX, diff --git a/sys/dev/sbus/vigra.c b/sys/dev/sbus/vigra.c index 90a8394ce..f115655ac 100644 --- a/sys/dev/sbus/vigra.c +++ b/sys/dev/sbus/vigra.c @@ -491,7 +491,7 @@ vigra_loadcmap_immediate(struct vigra_softc *sc, int start, int ncolors) { u_int32_t *colp = &sc->sc_cmap.cm_chip[start]; volatile u_int32_t *lutp; - + if (sc->sc_g300) lutp = &(sc->sc_ramdac->g300.cmap[start]); else diff --git a/sys/dev/sbus/xbox.c b/sys/dev/sbus/xbox.c index 157ab425d..68e1e2b56 100644 --- a/sys/dev/sbus/xbox.c +++ b/sys/dev/sbus/xbox.c @@ -71,7 +71,7 @@ xboxmatch(struct device *parent, void *cf, void *aux) return (1); } -void +void xboxattach(struct device *parent, struct device *self, void *aux) { struct xbox_softc *sc = (struct xbox_softc *)self; diff --git a/sys/dev/sbus/zx.c b/sys/dev/sbus/zx.c index a4969b77d..dfa0cd10c 100644 --- a/sys/dev/sbus/zx.c +++ b/sys/dev/sbus/zx.c @@ -173,7 +173,7 @@ int zx_match(struct device *parent, void *vcf, void *aux) { struct sbus_attach_args *sa = aux; - + if (strcmp(sa->sa_name, "SUNW,leo") == 0) return (1); diff --git a/sys/dev/sbus/zxreg.h b/sys/dev/sbus/zxreg.h index e76f9ca08..f85b6493c 100644 --- a/sys/dev/sbus/zxreg.h +++ b/sys/dev/sbus/zxreg.h @@ -51,7 +51,7 @@ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ - + #ifndef _DEV_SBUS_ZXREG_H_ #define _DEV_SBUS_ZXREG_H_ diff --git a/sys/dev/sdmmc/sdhc.c b/sys/dev/sdmmc/sdhc.c index 2f3a6f4bc..dd6e634a3 100644 --- a/sys/dev/sdmmc/sdhc.c +++ b/sys/dev/sdmmc/sdhc.c @@ -426,7 +426,7 @@ sdhc_host_found(struct sdhc_softc *sc, bus_space_tag_t iot, error = 0; goto err; } - + return 0; err: @@ -516,7 +516,7 @@ sdhc_host_reset(sdmmc_chipset_handle_t sch) if ((error = sdhc_soft_reset(hp, SDHC_RESET_ALL)) != 0) { splx(s); return (error); - } + } /* Set data timeout counter value to max for now. */ HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX); @@ -919,7 +919,7 @@ sdhc_start_command(struct sdhc_host *hp, struct sdmmc_command *cmd) int error; int seg; int s; - + DPRINTF(1,("%s: start cmd %u arg=%#x data=%p dlen=%d flags=%#x\n", DEVNAME(hp->sc), cmd->c_opcode, cmd->c_arg, cmd->c_data, cmd->c_datalen, cmd->c_flags)); @@ -1274,7 +1274,7 @@ sdhc_wait_intr(struct sdhc_host *hp, int mask, int secs) DPRINTF(2,("%s: intr status %#x error %#x\n", DEVNAME(hp->sc), status, hp->intr_error_status)); - + /* Command timeout has higher priority than command complete. */ if (ISSET(status, SDHC_ERROR_INTERRUPT)) { hp->intr_error_status = 0; diff --git a/sys/dev/sdmmc/sdmmc_io.c b/sys/dev/sdmmc/sdmmc_io.c index cf5c4aaa0..d8753b0da 100644 --- a/sys/dev/sdmmc/sdmmc_io.c +++ b/sys/dev/sdmmc/sdmmc_io.c @@ -490,7 +490,7 @@ sdmmc_io_read_1(struct sdmmc_function *sf, int reg) u_int8_t data = 0; rw_assert_wrlock(&sf->sc->sc_lock); - + (void)sdmmc_io_rw_direct(sf->sc, sf, reg, (u_char *)&data, SD_ARG_CMD52_READ); return data; @@ -509,7 +509,7 @@ u_int16_t sdmmc_io_read_2(struct sdmmc_function *sf, int reg) { u_int16_t data = 0; - + rw_assert_wrlock(&sf->sc->sc_lock); (void)sdmmc_io_rw_extended_subr(sf->sc, sf, NULL, reg, @@ -530,7 +530,7 @@ u_int32_t sdmmc_io_read_4(struct sdmmc_function *sf, int reg) { u_int32_t data = 0; - + rw_assert_wrlock(&sf->sc->sc_lock); (void)sdmmc_io_rw_extended_subr(sf->sc, sf, NULL, reg, diff --git a/sys/dev/sdmmc/sdmmcreg.h b/sys/dev/sdmmc/sdmmcreg.h index 245dbe849..965c88c1c 100644 --- a/sys/dev/sdmmc/sdmmcreg.h +++ b/sys/dev/sdmmc/sdmmcreg.h @@ -217,7 +217,7 @@ #define SD_CSD_CAPACITY(resp) ((SD_CSD_C_SIZE((resp))+1) << \ (SD_CSD_C_SIZE_MULT((resp))+2)) #define SD_CSD_V2_C_SIZE(resp) MMC_RSP_BITS((resp), 48, 22) -#define SD_CSD_V2_CAPACITY(resp) ((SD_CSD_V2_C_SIZE((resp))+1) << 10) +#define SD_CSD_V2_CAPACITY(resp) ((SD_CSD_V2_C_SIZE((resp))+1) << 10) #define SD_CSD_V2_BL_LEN 0x9 /* 512 */ #define SD_CSD_VDD_R_CURR_MIN(resp) MMC_RSP_BITS((resp), 59, 3) #define SD_CSD_VDD_R_CURR_MAX(resp) MMC_RSP_BITS((resp), 56, 3) diff --git a/sys/dev/sun/sunkbdmap.c b/sys/dev/sun/sunkbdmap.c index c084bdde1..1ff05b709 100644 --- a/sys/dev/sun/sunkbdmap.c +++ b/sys/dev/sun/sunkbdmap.c @@ -379,7 +379,7 @@ const keysym_t sunkbd5_keydesc_fr[] = { /* 004 Danish type 4 keyboard */ const keysym_t sunkbd_keydesc_dk[] = { KC(0x0d), KS_Multi_key, - KC(0x0f), KS_asciitilde, KS_asciicircum, + KC(0x0f), KS_asciitilde, KS_asciicircum, KC(0x1f), KS_2, KS_quotedbl, KS_at, KC(0x20), KS_3, KS_numbersign, KS_sterling, KC(0x21), KS_4, KS_currency, KS_dollar, @@ -775,7 +775,7 @@ const keysym_t sunkbd5_keydesc_es[] = { /* 00b Swedish/Finnish type 4 keyboard */ const keysym_t sunkbd_keydesc_sv[] = { KC(0x0d), KS_Multi_key, - KC(0x0f), KS_asciitilde, KS_asciicircum, + KC(0x0f), KS_asciitilde, KS_asciicircum, KC(0x1f), KS_2, KS_quotedbl, KS_at, KC(0x20), KS_3, KS_numbersign, KS_sterling, KC(0x21), KS_4, KS_currency, KS_dollar, @@ -809,7 +809,7 @@ const keysym_t sunkbd_keydesc_sv_nodead[] = { /* 02b Swedish type 5 keyboard */ const keysym_t sunkbd5_keydesc_sv[] = { KC(0x0d), KS_Mode_switch, - KC(0x0f), KS_asciitilde, KS_asciicircum, + KC(0x0f), KS_asciitilde, KS_asciicircum, KC(0x1f), KS_2, KS_quotedbl, KS_at, KC(0x20), KS_3, KS_numbersign, KS_sterling, KC(0x21), KS_4, KS_currency, KS_dollar, diff --git a/sys/dev/sun/z8530ms.c b/sys/dev/sun/z8530ms.c index 21097e47b..962f5d06e 100644 --- a/sys/dev/sun/z8530ms.c +++ b/sys/dev/sun/z8530ms.c @@ -367,7 +367,7 @@ zsms_stint(struct zs_chanstate *cs, int force) if (ISSET(delta, cs->cs_rr0_mask)) { SET(cs->cs_rr0_delta, delta); - + sc->sc_intr_flags |= INTR_ST_CHECK; cs->cs_softreq = 1; } diff --git a/sys/dev/tc/asc_tc.c b/sys/dev/tc/asc_tc.c index 82319f0e5..160d1850f 100644 --- a/sys/dev/tc/asc_tc.c +++ b/sys/dev/tc/asc_tc.c @@ -105,7 +105,7 @@ asc_tc_match(parent, cfdata, aux) void *cfdata, *aux; { struct tc_attach_args *d = aux; - + if (strncmp("PMAZ-AA ", d->ta_modname, TC_ROM_LLEN)) return (0); @@ -118,7 +118,7 @@ asc_tc_attach(parent, self, aux) void *aux; { struct tc_attach_args *ta = aux; - struct asc_tc_softc *asc = (struct asc_tc_softc *)self; + struct asc_tc_softc *asc = (struct asc_tc_softc *)self; struct ncr53c9x_softc *sc = &asc->asc.sc_ncr53c9x; /* @@ -136,7 +136,7 @@ asc_tc_attach(parent, self, aux) tc_intr_establish(parent, ta->ta_cookie, IPL_BIO, ncr53c9x_intr, sc, self->dv_xname); - + sc->sc_id = 7; sc->sc_freq = TC_SPEED_TO_KHZ(ta->ta_busspeed); /* in kHz so far */ diff --git a/sys/dev/tc/if_le_ioasic.c b/sys/dev/tc/if_le_ioasic.c index d0915ba1b..d04c9bd6b 100644 --- a/sys/dev/tc/if_le_ioasic.c +++ b/sys/dev/tc/if_le_ioasic.c @@ -219,13 +219,13 @@ le_ioasic_copytobuf_gap2(struct lance_softc *sc, void *fromv, { volatile caddr_t buf = sc->sc_mem; caddr_t from = fromv; - volatile u_int16_t *bptr; + volatile u_int16_t *bptr; if (boff & 0x1) { /* handle unaligned first byte */ bptr = ((volatile u_int16_t *)buf) + (boff - 1); *bptr = (*from++ << 8) | (*bptr & 0xff); - bptr += 2; + bptr += 2; len--; } else bptr = ((volatile u_int16_t *)buf) + boff; @@ -341,7 +341,7 @@ le_ioasic_copytobuf_gap16(struct lance_softc *sc, void *fromv, } while (len >= 16); break; - default: + default: /* Does odd-aligned case ever happen? */ do { bcopy(from, bptr, 16); diff --git a/sys/dev/tc/if_le_tc.c b/sys/dev/tc/if_le_tc.c index f68b19c81..007721e67 100644 --- a/sys/dev/tc/if_le_tc.c +++ b/sys/dev/tc/if_le_tc.c @@ -87,7 +87,7 @@ le_tc_attach(struct device *parent, struct device *self, void *aux) * baseboard implementation of a TC option card. */ lesc->sc_r1 = (struct lereg1 *) - TC_DENSE_TO_SPARSE(TC_PHYS_TO_UNCACHED(d->ta_addr + LE_OFFSET_LANCE)); + TC_DENSE_TO_SPARSE(TC_PHYS_TO_UNCACHED(d->ta_addr + LE_OFFSET_LANCE)); sc->sc_mem = (void *)(d->ta_addr + LE_OFFSET_RAM); sc->sc_copytodesc = lance_copytobuf_contig; diff --git a/sys/dev/tc/ioasic_subr.c b/sys/dev/tc/ioasic_subr.c index bb3a4364d..4c4ecef4d 100644 --- a/sys/dev/tc/ioasic_subr.c +++ b/sys/dev/tc/ioasic_subr.c @@ -6,17 +6,17 @@ * All rights reserved. * * Author: Keith Bostic, Chris G. Demetriou - * + * * Permission to use, copy, modify and distribute this software and * its documentation is hereby granted, provided that both the copyright * notice and this permission notice appear in all copies of the * software, derivative works or modified versions, and any portions * thereof, and that both notices appear in supporting documentation. - * - * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" - * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. - * + * * Carnegie Mellon requests users of this software to return to * * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU diff --git a/sys/dev/tc/ioasicreg.h b/sys/dev/tc/ioasicreg.h index d71b08605..35f7b1105 100644 --- a/sys/dev/tc/ioasicreg.h +++ b/sys/dev/tc/ioasicreg.h @@ -1,20 +1,20 @@ /* $OpenBSD: ioasicreg.h,v 1.3 2017/10/13 08:58:42 mpi Exp $ */ /* $NetBSD: ioasicreg.h,v 1.6 2000/07/17 02:18:17 thorpej Exp $ */ -/* +/* * Copyright (c) 1991,1990,1989,1994,1995 Carnegie Mellon University * All Rights Reserved. - * + * * Permission to use, copy, modify and distribute this software and * its documentation is hereby granted, provided that both the copyright * notice and this permission notice appear in all copies of the * software, derivative works or modified versions, and any portions * thereof, and that both notices appear in supporting documentation. - * - * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" - * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. - * + * * Carnegie Mellon requests users of this software to return to * * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU diff --git a/sys/dev/tc/tcds.c b/sys/dev/tc/tcds.c index 6409b95f1..9f842e851 100644 --- a/sys/dev/tc/tcds.c +++ b/sys/dev/tc/tcds.c @@ -36,17 +36,17 @@ * All rights reserved. * * Author: Keith Bostic, Chris G. Demetriou - * + * * Permission to use, copy, modify and distribute this software and * its documentation is hereby granted, provided that both the copyright * notice and this permission notice appear in all copies of the * software, derivative works or modified versions, and any portions * thereof, and that both notices appear in supporting documentation. - * - * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" - * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. - * + * * Carnegie Mellon requests users of this software to return to * * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU @@ -431,7 +431,7 @@ tcds_dma_enable(sc, on) cir = bus_space_read_4(sc->sc_bst, sc->sc_bsh, TCDS_CIR); /* XXX Clear/set IOSLOT/PBS bits. */ - if (on) + if (on) TCDS_CIR_SET(cir, sc->sc_dmabits); else TCDS_CIR_CLR(cir, sc->sc_dmabits); @@ -496,7 +496,7 @@ tcds_intr(arg) #undef CHECKINTR #ifdef DIAGNOSTIC - /* + /* * Interrupts not currently handled, but would like to know if they * occur. * diff --git a/sys/dev/tc/tcdsreg.h b/sys/dev/tc/tcdsreg.h index 6fc404079..b4d4e095d 100644 --- a/sys/dev/tc/tcdsreg.h +++ b/sys/dev/tc/tcdsreg.h @@ -6,17 +6,17 @@ * All rights reserved. * * Authors: Keith Bostic, Chris G. Demetriou - * + * * Permission to use, copy, modify and distribute this software and * its documentation is hereby granted, provided that both the copyright * notice and this permission notice appear in all copies of the * software, derivative works or modified versions, and any portions * thereof, and that both notices appear in supporting documentation. - * - * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" - * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. - * + * * Carnegie Mellon requests users of this software to return to * * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU @@ -136,7 +136,7 @@ void tcds_scsi_reset(int); /* * XXX * Start of MACH #defines, minimal changes to port to NetBSD. - * + * * The following register is the SCSI control interrupt register. It * starts, stops and resets scsi DMA. It takes over the SCSI functions * that were handled by the ASIC on the 3min. diff --git a/sys/dev/tc/tcdsvar.h b/sys/dev/tc/tcdsvar.h index 9aedc146f..25fb89779 100644 --- a/sys/dev/tc/tcdsvar.h +++ b/sys/dev/tc/tcdsvar.h @@ -6,17 +6,17 @@ * All rights reserved. * * Author: Chris G. Demetriou - * + * * Permission to use, copy, modify and distribute this software and * its documentation is hereby granted, provided that both the copyright * notice and this permission notice appear in all copies of the * software, derivative works or modified versions, and any portions * thereof, and that both notices appear in supporting documentation. - * - * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" - * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. - * + * * Carnegie Mellon requests users of this software to return to * * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU diff --git a/sys/dev/tc/tcreg.h b/sys/dev/tc/tcreg.h index 115c74995..97272ba79 100644 --- a/sys/dev/tc/tcreg.h +++ b/sys/dev/tc/tcreg.h @@ -6,17 +6,17 @@ * All rights reserved. * * Author: Chris G. Demetriou - * + * * Permission to use, copy, modify and distribute this software and * its documentation is hereby granted, provided that both the copyright * notice and this permission notice appear in all copies of the * software, derivative works or modified versions, and any portions * thereof, and that both notices appear in supporting documentation. - * - * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" - * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. - * + * * Carnegie Mellon requests users of this software to return to * * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU diff --git a/sys/dev/tc/tcvar.h b/sys/dev/tc/tcvar.h index 6fa495db1..122739079 100644 --- a/sys/dev/tc/tcvar.h +++ b/sys/dev/tc/tcvar.h @@ -6,17 +6,17 @@ * All rights reserved. * * Author: Chris G. Demetriou - * + * * Permission to use, copy, modify and distribute this software and * its documentation is hereby granted, provided that both the copyright * notice and this permission notice appear in all copies of the * software, derivative works or modified versions, and any portions * thereof, and that both notices appear in supporting documentation. - * - * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" - * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. - * + * * Carnegie Mellon requests users of this software to return to * * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU @@ -69,7 +69,7 @@ struct tcbus_attach_args { struct tc_slotdesc *tba_slots; u_int tba_nbuiltins; const struct tc_builtin *tba_builtins; - + /* TC bus resource management; XXX will move elsewhere eventually. */ void (*tba_intr_establish)(struct device *, void *, diff --git a/sys/dev/usb/dwc2/dwc2.c b/sys/dev/usb/dwc2/dwc2.c index d1b65d4f2..3887b7652 100644 --- a/sys/dev/usb/dwc2/dwc2.c +++ b/sys/dev/usb/dwc2/dwc2.c @@ -468,7 +468,7 @@ dwc2_abort_xfer(struct usbd_xfer *xfer, usbd_status status) return; } - /* Prevent any timeout to kick in. */ + /* Prevent any timeout to kick in. */ timeout_del(&xfer->timeout_handle); usb_rem_task(xfer->device, &xfer->abort_task); diff --git a/sys/dev/usb/dwc2/dwc2_hcdqueue.c b/sys/dev/usb/dwc2/dwc2_hcdqueue.c index aa08330b1..e9b94df45 100644 --- a/sys/dev/usb/dwc2/dwc2_hcdqueue.c +++ b/sys/dev/usb/dwc2/dwc2_hcdqueue.c @@ -2132,7 +2132,7 @@ dwc2_usb_calc_bus_time(int speed, int is_input, int isoc, int bytecount) tmp; } case USB_SPEED_FULL: /* ISOC or INTR */ - if (isoc) { + if (isoc) { tmp = (8354L * (31L + 10L * BitTime (bytecount))) / 1000L; return ((is_input) ? 7268L : 6265L) + BW_HOST_DELAY + diff --git a/sys/dev/usb/if_mos.c b/sys/dev/usb/if_mos.c index f7cf57fe3..7a0faa99f 100644 --- a/sys/dev/usb/if_mos.c +++ b/sys/dev/usb/if_mos.c @@ -65,8 +65,8 @@ */ /* - * Moschip MCS7730/MCS7830/MCS7832 USB to Ethernet controller - * The datasheet is available at the following URL: + * Moschip MCS7730/MCS7830/MCS7832 USB to Ethernet controller + * The datasheet is available at the following URL: * http://www.moschip.com/data/products/MCS7830/Data%20Sheet_7830.pdf */ @@ -546,7 +546,7 @@ mos_iff(struct mos_softc *sc) } } - /* + /* * The datasheet claims broadcast frames were always accepted * regardless of filter settings. But the hardware seems to * filter broadcast frames, so pass them explicitly. @@ -920,7 +920,7 @@ mos_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) rxstat = buf[pktlen] & MOS_RXSTS_MASK; if (rxstat != MOS_RXSTS_VALID) { - DPRINTF(("%s: erroneous frame received: ", + DPRINTF(("%s: erroneous frame received: ", sc->mos_dev.dv_xname)); if (rxstat & MOS_RXSTS_SHORT_FRAME) DPRINTF(("frame size less than 64 bytes\n")); diff --git a/sys/dev/usb/if_mosreg.h b/sys/dev/usb/if_mosreg.h index 2f5786b0e..bf7f0253b 100644 --- a/sys/dev/usb/if_mosreg.h +++ b/sys/dev/usb/if_mosreg.h @@ -84,8 +84,8 @@ #define MOS_CTL_ALLMULTI 0x02 #define MOS_CTL_SLEEP 0x04 #define MOS_CTL_TX_ENB 0x08 -/* - * The documentation calls this bit 'reserved', but in the FreeBSD driver +/* + * The documentation calls this bit 'reserved', but in the FreeBSD driver * provided by the vendor, this enables the receiver. */ #define MOS_CTL_RX_ENB 0x10 diff --git a/sys/dev/usb/if_mtw.c b/sys/dev/usb/if_mtw.c index 847842396..2a6d1e9f5 100644 --- a/sys/dev/usb/if_mtw.c +++ b/sys/dev/usb/if_mtw.c @@ -387,7 +387,7 @@ mtw_attachhook(struct device *self) sc->mac_ver = tmp >> 16; sc->mac_rev = tmp & 0xffff; - + /* retrieve RF rev. no and various other things from EEPROM */ mtw_read_eeprom(sc); @@ -570,7 +570,7 @@ mtw_alloc_mcu_ring(struct mtw_softc *sc) struct mtw_tx_ring *ring = &sc->sc_mcu; struct mtw_tx_data *data = &ring->data[0]; int error = 0; - + ring->cur = ring->queued = 0; data->sc = sc; /* backpointer for callbacks */ @@ -1164,7 +1164,7 @@ int mtw_mcu_calibrate(struct mtw_softc *sc, int func, uint32_t val) { struct mtw_mcu_cmd_8 cmd; - + cmd.func = htole32(func); cmd.val = htole32(val); return mtw_mcu_cmd(sc, 31, &cmd, sizeof(struct mtw_mcu_cmd_8)); @@ -1572,7 +1572,7 @@ mtw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) return 0; } -void +void mtw_newstate_cb(struct mtw_softc *sc, void *arg) { struct mtw_cmd_newstate *cmd = arg; @@ -1947,7 +1947,7 @@ mtw_newassoc(struct ieee80211com *ic, struct ieee80211_node *ni, int isnew) isnew, ether_sprintf(ni->ni_macaddr))); ieee80211_amrr_node_init(&sc->amrr, &sc->amn); - + /* start at lowest available bit-rate, AMRR will raise */ ni->ni_txrate = 0; @@ -2985,12 +2985,12 @@ mtw_wlan_enable(struct mtw_softc *sc, int enable) mtw_read(sc, MTW_WLAN_CTRL, &tmp); if (sc->asic_ver == 0x7612) tmp &= ~0xfffff000; - + tmp &= ~MTW_WLAN_CLK_EN; tmp |= MTW_WLAN_EN; mtw_write(sc, MTW_WLAN_CTRL, tmp); usbd_delay_ms(sc->sc_udev, 2); - + tmp |= MTW_WLAN_CLK_EN; if (sc->asic_ver == 0x7612) { tmp |= (MTW_WLAN_RESET | MTW_WLAN_RESET_RF); @@ -3150,7 +3150,7 @@ mtw_init(struct ifnet *ifp) /* clear RX WCID search table */ mtw_set_region_4(sc, MTW_WCID_ENTRY(0), 0xffffffff, 512); - + /* abort TSF synchronization */ mtw_abort_tsf_sync(sc); @@ -3283,7 +3283,7 @@ mtw_stop(struct ifnet *ifp, int disable) timeout_del(&sc->scan_to); timeout_del(&sc->calib_to); - s = splusb(); + s = splusb(); ieee80211_new_state(ic, IEEE80211_S_INIT, -1); /* wait for all queued asynchronous commands to complete */ usb_wait_task(sc->sc_udev, &sc->sc_task); diff --git a/sys/dev/usb/if_mtwvar.h b/sys/dev/usb/if_mtwvar.h index 013b6e58e..f546d5e58 100644 --- a/sys/dev/usb/if_mtwvar.h +++ b/sys/dev/usb/if_mtwvar.h @@ -38,7 +38,7 @@ #define MTW_RXQ_COUNT 2 #define MTW_TXQ_COUNT 6 -#define MTW_WCID_MAX 8 +#define MTW_WCID_MAX 8 #define MTW_AID2WCID(aid) (1 + ((aid) & 0x7)) struct mtw_rx_radiotap_header { diff --git a/sys/dev/usb/if_mue.c b/sys/dev/usb/if_mue.c index 331d30f7b..46093ca0c 100644 --- a/sys/dev/usb/if_mue.c +++ b/sys/dev/usb/if_mue.c @@ -84,11 +84,11 @@ const struct mue_type mue_devs[] = { int mue_match(struct device *, void *, void *); void mue_attach(struct device *, struct device *, void *); int mue_detach(struct device *, int); - + struct cfdriver mue_cd = { NULL, "mue", DV_IFNET }; - + const struct cfattach mue_ca = { sizeof(struct mue_softc), mue_match, mue_attach, mue_detach }; @@ -226,7 +226,7 @@ mue_csr_write(struct mue_softc *sc, uint32_t reg, uint32_t aval) return (0); } -/* +/* * Get exclusive access to the MII registers. */ void @@ -250,7 +250,7 @@ mue_unlock_mii(struct mue_softc *sc) int mue_mii_wait(struct mue_softc *sc) { - int ntries; + int ntries; for (ntries = 0; ntries < 100; ntries++) { if (!(mue_csr_read(sc, MUE_MII_ACCESS) & MUE_MII_ACCESS_BUSY)) @@ -258,7 +258,7 @@ mue_mii_wait(struct mue_softc *sc) DELAY(5); } - printf("%s: MII timed out\n", sc->mue_dev.dv_xname); + printf("%s: MII timed out\n", sc->mue_dev.dv_xname); return (1); } @@ -423,7 +423,7 @@ int mue_eeprom_wait(struct mue_softc *sc) { uint32_t val; - int ntries; + int ntries; for (ntries = 0; ntries < 100; ntries++) { val = mue_csr_read(sc, MUE_E2P_CMD); @@ -449,7 +449,7 @@ mue_eeprom_getbyte(struct mue_softc *sc, int addr, uint8_t *dest) if (ntries == 100) { printf("%s: EEPROM failed to come ready\n", - sc->mue_dev.dv_xname); + sc->mue_dev.dv_xname); return (ETIMEDOUT); } @@ -474,7 +474,7 @@ mue_read_eeprom(struct mue_softc *sc, caddr_t dest, int off, int cnt) uint8_t byte = 0; int i, err = 0; - /* + /* * EEPROM pins are muxed with the LED function on LAN7800 device. */ val = mue_csr_read(sc, MUE_HW_CFG); @@ -496,10 +496,10 @@ mue_read_eeprom(struct mue_softc *sc, caddr_t dest, int off, int cnt) return (err ? 1 : 0); } -int +int mue_dataport_wait(struct mue_softc *sc) { - int ntries; + int ntries; for (ntries = 0; ntries < 100; ntries++) { if (mue_csr_read(sc, MUE_DP_SEL) & MUE_DP_SEL_DPRDY) @@ -507,7 +507,7 @@ mue_dataport_wait(struct mue_softc *sc) DELAY(5); } - printf("%s: dataport timed out\n", sc->mue_dev.dv_xname); + printf("%s: dataport timed out\n", sc->mue_dev.dv_xname); return (1); } @@ -619,7 +619,7 @@ mue_chip_init(struct mue_softc *sc) mue_csr_write(sc, (sc->mue_flags & LAN7500) ? MUE_FCT_FLOW : MUE_7800_FCT_FLOW, 0); mue_csr_write(sc, MUE_FLOW, 0); - + /* Reset PHY. */ MUE_SETBIT(sc, MUE_PMT_CTL, MUE_PMT_CTL_PHY_RST); for (ntries = 0; ntries < 100; ntries++) { @@ -683,7 +683,7 @@ mue_set_macaddr(struct mue_softc *sc) mue_csr_write(sc, reg, val | MUE_ADDR_FILTX_VALID); } -/* +/* * Probe for a Microchip chip. */ int @@ -979,7 +979,7 @@ mue_encap(struct mue_softc *sc, struct mbuf *m, int idx) MUE_TX_CMD_A_FCS); /* Disable segmentation offload. */ hdr.tx_cmd_b = htole32(0); - memcpy(c->mue_buf, &hdr, sizeof(hdr)); + memcpy(c->mue_buf, &hdr, sizeof(hdr)); length = sizeof(hdr); m_copydata(m, 0, m->m_pkthdr.len, c->mue_buf + length); @@ -1039,7 +1039,7 @@ mue_iff(struct mue_softc *sc) while (enm != NULL) { h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) >> 23; - hashtbl[h / 32] |= 1 << (h % 32); + hashtbl[h / 32] |= 1 << (h % 32); ETHER_NEXT_MULTI(step, enm); } } diff --git a/sys/dev/usb/if_rsu.c b/sys/dev/usb/if_rsu.c index 834fdee0b..c441397fe 100644 --- a/sys/dev/usb/if_rsu.c +++ b/sys/dev/usb/if_rsu.c @@ -1460,7 +1460,7 @@ rsu_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) ifp->if_ierrors++; goto resubmit; } - + /* Determine if it is a firmware C2H event or an 802.11 frame. */ stat = (struct r92s_rx_stat *)data->buf; if ((letoh32(stat->rxdw1) & 0x1ff) == 0x1ff) @@ -2239,7 +2239,7 @@ rsu_init(struct ifnet *ifp) /* Set MAC address. */ IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl)); - rsu_write_region_1(sc, R92S_MACID, ic->ic_myaddr, IEEE80211_ADDR_LEN); + rsu_write_region_1(sc, R92S_MACID, ic->ic_myaddr, IEEE80211_ADDR_LEN); /* Queue Rx xfers (XXX C2H pipe for 11-pipe configurations?) */ for (i = 0; i < RSU_RX_LIST_COUNT; i++) { diff --git a/sys/dev/usb/if_run.c b/sys/dev/usb/if_run.c index 2d4408dd3..bd113dc2c 100644 --- a/sys/dev/usb/if_run.c +++ b/sys/dev/usb/if_run.c @@ -449,7 +449,7 @@ static const struct { RT5592_DEF_BBP }; -/* +/* * Default values for BBP register R196 for RT5592. */ static const uint8_t rt5592_bbp_r196[] = { @@ -3233,7 +3233,7 @@ run_rt3593_set_chan(struct run_softc *sc, u_int chan) run_rt3070_rf_write(sc, 31, (chan <= 14) ? 0xa0 : 0x80); - h20mhz = (sc->rf24_20mhz & 0x20) >> 5; + h20mhz = (sc->rf24_20mhz & 0x20) >> 5; run_rt3070_rf_read(sc, 30, &rf); rf = (rf & ~0x06) | (h20mhz << 1) | (h20mhz << 2); run_rt3070_rf_write(sc, 30, rf); @@ -3260,7 +3260,7 @@ run_rt3593_set_chan(struct run_softc *sc, u_int chan) else rf |= 0x40; run_rt3070_rf_write(sc, 6, rf); - + run_rt3070_rf_read(sc, 30, &rf); rf = (rf & ~0x18) | 0x10; run_rt3070_rf_write(sc, 30, rf); @@ -3505,7 +3505,7 @@ run_rt5592_set_chan(struct run_softc *sc, u_int chan) run_rt3070_rf_write(sc, 55, 0x43); - /* + /* * RF R49/R50 Tx power ALC code. * G-band bit<7:6>=1:0, bit<5:0> range from 0x0 ~ 0x27. */ @@ -3525,7 +3525,7 @@ run_rt5592_set_chan(struct run_softc *sc, u_int chan) } } - /* + /* * RF R49/R50 Tx power ALC code. * A-band bit<7:6>=1:1, bit<5:0> range from 0x0 ~ 0x2b. */ @@ -3932,7 +3932,7 @@ run_rt3070_rf_init(struct run_softc *sc) } } if (sc->mac_ver == 0x3070 && sc->mac_rev < 0x0201) { - /* + /* * Change voltage from 1.2V to 1.35V for RT3070. * The DAC issue (RT3070_LDO_CFG0) has been fixed * in RT3070(F). diff --git a/sys/dev/usb/if_smsc.c b/sys/dev/usb/if_smsc.c index 872a89c6f..084c71607 100644 --- a/sys/dev/usb/if_smsc.c +++ b/sys/dev/usb/if_smsc.c @@ -28,7 +28,7 @@ /* * SMSC LAN9xxx devices (http://www.smsc.com/) - * + * * The LAN9500 & LAN9500A devices are stand-alone USB to Ethernet chips that * support USB 2.0 and 10/100 Mbps Ethernet. * @@ -42,7 +42,7 @@ * H/W TCP & UDP Checksum Offloading * --------------------------------- * The chip supports both tx and rx offloading of UDP & TCP checksums, this - * feature can be dynamically enabled/disabled. + * feature can be dynamically enabled/disabled. * * RX checksumming is performed across bytes after the IPv4 header to the end of * the Ethernet frame, this means if the frame is padded with non-zero values @@ -195,7 +195,7 @@ smsc_enaddr_OF(struct smsc_softc *sc) * much more complicated than strictly needed since the * firmware device tree keeps changing as drivers get * upstreamed. Sigh. - * + * * Ultimately this should just use the "ethernet0" alias and * the "local-mac-address" property. */ @@ -236,7 +236,7 @@ smsc_read_reg(struct smsc_softc *sc, uint32_t off, uint32_t *data) smsc_warn_printf(sc, "Failed to read register 0x%0x\n", off); *data = letoh32(buf); - + return (err); } @@ -367,14 +367,14 @@ smsc_miibus_statchg(struct device *dev) smsc_dbg_printf(sc, "link flag not set\n"); return; } - + err = smsc_read_reg(sc, SMSC_AFC_CFG, &afc_cfg); if (err) { smsc_warn_printf(sc, "failed to read initial AFC_CFG, " "error %d\n", err); return; } - + /* Enable/disable full duplex operation and TX/RX pause */ if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { smsc_dbg_printf(sc, "full duplex operation\n"); @@ -385,17 +385,17 @@ smsc_miibus_statchg(struct device *dev) flow = 0xffff0002; else flow = 0; - + if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) afc_cfg |= 0xf; else afc_cfg &= ~0xf; - + } else { smsc_dbg_printf(sc, "half duplex operation\n"); sc->sc_mac_csr &= ~SMSC_MAC_CSR_FDPX; sc->sc_mac_csr |= SMSC_MAC_CSR_RCVOWN; - + flow = 0; afc_cfg |= 0xf; } @@ -431,7 +431,7 @@ smsc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) struct mii_data *mii = &sc->sc_mii; mii_pollstat(mii); - + ifmr->ifm_active = mii->mii_media_active; ifmr->ifm_status = mii->mii_media_status; } @@ -541,10 +541,10 @@ smsc_setmacaddress(struct smsc_softc *sc, const uint8_t *addr) val = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0]; if ((err = smsc_write_reg(sc, SMSC_MAC_ADDRL, val)) != 0) goto done; - + val = (addr[5] << 8) | addr[4]; err = smsc_write_reg(sc, SMSC_MAC_ADDRH, val); - + done: return (err); } @@ -570,7 +570,7 @@ smsc_init(void *xsc) struct smsc_chain *c; usbd_status err; int s, i; - + s = splnet(); /* Cancel pending I/O */ @@ -853,7 +853,7 @@ smsc_chip_init(struct smsc_softc *sc) } /* GPIO/LED setup */ - reg_val = SMSC_LED_GPIO_CFG_SPD_LED | SMSC_LED_GPIO_CFG_LNK_LED | + reg_val = SMSC_LED_GPIO_CFG_SPD_LED | SMSC_LED_GPIO_CFG_LNK_LED | SMSC_LED_GPIO_CFG_FDX_LED; smsc_write_reg(sc, SMSC_LED_GPIO_CFG, reg_val); @@ -869,7 +869,7 @@ smsc_chip_init(struct smsc_softc *sc) smsc_warn_printf(sc, "failed to read MAC_CSR (err=%d)\n", err); goto init_failed; } - + /* Vlan */ smsc_write_reg(sc, SMSC_VLAN1, (uint32_t)ETHERTYPE_VLAN); @@ -887,7 +887,7 @@ smsc_chip_init(struct smsc_softc *sc) smsc_write_reg(sc, SMSC_MAC_CSR, sc->sc_mac_csr); return (0); - + init_failed: smsc_err_printf(sc, "smsc_chip_init failed (err=%d)\n", err); return (err); @@ -1020,7 +1020,7 @@ smsc_attach(struct device *parent, struct device *self, void *aux) * address based on urandom. */ memset(sc->sc_ac.ac_enaddr, 0xff, ETHER_ADDR_LEN); - + /* Check if there is already a MAC address in the register */ if ((smsc_read_reg(sc, SMSC_MAC_ADDRL, &mac_l) == 0) && (smsc_read_reg(sc, SMSC_MAC_ADDRH, &mac_h) == 0)) { @@ -1033,10 +1033,10 @@ smsc_attach(struct device *parent, struct device *self, void *aux) } smsc_enaddr_OF(sc); - + printf("%s: address %s\n", sc->sc_dev.dv_xname, ether_sprintf(sc->sc_ac.ac_enaddr)); - + /* Initialise the chip for the first time */ smsc_chip_init(sc); @@ -1231,7 +1231,7 @@ smsc_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) total_len = 0; else total_len -= pktlen; - + m = m_devget(buf, pktlen, ETHER_ALIGN); if (m == NULL) { smsc_dbg_printf(sc, "m_devget returned NULL\n"); @@ -1373,15 +1373,15 @@ smsc_encap(struct smsc_softc *sc, struct mbuf *m, int idx) * Each frame is prefixed with two 32-bit values describing the * length of the packet and buffer. */ - txhdr = SMSC_TX_CTRL_0_BUF_SIZE(m->m_pkthdr.len) | + txhdr = SMSC_TX_CTRL_0_BUF_SIZE(m->m_pkthdr.len) | SMSC_TX_CTRL_0_FIRST_SEG | SMSC_TX_CTRL_0_LAST_SEG; txhdr = htole32(txhdr); memcpy(c->sc_buf, &txhdr, sizeof(txhdr)); - + txhdr = SMSC_TX_CTRL_1_PKT_LENGTH(m->m_pkthdr.len); txhdr = htole32(txhdr); memcpy(c->sc_buf + 4, &txhdr, sizeof(txhdr)); - + frm_len += 8; /* Next copy in the actual packet */ diff --git a/sys/dev/usb/if_smscreg.h b/sys/dev/usb/if_smscreg.h index f201fc9c1..4b337b947 100644 --- a/sys/dev/usb/if_smscreg.h +++ b/sys/dev/usb/if_smscreg.h @@ -55,7 +55,7 @@ * TX_CTRL_0 <12> Last segment of frame indicator * TX_CTRL_0 <10:0> Buffer size (?) * - * TX_CTRL_1 <14> Perform H/W checksumming on IP packets + * TX_CTRL_1 <14> Perform H/W checksumming on IP packets * TX_CTRL_1 <13> Disable automatic ethernet CRC generation * TX_CTRL_1 <12> Disable padding (?) * TX_CTRL_1 <10:0> Packet byte length @@ -203,7 +203,7 @@ #define SMSC_MAC_CSR_RXEN (0x1UL << 2) /* RX enable */ /* Interrupt control register */ -#define SMSC_INTR_NTEP (0x1UL << 31) +#define SMSC_INTR_NTEP (0x1UL << 31) #define SMSC_INTR_MACRTO (0x1UL << 19) #define SMSC_INTR_TX_STOP (0x1UL << 17) #define SMSC_INTR_RX_STOP (0x1UL << 16) diff --git a/sys/dev/usb/if_uath.c b/sys/dev/usb/if_uath.c index 336792308..5c105d4a4 100644 --- a/sys/dev/usb/if_uath.c +++ b/sys/dev/usb/if_uath.c @@ -97,7 +97,7 @@ static const struct uath_type { UATH_DEV_UG(CONCEPTRONIC, AR5523_1), UATH_DEV_UX(CONCEPTRONIC, AR5523_2), UATH_DEV_UX(DLINK, DWLAG122), - UATH_DEV_UX(DLINK, DWLAG132), + UATH_DEV_UX(DLINK, DWLAG132), UATH_DEV_UG(DLINK, DWLG132), UATH_DEV_UG(DLINK2, WUA2340), UATH_DEV_UG(GIGASET, AR5523), diff --git a/sys/dev/usb/if_udav.c b/sys/dev/usb/if_udav.c index 156ddde46..6b4f6e31f 100644 --- a/sys/dev/usb/if_udav.c +++ b/sys/dev/usb/if_udav.c @@ -273,7 +273,7 @@ udav_attach(struct device *parent, struct device *self, void *aux) ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); } else { - mii_attach(self, mii, 0xffffffff, + mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0); if (LIST_FIRST(&mii->mii_phys) == NULL) { ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, @@ -538,7 +538,7 @@ int udav_csr_read1(struct udav_softc *sc, int offset) { u_int8_t val = 0; - + if (sc == NULL) return (0); @@ -1076,10 +1076,10 @@ udav_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) ifp->if_ierrors++; goto done; } - + h = (struct udav_rx_hdr *)c->udav_buf; total_len = UGETW(h->length) - ETHER_CRC_LEN; - + DPRINTF(("%s: RX Status: 0x%02x\n", sc->sc_dev.dv_xname, h->pktstat)); if (h->pktstat & UDAV_RSR_LCS) { diff --git a/sys/dev/usb/if_udavreg.h b/sys/dev/usb/if_udavreg.h index 45254f8a8..481bca837 100644 --- a/sys/dev/usb/if_udavreg.h +++ b/sys/dev/usb/if_udavreg.h @@ -60,7 +60,7 @@ #define UDAV_NSR 0x01 /* Network Status Register */ #define UDAV_NSR_SPEED (1<<7) /* Media Speed (Int. PHY) */ #define UDAV_NSR_LINKST (1<<6) /* Link Status (Int. PHY) */ -#define UDAV_NSR_WAKEST (1<<5) /* Wakeup Status */ +#define UDAV_NSR_WAKEST (1<<5) /* Wakeup Status */ #define UDAV_NSR_TXFULL (1<<4) /* TX FIFO Full */ #define UDAV_NSR_TX2END (1<<3) /* TX Packet 2 Complete Status */ #define UDAV_NSR_TX1END (1<<2) /* TX Packet 1 Complete Status */ diff --git a/sys/dev/usb/if_umb.c b/sys/dev/usb/if_umb.c index 46ecb6842..aa0b66a15 100644 --- a/sys/dev/usb/if_umb.c +++ b/sys/dev/usb/if_umb.c @@ -1649,7 +1649,7 @@ umb_decode_packet_service(struct umb_softc *sc, void *data, int len) addlog("changed from %s to ", umb_packet_state(sc->sc_info.packetstate)); addlog("%s, class %s, speed: %llu up / %llu down\n", - umb_packet_state(state), + umb_packet_state(state), umb_dataclass(highestclass), up_speed, down_speed); } } @@ -1727,7 +1727,7 @@ umb_decode_signal_state(struct umb_softc *sc, void *data, int len) uks->rssi.kv_type = KSTAT_KV_T_INT32; kstat_kv_s32(&uks->rssi) = sc->sc_info.rssi; } - + if (sc->sc_info.ber == UMB_VALUE_UNKNOWN) uks->error_rate.kv_type = KSTAT_KV_T_NULL; else { @@ -2057,7 +2057,7 @@ umb_decode_ip_configuration(struct umb_softc *sc, void *data, int len) memcpy(&gw, data + off, sizeof(gw)); rv = umb_add_inet_config(sc, addr, ipv4elem.prefixlen, gw); - if (rv == 0) + if (rv == 0) state = UMB_S_UP; } diff --git a/sys/dev/usb/if_upgt.c b/sys/dev/usb/if_upgt.c index 1014943aa..3b5ea0049 100644 --- a/sys/dev/usb/if_upgt.c +++ b/sys/dev/usb/if_upgt.c @@ -635,7 +635,7 @@ upgt_fw_verify(struct upgt_softc *sc) if (*uc != 0) break; } - if (offset == sc->sc_fw_size) { + if (offset == sc->sc_fw_size) { printf("%s: firmware Boot Record Area not found!\n", sc->sc_dev.dv_xname); return (EIO); diff --git a/sys/dev/usb/if_urtw.c b/sys/dev/usb/if_urtw.c index cd66f1d31..52960b3f4 100644 --- a/sys/dev/usb/if_urtw.c +++ b/sys/dev/usb/if_urtw.c @@ -1075,7 +1075,7 @@ urtw_8225_write_s16(struct urtw_softc *sc, uint8_t addr, int index, USETW(req.wIndex, index); USETW(req.wLength, sizeof(uint16_t)); - data = htole16(data); + data = htole16(data); return (usbd_do_request(sc->sc_udev, &req, &data)); } @@ -1645,7 +1645,7 @@ urtw_write16_c(struct urtw_softc *sc, int val, uint16_t data, uint8_t idx) USETW(req.wIndex, idx & 0x03); USETW(req.wLength, sizeof(uint16_t)); - data = htole16(data); + data = htole16(data); return (usbd_do_request(sc->sc_udev, &req, &data)); } @@ -1660,7 +1660,7 @@ urtw_write32_c(struct urtw_softc *sc, int val, uint32_t data, uint8_t idx) USETW(req.wIndex, idx & 0x03); USETW(req.wLength, sizeof(uint32_t)); - data = htole32(data); + data = htole32(data); return (usbd_do_request(sc->sc_udev, &req, &data)); } diff --git a/sys/dev/usb/if_wi_usb.c b/sys/dev/usb/if_wi_usb.c index 5e44e6c02..7a2b54105 100644 --- a/sys/dev/usb/if_wi_usb.c +++ b/sys/dev/usb/if_wi_usb.c @@ -69,7 +69,7 @@ #include -int wi_usb_do_transmit_sync(struct wi_usb_softc *wsc, struct wi_usb_chain *c, +int wi_usb_do_transmit_sync(struct wi_usb_softc *wsc, struct wi_usb_chain *c, void *ident); void wi_usb_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status); @@ -565,7 +565,7 @@ wi_cmd_usb(struct wi_softc *wsc, int cmd, int val0, int val1, int val2) total_len = sizeof (struct wi_cmdreq); rnd_len = ROUNDUP64(total_len); if (rnd_len > WI_USB_BUFSZ) { - printf("read_record buf size err %x %x\n", + printf("read_record buf size err %x %x\n", rnd_len, WI_USB_BUFSZ); err = EIO; goto err_ret; @@ -648,7 +648,7 @@ wi_read_record_usb(struct wi_softc *wsc, struct wi_ltv_gen *ltv) rnd_len = ROUNDUP64(total_len); if (rnd_len > WI_USB_BUFSZ) { - printf("read_record buf size err %x %x\n", + printf("read_record buf size err %x %x\n", rnd_len, WI_USB_BUFSZ); wi_usb_tx_unlock(sc); return EIO; @@ -862,7 +862,7 @@ wi_write_record_usb(struct wi_softc *wsc, struct wi_ltv_gen *ltv) sizeof(prid->rid) + (ltv->wi_len-1)*2; rnd_len = ROUNDUP64(total_len); if (rnd_len > WI_USB_BUFSZ) { - printf("write_record buf size err %x %x\n", + printf("write_record buf size err %x %x\n", rnd_len, WI_USB_BUFSZ); wi_usb_tx_unlock(sc); return EIO; @@ -1654,7 +1654,7 @@ wi_start_usb(struct ifnet *ifp) splx(s); } -/* +/* * inquire is called from interrupt context (timeout) * It is not possible to sleep in interrupt context so it is necessary * to signal the kernel thread to perform the action. @@ -1670,7 +1670,7 @@ wi_init_usb(struct wi_softc *wsc) } -/* +/* * inquire is called from interrupt context (timeout) * It is not possible to sleep in interrupt context so it is necessary * to signal the kernel thread to perform the action. @@ -1695,7 +1695,7 @@ wi_inquire_usb(void *xsc) splx(s); } -/* +/* * Watchdog is normally called from interrupt context (timeout) * It is not possible to sleep in interrupt context so it is necessary * to signal the kernel thread to perform the action. @@ -1723,9 +1723,9 @@ wi_watchdog_usb(struct ifnet *ifp) } /* - * ioctl will always be called from a user context, + * ioctl will always be called from a user context, * therefore it is possible to sleep in the calling context - * acquire the lock and call the real ioctl function directly + * acquire the lock and call the real ioctl function directly */ int wi_ioctl_usb(struct ifnet *ifp, u_long command, caddr_t data) @@ -1768,7 +1768,7 @@ wi_usb_thread(void *arg) wi_usb_ctl_unlock(sc); for(;;) { - if (wi_thread_info->dying) { + if (wi_thread_info->dying) { if (--sc->wi_usb_refcnt < 0) usb_detach_wakeup(&sc->wi_usb_dev); kthread_exit(0); diff --git a/sys/dev/usb/if_wi_usb.h b/sys/dev/usb/if_wi_usb.h index 7216a5b0a..701abd8de 100644 --- a/sys/dev/usb/if_wi_usb.h +++ b/sys/dev/usb/if_wi_usb.h @@ -55,7 +55,7 @@ struct wi_rridreq { u_int16_t type; /* 0x00 */ u_int16_t frmlen; /* 0x02 */ u_int16_t rid; /* 0x04 */ - u_int8_t pad[58]; /* 0x06 + sizeof(.) == 64 */ + u_int8_t pad[58]; /* 0x06 + sizeof(.) == 64 */ }; struct wi_rridresp { u_int16_t type; /* 0x00 */ diff --git a/sys/dev/usb/if_zyd.c b/sys/dev/usb/if_zyd.c index 7e3fa3312..9c80c388e 100644 --- a/sys/dev/usb/if_zyd.c +++ b/sys/dev/usb/if_zyd.c @@ -855,7 +855,7 @@ zyd_cmd_write(struct zyd_softc *sc, u_int16_t code, const void *data, int len) int zyd_write16(struct zyd_softc *sc, uint16_t reg, uint16_t val) -{ +{ struct zyd_io io; io.reg = htole16(reg); diff --git a/sys/dev/usb/moscom.c b/sys/dev/usb/moscom.c index 9e7f05492..924c124b1 100644 --- a/sys/dev/usb/moscom.c +++ b/sys/dev/usb/moscom.c @@ -60,11 +60,11 @@ #define MOSCOM_INT_RXEN 0x01 #define MOSCOM_INT_TXEN 0x02 -#define MOSCOM_INT_RSEN 0x04 +#define MOSCOM_INT_RSEN 0x04 #define MOSCOM_INT_MDMEM 0x08 #define MOSCOM_INT_SLEEP 0x10 #define MOSCOM_INT_XOFF 0x20 -#define MOSCOM_INT_RTS 0x40 +#define MOSCOM_INT_RTS 0x40 #define MOSCOM_FIFO_EN 0x01 #define MOSCOM_FIFO_RXCLR 0x02 @@ -143,7 +143,7 @@ struct moscom_softc { void moscom_set(void *, int, int, int); int moscom_param(void *, int, struct termios *); int moscom_open(void *, int); -int moscom_cmd(struct moscom_softc *, int, int); +int moscom_cmd(struct moscom_softc *, int, int); const struct ucom_methods moscom_methods = { NULL, @@ -243,7 +243,7 @@ moscom_attach(struct device *parent, struct device *self, void *aux) uca.methods = &moscom_methods; uca.arg = sc; uca.info = NULL; - + sc->sc_subdev = config_found_sm(self, &uca, ucomprint, ucomsubmatch); } @@ -273,10 +273,10 @@ moscom_open(void *vsc, int portno) /* Purge FIFOs or odd things happen */ if (moscom_cmd(sc, MOSCOM_FIFO, 0x00) != 0) return (EIO); - + if (moscom_cmd(sc, MOSCOM_FIFO, MOSCOM_FIFO_EN | MOSCOM_FIFO_RXCLR | MOSCOM_FIFO_TXCLR | - MOSCOM_FIFO_DMA_BLK | MOSCOM_FIFO_RXLVL_MASK) != 0) + MOSCOM_FIFO_DMA_BLK | MOSCOM_FIFO_RXLVL_MASK) != 0) return (EIO); /* Magic tell device we're ready for data command */ @@ -383,7 +383,7 @@ moscom_cmd(struct moscom_softc *sc, int reg, int val) { usb_device_request_t req; usbd_status err; - + req.bmRequestType = UT_WRITE_VENDOR_DEVICE; req.bRequest = MOSCOM_WRITE; USETW(req.wValue, val + MOSCOM_UART_REG); diff --git a/sys/dev/usb/ohci.c b/sys/dev/usb/ohci.c index 1411fb493..eb1fb516f 100644 --- a/sys/dev/usb/ohci.c +++ b/sys/dev/usb/ohci.c @@ -685,7 +685,7 @@ ohci_handover(struct ohci_softc *sc) if (ctl & OHCI_IR) { /* SMM active, request change */ DPRINTF(("ohci_handover: SMM active, request owner change\n")); - if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == + if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == (OHCI_OC | OHCI_MIE)) OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); s = OREAD4(sc, OHCI_COMMAND_STATUS); diff --git a/sys/dev/usb/uark.c b/sys/dev/usb/uark.c index 043527bca..d42415333 100644 --- a/sys/dev/usb/uark.c +++ b/sys/dev/usb/uark.c @@ -170,7 +170,7 @@ uark_attach(struct device *parent, struct device *self, void *aux) uca.methods = &uark_methods; uca.arg = sc; uca.info = NULL; - + sc->sc_subdev = config_found_sm(self, &uca, ucomprint, ucomsubmatch); } @@ -280,7 +280,7 @@ void uark_get_status(void *vsc, int portno, u_char *lsr, u_char *msr) { struct uark_softc *sc = vsc; - + if (msr != NULL) *msr = sc->sc_msr; if (lsr != NULL) diff --git a/sys/dev/usb/uaudio.c b/sys/dev/usb/uaudio.c index d8e300a52..30c897476 100644 --- a/sys/dev/usb/uaudio.c +++ b/sys/dev/usb/uaudio.c @@ -357,7 +357,7 @@ struct uaudio_softc { /* pointer to first byte available */ unsigned char *ring_pos; - + /* audio(9) block size in bytes */ int ring_blksz; @@ -2966,7 +2966,7 @@ uaudio_stream_open(struct uaudio_softc *sc, int dir, /* * Require at least 2ms block size to ensure no * transfer exceeds two blocks. - * + * * XXX: use s->nframes_mask instead of 1000 */ if (1000 * blksz < 2 * sc->rate * bpa) { diff --git a/sys/dev/usb/uberry.c b/sys/dev/usb/uberry.c index f3d2248b1..714f7cca4 100644 --- a/sys/dev/usb/uberry.c +++ b/sys/dev/usb/uberry.c @@ -148,7 +148,7 @@ uberry_pearlmode(struct uberry_softc *sc) (void) usbd_do_request(sc->sc_udev, &req, &buffer); } -void +void uberry_charge(struct uberry_softc *sc) { usb_device_request_t req; diff --git a/sys/dev/usb/ubsa.c b/sys/dev/usb/ubsa.c index 22f534cc4..072e69a7d 100644 --- a/sys/dev/usb/ubsa.c +++ b/sys/dev/usb/ubsa.c @@ -652,11 +652,11 @@ ubsa_intr(struct usbd_xfer *xfer, void *priv, usbd_status status) #if 1 /* test */ if (cdcbuf->bmRequestType == UCDC_NOTIFICATION) { - printf("%s: this device is using CDC notify message in" + printf("%s: this device is using CDC notify message in" " intr pipe.\n" "Please send your dmesg to , thanks.\n", sc->sc_dev.dv_xname); - printf("%s: intr buffer 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", + printf("%s: intr buffer 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", sc->sc_dev.dv_xname, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6]); diff --git a/sys/dev/usb/udcf.c b/sys/dev/usb/udcf.c index 4b0b2f05e..3e1021ba7 100644 --- a/sys/dev/usb/udcf.c +++ b/sys/dev/usb/udcf.c @@ -481,7 +481,7 @@ udcf_bv_probe(void *xsc) if (data == -1) { DPRINTF(("bit detection failed\n")); return; - } + } DPRINTFN(1, (data ? "0" : "1")); if (!(data)) @@ -514,7 +514,7 @@ udcf_mg_probe(void *xsc) if (gettime() - sc->sc_last_mg < 57) { DPRINTF(("\nunexpected gap, resync\n")); sc->sc_sync = sc->sc_minute = 1; - goto cleanbits; + goto cleanbits; } /* extract bits w/o parity */ @@ -529,7 +529,7 @@ udcf_mg_probe(void *xsc) p2_bit = sc->sc_tbits >> 35 & 1; p3_bit = sc->sc_tbits >> 58 & 1; - minute_bits = sc->sc_tbits >> 21 & 0x7f; + minute_bits = sc->sc_tbits >> 21 & 0x7f; hour_bits = sc->sc_tbits >> 29 & 0x3f; day_bits = sc->sc_tbits >> 36 & 0x3f; wday = (sc->sc_tbits >> 42) & 0x07; diff --git a/sys/dev/usb/udl.c b/sys/dev/usb/udl.c index 2136a6dc9..d61d6e2c7 100644 --- a/sys/dev/usb/udl.c +++ b/sys/dev/usb/udl.c @@ -1372,7 +1372,7 @@ udl_set_enc_key(struct udl_softc *sc, uint8_t *buf, uint8_t len) printf("%s: %s: %s!\n", DN(sc), FUNC, usbd_errstr(error)); return (error); } - + return (USBD_NORMAL_COMPLETION); } @@ -2036,7 +2036,7 @@ udl_select_mode(struct udl_softc *sc) (sc->sc_edid_info.edid_preferred_mode->dot_clock * 1000) / (sc->sc_edid_info.edid_preferred_mode->htotal * sc->sc_edid_info.edid_preferred_mode->vtotal); - mode.clock = + mode.clock = sc->sc_edid_info.edid_preferred_mode->dot_clock / 10; mode.hdisplay = sc->sc_edid_info.edid_preferred_mode->hdisplay; @@ -2059,7 +2059,7 @@ udl_select_mode(struct udl_softc *sc) (sc->sc_edid_info.edid_modes[i].dot_clock * 1000) / (sc->sc_edid_info.edid_modes[i].htotal * sc->sc_edid_info.edid_modes[i].vtotal); - mode.clock = + mode.clock = sc->sc_edid_info.edid_modes[i].dot_clock / 10; mode.hdisplay = sc->sc_edid_info.edid_modes[i].hdisplay; @@ -2145,7 +2145,7 @@ udl_fb_line_write(struct udl_softc *sc, uint16_t rgb16, uint32_t x, off = (y * sc->sc_width) + x; while (width) { - if (width > UDL_CMD_MAX_PIXEL_COUNT) + if (width > UDL_CMD_MAX_PIXEL_COUNT) block = UDL_CMD_MAX_PIXEL_COUNT; else block = width; @@ -2334,7 +2334,7 @@ udl_fb_line_write_comp(struct udl_softc *sc, uint16_t rgb16, uint32_t x, off = (y * sc->sc_width) + x; while (width) { - if (width > UDL_CMD_MAX_PIXEL_COUNT) + if (width > UDL_CMD_MAX_PIXEL_COUNT) block = UDL_CMD_MAX_PIXEL_COUNT; else block = width; diff --git a/sys/dev/usb/udlio.h b/sys/dev/usb/udlio.h index 5cfbc5f12..fd4c7226a 100644 --- a/sys/dev/usb/udlio.h +++ b/sys/dev/usb/udlio.h @@ -20,7 +20,7 @@ * udl IOCTLs. */ struct udl_ioctl_damage { - int x1; + int x1; int x2; int y1; int y2; diff --git a/sys/dev/usb/udsbr.c b/sys/dev/usb/udsbr.c index 3960e03e3..695699efe 100644 --- a/sys/dev/usb/udsbr.c +++ b/sys/dev/usb/udsbr.c @@ -90,21 +90,21 @@ void udsbr_stop(struct udsbr_softc *sc); void udsbr_setfreq(struct udsbr_softc *sc, int freq); int udsbr_status(struct udsbr_softc *sc); -int udsbr_match(struct device *, void *, void *); -void udsbr_attach(struct device *, struct device *, void *); -int udsbr_detach(struct device *, int); -int udsbr_activate(struct device *, int); +int udsbr_match(struct device *, void *, void *); +void udsbr_attach(struct device *, struct device *, void *); +int udsbr_detach(struct device *, int); +int udsbr_activate(struct device *, int); -struct cfdriver udsbr_cd = { - NULL, "udsbr", DV_DULL -}; +struct cfdriver udsbr_cd = { + NULL, "udsbr", DV_DULL +}; -const struct cfattach udsbr_ca = { - sizeof(struct udsbr_softc), - udsbr_match, - udsbr_attach, - udsbr_detach, - udsbr_activate, +const struct cfattach udsbr_ca = { + sizeof(struct udsbr_softc), + udsbr_match, + udsbr_attach, + udsbr_detach, + udsbr_activate, }; int diff --git a/sys/dev/usb/uftdi.c b/sys/dev/usb/uftdi.c index 288c24c79..971059232 100644 --- a/sys/dev/usb/uftdi.c +++ b/sys/dev/usb/uftdi.c @@ -1169,7 +1169,7 @@ uftdi_8u232am_getrate(struct uftdi_softc *sc, speed_t speed, int *rate) else if (d > FTDI_8U232AM_MAX_DIV) d = FTDI_8U232AM_MAX_DIV; - /* + /* * Calculate the frequency needed for d to exactly divide down * to our target speed, and check that the actual frequency is * within 3% of this. @@ -1179,7 +1179,7 @@ uftdi_8u232am_getrate(struct uftdi_softc *sc, speed_t speed, int *rate) freq > (quad_t)(FTDI_8U232AM_FREQ << 4) * 100 / 97) return (-1); - /* + /* * Pack the divisor into the resultant value. The lower * 14-bits hold the integral part, while the upper 2 bits * encode the fractional component: either 0, 0.5, 0.25, or diff --git a/sys/dev/usb/ugen.c b/sys/dev/usb/ugen.c index 194a39a87..72085f336 100644 --- a/sys/dev/usb/ugen.c +++ b/sys/dev/usb/ugen.c @@ -899,7 +899,7 @@ ugen_isoc_rintr(struct usbd_xfer *xfer, void *addr, usbd_status status) selwakeup(&sce->rsel); } -int +int ugen_set_interface(struct ugen_softc *sc, int ifaceno, int altno) { struct usbd_interface *iface; diff --git a/sys/dev/usb/uhci.c b/sys/dev/usb/uhci.c index 536c40103..63b21d47f 100644 --- a/sys/dev/usb/uhci.c +++ b/sys/dev/usb/uhci.c @@ -2849,7 +2849,7 @@ uhci_portreset(struct uhci_softc *sc, int index) DPRINTFN(1,("uhci port %d reset timed out\n", index)); return (USBD_TIMEOUT); } - + sc->sc_isreset = 1; return (USBD_NORMAL_COMPLETION); } diff --git a/sys/dev/usb/uhid.c b/sys/dev/usb/uhid.c index a036e3f12..d672b28f8 100644 --- a/sys/dev/usb/uhid.c +++ b/sys/dev/usb/uhid.c @@ -72,15 +72,15 @@ int uhiddebug = 0; int uhid_match(struct device *, void *, void *); -struct cfdriver uhid_cd = { - NULL, "uhid", DV_DULL -}; +struct cfdriver uhid_cd = { + NULL, "uhid", DV_DULL +}; -const struct cfattach uhid_ca = { - sizeof(struct uhid_softc), - uhid_match, - uhid_attach, - uhid_detach, +const struct cfattach uhid_ca = { + sizeof(struct uhid_softc), + uhid_match, + uhid_attach, + uhid_detach, }; struct uhid_softc * diff --git a/sys/dev/usb/uhid.h b/sys/dev/usb/uhid.h index e54454612..0355806e5 100644 --- a/sys/dev/usb/uhid.h +++ b/sys/dev/usb/uhid.h @@ -59,7 +59,7 @@ struct uhid_softc *uhid_lookup(dev_t); int uhid_do_open(dev_t, int, int, struct proc *); -void uhid_attach(struct device *, struct device *, void *); -int uhid_detach(struct device *, int); +void uhid_attach(struct device *, struct device *, void *); +int uhid_detach(struct device *, int); #endif /* _KERNEL */ diff --git a/sys/dev/usb/uipaq.c b/sys/dev/usb/uipaq.c index c5aa8a03c..3acadc679 100644 --- a/sys/dev/usb/uipaq.c +++ b/sys/dev/usb/uipaq.c @@ -32,7 +32,7 @@ /* * iPAQ driver - * + * * 19 July 2003: Incorporated changes suggested by Sam Lawrance from * the uppc module * diff --git a/sys/dev/usb/umass.c b/sys/dev/usb/umass.c index 699a491d4..59ef30909 100644 --- a/sys/dev/usb/umass.c +++ b/sys/dev/usb/umass.c @@ -173,13 +173,13 @@ char *states[TSTATE_STATES+1] = { #endif /* USB device probe/attach/detach functions */ -int umass_match(struct device *, void *, void *); -void umass_attach(struct device *, struct device *, void *); -int umass_detach(struct device *, int); +int umass_match(struct device *, void *, void *); +void umass_attach(struct device *, struct device *, void *); +int umass_detach(struct device *, int); -struct cfdriver umass_cd = { - NULL, "umass", DV_DULL -}; +struct cfdriver umass_cd = { + NULL, "umass", DV_DULL +}; const struct cfattach umass_ca = { sizeof(struct umass_softc), umass_match, umass_attach, umass_detach @@ -842,7 +842,7 @@ umass_adjust_transfer(struct umass_softc *sc) } break; case UMASS_CPROTO_ATAPI: - sc->cbw.bCDBLength = UFI_COMMAND_LENGTH; + sc->cbw.bCDBLength = UFI_COMMAND_LENGTH; break; } } diff --git a/sys/dev/usb/umbg.c b/sys/dev/usb/umbg.c index 62e5bd017..2ddebc4df 100644 --- a/sys/dev/usb/umbg.c +++ b/sys/dev/usb/umbg.c @@ -182,7 +182,7 @@ umbg_attach(struct device *parent, struct device *self, void *aux) sc->sc_timedelta.type = SENSOR_TIMEDELTA; sc->sc_timedelta.status = SENSOR_S_UNKNOWN; - + switch (uaa->product) { case USB_PRODUCT_MEINBERG_DCF600USB: desc = "DCF600USB"; @@ -375,7 +375,7 @@ umbg_task(void *arg) bail_out: timeout_add_sec(&sc->sc_to, t_wait); - + } /* send a command and read back results */ diff --git a/sys/dev/usb/umcs.h b/sys/dev/usb/umcs.h index 3062d7dc2..66682ea68 100644 --- a/sys/dev/usb/umcs.h +++ b/sys/dev/usb/umcs.h @@ -115,8 +115,8 @@ #define UMCS_THR_VAL_HIGH3 0x44 #define UMCS_THR_VAL_LOW4 0x45 #define UMCS_THR_VAL_HIGH4 0x46 - - + + /* Bits for SPx registers */ #define UMCS_SPx_LOOP_PIPES 0x01 /* Loop Out FIFO to In FIFO */ #define UMCS_SPx_SKIP_ERR_DATA 0x02 /* Drop data received with errors */ @@ -229,7 +229,7 @@ #define UMCS_MODE_IRDA 0x80 /* IrDA mode is activated (default) */ /* All 8 bits is used as number of BAUD clocks of pause */ -#define UMCS_SPx_ICG_DEF 0x24 +#define UMCS_SPx_ICG_DEF 0x24 /* @@ -286,7 +286,7 @@ #define UMCS_DCR0_RESERVED1 0x02 /* Unused */ #define UMCS_DCR0_GPIO_MASK 0x0c /* GPIO Mode bits */ #define UMCS_DCR0_GPIO_IN 0x00 /* GPIO Mode - Input (0b00) */ -#define UMCS_DCR0_GPIO_OUT 0x08 /* GPIO Mode - Input (0b10) */ +#define UMCS_DCR0_GPIO_OUT 0x08 /* GPIO Mode - Input (0b10) */ #define UMCS_DCR0_RTS_ACTHI 0x10 /* RTS Active is High, (default low) */ #define UMCS_DCR0_RTS_AUTO 0x20 /* Control by state TX buffer or MCR */ #define UMCS_DCR0_IRDA 0x40 /* IrDA mode */ diff --git a/sys/dev/usb/umidi.c b/sys/dev/usb/umidi.c index 2fc5a091c..4a81772e9 100644 --- a/sys/dev/usb/umidi.c +++ b/sys/dev/usb/umidi.c @@ -123,21 +123,21 @@ const struct midi_hw_if umidi_hw_if = { 0, /* ioctl */ }; -int umidi_match(struct device *, void *, void *); -void umidi_attach(struct device *, struct device *, void *); -int umidi_detach(struct device *, int); -int umidi_activate(struct device *, int); +int umidi_match(struct device *, void *, void *); +void umidi_attach(struct device *, struct device *, void *); +int umidi_detach(struct device *, int); +int umidi_activate(struct device *, int); -struct cfdriver umidi_cd = { - NULL, "umidi", DV_DULL -}; +struct cfdriver umidi_cd = { + NULL, "umidi", DV_DULL +}; -const struct cfattach umidi_ca = { - sizeof(struct umidi_softc), - umidi_match, - umidi_attach, - umidi_detach, - umidi_activate, +const struct cfattach umidi_ca = { + sizeof(struct umidi_softc), + umidi_match, + umidi_attach, + umidi_detach, + umidi_activate, }; int @@ -868,7 +868,7 @@ open_out_jack(struct umidi_jack *jack, void *arg, void (*intr)(void *)) init_packet(&jack->packet); jack->opened = 1; jack->endpoint->num_open++; - + return USBD_NORMAL_COMPLETION; } @@ -881,8 +881,8 @@ open_in_jack(struct umidi_jack *jack, void *arg, void (*intr)(void *, int)) jack->arg = arg; jack->u.in.intr = intr; jack->opened = 1; - jack->endpoint->num_open++; - + jack->endpoint->num_open++; + return USBD_NORMAL_COMPLETION; } @@ -1088,7 +1088,7 @@ start_input_transfer(struct umidi_endpoint *ep) USBD_SHORT_XFER_OK | USBD_NO_COPY, USBD_NO_TIMEOUT, in_intr); err = usbd_transfer(ep->xfer); if (err != USBD_NORMAL_COMPLETION && err != USBD_IN_PROGRESS) { - DPRINTF(("%s: %s: usbd_transfer() failed err=%s\n", + DPRINTF(("%s: %s: usbd_transfer() failed err=%s\n", ep->sc->sc_dev.dv_xname, __func__, usbd_errstr(err))); return err; } @@ -1105,7 +1105,7 @@ start_output_transfer(struct umidi_endpoint *ep) USBD_NO_COPY, USBD_NO_TIMEOUT, out_intr); err = usbd_transfer(ep->xfer); if (err != USBD_NORMAL_COMPLETION && err != USBD_IN_PROGRESS) { - DPRINTF(("%s: %s: usbd_transfer() failed err=%s\n", + DPRINTF(("%s: %s: usbd_transfer() failed err=%s\n", ep->sc->sc_dev.dv_xname, __func__, usbd_errstr(err))); return err; } @@ -1144,7 +1144,7 @@ out_jack_output(struct umidi_jack *j, int d) SIMPLEQ_INSERT_TAIL(&ep->intrq, j, intrq_entry); ep->pending++; j->intr = 1; - } + } splx(s); return 0; } @@ -1170,8 +1170,8 @@ out_jack_flush(struct umidi_jack *j) if (usbd_is_dying(ep->sc->sc_udev) || !j->opened) return; - - s = splusb(); + + s = splusb(); if (ep->used != 0 && !ep->busy) { ep->busy = 1; start_output_transfer(ep); @@ -1220,7 +1220,7 @@ out_intr(struct usbd_xfer *xfer, void *priv, usbd_status status) struct umidi_softc *sc = ep->sc; struct umidi_jack *j; unsigned pending; - + if (usbd_is_dying(sc->sc_udev)) return; @@ -1255,7 +1255,7 @@ static const unsigned int umidi_evlen[] = { 4, 4, 4, 4, 3, 3, 4 }; #define EV_SYSEX_STOP 0xf7 static int -out_build_packet(int cable_number, struct umidi_packet *packet, +out_build_packet(int cable_number, struct umidi_packet *packet, uByte data, u_char *obuf) { if (data >= 0xf8) { /* is it a realtime message ? */ @@ -1274,12 +1274,12 @@ out_build_packet(int cable_number, struct umidi_packet *packet, case EV_SYSEX_STOP: if (packet->status != EV_SYSEX) break; if (packet->index == 0) - packet->index = 1; + packet->index = 1; packet->status = data; packet->buf[packet->index++] = data; packet->buf[0] = (0x4 - 1 + packet->index) | cable_number << 4; goto packetready; - case EV_TUNE_REQ: + case EV_TUNE_REQ: packet->status = data; packet->buf[0] = 0x5 | cable_number << 4; packet->index = 1; @@ -1289,19 +1289,19 @@ out_build_packet(int cable_number, struct umidi_packet *packet, break; } return 0; - } + } if (data >= 0x80) { /* is it a voice message ? */ packet->status = data; packet->index = 0; return 0; - } + } - /* else it is a data byte */ + /* else it is a data byte */ if (packet->status >= 0xf0) { switch(packet->status) { case EV_SYSEX: /* sysex starts or continues */ if (packet->index == 0) - packet->index = 1; + packet->index = 1; packet->buf[packet->index++] = data; if (packet->index >= UMIDI_PACKET_SIZE) { @@ -1310,7 +1310,7 @@ out_build_packet(int cable_number, struct umidi_packet *packet, } break; case EV_MTC: /* messages with 1 data byte */ - case EV_SONGSEL: + case EV_SONGSEL: packet->buf[0] = 0x2 | cable_number << 4; packet->buf[1] = packet->status; packet->buf[2] = data; @@ -1344,7 +1344,7 @@ out_build_packet(int cable_number, struct umidi_packet *packet, } /* ignore data with unknown status */ return 0; - + packetready: while (packet->index < UMIDI_PACKET_SIZE) packet->buf[packet->index++] = 0; diff --git a/sys/dev/usb/umidivar.h b/sys/dev/usb/umidivar.h index 841e9e062..42e2311f6 100644 --- a/sys/dev/usb/umidivar.h +++ b/sys/dev/usb/umidivar.h @@ -67,7 +67,7 @@ struct umidi_jack { void *arg; int binded; int opened; - SIMPLEQ_ENTRY(umidi_jack) intrq_entry; + SIMPLEQ_ENTRY(umidi_jack) intrq_entry; unsigned intr; union { struct { diff --git a/sys/dev/usb/umsm.c b/sys/dev/usb/umsm.c index 144667b50..7c6ee1603 100644 --- a/sys/dev/usb/umsm.c +++ b/sys/dev/usb/umsm.c @@ -354,7 +354,7 @@ umsm_match(struct device *parent, void *match, void *aux) id->bInterfaceProtocol == 0x00)))) { return UMATCH_NONE; - /* See the Quectel LTE&5G Linux USB Driver User Guide */ + /* See the Quectel LTE&5G Linux USB Driver User Guide */ } else if (uaa->vendor == USB_VENDOR_QUECTEL) { /* Some interfaces can be used as network devices */ if (id->bInterfaceClass != UICLASS_VENDOR) diff --git a/sys/dev/usb/umstc.c b/sys/dev/usb/umstc.c index 4bebeb418..832556ef4 100644 --- a/sys/dev/usb/umstc.c +++ b/sys/dev/usb/umstc.c @@ -200,7 +200,7 @@ umstc_brightness_task(void *arg) steps = -steps; dir = -1; } - + while (steps--) wsdisplay_brightness_step(NULL, dir); } diff --git a/sys/dev/usb/uoak.h b/sys/dev/usb/uoak.h index c1c63a725..fb83640e9 100644 --- a/sys/dev/usb/uoak.h +++ b/sys/dev/usb/uoak.h @@ -123,7 +123,7 @@ struct uoak_softc { size_t sc_flen; /* feature report length */ size_t sc_ilen; /* input report length */ size_t sc_olen; /* output report length */ - uint8_t *sc_ibuf; + uint8_t *sc_ibuf; /* buffers */ struct uoak_rcmd sc_rcmd; diff --git a/sys/dev/usb/uoak_subr.c b/sys/dev/usb/uoak_subr.c index c6d16240a..020d16906 100644 --- a/sys/dev/usb/uoak_subr.c +++ b/sys/dev/usb/uoak_subr.c @@ -16,7 +16,7 @@ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ -/* TORADEX OAK series sensors: common functions */ +/* TORADEX OAK series sensors: common functions */ /* http://developer.toradex.com/files/toradex-dev/uploads/media/Oak/Oak_ProgrammingGuide.pdf */ #include @@ -86,7 +86,7 @@ uoak_get_cmd(struct uoak_softc *sc) sc->sc_rcmd.dir = OAK_GET; /* check the device is ready to request */ - while (uoak_check_device_ready(sc) < 0) + while (uoak_check_device_ready(sc) < 0) usbd_delay_ms(sc->sc_udev, UOAK_RETRY_DELAY); /* issue request */ @@ -96,8 +96,8 @@ uoak_get_cmd(struct uoak_softc *sc) return EIO; /* wait till the device ready to return the request */ - while (uoak_check_device_ready(sc) < 0) - usbd_delay_ms(sc->sc_udev, UOAK_RESPONSE_DELAY); + while (uoak_check_device_ready(sc) < 0) + usbd_delay_ms(sc->sc_udev, UOAK_RESPONSE_DELAY); return 0; } @@ -118,7 +118,7 @@ uoak_get_device_name(struct uoak_softc *sc, enum uoak_target target) if (uoak_get_cmd(sc) < 0) return EIO; - strlcpy(sc->sc_config[target].devname, sc->sc_buf+1, + strlcpy(sc->sc_config[target].devname, sc->sc_buf+1, sizeof(sc->sc_config[target].devname)); return 0; } @@ -268,7 +268,7 @@ uoak_print_setting(struct uoak_softc *sc, enum uoak_target target) printf(" reports changes"); break; case OAK_REPORTMODE_FIXEDRATE: - printf(" rate %dms", + printf(" rate %dms", sc->sc_config[target].report_rate); break; default: diff --git a/sys/dev/usb/uoaklux.c b/sys/dev/usb/uoaklux.c index fee39e268..597b3e23e 100644 --- a/sys/dev/usb/uoaklux.c +++ b/sys/dev/usb/uoaklux.c @@ -172,7 +172,7 @@ uoaklux_attach(struct device *parent, struct device *self, void *aux) uoak_sensor_attach(scc, &sc->sc_sensor.lux, SENSOR_LUX); /* start sensor */ - sc->sc_sensortask = sensor_task_register(sc, uoaklux_refresh, + sc->sc_sensortask = sensor_task_register(sc, uoaklux_refresh, UOAKLUX_REFRESH_PERIOD); if (sc->sc_sensortask == NULL) { printf(", unable to register update task\n"); @@ -244,9 +244,9 @@ uoaklux_refresh(void *arg) /* blink LED for each cycle */ if (uoak_led_status(scc, OAK_TARGET_RAM, &led) < 0) DPRINTF(("status query error\n")); - if (led == OAK_LED_OFF) + if (led == OAK_LED_OFF) (void)uoak_led_ctrl(scc, OAK_TARGET_RAM, OAK_LED_ON); - else + else (void)uoak_led_ctrl(scc, OAK_TARGET_RAM, OAK_LED_OFF); uoak_sensor_refresh(&sc->sc_sensor.lux, 1000000, 0); diff --git a/sys/dev/usb/uoakrh.c b/sys/dev/usb/uoakrh.c index 4d8b253d6..14206daa2 100644 --- a/sys/dev/usb/uoakrh.c +++ b/sys/dev/usb/uoakrh.c @@ -186,7 +186,7 @@ uoakrh_attach(struct device *parent, struct device *self, void *aux) sensor_attach(&sc->sc_sensordev, &sc->sc_sensor.humi); /* start sensor */ - sc->sc_sensortask = sensor_task_register(sc, uoakrh_refresh, + sc->sc_sensortask = sensor_task_register(sc, uoakrh_refresh, UOAKRH_REFRESH_PERIOD); if (sc->sc_sensortask == NULL) { printf(", unable to register update task\n"); @@ -248,7 +248,7 @@ uoakrh_intr(struct uhidev *addr, void *ibuf, u_int len) humi = (scc->sc_ibuf[3] << 8) + (scc->sc_ibuf[2]); temp = (scc->sc_ibuf[5] << 8) + (scc->sc_ibuf[4]); - if (s->count == 0) { + if (s->count == 0) { s->tempval = temp; s->humival = humi; } @@ -271,9 +271,9 @@ uoakrh_refresh(void *arg) /* blink LED for each cycle */ if (uoak_led_status(scc, OAK_TARGET_RAM, &led) < 0) DPRINTF(("status query error\n")); - if (led == OAK_LED_OFF) + if (led == OAK_LED_OFF) (void)uoak_led_ctrl(scc, OAK_TARGET_RAM, OAK_LED_ON); - else + else (void)uoak_led_ctrl(scc, OAK_TARGET_RAM, OAK_LED_OFF); /* update sensor value */ diff --git a/sys/dev/usb/uow.c b/sys/dev/usb/uow.c index 299429170..fdb267eeb 100644 --- a/sys/dev/usb/uow.c +++ b/sys/dev/usb/uow.c @@ -54,21 +54,21 @@ struct uow_softc { u_int8_t sc_fifo[DS2490_DATAFIFOSIZE]; }; -int uow_match(struct device *, void *, void *); -void uow_attach(struct device *, struct device *, void *); -int uow_detach(struct device *, int); -int uow_activate(struct device *, int); +int uow_match(struct device *, void *, void *); +void uow_attach(struct device *, struct device *, void *); +int uow_detach(struct device *, int); +int uow_activate(struct device *, int); -struct cfdriver uow_cd = { - NULL, "uow", DV_DULL -}; +struct cfdriver uow_cd = { + NULL, "uow", DV_DULL +}; -const struct cfattach uow_ca = { - sizeof(struct uow_softc), - uow_match, - uow_attach, - uow_detach, - uow_activate, +const struct cfattach uow_ca = { + sizeof(struct uow_softc), + uow_match, + uow_attach, + uow_detach, + uow_activate, }; /* List of supported devices */ diff --git a/sys/dev/usb/usb.h b/sys/dev/usb/usb.h index 82d36deb8..859f47c67 100644 --- a/sys/dev/usb/usb.h +++ b/sys/dev/usb/usb.h @@ -576,7 +576,7 @@ typedef struct usb_port_status usb_port_status_t; #define UICLASS_VIDEO 0x0e #define UISUBCLASS_VIDEOCONTROL 1 #define UISUBCLASS_VIDEOSTREAM 2 -#define UISUBCLASS_VIDEO_IF_COLLECTION 3 +#define UISUBCLASS_VIDEO_IF_COLLECTION 3 #define UICLASS_DIAGNOSTIC 0xdc diff --git a/sys/dev/usb/usb_quirks.c b/sys/dev/usb/usb_quirks.c index be65ad086..4574e736f 100644 --- a/sys/dev/usb/usb_quirks.c +++ b/sys/dev/usb/usb_quirks.c @@ -196,7 +196,7 @@ usbd_find_quirk(usb_device_descriptor_t *d) vendor, product, UGETW(d->bcdDevice), t->quirks.uq_flags); #endif - + return (&t->quirks); } } @@ -210,7 +210,7 @@ usbd_find_quirk(usb_device_descriptor_t *d) #ifdef USB_DEBUG if (usbdebug && td->quirks.uq_flags) printf("usbd_find_quirk for device class 0x%02x/0x%02x/%x: %d\n", - d->bDeviceClass, d->bDeviceSubClass, + d->bDeviceClass, d->bDeviceSubClass, UGETW(d->bcdDevice), td->quirks.uq_flags); #endif diff --git a/sys/dev/usb/usb_subr.c b/sys/dev/usb/usb_subr.c index 4e8502d0a..3aaa6ab6b 100644 --- a/sys/dev/usb/usb_subr.c +++ b/sys/dev/usb/usb_subr.c @@ -1097,7 +1097,7 @@ usbd_new_device(struct device *parent, struct usbd_bus *bus, int depth, dd = &dev->ddesc; /* Try to get device descriptor */ - /* + /* * some device will need small size query at first (XXX: out of spec) * we will get full size descriptor later, just determine the maximum * packet size of the control pipe at this moment. @@ -1120,7 +1120,7 @@ usbd_new_device(struct device *parent, struct usbd_bus *bus, int depth, USB_DEVICE_DESCRIPTOR_SIZE); usbd_reset_port(up->parent, port); for (i = 0; i < 3; i++) { - err = usbd_get_desc(dev, UDESC_DEVICE, 0, + err = usbd_get_desc(dev, UDESC_DEVICE, 0, USB_DEVICE_DESCRIPTOR_SIZE, dd); if (!err) break; @@ -1135,7 +1135,7 @@ usbd_new_device(struct device *parent, struct usbd_bus *bus, int depth, USETW(dev->def_ep_desc.wMaxPacketSize, USB_MAX_IPACKET); usbd_reset_port(up->parent, port); usbd_delay_ms(dev, 500); - err = usbd_get_desc(dev, UDESC_DEVICE, 0, + err = usbd_get_desc(dev, UDESC_DEVICE, 0, USB_MAX_IPACKET, dd); } diff --git a/sys/dev/usb/usbdevs b/sys/dev/usb/usbdevs index f260a9219..cb387497e 100644 --- a/sys/dev/usb/usbdevs +++ b/sys/dev/usb/usbdevs @@ -854,7 +854,7 @@ product AGFA SNAPSCANE20 0x2091 SnapScan e20 product AGFA SNAPSCANE25 0x2095 SnapScan e25 product AGFA SNAPSCANE26 0x2097 SnapScan e26 product AGFA SNAPSCANE52 0x20fd SnapScan e52 - + /* Aincomm products */ product AINCOMM AWU2000B 0x1001 AWU2000B @@ -1003,7 +1003,7 @@ product APPLE WELLSPRING9_JIS 0x0274 Keyboard/Trackpad product APPLE WELLSPRING8_ANSI 0x0290 Keyboard/Trackpad product APPLE WELLSPRING8_ISO 0x0291 Keyboard/Trackpad product APPLE WELLSPRING8_JIS 0x0292 Keyboard/Trackpad -product APPLE WELLSPRINGM1_J293 0x0341 Keyboard/Trackpad +product APPLE WELLSPRINGM1_J293 0x0341 Keyboard/Trackpad product APPLE OPTMOUSE 0x0302 Optical mouse product APPLE BLUETOOTH_HCI 0x1000 HID-proxy product APPLE SPEAKERS 0x1101 Speakers @@ -1532,7 +1532,7 @@ product DELL TM1180 0x8100 TrueMobile 1180 WLAN product DELL PRISM_GT_1 0x8102 PrismGT USB 2.0 WLAN product DELL BLUETOOTH350 0x8103 Bluetooth product DELL PRISM_GT_2 0x8104 PrismGT USB 2.0 WLAN -product DELL W5500 0x8115 W5500 HSDPA +product DELL W5500 0x8115 W5500 HSDPA product DELL U740 0x8135 U740 CDMA product DELL EU870D 0x8138 EU870D HSDPA product DELL DW5821E 0x81d7 DW5821e LTE @@ -2034,7 +2034,7 @@ product FTDI CCS_MACHX 0xf9d2 MACH-X product FTDI CCS_LOAD_N_GO 0xf9d3 LOAD N GO product FTDI CCS_ICDU64 0xf9d4 ICDU64 product FTDI CCS_PRIME8 0xf9d5 PRIME8 -product FTDI ITM_TOUCH 0xf9e9 ITM Touchscreen +product FTDI ITM_TOUCH 0xf9e9 ITM Touchscreen product FTDI USBSERIAL 0xfa00 Matrix Orbital USB Serial product FTDI LCD_MX200 0xfa01 Matrix Orbital MX200 Series LCD product FTDI LCD_MTXO 0xfa02 Matrix Orbital LCD @@ -2111,7 +2111,7 @@ product GARMIN DAKOTA20 0x23c0 Dakota 20 product GARMIN GPSMAP62S 0x2459 GPSmap 62s /* GCT Semiconductor products */ -product GCTSEMICON INSTALL 0x7f40 GDM720x MASS storage mode +product GCTSEMICON INSTALL 0x7f40 GDM720x MASS storage mode /* Gear Head products */ product GEARHEAD GHKB 0x0003 Gear Head Keyboard @@ -2340,7 +2340,7 @@ product HYUNDAI UM175 0x3714 UM175 EVDO /* IBM Corporation */ product IBM OPTTRAVELMOUSE 0x3107 Optical product IBM OPTWHEELMOUSE 0x310b Wheel -product IBM USBCDROMDRIVE 0x4427 CD-ROM +product IBM USBCDROMDRIVE 0x4427 CD-ROM product IBM THINKPADHUB 0x4484 Hub /* Icom, Inc. */ @@ -3852,7 +3852,7 @@ product ROLAND PC300 0x0008 PC-300 MIDI Keyboard product ROLAND UM1 0x0009 UM-1 MIDI I/F product ROLAND SK500 0x000b SK-500 MIDI Keyboard product ROLAND SCD70 0x000c SC-D70 MIDI Synth -product ROLAND UM880N 0x0014 UM-880 MIDI I/F +product ROLAND UM880N 0x0014 UM-880 MIDI I/F product ROLAND SD90 0x0016 SD-90 MIDI Synth product ROLAND UM550 0x0023 UM-550 MIDI I/F product ROLAND SD20 0x0027 SD-20 MIDI Synth @@ -4460,7 +4460,7 @@ product TORADEX MAGR 0x000b Toradex OAK MAGR sensor product TORADEX RELAY 0x000d Toradex OAK RELAY product TORADEX 10V 0x000e Toradex OAK 10V sensor product TORADEX LN 0x000f Toradex OAK LN sensor -product TORADEX IO 0x0010 Toradex OAK IO +product TORADEX IO 0x0010 Toradex OAK IO product TORADEX ORIENT 0x0015 Toradex ORIENT Tilt sensor /* Toshiba Corp products */ @@ -4738,9 +4738,9 @@ product ZTE CDMA_MSM 0x0001 CDMA Technologies MSM modem product ZTE MF633 0x0016 ZTE MF633 USUPA USB modem product ZTE MF637 0x0031 ZTE MF637 HSUPA USB modem product ZTE K3565Z 0x0063 ZTE K3565-Z USB MSM modem -product ZTE UMASS_INSTALLER4 0x0083 ZTE USB MSM installer +product ZTE UMASS_INSTALLER4 0x0083 ZTE USB MSM installer product ZTE MSA110UP 0x0091 ONDA MSA110UP USB MSM modem -product ZTE UMASS_INSTALLER2 0x0103 ZTE USB MSM installer +product ZTE UMASS_INSTALLER2 0x0103 ZTE USB MSM installer product ZTE MF112 0x0117 ZTE MF112 HSUPA USB modem product ZTE HSUSB 0x1364 ZTE HSUSB product ZTE UMASS_INSTALLER 0x2000 ZTE USB MSM installer diff --git a/sys/dev/usb/uscom.c b/sys/dev/usb/uscom.c index fc2c06a74..801aeb498 100644 --- a/sys/dev/usb/uscom.c +++ b/sys/dev/usb/uscom.c @@ -140,7 +140,7 @@ uscom_attach(struct device *parent, struct device *self, void *aux) uca.methods = &uscom_methods; uca.arg = sc; uca.info = NULL; - + sc->sc_subdev = config_found_sm(self, &uca, ucomprint, ucomsubmatch); } diff --git a/sys/dev/usb/uslcom.c b/sys/dev/usb/uslcom.c index 5a14e9ef0..7e2f4a824 100644 --- a/sys/dev/usb/uslcom.c +++ b/sys/dev/usb/uslcom.c @@ -55,7 +55,7 @@ int uslcomdebug = 0; #define USLCOM_UART_DISABLE 0x00 #define USLCOM_UART_ENABLE 0x01 -#define USLCOM_CTRL_DTR_ON 0x0001 +#define USLCOM_CTRL_DTR_ON 0x0001 #define USLCOM_CTRL_DTR_SET 0x0100 #define USLCOM_CTRL_RTS_ON 0x0002 #define USLCOM_CTRL_RTS_SET 0x0200 @@ -505,7 +505,7 @@ void uslcom_get_status(void *vsc, int portno, u_char *lsr, u_char *msr) { struct uslcom_softc *sc = vsc; - + if (msr != NULL) *msr = sc->sc_msr; if (lsr != NULL) @@ -517,7 +517,7 @@ uslcom_break(void *vsc, int portno, int onoff) { struct uslcom_softc *sc = vsc; usb_device_request_t req; - int brk = onoff ? USLCOM_BREAK_ON : USLCOM_BREAK_OFF; + int brk = onoff ? USLCOM_BREAK_ON : USLCOM_BREAK_OFF; req.bmRequestType = USLCOM_WRITE; req.bRequest = USLCOM_BREAK; diff --git a/sys/dev/usb/usps.c b/sys/dev/usb/usps.c index 12cde0936..d275e0657 100644 --- a/sys/dev/usb/usps.c +++ b/sys/dev/usb/usps.c @@ -70,7 +70,7 @@ struct usps_softc { struct device sc_dev; struct usbd_device *sc_udev; struct usbd_interface *sc_iface; - struct usbd_pipe *sc_ipipe; + struct usbd_pipe *sc_ipipe; int sc_isize; struct usbd_xfer *sc_xfer; uint8_t sc_buf[16]; @@ -212,7 +212,7 @@ usps_attach(struct device *parent, struct device *self, void *aux) strlcpy(sc->sc_serial_sensor.desc, "unit serial#", sizeof(sc->sc_serial_sensor.desc)); - /* + /* * XXX: the device has mode of par port sensor, Watt of Ampair. * currently only watt mode is selected. */ @@ -255,7 +255,7 @@ usps_attach(struct device *parent, struct device *self, void *aux) goto fail; } - printf("%s: device#=%d, firmware version=V%02dL%02d\n", + printf("%s: device#=%d, firmware version=V%02dL%02d\n", sc->sc_dev.dv_xname, sc->sc_device_serial, sc->sc_firmware_version[0], sc->sc_firmware_version[1]); @@ -264,9 +264,9 @@ usps_attach(struct device *parent, struct device *self, void *aux) /* open interrupt endpoint */ sc->sc_intrbuf = malloc(sc->sc_isize, M_USBDEV, M_WAITOK); - if (sc->sc_intrbuf == NULL) + if (sc->sc_intrbuf == NULL) goto fail; - err = usbd_open_pipe_intr(sc->sc_iface, ep_intr, + err = usbd_open_pipe_intr(sc->sc_iface, ep_intr, USBD_SHORT_XFER_OK, &sc->sc_ipipe, sc, sc->sc_intrbuf, sc->sc_isize, usps_intr, USPS_INTR_TICKS); if (err) { @@ -401,7 +401,7 @@ usps_intr(struct usbd_xfer *xfer, void *priv, usbd_status status) } /* process intr packet */ - if (sc->sc_intrbuf == NULL) + if (sc->sc_intrbuf == NULL) return; pkt = (struct usps_port_pkt *)sc->sc_intrbuf; @@ -409,7 +409,7 @@ usps_intr(struct usbd_xfer *xfer, void *priv, usbd_status status) total = 0; for (i = 0; i < FX5204_NUM_PORTS; i++) { ps = &sc->sc_port_sensor[i]; - if (sc->sc_count == 0) + if (sc->sc_count == 0) ps->vmax = ps->vmin = pkt->port[i]; if (pkt->port[i] > ps->vmax) ps->vmax = pkt->port[i]; @@ -440,7 +440,7 @@ usps_get_device_info(struct usps_softc *sc) /* get Firmware version */ usps_cmd(sc, USPS_CMD_GET_FIRMWARE, 0, 2); - sc->sc_firmware_version[0] = + sc->sc_firmware_version[0] = (sc->sc_buf[0]>>4) * 10 + (sc->sc_buf[0] & 0xf); sc->sc_firmware_version[1] = (sc->sc_buf[1]>>4) * 10 + (sc->sc_buf[1] & 0xf); diff --git a/sys/dev/usb/utvfu.c b/sys/dev/usb/utvfu.c index e6807f992..34844e6b6 100644 --- a/sys/dev/usb/utvfu.c +++ b/sys/dev/usb/utvfu.c @@ -1561,11 +1561,11 @@ utvfu_vs_alloc_isoc(struct utvfu_softc *sc) for (i = 0; i < UTVFU_ISOC_TRANSFERS; i++) { sc->sc_iface.ixfer[i].sc = sc; - sc->sc_iface.ixfer[i].xfer = usbd_alloc_xfer(sc->sc_udev); + sc->sc_iface.ixfer[i].xfer = usbd_alloc_xfer(sc->sc_udev); if (sc->sc_iface.ixfer[i].xfer == NULL) { printf("%s: could not allocate isoc VS xfer!\n", DEVNAME(sc)); - return (USBD_NOMEM); + return (USBD_NOMEM); } size = sc->sc_iface.psize * sc->sc_nframes; @@ -1659,7 +1659,7 @@ utvfu_reqbufs(void *v, struct v4l2_requestbuffers *rb) else sc->sc_mmap_count = rb->count; - /* allocate the total mmap buffer */ + /* allocate the total mmap buffer */ sc->sc_mmap_bufsz = sc->sc_max_frame_sz; if (INT_MAX / sc->sc_mmap_count < sc->sc_max_frame_sz) /* overflow */ return (ENOMEM); diff --git a/sys/dev/usb/utvfu.h b/sys/dev/usb/utvfu.h index b623f0fab..c17dc98f8 100644 --- a/sys/dev/usb/utvfu.h +++ b/sys/dev/usb/utvfu.h @@ -98,7 +98,7 @@ struct utvfu_frame_buf { uint off; uint size; uint16_t chunks_done; - uint8_t fid; + uint8_t fid; uint8_t last_odd; uint8_t *buf; }; diff --git a/sys/dev/usb/uvideo.c b/sys/dev/usb/uvideo.c index 7769034d8..b92955704 100644 --- a/sys/dev/usb/uvideo.c +++ b/sys/dev/usb/uvideo.c @@ -171,7 +171,7 @@ void uvideo_vs_start_isoc_ixfer(struct uvideo_softc *, void uvideo_vs_cb(struct usbd_xfer *, void *, usbd_status); usbd_status uvideo_vs_decode_stream_header(struct uvideo_softc *, - uint8_t *, int); + uint8_t *, int); usbd_status uvideo_vs_decode_stream_header_isight(struct uvideo_softc *, uint8_t *, int); int uvideo_mmap_queue(struct uvideo_softc *, uint8_t *, int); @@ -709,7 +709,7 @@ uvideo_vc_parse_desc_header(struct uvideo_softc *sc, DEVNAME(sc)); return (USBD_INVAL); } - + sc->sc_desc_vc_header.fix = d; sc->sc_desc_vc_header.baInterfaceNr = (uByte *)(d + 1); if (UGETW(d->bcdUVC) < 0x0110) @@ -818,7 +818,7 @@ uvideo_find_ctrl(struct uvideo_softc *sc, int id) if (uvideo_has_ctrl(sc->sc_desc_vc_pu[j], uvideo_ctrls[i].ctrl_bit) != 0) { found = 1; - break; + break; } } if (found == 0) { @@ -1146,7 +1146,7 @@ usbd_status uvideo_vs_parse_desc_frame_sub(struct uvideo_softc *sc, const usb_descriptor_t *desc) { - struct usb_video_frame_desc *fd = + struct usb_video_frame_desc *fd = (struct usb_video_frame_desc *)(uint8_t *)desc; int fmtidx, frame_num; uint32_t fbuf_size; @@ -1368,7 +1368,7 @@ next: * off_num_elements: offset which tells the number of following elements * size_element: size of a single element * off_size_element: if size_element is 0 the element size is taken from - * this offset in the descriptor + * this offset in the descriptor */ int uvideo_desc_len(const usb_descriptor_t *desc, @@ -1583,7 +1583,7 @@ uvideo_vs_negotiation(struct uvideo_softc *sc, int commit) UGETW(hd->bcdUVC) < 0x0110 ) { DPRINTF(1, "%s: dwMaxVideoFrameSize == 0, fixed\n", DEVNAME(sc)); - USETDW(pc->dwMaxVideoFrameSize, + USETDW(pc->dwMaxVideoFrameSize, UGETDW(frame->dwMaxVideoFrameBufferSize)); } } @@ -1785,11 +1785,11 @@ uvideo_vs_alloc_isoc(struct uvideo_softc *sc) for (i = 0; i < UVIDEO_IXFERS; i++) { sc->sc_vs_cur->ixfer[i].sc = sc; - sc->sc_vs_cur->ixfer[i].xfer = usbd_alloc_xfer(sc->sc_udev); + sc->sc_vs_cur->ixfer[i].xfer = usbd_alloc_xfer(sc->sc_udev); if (sc->sc_vs_cur->ixfer[i].xfer == NULL) { printf("%s: could not allocate isoc VS xfer!\n", DEVNAME(sc)); - return (USBD_NOMEM); + return (USBD_NOMEM); } size = sc->sc_vs_cur->psize * sc->sc_nframes; @@ -2498,7 +2498,7 @@ uvideo_dump_desc_all(struct uvideo_softc *sc) printf("\n"); desc = usbd_desc_iter_next(&iter); - } + } } @@ -3262,7 +3262,7 @@ uvideo_reqbufs(void *v, struct v4l2_requestbuffers *rb) else sc->sc_mmap_count = rb->count; - /* allocate the total mmap buffer */ + /* allocate the total mmap buffer */ buf_size = UGETDW(sc->sc_desc_probe.dwMaxVideoFrameSize); if (buf_size >= SIZE_MAX / UVIDEO_MAX_BUFFERS) { printf("%s: video frame size too large!\n", DEVNAME(sc)); diff --git a/sys/dev/usb/uvisor.c b/sys/dev/usb/uvisor.c index c3ed21fcf..a7e48dc04 100644 --- a/sys/dev/usb/uvisor.c +++ b/sys/dev/usb/uvisor.c @@ -127,7 +127,7 @@ struct uvisor_softc { struct device sc_dev; /* base device */ struct usbd_device *sc_udev; /* device */ struct usbd_interface *sc_iface; /* interface */ -/* +/* * added sc_vendor for later interrogation in failed initialisations */ int sc_vendor; /* USB device vendor */ @@ -158,7 +158,7 @@ const struct ucom_methods uvisor_methods = { struct uvisor_type { struct usb_devno uv_dev; - u_int16_t uv_flags; + u_int16_t uv_flags; #define PALM4 0x0001 #define VISOR 0x0002 #define NOFRE 0x0004 @@ -244,9 +244,9 @@ uvisor_attach(struct device *parent, struct device *self, void *aux) sc->sc_flags = uvisor_lookup(uaa->vendor, uaa->product)->uv_flags; sc->sc_vendor = uaa->vendor; - + if ((sc->sc_flags & (VISOR | PALM4)) == 0) { - printf("%s: device is neither visor nor palm\n", + printf("%s: device is neither visor nor palm\n", sc->sc_dev.dv_xname); goto bad; } @@ -406,7 +406,7 @@ uvisor_init(struct uvisor_softc *sc, struct uvisor_connection_info *ci, if (err) return (err); } - + if (sc->sc_flags & VISOR) { DPRINTF(("uvisor_init: getting Visor connection info\n")); req.bmRequestType = UT_READ_VENDOR_ENDPOINT; @@ -419,10 +419,10 @@ uvisor_init(struct uvisor_softc *sc, struct uvisor_connection_info *ci, if (err) return (err); } - + if (sc->sc_flags & NOFRE) return (err); - + DPRINTF(("uvisor_init: getting available bytes\n")); req.bmRequestType = UT_READ_VENDOR_ENDPOINT; req.bRequest = UVISOR_REQUEST_BYTES_AVAILABLE; diff --git a/sys/dev/usb/uxrcom.c b/sys/dev/usb/uxrcom.c index 70d07bb3c..5d9868ee8 100644 --- a/sys/dev/usb/uxrcom.c +++ b/sys/dev/usb/uxrcom.c @@ -411,7 +411,7 @@ void uxrcom_get_status(void *vsc, int portno, u_char *lsr, u_char *msr) { struct uxrcom_softc *sc = vsc; - + if (msr != NULL) *msr = sc->sc_msr; if (lsr != NULL) diff --git a/sys/dev/videomode/devlist2h.awk b/sys/dev/videomode/devlist2h.awk index 6f25c732c..d2c71b424 100644 --- a/sys/dev/videomode/devlist2h.awk +++ b/sys/dev/videomode/devlist2h.awk @@ -108,7 +108,7 @@ NF > 0 && $1 == "product" { products[nproducts, 2], products[nproducts, 3]) > hfile i = 4; f = 5; - + ocomment = oparen = 0 if (f <= NF) { printf("\t\t/* ") > hfile diff --git a/sys/dev/videomode/edid.c b/sys/dev/videomode/edid.c index 2149bf5fb..015f764af 100644 --- a/sys/dev/videomode/edid.c +++ b/sys/dev/videomode/edid.c @@ -29,7 +29,7 @@ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ + */ #include #include @@ -136,15 +136,15 @@ edid_is_valid(uint8_t *d) { int sum = 0, i; uint8_t sig[8] = EDID_SIGNATURE; - + if (memcmp(d, sig, 8) != 0) return EINVAL; - + for (i = 0; i < 128; i++) sum += d[i]; if ((sum & 0xff) != 0) return EINVAL; - + return 0; } @@ -363,7 +363,7 @@ edid_det_timing(uint8_t *data, struct videomode *vmp) vblank = EDID_DET_TIMING_VBLANK(data); vsyncwid = EDID_DET_TIMING_VSYNC_WIDTH(data); vsyncoff = EDID_DET_TIMING_VSYNC_OFFSET(data); - + /* XXX: I'm not doing anything with the borders, should I? */ vmp->hdisplay = hactive; @@ -406,7 +406,7 @@ edid_block(struct edid_info *edid, uint8_t *data) edid->edid_preferred_mode = &edid->edid_modes[edid->edid_nmodes]; } - edid->edid_nmodes++; + edid->edid_nmodes++; } return; } @@ -428,13 +428,13 @@ edid_block(struct edid_info *edid, uint8_t *data) case EDID_DESC_BLOCK_TYPE_RANGE: edid->edid_have_range = 1; - edid->edid_range.er_min_vfreq = + edid->edid_range.er_min_vfreq = EDID_DESC_RANGE_MIN_VFREQ(data); - edid->edid_range.er_max_vfreq = + edid->edid_range.er_max_vfreq = EDID_DESC_RANGE_MAX_VFREQ(data); - edid->edid_range.er_min_hfreq = + edid->edid_range.er_min_hfreq = EDID_DESC_RANGE_MIN_HFREQ(data); - edid->edid_range.er_max_hfreq = + edid->edid_range.er_max_hfreq = EDID_DESC_RANGE_MAX_HFREQ(data); edid->edid_range.er_max_clock = EDID_DESC_RANGE_MAX_CLOCK(data); @@ -500,7 +500,7 @@ edid_parse(uint8_t *data, struct edid_info *edid) edid->edid_vendor[2] = EDID_MANFID_2(manfid); edid->edid_vendor[3] = 0; /* null terminate for convenience */ - edid->edid_product = data[EDID_OFFSET_PRODUCT_ID] + + edid->edid_product = data[EDID_OFFSET_PRODUCT_ID] + (data[EDID_OFFSET_PRODUCT_ID + 1] << 8); name = edid_findvendor(edid->edid_vendor); diff --git a/sys/dev/videomode/ediddevs b/sys/dev/videomode/ediddevs index 81eeb8214..e094661ec 100644 --- a/sys/dev/videomode/ediddevs +++ b/sys/dev/videomode/ediddevs @@ -29,7 +29,7 @@ $OpenBSD: ediddevs,v 1.1 2009/10/08 20:35:44 matthieu Exp $ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ + */ /* * Use "make -f Makefile.ediddevs" to regenerate ediddevs.h and ediddevs_data.h diff --git a/sys/dev/videomode/edidreg.h b/sys/dev/videomode/edidreg.h index 473c728e8..260e6a10d 100644 --- a/sys/dev/videomode/edidreg.h +++ b/sys/dev/videomode/edidreg.h @@ -29,7 +29,7 @@ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ + */ #ifndef _DEV_VIDEOMODE_EDIDREG_H #define _DEV_VIDEOMODE_EDIDREG_H diff --git a/sys/dev/videomode/edidvar.h b/sys/dev/videomode/edidvar.h index caf044cb6..2d7b5e43d 100644 --- a/sys/dev/videomode/edidvar.h +++ b/sys/dev/videomode/edidvar.h @@ -29,7 +29,7 @@ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ + */ #ifndef _DEV_VIDEOMODE_EDIDVAR_H #define _DEV_VIDEOMODE_EDIDVAR_H diff --git a/sys/dev/videomode/modelines b/sys/dev/videomode/modelines index 23b51eced..f3669eed9 100644 --- a/sys/dev/videomode/modelines +++ b/sys/dev/videomode/modelines @@ -171,4 +171,4 @@ Modeline "2048x1536" 388.04 2048 2216 2440 2832 1536 1537 1540 1612 -hsync +vs ModeLine "1152x900" 94.50 1152 1192 1320 1528 900 902 906 937 -hsync -vsync # 1152x900 @ 76Hz -ModeLine "1152x900" 105.56 1152 1168 1280 1472 900 902 906 943 -hsync -vsync +ModeLine "1152x900" 105.56 1152 1168 1280 1472 900 902 906 943 -hsync -vsync diff --git a/sys/dev/videomode/modelines2c.awk b/sys/dev/videomode/modelines2c.awk index 424610cea..3b812b926 100644 --- a/sys/dev/videomode/modelines2c.awk +++ b/sys/dev/videomode/modelines2c.awk @@ -79,7 +79,7 @@ NR == 1 { hsyncstart = $5; hsyncend = $6; htotal = $7; - + vdisplay = $8; vsyncstart = $9; vsyncend = $10; @@ -140,7 +140,7 @@ END { for ( i = 0; i < nmodes; i++ ) { - print dmodes[i]; + print dmodes[i]; } printf("};\n\n"); diff --git a/sys/dev/videomode/vesagtf.c b/sys/dev/videomode/vesagtf.c index 5c8a08f83..24ecaf22f 100644 --- a/sys/dev/videomode/vesagtf.c +++ b/sys/dev/videomode/vesagtf.c @@ -29,11 +29,11 @@ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ + */ /* * This was derived from a userland GTF program supplied by NVIDIA. - * NVIDIA's original boilerplate follows. + * NVIDIA's original boilerplate follows. * * Note that I have heavily modified the program for use in the EDID * kernel code for NetBSD, including removing the use of floating @@ -50,11 +50,11 @@ /* * Copyright (c) 2001, Andy Ritger aritger@nvidia.com * All rights reserved. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: - * + * * o Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * o Redistributions in binary form must reproduce the above copyright @@ -79,7 +79,7 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - * + * * * This program is based on the Generalized Timing Formula(GTF TM) * Standard Version: 1.0, Revision: 1.0 @@ -98,7 +98,7 @@ * of suitability for any purpose. The sample code contained within * this standard may be used without restriction. * - * + * * * The GTF EXCEL(TM) SPREADSHEET, a sample (and the definitive) * implementation of the GTF Timing Standard, is available at: @@ -123,12 +123,12 @@ * any experience with this, and 2) neither XFree86 modelines nor * fbset fb.modes provide an obvious way for margin timings to be * included in their mode descriptions (needs more investigation). - * + * * The GTF provides for computation of interlaced mode timings; * I've implemented the computations but not enabled them, yet. * I should probably enable and test this at some point. * - * + * * * TODO: * @@ -141,7 +141,7 @@ * o It would be nice if this were more general purpose to do things * outside the scope of the GTF: like generate double scan mode * timings, for example. - * + * * o Printing digits to the right of the decimal point when the * digits are 0 annoys me. * @@ -242,7 +242,7 @@ vesagtf_mode_params(unsigned h_pixels, unsigned v_lines, unsigned freq, #ifdef GTFDEBUG unsigned h_freq; #endif - + /* 1. In order to give correct results, the number of horizontal * pixels requested is first processed to ensure that it is divisible * by the character size, by rounding it to the nearest character @@ -250,26 +250,26 @@ vesagtf_mode_params(unsigned h_pixels, unsigned v_lines, unsigned freq, * * [H PIXELS RND] = ((ROUND([H PIXELS]/[CELL GRAN RND],0))*[CELLGRAN RND]) */ - + h_pixels = DIVIDE(h_pixels, CELL_GRAN) * CELL_GRAN; - + print_value(1, "[H PIXELS RND]", h_pixels); - + /* 2. If interlace is requested, the number of vertical lines assumed * by the calculation must be halved, as the computation calculates * the number of vertical lines per field. In either case, the * number of lines is rounded to the nearest integer. - * + * * [V LINES RND] = IF([INT RQD?]="y", ROUND([V LINES]/2,0), * ROUND([V LINES],0)) */ v_lines = (flags & VESAGTF_FLAG_ILACE) ? DIVIDE(v_lines, 2) : v_lines; - + print_value(2, "[V LINES RND]", v_lines); - - + + /* 3. Find the frame rate required: * * [V FIELD RATE RQD] = IF([INT RQD?]="y", [I/P FREQ RQD]*2, @@ -279,7 +279,7 @@ vesagtf_mode_params(unsigned h_pixels, unsigned v_lines, unsigned freq, v_field_rqd = (flags & VESAGTF_FLAG_ILACE) ? (freq * 2) : (freq); print_value(3, "[V FIELD RATE RQD]", v_field_rqd); - + /* 4. Find number of lines in Top margin: * 5. Find number of lines in Bottom margin: @@ -298,9 +298,9 @@ vesagtf_mode_params(unsigned h_pixels, unsigned v_lines, unsigned freq, print_value(4, "[TOP MARGIN (LINES)]", top_margin); print_value(5, "[BOT MARGIN (LINES)]", bottom_margin); - + /* 6. If interlace is required, then set variable [INTERLACE]=0.5: - * + * * [INTERLACE]=(IF([INT RQD?]="y",0.5,0)) * * To make this integer friendly, we use some special hacks in step @@ -310,7 +310,7 @@ vesagtf_mode_params(unsigned h_pixels, unsigned v_lines, unsigned freq, interlace = (flags & VESAGTF_FLAG_ILACE) ? 1 : 0; print_value(6, "[2*INTERLACE]", interlace); - + /* 7. Estimate the Horizontal period * @@ -346,7 +346,7 @@ vesagtf_mode_params(unsigned h_pixels, unsigned v_lines, unsigned freq, ((2 * (v_lines + (2 * top_margin) + params->min_porch)) + interlace)); print_value(7, "[H PERIOD EST (ps)]", h_period_est); - + /* 8. Find the number of lines in V sync + back porch: * @@ -358,19 +358,19 @@ vesagtf_mode_params(unsigned h_pixels, unsigned v_lines, unsigned freq, vsync_plus_bp = DIVIDE(params->min_vsbp * 1000000, h_period_est); print_value(8, "[V SYNC+BP]", vsync_plus_bp); - - + + /* 9. Find the number of lines in V back porch alone: * * [V BACK PORCH] = [V SYNC+BP] - [V SYNC RND] * * XXX is "[V SYNC RND]" a typo? should be [V SYNC RQD]? */ - + v_back_porch = vsync_plus_bp - params->vsync_rqd; - + print_value(9, "[V BACK PORCH]", v_back_porch); - + /* 10. Find the total number of lines in Vertical field period: * @@ -381,9 +381,9 @@ vesagtf_mode_params(unsigned h_pixels, unsigned v_lines, unsigned freq, total_v_lines = v_lines + top_margin + bottom_margin + vsync_plus_bp + interlace + params->min_porch; - + print_value(10, "[TOTAL V LINES]", total_v_lines); - + /* 11. Estimate the Vertical field frequency: * @@ -401,9 +401,9 @@ vesagtf_mode_params(unsigned h_pixels, unsigned v_lines, unsigned freq, */ v_field_est = DIVIDE(DIVIDE(1000000000000000ULL, h_period_est), total_v_lines); - + print_value(11, "[V FIELD RATE EST(uHz)]", v_field_est); - + /* 12. Find the actual horizontal period: * @@ -411,9 +411,9 @@ vesagtf_mode_params(unsigned h_pixels, unsigned v_lines, unsigned freq, */ h_period = DIVIDE(h_period_est * v_field_est, v_field_rqd * 1000); - + print_value(12, "[H PERIOD(ps)]", h_period); - + /* 13. Find the actual Vertical field frequency: * @@ -429,7 +429,7 @@ vesagtf_mode_params(unsigned h_pixels, unsigned v_lines, unsigned freq, v_field_rate = DIVIDE(1000000000000ULL, h_period * total_v_lines); print_value(13, "[V FIELD RATE]", v_field_rate); - + /* 14. Find the Vertical frame frequency: * @@ -442,7 +442,7 @@ vesagtf_mode_params(unsigned h_pixels, unsigned v_lines, unsigned freq, v_field_rate / 2 : v_field_rate; print_value(14, "[V FRAME RATE]", v_frame_rate); - + /* 15. Find number of pixels in left margin: * 16. Find number of pixels in right margin: @@ -462,7 +462,7 @@ vesagtf_mode_params(unsigned h_pixels, unsigned v_lines, unsigned freq, print_value(15, "[LEFT MARGIN (PIXELS)]", left_margin); print_value(16, "[RIGHT MARGIN (PIXELS)]", right_margin); - + /* 17. Find total number of active pixels in image and left and right * margins: @@ -472,10 +472,10 @@ vesagtf_mode_params(unsigned h_pixels, unsigned v_lines, unsigned freq, */ total_active_pixels = h_pixels + left_margin + right_margin; - + print_value(17, "[TOTAL ACTIVE PIXELS]", total_active_pixels); - - + + /* 18. Find the ideal blanking duty cycle from the blanking duty cycle * equation: * @@ -496,9 +496,9 @@ vesagtf_mode_params(unsigned h_pixels, unsigned v_lines, unsigned freq, ideal_duty_cycle = ((C_PRIME256(params) * 1000) - (M_PRIME256(params) * h_period / 1000000)); - + print_value(18, "[IDEAL DUTY CYCLE]", ideal_duty_cycle); - + /* 19. Find the number of pixels in the blanking time to the nearest * double character cell: @@ -517,7 +517,7 @@ vesagtf_mode_params(unsigned h_pixels, unsigned v_lines, unsigned freq, 2 * CELL_GRAN) * (2 * CELL_GRAN); print_value(19, "[H BLANK (PIXELS)]", h_blank); - + /* 20. Find total number of pixels: * @@ -525,9 +525,9 @@ vesagtf_mode_params(unsigned h_pixels, unsigned v_lines, unsigned freq, */ total_pixels = total_active_pixels + h_blank; - + print_value(20, "[TOTAL PIXELS]", total_pixels); - + /* 21. Find pixel clock frequency: * @@ -537,11 +537,11 @@ vesagtf_mode_params(unsigned h_pixels, unsigned v_lines, unsigned freq, * is usable with integer math. Recall that the [H PERIOD] is in * nsec. */ - + pixel_freq = DIVIDE(total_pixels * 1000000, DIVIDE(h_period, 1000)); - + print_value(21, "[PIXEL FREQ]", pixel_freq); - + /* 22. Find horizontal frequency: * @@ -555,10 +555,10 @@ vesagtf_mode_params(unsigned h_pixels, unsigned v_lines, unsigned freq, #ifdef GTFDEBUG h_freq = 1000000000 / h_period; - + print_value(22, "[H FREQ]", h_freq); #endif - + /* Stage 1 computations are now complete; I should really pass @@ -566,7 +566,7 @@ vesagtf_mode_params(unsigned h_pixels, unsigned v_lines, unsigned freq, computations, but I only need a few more values so I'll just append the computations here for now */ - + /* 17. Find the number of pixels in the horizontal sync period: * @@ -583,7 +583,7 @@ vesagtf_mode_params(unsigned h_pixels, unsigned v_lines, unsigned freq, CELL_GRAN; print_value(17, "[H SYNC (PIXELS)]", h_sync); - + /* 18. Find the number of pixels in the horizontal front porch period: * @@ -596,8 +596,8 @@ vesagtf_mode_params(unsigned h_pixels, unsigned v_lines, unsigned freq, h_front_porch = (h_blank / 2) - h_sync; print_value(18, "[H FRONT PORCH (PIXELS)]", h_front_porch); - - + + /* 36. Find the number of lines in the odd front porch period: * * [V ODD FRONT PORCH(LINES)]=([MIN PORCH RND]+[INTERLACE]) @@ -606,11 +606,11 @@ vesagtf_mode_params(unsigned h_pixels, unsigned v_lines, unsigned freq, * * [V ODD FRONT PORCH(LINES)]=(([MIN PORCH RND] * 2) + [2*INTERLACE]) / 2 */ - + v_odd_front_porch_lines = ((2 * params->min_porch) + interlace) / 2; - + print_value(36, "[V ODD FRONT PORCH(LINES)]", v_odd_front_porch_lines); - + /* finally, pack the results in the mode struct */ @@ -625,7 +625,7 @@ vesagtf_mode_params(unsigned h_pixels, unsigned v_lines, unsigned freq, vmp->vdisplay = v_lines; vmp->dot_clock = pixel_freq; - + } void @@ -667,7 +667,7 @@ print_xf86_mode (struct videomode *vmp) printf("\n"); printf(" # %dx%d @ %.2f Hz (GTF) hsync: %.2f kHz; pclk: %.2f MHz\n", vmp->hdisplay, vmp->vdisplay, vf, hf, vmp->dot_clock / 1000.0); - + printf(" Modeline \"%dx%d_%.2f\" %.2f" " %d %d %d %d" " %d %d %d %d" @@ -686,12 +686,12 @@ main (int argc, char *argv[]) printf("usage: %s x y refresh\n", argv[0]); exit(1); } - + vesagtf_mode(atoi(argv[1]), atoi(argv[2]), atoi(argv[3]), &m); print_xf86_mode(&m); - + return 0; - + } #endif diff --git a/sys/dev/videomode/vesagtf.h b/sys/dev/videomode/vesagtf.h index 885b685c8..6825b2e7e 100644 --- a/sys/dev/videomode/vesagtf.h +++ b/sys/dev/videomode/vesagtf.h @@ -29,7 +29,7 @@ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ + */ #ifndef _DEV_VIDEOMODE_VESAGTF_H #define _DEV_VIDEOMODE_VESAGTF_H diff --git a/sys/dev/x86emu/x86emu_regs.h b/sys/dev/x86emu/x86emu_regs.h index fda2d47aa..5b49e8ab1 100644 --- a/sys/dev/x86emu/x86emu_regs.h +++ b/sys/dev/x86emu/x86emu_regs.h @@ -98,8 +98,8 @@ #define F_ALWAYS_ON (0x0002) /* flag bits always on */ /* - * Define a mask for only those flag bits we will ever pass back - * (via PUSHF) + * Define a mask for only those flag bits we will ever pass back + * (via PUSHF) */ #define F_MSK (FB_CF|FB_PF|FB_AF|FB_ZF|FB_SF|FB_TF|FB_IF|FB_DF|FB_OF) diff --git a/sys/kern/init_main.c b/sys/kern/init_main.c index fd918a019..a068716bd 100644 --- a/sys/kern/init_main.c +++ b/sys/kern/init_main.c @@ -482,7 +482,7 @@ main(void *framep) /* * Now can look at time, having had a chance to verify the time - * from the file system. + * from the file system. */ LIST_FOREACH(pr, &allprocess, ps_list) { nanouptime(&pr->ps_start); diff --git a/sys/netinet/ip_ipsp.h b/sys/netinet/ip_ipsp.h index c24174d0f..ba33ff266 100644 --- a/sys/netinet/ip_ipsp.h +++ b/sys/netinet/ip_ipsp.h @@ -357,7 +357,7 @@ struct tdb { /* tunnel descriptor block */ #define TDBF_PFSYNC_RPL 0x80000 /* Replay counter should be bumped */ #define TDBF_ESN 0x100000 /* 64-bit sequence numbers (ESN) */ #define TDBF_PFSYNC_SNAPPED 0x200000 /* entry is being dispatched to peer */ -#define TDBF_IFACE 0x400000 /* entry policy is via sec(4) */ +#define TDBF_IFACE 0x400000 /* entry policy is via sec(4) */ #define TDBF_BITS ("\20" \ "\1UNIQUE\2TIMER\3BYTES\4ALLOCATIONS" \ diff --git a/sys/ntfs/ntfs_subr.c b/sys/ntfs/ntfs_subr.c index f9187d90f..5b2b63858 100644 --- a/sys/ntfs/ntfs_subr.c +++ b/sys/ntfs/ntfs_subr.c @@ -81,7 +81,7 @@ static signed int ntfs_toupper_usecount; !ntfs_uastrcmp(ntmp, aalp->al_name,aalp->al_namelen,name,namelen) ) /* - * + * */ int ntfs_ntvattrrele(struct ntvattr *vap) @@ -715,7 +715,7 @@ ntfs_fget(struct ntfsmount *ntmp, struct ntnode *ip, int attrtype, DPRINTF("ntfs_fget: fnode: attrtype: %u, attrname: %s\n", fp->f_attrtype, fp->f_attrname ? fp->f_attrname : ""); - if ((attrtype == fp->f_attrtype) && + if ((attrtype == fp->f_attrtype) && ((!attrname && !fp->f_attrname) || (attrname && fp->f_attrname && !strcmp(attrname,fp->f_attrname)))){ diff --git a/usr.bin/rdist/client.c b/usr.bin/rdist/client.c index 98d377d27..c29b1b8a2 100644 --- a/usr.bin/rdist/client.c +++ b/usr.bin/rdist/client.c @@ -293,7 +293,7 @@ checkfilename(char *name) for (cp = name; *cp; cp++) if (*cp == '\n') *cp = '?'; - message(MT_NERROR, + message(MT_NERROR, "Refuse to handle filename containing newline: %s", name); return(-1); diff --git a/usr.sbin/amd/amd/wire.c b/usr.sbin/amd/amd/wire.c index 29439bc9b..6162ae58a 100644 --- a/usr.sbin/amd/amd/wire.c +++ b/usr.sbin/amd/amd/wire.c @@ -88,7 +88,7 @@ getwire(void) !(ifa->ifa_flags & IFF_UP) || (ifa->ifa_flags & IFF_LOOPBACK)) continue; - + /* * Add interface to local network list */ diff --git a/usr.sbin/amd/amq/amq.c b/usr.sbin/amd/amq/amq.c index 57e2c4a5d..f8e5762bf 100644 --- a/usr.sbin/amd/amq/amq.c +++ b/usr.sbin/amd/amq/amq.c @@ -95,7 +95,7 @@ show_mti(amq_mount_tree *mt, enum show_opt e, int *mwid, int *dwid, printf("%-*.*s %-*.*s %-*.*s %s\n\t%-5d %-7d %-6d" " %-7d %-7d %-6d %02d/%02d/%02d %02d:%02d:%02d\n", *dwid, *dwid, *mt->mt_directory ? mt->mt_directory : "/", - *twid, *twid, mt->mt_type, *mwid, *mwid, + *twid, *twid, mt->mt_type, *mwid, *mwid, mt->mt_mountinfo, mt->mt_mountpoint, mt->mt_mountuid, mt->mt_getattr, mt->mt_lookup, mt->mt_readdir, mt->mt_readlink, mt->mt_statfs, diff --git a/usr.sbin/apmd/apm-proto.h b/usr.sbin/apmd/apm-proto.h index 867d0afbd..35402ac6b 100644 --- a/usr.sbin/apmd/apm-proto.h +++ b/usr.sbin/apmd/apm-proto.h @@ -3,7 +3,7 @@ /* * Copyright (c) 1996 John T. Kohl * All rights reserved. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: @@ -14,7 +14,7 @@ * documentation and/or other materials provided with the distribution. * 3. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR `AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -26,7 +26,7 @@ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. - * + * */ enum apm_action { diff --git a/usr.sbin/apmd/apmsubr.c b/usr.sbin/apmd/apmsubr.c index 6504fe823..ab794f3b6 100644 --- a/usr.sbin/apmd/apmsubr.c +++ b/usr.sbin/apmd/apmsubr.c @@ -3,7 +3,7 @@ /* * Copyright (c) 1995,1996 John T. Kohl * All rights reserved. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: @@ -14,7 +14,7 @@ * documentation and/or other materials provided with the distribution. * 3. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR `AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -26,7 +26,7 @@ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. - * + * */ #include diff --git a/usr.sbin/apmd/pathnames.h b/usr.sbin/apmd/pathnames.h index 250361040..3b49666ff 100644 --- a/usr.sbin/apmd/pathnames.h +++ b/usr.sbin/apmd/pathnames.h @@ -3,7 +3,7 @@ /* * Copyright (c) 1996 John T. Kohl * All rights reserved. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: @@ -14,7 +14,7 @@ * documentation and/or other materials provided with the distribution. * 3. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR `AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -26,7 +26,7 @@ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. - * + * */ #define _PATH_APM_SOCKET "/var/run/apmdev" diff --git a/usr.sbin/btrace/btrace.8 b/usr.sbin/btrace/btrace.8 index b23346518..2f7d5da25 100644 --- a/usr.sbin/btrace/btrace.8 +++ b/usr.sbin/btrace/btrace.8 @@ -72,7 +72,7 @@ collection of useful programs .El .Sh EXIT STATUS -.Ex -std +.Ex -std .Sh SEE ALSO .Xr dt 4 , .Xr bt 5 diff --git a/usr.sbin/config/sem.c b/usr.sbin/config/sem.c index b8b4b676c..db3962716 100644 --- a/usr.sbin/config/sem.c +++ b/usr.sbin/config/sem.c @@ -1096,7 +1096,7 @@ fixloc(const char *name, struct attr *attr, struct nvlist *got) if (attr->a_loclen == 0) /* e.g., "at root" */ lp = nullvec; else - lp = ereallocarray(NULL, attr->a_loclen + 1, + lp = ereallocarray(NULL, attr->a_loclen + 1, sizeof(const char *)); for (n = got; n != NULL; n = n->nv_next) n->nv_int = -1; diff --git a/usr.sbin/crunchgen/crunchgen.c b/usr.sbin/crunchgen/crunchgen.c index b5a859bd4..e0337d556 100644 --- a/usr.sbin/crunchgen/crunchgen.c +++ b/usr.sbin/crunchgen/crunchgen.c @@ -112,7 +112,7 @@ void gen_outputs(void); extern int crunchide_main(int, char *[]); -int +int main(int argc, char *argv[]) { char *p; @@ -216,7 +216,7 @@ main(int argc, char *argv[]) exit(goterror); } -void +void usage(void) { fprintf(stderr, @@ -239,7 +239,7 @@ void add_special(int argc, char **argv); prog_t *find_prog(char *str); void add_prog(char *progname); -void +void parse_conf_file(void) { if (!is_nonempty_file(infilename)) { @@ -254,7 +254,7 @@ parse_conf_file(void) } } -void +void parse_one_file(char *filename) { char *fieldv[MAXFIELDS]; @@ -311,7 +311,7 @@ parse_one_file(char *filename) fclose(cf); } -void +void parse_line(char *line, int *fc, char **fv, int nf) { char *p; @@ -336,7 +336,7 @@ parse_line(char *line, int *fc, char **fv, int nf) *p = '\0'; /* needed for '#' case */ } -void +void add_srcdirs(int argc, char **argv) { int i; @@ -374,7 +374,7 @@ add_srcdirs(int argc, char **argv) } } -void +void add_libdirs(int argc, char **argv) { int i; @@ -409,7 +409,7 @@ add_libdirs(int argc, char **argv) if (is_dir(tmppath2)) add_string(&libdirs, tmppath2); else { - snprintf(tmppath2, sizeof(tmppath2), + snprintf(tmppath2, sizeof(tmppath2), "%s/obj.%s", tmppath, MACHINE); if (is_dir(tmppath2)) add_string(&libdirs, tmppath2); @@ -426,7 +426,7 @@ add_libdirs(int argc, char **argv) } -void +void add_progs(int argc, char **argv) { int i; @@ -435,7 +435,7 @@ add_progs(int argc, char **argv) add_prog(argv[i]); } -void +void add_prog(char *progname) { prog_t *p1, *p2; @@ -463,7 +463,7 @@ add_prog(char *progname) p2->goterror = 0; } -void +void add_link(int argc, char **argv) { int i; @@ -480,7 +480,7 @@ add_link(int argc, char **argv) add_string(&p->links, argv[i]); } -void +void add_libs(int argc, char **argv) { int i; @@ -489,7 +489,7 @@ add_libs(int argc, char **argv) add_string(&libs, argv[i]); } -void +void add_special(int argc, char **argv) { int i; @@ -570,7 +570,7 @@ void output_strlst(FILE * outf, strlst_t * lst); char *genident(char *str); char *dir_search(char *progname); -void +void gen_outputs(void) { prog_t *p; @@ -584,7 +584,7 @@ gen_outputs(void) gen_output_makefile(); } -void +void fillin_program(prog_t * p) { char path[PATH_MAX]; @@ -654,7 +654,7 @@ fillin_program(prog_t * p) } } -void +void fillin_program_objs(prog_t * p, char *path) { char *cp, *obj, tempfname[PATH_MAX], cwd[PATH_MAX]; @@ -730,7 +730,7 @@ fillin_program_objs(prog_t * p, char *path) unlink(tempfname); } -void +void remove_error_progs(void) { prog_t *p1, *p2; @@ -753,7 +753,7 @@ remove_error_progs(void) } } -void +void gen_specials_cache(void) { FILE *cachef; @@ -785,7 +785,7 @@ gen_specials_cache(void) fclose(cachef); } -void +void gen_output_makefile(void) { prog_t *p; @@ -808,7 +808,7 @@ gen_output_makefile(void) fclose(outmk); } -void +void gen_output_cfile(void) { extern char *crunched_skel[]; @@ -883,7 +883,7 @@ dir_search(char *progname) return NULL; } -void +void top_makefile_rules(FILE * outmk) { prog_t *p; @@ -961,7 +961,7 @@ top_makefile_rules(FILE * outmk) fprintf(outmk, ".PHONY: all objs exe clean $(SUBMAKE_TARGETS)\n\n"); } -void +void prog_makefile_rules(FILE * outmk, prog_t * p) { fprintf(outmk, "\n# -------- %s\n\n", p->name); @@ -995,7 +995,7 @@ prog_makefile_rules(FILE * outmk, prog_t * p) elf_names ? "" : "_", p->ident); } -void +void output_strlst(FILE * outf, strlst_t * lst) { for (; lst != NULL; lst = lst->next) @@ -1003,14 +1003,14 @@ output_strlst(FILE * outf, strlst_t * lst) fprintf(outf, "\n"); } -void +void out_of_memory(void) { fprintf(stderr, "%s: %d: out of memory, stopping.\n", infilename, linenum); exit(1); } -void +void add_string(strlst_t ** listp, char *str) { strlst_t *p1, *p2; @@ -1034,7 +1034,7 @@ add_string(strlst_t ** listp, char *str) p1->next = p2; } -int +int is_dir(char *pathname) { struct stat buf; @@ -1044,7 +1044,7 @@ is_dir(char *pathname) return S_ISDIR(buf.st_mode); } -int +int is_nonempty_file(char *pathname) { struct stat buf; diff --git a/usr.sbin/crunchgen/crunchide.c b/usr.sbin/crunchgen/crunchide.c index 16e032370..02d4feb3a 100644 --- a/usr.sbin/crunchgen/crunchide.c +++ b/usr.sbin/crunchgen/crunchide.c @@ -79,7 +79,7 @@ int crunchide_main(int argc, char *argv[]); extern char *__progname; extern int elf_mangle; -int +int crunchide_main(int argc, char *argv[]) { int ch; @@ -126,7 +126,7 @@ struct keep { char *sym; } *keep_list; -void +void add_to_keep_list(char *symbol) { struct keep *newp, *prevp, *curp; @@ -153,7 +153,7 @@ add_to_keep_list(char *symbol) keep_list = newp; } -int +int in_keep_list(char *symbol) { struct keep *curp; @@ -166,7 +166,7 @@ in_keep_list(char *symbol) return curp && cmp == 0; } -void +void add_file_to_keep_list(char *filename) { FILE *keepf; @@ -187,7 +187,7 @@ add_file_to_keep_list(char *filename) fclose(keepf); } -void +void hide_syms(char *filename) { int inf; diff --git a/usr.sbin/crunchgen/mangle.c b/usr.sbin/crunchgen/mangle.c index 513bb65c9..756d4e848 100644 --- a/usr.sbin/crunchgen/mangle.c +++ b/usr.sbin/crunchgen/mangle.c @@ -34,7 +34,7 @@ #include "mangle.h" /* - * supports randomizing up to 32 characters, if an identifier is longer than + * supports randomizing up to 32 characters, if an identifier is longer than * 32 characters, we only modify the first 32 characters of it. * * However not all of the 32 characters will really be randomized as @@ -137,12 +137,12 @@ mangle_str(char *str) len = MAX_KEY_STR_LEN; keyval = key[len-1]++; - + for (i = 0; i < len; i++) { int idx = keyval % NUM_KEYS; keyval = keyval / NUM_KEYS; str[i] = validchars[idx]; - + } } diff --git a/usr.sbin/eigrpd/eigrpd.c b/usr.sbin/eigrpd/eigrpd.c index db169455c..3187b925f 100644 --- a/usr.sbin/eigrpd/eigrpd.c +++ b/usr.sbin/eigrpd/eigrpd.c @@ -701,7 +701,7 @@ merge_config(struct eigrpd_conf *conf, struct eigrpd_conf *xconf, } /* TODO update existing ifaces */ - } + } /* resend addresses to activate new interfaces */ if (proc == PROC_MAIN) diff --git a/usr.sbin/eigrpd/packet.c b/usr.sbin/eigrpd/packet.c index c68ad8fe2..9a2e51789 100644 --- a/usr.sbin/eigrpd/packet.c +++ b/usr.sbin/eigrpd/packet.c @@ -174,7 +174,7 @@ send_packet(struct eigrp_iface *ei, struct nbr *nbr, uint32_t flags, } if (flags) eigrp_hdr->flags |= htonl(flags); - + eigrp_hdr->chksum = 0; eigrp_hdr->chksum = in_cksum(ibuf_data(buf), ibuf_size(buf)); diff --git a/usr.sbin/fdformat/fdformat.c b/usr.sbin/fdformat/fdformat.c index 556e68528..6d6e6141a 100644 --- a/usr.sbin/fdformat/fdformat.c +++ b/usr.sbin/fdformat/fdformat.c @@ -29,7 +29,7 @@ /* * FreeBSD: * format a floppy disk - * + * * Added FD_GTYPE ioctl, verifying, proportional indicators. * Serge Vakulenko, vak@zebub.msk.su * Sat Dec 18 17:45:47 MSK 1993 @@ -106,7 +106,7 @@ verify_track(int fd, int track, int tracksize) fdopts |= FDOPT_NORETRY; (void)ioctl(fd, FD_SOPTS, &fdopts); } - + if (bufsz < tracksize) { free(buf); bufsz = tracksize; diff --git a/usr.sbin/ftp-proxy/ftp-proxy.c b/usr.sbin/ftp-proxy/ftp-proxy.c index 9291aaba9..2eb99918c 100644 --- a/usr.sbin/ftp-proxy/ftp-proxy.c +++ b/usr.sbin/ftp-proxy/ftp-proxy.c @@ -167,7 +167,7 @@ client_parse(struct session *s) if (s->cmd == CMD_PORT || s->cmd == CMD_EPRT) return (allow_data_connection(s)); } - + if (anonymous_only && (linebuf[0] == 'U' || linebuf[0] == 'u')) return (client_parse_anon(s)); @@ -364,7 +364,7 @@ get_line(char *buf, size_t *valid) linelen = i + 1; linebuf[linelen] = '\0'; *valid -= linelen; - + /* Move leftovers to the start. */ if (*valid != 0) bcopy(buf + linelen, buf, *valid); @@ -551,7 +551,7 @@ handle_signal(int sig, short event, void *arg) exit_daemon(); } - + struct session * init_session(void) @@ -973,7 +973,7 @@ allow_data_connection(struct session *s) * port collisions, to aid security (some systems pick weak * ports) or to satisfy RFC requirements (source port 20). */ - + /* Cast this once, to make code below it more readable. */ client_sa = sstosa(&s->client_ss); server_sa = sstosa(&s->server_ss); @@ -1070,7 +1070,7 @@ allow_data_connection(struct session *s) do_rollback(); return (0); } - + void server_read(struct bufferevent *bufev, void *arg) { diff --git a/usr.sbin/iscsictl/iscsictl.c b/usr.sbin/iscsictl/iscsictl.c index 5cb5a3474..9e6a3d024 100644 --- a/usr.sbin/iscsictl/iscsictl.c +++ b/usr.sbin/iscsictl/iscsictl.c @@ -387,7 +387,7 @@ show_vscsi_stats(struct ctrlmsghdr *cmh, struct pdu *pdu) vs->cnt_probe, vs->cnt_detach); printf("%llu I2T calls (%llu read, %llu writes)\n", vs->cnt_i2t, - vs->cnt_i2t_dir[1], + vs->cnt_i2t_dir[1], vs->cnt_i2t_dir[2]); if (fmt_scaled(vs->bytes_rd, buf) != 0) @@ -399,8 +399,8 @@ show_vscsi_stats(struct ctrlmsghdr *cmh, struct pdu *pdu) printf("%llu T2I calls (%llu done, %llu sense errors, %llu errors)\n", vs->cnt_t2i, - vs->cnt_t2i_status[0], - vs->cnt_t2i_status[1], + vs->cnt_t2i_status[0], + vs->cnt_t2i_status[1], vs->cnt_t2i_status[2]); } diff --git a/usr.sbin/iscsid/initiator.c b/usr.sbin/iscsid/initiator.c index e8e0a215d..2148dd32d 100644 --- a/usr.sbin/iscsid/initiator.c +++ b/usr.sbin/iscsid/initiator.c @@ -102,7 +102,7 @@ initiator_shutdown(struct initiator *i) log_debug("initiator_shutdown: going down"); TAILQ_FOREACH(s, &initiator->sessions, entry) - session_shutdown(s); + session_shutdown(s); } int @@ -287,7 +287,7 @@ initiator_login_kvp(struct connection *c, u_int8_t stage) default: log_warnx("initiator_login_kvp: exit stage left"); return NULL; - } + } return kvp; } diff --git a/usr.sbin/iscsid/pdu.c b/usr.sbin/iscsid/pdu.c index 7fe2d77da..e694d45c6 100644 --- a/usr.sbin/iscsid/pdu.c +++ b/usr.sbin/iscsid/pdu.c @@ -126,7 +126,7 @@ pdu_to_text(char *buf, size_t len) return k; } -/* Modified version of strtonum() to fit iscsid's need +/* Modified version of strtonum() to fit iscsid's need * * Copyright (c) 2004 Ted Unangst and Todd Miller * All rights reserved. @@ -198,7 +198,7 @@ text_to_bool(const char *buf, const char **errstrp) errno = 0; } else if (!strcmp(buf, "No")) errno = 0; - else + else errno = EINVAL; if (errstrp != NULL) { diff --git a/usr.sbin/lpd/lp.c b/usr.sbin/lpd/lp.c index bc60e91f8..f204c6329 100644 --- a/usr.sbin/lpd/lp.c +++ b/usr.sbin/lpd/lp.c @@ -123,7 +123,7 @@ lp_scanprinters(struct lp_printer *lp) if (r == -2) goto fail; return 1; - } else if (r == -1) + } else if (r == -1) fatal("cannot open %s", _PATH_PRINTCAP); else if (r == -2) errno = ELOOP; /* potential reference loop */ diff --git a/usr.sbin/lpd/lp_stty.c b/usr.sbin/lpd/lp_stty.c index 80504280d..d8dbbda8d 100644 --- a/usr.sbin/lpd/lp_stty.c +++ b/usr.sbin/lpd/lp_stty.c @@ -4,7 +4,7 @@ * Adapted from the following files in src/usr.sbin/lpr/lpd: * * extern.h,v 1.9 2015/09/29 02:37:29 - * key.c,v 1.8 2015/01/16 06:40:18 + * key.c,v 1.8 2015/01/16 06:40:18 * modes.c,v 1.8 2015/01/16 06:40:18 * printjob.c,v 1.58 2016/11/22 16:03:57 */ diff --git a/usr.sbin/lpr/SMM.doc/2.t b/usr.sbin/lpr/SMM.doc/2.t index b81151f4c..303941433 100644 --- a/usr.sbin/lpr/SMM.doc/2.t +++ b/usr.sbin/lpr/SMM.doc/2.t @@ -58,13 +58,13 @@ specifications, respectively. spawns a copy of itself to process the request; the master daemon continues to listen for new requests. .PP -Clients communicate with +Clients communicate with .I lpd using a simple transaction oriented protocol. Authentication of remote clients is done based on the ``privilege port'' scheme employed by \fIrshd\fP\|(8) and \fIrcmd\fP\|(3). -The following table shows the requests +The following table shows the requests understood by .IR lpd . In each request the first byte indicates the @@ -104,7 +104,7 @@ program works recursively backwards displaying the queue of the machine with the printer and then the queue(s) of the machine(s) that lead to it. .I Lpq has two forms of output: in the default, short, format it -gives a single line of output per queued job; in the long +gives a single line of output per queued job; in the long format it shows the list of files, and their sizes, that comprise a job. .NH 2 @@ -124,7 +124,7 @@ lpc \- line printer control program The .IR lpc (8) program is used by the system administrator to control the -operation of the line printer system. +operation of the line printer system. For each line printer configured in /etc/printcap, .I lpc may be used to: diff --git a/usr.sbin/lpr/SMM.doc/4.t b/usr.sbin/lpr/SMM.doc/4.t index c0f056cfa..b734a793b 100644 --- a/usr.sbin/lpr/SMM.doc/4.t +++ b/usr.sbin/lpr/SMM.doc/4.t @@ -32,7 +32,7 @@ .NH 1 Setting up .PP -OpenBSD comes with the necessary programs +OpenBSD comes with the necessary programs installed and with the default line printer queue created. If the system must be modified, the Makefile in the directory /usr/src/usr.sbin/lpr @@ -46,7 +46,7 @@ in the distribution system. .NH 2 Creating a printcap file .PP -The +The .I printcap database contains one or more entries per printer. A printer should have a separate spooling directory; diff --git a/usr.sbin/lpr/SMM.doc/5.t b/usr.sbin/lpr/SMM.doc/5.t index af8b50702..f1b731393 100644 --- a/usr.sbin/lpr/SMM.doc/5.t +++ b/usr.sbin/lpr/SMM.doc/5.t @@ -48,7 +48,7 @@ code if there were no errors, 1 if the job should be reprinted, and 2 if the job should be thrown away. When \fIlprm\fP sends a kill signal to the \fIlpd\fP process controlling -printing, it sends a SIGINT signal +printing, it sends a SIGINT signal to all filters and descendents of filters. This signal can be trapped by filters that need to do cleanup operations such as diff --git a/usr.sbin/lpr/SMM.doc/7.t b/usr.sbin/lpr/SMM.doc/7.t index 20370d15e..6ab7424f1 100644 --- a/usr.sbin/lpr/SMM.doc/7.t +++ b/usr.sbin/lpr/SMM.doc/7.t @@ -57,15 +57,15 @@ a missing or incorrect entry in the /etc/printcap file. .SH lpr: \fIprinter\fP\|: jobs queued, but cannot start daemon. .IP -The connection to +The connection to .I lpd -on the local machine failed. +on the local machine failed. This usually means the printer server started at boot time has died or is hung. Check the local socket /var/run/printer to be sure it still exists (if it does not exist, -there is no +there is no .I lpd -process running). +process running). Usually it is enough to get a super-user to type the following to restart .IR lpd . @@ -91,7 +91,7 @@ This means the queue was turned off with .DS % lpc disable \fIprinter\fP .DE -to prevent +to prevent .I lpr from putting files in the queue. This is normally done by the system manager when a printer is @@ -103,16 +103,16 @@ LPQ .SH waiting for \fIprinter\fP to become ready (offline ?) .IP -The printer device could not be opened by the daemon. +The printer device could not be opened by the daemon. This can happen for several reasons, the most common is that the printer is turned off-line. This message can also be generated if the printer is out of paper, the paper is jammed, etc. The actual reason is dependent on the meaning -of error codes returned by system device driver. -Not all printers supply enough information +of error codes returned by system device driver. +Not all printers supply enough information to distinguish when a printer is off-line or having -trouble (e.g. a printer connected through a serial line). +trouble (e.g. a printer connected through a serial line). Another possible cause of this message is some other process, such as an output filter, has an exclusive open on the device. Your only recourse @@ -136,7 +136,7 @@ waiting for \fIhost\fP to come up This implies there is a daemon trying to connect to the remote machine named .I host -to send the files in the local queue. +to send the files in the local queue. If the remote machine is up, .I lpd on the remote machine is probably dead or @@ -197,9 +197,9 @@ incorrect. Files may also be inaccessible if people manually manipulate the line printer system (i.e. they bypass the .I lpr -program). +program). .PP -In addition to messages generated by +In addition to messages generated by .IR lpd , any of the filters that .I lpd diff --git a/usr.sbin/lpr/common_source/common.c b/usr.sbin/lpr/common_source/common.c index e62272561..a56c44d81 100644 --- a/usr.sbin/lpr/common_source/common.c +++ b/usr.sbin/lpr/common_source/common.c @@ -242,7 +242,7 @@ getq(struct queue ***namelist) /* * Estimate the array size by taking the size of the directory file - * and dividing it by a multiple of the minimum size entry. + * and dividing it by a multiple of the minimum size entry. */ arraysz = (stbuf.st_size / 24); queue = calloc(arraysz, sizeof(struct queue *)); diff --git a/usr.sbin/lpr/filters/lpf.c b/usr.sbin/lpr/filters/lpf.c index 8c5ec688e..15528d369 100644 --- a/usr.sbin/lpr/filters/lpf.c +++ b/usr.sbin/lpr/filters/lpf.c @@ -62,7 +62,7 @@ char *acctfile; /* accounting information file */ __dead void usage(void); int -main(int argc, char **argv) +main(int argc, char **argv) { FILE *p = stdin, *o = stdout; int i, col; @@ -107,7 +107,7 @@ main(int argc, char **argv) memset(buf, ' ', sizeof(buf)); done = 0; - + while (!done) { col = indent; maxrep = -1; diff --git a/usr.sbin/lpr/lpc/cmds.c b/usr.sbin/lpr/lpc/cmds.c index 149904f79..4e9c05795 100644 --- a/usr.sbin/lpr/lpc/cmds.c +++ b/usr.sbin/lpr/lpc/cmds.c @@ -350,7 +350,7 @@ cleanpr(void) } } while (++i < nitems); } - + static void unlinkf(char *name) { @@ -1018,7 +1018,7 @@ topq(int argc, char **argv) out: PRIV_END; -} +} /* * Reposition the job by changing the modification time of @@ -1052,8 +1052,8 @@ doarg(char *job) FILE *fp; /* - * Look for a job item consisting of system name, colon, number - * (example: ucbarpa:114) + * Look for a job item consisting of system name, colon, number + * (example: ucbarpa:114) */ if ((cp = strchr(job, ':')) != NULL) { machine = job; diff --git a/usr.sbin/lpr/lpd/extern.h b/usr.sbin/lpr/lpd/extern.h index 81cb453ed..53bcbe395 100644 --- a/usr.sbin/lpr/lpd/extern.h +++ b/usr.sbin/lpr/lpd/extern.h @@ -41,14 +41,14 @@ */ struct info { int fd; /* file descriptor */ - int ldisc; /* line discipline */ + int ldisc; /* line discipline */ int off; /* turn off */ int set; /* need set */ int wset; /* need window set */ char *arg; /* argument */ - struct termios t; /* terminal info */ + struct termios t; /* terminal info */ struct winsize win; /* window info */ -}; +}; int allowedhost(FILE *, struct sockaddr *, socklen_t); int ksearch(char ***, struct info *); diff --git a/usr.sbin/lpr/lpd/printjob.c b/usr.sbin/lpr/lpd/printjob.c index 9b8579eff..3d1ac0952 100644 --- a/usr.sbin/lpr/lpd/printjob.c +++ b/usr.sbin/lpr/lpd/printjob.c @@ -1079,7 +1079,7 @@ scan_out(int scfd, char *scsp, int dlm) while (*--strp == BACKGND && strp >= outbuf) ; strp++; - *strp++ = '\n'; + *strp++ = '\n'; (void)write(scfd, outbuf, strp-outbuf); } } diff --git a/usr.sbin/lpr/lpd/recvjob.c b/usr.sbin/lpr/lpd/recvjob.c index 787da15b3..8158ffe27 100644 --- a/usr.sbin/lpr/lpd/recvjob.c +++ b/usr.sbin/lpr/lpd/recvjob.c @@ -87,7 +87,7 @@ recvjob(void) frecverr("unknown printer %s", printer); else if (status == -3) fatal("potential reference loop detected in printcap file"); - + if (cgetstr(bp, "lf", &LF) == -1) LF = _PATH_CONSOLE; if (cgetstr(bp, "sd", &SD) == -1) diff --git a/usr.sbin/lpr/lpr/lpr.c b/usr.sbin/lpr/lpr/lpr.c index cc92e3bb8..1c8b18aa4 100644 --- a/usr.sbin/lpr/lpr/lpr.c +++ b/usr.sbin/lpr/lpr/lpr.c @@ -79,7 +79,7 @@ static int nact; /* number of jobs to act on */ static int ncopies = 1; /* # of copies to make */ static const char *person; /* user name */ static int qflag; /* q job, but don't exec daemon */ -static int rflag; /* remove files upon completion */ +static int rflag; /* remove files upon completion */ static int sflag; /* symbolic link flag */ static int tfd; /* control file descriptor */ static char *tfname; /* tmp copy of cf before linking */ @@ -250,7 +250,7 @@ main(int argc, char **argv) errx(1, "only %ld copies are allowed", MC); /* * Get the identity of the person doing the lpr using the same - * algorithm as lprm. + * algorithm as lprm. */ if (real_uid != DU || person == NULL) { if ((pw = getpwuid(real_uid)) == NULL) @@ -424,7 +424,7 @@ copy(int f, char *n) } } (void)close(fd); - if (nc == 0 && nr == 0) + if (nc == 0 && nr == 0) warnx("%s: empty input file", f ? n : "stdin"); else nact++; diff --git a/usr.sbin/map-mbone/mapper.c b/usr.sbin/map-mbone/mapper.c index 42d31ba11..b443da1dc 100644 --- a/usr.sbin/map-mbone/mapper.c +++ b/usr.sbin/map-mbone/mapper.c @@ -8,7 +8,7 @@ /* * Copyright (c) 1992, 2001 Xerox Corporation. All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, + * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright notice, @@ -19,11 +19,11 @@ * and/or other materials provided with the distribution. * * Neither name of the Xerox, PARC, nor the names of its contributors may be used - * to endorse or promote products derived from this software - * without specific prior written permission. + * to endorse or promote products derived from this software + * without specific prior written permission. * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE XEROX CORPORATION OR CONTRIBUTORS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR @@ -32,7 +32,7 @@ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include @@ -376,10 +376,10 @@ void accept_neighbors(u_int32_t src, u_int32_t dst, u_char *p, int datalen, ifc_node->tries = -1; ifc_node->u.alias = node; } - + ifc = find_interface(ifc_addr, node); old_neighbors = ifc->neighbors; - + /* Add the neighbors for this interface */ while (ncount--) { u_int32_t neighbor; @@ -517,10 +517,10 @@ void accept_neighbors2(u_int32_t src, u_int32_t dst, u_char *p, int datalen, ifc_node->tries = -1; ifc_node->u.alias = node; } - + ifc = find_interface(ifc_addr, node); old_neighbors = ifc->neighbors; - + /* Add the neighbors for this interface */ while (ncount-- && datalen > 0) { u_int32_t neighbor; @@ -610,7 +610,7 @@ void print_map(Node *node) { if (node) { char *name, *addr; - + print_map(node->left); addr = inet_fmt(node->addr, s1); @@ -798,7 +798,7 @@ int main(int argc, char *argv[]) int flood = FALSE, graph = FALSE; int ch; const char *errstr; - + if (geteuid() != 0) { fprintf(stderr, "map-mbone: must be root\n"); exit(1); @@ -851,7 +851,7 @@ int main(int argc, char *argv[]) } argc -= optind; argv += optind; - + if (argc > 1) usage(); else if (argc == 1 && !(target_addr = host_addr(argv[0]))) { diff --git a/usr.sbin/memconfig/memconfig.c b/usr.sbin/memconfig/memconfig.c index 601dd1b7d..739417897 100644 --- a/usr.sbin/memconfig/memconfig.c +++ b/usr.sbin/memconfig/memconfig.c @@ -115,7 +115,7 @@ main(int argc, char *argv[]) for (i = 0; functions[i].cmd != NULL; i++) if (!strcmp(argv[1], functions[i].cmd)) break; - + if ((functions[i].func != helpfunc) && (memfd = open("/dev/mem", O_RDONLY)) == -1) err(1, "can't open /dev/mem"); diff --git a/usr.sbin/mkuboot/copy_elf.c b/usr.sbin/mkuboot/copy_elf.c index 7bcc8feda..25fb485d3 100644 --- a/usr.sbin/mkuboot/copy_elf.c +++ b/usr.sbin/mkuboot/copy_elf.c @@ -160,7 +160,7 @@ ELFNAME(copy_elf)(int ifd, const char *iname, int ofd, const char *oname, letoh32(phdr.p_type)); } - if (i == 0) + if (i == 0) vaddr = elfoff2h(phdr.p_vaddr); else if (vaddr != elfoff2h(phdr.p_vaddr)) { #ifdef DEBUG diff --git a/usr.sbin/mkuboot/mkuboot.c b/usr.sbin/mkuboot/mkuboot.c index 8d3adeb26..cfbde0f65 100644 --- a/usr.sbin/mkuboot/mkuboot.c +++ b/usr.sbin/mkuboot/mkuboot.c @@ -395,6 +395,6 @@ usage(void) (void)fprintf(stderr, "usage: %s [-a arch] [-e entry] [-l loadaddr] [-n name] [-o os] " "[-t type] infile outfile\n", __progname); - + exit(1); } diff --git a/usr.sbin/mopd/mopchk/Makefile b/usr.sbin/mopd/mopchk/Makefile index bdd10c47b..be2b6be9b 100644 --- a/usr.sbin/mopd/mopchk/Makefile +++ b/usr.sbin/mopd/mopchk/Makefile @@ -4,7 +4,7 @@ PROG= mopchk SRCS= mopchk.c device.c version.c pf.c loop-bsd.c file.c CFLAGS+= -I${.CURDIR} -I${.CURDIR}/.. -I${.CURDIR}/../common CLEANFILES= version.c version.h -.PATH: ${.CURDIR}/.. ${.CURDIR}/../common +.PATH: ${.CURDIR}/.. ${.CURDIR}/../common version.c version.h: ${.CURDIR}/../common/VERSION rm -f version.c; \ diff --git a/usr.sbin/mopd/mopchk/mopchk.c b/usr.sbin/mopd/mopchk/mopchk.c index f740a6a55..15cf230db 100644 --- a/usr.sbin/mopd/mopchk/mopchk.c +++ b/usr.sbin/mopd/mopchk/mopchk.c @@ -77,7 +77,7 @@ main(int argc, char **argv) /* NOTREACHED */ } } - + if (VersionFlag) printf("%s: Version %s\n", __progname, version); @@ -95,7 +95,7 @@ main(int argc, char **argv) if (p != NULL) { if (strcmp(p,ii->if_name) == 0) continue; - } + } printf("%-9s %x:%x:%x:%x:%x:%x\n", ii->if_name, ii->eaddr[0],ii->eaddr[1],ii->eaddr[2], @@ -104,7 +104,7 @@ main(int argc, char **argv) } } } - + if (VersionFlag || AllFlag) i = 1; else @@ -147,7 +147,7 @@ Usage(void) } /* - * Process incoming packages, NOT. + * Process incoming packages, NOT. */ void mopProcess(struct if_info *ii, u_char *pkt) diff --git a/usr.sbin/mopd/mopd/mopd.c b/usr.sbin/mopd/mopd/mopd.c index fd9d4b80c..96074b652 100644 --- a/usr.sbin/mopd/mopd/mopd.c +++ b/usr.sbin/mopd/mopd/mopd.c @@ -45,7 +45,7 @@ #include "pwd.h" /* - * The list of all interfaces that are being listened to. + * The list of all interfaces that are being listened to. * "selects" on the descriptors in this list. */ struct if_info *iflist; @@ -181,7 +181,7 @@ mopProcess(struct if_info *ii, u_char *pkt) /* * Ignore our own transmissions * - */ + */ if (mopCmpEAddr(ii->eaddr,src) == 0) return; diff --git a/usr.sbin/mopd/mopd/process.c b/usr.sbin/mopd/mopd/process.c index 4f6216942..a0a236dd4 100644 --- a/usr.sbin/mopd/mopd/process.c +++ b/usr.sbin/mopd/mopd/process.c @@ -176,7 +176,7 @@ mopStartLoad(u_char *dst, u_char *src, struct dllist *dl_rpr, int trans) bcopy(dst, dllist[i].eaddr, 6); } - /* If no slot yet, then return. No slot is free */ + /* If no slot yet, then return. No slot is free */ if (slot == -1) return; @@ -248,7 +248,7 @@ mopNextLoad(u_char *dst, u_char *src, u_char new_count, int trans) slot = i; } - /* If no slot yet, then return. No slot is free */ + /* If no slot yet, then return. No slot is free */ if (slot == -1) return; diff --git a/usr.sbin/mopd/mopprobe/Makefile b/usr.sbin/mopd/mopprobe/Makefile index 0d156da98..afe884301 100644 --- a/usr.sbin/mopd/mopprobe/Makefile +++ b/usr.sbin/mopd/mopprobe/Makefile @@ -5,7 +5,7 @@ SRCS= mopprobe.c device.c get.c cmp.c mopdef.c version.c pf.c loop-bsd.c \ print.c nma.c CFLAGS+= -I${.CURDIR} -I${.CURDIR}/.. -I${.CURDIR}/../common -DNODL CLEANFILES= version.c version.h -.PATH: ${.CURDIR}/../common +.PATH: ${.CURDIR}/../common version.c version.h: ${.CURDIR}/../common/VERSION rm -f version.c; \ diff --git a/usr.sbin/mopd/mopprobe/mopprobe.c b/usr.sbin/mopd/mopprobe/mopprobe.c index f6fe7f7f6..5d01acb55 100644 --- a/usr.sbin/mopd/mopprobe/mopprobe.c +++ b/usr.sbin/mopd/mopprobe/mopprobe.c @@ -95,7 +95,7 @@ main(int argc, char *argv[]) } } interface = argv[optind++]; - + if ((AllFlag && interface) || (!AllFlag && interface == 0) || (Not3Flag && Not4Flag)) @@ -127,7 +127,7 @@ mopProcess(struct if_info *ii, u_char *pkt) u_short ptype, moplen = 0, itype; int idx, trans, len, i, hwa = 0; struct once *o = NULL; - + /* We don't known with transport, Guess! */ trans = mopGetTrans(pkt, 0); @@ -150,14 +150,14 @@ mopProcess(struct if_info *ii, u_char *pkt) if (mopCmpEAddr(rc_mcst,dst) != 0) { return; } - + switch(ptype) { case MOP_K_PROTO_RC: break; default: return; } - + if (OnceFlag) { o = root; while (o != NULL) { @@ -184,10 +184,10 @@ mopProcess(struct if_info *ii, u_char *pkt) if (mopcode != MOP_K_CODE_SID) { return; } - + mopGetChar(pkt,&idx); /* Reserved */ mopGetShort(pkt,&idx); /* Receipt # */ - + device = 0; switch(trans) { @@ -199,7 +199,7 @@ mopProcess(struct if_info *ii, u_char *pkt) break; } - itype = mopGetShort(pkt,&idx); + itype = mopGetShort(pkt,&idx); while (idx < (int)(moplen)) { ilen = mopGetChar(pkt,&idx); @@ -228,7 +228,7 @@ mopProcess(struct if_info *ii, u_char *pkt) break; case MOP_K_INFO_SOFD: device = mopGetChar(pkt,&idx); - if (VerboseFlag && + if (VerboseFlag && (device != NMA_C_SOFD_LCS) && /* DECserver 100 */ (device != NMA_C_SOFD_DS2) && /* DECserver 200 */ (device != NMA_C_SOFD_DP2) && /* DECserver 250 */ @@ -244,7 +244,7 @@ mopProcess(struct if_info *ii, u_char *pkt) break; case MOP_K_INFO_SFID: tmpc = mopGetChar(pkt,&idx); - if ((tmpc > 0) && (tmpc < 17)) + if ((tmpc > 0) && (tmpc < 17)) idx = idx + tmpc; break; case MOP_K_INFO_PRTY: @@ -286,6 +286,6 @@ mopProcess(struct if_info *ii, u_char *pkt) idx = idx + ilen; }; } - itype = mopGetShort(pkt,&idx); + itype = mopGetShort(pkt,&idx); } } diff --git a/usr.sbin/mopd/moptrace/moptrace.c b/usr.sbin/mopd/moptrace/moptrace.c index 157dd12b7..1bea2351a 100644 --- a/usr.sbin/mopd/moptrace/moptrace.c +++ b/usr.sbin/mopd/moptrace/moptrace.c @@ -41,7 +41,7 @@ #include "common/get.h" /* - * The list of all interfaces that are being listened to. + * The list of all interfaces that are being listened to. * "selects" on the descriptors in this list. */ struct if_info *iflist; @@ -52,7 +52,7 @@ void mopProcess(struct if_info *, u_char *); int AllFlag = 0; /* listen on "all" interfaces */ int DebugFlag = 0; /* print debugging messages */ int Not3Flag = 0; /* Ignore MOP V3 messages */ -int Not4Flag = 0; /* Ignore MOP V4 messages */ +int Not4Flag = 0; /* Ignore MOP V4 messages */ int promisc = 1; /* Need promisc mode */ extern char *__progname; @@ -87,7 +87,7 @@ main(int argc, char *argv[]) } interface = argv[optind++]; - + if ((AllFlag && interface) || (!AllFlag && interface == 0) || (Not3Flag && Not4Flag)) @@ -129,7 +129,7 @@ mopProcess(struct if_info *ii, u_char *pkt) fprintf(stdout, "Interface : %s", ii->if_name); mopPrintHeader(stdout, pkt, trans); mopPrintMopHeader(stdout, pkt, trans); - + mopDumpDL(stdout, pkt, trans); mopDumpRC(stdout, pkt, trans); diff --git a/usr.sbin/mopd/otherOS/Makefile b/usr.sbin/mopd/otherOS/Makefile index 00aed7c67..32ad24310 100644 --- a/usr.sbin/mopd/otherOS/Makefile +++ b/usr.sbin/mopd/otherOS/Makefile @@ -42,7 +42,7 @@ INSTMAN="#" #sparc-linux2#INSTMAN= install -c -o root -g root -m 644 # Change these to cc/lex/yacc if you don't have gcc, flex and/or bison. -CC = cc +CC = cc LEX = lex YACC = yacc -y MAKE = make @@ -58,7 +58,7 @@ DIRS= mopchk mopd mopprobe moptrace CHDOC= mopchk.1 CHFIL= mopchk.c CHOBJ= mopchk.o -CHHDR= +CHHDR= LDDOC= mopd.8 LDFIL= mopd.c process.c LDOBJ= mopd.o process.o @@ -225,7 +225,7 @@ mopprobe: $(PBOBJ) $(COOBJ) $(OTOBJ) version.o moptrace: $(TROBJ) $(COOBJ) $(OTOBJ) version.o $(CC) $(CFLAGS) -o $@ $(TROBJ) $(COOBJ) $(OTOBJ) version.o $(LIB) -VERSION: +VERSION: @ln -s ../../../common/VERSION VERSION version.o: version.c diff --git a/usr.sbin/mopd/otherOS/loop-linux2.c b/usr.sbin/mopd/otherOS/loop-linux2.c index 1fc9827c3..ab31acbc3 100644 --- a/usr.sbin/mopd/otherOS/loop-linux2.c +++ b/usr.sbin/mopd/otherOS/loop-linux2.c @@ -96,8 +96,8 @@ Loop() int bufsize = 1100, maxfd =0; struct if_info *ii; -/* FIXME : this is a hack, for some reason specifying an interface would - * cause it to fail because bufsize is an impossible number, so I added a +/* FIXME : this is a hack, for some reason specifying an interface would + * cause it to fail because bufsize is an impossible number, so I added a * sanity check because I'm too lazy to figure out why. -- Karl */ if (bufsize > 1100) @@ -108,7 +108,7 @@ Loop() exit(0); } - buf = (u_char *) malloc((unsigned) bufsize); + buf = (u_char *) malloc((unsigned) bufsize); if (buf == 0) { syslog(LOG_ERR, "malloc: %m"); @@ -146,7 +146,7 @@ Loop() bp = buf; ep = bp + cc; - + if(bp < ep) { mopProcess(ii,buf); @@ -154,6 +154,6 @@ if(bp < ep) } -} -} +} +} diff --git a/usr.sbin/mopd/otherOS/loop.c b/usr.sbin/mopd/otherOS/loop.c index 58f06bbd3..7bffeefdf 100644 --- a/usr.sbin/mopd/otherOS/loop.c +++ b/usr.sbin/mopd/otherOS/loop.c @@ -136,7 +136,7 @@ Loop() fprintf(stderr,"no interfaces"); exit(0); } - + /* * Find the highest numbered file descriptor for select(). * Initialize the set of descriptors to listen to. diff --git a/usr.sbin/mopd/otherOS/mdtype b/usr.sbin/mopd/otherOS/mdtype index a74b48dee..1918dff58 100644 --- a/usr.sbin/mopd/otherOS/mdtype +++ b/usr.sbin/mopd/otherOS/mdtype @@ -9,7 +9,7 @@ machine="UNKNOWN" if [ -f /usr/bin/uname ]; then os=`/usr/bin/uname` - + if [ $os = "AIX" ]; then if [ "`/usr/bin/uname -v`" = "3" ]; then machine="rs6000" @@ -18,13 +18,13 @@ if [ -f /usr/bin/uname ]; then hw="`/usr/sbin/lsattr -l proc0 -E -a type | /usr/bin/cut -d\ -f2`" if [ $hw = "PowerPC_601" ]; then machine="rs6000" - fi + fi if [ $hw = "POWER" ]; then machine="rs6000" - fi + fi if [ $hw = "POWER2" ]; then machine="rs6000" - fi + fi fi fi @@ -45,9 +45,9 @@ fi if [ -f /bin/uname ]; then os=`/bin/uname` - + if [ $os = "Linux" ]; then - + machine="`/bin/uname -m`" if [ $machine = "i686" ]; then @@ -61,7 +61,7 @@ if [ -f /bin/uname ]; then if [ $machine = "i486" ]; then machine="i386" fi - + fi fi diff --git a/usr.sbin/mopd/otherOS/ostype b/usr.sbin/mopd/otherOS/ostype index ebe2b365a..243c23914 100644 --- a/usr.sbin/mopd/otherOS/ostype +++ b/usr.sbin/mopd/otherOS/ostype @@ -9,7 +9,7 @@ os="UNKNOWN" if [ -f /usr/bin/uname ]; then osname=`/usr/bin/uname` - + if [ $osname = "AIX" ]; then os="aix`/usr/bin/uname -v`" fi @@ -27,7 +27,7 @@ fi if [ -f /bin/uname ]; then osname=`/bin/uname` - + if [ $osname = "Linux" ]; then os="linux`/bin/uname -r | /usr/bin/cut -d. -f1`" fi diff --git a/usr.sbin/mopd/otherOS/pf-snit.c b/usr.sbin/mopd/otherOS/pf-snit.c index c9c88ac41..11222c7d1 100644 --- a/usr.sbin/mopd/otherOS/pf-snit.c +++ b/usr.sbin/mopd/otherOS/pf-snit.c @@ -85,29 +85,29 @@ pfInit(interface, mode, protocol, trans) int ioarg; char device[64]; unsigned long if_flags; - + struct ifreq ifr; struct strioctl si; - + /* get clone */ if ((fd = open(DEV_NIT, mode)) < 0) { syslog(LOG_ERR,"pfInit: open nit %m"); return(-1); } - + /* - * set filter for protocol + * set filter for protocol */ - + if (setup_pf(fd, protocol, trans) < 0) return(-1); - + /* * set options, bind to underlying interface */ - + strncpy(ifr.ifr_name, interface, sizeof(ifr.ifr_name)); - + /* bind */ si.ic_cmd = NIOCBIND; /* bind to underlying interface */ si.ic_timout = 10; @@ -117,7 +117,7 @@ pfInit(interface, mode, protocol, trans) syslog(LOG_ERR,"pfinit: I_STR %m"); return(-1); } - + if (promisc) { if_flags = NI_PROMISC; si.ic_cmd = NIOCSFLAGS; @@ -129,7 +129,7 @@ pfInit(interface, mode, protocol, trans) return(-1); } } - + /* set up messages */ if (ioctl(fd, I_SRDOPT, (char *)RMSGD) < 0) { /* want messages */ syslog(LOG_ERR,"pfInit: I_SRDOPT %m"); @@ -141,7 +141,7 @@ pfInit(interface, mode, protocol, trans) syslog(LOG_ERR,"pfInit: I_FLUSH %m"); return(-1); } - + return(fd); } @@ -192,7 +192,7 @@ setup_pf(s, prot, trans) syslog(LOG_ERR,"setup_pf: I_STR %m"); return(-1); } - + return(0); } @@ -207,14 +207,14 @@ u_char *addr; { struct ifreq ifr; struct sockaddr *sa; - + if (ioctl(fd, SIOCGIFADDR, &ifr) < 0) { syslog(LOG_ERR,"pfEthAddr: SIOCGIFADDR %m"); return(-1); } sa = (struct sockaddr *)ifr.ifr_data; bcopy((char *)sa->sa_data, (char *)addr, 6); - + return(0); } @@ -229,13 +229,13 @@ pfAddMulti(s, interface, addr) { struct ifreq ifr; int fd; - + strncpy(ifr.ifr_name, interface, sizeof (ifr.ifr_name) -1); ifr.ifr_name[sizeof(ifr.ifr_name)] = 0; - + ifr.ifr_addr.sa_family = AF_UNSPEC; bcopy(addr, ifr.ifr_addr.sa_data, 6); - + /* * open a socket, temporarily, to use for SIOC* ioctls */ @@ -250,7 +250,7 @@ pfAddMulti(s, interface, addr) return(-1); } close(fd); - + return(0); } @@ -265,13 +265,13 @@ char *interface, *addr; { struct ifreq ifr; int fd; - + strncpy(ifr.ifr_name, interface, sizeof (ifr.ifr_name) -1); ifr.ifr_name[sizeof(ifr.ifr_name)] = 0; - + ifr.ifr_addr.sa_family = AF_UNSPEC; bcopy(addr, ifr.ifr_addr.sa_data, 6); - + /* * open a socket, temporarily, to use for SIOC* ioctls * @@ -280,14 +280,14 @@ char *interface, *addr; syslog(LOG_ERR,"pfDelMulti: socket() %m"); return(-1); } - + if (ioctl(fd, SIOCDELMULTI, (caddr_t)&ifr) < 0) { syslog(LOG_ERR,"pfDelMulti: SIOCDELMULTI %m"); close(fd); return(-1); } close(fd); - + return(0); } @@ -312,10 +312,10 @@ pfWrite(fd, buf, len, trans) int fd, len, trans; u_char *buf; { - + struct sockaddr sa; struct strbuf pbuf, dbuf; - + sa.sa_family = AF_UNSPEC; bcopy(buf, sa.sa_data, sizeof(sa.sa_data)); @@ -330,6 +330,6 @@ pfWrite(fd, buf, len, trans) if (putmsg(fd, &pbuf, &dbuf, 0) == 0) return(len); - + return(-1); } diff --git a/usr.sbin/mrinfo/mrinfo.c b/usr.sbin/mrinfo/mrinfo.c index 47c518541..0f1396ba5 100644 --- a/usr.sbin/mrinfo/mrinfo.c +++ b/usr.sbin/mrinfo/mrinfo.c @@ -337,7 +337,7 @@ main(int argc, char *argv[]) } argc -= optind; argv += optind; - + if (argc > 1) usage(); if (argc == 1) diff --git a/usr.sbin/netgroup_mkdb/netgroup_mkdb.c b/usr.sbin/netgroup_mkdb/netgroup_mkdb.c index 942c06a9d..7c30cc9ae 100644 --- a/usr.sbin/netgroup_mkdb/netgroup_mkdb.c +++ b/usr.sbin/netgroup_mkdb/netgroup_mkdb.c @@ -222,7 +222,7 @@ ng_load(const char *fname) key.size = strlen(head->n_name) + 1; data.data = (u_char *) & head; data.size = sizeof(head); - switch ((db->put)(db, &key, &data, + switch ((db->put)(db, &key, &data, R_NOOVERWRITE)) { case 0: break; diff --git a/usr.sbin/npppd/l2tp/l2tp_ctrl.c b/usr.sbin/npppd/l2tp/l2tp_ctrl.c index 0e8152f32..2d9eaa7f6 100644 --- a/usr.sbin/npppd/l2tp/l2tp_ctrl.c +++ b/usr.sbin/npppd/l2tp/l2tp_ctrl.c @@ -759,7 +759,7 @@ l2tp_ctrl_input(l2tpd *_this, int listener_index, struct sockaddr *peer, if (ctrl->peer.ss_family != peer->sa_family) notmatch = 1; else if (peer->sa_family == AF_INET) { - if (SIN(peer)->sin_addr.s_addr != + if (SIN(peer)->sin_addr.s_addr != SIN(&ctrl->peer)->sin_addr.s_addr || SIN(peer)->sin_port != SIN(&ctrl->peer)->sin_port) notmatch = 1; diff --git a/usr.sbin/npppd/l2tp/l2tp_local.h b/usr.sbin/npppd/l2tp/l2tp_local.h index cdcb92c9e..c1fe8bad0 100644 --- a/usr.sbin/npppd/l2tp/l2tp_local.h +++ b/usr.sbin/npppd/l2tp/l2tp_local.h @@ -79,7 +79,7 @@ struct l2tp_header { #define L2TP_SESSION_ID_MASK 0x00007fff #define L2TP_SESSION_ID_SHUFFLE_MARK 0x10000000 -#ifndef L2TP_NCALL +#ifndef L2TP_NCALL #define L2TP_NCALL 10000 #endif diff --git a/usr.sbin/npppd/l2tp/l2tpd.c b/usr.sbin/npppd/l2tp/l2tpd.c index 6931929bf..c01d38830 100644 --- a/usr.sbin/npppd/l2tp/l2tpd.c +++ b/usr.sbin/npppd/l2tp/l2tpd.c @@ -565,7 +565,7 @@ l2tpd_reload(l2tpd *_this, struct l2tp_confs *l2tp_conf) i = 0; TAILQ_FOREACH(conf, l2tp_conf, entry) { TAILQ_FOREACH(addr, &conf->listen, entry) - l2tpd_add_listener(_this, i++, conf, + l2tpd_add_listener(_this, i++, conf, (struct sockaddr *)&addr->addr); } if (l2tpd_start(_this) != 0) diff --git a/usr.sbin/npppd/npppd/chap.c b/usr.sbin/npppd/npppd/chap.c index e0c7efae3..0d634a2bf 100644 --- a/usr.sbin/npppd/npppd/chap.c +++ b/usr.sbin/npppd/npppd/chap.c @@ -179,7 +179,7 @@ chap_start(chap *_this) chap_log(_this, LOG_ALERT, "Requested authentication type(0x%x) " "is not supported.", _this->type); - ppp_set_disconnect_cause(_this->ppp, + ppp_set_disconnect_cause(_this->ppp, PPP_DISCON_AUTH_PROTOCOL_UNACCEPTABLE, PPP_PROTO_CHAP, 2 /* local */, NULL); ppp_stop(_this->ppp, "Authentication Required"); @@ -229,7 +229,7 @@ chap_start(chap *_this) } else { chap_log(_this, LOG_INFO, "Client did't respond our challenage."); - ppp_set_disconnect_cause(_this->ppp, + ppp_set_disconnect_cause(_this->ppp, PPP_DISCON_AUTH_FSM_TIMEOUT, PPP_PROTO_CHAP, 0, NULL); ppp_stop(_this->ppp, "Authentication Required"); diff --git a/usr.sbin/npppd/npppd/fsm.h b/usr.sbin/npppd/npppd/fsm.h index e793e792b..a35b06b26 100644 --- a/usr.sbin/npppd/npppd/fsm.h +++ b/usr.sbin/npppd/npppd/fsm.h @@ -88,7 +88,7 @@ typedef struct fsm_callbacks { (fsm *, u_char *, int *, int); void (*up)(fsm *); /* Called when fsm reaches OPENED state */ void (*down)(fsm *); /* Called when fsm leaves OPENED state */ - + void (*starting)(fsm *); /* Called when we want the lower layer */ void (*finished)(fsm *); /* Called when we don't want the lower layer */ void (*protreject)(int); /* Called when Protocol-Reject received */ diff --git a/usr.sbin/npppd/npppd/lcp.c b/usr.sbin/npppd/npppd/lcp.c index e13267025..d424d4f18 100644 --- a/usr.sbin/npppd/npppd/lcp.c +++ b/usr.sbin/npppd/npppd/lcp.c @@ -214,7 +214,7 @@ lcp_open(fsm *f) "failed to negotiate a auth protocol."); fsm_close(f, "Authentication is required"); ppp_set_disconnect_cause(f->ppp, - PPP_DISCON_AUTH_PROTOCOL_UNACCEPTABLE, + PPP_DISCON_AUTH_PROTOCOL_UNACCEPTABLE, _this->auth_order[0] /* first one */, 1 /* peer refused */, NULL); ppp_stop(f->ppp, "Authentication is required"); @@ -746,7 +746,7 @@ lcp_nakci(fsm *f, u_char *inp, int inlen) "auth proto=%s", peer_auth); ppp_set_disconnect_cause(f->ppp, - PPP_DISCON_AUTH_PROTOCOL_UNACCEPTABLE, + PPP_DISCON_AUTH_PROTOCOL_UNACCEPTABLE, authproto, 2 /* couldn't accept peer's */, NULL); ppp_stop(f->ppp, "Authentication is required"); diff --git a/usr.sbin/npppd/npppd/npppd.c b/usr.sbin/npppd/npppd/npppd.c index e23f8308d..185fed0a7 100644 --- a/usr.sbin/npppd/npppd/npppd.c +++ b/usr.sbin/npppd/npppd/npppd.c @@ -580,7 +580,7 @@ npppd_reset_routing_table(npppd *_this, int pool_only) #ifndef NO_ROUTE_FOR_POOLED_ADDRESS slist rtlist0; - if (_this->iface[0].using_pppx) + if (_this->iface[0].using_pppx) return 0; slist_init(&rtlist0); diff --git a/usr.sbin/npppd/npppd/npppd_auth.c b/usr.sbin/npppd/npppd/npppd_auth.c index 693125797..1bc3e2c72 100644 --- a/usr.sbin/npppd/npppd/npppd_auth.c +++ b/usr.sbin/npppd/npppd/npppd_auth.c @@ -498,7 +498,7 @@ npppd_auth_get_user(npppd_auth_base *base, const char *username) buf[lusername - lsuffix] = '\0'; un = buf; } - + if (priv_get_user_info(base->users_file_path, un, &u) == 0) return u; @@ -542,7 +542,7 @@ npppd_auth_radius_reload(npppd_auth_base *base, struct authconf *auth) ? DEFAULT_RADIUS_MAX_FAILOVERS : auth->data.radius.acct.max_failovers; - _this->rad_acct_setting->curr_server = + _this->rad_acct_setting->curr_server = _this->rad_auth_setting->curr_server = 0; /* load configs for authentication server */ diff --git a/usr.sbin/npppd/npppd/npppd_ctl.h b/usr.sbin/npppd/npppd/npppd_ctl.h index d1b4fbe02..075888022 100644 --- a/usr.sbin/npppd/npppd/npppd_ctl.h +++ b/usr.sbin/npppd/npppd/npppd_ctl.h @@ -42,7 +42,7 @@ enum imsg_type { IMSG_NONE, IMSG_CTL_OK, /* answers to npppctl requests */ - IMSG_CTL_FAIL, + IMSG_CTL_FAIL, IMSG_CTL_NOP, /* npppctl requests */ IMSG_CTL_WHO, IMSG_CTL_DISCONNECT, diff --git a/usr.sbin/npppd/npppd/npppd_radius.c b/usr.sbin/npppd/npppd/npppd_radius.c index c15e42cb0..d8f72e1e4 100644 --- a/usr.sbin/npppd/npppd/npppd_radius.c +++ b/usr.sbin/npppd/npppd/npppd_radius.c @@ -55,7 +55,7 @@ #define NPPPD_RADIUS_DBG(x) ppp_log x #define NPPPD_RADIUS_ASSERT(x) ASSERT(x) #else -#define NPPPD_RADIUS_DBG(x) +#define NPPPD_RADIUS_DBG(x) #define NPPPD_RADIUS_ASSERT(x) #endif @@ -68,14 +68,14 @@ static void npppd_ppp_radius_acct_reqcb(void *, RADIUS_PACKET *, int, RADIUS_REQ * RADIUS common functions ***********************************************************************/ /** - * Retribute Framed-IP-Address and Framed-IP-Netmask attribute of from + * Retribute Framed-IP-Address and Framed-IP-Netmask attribute of from * the given RADIUS packet and set them as the fields of ppp context. - */ + */ void ppp_proccess_radius_framed_ip(npppd_ppp *_this, RADIUS_PACKET *pkt) { struct in_addr ip4; - + if (radius_get_ipv4_attr(pkt, RADIUS_TYPE_FRAMED_IP_ADDRESS, &ip4) == 0) _this->realm_framed_ip_address = ip4; diff --git a/usr.sbin/npppd/npppd/pap.c b/usr.sbin/npppd/npppd/pap.c index 86c58f227..5aa55e373 100644 --- a/usr.sbin/npppd/npppd/pap.c +++ b/usr.sbin/npppd/npppd/pap.c @@ -310,7 +310,7 @@ pap_response(pap *_this, int authok, const char *mes) "logtype=Failure username=\"%s\" realm=%s", _this->name, realm); pap_stop(_this); - ppp_set_disconnect_cause(_this->ppp, + ppp_set_disconnect_cause(_this->ppp, PPP_DISCON_AUTH_FAILED, PPP_PROTO_PAP, 1 /* peer */, NULL); ppp_stop(_this->ppp, "Authentication Required"); } else { diff --git a/usr.sbin/npppd/npppd/radius_req.c b/usr.sbin/npppd/npppd/radius_req.c index c1693c873..b60ac79ac 100644 --- a/usr.sbin/npppd/npppd/radius_req.c +++ b/usr.sbin/npppd/npppd/radius_req.c @@ -292,7 +292,7 @@ radius_prepare(radius_req_setting *setting, void *context, if (pctx != NULL) *pctx = lap; - radius_req_setting_ref(setting); + radius_req_setting_ref(setting); return 0; fail: diff --git a/usr.sbin/nsd/Makefile.in b/usr.sbin/nsd/Makefile.in index 9b6c8b593..b1ea7f8fe 100644 --- a/usr.sbin/nsd/Makefile.in +++ b/usr.sbin/nsd/Makefile.in @@ -154,7 +154,7 @@ uninstall: @echo @echo "You still need to remove $(DESTDIR)$(configdir), $(DESTDIR)$(piddir), $(DESTDIR)$(dbfile) directory by hand." -test: +test: nsd: $(NSD_OBJ) $(LIBOBJS) $(LINK) -o $@ $(NSD_OBJ) $(LIBOBJS) $(SSL_LIBS) $(LIBS) @@ -388,7 +388,7 @@ config.h.in: configure.ac configure: configure.ac autoconf -tags: +tags: ctags *.[ch] # dependency generation diff --git a/usr.sbin/nsd/acx_nlnetlabs.m4 b/usr.sbin/nsd/acx_nlnetlabs.m4 index f27615bd8..54d32907b 100644 --- a/usr.sbin/nsd/acx_nlnetlabs.m4 +++ b/usr.sbin/nsd/acx_nlnetlabs.m4 @@ -1,5 +1,5 @@ # acx_nlnetlabs.m4 - common macros for configure checks -# Copyright 2009, Wouter Wijngaards, NLnet Labs. +# Copyright 2009, Wouter Wijngaards, NLnet Labs. # BSD licensed. # # Version 46 @@ -121,7 +121,7 @@ dnl Escape backslashes as \\, for C:\ paths, for the C preprocessor defines. dnl for example, ACX_ESCAPE_BACKSLASH($from_var, to_var) -dnl $1: the text to change. +dnl $1: the text to change. dnl $2: the result. AC_DEFUN([ACX_ESCAPE_BACKSLASH], [$2="`echo $1 | sed -e 's/\\\\/\\\\\\\\/g'`" ]) @@ -129,7 +129,7 @@ AC_DEFUN([ACX_ESCAPE_BACKSLASH], [$2="`echo $1 | sed -e 's/\\\\/\\\\\\\\/g'`" dnl Calculate comma separated windows-resource numbers from package version. dnl Picks the first three(,0) or four numbers out of the name. dnl $1: variable for the result -AC_DEFUN([ACX_RSRC_VERSION], +AC_DEFUN([ACX_RSRC_VERSION], [$1=[`echo $PACKAGE_VERSION | sed -e 's/^[^0-9]*\([0-9][0-9]*\)[^0-9][^0-9]*\([0-9][0-9]*\)[^0-9][^0-9]*\([0-9][0-9]*\)[^0-9][^0-9]*\([0-9][0-9]*\).*$/\1,\2,\3,\4/' -e 's/^[^0-9]*\([0-9][0-9]*\)[^0-9][^0-9]*\([0-9][0-9]*\)[^0-9][^0-9]*\([0-9][0-9]*\)[^0-9]*$/\1,\2,\3,0/' `] ]) @@ -138,7 +138,7 @@ dnl Checks if the compiler will accept the flag. dnl $1: the flag without a - in front, so g to check -g. dnl $2: executed if yes dnl $3: executed if no -AC_DEFUN([ACX_CHECK_COMPILER_FLAG], +AC_DEFUN([ACX_CHECK_COMPILER_FLAG], [ AC_REQUIRE([AC_PROG_CC]) AC_MSG_CHECKING(whether $CC supports -$1) @@ -238,12 +238,12 @@ AC_MSG_CHECKING([$CC dependency flag]) echo 'void f(void){}' >conftest.c if test "`$CC -MM conftest.c 2>&1`" = "conftest.o: conftest.c"; then DEPFLAG="-MM" -else +else if test "`$CC -xM1 conftest.c 2>&1`" = "conftest.o: conftest.c"; then DEPFLAG="-xM1" else DEPFLAG="-MM" # dunno do something - fi + fi fi AC_MSG_RESULT($DEPFLAG) rm -f conftest.c @@ -453,7 +453,7 @@ AC_DEFUN([ACX_CHECK_FLTO], [ ]) dnl Check the printf-format attribute (if any) -dnl result in HAVE_ATTR_FORMAT. +dnl result in HAVE_ATTR_FORMAT. dnl Make sure you also include the AHX_CONFIG_FORMAT_ATTRIBUTE. AC_DEFUN([ACX_CHECK_FORMAT_ATTRIBUTE], [AC_REQUIRE([AC_PROG_CC]) @@ -487,7 +487,7 @@ AC_DEFUN([AHX_CONFIG_FORMAT_ATTRIBUTE], ]) dnl Check how to mark function arguments as unused. -dnl result in HAVE_ATTR_UNUSED. +dnl result in HAVE_ATTR_UNUSED. dnl Make sure you include AHX_CONFIG_UNUSED_ATTRIBUTE also. AC_DEFUN([ACX_CHECK_UNUSED_ATTRIBUTE], [AC_REQUIRE([AC_PROG_CC]) @@ -559,7 +559,7 @@ LT_INIT ]) dnl Detect if u_char type is defined, otherwise define it. -AC_DEFUN([ACX_TYPE_U_CHAR], +AC_DEFUN([ACX_TYPE_U_CHAR], [AC_CHECK_TYPE([u_char], , [AC_DEFINE([u_char], [unsigned char], [Define to 'unsigned char if not defined])], [ AC_INCLUDES_DEFAULT @@ -570,7 +570,7 @@ AC_INCLUDES_DEFAULT dnl Detect if rlim_t type is defined, otherwise define it. AC_DEFUN([ACX_TYPE_RLIM_T], -[AC_CHECK_TYPE(rlim_t, , +[AC_CHECK_TYPE(rlim_t, , [AC_DEFINE([rlim_t], [unsigned long], [Define to 'int' if not defined])], [ AC_INCLUDES_DEFAULT #ifdef HAVE_SYS_RESOURCE_H @@ -581,7 +581,7 @@ AC_INCLUDES_DEFAULT dnl Detect if socklen_t type is defined, otherwise define it. AC_DEFUN([ACX_TYPE_SOCKLEN_T], [ -AC_CHECK_TYPE(socklen_t, , +AC_CHECK_TYPE(socklen_t, , [AC_DEFINE([socklen_t], [int], [Define to 'int' if not defined])], [ AC_INCLUDES_DEFAULT #ifdef HAVE_SYS_SOCKET_H @@ -707,7 +707,7 @@ AC_DEFUN([ACX_SSL_CHECKS], [ LIBSSL_LDFLAGS="$LIBSSL_LDFLAGS -L$ssldir_lib" ACX_RUNTIME_PATH_ADD([$ssldir_lib]) fi - + AC_MSG_CHECKING([for EVP_sha256 in -lcrypto]) LIBS="$LIBS -lcrypto" LIBSSL_LIBS="$LIBSSL_LIBS -lcrypto" @@ -720,7 +720,7 @@ AC_DEFUN([ACX_SSL_CHECKS], [ [If you have EVP_sha256]) ],[ AC_MSG_RESULT(no) - # check if -lwsock32 or -lgdi32 are needed. + # check if -lwsock32 or -lgdi32 are needed. BAKLIBS="$LIBS" BAKSSLLIBS="$LIBSSL_LIBS" LIBS="$LIBS -lgdi32 -lws2_32" @@ -732,7 +732,7 @@ AC_DEFUN([ACX_SSL_CHECKS], [ ]])],[ AC_DEFINE([HAVE_EVP_SHA256], 1, [If you have EVP_sha256]) - AC_MSG_RESULT(yes) + AC_MSG_RESULT(yes) ],[ AC_MSG_RESULT(no) LIBS="$BAKLIBS" @@ -746,7 +746,7 @@ AC_DEFUN([ACX_SSL_CHECKS], [ ]])],[ AC_DEFINE([HAVE_EVP_SHA256], 1, [If you have EVP_sha256]) - AC_MSG_RESULT(yes) + AC_MSG_RESULT(yes) ],[ AC_MSG_RESULT(no) LIBS="$BAKLIBS" @@ -760,7 +760,7 @@ AC_DEFUN([ACX_SSL_CHECKS], [ ]])],[ AC_DEFINE([HAVE_EVP_SHA256], 1, [If you have EVP_sha256]) - AC_MSG_RESULT(yes) + AC_MSG_RESULT(yes) ],[ AC_MSG_RESULT(no) AC_MSG_ERROR([OpenSSL found in $ssldir, but version 0.9.7 or higher is required]) @@ -779,7 +779,7 @@ AC_CHECK_HEADERS([openssl/rand.h],,, [AC_INCLUDES_DEFAULT]) dnl Check for SSL, where SSL is mandatory dnl Adds --with-ssl option, searches for openssl and defines HAVE_SSL if found -dnl Setup of CPPFLAGS, CFLAGS. Adds -lcrypto to LIBS. +dnl Setup of CPPFLAGS, CFLAGS. Adds -lcrypto to LIBS. dnl Checks main header files of SSL. dnl AC_DEFUN([ACX_WITH_SSL], @@ -797,7 +797,7 @@ AC_ARG_WITH(ssl, AS_HELP_STRING([--with-ssl=pathname],[enable SSL (will check /u dnl Check for SSL, where ssl is optional (--without-ssl is allowed) dnl Adds --with-ssl option, searches for openssl and defines HAVE_SSL if found -dnl Setup of CPPFLAGS, CFLAGS. Adds -lcrypto to LIBS. +dnl Setup of CPPFLAGS, CFLAGS. Adds -lcrypto to LIBS. dnl Checks main header files of SSL. dnl AC_DEFUN([ACX_WITH_SSL_OPTIONAL], @@ -1037,7 +1037,7 @@ int main(void) /* send and receive on the socket */ if((p=fork()) == 0) { for(i=0; i_limit = buffer->_capacity = capacity; buffer->_fixed = 0; buffer_invariant(buffer); - + region_add_cleanup(region, buffer_cleanup, buffer); return buffer; @@ -49,7 +49,7 @@ buffer_create_from(buffer_type *buffer, void *data, size_t size) buffer->_limit = buffer->_capacity = size; buffer->_data = (uint8_t *) data; buffer->_fixed = 1; - + buffer_invariant(buffer); } @@ -57,7 +57,7 @@ void buffer_clear(buffer_type *buffer) { buffer_invariant(buffer); - + buffer->_position = 0; buffer->_limit = buffer->_capacity; } @@ -66,7 +66,7 @@ void buffer_flip(buffer_type *buffer) { buffer_invariant(buffer); - + buffer->_limit = buffer->_position; buffer->_position = 0; } @@ -75,7 +75,7 @@ void buffer_rewind(buffer_type *buffer) { buffer_invariant(buffer); - + buffer->_position = 0; } @@ -109,7 +109,7 @@ buffer_printf(buffer_type *buffer, const char *format, ...) va_list args; int written; size_t remaining; - + buffer_invariant(buffer); assert(buffer->_limit == buffer->_capacity); diff --git a/usr.sbin/nsd/buffer.h b/usr.sbin/nsd/buffer.h index 9cf532147..469aaa160 100644 --- a/usr.sbin/nsd/buffer.h +++ b/usr.sbin/nsd/buffer.h @@ -26,7 +26,7 @@ struct buffer { /* * The current position used for reading/writing. - */ + */ size_t _position; /* diff --git a/usr.sbin/nsd/configlexer.lex b/usr.sbin/nsd/configlexer.lex index 836dd8009..cc6f6af77 100644 --- a/usr.sbin/nsd/configlexer.lex +++ b/usr.sbin/nsd/configlexer.lex @@ -400,7 +400,7 @@ include{COLON} { LEXOUT(("v(%s) ", yytext)); BEGIN(include); } } } -{UNQUOTEDLETTER}* { LEXOUT(("unquotedstr(%s) ", yytext)); +{UNQUOTEDLETTER}* { LEXOUT(("unquotedstr(%s) ", yytext)); c_lval.str = region_strdup(cfg_parser->opt->region, yytext); return STRING; } %% diff --git a/usr.sbin/nsd/configparser.y b/usr.sbin/nsd/configparser.y index 901c1ca2c..5f55fc20a 100644 --- a/usr.sbin/nsd/configparser.y +++ b/usr.sbin/nsd/configparser.y @@ -993,7 +993,7 @@ pattern_or_zone_option: { cfg_parser->pattern->min_retry_time = $2; cfg_parser->pattern->min_retry_time_is_default = 0; - } + } | VAR_MIN_EXPIRE_TIME STRING { long long num; diff --git a/usr.sbin/nsd/configure.ac b/usr.sbin/nsd/configure.ac index bd880566f..9ee94decd 100644 --- a/usr.sbin/nsd/configure.ac +++ b/usr.sbin/nsd/configure.ac @@ -1106,7 +1106,7 @@ AC_INCLUDES_DEFAULT #include #include ]) - AC_CHECK_DECL([TLS1_3_VERSION], + AC_CHECK_DECL([TLS1_3_VERSION], [AC_DEFINE([HAVE_TLS_1_3], [1], [Define if TLS 1.3 is supported by OpenSSL])], [AC_MSG_WARN([No TLS 1.3, therefore XFR-over-TLS is disabled])], [[#include ]]) diff --git a/usr.sbin/nsd/dbaccess.c b/usr.sbin/nsd/dbaccess.c index da5d94003..f948c18b0 100644 --- a/usr.sbin/nsd/dbaccess.c +++ b/usr.sbin/nsd/dbaccess.c @@ -141,7 +141,7 @@ read_rrset(udb_base* udb, namedb_type* db, zone_type* zone, } /** read one elem from db, of type domain_d */ -static void read_node_elem(udb_base* udb, namedb_type* db, +static void read_node_elem(udb_base* udb, namedb_type* db, region_type* dname_region, zone_type* zone, struct domain_d* d) { const dname_type* dname; diff --git a/usr.sbin/nsd/difffile.c b/usr.sbin/nsd/difffile.c index c48c70687..d46988b2c 100644 --- a/usr.sbin/nsd/difffile.c +++ b/usr.sbin/nsd/difffile.c @@ -115,7 +115,7 @@ diff_write_commit(const char* zone, uint32_t old_serial, uint32_t new_serial, zone, strerror(errno)); } - /* overwrite the first part of the file with 'committed = 1', + /* overwrite the first part of the file with 'committed = 1', * as well as the end_time and number of parts. * also write old_serial and new_serial, so that a bad file mixup * will result in unusable serial numbers. */ @@ -586,7 +586,7 @@ static void nsec3_add_rr_trigger(namedb_type* db, rr_type* rr, zone_type* zone, udb_ptr* udbz) { - /* the RR has been added in full, also to UDB (and thus NSEC3PARAM + /* the RR has been added in full, also to UDB (and thus NSEC3PARAM * in the udb has been adjusted) */ if(zone->nsec3_param && rr->type == TYPE_NSEC3 && (!rr->owner->nsec3 || !rr->owner->nsec3->nsec3_node.key) @@ -873,7 +873,7 @@ add_RR(namedb_type* db, const dname_type* dname, assert(zone->nsec3_param >= rrs_old && zone->nsec3_param < rrs_old+rrset->rr_count); /* in this order to make sure no overflow/underflow*/ - zone->nsec3_param = (void*)zone->nsec3_param - + zone->nsec3_param = (void*)zone->nsec3_param - (void*)rrs_old + (void*)rrset->rrs; } #endif /* NSEC3 */ @@ -890,7 +890,7 @@ add_RR(namedb_type* db, const dname_type* dname, if(rrset_added) { domain_type* p = domain->parent; nsec3_add_rrset_trigger(db, domain, zone, type); - /* go up and process (possibly created) empty nonterminals, + /* go up and process (possibly created) empty nonterminals, * until we hit the apex or root */ while(p && p->rrsets == NULL && !p->is_apex) { nsec3_rrsets_changed_add_prehash(db, p, zone); diff --git a/usr.sbin/nsd/dns.c b/usr.sbin/nsd/dns.c index 773facc6d..f48d28b3d 100644 --- a/usr.sbin/nsd/dns.c +++ b/usr.sbin/nsd/dns.c @@ -341,7 +341,7 @@ static rrtype_descriptor_type rrtype_descriptors[(RRTYPE_DESCRIPTORS_LENGTH+1)] , RDATA_WF_SVCPARAM, RDATA_WF_SVCPARAM, RDATA_WF_SVCPARAM , RDATA_WF_SVCPARAM, RDATA_WF_SVCPARAM, RDATA_WF_SVCPARAM }, - { RDATA_ZF_SHORT , RDATA_ZF_DNAME + { RDATA_ZF_SHORT , RDATA_ZF_DNAME , RDATA_ZF_SVCPARAM, RDATA_ZF_SVCPARAM , RDATA_ZF_SVCPARAM, RDATA_ZF_SVCPARAM, RDATA_ZF_SVCPARAM , RDATA_ZF_SVCPARAM, RDATA_ZF_SVCPARAM, RDATA_ZF_SVCPARAM diff --git a/usr.sbin/nsd/dnstap/dnstap.c b/usr.sbin/nsd/dnstap/dnstap.c index 19543d755..e9021dcf8 100644 --- a/usr.sbin/nsd/dnstap/dnstap.c +++ b/usr.sbin/nsd/dnstap/dnstap.c @@ -547,7 +547,7 @@ dt_create(const char *socket_path, char* ip, unsigned num_workers, fwopt = fstrm_writer_options_init(); #ifndef NDEBUG - res = + res = #else (void) #endif diff --git a/usr.sbin/nsd/dnstap/dnstap_collector.c b/usr.sbin/nsd/dnstap/dnstap_collector.c index 1578bdfb0..26ad9694e 100644 --- a/usr.sbin/nsd/dnstap/dnstap_collector.c +++ b/usr.sbin/nsd/dnstap/dnstap_collector.c @@ -260,7 +260,7 @@ dt_handle_input(int fd, short event, void* arg) dt_submit_content(dt_input->dt_collector->dt_env, dt_input->buffer); } - + /* clear buffer for next message */ buffer_clear(dt_input->buffer); } @@ -339,7 +339,7 @@ static void dt_attach_events(struct dt_collector* dt_col, struct nsd* nsd) log_msg(LOG_ERR, "dnstap collector: event_base_set failed"); if(event_add(dt_col->cmd_event, NULL) != 0) log_msg(LOG_ERR, "dnstap collector: event_add failed"); - + /* add worker input handlers */ dt_col->inputs = xalloc_array_zero(dt_col->count, sizeof(*dt_col->inputs)); @@ -355,7 +355,7 @@ static void dt_attach_events(struct dt_collector* dt_col, struct nsd* nsd) log_msg(LOG_ERR, "dnstap collector: event_base_set failed"); if(event_add(dt_col->inputs[i].event, NULL) != 0) log_msg(LOG_ERR, "dnstap collector: event_add failed"); - + dt_col->inputs[i].buffer = buffer_create(dt_col->region, /* msglen + is_response + addrlen + is_tcp + packetlen + packet + zonelen + zone + spare + local_addr + addr */ 4+1+4+1+4+TCP_MAX_MESSAGE_LEN+4+MAXHOSTNAMELEN + 32 + diff --git a/usr.sbin/nsd/edns.c b/usr.sbin/nsd/edns.c index 478ec681d..5ec8df231 100644 --- a/usr.sbin/nsd/edns.c +++ b/usr.sbin/nsd/edns.c @@ -101,7 +101,7 @@ edns_handle_option(uint16_t optcode, uint16_t optlen, buffer_type* packet, case COOKIE_CODE: /* Cookies enabled? */ if(nsd->do_answer_cookie) { - if (optlen == 8) + if (optlen == 8) edns->cookie_status = COOKIE_INVALID; else if (optlen < 16 || optlen > 40) return 0; /* FORMERR */ @@ -255,7 +255,7 @@ void cookie_verify(query_type *q, struct nsd* nsd, uint32_t *now_p) { | (q->edns.cookie[13] << 16) | (q->edns.cookie[14] << 8) | q->edns.cookie[15]; - + now_uint32 = *now_p ? *now_p : (*now_p = (uint32_t)time(NULL)); if(compare_1982(now_uint32, cookie_time) > 0) { @@ -309,7 +309,7 @@ void cookie_create(query_type *q, struct nsd* nsd, uint32_t *now_p) { uint8_t hash[8]; uint32_t now_uint32; - + if (q->edns.cookie_status == COOKIE_VALID_REUSE) return; diff --git a/usr.sbin/nsd/install-sh b/usr.sbin/nsd/install-sh index e9de23842..eed95e3ec 100644 --- a/usr.sbin/nsd/install-sh +++ b/usr.sbin/nsd/install-sh @@ -115,7 +115,7 @@ fi if [ x"$dir_arg" != x ]; then dst=$src src="" - + if [ -d $dst ]; then instcmd=: chmodcmd="" @@ -125,7 +125,7 @@ if [ x"$dir_arg" != x ]; then else # Waiting for this to be detected by the "$instcmd $src $dsttmp" command -# might cause directories to be created, which would be especially bad +# might cause directories to be created, which would be especially bad # if $src (and thus $dsttmp) contains '*'. if [ -f $src -o -d $src ] @@ -135,7 +135,7 @@ else echo "install: $src does not exist" exit 1 fi - + if [ x"$dst" = x ] then echo "install: no destination specified" @@ -202,17 +202,17 @@ else # If we're going to rename the final executable, determine the name now. - if [ x"$transformarg" = x ] + if [ x"$transformarg" = x ] then dstfile=`basename $dst` else - dstfile=`basename $dst $transformbasename | + dstfile=`basename $dst $transformbasename | sed $transformarg`$transformbasename fi # don't allow the sed command to completely eliminate the filename - if [ x"$dstfile" = x ] + if [ x"$dstfile" = x ] then dstfile=`basename $dst` else @@ -243,7 +243,7 @@ else # Now rename the file to the real destination. $doit $rmcmd -f $dstdir/$dstfile && - $doit $mvcmd $dsttmp $dstdir/$dstfile + $doit $mvcmd $dsttmp $dstdir/$dstfile fi && diff --git a/usr.sbin/nsd/ipc.h b/usr.sbin/nsd/ipc.h index b0d2dce2d..960bb4866 100644 --- a/usr.sbin/nsd/ipc.h +++ b/usr.sbin/nsd/ipc.h @@ -20,7 +20,7 @@ struct nsdst; struct event; /* - * Data for the server_main IPC handler + * Data for the server_main IPC handler * Used by parent side to listen to children, and write to children. */ struct main_ipc_handler_data @@ -41,7 +41,7 @@ struct main_ipc_handler_data /* * Data for ipc handler, nsd and a conn for reading ipc msgs. - * Used by children to listen to parent. + * Used by children to listen to parent. * Used by parent to listen to xfrd. */ struct ipc_handler_conn_data diff --git a/usr.sbin/nsd/ixfrcreate.c b/usr.sbin/nsd/ixfrcreate.c index 33855ebbc..f2f6d1758 100644 --- a/usr.sbin/nsd/ixfrcreate.c +++ b/usr.sbin/nsd/ixfrcreate.c @@ -557,7 +557,7 @@ static int process_diff_domain(FILE* spool, struct ixfr_create* ixfrcr, * later, the notseen ones from the new zone are added RRsets. * For the ones not in the new zone, they are deleted RRsets. * If they exist in old and new, check for RR differences. */ - uint32_t spool_type_count, i; + uint32_t spool_type_count, i; uint16_t marktypes[65536]; size_t marktypes_used = 0; if(!read_spool_u32(spool, &spool_type_count)) { @@ -780,7 +780,7 @@ static int process_spool_for_domain(FILE* spool, struct ixfr_create* ixfrcr, if(!process_spool_before_domain(spool, ixfrcr, store, domain, iter, tmp_region)) return 0; - + if(ixfr_create_too_large(ixfrcr, store)) return 0; /* are we at the correct domain now? */ diff --git a/usr.sbin/nsd/lookup3.c b/usr.sbin/nsd/lookup3.c index 9b47d156c..45bf478ec 100644 --- a/usr.sbin/nsd/lookup3.c +++ b/usr.sbin/nsd/lookup3.c @@ -13,8 +13,8 @@ lookup3.c, by Bob Jenkins, May 2006, Public Domain. These are functions for producing 32-bit hashes for hash table lookup. -hashword(), hashlittle(), hashlittle2(), hashbig(), mix(), and final() -are externally useful functions. Routines to test the hash are included +hashword(), hashlittle(), hashlittle2(), hashbig(), mix(), and final() +are externally useful functions. Routines to test the hash are included if SELF_TEST is defined. You can use this free for any purpose. It's in the public domain. It has no warranty. @@ -22,7 +22,7 @@ You probably want to use hashlittle(). hashlittle() and hashbig() hash byte arrays. hashlittle() is is faster than hashbig() on little-endian machines. Intel and AMD are little-endian machines. On second thought, you probably want hashlittle2(), which is identical to -hashlittle() except it returns two 32-bit hashes for the price of one. +hashlittle() except it returns two 32-bit hashes for the price of one. You could implement hashbig2() if you wanted but I haven't bothered here. If you want to find a hash of, say, exactly 7 integers, do @@ -35,9 +35,9 @@ If you want to find a hash of, say, exactly 7 integers, do then use c as the hash value. If you have a variable length array of 4-byte integers to hash, use hashword(). If you have a byte array (like a character string), use hashlittle(). If you have several byte arrays, or -a mix of things, see the comments above hashlittle(). +a mix of things, see the comments above hashlittle(). -Why is this so big? I read 12 bytes at a time into 3 4-byte integers, +Why is this so big? I read 12 bytes at a time into 3 4-byte integers, then mix those integers. This is fast (you can do a lot more thorough mixing with 12*3 instructions on 3 integers than you can with 3 instructions on 1 byte), but shoehorning those bytes into integers efficiently is messy. @@ -126,7 +126,7 @@ This was tested for: the output delta to a Gray code (a^(a>>1)) so a string of 1's (as is commonly produced by subtraction) look like a single 1-bit difference. -* the base values were pseudorandom, all zero but one bit set, or +* the base values were pseudorandom, all zero but one bit set, or all zero plus a counter that starts at zero. Some k values for my "a-=c; a^=rot(c,k); c+=b;" arrangement that @@ -136,7 +136,7 @@ satisfy this are 14 9 3 7 17 3 Well, "9 15 3 18 27 15" didn't quite get 32 bits diffing for "differ" defined as + with a one-bit base and a two-bit delta. I -used http://burtleburtle.net/bob/hash/avalanche.html to choose +used http://burtleburtle.net/bob/hash/avalanche.html to choose the operations, constants, and arrangements of the variables. This does not achieve avalanche. There are input bits of (a,b,c) @@ -175,7 +175,7 @@ produce values of c that look totally different. This was tested for the output delta to a Gray code (a^(a>>1)) so a string of 1's (as is commonly produced by subtraction) look like a single 1-bit difference. -* the base values were pseudorandom, all zero but one bit set, or +* the base values were pseudorandom, all zero but one bit set, or all zero plus a counter that starts at zero. These constants passed: @@ -234,7 +234,7 @@ uint32_t initval) /* the previous hash, or an arbitrary value */ /*------------------------------------------- handle the last 3 uint32_t's */ switch(length) /* all the case statements fall through */ - { + { case 3 : c+=k[2]; /* fallthrough */ case 2 : b+=k[1]; @@ -255,7 +255,7 @@ uint32_t initval) /* the previous hash, or an arbitrary value */ -------------------------------------------------------------------- hashword2() -- same as hashword(), but take two seeds and return two 32-bit values. pc and pb must both be nonnull, and *pc and *pb must -both be initialized with seeds. If you pass in (*pb)==0, the output +both be initialized with seeds. If you pass in (*pb)==0, the output (*pc) will be the same as the return value from hashword(). -------------------------------------------------------------------- */ @@ -284,7 +284,7 @@ uint32_t *pb) /* IN: more seed OUT: secondary hash value */ /*------------------------------------------- handle the last 3 uint32_t's */ switch(length) /* all the case statements fall through */ - { + { case 3 : c+=k[2]; case 2 : b+=k[1]; case 1 : a+=k[0]; @@ -352,7 +352,7 @@ uint32_t hashlittle( const void *key, size_t length, uint32_t initval) } /*----------------------------- handle the last (probably partial) block */ - /* + /* * "k[2]&0xffffff" actually reads beyond the end of the string, but * then masks off the part it's not allowed to read. Because the * string is aligned, the masked-off tail is in the same word as the @@ -519,7 +519,7 @@ uint32_t hashlittle( const void *key, size_t length, uint32_t initval) * the key. *pc is better mixed than *pb, so use *pc first. If you want * a 64-bit value do something like "*pc + (((uint64_t)*pb)<<32)". */ -void hashlittle2( +void hashlittle2( const void *key, /* the key to hash */ size_t length, /* length of the key */ uint32_t *pc, /* IN: primary initval, OUT: primary hash */ @@ -551,7 +551,7 @@ void hashlittle2( } /*----------------------------- handle the last (probably partial) block */ - /* + /* * "k[2]&0xffffff" actually reads beyond the end of the string, but * then masks off the part it's not allowed to read. Because the * string is aligned, the masked-off tail is in the same word as the @@ -703,7 +703,7 @@ void hashlittle2( * hashbig(): * This is the same as hashword() on big-endian machines. It is different * from hashlittle() on all machines. hashbig() takes advantage of - * big-endian byte ordering. + * big-endian byte ordering. */ uint32_t hashbig( const void *key, size_t length, uint32_t initval) { @@ -732,7 +732,7 @@ uint32_t hashbig( const void *key, size_t length, uint32_t initval) } /*----------------------------- handle the last (probably partial) block */ - /* + /* * "k[2]<<8" actually reads beyond the end of the string, but * then shifts out the part it's not allowed to read. Because the * string is aligned, the illegal read is in the same word as the @@ -843,7 +843,7 @@ void driver1() time(&a); for (i=0; i<256; ++i) buf[i] = 'x'; - for (i=0; i<1; ++i) + for (i=0; i<1; ++i) { h = hashlittle(&buf[0],1,h); } @@ -879,7 +879,7 @@ void driver2() /*---- check that every output bit is affected by that input bit */ for (k=0; kz) z=k; - if (k==MAXPAIR) + if (k==MAXPAIR) { printf("Some bit didn't change: "); printf("%.8x %.8x %.8x %.8x %.8x %.8x ", @@ -990,7 +990,7 @@ void driver3() i=47, j=0; hashword2(&len, 1, &i, &j); if (hashword(&len, 1, 47) != i) - printf("hashword2 and hashword mismatch %x %x\n", + printf("hashword2 and hashword mismatch %x %x\n", i, hashword(&len, 1, 47)); /* check hashlittle doesn't read before or after the ends of the string */ @@ -1007,7 +1007,7 @@ void driver3() *(b-1)=(uint8_t)~0; x = hashlittle(b, len, (uint32_t)1); y = hashlittle(b, len, (uint32_t)1); - if ((ref != x) || (ref != y)) + if ((ref != x) || (ref != y)) { printf("alignment error: %.8x %.8x %.8x %d %d\n",ref,x,y, h, i); diff --git a/usr.sbin/nsd/lookup3.h b/usr.sbin/nsd/lookup3.h index 59dad7c48..ab6d990b6 100644 --- a/usr.sbin/nsd/lookup3.h +++ b/usr.sbin/nsd/lookup3.h @@ -4,22 +4,22 @@ * Copyright (c) 2007, NLnet Labs. All rights reserved. * * This software is open source. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: - * + * * Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. - * + * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. - * + * * Neither the name of the NLNET LABS nor the names of its contributors may * be used to endorse or promote products derived from this software without * specific prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR diff --git a/usr.sbin/nsd/mini_event.c b/usr.sbin/nsd/mini_event.c index 4df420f9f..4fbac7630 100644 --- a/usr.sbin/nsd/mini_event.c +++ b/usr.sbin/nsd/mini_event.c @@ -2,24 +2,24 @@ * mini_event.c - implementation of part of libevent api, portably. * * Copyright (c) 2007, NLnet Labs. All rights reserved. - * + * * This software is open source. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: - * + * * Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. - * + * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. - * + * * Neither the name of the NLNET LABS nor the names of its contributors may * be used to endorse or promote products derived from this software without * specific prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -31,7 +31,7 @@ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * */ /** @@ -52,7 +52,7 @@ #ifdef HAVE_WINSOCK2_H #define FD_SET_T (u_int) #else -#define FD_SET_T +#define FD_SET_T #endif #include @@ -123,7 +123,7 @@ event_init(time_t* time_secs, struct timeval* time_tv) if((int)FD_SETSIZE < base->capfd) base->capfd = (int)FD_SETSIZE; #endif - base->fds = (struct event**)calloc((size_t)base->capfd, + base->fds = (struct event**)calloc((size_t)base->capfd, sizeof(struct event*)); if(!base->fds) { event_base_free(base); @@ -157,7 +157,7 @@ event_get_method(void) /** call timeouts handlers, and return how long to wait for next one or -1 */ static int -handle_timeouts(struct event_base* base, struct timeval* now, +handle_timeouts(struct event_base* base, struct timeval* now, struct timeval* wait) { struct event* p; @@ -170,7 +170,7 @@ handle_timeouts(struct event_base* base, struct timeval* now, !=RBTREE_NULL) { #ifndef S_SPLINT_S if(p->ev_timeout.tv_sec > now->tv_sec || - (p->ev_timeout.tv_sec==now->tv_sec && + (p->ev_timeout.tv_sec==now->tv_sec && p->ev_timeout.tv_usec > now->tv_usec)) { /* there is a next larger timeout. wait for it */ wait->tv_sec = p->ev_timeout.tv_sec - now->tv_sec; @@ -179,7 +179,7 @@ handle_timeouts(struct event_base* base, struct timeval* now, wait->tv_usec = 1000000 - (now->tv_usec - p->ev_timeout.tv_usec); } else { - wait->tv_usec = p->ev_timeout.tv_usec + wait->tv_usec = p->ev_timeout.tv_usec - now->tv_usec; } return tofired; @@ -220,7 +220,7 @@ handle_select(struct event_base* base, struct timeval* wait) } if(settime(base) < 0) return -1; - + for(i=0; imaxfd+1; i++) { short bits = 0; if(!base->fds[i] || !(FD_ISSET(i, &base->ready))) { @@ -236,7 +236,7 @@ handle_select(struct event_base* base, struct timeval* wait) } bits &= base->fds[i]->ev_flags; if(bits) { - (*base->fds[i]->ev_callback)(base->fds[i]->ev_fd, + (*base->fds[i]->ev_callback)(base->fds[i]->ev_fd, bits, base->fds[i]->ev_arg); if(ret==0) break; @@ -291,7 +291,7 @@ event_base_dispatch(struct event_base* base) /** exit that loop */ int -event_base_loopexit(struct event_base* base, +event_base_loopexit(struct event_base* base, struct timeval* ATTR_UNUSED(tv)) { base->need_to_exit = 1; @@ -320,7 +320,7 @@ event_base_free(struct event_base* base) /** set content of event */ void -event_set(struct event* ev, int fd, short bits, +event_set(struct event* ev, int fd, short bits, void (*cb)(int, short, void *), void* arg) { ev->node.key = ev; diff --git a/usr.sbin/nsd/mini_event.h b/usr.sbin/nsd/mini_event.h index f88b17745..78684575d 100644 --- a/usr.sbin/nsd/mini_event.h +++ b/usr.sbin/nsd/mini_event.h @@ -2,24 +2,24 @@ * mini-event.h - micro implementation of libevent api, using select() only. * * Copyright (c) 2007, NLnet Labs. All rights reserved. - * + * * This software is open source. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: - * + * * Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. - * + * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. - * + * * Neither the name of the NLNET LABS nor the names of its contributors may * be used to endorse or promote products derived from this software without * specific prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -42,7 +42,7 @@ * * Although limited to select() and a max (1024) open fds, it * is efficient: - * o dispatch call caches fd_sets to use. + * o dispatch call caches fd_sets to use. * o handler calling takes time ~ to the number of fds. * o timeouts are stored in a redblack tree, sorted, so take log(n). * Timeouts are only accurate to the second (no subsecond accuracy). @@ -62,7 +62,7 @@ struct region; #ifndef HAVE_EVENT_BASE_FREE #define HAVE_EVENT_BASE_FREE -#endif +#endif /** event timeout */ #define EV_TIMEOUT 0x01 @@ -95,13 +95,13 @@ struct event_base /** capacity - size of the fds array */ int capfd; /* fdset for read write, for fds ready, and added */ - fd_set + fd_set /** fds for reading */ - reads, + reads, /** fds for writing */ - writes, + writes, /** fds determined ready for use */ - ready, + ready, /** ready plus newly added events. */ content; /** array of 0 - maxsig of ptr to event for it */ diff --git a/usr.sbin/nsd/namedb.c b/usr.sbin/nsd/namedb.c index 772e038b1..2fb6215c7 100644 --- a/usr.sbin/nsd/namedb.c +++ b/usr.sbin/nsd/namedb.c @@ -34,7 +34,7 @@ allocate_domain_info(domain_table_type* table, result = (domain_type *) region_alloc(table->region, sizeof(domain_type)); #ifdef USE_RADIX_TREE - result->dname + result->dname #else result->node.key #endif diff --git a/usr.sbin/nsd/namedb.h b/usr.sbin/nsd/namedb.h index 3143e867d..8e3f44484 100644 --- a/usr.sbin/nsd/namedb.h +++ b/usr.sbin/nsd/namedb.h @@ -364,7 +364,7 @@ zone_type *namedb_find_zone(namedb_type *db, const dname_type *dname); /* * Delete a domain name from the domain table. Removes dname_info node. * Only deletes if usage is 0, has no rrsets and no children. Checks parents - * for deletion as well. Adjusts numberlist(domain.number), and + * for deletion as well. Adjusts numberlist(domain.number), and * wcard_child closest match. */ void domain_table_deldomain(namedb_type* db, domain_type* domain); diff --git a/usr.sbin/nsd/netio.c b/usr.sbin/nsd/netio.c index 58fd2e18b..62577f996 100644 --- a/usr.sbin/nsd/netio.c +++ b/usr.sbin/nsd/netio.c @@ -199,7 +199,7 @@ netio_dispatch(netio_type *netio, const struct timespec *timeout, const sigset_t #endif /* HAVE_PPOLL */ if (rc == -1) { if(errno == EINVAL || errno == EACCES || errno == EBADF) { - log_msg(LOG_ERR, "fatal error poll: %s.", + log_msg(LOG_ERR, "fatal error poll: %s.", strerror(errno)); exit(1); } diff --git a/usr.sbin/nsd/nsd-checkconf.8.in b/usr.sbin/nsd/nsd-checkconf.8.in index ac23b1bb7..9d1032480 100644 --- a/usr.sbin/nsd/nsd-checkconf.8.in +++ b/usr.sbin/nsd/nsd-checkconf.8.in @@ -22,8 +22,8 @@ .I configfile .SH "DESCRIPTION" .B nsd\-checkconf -reads a configuration file. It prints parse errors to standard -error, and performs additional checks on the contents. The +reads a configuration file. It prints parse errors to standard +error, and performs additional checks on the contents. The configfile format is described in nsd.conf(5). .P The utility of this program is to check a config file for errors before @@ -33,8 +33,8 @@ access the nsd config file, using the \-o and \-z options. .SH "OPTIONS" .TP .B \-v -After reading print the options to standard output in configfile -format. Without this option, only success or parse errors are +After reading print the options to standard output in configfile +format. Without this option, only success or parse errors are reported. .TP .B \-f @@ -46,12 +46,12 @@ Print usage help information and exit. .TP .B \-o\fI option Return only this option from the config file. This option can -be used in conjunction with the +be used in conjunction with the .B \-z and the .B \-p option, or without them to query the server: section. -The special value +The special value .I zones prints out a list of configured zones. The special value @@ -61,13 +61,13 @@ prints out a list of configured patterns. .RS This option can be used to parse the config file from the shell. If the .B \-z -option is given, but the -.B \-o -option is not given, nothing is printed. +option is given, but the +.B \-o +option is not given, nothing is printed. .RE .TP .B \-s\fI keyname -Prints the key secret (base64 blob) configured for this key in the +Prints the key secret (base64 blob) configured for this key in the config file. Used to help shell scripts parse the config file. .TP .B \-t\fI tls-auth @@ -75,12 +75,12 @@ Prints the authentication domain name configured for this tls-auth clause in the config file. Used to help shell scripts parse the config file. .TP .B \-p\fI pattern -Return the option specified with +Return the option specified with .B \-o for the given pattern name. .TP .B \-z\fI zonename -Return the option specified with +Return the option specified with .B \-o for zone 'zonename'. .P @@ -90,7 +90,7 @@ is used. .RE .P .RS -The \-o, \-s and \-z option print configfile options to standard output. +The \-o, \-s and \-z option print configfile options to standard output. .RE .SH "FILES" .TP diff --git a/usr.sbin/nsd/nsd-control.8.in b/usr.sbin/nsd/nsd-control.8.in index 76734e1b3..2a1208d98 100644 --- a/usr.sbin/nsd/nsd-control.8.in +++ b/usr.sbin/nsd/nsd-control.8.in @@ -7,9 +7,9 @@ \- NSD remote server control utility. .SH "SYNOPSIS" .B nsd\-control -.RB [ \-c +.RB [ \-c .IR cfgfile ] -.RB [ \-s +.RB [ \-s .IR server ] .IR command .SH "DESCRIPTION" @@ -34,7 +34,7 @@ address is read from the config file. There are several commands that the server understands. .TP .B start -Start the server. Simply execs \fInsd\fR(8). The nsd executable +Start the server. Simply execs \fInsd\fR(8). The nsd executable is not searched for in the \fBPATH\fR set in the environment. Instead the default location relative to the installation prefix specified at compile-time. The executable location can be overridden by setting @@ -67,7 +67,7 @@ and create a new logfile. The log can also be reopened with kill \-HUP (which also reloads all zonefiles). .TP .B status -Display server status. Exit code 3 if not running (the connection to the +Display server status. Exit code 3 if not running (the connection to the port is refused), 1 on error, 0 if running. .TP .B stats @@ -223,13 +223,13 @@ Show the current configured cookie secrets with their status. .SH "EXIT CODE" The nsd\-control program exits with status code 1 on error, 0 on success. .SH "SET UP" -The setup requires a self\-signed certificate and private keys for both +The setup requires a self\-signed certificate and private keys for both the server and client. The script \fInsd\-control\-setup\fR generates these in the default run directory, or with \-d in another directory. If you change the access control permissions on the key files you can decide who can use nsd\-control, by default owner and group but not all users. The script preserves private keys present in the directory. -After running the script as root, turn on \fBcontrol\-enable\fR in +After running the script as root, turn on \fBcontrol\-enable\fR in \fInsd.conf\fR. .SH "STATISTIC COUNTERS" The \fIstats\fR command shows a number of statistic counters. @@ -339,6 +339,6 @@ nsd configuration file. directory with private keys (nsd_server.key and nsd_control.key) and self\-signed certificates (nsd_server.pem and nsd_control.pem). .SH "SEE ALSO" -\fInsd.conf\fR(5), +\fInsd.conf\fR(5), \fInsd\fR(8), \fInsd\-checkconf\fR(8) diff --git a/usr.sbin/nsd/nsd-control.c b/usr.sbin/nsd/nsd-control.c index ddd380d08..e42685aa4 100644 --- a/usr.sbin/nsd/nsd-control.c +++ b/usr.sbin/nsd/nsd-control.c @@ -4,22 +4,22 @@ * Copyright (c) 2011, NLnet Labs. All rights reserved. * * This software is open source. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: - * + * * Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. - * + * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. - * + * * Neither the name of the NLNET LABS nor the names of its contributors may * be used to endorse or promote products derived from this software without * specific prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -272,7 +272,7 @@ contact_server(const char* svr, struct nsd_options* cfg, int statuscmd) fprintf(stderr, "could not parse port %s\n", ps); exit(1); } - } + } if(svr[0] == '/') { #ifdef HAVE_SYS_UN_H struct sockaddr_un* usock = (struct sockaddr_un *) &addr; diff --git a/usr.sbin/nsd/nsd.8.in b/usr.sbin/nsd/nsd.8.in index 38b36e648..df3d1bc58 100644 --- a/usr.sbin/nsd/nsd.8.in +++ b/usr.sbin/nsd/nsd.8.in @@ -6,16 +6,16 @@ \- Name Server Daemon (NSD) version 4.7.0. .SH "SYNOPSIS" .B nsd -.RB [ \-4 ] -.RB [ \-6 ] -.RB [ \-a +.RB [ \-4 ] +.RB [ \-6 ] +.RB [ \-a .IR ip\-address[@port] ] .RB [ \-c .IR configfile ] -.RB [ \-d ] +.RB [ \-d ] .RB [ \-f .IR database ] -.RB [ \-h ] +.RB [ \-h ] .RB [ \-i .IR identity ] .RB [ \-I @@ -41,40 +41,40 @@ .RB [ \-v ] .SH "DESCRIPTION" .B NSD -is a complete implementation of an authoritative DNS nameserver. +is a complete implementation of an authoritative DNS nameserver. Upon startup, .B NSD -will read the database specified with +will read the database specified with .B \-f .I database -argument and put itself into background and answers queries on port -53 or a different port specified with +argument and put itself into background and answers queries on port +53 or a different port specified with .B \-p .I port option. The .I database is created if it does not exist. By default, -.B NSD -will bind to all local interfaces available. Use the +.B NSD +will bind to all local interfaces available. Use the .B \-a .I ip\-address[@port] option to specify a single particular interface address to be bound. If this option is given more than once, .B NSD will bind its UDP and TCP sockets to all the specified ip\-addresses -separately. If IPv6 is enabled when -.B NSD +separately. If IPv6 is enabled when +.B NSD is compiled an IPv6 address can also be specified. .P .SH "OPTIONS" All the options can be specified in the configfile ( -.B \-c -argument), except for the -.B \-v -and -.B \-h -options. If options are specified on the commandline, the options -on the commandline take precedence over the options in the +.B \-c +argument), except for the +.B \-v +and +.B \-h +options. If options are specified on the commandline, the options +on the commandline take precedence over the options in the configfile. .P Normally @@ -97,12 +97,12 @@ The must be specified in numeric format (using the standard IPv4 or IPv6 notation). Optionally, a port number can be given. This flag can be specified multiple times to listen to -multiple IP addresses. If this flag is not specified, +multiple IP addresses. If this flag is not specified, .B NSD listens to the wildcard interface. .TP .B \-c\fI configfile -Read specified +Read specified .I configfile instead of the default .IR @nsdconfigfile@ . @@ -116,9 +116,9 @@ Use the specified .I database instead of the default of .IR '@dbfile@' . -If a -.B zonesdir: -is specified in the config file this path can be relative to that +If a +.B zonesdir: +is specified in the config file this path can be relative to that directory. .TP .B \-h @@ -135,24 +135,24 @@ when they are anycast). The default is the name returned by gethostname(3). .B \-I\fI nsid Add the specified .I nsid -to the EDNS section of the answer when queried with an NSID EDNS +to the EDNS section of the answer when queried with an NSID EDNS enabled packet. As a sequence of hex characters or with ascii_ prefix and then an ascii string. .TP .B \-l\fI logfile -Log messages to the specified +Log messages to the specified .IR logfile . -The default is to log to stderr and syslog. If a -.B zonesdir: -is specified in the config file this path can be relative to that +The default is to log to stderr and syslog. If a +.B zonesdir: +is specified in the config file this path can be relative to that directory. .TP .B \-N\fI count Start .I count -.B NSD -servers. The default is 1. Starting more than a single server is -only useful on machines with multiple CPUs and/or network adapters. +.B NSD +servers. The default is 1. Starting more than a single server is +only useful on machines with multiple CPUs and/or network adapters. .TP .B \-n\fI number The maximum @@ -165,9 +165,9 @@ Use the specified .I pidfile instead of the platform specific default, which is mostly .IR @pidfile@ . -If a -.B zonesdir: -is specified in the config file, this path can be relative to that +If a +.B zonesdir: +is specified in the config file, this path can be relative to that directory. .TP .B \-p\fI port @@ -176,18 +176,18 @@ Answer the queries on the specified Normally this is port 53. .TP .B \-s\fI seconds -Produce statistics dump every +Produce statistics dump every .I seconds seconds. This is equal to sending .I SIGUSR1 to the daemon periodically. .TP .B \-t\fI chroot -Specifies a directory to -.I chroot -to upon startup. This option requires you to ensure that appropriate +Specifies a directory to +.I chroot +to upon startup. This option requires you to ensure that appropriate syslogd(8) socket (e.g. -.I chrootdir +.I chrootdir /dev/log) is available, otherwise .B NSD won't produce any log output. @@ -198,16 +198,16 @@ Drop user and group privileges to those of after binding the socket. The .I username -must be one of: username, id, or id.gid. For example: nsd, 80, or +must be one of: username, id, or id.gid. For example: nsd, 80, or 80.80. .TP .B \-V\fI level -This value specifies the verbosity level for (non\-debug) logging. +This value specifies the verbosity level for (non\-debug) logging. Default is 0. .TP .B \-v -Print the version number of -.B NSD +Print the version number of +.B NSD to standard error and exit. .LP .B NSD @@ -215,7 +215,7 @@ reacts to the following signals: .TP SIGTERM Stop answering queries, shutdown, and exit normally. -.TP +.TP SIGHUP Reload. Scans zone files and if changed (mtime) reads them in. Also reopens the logfile (assists logrotation). diff --git a/usr.sbin/nsd/nsd.conf.5.in b/usr.sbin/nsd/nsd.conf.5.in index 6780ea7e8..ea3a03919 100644 --- a/usr.sbin/nsd/nsd.conf.5.in +++ b/usr.sbin/nsd/nsd.conf.5.in @@ -8,16 +8,16 @@ .B nsd.conf .SH "DESCRIPTION" .B Nsd.conf -is used to configure nsd(8). The file format has attributes and -values. Some attributes have attributes inside them. The notation -is: attribute: value. +is used to configure nsd(8). The file format has attributes and +values. Some attributes have attributes inside them. The notation +is: attribute: value. .PP Comments start with # and last to the end of line. Empty lines are ignored as is whitespace at the beginning of a line. Quotes can be used, for names with spaces, eg. "file name.zone". .PP .B Nsd.conf -specifies options for the nsd server, zone files, primaries and +specifies options for the nsd server, zone files, primaries and secondaries. .SH "EXAMPLE" An example of a short nsd.conf file is below. @@ -55,7 +55,7 @@ zone: name: example.com .RE .RS 5 -zonefile: @configdir@/example.com.zone +zonefile: @configdir@/example.com.zone .RE .TP zone: @@ -66,7 +66,7 @@ zone: name: masterzone.com .RE .RS 5 -zonefile: @configdir@/masterzone.com.zone +zonefile: @configdir@/masterzone.com.zone .RE .RS 5 notify: 192.0.2.1 NOKEY @@ -83,7 +83,7 @@ zone: name: secondzone.com .RE .RS 5 -zonefile: @configdir@/secondzone.com.zone +zonefile: @configdir@/secondzone.com.zone .RE .RS 5 allow-notify: 192.0.2.2 NOKEY @@ -95,11 +95,11 @@ request-xfr: 192.0.2.2 NOKEY Then, use kill \-HUP to reload changes from master zone files. And use kill \-TERM to stop the server. .SH "FILE FORMAT" -There must be whitespace between keywords. Attribute keywords end -with a colon ':'. An attribute is followed by its containing -attributes, or a value. +There must be whitespace between keywords. Attribute keywords end +with a colon ':'. An attribute is followed by its containing +attributes, or a value. .P -At the top level only +At the top level only .BR server: , .BR verify: , .BR key: , @@ -110,22 +110,22 @@ and .B remote-control: are allowed. These are followed by their attributes or a new top-level keyword. The .B zone: -attribute is followed by zone options. The -.B server: -attribute is followed by global options for the -.B NSD +attribute is followed by zone options. The +.B server: +attribute is followed by global options for the +.B NSD server. The .B verify: attribute is used to control zone verification. A -.B key: +.B key: attribute is used to define keys for authentication. The .B pattern: attribute is followed by the zone options for zones that use the pattern. -A +A .B tls-auth: attribute is used to define credentials for authenticating an outgoing TLS connection used for XFR-over-TLS. .P -Files can be included using the +Files can be included using the .B include: directive. It can appear anywhere, and takes a single filename as an argument. Processing continues as if the text from the included file @@ -138,15 +138,15 @@ and '~' work, see \fBglob\fR(7). If no files match the pattern, this is not an error. .SS "Server Options" .LP -The global options (if not overridden from the NSD commandline) are -taken from the -.B server: -clause. There may only be one -.B server: +The global options (if not overridden from the NSD commandline) are +taken from the +.B server: +clause. There may only be one +.B server: clause. .TP .B ip\-address:\fR [@port] [servers] [bindtodevice] [setfib] -NSD will bind to the listed ip\-address. Can be given multiple times +NSD will bind to the listed ip\-address. Can be given multiple times to bind multiple ip\-addresses. Optionally, a port number can be given. If none are given NSD listens to the wildcard interface. Same as commandline option .BR \-a. @@ -183,7 +183,7 @@ that are down. Similar to ip\-transparent. Default is no. Use the SO_REUSEPORT socket option, and create file descriptors for every server in the server\-count. This improves performance of the network stack. Only really useful if you also configure a server\-count higher -than 1 (such as, equal to the number of cpus). The default is no. +than 1 (such as, equal to the number of cpus). The default is no. It works on Linux, but does not work on FreeBSD, and likely does not work on other systems. .TP @@ -194,7 +194,7 @@ Set the send buffer size for query-servicing sockets. Set to 0 to use the defau Set the receive buffer size for query-servicing sockets. Set to 0 to use the default settings. .TP .B debug\-mode:\fR -Turns on debugging mode for nsd, does not fork a daemon process. +Turns on debugging mode for nsd, does not fork a daemon process. Default is no. Same as commandline option .BR \-d. If set to yes it does not fork and stays in the foreground, which can @@ -208,16 +208,16 @@ If yes, NSD listens to IPv4 connections. Default yes. If yes, NSD listens to IPv6 connections. Default yes. .TP .B database:\fR -By default +By default .I '@dbfile@' -is used. The specified file is used to store the compiled -zone information. Same as commandline option +is used. The specified file is used to store the compiled +zone information. Same as commandline option .BR \-f. If set to "" then no database is used. This uses less memory but zone updates are not (immediately) spooled to disk. .TP .B zonelistfile:\fR -By default +By default .I @zonelistfile@ is used. The specified file is used to store the dynamically added list of zones. The list is written to by NSD to add and delete zones. @@ -225,9 +225,9 @@ It is a text file with a zone\-name and pattern\-name on each line. This file is used for the nsd\-control addzone and delzone commands. .TP .B identity:\fR -Returns the specified identity when asked for CH TXT ID.SERVER. -Default is the name as returned by gethostname(3). Same as -commandline option +Returns the specified identity when asked for CH TXT ID.SERVER. +Default is the name as returned by gethostname(3). Same as +commandline option .BR \-i . See hide\-identity to set the server to not respond to such queries. .TP @@ -243,8 +243,8 @@ with ascii_ prefix and then an ascii string. Same as commandline option .BR \-I . .TP .B logfile:\fR -Log messages to the logfile. The default is to log to stderr and -syslog (with facility LOG_DAEMON). Same as commandline option +Log messages to the logfile. The default is to log to stderr and +syslog (with facility LOG_DAEMON). Same as commandline option .BR \-l . .TP .B log\-only\-syslog:\fR @@ -254,7 +254,7 @@ been opened, the server uses stderr. Stderr is also used if syslog is not available. Default is no. .TP .B server\-count:\fR -Start this many NSD servers. Default is 1. Same as commandline +Start this many NSD servers. Default is 1. Same as commandline option .BR \-N . .TP @@ -275,7 +275,7 @@ enabled. .BR \-n .TP .B tcp\-count:\fR -The maximum number of concurrent, active TCP connections by each server. +The maximum number of concurrent, active TCP connections by each server. Default is 100. Same as commandline option .BR \-n . .TP @@ -293,7 +293,7 @@ The default is 120 seconds. .TP .B tcp-mss:\fR Maximum segment size (MSS) of TCP socket on which the server responds -to queries. Value lower than common MSS on Ethernet +to queries. Value lower than common MSS on Ethernet (1220 for example) will address path MTU problem. Note that not all platform supports socket option to set MSS (TCP_MAXSEG). Default is system default MSS determined by interface MTU and @@ -331,21 +331,21 @@ Preferred EDNS buffer size for IPv4. Default 1232. Preferred EDNS buffer size for IPv6. Default 1232. .TP .B pidfile:\fR -Use the pid file instead of the platform specific default, usually -.IR @pidfile@. -Same as commandline option +Use the pid file instead of the platform specific default, usually +.IR @pidfile@. +Same as commandline option .BR \-P . With "" there is no pidfile, for some startup management setups, where a pidfile is not useful to have. .TP .B port:\fR -Answer queries on the specified port. Default is 53. Same as -commandline option +Answer queries on the specified port. Default is 53. Same as +commandline option .BR \-p . .TP .B statistics:\fR -If not present no statistics are dumped. Statistics are produced -every number seconds. Same as commandline option +If not present no statistics are dumped. Statistics are produced +every number seconds. Same as commandline option .BR \-s . .TP .B chroot:\fR @@ -355,12 +355,12 @@ inside the chroot, you have to prepend the \fBchroot\fR path. That way, you can switch the chroot option on and off without having to modify anything else in the configuration. Set the value to "" (the empty string) to disable the chroot. By default "\fI@chrootdir@\fR" is used. Same as -commandline option +commandline option .BR \-t . .TP .B username:\fR -After binding the socket, drop user privileges and assume the -username. Can be username, id or id.gid. Same as commandline option +After binding the socket, drop user privileges and assume the +username. Can be username, id or id.gid. Same as commandline option .BR \-u . .TP .B zonesdir:\fR @@ -374,7 +374,7 @@ to disable the change of working directory. By default "\fI@zonesdir@\fR" is used. .TP .B difffile:\fR -Ignored, for compatibility with NSD3 config files. +Ignored, for compatibility with NSD3 config files. .TP .B xfrdfile:\fR The soa timeout and zone transfer daemon in NSD will save its state to @@ -391,14 +391,14 @@ is created here that is removed when NSD exits. Default is .IR @xfrdir@ . .TP .B xfrd\-reload\-timeout:\fR -If this value is \-1, xfrd will not trigger a reload after a zone -transfer. If positive xfrd will trigger a reload after a zone -transfer, then it will wait for the number of seconds before it will -trigger a new reload. Setting this value throttles the reloads to +If this value is \-1, xfrd will not trigger a reload after a zone +transfer. If positive xfrd will trigger a reload after a zone +transfer, then it will wait for the number of seconds before it will +trigger a new reload. Setting this value throttles the reloads to once per the number of seconds. The default is 1 second. .TP .B verbosity:\fR -This value specifies the verbosity level for (non\-debug) logging. +This value specifies the verbosity level for (non\-debug) logging. Default is 0. 1 gives more information about incoming notifies and zone transfers. 2 lists soft warnings that are encountered. 3 prints more information. @@ -414,11 +414,11 @@ Verbosity 2 prints additionally soft errors, like connection resets over TCP. And notify refusal, and axfr request refusals. .TP .B hide\-version:\fR -Prevent NSD from replying with the version string on CHAOS class +Prevent NSD from replying with the version string on CHAOS class queries. Default is no. .TP .B hide\-identity:\fR -Prevent NSD from replying with the identity string on CHAOS class +Prevent NSD from replying with the identity string on CHAOS class queries. Default is no. .TP .B drop\-updates:\fR @@ -449,7 +449,7 @@ The default is yes. .B confine\-to\-zone:\fR If set to yes, additional information will not be added to the response if the apex zone of the additional information does not match the apex zone of the -initial query (E.G. CNAME resolution). Default is no. +initial query (E.G. CNAME resolution). Default is no. .TP .B refuse\-any:\fR Refuse queries of type ANY. This is useful to stop query floods trying @@ -494,7 +494,7 @@ the zone\-specific ratelimit options are updated). .TP .B rrl\-slip:\fR This option controls the number of packets discarded before we send back a SLIP response -(a response with "truncated" bit set to one). 0 disables the sending of SLIP packets, +(a response with "truncated" bit set to one). 0 disables the sending of SLIP packets, 1 means every query will get a SLIP response. Default is 2, cuts traffic in half and legit users have a fair chance to get a +TC response. .TP @@ -748,10 +748,10 @@ and can be given. They are applied to the patterns and zones that include this pattern. .SS "Zone Options" -.LP -For every zone the options need to be specified in one -.B zone: -clause. The access control list elements can be given multiple +.LP +For every zone the options need to be specified in one +.B zone: +clause. The access control list elements can be given multiple times to add multiple servers. These elements need to be added explicitly. .LP @@ -761,9 +761,9 @@ and they cannot be deleted via delzone, but remove them from the config file and repattern. .TP .B name:\fR -The name of the zone. This is the domain name of the apex of the -zone. May end with a '.' (in FQDN notation). For example -"example.com", "sub.example.net.". This attribute must be present in +The name of the zone. This is the domain name of the apex of the +zone. May end with a '.' (in FQDN notation). For example +"example.com", "sub.example.net.". This attribute must be present in each zone. .TP .B zonefile:\fR @@ -801,49 +801,49 @@ scanned for a match in the order of the statements. Without without TSIG key (which is the default). .P .RS -The ip\-spec is either a plain IP address (IPv4 or IPv6), or can be -a subnet of the form 1.2.3.4/24, or masked like -1.2.3.4&255.255.255.0 or a range of the form 1.2.3.4\-1.2.3.25. -Note the ip\-spec ranges do not use spaces around the /, &, @ and \- +The ip\-spec is either a plain IP address (IPv4 or IPv6), or can be +a subnet of the form 1.2.3.4/24, or masked like +1.2.3.4&255.255.255.0 or a range of the form 1.2.3.4\-1.2.3.25. +Note the ip\-spec ranges do not use spaces around the /, &, @ and \- symbols. .RE .TP .B allow\-notify:\fR -Access control list. The listed (primary) address is allowed to -send notifies to this (secondary) server. Notifies from unlisted or -specifically BLOCKED addresses are discarded. If NOKEY is given no +Access control list. The listed (primary) address is allowed to +send notifies to this (secondary) server. Notifies from unlisted or +specifically BLOCKED addresses are discarded. If NOKEY is given no TSIG signature is required. BLOCKED supersedes other entries, other entries are scanned for a match in the order of the statements. .P .RS -The ip\-spec is either a plain IP address (IPv4 or IPv6), or can be -a subnet of the form 1.2.3.4/24, or masked like -1.2.3.4&255.255.255.0 or a range of the form 1.2.3.4\-1.2.3.25. -A port number can be added using a suffix of @number, for example +The ip\-spec is either a plain IP address (IPv4 or IPv6), or can be +a subnet of the form 1.2.3.4/24, or masked like +1.2.3.4&255.255.255.0 or a range of the form 1.2.3.4\-1.2.3.25. +A port number can be added using a suffix of @number, for example 1.2.3.4@5300 or 1.2.3.4/24@5300 for port 5300. -Note the ip\-spec ranges do not use spaces around the /, &, @ and \- +Note the ip\-spec ranges do not use spaces around the /, &, @ and \- symbols. .RE .TP .B request\-xfr:\fR [AXFR|UDP] [tls\-auth\-name] -Access control list. The listed address (the master) is queried for +Access control list. The listed address (the master) is queried for AXFR/IXFR on update. A port number can be added using a suffix of @number, for example 1.2.3.4@5300. The specified key is used during AXFR/IXFR. If tls-auth-name is included, the specified tls-auth clause will be used to perform authenticated XFR-over-TLS. .P .RS -If the AXFR option is given, the server will not be contacted with -IXFR queries but only AXFR requests will be made to the server. This -allows an NSD secondary to have a master server that runs NSD. If -the AXFR option is left out then both IXFR and AXFR requests are +If the AXFR option is given, the server will not be contacted with +IXFR queries but only AXFR requests will be made to the server. This +allows an NSD secondary to have a master server that runs NSD. If +the AXFR option is left out then both IXFR and AXFR requests are made to the master server. .P -If the UDP option is given, the secondary will use UDP to transmit the IXFR +If the UDP option is given, the secondary will use UDP to transmit the IXFR requests. You should deploy TSIG when allowing UDP transport, to authenticate -notifies and zone transfers. Otherwise, NSD is more vulnerable for -Kaminsky\-style attacks. If the UDP option is left out then IXFR will be +notifies and zone transfers. Otherwise, NSD is more vulnerable for +Kaminsky\-style attacks. If the UDP option is left out then IXFR will be transmitted using TCP. .P If a tls-auth-name is given then TLS (by default on port 853) will be used @@ -853,7 +853,7 @@ not be sent. Support for TLS 1.3 is required for XFR-over-TLS. .RE .TP .B allow\-axfr\-fallback:\fR -This option should be accompanied by request\-xfr. It (dis)allows NSD (as secondary) +This option should be accompanied by request\-xfr. It (dis)allows NSD (as secondary) to fallback to AXFR if the primary name server does not support IXFR. Default is yes. .TP .B size\-limit\-xfr:\fR @@ -861,11 +861,11 @@ This option should be accompanied by request\-xfr. It specifies XFR temporary fi If this option is 0, unlimited. Default value is 0. .TP .B notify:\fR -Access control list. The listed address (a secondary) is notified +Access control list. The listed address (a secondary) is notified of updates to this zone. A port number can be added using a suffix of @number, -for example 1.2.3.4@5300. The specified key is used to sign the -notify. Only on secondary configurations will NSD be able to detect -zone updates (as it gets notified itself, or refreshes after a +for example 1.2.3.4@5300. The specified key is used to sign the +notify. Only on secondary configurations will NSD be able to detect +zone updates (as it gets notified itself, or refreshes after a time). .TP .B notify\-retry:\fR @@ -873,9 +873,9 @@ This option should be accompanied by notify. It sets the number of retries when sending notifies. .TP .B provide\-xfr:\fR -Access control list. The listed address (a secondary) is allowed to -request AXFR from this server. Zone data will be provided to the -address. The specified key is used during AXFR. For unlisted or +Access control list. The listed address (a secondary) is allowed to +request AXFR from this server. Zone data will be provided to the +address. The specified key is used during AXFR. For unlisted or BLOCKED addresses no data is provided, requests are discarded. BLOCKED supersedes other entries, other entries are scanned for a match in the order of the statements. @@ -883,21 +883,21 @@ NSD provides AXFR for its secondaries, but IXFR is not implemented (IXFR is implemented for request\-xfr, but not for provide\-xfr). .P .RS -The ip\-spec is either a plain IP address (IPv4 or IPv6), or can be -a subnet of the form 1.2.3.4/24, or masked like -1.2.3.4&255.255.255.0 or a range of the form 1.2.3.4\-1.2.3.25. -A port number can be added using a suffix of @number, for example -1.2.3.4@5300 or 1.2.3.4/24@5300 for port 5300. Note the ip\-spec +The ip\-spec is either a plain IP address (IPv4 or IPv6), or can be +a subnet of the form 1.2.3.4/24, or masked like +1.2.3.4&255.255.255.0 or a range of the form 1.2.3.4\-1.2.3.25. +A port number can be added using a suffix of @number, for example +1.2.3.4@5300 or 1.2.3.4/24@5300 for port 5300. Note the ip\-spec ranges do not use spaces around the /, &, @ and \- symbols. .RE .TP .B outgoing\-interface:\fR -Access control list. The listed address is used to request AXFR|IXFR (in case of -a secondary) or used to send notifies (in case of a primary). +Access control list. The listed address is used to request AXFR|IXFR (in case of +a secondary) or used to send notifies (in case of a primary). .P .RS The ip\-address is a plain IP address (IPv4 or IPv6). -A port number can be added using a suffix of @number, for example +A port number can be added using a suffix of @number, for example 1.2.3.4@5300. .RE .TP @@ -1001,9 +1001,9 @@ Number of seconds before verifier is forcefully terminated. Specify 0 (zero) to not use a specific timeout. Default is verifier\-timeout from .B verify:\fR. .SS "Key Declarations" -The -.B key: -clause establishes a key for use in access control lists. It has +The +.B key: +clause establishes a key for use in access control lists. It has the following attributes. .TP .B name:\fR @@ -1019,7 +1019,7 @@ Algorithms are only available when they were compiled in (available in the crypto library). .TP .B secret:\fR -The base64 encoded shared secret. It is possible to put the +The base64 encoded shared secret. It is possible to put the .B secret: declaration (and base64 blob) into a different file, and then to .B include: @@ -1029,10 +1029,10 @@ The content of the secret is the agreed base64 secret content. To make it up, enter a password (its length must be a multiple of 4 characters, A\-Za\-z0\-9), or use dev-random output through a base64 encode filter. .SS "TLS Auth Declarations" -The -.B tls-auth: +The +.B tls-auth: clause establishes authentication attributes to use when authenticating -the far end of an outgoing TLS connection used in access control lists for XFR-over-TLS. +the far end of an outgoing TLS connection used in access control lists for XFR-over-TLS. It has the following attributes. .TP .B name:\fR @@ -1112,17 +1112,17 @@ These are client queries to NSD. Enable to log auth response messages. Default is no. These are responses from NSD to clients. .SH "NSD CONFIGURATION FOR BIND9 HACKERS" -BIND9 is a name server implementation with its own configuration -file format, named.conf(5). BIND9 types zones as 'Master' or 'Slave'. +BIND9 is a name server implementation with its own configuration +file format, named.conf(5). BIND9 types zones as 'Master' or 'Slave'. .SS "Slave zones" -For a slave zone, the master servers are listed. The master servers are -queried for zone data, and are listened to for update notifications. -In NSD these two properties need to be configured separately, by listing -the master address in allow\-notify and request\-xfr statements. +For a slave zone, the master servers are listed. The master servers are +queried for zone data, and are listened to for update notifications. +In NSD these two properties need to be configured separately, by listing +the master address in allow\-notify and request\-xfr statements. .P In BIND9 you only need to provide allow\-notify elements for any extra sources of notifications (i.e. the operators), NSD needs to have -allow\-notify for both masters and operators. BIND9 allows +allow\-notify for both masters and operators. BIND9 allows additional transfer sources, in NSD you list those as request\-xfr. .P Here is an example of a slave zone in BIND9 syntax. @@ -1163,10 +1163,10 @@ masters { 162.0.4.49; }; .RE }; .P -For NSD, DNSSEC is enabled automatically for zones that are signed. The -dnssec\-enable statement in the options clause is not needed. In NSD -keys are associated with an IP address in the access control list -statement, therefore the server{} statement is not needed. Below is +For NSD, DNSSEC is enabled automatically for zones that are signed. The +dnssec\-enable statement in the options clause is not needed. In NSD +keys are associated with an IP address in the access control list +statement, therefore the server{} statement is not needed. Below is the same example in an NSD config file. .LP # Config file for example.org @@ -1194,7 +1194,7 @@ zonefile: "secondary/example.org.signed" # the master is allowed to notify and will provide zone data. .RE .RS 5 -allow\-notify: 162.0.4.49 NOKEY +allow\-notify: 162.0.4.49 NOKEY .RE .RS 5 request\-xfr: 162.0.4.49 tsig.example.org. @@ -1202,15 +1202,15 @@ request\-xfr: 162.0.4.49 tsig.example.org. .P Notice that the master is listed twice, once to allow it to send notifies to this slave server and once to tell the slave server where to look for -updates zone data. More allow\-notify and request\-xfr lines can be +updates zone data. More allow\-notify and request\-xfr lines can be added to specify more masters. .P -It is possible to specify extra allow\-notify lines for addresses +It is possible to specify extra allow\-notify lines for addresses that are also allowed to send notifications to this slave server. .SS "Master zones" For a master zone in BIND9, the slave servers are listed. These slave servers are sent notifications of updated and are allowed to request -transfer of the zone data. In NSD these two properties need to be +transfer of the zone data. In NSD these two properties need to be configured separately. .P Here is an example of a master zone in BIND9 syntax. @@ -1253,11 +1253,11 @@ provide\-xfr: ::0/0 NOKEY # notify: 1.2.3.4 NOKEY .RE .SS "Other" -NSD is an authoritative only DNS server. This means that it is -meant as a primary or secondary server for zones, providing DNS -data to DNS resolvers and caches. BIND9 can function as an -authoritative DNS server, the configuration options for that are -compared with those for NSD in this section. However, BIND9 can +NSD is an authoritative only DNS server. This means that it is +meant as a primary or secondary server for zones, providing DNS +data to DNS resolvers and caches. BIND9 can function as an +authoritative DNS server, the configuration options for that are +compared with those for NSD in this section. However, BIND9 can also function as a resolver or cache. The configuration options that BIND9 has for the resolver or caching thus have no equivalents for NSD. .SH "FILES" @@ -1271,13 +1271,13 @@ database default .B NSD configuration file -.SH "SEE ALSO" +.SH "SEE ALSO" \fInsd\fR(8), \fInsd\-checkconf\fR(8), \fInsd\-control\fR(8) .SH "AUTHORS" .B NSD -was written by NLnet Labs and RIPE NCC joint team. Please see +was written by NLnet Labs and RIPE NCC joint team. Please see CREDITS file in the distribution for further details. .SH "BUGS" .B nsd.conf -is parsed by a primitive parser, error messages may not be to the +is parsed by a primitive parser, error messages may not be to the point. diff --git a/usr.sbin/nsd/nsd.conf.sample.in b/usr.sbin/nsd/nsd.conf.sample.in index 67fdf4cb1..4bf338004 100644 --- a/usr.sbin/nsd/nsd.conf.sample.in +++ b/usr.sbin/nsd/nsd.conf.sample.in @@ -259,7 +259,7 @@ server: # tls-service-pem: "path/to/publiccertfile.pem" # tls-service-ocsp: "path/to/ocsp.pem" # tls-port: 853 - + # Certificates used to authenticate connections made upstream for # Transfers over TLS (XoT). Default is "" (default verify locations). # tls-cert-bundle: "path/to/ca-bundle.pem" @@ -315,7 +315,7 @@ verify: # dnstap-log-auth-query-messages: no # dnstap-log-auth-response-messages: no -# Remote control config section. +# Remote control config section. remote-control: # Enable remote control with nsd-control(8) here. # set up the keys and certificates with nsd-control-setup. @@ -361,10 +361,10 @@ remote-control: # e.g. from dd if=/dev/random of=/dev/stdout count=1 bs=32 | base64 #secret: "K2tf3TRjvQkVCmJF3/Z9vA==" -# The tls-auth clause establishes authentication attributes to use when -# authenticating the far end of an outgoing TLS connection in access control +# The tls-auth clause establishes authentication attributes to use when +# authenticating the far end of an outgoing TLS connection in access control # lists used for XFR-over-TLS. If authentication fails, the XFR request will not -# be made. Support for TLS 1.3 is required for XFR-over-TLS. It has the +# be made. Support for TLS 1.3 is required for XFR-over-TLS. It has the # following attributes: # # tls-auth: @@ -391,7 +391,7 @@ remote-control: # if label or character does not exist you get a dot '.'. # for example "%s.zone" or "zones/%1/%2/%3/%s" or "secondary/%z/%s" #zonefile: "%s.zone" - + # The allow-query allows an access control list to be specified # for a zone to be queried. Without an allow-query option, any # IP address is allowed to send queries for the zone. diff --git a/usr.sbin/nsd/nsec3.c b/usr.sbin/nsd/nsec3.c index 4ed55e68c..96ddf3169 100644 --- a/usr.sbin/nsd/nsec3.c +++ b/usr.sbin/nsd/nsec3.c @@ -409,7 +409,7 @@ hash_tree_clear(rbtree_type* tree) * then mean setting the key value of the nodes to NULL to indicate * absence of the prehash. * But since prehash structs are separatly allocated, this is no longer - * necessary as currently the prehash structs are simply recycled and + * necessary as currently the prehash structs are simply recycled and * NULLed. * * rbnode_type* n; diff --git a/usr.sbin/nsd/options.c b/usr.sbin/nsd/options.c index 7f435adcb..654217f46 100644 --- a/usr.sbin/nsd/options.c +++ b/usr.sbin/nsd/options.c @@ -413,7 +413,7 @@ parse_zone_list_file(struct nsd_options* opt) */ char hdr[64]; char buf[1024]; - + /* create empty data structures */ opt->zonefree = rbtree_create(opt->region, comp_zonebucket); opt->zonelist = NULL; @@ -1025,7 +1025,7 @@ copy_acl_list(struct nsd_options* opt, struct acl_options* a) if(!blist) blist = b; else blast->next = b; blast = b; - + a = a->next; } return blist; @@ -2568,9 +2568,9 @@ resolve_interface_names(struct nsd_options* options) if(getifaddrs(&addrs) == -1) error("failed to list interfaces"); - resolve_interface_names_for_ref(&options->ip_addresses, + resolve_interface_names_for_ref(&options->ip_addresses, addrs, options->region); - resolve_interface_names_for_ref(&options->control_interface, + resolve_interface_names_for_ref(&options->control_interface, addrs, options->region); freeifaddrs(addrs); diff --git a/usr.sbin/nsd/options.h b/usr.sbin/nsd/options.h index a95409111..b6cad8964 100644 --- a/usr.sbin/nsd/options.h +++ b/usr.sbin/nsd/options.h @@ -57,7 +57,7 @@ struct nsd_options { /* tree of zonestat names and their id values, entries are struct * zonestatname with malloced key=stringname. The number of items - * is the max statnameid, no items are freed from this. + * is the max statnameid, no items are freed from this. * kept correct in the xfrd process, and on startup. */ rbtree_type* zonestatnames; diff --git a/usr.sbin/nsd/query.c b/usr.sbin/nsd/query.c index 9b34f029d..394c13afc 100644 --- a/usr.sbin/nsd/query.c +++ b/usr.sbin/nsd/query.c @@ -1317,7 +1317,7 @@ answer_lookup_zone(struct nsd *nsd, struct query *q, answer_type *answer, why->ip_address_spec, why->nokey?"NOKEY": (why->blocked?"BLOCKED":why->key_name))); - } else { + } else { if (verbosity >= 2) { char address[128]; addr2str(&q->addr, address, sizeof(address)); @@ -1326,7 +1326,7 @@ answer_lookup_zone(struct nsd *nsd, struct query *q, answer_type *answer, address, why ? ( why->nokey ? "NOKEY" : why->blocked ? "BLOCKED" - : why->key_name ) + : why->key_name ) : "no acl matches", why?why->ip_address_spec:".")); } diff --git a/usr.sbin/nsd/radtree.c b/usr.sbin/nsd/radtree.c index 472e9c128..a6bd15b0e 100644 --- a/usr.sbin/nsd/radtree.c +++ b/usr.sbin/nsd/radtree.c @@ -126,7 +126,7 @@ radnode_find_prev_from_idx(struct radnode* n, unsigned from) return NULL; } -/** +/** * Find a prefix of the key, in whole-nodes. * Finds the longest prefix that corresponds to a whole radnode entry. * There may be a slightly longer prefix in one of the array elements. @@ -413,7 +413,7 @@ radsel_split(struct region* region, struct radsel* r, uint8_t* k, r->node->array[add->pidx].str = split_str; r->node->array[add->pidx].len = split_len; } else { - /* okay we need to create a new node that chooses between + /* okay we need to create a new node that chooses between * the nodes 'add' and r.node * We do this so that r.node stays the same pointer for its * key name. */ @@ -595,7 +595,7 @@ struct radnode* radix_insert(struct radtree* rt, uint8_t* k, /* use bucket but it has a shared prefix, * split that out and create a new intermediate * node to split out between the two. - * One of the two might exactmatch the new + * One of the two might exactmatch the new * intermediate node */ if(!radsel_split(rt->region, &n->array[byte-n->offset], k, pos+1, len, add)) { @@ -773,8 +773,8 @@ radnode_cleanup_leaf(struct region* region, struct radnode* n, } } -/** - * Cleanup a radix node that was made smaller, see if it can +/** + * Cleanup a radix node that was made smaller, see if it can * be merged with others. * @param rt: tree to remove root if needed. * @param n: node to cleanup @@ -1055,7 +1055,7 @@ void radname_d2r(uint8_t* k, radstrlen_type* len, const uint8_t* dname, * because the only allowed empty label is the final root label, * we can also remove the last 00 label-end. * The total result length is one-or-two less than the dname. - * + * * examples (numbers are bytes, letters are ascii): * - root: dname: 0, radname: '' * - nl.: dname: 3nl0, radname: 'nl' @@ -1078,7 +1078,7 @@ void radname_d2r(uint8_t* k, radstrlen_type* len, const uint8_t* dname, *len = 0; return; } - + /* walk through domain name and remember label positions */ do { /* compression pointers not allowed */ @@ -1259,7 +1259,7 @@ struct radnode* radname_search(struct radtree* rt, const uint8_t* d, /* if last label, no match since * we are in the additional string */ if(lab == 0) - return NULL; + return NULL; /* next label, search for byte 00 */ lpos = 0; lab--; @@ -1392,7 +1392,7 @@ int radname_find_less_equal(struct radtree* rt, const uint8_t* d, size_t max, * this array element */ *result =radix_prev( n->array[byte].node); - return 0; + return 0; } /* next label, search for byte 00 */ lpos = 0; @@ -1402,7 +1402,7 @@ int radname_find_less_equal(struct radtree* rt, const uint8_t* d, size_t max, if(b < n->array[byte].str[i]) { *result =radix_prev( n->array[byte].node); - return 0; + return 0; } else if(b > n->array[byte].str[i]) { /* the key is after the additional, * so everything in its subtree is diff --git a/usr.sbin/nsd/radtree.h b/usr.sbin/nsd/radtree.h index c5d830a13..2d7cfdb1c 100644 --- a/usr.sbin/nsd/radtree.h +++ b/usr.sbin/nsd/radtree.h @@ -48,7 +48,7 @@ struct radnode { /** capacity of the lookup array (can be larger than length) */ uint16_t capacity; /** the lookup array by [byte-offset] */ - struct radsel* array; + struct radsel* array; } ATTR_PACKED; /** diff --git a/usr.sbin/nsd/rdata.c b/usr.sbin/nsd/rdata.c index 8a6f7f731..5210c5f6e 100644 --- a/usr.sbin/nsd/rdata.c +++ b/usr.sbin/nsd/rdata.c @@ -671,7 +671,7 @@ rdata_svcparam_ipv4hint_to_string(buffer_type *output, uint16_t val_len, uint16_t *data) { char ip_str[INET_ADDRSTRLEN + 1]; - + assert(val_len > 0); /* Guaranteed by rdata_svcparam_to_string */ if ((val_len % IP4ADDRLEN) == 0) { @@ -698,7 +698,7 @@ rdata_svcparam_ipv6hint_to_string(buffer_type *output, uint16_t val_len, uint16_t *data) { char ip_str[INET6_ADDRSTRLEN + 1]; - + assert(val_len > 0); /* Guaranteed by rdata_svcparam_to_string */ if ((val_len % IP6ADDRLEN) == 0) { @@ -805,7 +805,7 @@ rdata_svcparam_to_string(buffer_type *output, rdata_atom_type rdata, uint16_t size = rdata_atom_size(rdata); uint16_t* data = (uint16_t *)rdata_atom_data(rdata); uint16_t svcparamkey, val_len; - uint8_t* dp; + uint8_t* dp; size_t i; if (size < 4) diff --git a/usr.sbin/nsd/region-allocator.h b/usr.sbin/nsd/region-allocator.h index 99af23350..784c287c7 100644 --- a/usr.sbin/nsd/region-allocator.h +++ b/usr.sbin/nsd/region-allocator.h @@ -76,7 +76,7 @@ size_t region_add_cleanup(region_type *region, void (*action)(void *), void *data); -/* +/* * Remove cleanup, both action and data must match exactly. */ void region_remove_cleanup(region_type *region, @@ -98,7 +98,7 @@ void *region_alloc_array(region_type *region, size_t num, size_t size); */ void *region_alloc_init(region_type *region, const void *init, size_t size); -/** +/** * Allocate array (with integer overflow check on sizes), and init with * the given array copied into it. Allocated in the region */ @@ -112,7 +112,7 @@ void *region_alloc_array_init(region_type *region, const void *init, */ void *region_alloc_zero(region_type *region, size_t size); -/** +/** * Allocate array (with integer overflow check on sizes), and zero it. * Allocated in the region. */ diff --git a/usr.sbin/nsd/remote.c b/usr.sbin/nsd/remote.c index 5cdee68db..ee6dc2d91 100644 --- a/usr.sbin/nsd/remote.c +++ b/usr.sbin/nsd/remote.c @@ -4,22 +4,22 @@ * Copyright (c) 2008, NLnet Labs. All rights reserved. * * This software is open source. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: - * + * * Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. - * + * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. - * + * * Neither the name of the NLNET LABS nor the names of its contributors may * be used to endorse or promote products derived from this software without * specific prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -38,7 +38,7 @@ * * This file contains the remote control functionality for the daemon. * The remote control can be performed using either the commandline - * nsd-control tool, or a TLS capable web browser. + * nsd-control tool, or a TLS capable web browser. * The channel is secured using TLSv1, and certificates. * Both the server and the client(control tool) have their own keys. */ @@ -188,7 +188,7 @@ struct remote_stream { }; typedef struct remote_stream RES; -/** +/** * Print fixed line of text over ssl connection in blocking mode * @param res: print to * @param text: the text. @@ -196,7 +196,7 @@ typedef struct remote_stream RES; */ static int ssl_print_text(RES* res, const char* text); -/** +/** * printf style printing to the ssl connection * @param res: the RES connection to print to. Blocking. * @param format: printf style format string. @@ -246,7 +246,7 @@ log_crypto_err(const char* str) #ifdef BIND8_STATS /** subtract timers and the values do not overflow or become negative */ static void -timeval_subtract(struct timeval* d, const struct timeval* end, +timeval_subtract(struct timeval* d, const struct timeval* end, const struct timeval* start) { #ifndef S_SPLINT_S @@ -631,7 +631,7 @@ remote_accept_callback(int fd, short event, void* arg) goto close_exit; } - n->tval.tv_sec = REMOTE_CONTROL_TCP_TIMEOUT; + n->tval.tv_sec = REMOTE_CONTROL_TCP_TIMEOUT; n->tval.tv_usec = 0L; n->fd = newfd; @@ -693,7 +693,7 @@ remote_accept_callback(int fd, short event, void* arg) rc->busy_list = n; rc->active ++; - /* perform the first nonblocking read already, for windows, + /* perform the first nonblocking read already, for windows, * so it can return wouldblock. could be faster too. */ remote_control_callback(newfd, EV_READ, n); } @@ -753,7 +753,7 @@ clean_point(struct daemon_remote* rc, struct rc_state* s) static int ssl_print_text(RES* res, const char* text) { - if(!res) + if(!res) return 0; #ifdef HAVE_SSL if(res->ssl) { @@ -860,7 +860,7 @@ static char* skipwhite(char* str) { /* EOS \0 is not a space */ - while( isspace((unsigned char)*str) ) + while( isspace((unsigned char)*str) ) str++; return str; } @@ -1260,7 +1260,7 @@ zonestat_inc_ifneeded(xfrd_state_type* xfrd) #ifdef USE_ZONE_STATS if(xfrd->nsd->options->zonestatnames->count != xfrd->zonestat_safe) task_new_zonestat_inc(xfrd->nsd->task[xfrd->nsd->mytask], - xfrd->last_task, + xfrd->last_task, xfrd->nsd->options->zonestatnames->count); #else (void)xfrd; @@ -1501,7 +1501,7 @@ do_addzones(RES* ssl, xfrd_state_type* xfrd) if(buf[0] == 0x04 && buf[1] == 0) break; /* end of transmission */ if(!perform_addzone(ssl, xfrd, buf)) { - if(!ssl_printf(ssl, "error for input line '%s'\n", + if(!ssl_printf(ssl, "error for input line '%s'\n", buf)) return; } else { @@ -1523,7 +1523,7 @@ do_delzones(RES* ssl, xfrd_state_type* xfrd) if(buf[0] == 0x04 && buf[1] == 0) break; /* end of transmission */ if(!perform_delzone(ssl, xfrd, buf)) { - if(!ssl_printf(ssl, "error for input line '%s'\n", + if(!ssl_printf(ssl, "error for input line '%s'\n", buf)) return; } else { @@ -1639,7 +1639,7 @@ add_cfgzone(xfrd_state_type* xfrd, const char* pname) if(!zopt) return; zopt->part_of_config = 1; - zopt->name = region_strdup(xfrd->nsd->options->region, + zopt->name = region_strdup(xfrd->nsd->options->region, pname + strlen(PATTERN_IMPLICIT_MARKER)); zopt->pattern = pattern_options_find(xfrd->nsd->options, pname); if(!zopt->name || !zopt->pattern) @@ -2618,7 +2618,7 @@ print_longnum(RES* ssl, char* desc, uint64_t x) /* more than a Gb */ size_t front = (size_t)(x / (uint64_t)1000000); size_t back = (size_t)(x % (uint64_t)1000000); - return ssl_printf(ssl, "%s%lu%6.6lu\n", desc, + return ssl_printf(ssl, "%s%lu%6.6lu\n", desc, (unsigned long)front, (unsigned long)back); } else { return ssl_printf(ssl, "%s%lu\n", desc, (unsigned long)x); @@ -2764,7 +2764,7 @@ zonestat_print(RES* ssl, xfrd_state_type* xfrd, int clear) memcpy(&stat0, &xfrd->nsd->zonestat[0][n->id], sizeof(stat0)); memcpy(&stat1, &xfrd->nsd->zonestat[1][n->id], sizeof(stat1)); stats_add(&stat0, &stat1); - + /* save a copy of current (cumulative) stats in stat1 */ memcpy(&stat1, &stat0, sizeof(stat1)); /* subtract last total of stats that was 'cleared' */ @@ -2831,7 +2831,7 @@ print_stats(RES* ssl, xfrd_state_type* xfrd, struct timeval* now, int clear) return; if(!print_longnum(ssl, "size.xfrd.mem=", region_get_mem(xfrd->region))) return; - if(!print_longnum(ssl, "size.config.disk=", + if(!print_longnum(ssl, "size.config.disk=", xfrd->nsd->options->zonelist_off)) return; if(!print_longnum(ssl, "size.config.mem=", region_get_mem( diff --git a/usr.sbin/nsd/remote.h b/usr.sbin/nsd/remote.h index fb8fd699a..9c115cd73 100644 --- a/usr.sbin/nsd/remote.h +++ b/usr.sbin/nsd/remote.h @@ -4,22 +4,22 @@ * Copyright (c) 2008, NLnet Labs. All rights reserved. * * This software is open source. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: - * + * * Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. - * + * * Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. - * + * * Neither the name of the NLNET LABS nor the names of its contributors may * be used to endorse or promote products derived from this software without * specific prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -38,7 +38,7 @@ * * This file contains the remote control functionality for the daemon. * The remote control can be performed using either the commandline - * nsd-control tool, or a SSLv3/TLS capable web browser. + * nsd-control tool, or a SSLv3/TLS capable web browser. * The channel is secured using SSLv3 or TLSv1, and certificates. * Both the server and the client(control tool) have their own keys. */ diff --git a/usr.sbin/nsd/server.c b/usr.sbin/nsd/server.c index 529edcf40..108a9c854 100644 --- a/usr.sbin/nsd/server.c +++ b/usr.sbin/nsd/server.c @@ -243,7 +243,7 @@ struct tcp_handler_data * The number of queries handled by this specific TCP connection. */ int query_count; - + /* * The timeout in msec for this tcp connection */ @@ -1738,7 +1738,7 @@ server_send_soa_xfrd(struct nsd* nsd, int shortsoa) cmd != NSD_RELOAD) { log_msg(LOG_ERR, "did not get start signal from xfrd"); exit(1); - } + } if(nsd->signal_hint_shutdown) { goto shutdown; } @@ -2129,7 +2129,7 @@ block_read(struct nsd* nsd, int s, void* p, ssize_t sz, int timeout) memset(&fd, 0, sizeof(fd)); fd.fd = s; fd.events = POLLIN; - + while( total < sz) { ssize_t ret; ret = poll(&fd, 1, (timeout==-1)?-1:timeout*1000); @@ -4096,7 +4096,7 @@ handle_tcp_writing(int fd, short event, void* arg) #ifdef HAVE_WRITEV struct iovec iov[2]; iov[0].iov_base = (uint8_t*)&n_tcplen + data->bytes_transmitted; - iov[0].iov_len = sizeof(n_tcplen) - data->bytes_transmitted; + iov[0].iov_len = sizeof(n_tcplen) - data->bytes_transmitted; iov[1].iov_base = buffer_begin(q->packet); iov[1].iov_len = buffer_limit(q->packet); sent = writev(fd, iov, 2); @@ -4140,7 +4140,7 @@ handle_tcp_writing(int fd, short event, void* arg) goto packet_could_be_done; #endif } - + sent = write(fd, buffer_current(q->packet), buffer_remaining(q->packet)); diff --git a/usr.sbin/nsd/udb.c b/usr.sbin/nsd/udb.c index d94d41594..ff50a0585 100644 --- a/usr.sbin/nsd/udb.c +++ b/usr.sbin/nsd/udb.c @@ -762,7 +762,7 @@ regen_its_ptrs(void* base, udb_base* udb, udb_chunk_d* atp, arg[0] = rb_old; arg[1] = rb_new; /* walk through the structs here and put them on their respective * relptr lists */ - (*udb->walkfunc)(base, udb->walkarg, atp->type, data, dsz, + (*udb->walkfunc)(base, udb->walkarg, atp->type, data, dsz, ®en_relptr_func, arg); } @@ -913,7 +913,7 @@ fsck_file(udb_base* udb, udb_alloc* alloc, int moved) } } } - + /* rebuild freelists */ /* recalculate stats in alloc (except 'stat_data') */ /* possibly new end 'nextgrow' value */ diff --git a/usr.sbin/nsd/udb.h b/usr.sbin/nsd/udb.h index b3f495d9b..ff5c95d7a 100644 --- a/usr.sbin/nsd/udb.h +++ b/usr.sbin/nsd/udb.h @@ -104,7 +104,7 @@ struct udb_rel_ptr { udb_void next; }; -/** +/** * This is the routine that is called for every relptr * @param base: the baseptr for REL. * @param p: the relptr, a real pointer to it. @@ -112,7 +112,7 @@ struct udb_rel_ptr { */ typedef void udb_walk_relptr_cb(void*, udb_rel_ptr*, void*); -/** +/** * This routine calls the callback for every relptr in a datablock * params in order: * base: the baseptr for REL macro. @@ -246,7 +246,7 @@ struct udb_chunk_d { uint8_t flags; /** padding onto 8-alignment */ uint8_t pad[5]; - /** udb_rel_ptr* first in list of rel-ptrs that point back here + /** udb_rel_ptr* first in list of rel-ptrs that point back here * In the free chunk this is the previous pointer. */ udb_void ptrlist; /* user data space starts here, 64-bit aligned */ @@ -289,7 +289,7 @@ struct udb_xl_chunk_d { uint8_t flags; /** padding onto 8-alignment */ uint8_t pad[5]; - /** udb_rel_ptr* first in list of rel-ptrs that point back here + /** udb_rel_ptr* first in list of rel-ptrs that point back here * In the free chunk this is the previous pointer. */ udb_void ptrlist; /** size of this chunk in bytes */ @@ -312,7 +312,7 @@ struct udb_alloc_d { uint64_t stat_free; /** stats: number of bytes in alloced chunks, sum of their 2**x size */ uint64_t stat_alloc; - /** offset to create next chunk at. can be before file-end, or be + /** offset to create next chunk at. can be before file-end, or be * fsize, volatile because it is used as a 'commit', and thus we want * this to be written to memory (and thus disk) immediately. */ volatile uint64_t nextgrow; @@ -332,7 +332,7 @@ struct udb_alloc { udb_alloc_d* disk; }; -/** +/** * file header length, the file start with * 64bit: magic number to identify file (and prevent stupid mistakes) * globdata: global data. Fixed size segment. (starts with size uint64) @@ -424,15 +424,15 @@ udb_rel_ptr* udb_base_get_userdata(udb_base* udb); */ void udb_base_set_userdata(udb_base* udb, udb_void user); -/** - * Set the user flags (to any value, uint8). +/** + * Set the user flags (to any value, uint8). * @param udb: the udb. * @param v: new value. */ void udb_base_set_userflags(udb_base* udb, uint8_t v); -/** - * Get the user flags. +/** + * Get the user flags. * @param udb: the udb. * @param v: new value. */ @@ -556,7 +556,7 @@ udb_void udb_alloc_realloc(udb_alloc* alloc, udb_void r, size_t osz, */ int udb_alloc_grow(udb_alloc* alloc, size_t sz, size_t num); -/** +/** * attempt to compact the data and move free space to the end * can shrink the db, which calls sync on the db (for portability). * @param udb: the udb base. @@ -564,7 +564,7 @@ int udb_alloc_grow(udb_alloc* alloc, size_t sz, size_t num); */ int udb_compact(udb_base* udb); -/** +/** * set the udb to inhibit or uninhibit compaction. Does not perform * the compaction itself if enabled, for that call udb_compact. * @param udb: the udb base @@ -608,13 +608,13 @@ int udb_valid_dataptr(udb_base* udb, udb_void to); int udb_valid_rptr(udb_base* udb, udb_void rptr, udb_void to); /*** UDB_REL_PTR ***/ -/** +/** * Init a new UDB rel ptr at NULL. * @param ptr: sysptr, becomes inited. */ void udb_rel_ptr_init(udb_rel_ptr* ptr); -/** +/** * Unlink a UDB rel ptr. * @param base: the udb base * @param ptr: sysptr, unlinked diff --git a/usr.sbin/nsd/udbradtree.c b/usr.sbin/nsd/udbradtree.c index 5de16c7bb..c1f62094a 100644 --- a/usr.sbin/nsd/udbradtree.c +++ b/usr.sbin/nsd/udbradtree.c @@ -148,7 +148,7 @@ void udb_radix_tree_delete(udb_base* udb, udb_ptr* rt) udb_ptr_free_space(rt, udb, sizeof(struct udb_radtree_d)); } -/** +/** * Find a prefix of the key, in whole-nodes. * Finds the longest prefix that corresponds to a whole radnode entry. * There may be a slightly longer prefix in one of the array elements. @@ -407,7 +407,7 @@ static int udb_radnode_str_space(udb_base* udb, udb_ptr* n, /** copy remainder from prefixes for a split: * plen: len prefix, l: longer bstring, llen: length of l. */ -static void udb_radsel_prefix_remainder(udb_radstrlen_type plen, +static void udb_radsel_prefix_remainder(udb_radstrlen_type plen, uint8_t* l, udb_radstrlen_type llen, uint8_t* s, udb_radstrlen_type* slen) { @@ -554,7 +554,7 @@ static int udb_radsel_split(udb_base* udb, udb_ptr* n, uint8_t idx, uint8_t* k, } udb_ptr_unlink(&rnode, udb); } else { - /* okay we need to create a new node that chooses between + /* okay we need to create a new node that chooses between * the nodes 'add' and r.node * We do this so that r.node stays the same pointer for its * key name. */ @@ -756,7 +756,7 @@ udb_void udb_radix_insert(udb_base* udb, udb_ptr* rt, uint8_t* k, /* use bucket but it has a shared prefix, * split that out and create a new intermediate * node to split out between the two. - * One of the two might exactmatch the new + * One of the two might exactmatch the new * intermediate node */ if(!udb_radsel_split(udb, &n, byte-RADNODE(&n)->offset, k, pos+1, len, &add)) { @@ -988,8 +988,8 @@ udb_radnode_cleanup_leaf(udb_base* udb, udb_ptr* n, udb_ptr* par) return 1; } -/** - * Cleanup a radix node that was made smaller, see if it can +/** + * Cleanup a radix node that was made smaller, see if it can * be merged with others. * @param udb: the udb * @param rt: tree to remove root if needed. diff --git a/usr.sbin/nsd/udbzone.c b/usr.sbin/nsd/udbzone.c index 30f1c4beb..f2b8b52ef 100644 --- a/usr.sbin/nsd/udbzone.c +++ b/usr.sbin/nsd/udbzone.c @@ -494,12 +494,12 @@ rrset_create(udb_base* udb, udb_ptr* domain, uint16_t t, udb_ptr* res) udb_rel_ptr_init(&RRSET(res)->next); udb_rel_ptr_init(&RRSET(res)->rrs); RRSET(res)->type = t; - + #if 0 /* link it in, at the front */ udb_rptr_set_rptr(&RRSET(res)->next, udb, &DOMAIN(domain)->rrsets); udb_rptr_set_ptr(&DOMAIN(domain)->rrsets, udb, res); -#else +#else /* preserve RRset order, link at end */ if(DOMAIN(domain)->rrsets.data == 0) { udb_rptr_set_ptr(&DOMAIN(domain)->rrsets, udb, res); diff --git a/usr.sbin/nsd/xfrd-disk.c b/usr.sbin/nsd/xfrd-disk.c index 274d5a2dd..59ecf47ca 100644 --- a/usr.sbin/nsd/xfrd-disk.c +++ b/usr.sbin/nsd/xfrd-disk.c @@ -304,7 +304,7 @@ xfrd_read_state(struct xfrd_state* xfrd) { zone->state = xfrd_zone_expired; xfrd_set_refresh_now(zone); - } + } /* there is a zone read and it matches what we had before */ if(zone->soa_nsd_acquired && zone->state != xfrd_zone_expired @@ -313,7 +313,7 @@ xfrd_read_state(struct xfrd_state* xfrd) zone->state = state; xfrd_set_timer(zone, within_refresh_bounds(zone, timeout)); - } + } if((zone->soa_nsd_acquired == 0 && soa_nsd_acquired_read == 0 && soa_disk_acquired_read == 0) || (zone->state != xfrd_zone_ok && timeout != 0)) { diff --git a/usr.sbin/nsd/xfrd-notify.c b/usr.sbin/nsd/xfrd-notify.c index 280ac7ff7..8c7bf466f 100644 --- a/usr.sbin/nsd/xfrd-notify.c +++ b/usr.sbin/nsd/xfrd-notify.c @@ -248,7 +248,7 @@ notify_pkt_retry(struct notify_zone* zone, int index) } static void -xfrd_handle_notify_reply(struct notify_zone* zone, buffer_type* packet, +xfrd_handle_notify_reply(struct notify_zone* zone, buffer_type* packet, struct sockaddr* src, socklen_t srclen) { int i; diff --git a/usr.sbin/nsd/xfrd-notify.h b/usr.sbin/nsd/xfrd-notify.h index 3a20f383f..9ddf1e12b 100644 --- a/usr.sbin/nsd/xfrd-notify.h +++ b/usr.sbin/nsd/xfrd-notify.h @@ -34,7 +34,7 @@ struct acl_options; struct xfrd_state; /** number of concurrent notify packets in flight */ -#define NOTIFY_CONCURRENT_MAX 16 +#define NOTIFY_CONCURRENT_MAX 16 /** notify packet info */ struct notify_pkt { diff --git a/usr.sbin/nsd/xfrd-tcp.c b/usr.sbin/nsd/xfrd-tcp.c index 5b1d80bb5..3b499ae3c 100644 --- a/usr.sbin/nsd/xfrd-tcp.c +++ b/usr.sbin/nsd/xfrd-tcp.c @@ -67,7 +67,7 @@ tls_verify_callback(int preverify_ok, X509_STORE_CTX *ctx) int err = X509_STORE_CTX_get_error(ctx); int depth = X509_STORE_CTX_get_error_depth(ctx); - // report the specific cert error here - will need custom verify code if + // report the specific cert error here - will need custom verify code if // SPKI pins are supported if (!preverify_ok) log_msg(LOG_ERR, "xfrd tls: TLS verify failed - (%d) depth: %d error: %s", @@ -78,14 +78,14 @@ tls_verify_callback(int preverify_ok, X509_STORE_CTX *ctx) } static int -setup_ssl(struct xfrd_tcp_pipeline* tp, struct xfrd_tcp_set* tcp_set, +setup_ssl(struct xfrd_tcp_pipeline* tp, struct xfrd_tcp_set* tcp_set, const char* auth_domain_name) { if (!tcp_set->ssl_ctx) { log_msg(LOG_ERR, "xfrd tls: No TLS CTX, cannot set up XFR-over-TLS"); return 0; } - DEBUG(DEBUG_XFRD,1, (LOG_INFO, "xfrd: setting up TLS for tls_auth domain name %s", + DEBUG(DEBUG_XFRD,1, (LOG_INFO, "xfrd: setting up TLS for tls_auth domain name %s", auth_domain_name)); tp->ssl = SSL_new((SSL_CTX*)tcp_set->ssl_ctx); if(!tp->ssl) { @@ -525,7 +525,7 @@ pipeline_find(struct xfrd_tcp_set* set, xfrd_zone_type* zone) if(rbtree_find_less_equal(set->pipetree, key, &sme)) { /* exact match, strange, fully unused tcp cannot be open */ assert(0); - } + } if(!sme) return NULL; r = (struct xfrd_tcp_pipeline*)sme->key; @@ -1464,7 +1464,7 @@ xfrd_tcp_read(struct xfrd_tcp_pipeline* tp) xfrd_tcp_pipe_stop(tp); return; } - } else + } else #endif ret = conn_read(tcp); if(ret == -1) { diff --git a/usr.sbin/nsd/xfrd.c b/usr.sbin/nsd/xfrd.c index b7e1628c7..92c935f37 100644 --- a/usr.sbin/nsd/xfrd.c +++ b/usr.sbin/nsd/xfrd.c @@ -210,7 +210,7 @@ xfrd_init(int socket, struct nsd* nsd, int shortsoa, int reload_active, xfrd_receive_soa(socket, shortsoa); if(nsd->options->xfrdfile != NULL && nsd->options->xfrdfile[0]!=0) xfrd_read_state(xfrd); - + /* did we get killed before startup was successful? */ if(nsd->signal_hint_shutdown) { kill(nsd_pid, SIGTERM); @@ -282,7 +282,7 @@ xfrd_sig_process(void) if(!(xfrd->ipc_handler_flags&EV_WRITE)) { ipc_xfrd_set_listening(xfrd, EV_PERSIST|EV_READ|EV_WRITE); } - } + } /* collect children that exited. */ xfrd->nsd->signal_hint_child = 0; @@ -522,7 +522,7 @@ xfrd_init_slave_zone(xfrd_state_type* xfrd, struct zone_options* zone_opt) num = 0; num_xot = 0; for (; xzone->master != NULL; xzone->master = xzone->master->next, num++) { - if (xzone->master->tls_auth_options != NULL) num_xot++; + if (xzone->master->tls_auth_options != NULL) num_xot++; } if (num_xot != 0 && num != num_xot) log_msg(LOG_WARNING, "Some but not all request-xfrs for %s have XFR-over-TLS configured", @@ -731,7 +731,7 @@ xfrd_receive_soa(int socket, int shortsoa) } } udb_ptr_unlink(&last_task, xtask); - + /* send RELOAD to main to give it this tasklist */ task_process_sync(xtask); cmd = NSD_RELOAD; @@ -819,7 +819,7 @@ xfrd_del_slave_zone(xfrd_state_type* xfrd, const dname_type* dname) { xfrd_zone_type* z = (xfrd_zone_type*)rbtree_delete(xfrd->zones, dname); if(!z) return; - + /* io */ if(z->tcp_waiting) { /* delete from tcp waiting list */ diff --git a/usr.sbin/nsd/xfrd.h b/usr.sbin/nsd/xfrd.h index b6a840f81..eeb6721db 100644 --- a/usr.sbin/nsd/xfrd.h +++ b/usr.sbin/nsd/xfrd.h @@ -428,7 +428,7 @@ void xfrd_tsig_sign_request(buffer_type* packet, struct tsig_record* tsig, void xfrd_handle_incoming_soa(xfrd_zone_type* zone, xfrd_soa_type* soa, time_t acquired); /* handle a packet passed along ipc route. acl is the one that accepted - the packet. The packet is the network blob received. acl_xfr is + the packet. The packet is the network blob received. acl_xfr is provide-xfr acl matching notify sender or -1 */ void xfrd_handle_passed_packet(buffer_type* packet, int acl_num, int acl_xfr); diff --git a/usr.sbin/nsd/zlexer.lex b/usr.sbin/nsd/zlexer.lex index fb6eadf07..711bb62cf 100644 --- a/usr.sbin/nsd/zlexer.lex +++ b/usr.sbin/nsd/zlexer.lex @@ -1,7 +1,7 @@ %{ /* * zlexer.lex - lexical analyzer for (DNS) zone files - * + * * Copyright (c) 2001-2006, NLnet Labs. All rights reserved * * See LICENSE for the license. @@ -119,7 +119,7 @@ int at_eof(void) yy_current_buffer->yy_ch_buf[0] = ((at_bol)?'\n':' '); \ } #endif - + %} %option noinput %option nounput @@ -168,11 +168,11 @@ ANY [^\"\n\\]|\\. ++parser->line; parser->error_occurred = error_occurred; } -.+ { +.+ { char *tmp; domain_type *origin = parser->origin; int error_occurred = parser->error_occurred; - + BEGIN(INITIAL); if (include_stack_ptr >= MAXINCLUDES ) { zc_error("includes nested too deeply, skipped (>%d)", @@ -186,7 +186,7 @@ ANY [^\"\n\\]|\\. *tmp = '\0'; } strip_string(yytext); - + /* Parse origin for include file. */ tmp = strrchr(yytext, ' '); if (!tmp) { @@ -194,7 +194,7 @@ ANY [^\"\n\\]|\\. } if (tmp) { const dname_type *dname; - + /* split the original yytext */ *tmp = '\0'; strip_string(yytext); @@ -210,7 +210,7 @@ ANY [^\"\n\\]|\\. parser->db->domains, dname); } } - + if (strlen(yytext) == 0) { zc_error("missing file name in $INCLUDE directive"); } else if (!(input = fopen(yytext, "r"))) { @@ -258,7 +258,7 @@ ANY [^\"\n\\]|\\. } {NEWLINE} { ++parser->line; - if (!paren_open) { + if (!paren_open) { lexer_state = EXPECT_OWNER; LEXOUT(("NL\n")); return NL; @@ -347,7 +347,7 @@ ANY [^\"\n\\]|\\. * returned and the TYPE parameter is set to the RR type value. */ static int -rrtype_to_token(const char *word, uint16_t *type) +rrtype_to_token(const char *word, uint16_t *type) { uint16_t t = rrtype_from_string(word); if (t != 0) { @@ -364,7 +364,7 @@ rrtype_to_token(const char *word, uint16_t *type) * Remove \DDD constructs from the input. See RFC 1035, section 5.1. */ static size_t -zoctet(char *text) +zoctet(char *text) { /* * s follows the string, p lags behind and rebuilds the new @@ -372,7 +372,7 @@ zoctet(char *text) */ char *s; char *p; - + for (s = p = text; *s; ++s, ++p) { assert(p <= s); if (s[0] != '\\') { @@ -415,7 +415,7 @@ parse_token(int token, char *yytext, enum lexer_state *lexer_state) const char *t; int token; uint16_t rrclass; - + /* type */ token = rrtype_to_token(yytext, &yylval.type); if (token != 0) { @@ -445,7 +445,7 @@ parse_token(int token, char *yytext, enum lexer_state *lexer_state) yylval.data.str = str; yylval.data.len = len; - + LEXOUT(("%d[%s] ", token, yytext)); return token; } diff --git a/usr.sbin/nsd/zonec.c b/usr.sbin/nsd/zonec.c index c01fc51b3..0ef403277 100644 --- a/usr.sbin/nsd/zonec.c +++ b/usr.sbin/nsd/zonec.c @@ -918,7 +918,7 @@ zparser_conv_svcbparam_ipv6hint_value(region_type *region, const char *val) } } - /* count == number of comma's in val + 1 + /* count == number of comma's in val + 1 * so actually the number of IPv6 addresses in val */ r = alloc_rdata(region, 2 * sizeof(uint16_t) + IP6ADDRLEN * count); @@ -987,7 +987,7 @@ zparser_conv_svcbparam_mandatory_value(region_type *region, for(;;) { if (!(next_key = strchr(val, ','))) { *key_dst = htons(svcbparam_lookup_key(val, val_len)); - break; + break; } else { *key_dst = htons(svcbparam_lookup_key(val, next_key - val)); } @@ -1613,7 +1613,7 @@ zadd_rdata_txt_wireformat(uint16_t *data, int first) zc_error_prev_line("too many rdata txt elements"); return; } - + /* First STR in str_seq, allocate 65K in first unused rdata * else find last used rdata */ if (first) { @@ -1628,12 +1628,12 @@ zadd_rdata_txt_wireformat(uint16_t *data, int first) } else rd = &parser->current_rr.rdatas[parser->current_rr.rdata_count-1]; - + if ((size_t)rd->data[0] + (size_t)data[0] > 65535) { zc_error_prev_line("too large rdata element"); return; } - + memcpy((uint8_t *)rd->data + 2 + rd->data[0], data + 1, data[0]); rd->data[0] += data[0]; } @@ -1648,7 +1648,7 @@ zadd_rdata_txt_clean_wireformat() rdata_atom_type *rd = &parser->current_rr.rdatas[parser->current_rr.rdata_count-1]; if(!rd || !rd->data) return; /* previous syntax failure */ - if ((tmp_data = (uint16_t *) region_alloc(parser->region, + if ((tmp_data = (uint16_t *) region_alloc(parser->region, ((size_t)rd->data[0]) + ((size_t)2))) != NULL) { memcpy(tmp_data, rd->data, rd->data[0] + 2); /* rd->data of u16+65535 freed when rr_region is freed */ @@ -1696,7 +1696,7 @@ zadd_rdata_svcb_check_wireformat() * in each rdata in the remainder of this function. */ memset(paramkeys, 0, sizeof(paramkeys)); - /* + /* * In draft-ietf-dnsop-svcb-https-04 Section 7: * In wire format, the keys are represented by their numeric values in * network byte order, concatenated in ascending order. @@ -1715,13 +1715,13 @@ zadd_rdata_svcb_check_wireformat() assert(parser->current_rr.rdatas[i].data); assert(rdata_atom_data(parser->current_rr.rdatas[i])); assert(rdata_atom_size(parser->current_rr.rdatas[i]) >= sizeof(uint16_t)); - + key = read_uint16(rdata_atom_data(parser->current_rr.rdatas[i])); /* In draft-ietf-dnsop-svcb-https-04 Section 7: * * Keys (...) MUST NOT appear more than once. - * + * * If they key has already been seen, we have a duplicate */ if (!paramkeys[key]) @@ -1756,7 +1756,7 @@ zadd_rdata_svcb_check_wireformat() if (size % 2) zc_error_prev_line("mandatory rdata must be a multiple of shorts"); - + else for (i = 0; i < (size - 4)/2; i++) { key = ntohs(mandatory_values[i]); diff --git a/usr.sbin/nsd/zparser.y b/usr.sbin/nsd/zparser.y index 79cd61018..e6cfbbea6 100644 --- a/usr.sbin/nsd/zparser.y +++ b/usr.sbin/nsd/zparser.y @@ -966,7 +966,7 @@ rdata_rrsig: str sp str sp str sp str sp str sp str sp str sp wire_dname sp str_ zadd_rdata_wireformat(zparser_conv_time(parser->region, $9.str)); /* sig exp */ zadd_rdata_wireformat(zparser_conv_time(parser->region, $11.str)); /* sig inc */ zadd_rdata_wireformat(zparser_conv_short(parser->region, $13.str)); /* key id */ - zadd_rdata_wireformat(zparser_conv_dns_name(parser->region, + zadd_rdata_wireformat(zparser_conv_dns_name(parser->region, (const uint8_t*) $15.str,$15.len)); /* sig name */ zadd_rdata_wireformat(zparser_conv_b64(parser->region, $17.str)); /* sig data */ } @@ -974,7 +974,7 @@ rdata_rrsig: str sp str sp str sp str sp str sp str sp str sp wire_dname sp str_ rdata_nsec: wire_dname nsec_seq { - zadd_rdata_wireformat(zparser_conv_dns_name(parser->region, + zadd_rdata_wireformat(zparser_conv_dns_name(parser->region, (const uint8_t*) $1.str, $1.len)); /* nsec name */ zadd_rdata_wireformat(zparser_conv_nsec(parser->region, nsecbits)); /* nsec bitlist */ memset(nsecbits, 0, sizeof(nsecbits)); @@ -1041,7 +1041,7 @@ rdata_ipsec_base: str sp str sp str sp dotted_str zadd_rdata_wireformat(zparser_conv_byte(parser->region, $3.str)); /* gateway type */ zadd_rdata_wireformat(zparser_conv_byte(parser->region, $5.str)); /* algorithm */ switch(atoi($3.str)) { - case IPSECKEY_NOGATEWAY: + case IPSECKEY_NOGATEWAY: zadd_rdata_wireformat(alloc_rdata_init(parser->region, "", 0)); break; case IPSECKEY_IP4: @@ -1067,7 +1067,7 @@ rdata_ipsec_base: str sp str sp str sp dotted_str MAXDOMAINLEN); break; } - name = dname_concatenate(parser->rr_region, name, + name = dname_concatenate(parser->rr_region, name, domain_dname(parser->origin)); } zadd_rdata_wireformat(alloc_rdata_init(parser->region, @@ -1086,7 +1086,7 @@ rdata_ipseckey: rdata_ipsec_base sp str_sp_seq trail | rdata_ipsec_base trail ; -/* RFC 6742 */ +/* RFC 6742 */ rdata_nid: str sp dotted_str trail { zadd_rdata_wireformat(zparser_conv_short(parser->region, $1.str)); /* preference */ @@ -1354,10 +1354,10 @@ nsec3_add_params(const char* hashalgo_str, const char* flag_str, zadd_rdata_wireformat(zparser_conv_short(parser->region, iter_str)); /* salt */ - if(strcmp(salt_str, "-") != 0) - zadd_rdata_wireformat(zparser_conv_hex_length(parser->region, - salt_str, salt_len)); - else + if(strcmp(salt_str, "-") != 0) + zadd_rdata_wireformat(zparser_conv_hex_length(parser->region, + salt_str, salt_len)); + else zadd_rdata_wireformat(alloc_rdata_init(parser->region, "", 1)); } #endif /* NSEC3 */ diff --git a/usr.sbin/ntpd/client.c b/usr.sbin/ntpd/client.c index 10924fc1c..22da46aab 100644 --- a/usr.sbin/ntpd/client.c +++ b/usr.sbin/ntpd/client.c @@ -253,7 +253,7 @@ handle_auto(uint8_t trusted, double offset) v[count++] = offset; if (count < AUTO_REPLIES) return; - + /* we have enough */ qsort(v, count, sizeof(double), auto_cmp); if (AUTO_REPLIES % 2 == 0) diff --git a/usr.sbin/ntpd/config.c b/usr.sbin/ntpd/config.c index 0dd2978de..78fad710b 100644 --- a/usr.sbin/ntpd/config.c +++ b/usr.sbin/ntpd/config.c @@ -132,7 +132,7 @@ int host_dns(const char *s, int synced, struct ntp_addr **hn) { int error, save_opts; - + log_debug("trying to resolve %s", s); error = host_dns1(s, hn, 0); if (!synced && error <= 0) { diff --git a/usr.sbin/ntpd/constraint.c b/usr.sbin/ntpd/constraint.c index f6686fd9b..18f79bb9b 100644 --- a/usr.sbin/ntpd/constraint.c +++ b/usr.sbin/ntpd/constraint.c @@ -714,7 +714,7 @@ constraint_msg_close(u_int32_t id, u_int8_t *data, size_t len) " received in time, next query %ds", log_sockaddr((struct sockaddr *) &cstr->addr->ss), CONSTRAINT_SCAN_INTERVAL); - + cnt = 0; TAILQ_FOREACH(tmp, &conf->constraints, entry) cnt++; diff --git a/usr.sbin/ntpd/ntp_dns.c b/usr.sbin/ntpd/ntp_dns.c index 8928b8cd7..8a8ef100e 100644 --- a/usr.sbin/ntpd/ntp_dns.c +++ b/usr.sbin/ntpd/ntp_dns.c @@ -224,13 +224,13 @@ probe_root_ns(void) _res.retrans = 1; _res.retry = 1; _res.options |= RES_USE_CD; - + ret = res_query(".", C_IN, T_NS, buf, sizeof(buf)); _res.retrans = old_retrans; _res.retry = old_retry; _res.options = old_options; - + return ret; } @@ -239,7 +239,7 @@ probe_root(void) { int n; - n = probe_root_ns(); + n = probe_root_ns(); if (n < 0) { /* give programs like unwind a second chance */ sleep(1); diff --git a/usr.sbin/ntpd/sensors.c b/usr.sbin/ntpd/sensors.c index ff0eec09b..06759ddf6 100644 --- a/usr.sbin/ntpd/sensors.c +++ b/usr.sbin/ntpd/sensors.c @@ -195,7 +195,7 @@ sensor_query(struct ntp_sensor *s) return; s->last = sensor.tv.tv_sec; - + if (!s->trusted && !TAILQ_EMPTY(&conf->constraints)) { if (conf->constraint_median == 0) { return; diff --git a/usr.sbin/ntpd/util.c b/usr.sbin/ntpd/util.c index be113ba85..bbac1c55a 100644 --- a/usr.sbin/ntpd/util.c +++ b/usr.sbin/ntpd/util.c @@ -94,7 +94,7 @@ lfp_to_d(struct l_fixedpt lfp) /* see comment in ntp.h */ base = NTP_ERA; if (lfp.int_partl <= INT32_MAX) - base++; + base++; ret = base * SECS_IN_ERA; ret += (double)(lfp.int_partl) + ((double)lfp.fractionl / UINT_MAX); diff --git a/usr.sbin/ospf6d/rde.c b/usr.sbin/ospf6d/rde.c index f67440499..53e483d0d 100644 --- a/usr.sbin/ospf6d/rde.c +++ b/usr.sbin/ospf6d/rde.c @@ -1174,7 +1174,7 @@ rde_asext_lookup(struct in6_addr prefix, int plen) struct iface *iface; struct iface_addr *ia; struct in6_addr ina, inb; - + LIST_FOREACH(area, &rdeconf->area_list, entry) { LIST_FOREACH(iface, &area->iface_list, entry) { TAILQ_FOREACH(ia, &iface->ifa_list, entry) { diff --git a/usr.sbin/pppd/cbcp.c b/usr.sbin/pppd/cbcp.c index 9e64cec18..5f11c5f86 100644 --- a/usr.sbin/pppd/cbcp.c +++ b/usr.sbin/pppd/cbcp.c @@ -71,7 +71,7 @@ struct protent cbcp_protent = { NULL }; -cbcp_state cbcp[NUM_PPP]; +cbcp_state cbcp[NUM_PPP]; /* internal prototypes */ @@ -138,7 +138,7 @@ cbcp_input(int unit, u_char *inpacket, int pktlen) return; } len -= CBCP_MINLEN; - + switch(code) { case CBCP_REQ: us->us_id = id; @@ -198,7 +198,7 @@ cbcp_printpkt(u_char *p, int plen, void (*printer)(void *, char *, ...), if (code >= 1 && code <= sizeof(cbcp_codenames) / sizeof(char *)) printer(arg, " %s", cbcp_codenames[code-1]); else - printer(arg, " code=0x%x", code); + printer(arg, " code=0x%x", code); printer(arg, " id=0x%x", id); len -= HEADERLEN; @@ -221,7 +221,7 @@ cbcp_printpkt(u_char *p, int plen, void (*printer)(void *, char *, ...), if (opt >= 1 && opt <= sizeof(cbcp_optionnames) / sizeof(char *)) printer(arg, " %s", cbcp_optionnames[opt-1]); else - printer(arg, " option=0x%x", opt); + printer(arg, " option=0x%x", opt); if (olen > 2) { GETCHAR(delay, p); @@ -366,13 +366,13 @@ cbcp_send(cbcp_state *us, u_char code, u_char *buf, int len) outp = outpacket_buf; outlen = 4 + len; - + MAKEHEADER(outp, PPP_CBCP); PUTCHAR(code, outp); PUTCHAR(us->us_id, outp); PUTSHORT(outlen, outp); - + if (len) BCOPY(buf, outp, len); diff --git a/usr.sbin/pppd/chap.c b/usr.sbin/pppd/chap.c index b98e7fc57..9daa03247 100644 --- a/usr.sbin/pppd/chap.c +++ b/usr.sbin/pppd/chap.c @@ -755,7 +755,7 @@ ChapGenChallenge(cstate) <= MAX_CHALLENGE_LENGTH */ chal_len = MIN_CHALLENGE_LENGTH + arc4random_uniform(MAX_CHALLENGE_LENGTH - MIN_CHALLENGE_LENGTH + 1); - + cstate->chal_len = chal_len; cstate->chal_id = ++cstate->id; cstate->chal_transmits = 0; diff --git a/usr.sbin/pppd/chat/chat.c b/usr.sbin/pppd/chat/chat.c index 9f4ac4dd6..710b26186 100644 --- a/usr.sbin/pppd/chat/chat.c +++ b/usr.sbin/pppd/chat/chat.c @@ -19,7 +19,7 @@ * added -T and -U option and \T and \U substitution to pass a phone * number into chat script. Two are needed for some ISDN TA applications. * Keith Dart - * + * * * Added SAY keyword to send output to stderr. * This allows to turn ECHO OFF and to output specific, user selected, @@ -43,7 +43,7 @@ * In the same vein as above, added CLR_REPORT keyword. * * Allow for comments. Line starting with '#' are comments and are - * ignored. If a '#' is to be expected as the first character, the + * ignored. If a '#' is to be expected as the first character, the * expect string must be quoted. * * @@ -167,7 +167,7 @@ int clear_abort_next = 0; char *report_string[MAX_REPORTS] ; char report_buffer[50] ; -int n_reports = 0, report_next = 0, report_gathering = 0 ; +int n_reports = 0, report_next = 0, report_gathering = 0 ; int clear_report_next = 0; int say_next = 0, hup_next = 0; @@ -321,7 +321,7 @@ main(argc, argv) } init(); - + if (chat_file != NULL) { if (argc > 0) usage(); @@ -641,7 +641,7 @@ int sending; /* set to 1 when sending (putting) this string. */ t++; if (isoctal(*t)) { t++; - if (isoctal(*t)) + if (isoctal(*t)) t++; } } @@ -712,7 +712,7 @@ int sending; /* set to 1 when sending (putting) this string. */ case 'T': if (sending && phone_num) { - for ( phchar = phone_num; *phchar != '\0'; phchar++) + for ( phchar = phone_num; *phchar != '\0'; phchar++) *s1++ = *phchar; } else { @@ -723,7 +723,7 @@ int sending; /* set to 1 when sending (putting) this string. */ case 'U': if (sending && phone_num2) { - for ( phchar = phone_num2; *phchar != '\0'; phchar++) + for ( phchar = phone_num2; *phchar != '\0'; phchar++) *s1++ = *phchar; } else { @@ -760,7 +760,7 @@ int sending; /* set to 1 when sending (putting) this string. */ else *s1++ = 'N'; break; - + default: if (isoctal (cur_chr)) { cur_chr &= 0x07; @@ -873,7 +873,7 @@ char *s; ++hup_next; return; } - + if (strcmp(s, "ABORT") == 0) { ++abort_next; return; @@ -1002,14 +1002,14 @@ register char *s; if (abort_next) { char *s1; - + abort_next = 0; - + if (n_aborts >= MAX_ABORTS) fatal(2, "Too many ABORT strings"); - + s1 = clean(s, 0); - + if (strlen(s1) > strlen(s) || strlen(s1) + 1 > sizeof(fail_buffer)) fatal(1, "Illegal or too-long ABORT string ('%v')", s); @@ -1026,11 +1026,11 @@ register char *s; int i; int old_max; int pack = 0; - + clear_abort_next = 0; - + s1 = clean(s, 0); - + if (strlen(s1) > strlen(s) || strlen(s1) + 1 > sizeof(fail_buffer)) fatal(1, "Illegal or too-long CLR_ABORT string ('%v')", s); @@ -1054,18 +1054,18 @@ register char *s; if (report_next) { char *s1; - + report_next = 0; if (n_reports >= MAX_REPORTS) fatal(2, "Too many REPORT strings"); - + s1 = clean(s, 0); - + if (strlen(s1) > strlen(s) || strlen(s1) > sizeof fail_buffer - 1) fatal(1, "Illegal or too-long REPORT string ('%v')", s); - + report_string[n_reports++] = s1; - + if (verbose) logmsg("report (%v)", s); return; @@ -1076,11 +1076,11 @@ register char *s; int i; int old_max; int pack = 0; - + clear_report_next = 0; - + s1 = clean(s, 0); - + if (strlen(s1) > strlen(s) || strlen(s1) > sizeof fail_buffer - 1) fatal(1, "Illegal or too-long REPORT string ('%v')", s); @@ -1098,14 +1098,14 @@ register char *s; free(s1); if (pack) pack_array(report_string,old_max); - + return; } if (timeout_next) { timeout_next = 0; timeout = atoi(s); - + if (timeout <= 0) timeout = DEFAULT_CHAT_TIMEOUT; @@ -1144,7 +1144,7 @@ int get_char() if (fcntl(0, F_SETFL, status & ~O_NONBLOCK) == -1) fatal(2, "Can't set file mode flags on stdin: %m"); - + return (-1); } } @@ -1162,17 +1162,17 @@ int c; switch (status) { case 1: return (0); - + default: logmsg("warning: write() on stdout returned %d", status); - + case -1: if ((status = fcntl(0, F_GETFL)) == -1) fatal(2, "Can't get file mode flags on stdin, %m"); if (fcntl(0, F_SETFL, status & ~O_NONBLOCK) == -1) fatal(2, "Can't set file mode flags on stdin: %m"); - + return (-1); } } @@ -1413,7 +1413,7 @@ register char *string; } alarm(0); - + if (verbose && printed) { if (alarmed) logmsg(" -- read timed out"); diff --git a/usr.sbin/pppd/fsm.c b/usr.sbin/pppd/fsm.c index 0a95205bf..b8fcde282 100644 --- a/usr.sbin/pppd/fsm.c +++ b/usr.sbin/pppd/fsm.c @@ -355,28 +355,28 @@ fsm_input(f, inpacket, l) case CONFREQ: fsm_rconfreq(f, id, inp, len); break; - + case CONFACK: fsm_rconfack(f, id, inp, len); break; - + case CONFNAK: case CONFREJ: fsm_rconfnakrej(f, code, id, inp, len); break; - + case TERMREQ: fsm_rtermreq(f, id, inp, len); break; - + case TERMACK: fsm_rtermack(f); break; - + case CODEREJ: fsm_rcoderej(f, inp, len); break; - + default: if( !f->callbacks->extcode || !(*f->callbacks->extcode)(f, code, id, inp, len) ) diff --git a/usr.sbin/pppd/ipcp.c b/usr.sbin/pppd/ipcp.c index 1296d897b..bb0da91b1 100644 --- a/usr.sbin/pppd/ipcp.c +++ b/usr.sbin/pppd/ipcp.c @@ -1217,7 +1217,7 @@ ipcp_up(f) } /* assign a default route through the interface if required */ - if (ipcp_wantoptions[f->unit].default_route) + if (ipcp_wantoptions[f->unit].default_route) if (sifdefaultroute(f->unit, go->ouraddr, ho->hisaddr)) default_route_set[f->unit] = 1; diff --git a/usr.sbin/pppd/ipcp.h b/usr.sbin/pppd/ipcp.h index a9064f008..d56012926 100644 --- a/usr.sbin/pppd/ipcp.h +++ b/usr.sbin/pppd/ipcp.h @@ -63,7 +63,7 @@ #define IPCP_VJ_COMP 0x002d /* current value for VJ compression option*/ #define IPCP_VJ_COMP_OLD 0x0037 /* "old" (i.e, broken) value for VJ */ - /* compression option*/ + /* compression option*/ typedef struct ipcp_options { int neg_addr : 1; /* Negotiate IP Address? */ diff --git a/usr.sbin/pppd/options.c b/usr.sbin/pppd/options.c index a66719484..fe1125e67 100644 --- a/usr.sbin/pppd/options.c +++ b/usr.sbin/pppd/options.c @@ -1107,7 +1107,7 @@ setpassfilter(argv) { pc.linktype = DLT_PPP; pc.snapshot = PPP_HDRLEN; - + if (pcap_compile(&pc, &pass_filter, *argv, 1, netmask) == 0) return 1; option_error("error in pass-filter expression: %s\n", pcap_geterr(&pc)); @@ -1123,7 +1123,7 @@ setactivefilter(argv) { pc.linktype = DLT_PPP; pc.snapshot = PPP_HDRLEN; - + if (pcap_compile(&pc, &active_filter, *argv, 1, netmask) == 0) return 1; option_error("error in active-filter expression: %s\n", pcap_geterr(&pc)); @@ -1426,7 +1426,7 @@ setdisconnector(argv) novm("disconnect script"); disconnector_info.priv = privileged_option; disconnector_info.source = option_source; - + return (1); } @@ -1470,7 +1470,7 @@ setmaxconnect(argv) } /* - * setdomain - Set domain name to append to hostname + * setdomain - Set domain name to append to hostname */ static int setdomain(argv) @@ -1592,7 +1592,7 @@ setdevname(cp, quiet) default_device = FALSE; devnam_info.priv = privileged_option; devnam_info.source = option_source; - + return 1; } @@ -1609,13 +1609,13 @@ setipaddr(arg) struct in_addr ina; u_int32_t local, remote; ipcp_options *wo = &ipcp_wantoptions[0]; - + /* * IP address pair separated by ":". */ if ((colon = strchr(arg, ':')) == NULL) return 0; - + /* * If colon first character, then no local addr. */ @@ -1640,7 +1640,7 @@ setipaddr(arg) wo->ouraddr = local; *colon = ':'; } - + /* * If colon last character, then no remote addr. */ diff --git a/usr.sbin/pppd/pppstats/pppstats.c b/usr.sbin/pppd/pppstats/pppstats.c index a606caf12..0060d007b 100644 --- a/usr.sbin/pppd/pppstats/pppstats.c +++ b/usr.sbin/pppd/pppstats/pppstats.c @@ -185,9 +185,9 @@ intpr() printf("OUT: COMPRESSED INCOMPRESSIBLE COMP\n"); bunit = dflag? "KB/S": "BYTE"; printf(" %s PACK %s PACK RATIO | ", - bunit, bunit); + bunit, bunit); printf(" %s PACK %s PACK RATIO", - bunit, bunit); + bunit, bunit); } else { printf("%8.8s %6.6s %6.6s", "IN", "PACK", "VJCOMP"); diff --git a/usr.sbin/pppd/sys-bsd.c b/usr.sbin/pppd/sys-bsd.c index bac8dab19..9b05d529d 100644 --- a/usr.sbin/pppd/sys-bsd.c +++ b/usr.sbin/pppd/sys-bsd.c @@ -263,7 +263,7 @@ establish_ppp(fd) /* * Find out which interface we were given. */ - if (ioctl(fd, PPPIOCGUNIT, &ifunit) == -1) { + if (ioctl(fd, PPPIOCGUNIT, &ifunit) == -1) { syslog(LOG_ERR, "ioctl(PPPIOCGUNIT): %m"); die(1); } @@ -271,7 +271,7 @@ establish_ppp(fd) /* * Check that we got the same unit again. */ - if (ioctl(fd, PPPIOCGUNIT, &x) == -1) { + if (ioctl(fd, PPPIOCGUNIT, &x) == -1) { syslog(LOG_ERR, "ioctl(PPPIOCGUNIT): %m"); die(1); } @@ -332,7 +332,7 @@ restore_loop() /* * Check that we got the same unit again. */ - if (ioctl(loop_slave, PPPIOCGUNIT, &x) == -1) { + if (ioctl(loop_slave, PPPIOCGUNIT, &x) == -1) { syslog(LOG_ERR, "ioctl(PPPIOCGUNIT): %m"); die(1); } @@ -534,7 +534,7 @@ open_ppp_loopback() syslog(LOG_WARNING, "couldn't set attributes on loopback: %m"); } - if ((flags = fcntl(loop_master, F_GETFL)) != -1) + if ((flags = fcntl(loop_master, F_GETFL)) != -1) if (fcntl(loop_master, F_SETFL, flags | O_NONBLOCK) == -1) syslog(LOG_WARNING, "couldn't set loopback to nonblock: %m"); @@ -547,7 +547,7 @@ open_ppp_loopback() /* * Find out which interface we were given. */ - if (ioctl(ppp_fd, PPPIOCGUNIT, &ifunit) == -1) { + if (ioctl(ppp_fd, PPPIOCGUNIT, &ifunit) == -1) { syslog(LOG_ERR, "ioctl(PPPIOCGUNIT): %m"); die(1); } diff --git a/usr.sbin/pppd/upap.c b/usr.sbin/pppd/upap.c index 2d07cfb9f..4e86062cf 100644 --- a/usr.sbin/pppd/upap.c +++ b/usr.sbin/pppd/upap.c @@ -511,7 +511,7 @@ upap_sauthreq(u) outlen = UPAP_HEADERLEN + 2 * sizeof (u_char) + u->us_userlen + u->us_passwdlen; outp = outpacket_buf; - + MAKEHEADER(outp, PPP_PAP); PUTCHAR(UPAP_AUTHREQ, outp); diff --git a/usr.sbin/pstat/pstat.c b/usr.sbin/pstat/pstat.c index 5e24424cf..f62c96c8a 100644 --- a/usr.sbin/pstat/pstat.c +++ b/usr.sbin/pstat/pstat.c @@ -238,7 +238,7 @@ main(int argc, char *argv[]) int longformat = 0, stringformat = 0, error = 0, n; uint32_t mask = ~0; char format[10], buf[1024]; - + n = strlen(dformat); if (n == 0) errx(1, "illegal format"); diff --git a/usr.sbin/radiusctl/radiusctl.c b/usr.sbin/radiusctl/radiusctl.c index c374884eb..ed6e5cded 100644 --- a/usr.sbin/radiusctl/radiusctl.c +++ b/usr.sbin/radiusctl/radiusctl.c @@ -239,7 +239,7 @@ radius_test(struct parse_result *res) test.res = res; test.sock = sock; test.reqpkt = reqpkt; - + event_set(&test.ev_recv, sock, EV_READ|EV_PERSIST, radius_test_recv, &test); diff --git a/usr.sbin/rbootd/utils.c b/usr.sbin/rbootd/utils.c index dc38cc1fd..57ca88c75 100644 --- a/usr.sbin/rbootd/utils.c +++ b/usr.sbin/rbootd/utils.c @@ -82,7 +82,7 @@ DispPkt(RMPCONN *rconn, int direct) fputs((direct==DIR_RCVD)?"<<< ":(direct==DIR_SENT)?">>> ":"", DbgFp); /* display packet timestamp */ - + tim = rconn->tstamp.tv_sec; tmp = localtime(&tim); fprintf(DbgFp, "%02d:%02d:%02d.%06ld ", tmp->tm_hour, tmp->tm_min, diff --git a/usr.sbin/rcctl/rcctl.sh b/usr.sbin/rcctl/rcctl.sh index eda191fae..951a010c5 100644 --- a/usr.sbin/rcctl/rcctl.sh +++ b/usr.sbin/rcctl/rcctl.sh @@ -275,7 +275,7 @@ svc_get() # these are expensive, make sure they are explicitly requested if [ -z "${_var}" -o "${_var}" = "class" ]; then getcap -f /etc/login.conf.d/${_svc}:/etc/login.conf \ - ${_svc} 1>/dev/null 2>&1 && daemon_class=${_svc} + ${_svc} 1>/dev/null 2>&1 && daemon_class=${_svc} [ -z "${daemon_class}" ] && \ daemon_class="$(svc_getdef ${_svc} class)" fi diff --git a/usr.sbin/repquota/repquota.c b/usr.sbin/repquota/repquota.c index 9a4cafcfe..6287a21ae 100644 --- a/usr.sbin/repquota/repquota.c +++ b/usr.sbin/repquota/repquota.c @@ -205,8 +205,8 @@ repquota(struct fstab *fs, int type, char *qfpathname) continue; printf("%-10s", fup->fu_name); printf("%c%c %7d %7d %7d %6s", - fup->fu_dqblk.dqb_bsoftlimit && - fup->fu_dqblk.dqb_curblocks >= + fup->fu_dqblk.dqb_bsoftlimit && + fup->fu_dqblk.dqb_curblocks >= fup->fu_dqblk.dqb_bsoftlimit ? '+' : '-', fup->fu_dqblk.dqb_isoftlimit && fup->fu_dqblk.dqb_curinodes >= @@ -217,8 +217,8 @@ repquota(struct fstab *fs, int type, char *qfpathname) / 1024), (int)(dbtob((u_quad_t)fup->fu_dqblk.dqb_bhardlimit) / 1024), - fup->fu_dqblk.dqb_bsoftlimit && - fup->fu_dqblk.dqb_curblocks >= + fup->fu_dqblk.dqb_bsoftlimit && + fup->fu_dqblk.dqb_curblocks >= fup->fu_dqblk.dqb_bsoftlimit ? timeprt(fup->fu_dqblk.dqb_btime) : ""); printf(" %6d %5d %5d %6s\n", diff --git a/usr.sbin/ripd/ripd.c b/usr.sbin/ripd/ripd.c index 6675a2041..9550f4309 100644 --- a/usr.sbin/ripd/ripd.c +++ b/usr.sbin/ripd/ripd.c @@ -376,7 +376,7 @@ main_dispatch_ripe(int fd, short event, void *bula) if (!shut) imsg_event_add(iev); else { - /* this pipe is dead, so remove the event handler */ + /* this pipe is dead, so remove the event handler */ event_del(&iev->ev); event_loopexit(NULL); } @@ -432,7 +432,7 @@ main_dispatch_rde(int fd, short event, void *bula) if (!shut) imsg_event_add(iev); else { - /* this pipe is dead, so remove the event handler */ + /* this pipe is dead, so remove the event handler */ event_del(&iev->ev); event_loopexit(NULL); } diff --git a/usr.sbin/ripd/ripe.c b/usr.sbin/ripd/ripe.c index c1b3c724e..e8b0539aa 100644 --- a/usr.sbin/ripd/ripe.c +++ b/usr.sbin/ripd/ripe.c @@ -291,7 +291,7 @@ ripe_dispatch_main(int fd, short event, void *bula) if (!shut) imsg_event_add(iev); else { - /* this pipe is dead, so remove the event handler */ + /* this pipe is dead, so remove the event handler */ event_del(&iev->ev); event_loopexit(NULL); } @@ -440,7 +440,7 @@ ripe_dispatch_rde(int fd, short event, void *bula) if (!shut) imsg_event_add(iev); else { - /* this pipe is dead, so remove the event handler */ + /* this pipe is dead, so remove the event handler */ event_del(&iev->ev); event_loopexit(NULL); } diff --git a/usr.sbin/route6d/route6d.c b/usr.sbin/route6d/route6d.c index 2ae2452a8..f1abc79b1 100644 --- a/usr.sbin/route6d/route6d.c +++ b/usr.sbin/route6d/route6d.c @@ -4,7 +4,7 @@ /* * Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project. * All rights reserved. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: @@ -16,7 +16,7 @@ * 3. Neither the name of the project nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE @@ -101,7 +101,7 @@ struct ifc { /* Configuration of an interface */ int ifc_joined; /* joined to ff02::9 */ }; -struct ifac { /* Address associated to an interface */ +struct ifac { /* Address associated to an interface */ struct ifc *ifa_conf; /* back pointer */ struct ifac *ifa_next; struct in6_addr ifa_addr; /* address */ @@ -671,8 +671,8 @@ ripsend(struct ifc *ifcp, struct sockaddr_in6 *sin6, int flag) * Request from non-link local address is not * a regular route6d update. */ - maxrte = (IFMINMTU - sizeof(struct ip6_hdr) - - sizeof(struct udphdr) - + maxrte = (IFMINMTU - sizeof(struct ip6_hdr) - + sizeof(struct udphdr) - sizeof(struct rip6) + sizeof(struct netinfo6)) / sizeof(struct netinfo6); nrt = 0; np = ripbuf->rip6_nets; nh = NULL; @@ -716,8 +716,8 @@ ripsend(struct ifc *ifcp, struct sockaddr_in6 *sin6, int flag) return; } - maxrte = (ifcp->ifc_mtu - sizeof(struct ip6_hdr) - - sizeof(struct udphdr) - + maxrte = (ifcp->ifc_mtu - sizeof(struct ip6_hdr) - + sizeof(struct udphdr) - sizeof(struct rip6) + sizeof(struct netinfo6)) / sizeof(struct netinfo6); @@ -792,13 +792,13 @@ out_filter(struct riprt *rrt, struct ifc *ifcp) /* * -A: filter out less specific routes, if we have aggregated * route configured. - */ + */ for (iffp = ifcp->ifc_filter; iffp; iffp = iffp->iff_next) { if (iffp->iff_type != 'A') continue; if (rrt->rrt_info.rip6_plen <= iffp->iff_plen) continue; - ia = rrt->rrt_info.rip6_dest; + ia = rrt->rrt_info.rip6_dest; applyplen(&ia, iffp->iff_plen); if (IN6_ARE_ADDR_EQUAL(&ia, &iffp->iff_addr)) return 0; @@ -834,7 +834,7 @@ out_filter(struct riprt *rrt, struct ifc *ifcp) continue; if (rrt->rrt_info.rip6_plen < iffp->iff_plen) continue; - ia = rrt->rrt_info.rip6_dest; + ia = rrt->rrt_info.rip6_dest; applyplen(&ia, iffp->iff_plen); if (IN6_ARE_ADDR_EQUAL(&ia, &iffp->iff_addr)) { ok = 1; @@ -1044,8 +1044,8 @@ riprecv(void) } else { riprequest(NULL, np, nn, &fsock); } - return; - } + return; + } if (!IN6_IS_ADDR_LINKLOCAL(&fsock.sin6_addr)) { log_debug("Response from non-ll addr: %s", @@ -1094,7 +1094,7 @@ riprecv(void) return; /* The packet is from me; ignore */ if (rp->rip6_cmd != RIP6_RESPONSE) { log_debug("Invalid command %d", rp->rip6_cmd); - return; + return; } /* -N: no use */ @@ -1174,7 +1174,7 @@ riprecv(void) /* special rule: ::/0 means default, not "in /0" */ if (iffp->iff_plen == 0 && np->rip6_plen > 0) continue; - ia = np->rip6_dest; + ia = np->rip6_dest; applyplen(&ia, iffp->iff_plen); if (IN6_ARE_ADDR_EQUAL(&ia, &iffp->iff_addr)) { ok = 1; @@ -1229,7 +1229,7 @@ riprecv(void) } else if (nq->rip6_metric == np->rip6_metric && np->rip6_metric < HOPCNT_INFINITY6) { if (rrt->rrt_index == ifcp->ifc_index && - IN6_ARE_ADDR_EQUAL(&nh, &rrt->rrt_gw)) { + IN6_ARE_ADDR_EQUAL(&nh, &rrt->rrt_gw)) { /* same metric, same route from same gw */ rrt->rrt_t = t; } else if (rrt->rrt_t < t_half_lifetime) { @@ -1244,7 +1244,7 @@ riprecv(void) rrt->rrt_t = t; } } - /* + /* * if nq->rip6_metric == HOPCNT_INFINITY6 then * do not update age value. Do nothing. */ @@ -2954,7 +2954,7 @@ ifonly: #if 0 /* * When the address has already been registered in the - * kernel routing table, it should be removed + * kernel routing table, it should be removed */ delroute(&rrt->rrt_info, &gw); #else @@ -3038,7 +3038,7 @@ mask2len(const struct in6_addr *addr, int lenlim) { int i = 0, j; const u_char *p = (const u_char *)addr; - + for (j = 0; j < lenlim; j++, p++) { if (*p != 0xff) break; @@ -3151,7 +3151,7 @@ ripsuptrig(void) time_t t; double r = arc4random(); - t = (int)(RIP_TRIG_INT6_MIN + + t = (int)(RIP_TRIG_INT6_MIN + (RIP_TRIG_INT6_MAX - RIP_TRIG_INT6_MIN) * (r / UINT32_MAX)); sup_trig_update = time(NULL) + t; return t; diff --git a/usr.sbin/route6d/route6d.h b/usr.sbin/route6d/route6d.h index 75c7bb73a..226f58202 100644 --- a/usr.sbin/route6d/route6d.h +++ b/usr.sbin/route6d/route6d.h @@ -4,7 +4,7 @@ /* * Copyright (C) 1995, 1996, 1997, and 1998 WIDE Project. * All rights reserved. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: @@ -16,7 +16,7 @@ * 3. Neither the name of the project nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE PROJECT AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE diff --git a/usr.sbin/rpc.lockd/lockd_lock.c b/usr.sbin/rpc.lockd/lockd_lock.c index bb751cbb0..43e90dbc4 100644 --- a/usr.sbin/rpc.lockd/lockd_lock.c +++ b/usr.sbin/rpc.lockd/lockd_lock.c @@ -204,7 +204,7 @@ testlock(struct nlm4_lock *lock, int flags) } /* - * getlock: try to acquire the lock. + * getlock: try to acquire the lock. * If file is already locked and we can sleep, put the lock in the list with * status LKST_WAITING; it'll be processed later. * Otherwise try to lock. If we're allowed to block, fork a child which @@ -220,7 +220,7 @@ getlock(nlm4_lockargs * lckarg, struct svc_req *rqstp, int flags) if (grace_expired == 0 && lckarg->reclaim == 0) return (flags & LOCK_V4) ? nlm4_denied_grace_period : nlm_denied_grace_period; - + /* allocate new file_lock for this request */ newfl = lalloc(); if (newfl == NULL) { @@ -265,7 +265,7 @@ getlock(nlm4_lockargs * lckarg, struct svc_req *rqstp, int flags) if (newfl->client_cookie.n_bytes == NULL) { syslog(LOG_NOTICE, "malloc failed (%m)"); lfree(newfl); - return (flags & LOCK_V4) ? + return (flags & LOCK_V4) ? nlm4_denied_nolock : nlm_denied_nolocks; } memcpy(newfl->client_cookie.n_bytes, lckarg->cookie.n_bytes, @@ -472,7 +472,7 @@ sigchild_handler(int sig) do_unlock(fl); return; } - + /* check lock status */ syslog(LOG_DEBUG, "processing child %d, status %d", pid, fl->status); @@ -559,7 +559,7 @@ do_lock(struct file_lock *fl, int block) syslog(LOG_NOTICE, "flock failed (%m)"); _exit(1); } - /* lock granted */ + /* lock granted */ _exit(0); /*NOTREACHED*/ default: @@ -731,7 +731,7 @@ void siglock(void) { sigset_t block; - + sigemptyset(&block); sigaddset(&block, SIGCHLD); @@ -744,7 +744,7 @@ void sigunlock(void) { sigset_t block; - + sigemptyset(&block); sigaddset(&block, SIGCHLD); diff --git a/usr.sbin/rpc.lockd/procs.c b/usr.sbin/rpc.lockd/procs.c index daafeea13..c862ecce9 100644 --- a/usr.sbin/rpc.lockd/procs.c +++ b/usr.sbin/rpc.lockd/procs.c @@ -60,7 +60,7 @@ * Notes: Extracts the source address from the transport handle * passed in as part of the called procedure specification */ -static void +static void log_from_addr(char *fun_name, struct svc_req *req) { struct sockaddr_in *addr; @@ -195,7 +195,7 @@ get_client(struct sockaddr_in *host_addr, u_long vers) * calling it with timeout 0 as a hack to just issue a datagram * without expecting a result */ -void +void transmit_result(int opcode, nlm_res *result, struct sockaddr_in *addr) { static char dummy; diff --git a/usr.sbin/rpc.lockd/test.c b/usr.sbin/rpc.lockd/test.c index 8a6dce685..2e2616001 100644 --- a/usr.sbin/rpc.lockd/test.c +++ b/usr.sbin/rpc.lockd/test.c @@ -275,7 +275,7 @@ nlm_free_all_3(nlm_notify *argp, CLIENT *clnt) } -int +int main(int argc, char **argv) { CLIENT *cli; diff --git a/usr.sbin/sasyncd/monitor.c b/usr.sbin/sasyncd/monitor.c index 60b11e333..514a8ff13 100644 --- a/usr.sbin/sasyncd/monitor.c +++ b/usr.sbin/sasyncd/monitor.c @@ -484,7 +484,7 @@ m_priv_iked_imsg(u_int cmd) if (connect(fd, (struct sockaddr *)&sun, sizeof(sun)) == -1) { log_err("m_priv_iked_imsg: connect"); - goto out; + goto out; } imsg_init(&ibuf, fd); diff --git a/usr.sbin/slowcgi/slowcgi.c b/usr.sbin/slowcgi/slowcgi.c index 9a0f8b565..4b5e1fad5 100644 --- a/usr.sbin/slowcgi/slowcgi.c +++ b/usr.sbin/slowcgi/slowcgi.c @@ -307,7 +307,7 @@ main(int argc, char *argv[]) fcgi_socket = optarg; break; case 't': - timeout.tv_sec = strtonum(optarg, 1, TIMEOUT_MAX, + timeout.tv_sec = strtonum(optarg, 1, TIMEOUT_MAX, &errstr); if (errstr != NULL) errx(1, "timeout is %s: %s", errstr, optarg); diff --git a/usr.sbin/unbound/doc/Changelog b/usr.sbin/unbound/doc/Changelog index be48561d8..c495795be 100644 --- a/usr.sbin/unbound/doc/Changelog +++ b/usr.sbin/unbound/doc/Changelog @@ -228,7 +228,7 @@ either we set up a TLS connection or we return an error. 21 March 2023: Philip - - Fix issue #851: reserved identifier violation + - Fix issue #851: reserved identifier violation 20 March 2023: Wouter - iana portlist update. @@ -2808,7 +2808,7 @@ SOA serial probes. This fixes that probes fail because earlier probe addresses are unreachable. - Fix that auth zone fails over to next master for timeout in tcp. - - Squelch SSL read and write connection reset by peer and broken pipe + - Squelch SSL read and write connection reset by peer and broken pipe messages. Verbosity 2 and higher enables them. 8 April 2019: Wouter @@ -3210,7 +3210,7 @@ this omits 'can't assign requested address' errors unless verbosity is set to a high value. - Set default for so-reuseport to no for FreeBSD. It is enabled - by default for Linux and DragonFlyBSD. The setting can + by default for Linux and DragonFlyBSD. The setting can be configured in unbound.conf to override the default. - iana port update. @@ -3810,7 +3810,7 @@ - Fixed contrib/fastrpz.patch, even though this already applied cleanly for me, now also for others. - patch to log creates keytag queries, from A. Schulze. - - patch suggested by Debian lintian: allow to -> allow one to, from + - patch suggested by Debian lintian: allow to -> allow one to, from A. Schulze. - Attempt to remove warning about trailing whitespace. @@ -3961,39 +3961,39 @@ - Check whether --with-libunbound-only is set when using --with-nettle or --with-nss. -4 December 2017: Wouter +4 December 2017: Wouter - Fix link failure on OmniOS. -1 December 2017: Wouter +1 December 2017: Wouter - auth zone work. -30 November 2017: Wouter +30 November 2017: Wouter - Fix #3299 - forward CNAME daisy chain is not working -14 November 2017: Wouter +14 November 2017: Wouter - Fix #2882: Unbound behaviour changes (wrong) when domain-insecure is set for stub zone. It no longer searches for DNSSEC information. - auth xfer work on probe timer and lookup. -13 November 2017: Wouter +13 November 2017: Wouter - Fix #2801: Install libunbound.pc. - Fix qname minimisation to send AAAA queries at zonecut like type A. - reverted AAAA change. -7 November 2017: Wouter +7 November 2017: Wouter - Fix #2492: Documentation libunbound. -3 November 2017: Wouter +3 November 2017: Wouter - Fix #2362: TLS1.3/openssl-1.1.1 not working. - Fix #2034 - Autoconf and -flto. - Fix #2141 - for libsodium detect lack of entropy in chroot, print a message and exit. -2 November 2017: Wouter +2 November 2017: Wouter - Fix #1913: ub_ctx_config is under circumstances thread-safe. - make ip-transparent option work on OpenBSD. -31 October 2017: Wouter +31 October 2017: Wouter - Document that errno is left informative on libunbound config read fail. - lexer output. @@ -4007,13 +4007,13 @@ 24 October 2017: Ralph - Update B root ipv4 address. -19 October 2017: Wouter +19 October 2017: Wouter - authzone work, probe timer setup. -18 October 2017: Wouter +18 October 2017: Wouter - lint for recent authzone commit. -17 October 2017: Wouter +17 October 2017: Wouter - Fix #1749: With harden-referral-path: performance drops, due to circular dependency in NS and DS lookups. - [dnscrypt] prevent dnscrypt-secret-key, dnscrypt-provider-cert @@ -4033,19 +4033,19 @@ - Better documentation for cache-max-negative-ttl. - Work on local root zone code. -10 October 2017: Wouter +10 October 2017: Wouter - tag 1.6.7 - trunk has version 1.6.8. -6 October 2017: Wouter +6 October 2017: Wouter - Fix spelling in unbound-control man page. -5 October 2017: Wouter +5 October 2017: Wouter - Fix trust-anchor-signaling works in libunbound. - Fix some more crpls in testdata for different signaling default. - tag 1.6.7rc1 -5 October 2017: Ralph +5 October 2017: Ralph - Set trust-anchor-signaling default to yes - Use RCODE from A query on DNS64 synthesized answer. @@ -4391,7 +4391,7 @@ - sldns SMIMEA and AVC definitions, same as getdns definitions. 1 May 2017: Wouter - - Fix #1259: "--disable-ecdsa" argument overwritten + - Fix #1259: "--disable-ecdsa" argument overwritten by "#ifdef SHA256_DIGEST_LENGTH@daemon/remote.c". - iana portlist update - Fix #1258: Windows 10 X64 unbound 1.6.2 service will not start. @@ -4413,7 +4413,7 @@ 21 April 2017: Ralph - Fix #1254: clarify ratelimit-{for,below}-domain (from Manu Bretelle). - iana portlist update - + 18 April 2017: Ralph - Fix #1252: more indentation inconsistencies. - Fix #1253: unused variable in edns-subnet/addrtree.c:getbit(). @@ -4514,7 +4514,7 @@ 21 March 2017: Ralph - Merge EDNS Client subnet implementation from feature branch into main - branch, using new EDNS processing framework. + branch, using new EDNS processing framework. 21 March 2017: Wouter - Fix doxygen for dnscrypt files. @@ -4647,7 +4647,7 @@ - iana portlist update 12 January 2017: Wouter - - Fix to also block meta types 128 through to 248 with formerr. + - Fix to also block meta types 128 through to 248 with formerr. - Fix #1206: Some view-related commands are missing from 'unbound-control -h' 9 January 2017: Wouter @@ -4926,8 +4926,8 @@ - Add default root hints for IPv6 E.ROOT-SERVERS.NET, 2001:500:a8::e. 25 August 2016: Ralph - - Clarify local-zone-override entry in unbound.conf.5 - + - Clarify local-zone-override entry in unbound.conf.5 + 25 August 2016: Wouter - 64bit build option for makedist windows compile, -w64. @@ -4937,7 +4937,7 @@ - unbound.conf.5 entries for define-tag, access-control-tag, access-control-tag-action, access-control-tag-data, local-zone-tag, and local-zone-override. - + 23 August 2016: Wouter - Fix #804: unbound stops responding after outage. Fixes queries that attempt to wait for an empty list of subqueries. @@ -5129,7 +5129,7 @@ harden-below-nxdomain documentation. 20 May 2016: Ralph - - No QNAME minimisation fall-back for NXDOMAIN answers from DNSSEC + - No QNAME minimisation fall-back for NXDOMAIN answers from DNSSEC signed zones. - iana portlist update. @@ -5326,7 +5326,7 @@ warnings. 15 December 2015: Ralph - - Fix #729: omit use of escape sequences in echo since they are not + - Fix #729: omit use of escape sequences in echo since they are not portable (unbound-control-setup). 11 December 2015: Wouter @@ -5353,7 +5353,7 @@ 3 December 2015: Ralph - (after rc1 tag) - Committed fix to qname minimisation and unit test case for it. - + 3 December 2015: Wouter - iana portlist update. - 1.5.7rc1 prerelease tag. @@ -6302,7 +6302,7 @@ - if configured --with-libunbound-only fix make install. 31 Oct 2013: Wouter - - Fix #531: Set SO_REUSEADDR so that the wildcard interface and a + - Fix #531: Set SO_REUSEADDR so that the wildcard interface and a more specific interface port 53 can be used at the same time, and one of the daemons is unbound. - iana portlist update. @@ -6855,7 +6855,7 @@ - iter forwards uses malloc inside for more dynamicity. 13 February 2012: Wouter - - RT#2955. Fix for cygwin compilation. + - RT#2955. Fix for cygwin compilation. - iana portlist updated. 10 February 2012: Wouter @@ -7028,7 +7028,7 @@ Matthew Lee). 21 October 2011: Wouter - - fix --enable-allsymbols, fptr wlist is disabled on windows with this + - fix --enable-allsymbols, fptr wlist is disabled on windows with this option enabled because of memory layout exe vs dll. 19 October 2011: Wouter @@ -7522,7 +7522,7 @@ 16 August 2010: Wouter - Fix acx_nlnetlabs.m4 configure output for autoconf-2.66 AS_TR_CPP changes, uses m4_bpatsubst now. - - make test (or make check) should be more portable and run the unit + - make test (or make check) should be more portable and run the unit test and testbound scripts. (make longtest has special requirements). 13 August 2010: Wouter @@ -7615,7 +7615,7 @@ 23 June 2010: Wouter - iana portlist updated. - - makedist upgraded cross compile openssl option, like this: + - makedist upgraded cross compile openssl option, like this: ./makedist.sh -s -wssl openssl-1.0.0a.tar.gz -w --enable-gost 22 June 2010: Wouter @@ -7644,7 +7644,7 @@ - added documentation for the histogram printout to syslog. 11 June 2010: Wouter - - When retry to parent the retrycount is not wiped, so failed + - When retry to parent the retrycount is not wiped, so failed nameservers are not tried again. - iana portlist updated. @@ -7674,7 +7674,7 @@ - new splint flags for newer splint install. 31 May 2010: Wouter - - Fix AD flag handling, it could in some cases mistakenly copy the AD + - Fix AD flag handling, it could in some cases mistakenly copy the AD flag from upstream servers. - alloc_special_obtain out of memory is not a fatal error any more, enabling unbound to continue longer in out of memory conditions. @@ -7734,7 +7734,7 @@ it was possible to not expire host data (if accessed often). 28 April 2010: Wouter - - ldns tarball updated and GOST support is detected and then enabled. + - ldns tarball updated and GOST support is detected and then enabled. - iana portlist updated. - Fix detection of gost support in ldns (reported by Chris Smith). @@ -7755,7 +7755,7 @@ no more double include. - More strict scrubber (Thanks to George Barwood for the idea): NS set must be pertinent to the query (qname subdomain nsname). - - Fix bug#307: In 0x20 backoff fix fallback so the number of + - Fix bug#307: In 0x20 backoff fix fallback so the number of outstanding queries does not become -1 and block the request. Fixed handling of recursion-lame in combination with 0x20 fallback. Fix so RRsets are compared canonicalized and sorted if the immediate @@ -7799,8 +7799,8 @@ 6 April 2010: Wouter - Fix EDNS probe for .de DNSSEC testbed failure, where the infra - cache timeout coincided with a server update, the current EDNS - backoff is less sensitive, and does not cache the backoff unless + cache timeout coincided with a server update, the current EDNS + backoff is less sensitive, and does not cache the backoff unless the backoff actually works and the domain is not expecting DNSSEC. - GOST support with correct algorithm numbers. @@ -7918,7 +7918,7 @@ - iana portlist updated. 16 February 2010: Wouter - - Check for 'no space left on device' (or other errors) when + - Check for 'no space left on device' (or other errors) when writing updated autotrust anchors and print errno to log. 15 February 2010: Wouter @@ -8007,7 +8007,7 @@ - review comments. - tag 1.4.1. - trunk to version 1.4.2. - + 15 December 2009: Wouter - Answer to qclass=ANY queries, with class IN contents. Test that validation also works. @@ -8089,14 +8089,14 @@ - fix manpage errors reported by debian lintian. - review comments. - fixup very long vallog2 level error strings. - + 11 November 2009: Wouter - ldns tarball updated (to 1.6.2). - review comments. 10 November 2009: Wouter - Thanks to Surfnet found bug in new dnssec-retry code that failed - to combine well when combined with DLV and a particular failure. + to combine well when combined with DLV and a particular failure. - Fixed unbound-control -h output about argument optionality. - review comments. @@ -8127,7 +8127,7 @@ - please doxygen - add val-log-level print to corner case (nameserver.epost.bg). - more detail to errors from insecure delegation checks. - - Fix double time subtraction in negative cache reported by + - Fix double time subtraction in negative cache reported by Amanda Constant and Hugh Mahon. - Made new validator error string available from libunbound for applications. It is in result->why_bogus, a zero-terminated string. @@ -8306,7 +8306,7 @@ - autotrust: process events. 17 August 2009: Wouter - - Fix so that servers are only blacklisted if they fail to reply + - Fix so that servers are only blacklisted if they fail to reply to 16 queries in a row and the timeout gets above 2 minutes. - autotrust work, split up DS verification of DNSKEYs. @@ -8429,7 +8429,7 @@ - iana portlist updated. (one less port allocated, one more fraction of a bit for security!) - updated fedora specfile in contrib from Paul Wouters. - + 19 June 2009: Wouter - Fixup strict aliasing warning in iter priv code. and config_file code. @@ -8489,7 +8489,7 @@ 9 June 2009: Wouter - openssl key files are opened apache-style, when user is root and - before chrooting. This makes permissions on remote-control key + before chrooting. This makes permissions on remote-control key files easier to set up. Fixes bug #251. - flush_type and flush_name remove msg cache entries. - codereview - dp copy bogus setting fix. @@ -8540,7 +8540,7 @@ Assertion checked if recursion parent query still existed. 29 April 2009: Wouter - - Thanks to Brett Carr, caught windows resource leak, use + - Thanks to Brett Carr, caught windows resource leak, use closesocket() and not close() on sockets or else the network stack starts to leak handles. - Removed usage of windows Mutex because windows cannot handle enough @@ -8611,9 +8611,9 @@ - nxdomain ttl considerations in requirements.txt 3 April 2009: Wouter - - Fixed a bug that caused messages to be stored in the cache too + - Fixed a bug that caused messages to be stored in the cache too long. Hard to trigger, but NXDOMAINs for nameservers or CNAME - targets have been more vulnerable to the TTL miscalculation bug. + targets have been more vulnerable to the TTL miscalculation bug. - documentation test fixed for python addition. 2 April 2009: Wouter @@ -8621,7 +8621,7 @@ - documentation for pythonmod and pyunbound is generated in doc/html. - iana portlist updated. - fixed bug in unbound-control flush_zone where it would not flush - every message in the target domain. This especially impacted + every message in the target domain. This especially impacted NXDOMAIN messages which could remain in the cache regardless. - python module test package. @@ -8719,7 +8719,7 @@ 11 March 2009: Wouter - winsock event handler resets WSAevents after signalled. - winsock event handler tests if signals are really signalled. - - install and service with log to file works on XP and Vista on + - install and service with log to file works on XP and Vista on default install location. - on windows logging to the Application logbook works (as a service). - fix RUN_DIR on windows compile setting in makedist. @@ -8751,7 +8751,7 @@ - document FAQ entry on stub/forward zones and default blocking. - fix asynclook test app for libunbound not exporting symbols. - service install and remove utils that work with vista UAC. - + 27 February 2009: Wouter - Fixup lexer, to not give warnings about fwrite. Appeared in new lexer features. @@ -8780,13 +8780,13 @@ builtin. The program uses wget and gpg to work. - iana portlist updated. - update-itar.sh: using ftp:// urls because https godaddy certificate - is not available everywhere and then gives fatal errors. The + is not available everywhere and then gives fatal errors. The security is provided by pgp signature. 18 February 2009: Wouter - more cycle detection. Also for target queries. - fixup bug where during deletion of the mesh queries the callbacks - that were reentrant caused assertion failures. Keep the mesh in + that were reentrant caused assertion failures. Keep the mesh in a reentrant safe state. Affects libunbound, reload of server, on quit and flush_requestlist. - iana portlist updated. @@ -8820,7 +8820,7 @@ - iana portlist updated. - fixup EOL in include directive (reported by Paul Wouters). You can no longer specify newlines in the names of included files. - - config parser changed. Gives some syntax errors closer to where they + - config parser changed. Gives some syntax errors closer to where they occurred. Does not enforce a space after keyword anymore. Does not allow literal newlines inside quoted strings anymore. - verbosity level 5 logs customer IP for new requestlist entries. @@ -8836,15 +8836,15 @@ - 1.3.0 development continues: change in libunbound API: ub_cancel can return an error, that the async_id did not exist, or that it was already delivered. - The result could have been delivered just before the cancel + The result could have been delivered just before the cancel routine managed to acquire the lock, so a caller may get the - result at the same time they call cancel. For this case, + result at the same time they call cancel. For this case, ub_cancel tries to return an error code. Fixes race condition in ub_cancel() libunbound function. - MacOSX Leopard cleaner text output from configure. - initgroups(3) is called to drop secondary group permissions, if applicable. - - configure option --with-ldns-builtin forces the use of the + - configure option --with-ldns-builtin forces the use of the inluded ldns package with the unbound source. The -I include is put before the others, so it avoids bad include files from an older ldns install. @@ -8865,13 +8865,13 @@ available (network unreachable). Debug still printed on high verbosity. - unbound-host -4 and -6 options. Stops annoying ipv6 errors when - debugging with unbound-host -4 -d ... + debugging with unbound-host -4 -d ... - more cycle detection for NS-check, addr-check, root-prime and stub-prime queries in the iterator. Avoids possible deadlock when priming fails. 15 January 2009: Wouter - - bug #229: fixup configure checks for compilation with Solaris + - bug #229: fixup configure checks for compilation with Solaris Sun cc compiler, ./configure CC=/opt/SUNWspro/bin/cc - fixup suncc warnings. - fix bug where unbound could crash using libevent 1.3 and older. @@ -8909,7 +8909,7 @@ - removed debug print. 8 January 2009: Wouter - - new version of ldns-trunk (today) included as tarball, fixed + - new version of ldns-trunk (today) included as tarball, fixed bug #224, building with -j race condition. - remove possible race condition in the test for race conditions. @@ -9057,7 +9057,7 @@ 11 November 2008: Wouter - unit test for negative cache, stress tests the refcounting. - fix for refcounting error that could cause fptr_wlist fatal exit - in the negative cache rbtree (upcoming 1.1 feature). (Thanks to + in the negative cache rbtree (upcoming 1.1 feature). (Thanks to Attila Nagy for testing). - nicer comments in cachedump about failed RR to string conversion. - fix 32bit wrap around when printing large (4G and more) mem usage @@ -9130,7 +9130,7 @@ 20 October 2008: Wouter - quench a log message that is debug only. - iana portlist updated. - - do not query bogus nameservers. It is like nameservers that have + - do not query bogus nameservers. It is like nameservers that have the NS or A or AAAA record bogus are listed as donotquery. - if server selection is faced with only bad choices, it will attempt to get more options to be fetched. @@ -9140,7 +9140,7 @@ the operators get the problem fixed sooner. It makes validation failures go away sooner (60 seconds after the zone is fixed). Also it is likely to try different nameserver targets every minute, - so that if a zone is bad on one server but not another, it is + so that if a zone is bad on one server but not another, it is likely to pick up the 'correct' one after a couple minutes, and if the TTL is big enough that solves validation for the zone. - fixup unbound-control compilation on windows. @@ -9175,7 +9175,7 @@ 13 October 2008: Wouter - fixed recursion servers deployed as authoritative detection, so - that as a last resort, a +RD query is sent there to get the + that as a last resort, a +RD query is sent there to get the correct answer. - iana port list update. - ldns tarball is snapshot of ldns r2759 (1.4.0-pre-20081013). @@ -9354,13 +9354,13 @@ - negative cache code, reviewed. 18 August 2008: Wouter - - changes info: in logfile to notice: info: or debug: depending on + - changes info: in logfile to notice: info: or debug: depending on the verbosity of the statements. Better logfile message classification. - bug #208: extra rc.d unbound flexibility for freebsd/nanobsd. 15 August 2008: Wouter - - DLV nsec code fixed for better detection of closest existing + - DLV nsec code fixed for better detection of closest existing enclosers from NSEC responses. - DLV works, straight to the dlv repository, so not for production. - Iana port update. @@ -9393,7 +9393,7 @@ validator is used on those NS records (if anchors enabled). 7 August 2008: Wouter - - Scrubber more strict. CNAME chains, DNAMEs from cache, other + - Scrubber more strict. CNAME chains, DNAMEs from cache, other irrelevant rrsets removed. - 1.0.2 released from 1.0 support branch. - fixup update-anchor.sh to work both in BSD shell and bash. @@ -9402,7 +9402,7 @@ - fixup DS test so apex nodata works again. 4 August 2008: Wouter - - iana port update. + - iana port update. - TODO update. - fix bug 201: null ptr deref on cleanup while udp pkts wait for port. - added explanatory text for outgoing-port-permit in manpage. @@ -9508,7 +9508,7 @@ - WSA Startup and Cleanup called in unbound.exe. 13 June 2008: Wouter - - port mingw32, more signal ifdefs, detect sleep, usleep, + - port mingw32, more signal ifdefs, detect sleep, usleep, random, srandom (used inside the tests). - signed or unsigned FD_SET is cast. @@ -9545,24 +9545,24 @@ 2 June 2008: Wouter - Jelte fixed bugs in my absence - - bug 178: fixed unportable shell usage in configure (relied on + - bug 178: fixed unportable shell usage in configure (relied on bash shell). - bug 180: fixed buffer overflow in unbound-checkconf use of strncat. - bug 181: fixed buffer overflow in ldns (called by unbound to parse config file parts). - fixes by Wouter - - bug 177: fixed compilation failure on opensuse, the - --disable-static configure flag caused problems. (Patch from + - bug 177: fixed compilation failure on opensuse, the + --disable-static configure flag caused problems. (Patch from Klaus Singvogel) - bug 179: same fix as 177. - - bug 185: --disable-shared not passed along to ldns included with + - bug 185: --disable-shared not passed along to ldns included with unbound. Fixed so that configure parameters are passed to the subdir configure script. fixed that ./libtool is used always, you can still override manually with ./configure libtool=mylibtool or set $libtool in the environment. - update of the ldns tarball to current ldns svn version (fix 181). - - bug 184: -r option for unbound-host, read resolv.conf for + - bug 184: -r option for unbound-host, read resolv.conf for forwarder. (Note that forwarder must support DNSSEC for validation to succeed). @@ -9703,7 +9703,7 @@ section must be present in the reply (by the scrubber). And it must be equal to the question sent, at least lowercase folded. Previously this feature happened because the cache code refused - to store such messages. However blocking by the scrubber makes + to store such messages. However blocking by the scrubber makes sure nothing gets into the RRset cache. Also, this looks like a timeout (instead of an allocation failure) and this retries are done (which is useful in a spoofing situation). @@ -9711,7 +9711,7 @@ include unknown servers. This makes unbound explore unknown servers. 7 March 2008: Wouter - - -C config feature for harvest program. + - -C config feature for harvest program. - harvest handles CNAMEs too. 5 March 2008: Wouter @@ -9719,7 +9719,7 @@ 4 March 2008: Wouter - From report by Jinmei Tatuya, rfc2181 trust value for remainder - of a cname trust chain is lower; not full answer_AA. + of a cname trust chain is lower; not full answer_AA. - test for this fix. - default config file location is /usr/local/etc/unbound. Thus prefix is used to determine the location. This is also the @@ -9750,7 +9750,7 @@ - harvest debug tool 26 February 2008: Wouter - - delay utility delays TCP as well. If the server that is forwarded + - delay utility delays TCP as well. If the server that is forwarded to has a TCP error, the delay utility closes the connection. - delay does REUSE_ADDR, and can handle a server that closes its end. - answers use casing from query. @@ -9782,7 +9782,7 @@ 21 February 2008: Wouter - speedup of root-delegation message encoding by 15%. - minor speedup of compress tree_lookup, maybe 1%. - - speedup of dname_lab_cmp and memlowercmp - the top functions in + - speedup of dname_lab_cmp and memlowercmp - the top functions in profiler output, maybe a couple percent when it matters. 20 February 2008: Wouter @@ -9801,7 +9801,7 @@ to default 'no'). - time is only gotten once and the value is shared across unbound. - unittest cleans up crypto, so that it has no memory leaks. - - mini_event shares the time value with unbound this results in + - mini_event shares the time value with unbound this results in +3% speed for cache responses and +9% for recursions. - ldns tarball update with new NSEC3 sign code numbers. - perform several reads per UDP operation. This improves performance @@ -9809,11 +9809,11 @@ improves cache response +50%, and recursions +10%. - modified asynclook test. because the callback from async is not in any sort of lock (and thus can use all library functions freely), - this causes a tiny race condition window when the last lock is + this causes a tiny race condition window when the last lock is released for a callback and a new cancel() for that callback. - The only way to remove this is by putting callbacks into some + The only way to remove this is by putting callbacks into some lock window. I'd rather have the small possibility of a callback - for a cancelled function then no use of library functions in + for a cancelled function then no use of library functions in callbacks. Could be possible to only outlaw process(), wait(), cancel() from callbacks, by adding another lock, but I'd rather not. @@ -9822,12 +9822,12 @@ - unbound host prints errors if fails to configure context. - fixup perf to resend faster, so that long waiting requests do not hold up the queue, they become lost packets or SERVFAILs, - or can be sent a little while later (i.e. processing time may + or can be sent a little while later (i.e. processing time may take long, but throughput has to be high). - fixup iterator operating in no cache conditions (RD flag unset after a CNAME). - streamlined code for RD flag setting. - - profiled code and changed dname compares to be faster. + - profiled code and changed dname compares to be faster. The speedup is about +3% to +8% (depending on the test). - minievent tests for eintr and eagain. @@ -9872,7 +9872,7 @@ 7 February 2008: Wouter - moved up all current level 2 to be level 3. And 3 to 4. - to make room for new debug level 2 for detailed information + to make room for new debug level 2 for detailed information for operators. - verbosity level 2. Describes recursion and validation. - cleaner configure script and fixes for libevent solaris. @@ -9901,7 +9901,7 @@ 30 January 2008: Wouter - check trailing / on chrootdir in checkconf. - check if root hints and anchor files are in chrootdir. - - no route to host tcp error is verbosity level 2. + - no route to host tcp error is verbosity level 2. - removed unused send_reply_iov. and its configure check. - added prints of 'remote address is 1.2.3.4 port 53' to errors from netevent; the basic socket errors. @@ -9922,7 +9922,7 @@ - close fds after removing commpoints only (for epoll, kqueue). 25 January 2008: Wouter - - added tpkg for asynclook and library use. + - added tpkg for asynclook and library use. - allows localhost to be queried when as a library. - fixup race condition between cancel and answer (in case of really fast answers that beat the cancel). @@ -10007,7 +10007,7 @@ - ldns.tgz updated with ldns-trunk (where buffer.h is updated). - fix lint, unit test in optimize mode. - default access control allows ::ffff:127.0.0.1 v6mapped localhost. - + 11 January 2008: Wouter - man page, warning removed. - added text describing the use of stub zones for private zones. @@ -10035,7 +10035,7 @@ 2 January 2008: Wouter - fixup typo in requirements. - - document that 'refused' is a better choice than 'drop' for + - document that 'refused' is a better choice than 'drop' for the access control list, as refused will stop retries. 7 December 2007: Wouter @@ -10091,7 +10091,7 @@ - library extensive featurelist added to TODO. - please doxygen, lint. - library test application, with basic functionality. - - fix for building in a subdirectory. + - fix for building in a subdirectory. - link lib fix for Leopard. 30 November 2007: Wouter @@ -10145,7 +10145,7 @@ * But not: wildcard, nsec, referral, rrsig, cname/dname, or additional section processing, NS put in auth. - test for correct working of static and transparent and couple - of important defaults (localhost, as112, reverses). + of important defaults (localhost, as112, reverses). Also checks deny and refuse settings. - fixup implicit zone generation and AA bit for NXDOMAIN on localdata. @@ -10157,7 +10157,7 @@ - local-zone and local-data options, config storage and documentation. 19 November 2007: Wouter - - do not downcase NSEC and RRSIG for verification. Follows + - do not downcase NSEC and RRSIG for verification. Follows draft-ietf-dnsext-dnssec-bis-updates-06.txt. - fixup leaking unbound daemons at end of tests. - README file updated. @@ -10182,7 +10182,7 @@ 14 November 2007: Wouter - testbed script does not recreate configure, since its in svn now. - - fixup checkconf test so that it does not test + - fixup checkconf test so that it does not test /etc/unbound/unbound.conf. - tag 0.6. @@ -10203,7 +10203,7 @@ If it doesn't exist, it is installed with the doc/example.conf file. The file is not deleted on uninstall. - default listening is not all, but localhost interfaces. - + 8 November 2007: Wouter - Fixup chroot and drop user privileges. - new L root ip address in default hints. @@ -10267,8 +10267,8 @@ - added configure (and its files) to svn, so that the trunk is easier to use. ./configure, config.guess, config.sub, ltmain.sh, and config.h.in. - - added yacc/lex generated files, util/configlexer.c, - util/configparser.c util/configparser.h, to svn. + - added yacc/lex generated files, util/configlexer.c, + util/configparser.c util/configparser.h, to svn. - without lex no attempt to use it. - unsecure response validation collated into one block. - remove warning about const cast of cfgfile name. @@ -10278,7 +10278,7 @@ make arguments from the unbound make invocation. - nicer error when libevent problem causes instant exit on signal. - read root hints from a root hint file (like BIND does). - + 18 October 2007: Wouter - addresses are logged with errors. - fixup testcode fake event to remove pending before callback @@ -10311,7 +10311,7 @@ - fix crash where failure to prime DNSKEY tried to print null pointer in the log message. - removed some debug prints, only verb_algo (4) enables them. - - fixup test; new random generator took new paths; such as one + - fixup test; new random generator took new paths; such as one where no scripted answer was available. - mark insecure RRs as insecure. - fixup removal of nonsecure items from the additional. @@ -10424,7 +10424,7 @@ proof is possible - the signature has been stripped off. 20 September 2007: Wouter - - fixup and test for NSEC wildcard with empty nonterminals. + - fixup and test for NSEC wildcard with empty nonterminals. - makedist.sh fixup for svn info. - acl features request in plan. - improved DS empty nonterminal handling. @@ -10463,7 +10463,7 @@ 12 September 2007: Wouter - fixup of manual page warnings, like for NSD bugreport. - - nsec3 work, config, max iterations, filter, and hash cache. + - nsec3 work, config, max iterations, filter, and hash cache. 6 September 2007: Wouter - fixup to find libevent on mac port install. @@ -10506,7 +10506,7 @@ CNAME'd messages. 3 September 2007: Wouter - - Fixed error in iterator that would cause assertion failure in + - Fixed error in iterator that would cause assertion failure in validator. CNAME to a NXDOMAIN response was collated into a response with both a CNAME and the NXDOMAIN rcode. Added a test that the rcode is changed to NOERROR (because of the CNAME). @@ -10518,7 +10518,7 @@ - tool too summarize allocations per code line. 31 August 2007: Wouter - - can read bind trusted-keys { ... }; files, in a compatibility mode. + - can read bind trusted-keys { ... }; files, in a compatibility mode. - iterator should not detach target queries that it still could need. the protection against multiple outstanding queries is moved to a current_query num check. @@ -10534,7 +10534,7 @@ - memory accounting fixup for outside network tcp callbacks. - memory accounting for iterator fixed storage. - key cache size and slabs config options. - - lib crypto cleanups at exit. + - lib crypto cleanups at exit. 29 August 2007: Wouter - test tool to sign rrsets for testing validator with. @@ -10563,7 +10563,7 @@ canonicalization routine will fail if it does not fit in buffer. - faster verification for large sigsets. - verb_detail mode reports validation failures, but not the entire - algorithm for validation. Key prime failures are reported as + algorithm for validation. Key prime failures are reported as verb_ops level. 27 August 2007: Wouter @@ -10595,7 +10595,7 @@ 23 August 2007: Wouter - CNAME handling - move needs_validation to before val_new(). val_new() setups the chase-reply to be an edited copy of the msg. - new classification, and find signer can find for it. + new classification, and find signer can find for it. removal of unsigned crap from additional, and query restart for cname. - refuse to follow wildcarded DNAMEs when validating. @@ -10731,7 +10731,7 @@ 30 July 2007: Wouter - changed random state init, so that sequential process IDs are not cancelled out by sequential thread-ids in the random number seed. - - the fwd_three test, which sends three queries to unbound, and + - the fwd_three test, which sends three queries to unbound, and unbound is kept waiting by ldns-testns for 3 seconds, failed because the retry timeout for default by unbound is 3 seconds too, it would hit that timeout and fail the test. Changed so that unbound @@ -10912,7 +10912,7 @@ 7 June 2007: Wouter - fixup error in double linked list insertion for subqueries and for outbound list of serviced queries for iterator module. - - nicer printout of outgoing port selection. + - nicer printout of outgoing port selection. - fixup cname target readout. - nicer debug output. - fixup rrset counts when prepending CNAMEs to the answer. @@ -10958,7 +10958,7 @@ - sanitize incoming messages. - split msgreply encode functions into own file msgencode.c. - msg_parse to queryinfo/replyinfo conversion more versatile. - - process_response, classify response, delegpt_from_message. + - process_response, classify response, delegpt_from_message. 31 May 2007: Wouter - querytargets state. @@ -11027,7 +11027,7 @@ and udp retries and rtt timing. 16 May 2007: Wouter - - lruhash_touch() would cause locking order problems. Fixup in + - lruhash_touch() would cause locking order problems. Fixup in lock-verify in case locking cycle is found. - services/cache/rrset.c for rrset cache code. - special rrset_cache LRU updating function that uses the rrset id. @@ -11065,7 +11065,7 @@ locks are disabled. 8 May 2007: Wouter - - outgoing network keeps list of available tcp buffers for outgoing + - outgoing network keeps list of available tcp buffers for outgoing tcp queries. - outgoing-num-tcp config option. - outgoing network keeps waiting list of queries waiting for buffer. @@ -11101,7 +11101,7 @@ 2 May 2007: Wouter - dname unit tests in own file and spread out neatly in functions. - more dname unit tests. - - message encoding creates truncated TC flagged messages if they do + - message encoding creates truncated TC flagged messages if they do not fit, and will leave out (whole)rrsets from additional if needed. 1 May 2007: Wouter @@ -11181,7 +11181,7 @@ 12 April 2007: Wouter - dname compare routine that preserves case, with unit tests. - + 11 April 2007: Wouter - parse work - dname packet parse, msgparse, querysection parse, start of sectionparse. @@ -11209,7 +11209,7 @@ in netevent (which is there to please lint) can be correct. The type on several OSes ranges from int, int32, uint32, size_t. Detects unsigned or signed using math trick. - - constants for DNS flags. + - constants for DNS flags. - compilation without locks fixup. - removed include of unportable header from lookup3.c. - more portable use of struct msghdr. @@ -11220,7 +11220,7 @@ 2 April 2007: Wouter - check sizes of udp received messages, not too short. - review changes. Some memmoves can be memcpys: 4byte aligned. - set id correctly on cached answers. + set id correctly on cached answers. - review changes msgreply.c, memleak on error condition. AA flag clear on cached reply. Lowercase queries on hashing. unit test on lowercasing. Test AA bit not set on cached reply. @@ -11264,7 +11264,7 @@ - AIX configure check. - lock-verify can handle references to locks that are created in files it has not yet read in. - - threaded hash table test. + - threaded hash table test. - unit test runs lock-verify afterwards and checks result. - need writelock to update data on hash_insert. - message cache code, msgreply code. @@ -11306,7 +11306,7 @@ 7 March 2007: Wouter - created a wrapper around thread calls that performs some basic - checking for data race and deadlock, and basic performance + checking for data race and deadlock, and basic performance contention measurement. 6 March 2007: Wouter @@ -11331,7 +11331,7 @@ - ub_thread_join portable definition. - forking is used if no threading is available. Tested, it works, since pipes work across processes as well. - Thread_join is replaced with waitpid. + Thread_join is replaced with waitpid. - During reloads the daemon will temporarily handle signals, so that they do not result in problems. - Also randomize the outgoing port range for tests. @@ -11377,7 +11377,7 @@ 19 February 2007: Wouter - Created 0.0 svn tag. - - added acx_pthread.m4 autoconf check for pthreads from + - added acx_pthread.m4 autoconf check for pthreads from the autoconf archive. It is GPL-with-autoconf-exception Licensed. You can specify --with-pthreads, or --without-pthreads to configure. diff --git a/usr.sbin/unbound/util/data/msgparse.h b/usr.sbin/unbound/util/data/msgparse.h index 5c98026cb..1f2f825b2 100644 --- a/usr.sbin/unbound/util/data/msgparse.h +++ b/usr.sbin/unbound/util/data/msgparse.h @@ -245,7 +245,7 @@ struct edns_data { unsigned int cookie_valid : 1; /** if the cookie holds only the client part */ unsigned int cookie_client : 1; -}; +}; /** * EDNS option diff --git a/usr.sbin/unbound/validator/validator.c b/usr.sbin/unbound/validator/validator.c index 8ff3f02ff..004846016 100644 --- a/usr.sbin/unbound/validator/validator.c +++ b/usr.sbin/unbound/validator/validator.c @@ -112,7 +112,7 @@ fill_nsec3_iter(struct val_env* ve, char* s, int c) s = e; if(i>0 && ve->nsec3_keysize[i-1] >= ve->nsec3_keysize[i]) { log_err("nsec3 key iterations not ascending: %d %d", - (int)ve->nsec3_keysize[i-1], + (int)ve->nsec3_keysize[i-1], (int)ve->nsec3_keysize[i]); return 0; }