SecBSD/src
2
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

zap whitespace and tab

Browse source
This commit is contained in:
purplerain 2023-09-26 19:52:17 +00:00
parent 5b49f88fed
commit 4de47ea988
Signed by: purplerain
GPG key ID: F42C07F07E2E35B7
681 changed files with 35748 additions and 35743 deletions
Download patch file Download diff file Expand all files Collapse all files

24
sys/dev/pci/drm/amd/amdgpu/ObjectID.h
View file

@ -1,5 +1,5 @@
/*
* Copyright 2006-2007 Advanced Micro Devices, Inc.
* Copyright 2006-2007 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -37,13 +37,13 @@
#define GRAPH_OBJECT_TYPE_CONNECTOR 0x3
#define GRAPH_OBJECT_TYPE_ROUTER 0x4
/* deleted */
#define GRAPH_OBJECT_TYPE_DISPLAY_PATH 0x6
#define GRAPH_OBJECT_TYPE_DISPLAY_PATH 0x6
#define GRAPH_OBJECT_TYPE_GENERIC 0x7
/****************************************************/
/* Encoder Object ID Definition */
/****************************************************/
#define ENCODER_OBJECT_ID_NONE 0x00
#define ENCODER_OBJECT_ID_NONE 0x00
/* Radeon Class Display Hardware */
#define ENCODER_OBJECT_ID_INTERNAL_LVDS 0x01
@ -96,7 +96,7 @@
/****************************************************/
/* Connector Object ID Definition */
/****************************************************/
#define CONNECTOR_OBJECT_ID_NONE 0x00
#define CONNECTOR_OBJECT_ID_NONE 0x00
#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I 0x01
#define CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I 0x02
#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D 0x03
@ -158,7 +158,7 @@
#define RESERVED1_ID_MASK 0x0800
#define OBJECT_TYPE_MASK 0x7000
#define RESERVED2_ID_MASK 0x8000
#define OBJECT_ID_SHIFT 0x00
#define ENUM_ID_SHIFT 0x08
#define OBJECT_TYPE_SHIFT 0x0C
@ -179,14 +179,14 @@
/* Encoder Object ID definition - Shared with BIOS */
/****************************************************/
/*
#define ENCODER_INTERNAL_LVDS_ENUM_ID1 0x2101
#define ENCODER_INTERNAL_LVDS_ENUM_ID1 0x2101
#define ENCODER_INTERNAL_TMDS1_ENUM_ID1 0x2102
#define ENCODER_INTERNAL_TMDS2_ENUM_ID1 0x2103
#define ENCODER_INTERNAL_DAC1_ENUM_ID1 0x2104
#define ENCODER_INTERNAL_DAC2_ENUM_ID1 0x2105
#define ENCODER_INTERNAL_SDVOA_ENUM_ID1 0x2106
#define ENCODER_INTERNAL_SDVOB_ENUM_ID1 0x2107
#define ENCODER_SIL170B_ENUM_ID1 0x2108
#define ENCODER_SIL170B_ENUM_ID1 0x2108
#define ENCODER_CH7303_ENUM_ID1 0x2109
#define ENCODER_CH7301_ENUM_ID1 0x210A
#define ENCODER_INTERNAL_DVO1_ENUM_ID1 0x210B
@ -200,8 +200,8 @@
#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1 0x2113
#define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1 0x2114
#define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1 0x2115
#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 0x2116
#define ENCODER_SI178_ENUM_ID1 0x2117
#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 0x2116
#define ENCODER_SI178_ENUM_ID1 0x2117
#define ENCODER_MVPU_FPGA_ENUM_ID1 0x2118
#define ENCODER_INTERNAL_DDI_ENUM_ID1 0x2119
#define ENCODER_VT1625_ENUM_ID1 0x211A
@ -316,7 +316,7 @@
#define ENCODER_SI178_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_SI178 << OBJECT_ID_SHIFT)
ENCODER_OBJECT_ID_SI178 << OBJECT_ID_SHIFT)
#define ENCODER_MVPU_FPGA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
@ -324,7 +324,7 @@
#define ENCODER_INTERNAL_DDI_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_INTERNAL_DDI << OBJECT_ID_SHIFT)
ENCODER_OBJECT_ID_INTERNAL_DDI << OBJECT_ID_SHIFT)
#define ENCODER_VT1625_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
@ -352,7 +352,7 @@
#define ENCODER_INTERNAL_KLDSCP_LVTMA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA << OBJECT_ID_SHIFT)
ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA << OBJECT_ID_SHIFT)
#define ENCODER_INTERNAL_UNIPHY1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\

2
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
View file

@ -6227,7 +6227,7 @@ int amdgpu_in_reset(struct amdgpu_device *adev)
{
return atomic_read(&adev->reset_domain->in_gpu_reset);
}
/**
* amdgpu_device_halt() - bring hardware to some kind of halt state
*

2
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
View file

@ -3438,7 +3438,7 @@ amdgpu_init_backlight(struct amdgpu_device *adev)
if (bd == NULL)
return;
drm_connector_list_iter_begin(dev, &conn_iter);
drm_for_each_connector_iter(connector, &conn_iter) {
if (connector->connector_type != DRM_MODE_CONNECTOR_LVDS &&

2
sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c
View file

@ -1098,7 +1098,7 @@ void amdgpu_bo_fini(struct amdgpu_device *adev)
arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
#else
drm_mtrr_del(0, adev->gmc.aper_base, adev->gmc.aper_size, DRM_MTRR_WC);
#endif
}
drm_dev_exit(idx);

2
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
View file

@ -101,7 +101,7 @@ amdgpu_vm_it_iter_next(struct amdgpu_bo_va_mapping *node, uint64_t start,
static void
amdgpu_vm_it_remove(struct amdgpu_bo_va_mapping *node,
struct rb_root_cached *root)
struct rb_root_cached *root)
{
rb_erase_cached(&node->rb, root);
}

4
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
View file

@ -1906,7 +1906,7 @@ static int gfx_v11_0_rlc_load_microcode(struct amdgpu_device *adev)
if (version_minor == 3)
gfx_v11_0_load_rlcp_rlcv_microcode(adev);
}
return 0;
}
@ -3348,7 +3348,7 @@ static int gfx_v11_0_cp_compute_load_microcode(struct amdgpu_device *adev)
}
memcpy(fw, fw_data, fw_size);
amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);

8
sys/dev/pci/drm/amd/amdgpu/imu_v11_0.c
View file

@ -58,7 +58,7 @@ static int imu_v11_0_init_microcode(struct amdgpu_device *adev)
imu_hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data;
adev->gfx.imu_fw_version = le32_to_cpu(imu_hdr->header.ucode_version);
//adev->gfx.imu_feature_version = le32_to_cpu(imu_hdr->ucode_feature_version);
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_IMU_I];
info->ucode_id = AMDGPU_UCODE_ID_IMU_I;
@ -240,9 +240,9 @@ static const struct imu_rlc_ram_golden imu_rlc_ram_golden_11[] =
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_BOT, 0x00000002, 0xe0000000),
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_TOP, 0x00000000, 0xe0000000),
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL2, 0x00020000, 0xe0000000),
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA0_UCODE_SELFLOAD_CONTROL, 0x00000210, 0),
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA1_UCODE_SELFLOAD_CONTROL, 0x00000210, 0),
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCPC_PSP_DEBUG, CPC_PSP_DEBUG__GPA_OVERRIDE_MASK, 0),
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA0_UCODE_SELFLOAD_CONTROL, 0x00000210, 0),
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA1_UCODE_SELFLOAD_CONTROL, 0x00000210, 0),
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCPC_PSP_DEBUG, CPC_PSP_DEBUG__GPA_OVERRIDE_MASK, 0),
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCPG_PSP_DEBUG, CPG_PSP_DEBUG__GPA_OVERRIDE_MASK, 0)
};

2
sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c
View file

@ -186,7 +186,7 @@ static int xgpu_ai_send_access_requests(struct amdgpu_device *adev,
/* Dummy REQ_GPU_INIT_DATA handling */
r = xgpu_ai_poll_msg(adev, IDH_REQ_GPU_INIT_DATA_READY);
/* version set to 0 since dummy */
adev->virt.req_init_data_ver = 0;
adev->virt.req_init_data_ver = 0;
}
return 0;

2
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
View file

@ -273,7 +273,7 @@ static int sdma_v5_0_init_microcode(struct amdgpu_device *adev)
if (ret)
return ret;
}
return ret;
}

2
sys/dev/pci/drm/amd/display/dc/dce/dce_aux.c
View file

@ -770,7 +770,7 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
aux_defer_retries,
AUX_MAX_RETRIES);
goto fail;
} else
} else
udelay(300);
} else if (payload->write && ret > 0) {
/* sink requested more time to complete the write via AUX_ACKM */

2
sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_resource.c
View file

@ -672,7 +672,7 @@ static const struct dc_plane_cap plane_cap = {
.max_downscale_factor = {
.argb8888 = 167,
.nv12 = 167,
.fp16 = 167
.fp16 = 167
},
64,
64

2
sys/dev/pci/drm/amd/display/modules/color/color_gamma.c
View file

@ -359,7 +359,7 @@ static struct fixed31_32 translate_from_linear_space(
scratch_1 = dc_fixpt_add(one, args->a3);
/* In the first region (first 16 points) and in the
* region delimited by START/END we calculate with
* full precision to avoid error accumulation.
* full precision to avoid error accumulation.
*/
if ((cal_buffer->buffer_index >= PRECISE_LUT_REGION_START &&
cal_buffer->buffer_index <= PRECISE_LUT_REGION_END) ||

2
sys/dev/pci/drm/amd/include/amd_shared.h
View file

@ -60,7 +60,7 @@ enum amd_apu_flags {
* acquires the list of IP blocks for the GPU in use on initialization.
* It can then operate on this list to perform standard driver operations
* such as: init, fini, suspend, resume, etc.
*
*
*
* IP block implementations are named using the following convention:
* <functionality>_v<version> (E.g.: gfx_v6_0).

2254
sys/dev/pci/drm/amd/include/asic_reg/nbif/nbif_6_1_offset.h
View file

File diff suppressed because it is too large Load diff

530
sys/dev/pci/drm/amd/include/atomfirmware.h
View file

File diff suppressed because it is too large Load diff

4
sys/dev/pci/drm/amd/include/atomfirmwareid.h
View file

@ -1,12 +1,12 @@
/****************************************************************************\
*
*
* File Name atomfirmwareid.h
*
* Description ATOM BIOS command/data table ID definition header file
*
* Copyright 2016 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
* and associated documentation files (the "Software"), to deal in the Software without restriction,
* including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so,

22
sys/dev/pci/drm/amd/include/displayobject.h
View file

@ -1,14 +1,14 @@
/****************************************************************************\
*
*
* Module Name displayobjectsoc15.h
* Project
* Device
* Project
* Device
*
* Description Contains the common definitions for display objects for SoC15 products.
*
* Copyright 2014 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
* and associated documentation files (the "Software"), to deal in the Software without restriction,
* including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so,
@ -35,7 +35,7 @@
/****************************************************
* Display Object Type Definition
* Display Object Type Definition
*****************************************************/
enum display_object_type{
DISPLAY_OBJECT_TYPE_NONE =0x00,
@ -45,7 +45,7 @@ DISPLAY_OBJECT_TYPE_CONNECTOR =0x03
};
/****************************************************
* Encorder Object Type Definition
* Encorder Object Type Definition
*****************************************************/
enum encoder_object_type{
ENCODER_OBJECT_ID_NONE =0x00,
@ -56,11 +56,11 @@ ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 =0x03,
/****************************************************
* Connector Object ID Definition
* Connector Object ID Definition
*****************************************************/
enum connector_object_type{
CONNECTOR_OBJECT_ID_NONE =0x00,
CONNECTOR_OBJECT_ID_NONE =0x00,
CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D =0x01,
CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D =0x02,
CONNECTOR_OBJECT_ID_HDMI_TYPE_A =0x03,
@ -72,12 +72,12 @@ CONNECTOR_OBJECT_ID_OPM =0x07
/****************************************************
* Protection Object ID Definition
* Protection Object ID Definition
*****************************************************/
//No need
/****************************************************
* Object ENUM ID Definition
* Object ENUM ID Definition
*****************************************************/
enum object_enum_id{
@ -90,7 +90,7 @@ OBJECT_ENUM_ID6 =0x06
};
/****************************************************
*Object ID Bit definition
*Object ID Bit definition
*****************************************************/
enum object_id_bit{
OBJECT_ID_MASK =0x00FF,

700
sys/dev/pci/drm/amd/include/ivsrcid/dcn/irqsrcs_dcn_1_0.h
View file

File diff suppressed because it is too large Load diff

48
sys/dev/pci/drm/amd/include/ivsrcid/ivsrcid_vislands30.h
View file

@ -27,40 +27,40 @@
// IV Source IDs
#define VISLANDS30_IV_SRCID_D1_V_UPDATE_INT 7 // 0x07
#define VISLANDS30_IV_SRCID_D1_V_UPDATE_INT 7 // 0x07
#define VISLANDS30_IV_EXTID_D1_V_UPDATE_INT 0
#define VISLANDS30_IV_SRCID_D1_GRPH_PFLIP 8 // 0x08
#define VISLANDS30_IV_SRCID_D1_GRPH_PFLIP 8 // 0x08
#define VISLANDS30_IV_EXTID_D1_GRPH_PFLIP 0
#define VISLANDS30_IV_SRCID_D2_V_UPDATE_INT 9 // 0x09
#define VISLANDS30_IV_SRCID_D2_V_UPDATE_INT 9 // 0x09
#define VISLANDS30_IV_EXTID_D2_V_UPDATE_INT 0
#define VISLANDS30_IV_SRCID_D2_GRPH_PFLIP 10 // 0x0a
#define VISLANDS30_IV_SRCID_D2_GRPH_PFLIP 10 // 0x0a
#define VISLANDS30_IV_EXTID_D2_GRPH_PFLIP 0
#define VISLANDS30_IV_SRCID_D3_V_UPDATE_INT 11 // 0x0b
#define VISLANDS30_IV_SRCID_D3_V_UPDATE_INT 11 // 0x0b
#define VISLANDS30_IV_EXTID_D3_V_UPDATE_INT 0
#define VISLANDS30_IV_SRCID_D3_GRPH_PFLIP 12 // 0x0c
#define VISLANDS30_IV_SRCID_D3_GRPH_PFLIP 12 // 0x0c
#define VISLANDS30_IV_EXTID_D3_GRPH_PFLIP 0
#define VISLANDS30_IV_SRCID_D4_V_UPDATE_INT 13 // 0x0d
#define VISLANDS30_IV_SRCID_D4_V_UPDATE_INT 13 // 0x0d
#define VISLANDS30_IV_EXTID_D4_V_UPDATE_INT 0
#define VISLANDS30_IV_SRCID_D4_GRPH_PFLIP 14 // 0x0e
#define VISLANDS30_IV_SRCID_D4_GRPH_PFLIP 14 // 0x0e
#define VISLANDS30_IV_EXTID_D4_GRPH_PFLIP 0
#define VISLANDS30_IV_SRCID_D5_V_UPDATE_INT 15 // 0x0f
#define VISLANDS30_IV_SRCID_D5_V_UPDATE_INT 15 // 0x0f
#define VISLANDS30_IV_EXTID_D5_V_UPDATE_INT 0
#define VISLANDS30_IV_SRCID_D5_GRPH_PFLIP 16 // 0x10
#define VISLANDS30_IV_SRCID_D5_GRPH_PFLIP 16 // 0x10
#define VISLANDS30_IV_EXTID_D5_GRPH_PFLIP 0
#define VISLANDS30_IV_SRCID_D6_V_UPDATE_INT 17 // 0x11
#define VISLANDS30_IV_SRCID_D6_V_UPDATE_INT 17 // 0x11
#define VISLANDS30_IV_EXTID_D6_V_UPDATE_INT 0
#define VISLANDS30_IV_SRCID_D6_GRPH_PFLIP 18 // 0x12
#define VISLANDS30_IV_SRCID_D6_GRPH_PFLIP 18 // 0x12
#define VISLANDS30_IV_EXTID_D6_GRPH_PFLIP 0
#define VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 19 // 0x13
@ -162,40 +162,40 @@
#define VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT2 24 // 0x18
#define VISLANDS30_IV_EXTID_D6_VERTICAL_INTERRUPT2 9
#define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A 42 // 0x2a
#define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A 42 // 0x2a
#define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_A 0
#define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_B 42 // 0x2a
#define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_B 42 // 0x2a
#define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_B 1
#define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_C 42 // 0x2a
#define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_C 42 // 0x2a
#define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_C 2
#define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_D 42 // 0x2a
#define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_D 42 // 0x2a
#define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_D 3
#define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_E 42 // 0x2a
#define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_E 42 // 0x2a
#define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_E 4
#define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_F 42 // 0x2a
#define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_F 42 // 0x2a
#define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_F 5
#define VISLANDS30_IV_SRCID_HPD_RX_A 42 // 0x2a
#define VISLANDS30_IV_SRCID_HPD_RX_A 42 // 0x2a
#define VISLANDS30_IV_EXTID_HPD_RX_A 6
#define VISLANDS30_IV_SRCID_HPD_RX_B 42 // 0x2a
#define VISLANDS30_IV_SRCID_HPD_RX_B 42 // 0x2a
#define VISLANDS30_IV_EXTID_HPD_RX_B 7
#define VISLANDS30_IV_SRCID_HPD_RX_C 42 // 0x2a
#define VISLANDS30_IV_SRCID_HPD_RX_C 42 // 0x2a
#define VISLANDS30_IV_EXTID_HPD_RX_C 8
#define VISLANDS30_IV_SRCID_HPD_RX_D 42 // 0x2a
#define VISLANDS30_IV_SRCID_HPD_RX_D 42 // 0x2a
#define VISLANDS30_IV_EXTID_HPD_RX_D 9
#define VISLANDS30_IV_SRCID_HPD_RX_E 42 // 0x2a
#define VISLANDS30_IV_SRCID_HPD_RX_E 42 // 0x2a
#define VISLANDS30_IV_EXTID_HPD_RX_E 10
#define VISLANDS30_IV_SRCID_HPD_RX_F 42 // 0x2a
#define VISLANDS30_IV_SRCID_HPD_RX_F 42 // 0x2a
#define VISLANDS30_IV_EXTID_HPD_RX_F 11
#define VISLANDS30_IV_SRCID_GPIO_19 0x00000053 /* 83 */

4
sys/dev/pci/drm/amd/include/ivsrcid/sdma1/irqsrcs_sdma1_5_0.h
View file

@ -22,8 +22,8 @@
#ifndef __IRQSRCS_SDMA1_5_0_H__
#define __IRQSRCS_SDMA1_5_0_H__
#define SDMA1_5_0__SRCID__SDMA_ATOMIC_RTN_DONE 217 // 0xD9 SDMA atomic*_rtn ops complete
#define SDMA1_5_0__SRCID__SDMA_ATOMIC_TIMEOUT 218 // 0xDA SDMA atomic CMPSWAP loop timeout
#define SDMA1_5_0__SRCID__SDMA_ATOMIC_RTN_DONE 217 // 0xD9 SDMA atomic*_rtn ops complete
#define SDMA1_5_0__SRCID__SDMA_ATOMIC_TIMEOUT 218 // 0xDA SDMA atomic CMPSWAP loop timeout
#define SDMA1_5_0__SRCID__SDMA_IB_PREEMPT 219 // 0xDB sdma mid-command buffer preempt interrupt
#define SDMA1_5_0__SRCID__SDMA_ECC 220 // 0xDC ECC Error
#define SDMA1_5_0__SRCID__SDMA_PAGE_FAULT 221 // 0xDD Page Fault Error from UTCL2 when nack=3

2
sys/dev/pci/drm/amd/include/navi10_ip_offset.h
View file

@ -28,7 +28,7 @@
struct IP_BASE_INSTANCE {
unsigned int segment[MAX_SEGMENT];
};
struct IP_BASE {
struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
} __maybe_unused;

44
sys/dev/pci/drm/amd/include/pptable.h
View file

@ -133,7 +133,7 @@ typedef struct _ATOM_PPLIB_EXTENDEDHEADER
USHORT usUVDTableOffset; //points to ATOM_PPLIB_UVD_Table
USHORT usSAMUTableOffset; //points to ATOM_PPLIB_SAMU_Table
USHORT usPPMTableOffset; //points to ATOM_PPLIB_PPM_Table
USHORT usACPTableOffset; //points to ATOM_PPLIB_ACP_Table
USHORT usACPTableOffset; //points to ATOM_PPLIB_ACP_Table
/* points to ATOM_PPLIB_POWERTUNE_Table */
USHORT usPowerTuneTableOffset;
/* points to ATOM_PPLIB_CLOCK_Voltage_Dependency_Table for sclkVddgfxTable */
@ -223,14 +223,14 @@ typedef struct _ATOM_PPLIB_POWERPLAYTABLE3
typedef struct _ATOM_PPLIB_POWERPLAYTABLE4
{
ATOM_PPLIB_POWERPLAYTABLE3 basicTable3;
ULONG ulGoldenPPID; // PPGen use only
ULONG ulGoldenPPID; // PPGen use only
ULONG ulGoldenRevision; // PPGen use only
USHORT usVddcDependencyOnSCLKOffset;
USHORT usVddciDependencyOnMCLKOffset;
USHORT usVddcDependencyOnMCLKOffset;
USHORT usMaxClockVoltageOnDCOffset;
USHORT usVddcPhaseShedLimitsTableOffset; // Points to ATOM_PPLIB_PhaseSheddingLimits_Table
USHORT usMvddDependencyOnMCLKOffset;
USHORT usMvddDependencyOnMCLKOffset;
} ATOM_PPLIB_POWERPLAYTABLE4, *LPATOM_PPLIB_POWERPLAYTABLE4;
typedef struct _ATOM_PPLIB_POWERPLAYTABLE5
@ -374,23 +374,23 @@ typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO
UCHAR ucPadding; // For proper alignment and size.
USHORT usVDDC; // For the 780, use: None, Low, High, Variable
UCHAR ucMaxHTLinkWidth; // From SBIOS - {2, 4, 8, 16}
UCHAR ucMinHTLinkWidth; // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled. Minimum down stream width could
UCHAR ucMinHTLinkWidth; // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled. Minimum down stream width could
USHORT usHTLinkFreq; // See definition ATOM_PPLIB_RS780_HTLINKFREQ_xxx or in MHz(>=200).
ULONG ulFlags;
ULONG ulFlags;
} ATOM_PPLIB_RS780_CLOCK_INFO;
#define ATOM_PPLIB_RS780_VOLTAGE_NONE 0
#define ATOM_PPLIB_RS780_VOLTAGE_LOW 1
#define ATOM_PPLIB_RS780_VOLTAGE_HIGH 2
#define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE 3
#define ATOM_PPLIB_RS780_VOLTAGE_NONE 0
#define ATOM_PPLIB_RS780_VOLTAGE_LOW 1
#define ATOM_PPLIB_RS780_VOLTAGE_HIGH 2
#define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE 3
#define ATOM_PPLIB_RS780_SPMCLK_NONE 0 // We cannot change the side port memory clock, leave it as it is.
#define ATOM_PPLIB_RS780_SPMCLK_LOW 1
#define ATOM_PPLIB_RS780_SPMCLK_HIGH 2
#define ATOM_PPLIB_RS780_HTLINKFREQ_NONE 0
#define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1
#define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2
#define ATOM_PPLIB_RS780_HTLINKFREQ_NONE 0
#define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1
#define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2
typedef struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO
{
@ -432,14 +432,14 @@ typedef struct _ATOM_PPLIB_CI_CLOCK_INFO
USHORT usMemoryClockLow;
UCHAR ucMemoryClockHigh;
UCHAR ucPCIEGen;
USHORT usPCIELane;
} ATOM_PPLIB_CI_CLOCK_INFO;
typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO{
USHORT usEngineClockLow; //clockfrequency & 0xFFFF. The unit is in 10khz
UCHAR ucEngineClockHigh; //clockfrequency >> 16.
UCHAR ucEngineClockHigh; //clockfrequency >> 16.
UCHAR vddcIndex; //2-bit vddc index;
USHORT tdpLimit;
//please initalize to 0
@ -464,10 +464,10 @@ typedef struct _ATOM_PPLIB_CZ_CLOCK_INFO {
typedef struct _ATOM_PPLIB_STATE_V2
{
//number of valid dpm levels in this state; Driver uses it to calculate the whole
//number of valid dpm levels in this state; Driver uses it to calculate the whole
//size of the state: sizeof(ATOM_PPLIB_STATE_V2) + (ucNumDPMLevels - 1) * sizeof(UCHAR)
UCHAR ucNumDPMLevels;
//a index to the array of nonClockInfos
UCHAR nonClockInfoIndex;
/**
@ -477,9 +477,9 @@ typedef struct _ATOM_PPLIB_STATE_V2
} ATOM_PPLIB_STATE_V2;
typedef struct _StateArray{
//how many states we have
//how many states we have
UCHAR ucNumEntries;
ATOM_PPLIB_STATE_V2 states[1];
}StateArray;
@ -487,10 +487,10 @@ typedef struct _StateArray{
typedef struct _ClockInfoArray{
//how many clock levels we have
UCHAR ucNumEntries;
//sizeof(ATOM_PPLIB_CLOCK_INFO)
UCHAR ucEntrySize;
UCHAR clockInfo[1];
}ClockInfoArray;
@ -500,7 +500,7 @@ typedef struct _NonClockInfoArray{
UCHAR ucNumEntries;
//sizeof(ATOM_PPLIB_NONCLOCK_INFO)
UCHAR ucEntrySize;
ATOM_PPLIB_NONCLOCK_INFO nonClockInfo[1];
}NonClockInfoArray;
@ -722,7 +722,7 @@ typedef struct _ATOM_PPLIB_PPM_Table
ULONG ulPlatformTDC;
ULONG ulSmallACPlatformTDC;
ULONG ulApuTDP;
ULONG ulDGpuTDP;
ULONG ulDGpuTDP;
ULONG ulDGpuUlvPower;
ULONG ulTjmax;
} ATOM_PPLIB_PPM_Table;

2
sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ppatomfwctrl.c
View file

@ -158,7 +158,7 @@ int pp_atomfwctrl_get_voltage_table_v4(struct pp_hwmgr *hwmgr,
return result;
}
static struct atom_gpio_pin_lut_v2_1 *pp_atomfwctrl_get_gpio_lookup_table(
struct pp_hwmgr *hwmgr)
{

8
sys/dev/pci/drm/amd/pm/powerplay/inc/smu11_driver_if.h
View file

@ -773,8 +773,8 @@ typedef struct {
uint8_t Gfx_IdleHystLimit;
uint8_t Gfx_FPS;
uint8_t Gfx_MinActiveFreqType;
uint8_t Gfx_BoosterFreqType;
uint8_t Gfx_UseRlcBusy;
uint8_t Gfx_BoosterFreqType;
uint8_t Gfx_UseRlcBusy;
uint16_t Gfx_MinActiveFreq;
uint16_t Gfx_BoosterFreq;
uint16_t Gfx_PD_Data_time_constant;
@ -788,7 +788,7 @@ typedef struct {
uint8_t Soc_IdleHystLimit;
uint8_t Soc_FPS;
uint8_t Soc_MinActiveFreqType;
uint8_t Soc_BoosterFreqType;
uint8_t Soc_BoosterFreqType;
uint8_t Soc_UseRlcBusy;
uint16_t Soc_MinActiveFreq;
uint16_t Soc_BoosterFreq;
@ -804,7 +804,7 @@ typedef struct {
uint8_t Mem_FPS;
uint8_t Mem_MinActiveFreqType;
uint8_t Mem_BoosterFreqType;
uint8_t Mem_UseRlcBusy;
uint8_t Mem_UseRlcBusy;
uint16_t Mem_MinActiveFreq;
uint16_t Mem_BoosterFreq;
uint16_t Mem_PD_Data_time_constant;

2
sys/dev/pci/drm/amd/pm/powerplay/inc/smu73_discrete.h
View file

@ -127,7 +127,7 @@ typedef struct SMU73_Discrete_MemoryLevel SMU73_Discrete_MemoryLevel;
struct SMU73_Discrete_LinkLevel
{
uint8_t PcieGenSpeed; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3
uint8_t PcieLaneCount; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16
uint8_t PcieLaneCount; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16
uint8_t EnabledForActivity;
uint8_t SPC;
uint32_t DownThreshold;

4
sys/dev/pci/drm/amd/pm/powerplay/inc/smu74_discrete.h
View file

@ -809,7 +809,7 @@ typedef struct SMU7_GfxCuPgScoreboard SMU7_GfxCuPgScoreboard;
#define DB_Enable_MASK 0x1000000
#define DB_IR_MASK 0x2000000
#define DB_PCC_MASK 0x4000000
#define DB_PCC_MASK 0x4000000
#define DB_EDC_MASK 0x8000000
#define SQ_Enable_SHIFT 0
@ -829,7 +829,7 @@ typedef struct SMU7_GfxCuPgScoreboard SMU7_GfxCuPgScoreboard;
#define DB_Enable_SHIFT 24
#define DB_IR_SHIFT 25
#define DB_PCC_SHIFT 26
#define DB_PCC_SHIFT 26
#define DB_EDC_SHIFT 27
#define BTCGB0_Vdroop_Enable_MASK 0x1

64
sys/dev/pci/drm/amd/pm/powerplay/inc/smu_ucode_xfer_cz.h
View file

@ -56,7 +56,7 @@
#define END_OF_TASK_LIST (uint16_t)0xffff
// Size of DRAM regions (in bytes) requested by SMU:
#define SMU_DRAM_REQ_MM_PWR_LOG 48
#define SMU_DRAM_REQ_MM_PWR_LOG 48
#define UCODE_ID_SDMA0 0
#define UCODE_ID_SDMA1 1
@ -73,35 +73,35 @@
#define UCODE_ID_DMCU_ERAM 12
#define UCODE_ID_DMCU_IRAM 13
#define UCODE_ID_SDMA0_MASK 0x00000001
#define UCODE_ID_SDMA1_MASK 0x00000002
#define UCODE_ID_CP_CE_MASK 0x00000004
#define UCODE_ID_CP_PFP_MASK 0x00000008
#define UCODE_ID_CP_ME_MASK 0x00000010
#define UCODE_ID_CP_MEC_JT1_MASK 0x00000020
#define UCODE_ID_CP_MEC_JT2_MASK 0x00000040
#define UCODE_ID_GMCON_RENG_MASK 0x00000080
#define UCODE_ID_RLC_G_MASK 0x00000100
#define UCODE_ID_RLC_SCRATCH_MASK 0x00000200
#define UCODE_ID_RLC_SRM_ARAM_MASK 0x00000400
#define UCODE_ID_RLC_SRM_DRAM_MASK 0x00000800
#define UCODE_ID_DMCU_ERAM_MASK 0x00001000
#define UCODE_ID_DMCU_IRAM_MASK 0x00002000
#define UCODE_ID_SDMA0_MASK 0x00000001
#define UCODE_ID_SDMA1_MASK 0x00000002
#define UCODE_ID_CP_CE_MASK 0x00000004
#define UCODE_ID_CP_PFP_MASK 0x00000008
#define UCODE_ID_CP_ME_MASK 0x00000010
#define UCODE_ID_CP_MEC_JT1_MASK 0x00000020
#define UCODE_ID_CP_MEC_JT2_MASK 0x00000040
#define UCODE_ID_GMCON_RENG_MASK 0x00000080
#define UCODE_ID_RLC_G_MASK 0x00000100
#define UCODE_ID_RLC_SCRATCH_MASK 0x00000200
#define UCODE_ID_RLC_SRM_ARAM_MASK 0x00000400
#define UCODE_ID_RLC_SRM_DRAM_MASK 0x00000800
#define UCODE_ID_DMCU_ERAM_MASK 0x00001000
#define UCODE_ID_DMCU_IRAM_MASK 0x00002000
#define UCODE_ID_SDMA0_SIZE_BYTE 10368
#define UCODE_ID_SDMA1_SIZE_BYTE 10368
#define UCODE_ID_CP_CE_SIZE_BYTE 8576
#define UCODE_ID_CP_PFP_SIZE_BYTE 16768
#define UCODE_ID_CP_ME_SIZE_BYTE 16768
#define UCODE_ID_CP_MEC_JT1_SIZE_BYTE 384
#define UCODE_ID_CP_MEC_JT2_SIZE_BYTE 384
#define UCODE_ID_GMCON_RENG_SIZE_BYTE 4096
#define UCODE_ID_RLC_G_SIZE_BYTE 2048
#define UCODE_ID_RLC_SCRATCH_SIZE_BYTE 132
#define UCODE_ID_RLC_SRM_ARAM_SIZE_BYTE 8192
#define UCODE_ID_RLC_SRM_DRAM_SIZE_BYTE 4096
#define UCODE_ID_DMCU_ERAM_SIZE_BYTE 24576
#define UCODE_ID_DMCU_IRAM_SIZE_BYTE 1024
#define UCODE_ID_SDMA0_SIZE_BYTE 10368
#define UCODE_ID_SDMA1_SIZE_BYTE 10368
#define UCODE_ID_CP_CE_SIZE_BYTE 8576
#define UCODE_ID_CP_PFP_SIZE_BYTE 16768
#define UCODE_ID_CP_ME_SIZE_BYTE 16768
#define UCODE_ID_CP_MEC_JT1_SIZE_BYTE 384
#define UCODE_ID_CP_MEC_JT2_SIZE_BYTE 384
#define UCODE_ID_GMCON_RENG_SIZE_BYTE 4096
#define UCODE_ID_RLC_G_SIZE_BYTE 2048
#define UCODE_ID_RLC_SCRATCH_SIZE_BYTE 132
#define UCODE_ID_RLC_SRM_ARAM_SIZE_BYTE 8192
#define UCODE_ID_RLC_SRM_DRAM_SIZE_BYTE 4096
#define UCODE_ID_DMCU_ERAM_SIZE_BYTE 24576
#define UCODE_ID_DMCU_IRAM_SIZE_BYTE 1024
#define NUM_UCODES 14
@ -125,9 +125,9 @@ struct TOC {
};
// META DATA COMMAND Definitions
#define METADATA_CMD_MODE0 0x00000103
#define METADATA_CMD_MODE1 0x00000113
#define METADATA_CMD_MODE2 0x00000123
#define METADATA_CMD_MODE0 0x00000103
#define METADATA_CMD_MODE1 0x00000113
#define METADATA_CMD_MODE2 0x00000123
#define METADATA_CMD_MODE3 0x00000133
#define METADATA_CMD_DELAY 0x00000203
#define METADATA_CMD_CHNG_REGSPACE 0x00000303

10
sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h
View file

@ -365,7 +365,7 @@ typedef struct {
uint16_t FanMaximumRpm;
uint16_t FanTargetTemperature;
uint16_t FanTargetGfxclk;
uint8_t FanZeroRpmEnable;
uint8_t FanZeroRpmEnable;
uint8_t FanTachEdgePerRev;
@ -659,8 +659,8 @@ typedef struct {
uint8_t Gfx_IdleHystLimit;
uint8_t Gfx_FPS;
uint8_t Gfx_MinActiveFreqType;
uint8_t Gfx_BoosterFreqType;
uint8_t Gfx_UseRlcBusy;
uint8_t Gfx_BoosterFreqType;
uint8_t Gfx_UseRlcBusy;
uint16_t Gfx_MinActiveFreq;
uint16_t Gfx_BoosterFreq;
uint16_t Gfx_PD_Data_time_constant;
@ -674,7 +674,7 @@ typedef struct {
uint8_t Soc_IdleHystLimit;
uint8_t Soc_FPS;
uint8_t Soc_MinActiveFreqType;
uint8_t Soc_BoosterFreqType;
uint8_t Soc_BoosterFreqType;
uint8_t Soc_UseRlcBusy;
uint16_t Soc_MinActiveFreq;
uint16_t Soc_BoosterFreq;
@ -690,7 +690,7 @@ typedef struct {
uint8_t Mem_FPS;
uint8_t Mem_MinActiveFreqType;
uint8_t Mem_BoosterFreqType;
uint8_t Mem_UseRlcBusy;
uint8_t Mem_UseRlcBusy;
uint16_t Mem_MinActiveFreq;
uint16_t Mem_BoosterFreq;
uint16_t Mem_PD_Data_time_constant;

4
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
View file

@ -1315,8 +1315,8 @@ struct pptable_funcs {
* @get_ecc_table: message SMU to get ECC INFO table.
*/
ssize_t (*get_ecc_info)(struct smu_context *smu, void *table);
/**
* @stb_collect_info: Collects Smart Trace Buffers data.
*/

234
sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h
View file

@ -24,7 +24,7 @@
#define __SMU11_DRIVER_IF_NAVI10_H__
// *** IMPORTANT ***
// SMU TEAM: Always increment the interface version if
// SMU TEAM: Always increment the interface version if
// any structure is changed in this file
// Be aware of that the version should be updated in
// smu_v11_0.h, maybe rename is also needed.
@ -42,7 +42,7 @@
#define NUM_PHYCLK_DPM_LEVELS 8
#define NUM_DISPCLK_DPM_LEVELS 8
#define NUM_PIXCLK_DPM_LEVELS 8
#define NUM_UCLK_DPM_LEVELS 4
#define NUM_UCLK_DPM_LEVELS 4
#define NUM_MP1CLK_DPM_LEVELS 2
#define NUM_LINK_LEVELS 2
@ -76,24 +76,24 @@
#define FEATURE_DPM_MP0CLK_BIT 5
#define FEATURE_DPM_LINK_BIT 6
#define FEATURE_DPM_DCEFCLK_BIT 7
#define FEATURE_MEM_VDDCI_SCALING_BIT 8
#define FEATURE_MEM_VDDCI_SCALING_BIT 8
#define FEATURE_MEM_MVDD_SCALING_BIT 9
//Idle
//Idle
#define FEATURE_DS_GFXCLK_BIT 10
#define FEATURE_DS_SOCCLK_BIT 11
#define FEATURE_DS_LCLK_BIT 12
#define FEATURE_DS_DCEFCLK_BIT 13
#define FEATURE_DS_UCLK_BIT 14
#define FEATURE_GFX_ULV_BIT 15
#define FEATURE_FW_DSTATE_BIT 16
#define FEATURE_GFX_ULV_BIT 15
#define FEATURE_FW_DSTATE_BIT 16
#define FEATURE_GFXOFF_BIT 17
#define FEATURE_BACO_BIT 18
#define FEATURE_VCN_PG_BIT 19
#define FEATURE_VCN_PG_BIT 19
#define FEATURE_JPEG_PG_BIT 20
#define FEATURE_USB_PG_BIT 21
#define FEATURE_RSMU_SMN_CG_BIT 22
//Throttler/Response
//Throttler/Response
#define FEATURE_PPT_BIT 23
#define FEATURE_TDC_BIT 24
#define FEATURE_GFX_EDC_BIT 25
@ -101,15 +101,15 @@
#define FEATURE_GTHR_BIT 27
#define FEATURE_ACDC_BIT 28
#define FEATURE_VR0HOT_BIT 29
#define FEATURE_VR1HOT_BIT 30
#define FEATURE_VR1HOT_BIT 30
#define FEATURE_FW_CTF_BIT 31
#define FEATURE_FAN_CONTROL_BIT 32
#define FEATURE_THERMAL_BIT 33
#define FEATURE_GFX_DCS_BIT 34
//VF
//VF
#define FEATURE_RM_BIT 35
#define FEATURE_LED_DISPLAY_BIT 36
//Other
//Other
#define FEATURE_GFX_SS_BIT 37
#define FEATURE_OUT_OF_BAND_MONITOR_BIT 38
#define FEATURE_TEMP_DEPENDENT_VMIN_BIT 39
@ -202,13 +202,13 @@
#define FW_DSTATE_MP1_DS_BIT 5
#define FW_DSTATE_MP1_WHISPER_MODE_BIT 6
#define FW_DSTATE_LIV_MIN_BIT 7
#define FW_DSTATE_SOC_PLL_PWRDN_BIT 8
#define FW_DSTATE_SOC_PLL_PWRDN_BIT 8
#define FW_DSTATE_SOC_ULV_MASK (1 << FW_DSTATE_SOC_ULV_BIT )
#define FW_DSTATE_G6_HSR_MASK (1 << FW_DSTATE_G6_HSR_BIT )
#define FW_DSTATE_G6_PHY_VDDCI_OFF_MASK (1 << FW_DSTATE_G6_PHY_VDDCI_OFF_BIT )
#define FW_DSTATE_MP1_DS_MASK (1 << FW_DSTATE_MP1_DS_BIT )
#define FW_DSTATE_MP0_DS_MASK (1 << FW_DSTATE_MP0_DS_BIT )
#define FW_DSTATE_MP1_DS_MASK (1 << FW_DSTATE_MP1_DS_BIT )
#define FW_DSTATE_MP0_DS_MASK (1 << FW_DSTATE_MP0_DS_BIT )
#define FW_DSTATE_SMN_DS_MASK (1 << FW_DSTATE_SMN_DS_BIT )
#define FW_DSTATE_MP1_WHISPER_MODE_MASK (1 << FW_DSTATE_MP1_WHISPER_MODE_BIT )
#define FW_DSTATE_LIV_MIN_MASK (1 << FW_DSTATE_LIV_MIN_BIT )
@ -235,10 +235,10 @@ typedef enum {
I2C_CONTROLLER_NAME_VR_VDDCI,
I2C_CONTROLLER_NAME_VR_MVDD,
I2C_CONTROLLER_NAME_LIQUID0,
I2C_CONTROLLER_NAME_LIQUID1,
I2C_CONTROLLER_NAME_LIQUID1,
I2C_CONTROLLER_NAME_PLX,
I2C_CONTROLLER_NAME_SPARE,
I2C_CONTROLLER_NAME_COUNT,
I2C_CONTROLLER_NAME_COUNT,
} I2cControllerName_e;
typedef enum {
@ -248,9 +248,9 @@ typedef enum {
I2C_CONTROLLER_THROTTLER_VR_VDDCI,
I2C_CONTROLLER_THROTTLER_VR_MVDD,
I2C_CONTROLLER_THROTTLER_LIQUID0,
I2C_CONTROLLER_THROTTLER_LIQUID1,
I2C_CONTROLLER_THROTTLER_LIQUID1,
I2C_CONTROLLER_THROTTLER_PLX,
I2C_CONTROLLER_THROTTLER_COUNT,
I2C_CONTROLLER_THROTTLER_COUNT,
} I2cControllerThrottler_e;
typedef enum {
@ -260,7 +260,7 @@ typedef enum {
I2C_CONTROLLER_PROTOCOL_TMP_1,
I2C_CONTROLLER_PROTOCOL_SPARE_0,
I2C_CONTROLLER_PROTOCOL_SPARE_1,
I2C_CONTROLLER_PROTOCOL_COUNT,
I2C_CONTROLLER_PROTOCOL_COUNT,
} I2cControllerProtocol_e;
typedef struct {
@ -275,9 +275,9 @@ typedef struct {
} I2cControllerConfig_t;
typedef enum {
I2C_PORT_SVD_SCL = 0,
I2C_PORT_GPIO,
} I2cPort_e;
I2C_PORT_SVD_SCL = 0,
I2C_PORT_GPIO,
} I2cPort_e;
typedef enum {
I2C_SPEED_FAST_50K = 0, //50 Kbits/s
@ -285,14 +285,14 @@ typedef enum {
I2C_SPEED_FAST_400K, //400 Kbits/s
I2C_SPEED_FAST_PLUS_1M, //1 Mbits/s (in fast mode)
I2C_SPEED_HIGH_1M, //1 Mbits/s (in high speed mode)
I2C_SPEED_HIGH_2M, //2.3 Mbits/s
I2C_SPEED_COUNT,
I2C_SPEED_HIGH_2M, //2.3 Mbits/s
I2C_SPEED_COUNT,
} I2cSpeed_e;
typedef enum {
I2C_CMD_READ = 0,
I2C_CMD_WRITE,
I2C_CMD_COUNT,
I2C_CMD_COUNT,
} I2cCmdType_e;
#define CMDCONFIG_STOP_BIT 0
@ -303,7 +303,7 @@ typedef enum {
typedef struct {
uint8_t RegisterAddr; ////only valid for write, ignored for read
uint8_t Cmd; //Read(0) or Write(1)
uint8_t Cmd; //Read(0) or Write(1)
uint8_t Data; //Return data for read. Data to send for write
uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command
} SwI2cCmd_t; //SW I2C Command Table
@ -318,7 +318,7 @@ typedef struct {
SwI2cCmd_t SwI2cCmds[MAX_SW_I2C_COMMANDS];
uint32_t MmHubPadding[8]; // SMU internal use
} SwI2cRequest_t; // SW I2C Request Table
//D3HOT sequences
@ -342,30 +342,30 @@ typedef enum {
PG_POWER_UP,
} PowerGatingSettings_e;
typedef struct {
typedef struct {
uint32_t a; // store in IEEE float format in this variable
uint32_t b; // store in IEEE float format in this variable
uint32_t c; // store in IEEE float format in this variable
} QuadraticInt_t;
typedef struct {
typedef struct {
uint32_t m; // store in IEEE float format in this variable
uint32_t b; // store in IEEE float format in this variable
} LinearInt_t;
typedef struct {
typedef struct {
uint32_t a; // store in IEEE float format in this variable
uint32_t b; // store in IEEE float format in this variable
uint32_t c; // store in IEEE float format in this variable
} DroopInt_t;
typedef enum {
GFXCLK_SOURCE_PLL = 0,
GFXCLK_SOURCE_DFLL,
GFXCLK_SOURCE_COUNT,
} GfxclkSrc_e;
GFXCLK_SOURCE_PLL = 0,
GFXCLK_SOURCE_DFLL,
GFXCLK_SOURCE_COUNT,
} GfxclkSrc_e;
//Only Clks that have DPM descriptors are listed here
//Only Clks that have DPM descriptors are listed here
typedef enum {
PPCLK_GFXCLK = 0,
PPCLK_SOCCLK,
@ -389,7 +389,7 @@ typedef enum {
PPT_THROTTLER_PPT0,
PPT_THROTTLER_PPT1,
PPT_THROTTLER_PPT2,
PPT_THROTTLER_PPT3,
PPT_THROTTLER_PPT3,
PPT_THROTTLER_COUNT
} PPT_THROTTLER_e;
@ -435,7 +435,7 @@ typedef struct {
uint8_t VoltageMode; // 0 - AVFS only, 1- min(AVFS,SS), 2-SS only
uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM
uint8_t NumDiscreteLevels; // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used
uint8_t Padding;
uint8_t Padding;
LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz)
QuadraticInt_t SsCurve; // Slow-slow curve (GHz->V)
} DpmDescriptor_t;
@ -447,9 +447,9 @@ typedef enum {
TEMP_VR_GFX,
TEMP_VR_MEM0,
TEMP_VR_MEM1,
TEMP_VR_SOC,
TEMP_VR_SOC,
TEMP_LIQUID0,
TEMP_LIQUID1,
TEMP_LIQUID1,
TEMP_PLX,
TEMP_COUNT
} TEMP_e;
@ -468,14 +468,14 @@ typedef enum {
#define HBM_TEMPERATURE_EXCEEDING_TEMPERATURE_LIMIT_BIT 13
#define HBM_TEMPERATURE_EXCEEDING_MAX_MEMORY_TEMPERATURE_BIT 14
#define POWER_MANAGER_CONTROLLER_MASK (1 << POWER_MANAGER_CONTROLLER_BIT )
#define POWER_MANAGER_CONTROLLER_MASK (1 << POWER_MANAGER_CONTROLLER_BIT )
#define MAXIMUM_DPM_STATE_GFX_ENGINE_RESTRICTED_MASK (1 << MAXIMUM_DPM_STATE_GFX_ENGINE_RESTRICTED_BIT )
#define GPU_DIE_TEMPERATURE_THROTTLING_MASK (1 << GPU_DIE_TEMPERATURE_THROTTLING_BIT )
#define GPU_DIE_TEMPERATURE_THROTTLING_MASK (1 << GPU_DIE_TEMPERATURE_THROTTLING_BIT )
#define HBM_DIE_TEMPERATURE_THROTTLING_MASK (1 << HBM_DIE_TEMPERATURE_THROTTLING_BIT )
#define TGP_THROTTLING_MASK (1 << TGP_THROTTLING_BIT )
#define PCC_THROTTLING_MASK (1 << PCC_THROTTLING_BIT )
#define HBM_TEMPERATURE_EXCEEDING_TEMPERATURE_LIMIT_MASK (1 << HBM_TEMPERATURE_EXCEEDING_TEMPERATURE_LIMIT_BIT )
#define HBM_TEMPERATURE_EXCEEDING_MAX_MEMORY_TEMPERATURE_MASK (1 << HBM_TEMPERATURE_EXCEEDING_MAX_MEMORY_TEMPERATURE_BIT)
#define HBM_TEMPERATURE_EXCEEDING_MAX_MEMORY_TEMPERATURE_MASK (1 << HBM_TEMPERATURE_EXCEEDING_MAX_MEMORY_TEMPERATURE_BIT)
//This structure to be DMA to SMBUS Config register space
typedef struct {
@ -500,7 +500,7 @@ typedef struct {
uint32_t DieTemperatureRegisterOffset;
uint32_t Reserved2;
uint32_t Reserved3;
uint32_t Status;
@ -512,7 +512,7 @@ typedef struct {
uint8_t MemoryHotspotPosition;
uint8_t Reserved4;
uint32_t BoardLevelEnergyAccumulator;
uint32_t BoardLevelEnergyAccumulator;
} OutOfBandMonitor_t;
#pragma pack(push, 1)
@ -526,19 +526,19 @@ typedef struct {
uint16_t SocketPowerLimitAc[PPT_THROTTLER_COUNT];
uint16_t SocketPowerLimitAcTau[PPT_THROTTLER_COUNT];
uint16_t SocketPowerLimitDc[PPT_THROTTLER_COUNT];
uint16_t SocketPowerLimitDcTau[PPT_THROTTLER_COUNT];
uint16_t SocketPowerLimitDcTau[PPT_THROTTLER_COUNT];
uint16_t TdcLimitSoc; // Amps
uint16_t TdcLimitSocTau; // Time constant of LPF in ms
uint16_t TdcLimitGfx; // Amps
uint16_t TdcLimitGfxTau; // Time constant of LPF in ms
uint16_t TedgeLimit; // Celcius
uint16_t ThotspotLimit; // Celcius
uint16_t TmemLimit; // Celcius
uint16_t Tvr_gfxLimit; // Celcius
uint16_t Tvr_mem0Limit; // Celcius
uint16_t Tvr_mem1Limit; // Celcius
uint16_t Tvr_mem1Limit; // Celcius
uint16_t Tvr_socLimit; // Celcius
uint16_t Tliquid0Limit; // Celcius
uint16_t Tliquid1Limit; // Celcius
@ -547,11 +547,11 @@ typedef struct {
uint16_t PpmPowerLimit; // Switch this this power limit when temperature is above PpmTempThreshold
uint16_t PpmTemperatureThreshold;
// SECTION: Throttler settings
uint32_t ThrottlerControlMask; // See Throtter masks defines
// SECTION: FW DSTATE Settings
// SECTION: FW DSTATE Settings
uint32_t FwDStateMask; // See FW DState masks defines
// SECTION: ULV Settings
@ -560,13 +560,13 @@ typedef struct {
uint8_t GceaLinkMgrIdleThreshold; //Set by SMU FW during enablment of SOC_ULV. Controls delay for GFX SDP port disconnection during idle events
uint8_t paddingRlcUlvParams[3];
uint8_t UlvSmnclkDid; //DID for ULV mode. 0 means CLK will not be modified in ULV.
uint8_t UlvMp1clkDid; //DID for ULV mode. 0 means CLK will not be modified in ULV.
uint8_t UlvGfxclkBypass; // 1 to turn off/bypass Gfxclk during ULV, 0 to leave Gfxclk on during ULV
uint8_t Padding234;
uint16_t MinVoltageUlvGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX in ULV mode
uint16_t MinVoltageUlvGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX in ULV mode
uint16_t MinVoltageUlvSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC in ULV mode
@ -595,7 +595,7 @@ typedef struct {
uint16_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz
uint16_t Padding8_Clks;
uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:Div-1/8
// SECTION: DPM Config 2
@ -605,11 +605,11 @@ typedef struct {
uint16_t MemMvddVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2)
// GFXCLK DPM
uint16_t GfxclkFgfxoffEntry; // in Mhz
uint16_t GfxclkFinit; // in Mhz
uint16_t GfxclkFinit; // in Mhz
uint16_t GfxclkFidle; // in MHz
uint16_t GfxclkSlewRate; // for PLL babystepping???
uint16_t GfxclkFopt; // in Mhz
uint8_t Padding567[2];
uint8_t Padding567[2];
uint16_t GfxclkDsMaxFreq; // in MHz
uint8_t GfxclkSource; // 0 = PLL, 1 = DFLL
uint8_t Padding456;
@ -617,7 +617,7 @@ typedef struct {
// UCLK section
uint8_t LowestUclkReservedForUlv; // Set this to 1 if UCLK DPM0 is reserved for ULV-mode only
uint8_t paddingUclk[3];
uint8_t MemoryType; // 0-GDDR6, 1-HBM
uint8_t MemoryChannels;
uint8_t PaddingMem[2];
@ -625,14 +625,14 @@ typedef struct {
// Link DPM Settings
uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4
uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16
uint16_t LclkFreq[NUM_LINK_LEVELS];
uint16_t LclkFreq[NUM_LINK_LEVELS];
// GFXCLK Thermal DPM (formerly 'Boost' Settings)
uint16_t EnableTdpm;
uint16_t EnableTdpm;
uint16_t TdpmHighHystTemperature;
uint16_t TdpmLowHystTemperature;
uint16_t GfxclkFreqHighTempLimit; // High limit on GFXCLK when temperature is high, for reliability.
// SECTION: Fan Control
uint16_t FanStopTemp; //Celcius
uint16_t FanStartTemp; //Celcius
@ -640,11 +640,11 @@ typedef struct {
uint16_t FanGainEdge;
uint16_t FanGainHotspot;
uint16_t FanGainLiquid0;
uint16_t FanGainLiquid1;
uint16_t FanGainLiquid1;
uint16_t FanGainVrGfx;
uint16_t FanGainVrSoc;
uint16_t FanGainVrMem0;
uint16_t FanGainVrMem1;
uint16_t FanGainVrMem1;
uint16_t FanGainPlx;
uint16_t FanGainMem;
uint16_t FanPwmMin;
@ -655,10 +655,10 @@ typedef struct {
uint16_t FanTargetGfxclk;
uint8_t FanTempInputSelect;
uint8_t FanPadding;
uint8_t FanZeroRpmEnable;
uint8_t FanZeroRpmEnable;
uint8_t FanTachEdgePerRev;
//uint8_t padding8_Fan[2];
// The following are AFC override parameters. Leave at 0 to use FW defaults.
int16_t FuzzyFan_ErrorSetDelta;
int16_t FuzzyFan_ErrorRateSetDelta;
@ -666,18 +666,18 @@ typedef struct {
uint16_t FuzzyFan_Reserved;
// SECTION: AVFS
// SECTION: AVFS
// Overrides
uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT];
uint8_t Padding8_Avfs[2];
QuadraticInt_t qAvfsGb[AVFS_VOLTAGE_COUNT]; // GHz->V Override of fused curve
QuadraticInt_t qAvfsGb[AVFS_VOLTAGE_COUNT]; // GHz->V Override of fused curve
DroopInt_t dBtcGbGfxPll; // GHz->V BtcGb
DroopInt_t dBtcGbGfxDfll; // GHz->V BtcGb
DroopInt_t dBtcGbSoc; // GHz->V BtcGb
LinearInt_t qAgingGb[AVFS_VOLTAGE_COUNT]; // GHz->V
LinearInt_t qAgingGb[AVFS_VOLTAGE_COUNT]; // GHz->V
QuadraticInt_t qStaticVoltageOffset[AVFS_VOLTAGE_COUNT]; // GHz->V
QuadraticInt_t qStaticVoltageOffset[AVFS_VOLTAGE_COUNT]; // GHz->V
uint16_t DcTol[AVFS_VOLTAGE_COUNT]; // mV Q2
@ -689,14 +689,14 @@ typedef struct {
// SECTION: Advanced Options
uint32_t DebugOverrides;
QuadraticInt_t ReservedEquation0;
QuadraticInt_t ReservedEquation1;
QuadraticInt_t ReservedEquation2;
QuadraticInt_t ReservedEquation3;
QuadraticInt_t ReservedEquation0;
QuadraticInt_t ReservedEquation1;
QuadraticInt_t ReservedEquation2;
QuadraticInt_t ReservedEquation3;
// Total Power configuration, use defines from PwrConfig_e
uint8_t TotalPowerConfig; //0-TDP, 1-TGP, 2-TCP Estimated, 3-TCP Measured
uint8_t TotalPowerSpare1;
uint8_t TotalPowerSpare1;
uint16_t TotalPowerSpare2;
// APCC Settings
@ -712,13 +712,13 @@ typedef struct {
uint16_t VDDGFX_Vmin_LoTemp; // mV Q2
uint16_t VDDSOC_Vmin_HiTemp; // mV Q2
uint16_t VDDSOC_Vmin_LoTemp; // mV Q2
uint16_t VDDGFX_TVminHystersis; // Celcius
uint16_t VDDSOC_TVminHystersis; // Celcius
// BTC Setting
uint32_t BtcConfig;
uint16_t SsFmin[10]; // PPtable value to function similar to VFTFmin for SS Curve; Size is PPCLK_COUNT rounded to nearest multiple of 2
uint16_t DcBtcGb[AVFS_VOLTAGE_COUNT];
@ -727,12 +727,12 @@ typedef struct {
// SECTION: BOARD PARAMETERS
// I2C Control
I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS];
I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS];
// SVI2 Board Parameters
uint16_t MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value.
uint16_t MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value.
uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields
uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields
uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields
@ -741,7 +741,7 @@ typedef struct {
uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN)
uint8_t Padding8_V;
uint8_t Padding8_V;
// Telemetry Settings
uint16_t GfxMaxCurrent; // in Amps
@ -755,19 +755,19 @@ typedef struct {
uint16_t Mem0MaxCurrent; // in Amps
int8_t Mem0Offset; // in Amps
uint8_t Padding_TelemetryMem0;
uint16_t Mem1MaxCurrent; // in Amps
int8_t Mem1Offset; // in Amps
uint8_t Padding_TelemetryMem1;
// GPIO Settings
uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching
uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching
uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event
uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event
uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event
uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event
uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event
uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event
uint8_t GthrGpio; // GPIO pin configured for GTHR Event
uint8_t GthrPolarity; // replace GPIO polarity for GTHR
@ -776,7 +776,7 @@ typedef struct {
uint8_t LedPin1; // GPIO number for LedPin[1]
uint8_t LedPin2; // GPIO number for LedPin[2]
uint8_t padding8_4;
// GFXCLK PLL Spread Spectrum
uint8_t PllGfxclkSpreadEnabled; // on or off
uint8_t PllGfxclkSpreadPercent; // Q4.4
@ -786,7 +786,7 @@ typedef struct {
uint8_t DfllGfxclkSpreadEnabled; // on or off
uint8_t DfllGfxclkSpreadPercent; // Q4.4
uint16_t DfllGfxclkSpreadFreq; // kHz
// UCLK Spread Spectrum
uint8_t UclkSpreadEnabled; // on or off
uint8_t UclkSpreadPercent; // Q4.4
@ -799,7 +799,7 @@ typedef struct {
// Total board power
uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power
uint16_t BoardPadding;
uint16_t BoardPadding;
// Mvdd Svi2 Div Ratio Setting
uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16)
@ -831,7 +831,7 @@ typedef struct {
} DriverSmuConfig_t;
typedef struct {
uint16_t GfxclkFmin; // MHz
uint16_t GfxclkFmax; // MHz
uint16_t GfxclkFreq1; // MHz
@ -844,7 +844,7 @@ typedef struct {
int16_t OverDrivePct; // %
uint16_t FanMaximumRpm;
uint16_t FanMinimumPwm;
uint16_t FanTargetTemperature; // Degree Celcius
uint16_t FanTargetTemperature; // Degree Celcius
uint16_t FanMode;
uint16_t FanMaxPwm;
uint16_t FanMinPwm;
@ -855,7 +855,7 @@ typedef struct {
uint32_t MmHubPadding[6]; // SMU internal use
} OverDriveTable_t;
} OverDriveTable_t;
typedef struct {
uint16_t CurrClock[PPCLK_COUNT];
@ -874,14 +874,14 @@ typedef struct {
uint16_t TemperatureMem ;
uint16_t TemperatureVrGfx ;
uint16_t TemperatureVrMem0 ;
uint16_t TemperatureVrMem1 ;
uint16_t TemperatureVrSoc ;
uint16_t TemperatureVrMem1 ;
uint16_t TemperatureVrSoc ;
uint16_t TemperatureLiquid0 ;
uint16_t TemperatureLiquid1 ;
uint16_t TemperatureLiquid1 ;
uint16_t TemperaturePlx ;
uint16_t Padding16 ;
uint32_t ThrottlerStatus ;
uint32_t ThrottlerStatus ;
uint8_t LinkDpmLevel;
uint8_t Padding8_2;
uint16_t CurrFanSpeed;
@ -907,14 +907,14 @@ typedef struct {
uint16_t TemperatureMem ;
uint16_t TemperatureVrGfx ;
uint16_t TemperatureVrMem0 ;
uint16_t TemperatureVrMem1 ;
uint16_t TemperatureVrSoc ;
uint16_t TemperatureVrMem1 ;
uint16_t TemperatureVrSoc ;
uint16_t TemperatureLiquid0 ;
uint16_t TemperatureLiquid1 ;
uint16_t TemperatureLiquid1 ;
uint16_t TemperaturePlx ;
uint16_t Padding16 ;
uint32_t ThrottlerStatus ;
uint32_t ThrottlerStatus ;
uint8_t LinkDpmLevel;
uint8_t Padding8_2;
uint16_t CurrFanSpeed;
@ -1024,11 +1024,11 @@ typedef struct {
uint16_t MaxClock; // This is either DCEFCLK or SOCCLK (in MHz)
uint16_t MinUclk;
uint16_t MaxUclk;
uint8_t WmSetting;
uint8_t Padding[3];
uint32_t MmHubPadding[8]; // SMU internal use
uint32_t MmHubPadding[8]; // SMU internal use
} WatermarkRowGeneric_t;
#define NUM_WM_RANGES 4
@ -1058,7 +1058,7 @@ typedef struct {
typedef struct {
uint16_t avgPsmCount[36];
uint16_t minPsmCount[36];
float avgPsmVoltage[36];
float avgPsmVoltage[36];
float minPsmVoltage[36];
uint32_t MmHubPadding[8]; // SMU internal use
@ -1069,7 +1069,7 @@ typedef struct {
uint8_t Padding;
uint8_t AvfsEn[AVFS_VOLTAGE_COUNT];
uint8_t OverrideVFT[AVFS_VOLTAGE_COUNT];
uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT];
@ -1122,7 +1122,7 @@ typedef struct {
uint8_t Gfx_IdleHystLimit;
uint8_t Gfx_FPS;
uint8_t Gfx_MinActiveFreqType;
uint8_t Gfx_BoosterFreqType;
uint8_t Gfx_BoosterFreqType;
uint8_t Gfx_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock.
uint16_t Gfx_MinActiveFreq; // MHz
uint16_t Gfx_BoosterFreq; // MHz
@ -1132,12 +1132,12 @@ typedef struct {
uint32_t Gfx_PD_Data_limit_c; // Q16
uint32_t Gfx_PD_Data_error_coeff; // Q16
uint32_t Gfx_PD_Data_error_rate_coeff; // Q16
uint8_t Soc_ActiveHystLimit;
uint8_t Soc_IdleHystLimit;
uint8_t Soc_FPS;
uint8_t Soc_MinActiveFreqType;
uint8_t Soc_BoosterFreqType;
uint8_t Soc_BoosterFreqType;
uint8_t Soc_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock.
uint16_t Soc_MinActiveFreq; // MHz
uint16_t Soc_BoosterFreq; // MHz
@ -1147,7 +1147,7 @@ typedef struct {
uint32_t Soc_PD_Data_limit_c; // Q16
uint32_t Soc_PD_Data_error_coeff; // Q16
uint32_t Soc_PD_Data_error_rate_coeff; // Q16
uint8_t Mem_ActiveHystLimit;
uint8_t Mem_IdleHystLimit;
uint8_t Mem_FPS;
@ -1168,20 +1168,20 @@ typedef struct {
uint8_t Mem_DownHystLimit;
uint16_t Mem_Fps;
uint32_t MmHubPadding[8]; // SMU internal use
uint32_t MmHubPadding[8]; // SMU internal use
} DpmActivityMonitorCoeffInt_t;
// Workload bits
#define WORKLOAD_PPLIB_DEFAULT_BIT 0
#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1
#define WORKLOAD_PPLIB_POWER_SAVING_BIT 2
#define WORKLOAD_PPLIB_VIDEO_BIT 3
#define WORKLOAD_PPLIB_VR_BIT 4
#define WORKLOAD_PPLIB_COMPUTE_BIT 5
#define WORKLOAD_PPLIB_CUSTOM_BIT 6
#define WORKLOAD_PPLIB_COUNT 7
#define WORKLOAD_PPLIB_DEFAULT_BIT 0
#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1
#define WORKLOAD_PPLIB_POWER_SAVING_BIT 2
#define WORKLOAD_PPLIB_VIDEO_BIT 3
#define WORKLOAD_PPLIB_VR_BIT 4
#define WORKLOAD_PPLIB_COMPUTE_BIT 5
#define WORKLOAD_PPLIB_CUSTOM_BIT 6
#define WORKLOAD_PPLIB_COUNT 7
// These defines are used with the following messages:
@ -1212,8 +1212,8 @@ typedef struct {
typedef struct {
float FlopsPerByteTable[RLC_PACE_TABLE_NUM_LEVELS];
uint32_t MmHubPadding[8]; // SMU internal use
uint32_t MmHubPadding[8]; // SMU internal use
} RlcPaceFlopsPerByteOverride_t;
// These defines are used with the SMC_MSG_SetUclkFastSwitch message.

322
sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h
View file

@ -25,7 +25,7 @@
#define __SMU11_DRIVER_IF_SIENNA_CICHLID_H__
// *** IMPORTANT ***
// SMU TEAM: Always increment the interface version if
// SMU TEAM: Always increment the interface version if
// any structure is changed in this file
#define SMU11_DRIVER_IF_VERSION 0x40
@ -42,10 +42,10 @@
#define NUM_DISPCLK_DPM_LEVELS 8
#define NUM_PIXCLK_DPM_LEVELS 8
#define NUM_DTBCLK_DPM_LEVELS 8
#define NUM_UCLK_DPM_LEVELS 4
#define NUM_UCLK_DPM_LEVELS 4
#define NUM_MP1CLK_DPM_LEVELS 2
#define NUM_LINK_LEVELS 2
#define NUM_FCLK_DPM_LEVELS 8
#define NUM_FCLK_DPM_LEVELS 8
#define NUM_XGMI_LEVELS 2
#define NUM_XGMI_PSTATE_LEVELS 4
#define NUM_OD_FAN_MAX_POINTS 6
@ -83,43 +83,43 @@
#define FEATURE_DPM_LINK_BIT 7
#define FEATURE_DPM_DCEFCLK_BIT 8
#define FEATURE_DPM_XGMI_BIT 9
#define FEATURE_MEM_VDDCI_SCALING_BIT 10
#define FEATURE_MEM_VDDCI_SCALING_BIT 10
#define FEATURE_MEM_MVDD_SCALING_BIT 11
//Idle
//Idle
#define FEATURE_DS_GFXCLK_BIT 12
#define FEATURE_DS_SOCCLK_BIT 13
#define FEATURE_DS_FCLK_BIT 14
#define FEATURE_DS_LCLK_BIT 15
#define FEATURE_DS_DCEFCLK_BIT 16
#define FEATURE_DS_UCLK_BIT 17
#define FEATURE_GFX_ULV_BIT 18
#define FEATURE_FW_DSTATE_BIT 19
#define FEATURE_GFX_ULV_BIT 18
#define FEATURE_FW_DSTATE_BIT 19
#define FEATURE_GFXOFF_BIT 20
#define FEATURE_BACO_BIT 21
#define FEATURE_MM_DPM_PG_BIT 22
#define FEATURE_MM_DPM_PG_BIT 22
#define FEATURE_SPARE_23_BIT 23
//Throttler/Response
//Throttler/Response
#define FEATURE_PPT_BIT 24
#define FEATURE_TDC_BIT 25
#define FEATURE_APCC_PLUS_BIT 26
#define FEATURE_GTHR_BIT 27
#define FEATURE_ACDC_BIT 28
#define FEATURE_VR0HOT_BIT 29
#define FEATURE_VR1HOT_BIT 30
#define FEATURE_VR1HOT_BIT 30
#define FEATURE_FW_CTF_BIT 31
#define FEATURE_FAN_CONTROL_BIT 32
#define FEATURE_THERMAL_BIT 33
#define FEATURE_GFX_DCS_BIT 34
//VF
//VF
#define FEATURE_RM_BIT 35
#define FEATURE_LED_DISPLAY_BIT 36
//Other
//Other
#define FEATURE_GFX_SS_BIT 37
#define FEATURE_OUT_OF_BAND_MONITOR_BIT 38
#define FEATURE_TEMP_DEPENDENT_VMIN_BIT 39
#define FEATURE_MMHUB_PG_BIT 40
#define FEATURE_MMHUB_PG_BIT 40
#define FEATURE_ATHUB_PG_BIT 41
#define FEATURE_APCC_DFLL_BIT 42
#define FEATURE_DF_SUPERV_BIT 43
@ -225,7 +225,7 @@ typedef enum {
#define FW_DSTATE_MP1_WHISPER_MODE_BIT 6
#define FW_DSTATE_SOC_LIV_MIN_BIT 7
#define FW_DSTATE_SOC_PLL_PWRDN_BIT 8
#define FW_DSTATE_MEM_PLL_PWRDN_BIT 9
#define FW_DSTATE_MEM_PLL_PWRDN_BIT 9
#define FW_DSTATE_OPTIMIZE_MALL_REFRESH_BIT 10
#define FW_DSTATE_MEM_PSI_BIT 11
#define FW_DSTATE_HSR_NON_STROBE_BIT 12
@ -234,8 +234,8 @@ typedef enum {
#define FW_DSTATE_SOC_ULV_MASK (1 << FW_DSTATE_SOC_ULV_BIT )
#define FW_DSTATE_G6_HSR_MASK (1 << FW_DSTATE_G6_HSR_BIT )
#define FW_DSTATE_G6_PHY_VDDCI_OFF_MASK (1 << FW_DSTATE_G6_PHY_VDDCI_OFF_BIT )
#define FW_DSTATE_MP1_DS_MASK (1 << FW_DSTATE_MP1_DS_BIT )
#define FW_DSTATE_MP0_DS_MASK (1 << FW_DSTATE_MP0_DS_BIT )
#define FW_DSTATE_MP1_DS_MASK (1 << FW_DSTATE_MP1_DS_BIT )
#define FW_DSTATE_MP0_DS_MASK (1 << FW_DSTATE_MP0_DS_BIT )
#define FW_DSTATE_SMN_DS_MASK (1 << FW_DSTATE_SMN_DS_BIT )
#define FW_DSTATE_MP1_WHISPER_MODE_MASK (1 << FW_DSTATE_MP1_WHISPER_MODE_BIT )
#define FW_DSTATE_SOC_LIV_MIN_MASK (1 << FW_DSTATE_SOC_LIV_MIN_BIT )
@ -312,10 +312,10 @@ typedef enum {
I2C_CONTROLLER_NAME_VR_VDDCI,
I2C_CONTROLLER_NAME_VR_MVDD,
I2C_CONTROLLER_NAME_LIQUID0,
I2C_CONTROLLER_NAME_LIQUID1,
I2C_CONTROLLER_NAME_LIQUID1,
I2C_CONTROLLER_NAME_PLX,
I2C_CONTROLLER_NAME_OTHER,
I2C_CONTROLLER_NAME_COUNT,
I2C_CONTROLLER_NAME_COUNT,
} I2cControllerName_e;
typedef enum {
@ -325,10 +325,10 @@ typedef enum {
I2C_CONTROLLER_THROTTLER_VR_VDDCI,
I2C_CONTROLLER_THROTTLER_VR_MVDD,
I2C_CONTROLLER_THROTTLER_LIQUID0,
I2C_CONTROLLER_THROTTLER_LIQUID1,
I2C_CONTROLLER_THROTTLER_LIQUID1,
I2C_CONTROLLER_THROTTLER_PLX,
I2C_CONTROLLER_THROTTLER_INA3221,
I2C_CONTROLLER_THROTTLER_COUNT,
I2C_CONTROLLER_THROTTLER_COUNT,
} I2cControllerThrottler_e;
typedef enum {
@ -336,24 +336,24 @@ typedef enum {
I2C_CONTROLLER_PROTOCOL_VR_IR35217,
I2C_CONTROLLER_PROTOCOL_TMP_TMP102A,
I2C_CONTROLLER_PROTOCOL_INA3221,
I2C_CONTROLLER_PROTOCOL_COUNT,
I2C_CONTROLLER_PROTOCOL_COUNT,
} I2cControllerProtocol_e;
typedef struct {
uint8_t Enabled;
uint8_t Speed;
uint8_t SlaveAddress;
uint8_t SlaveAddress;
uint8_t ControllerPort;
uint8_t ControllerName;
uint8_t ThermalThrotter;
uint8_t I2cProtocol;
uint8_t PaddingConfig;
uint8_t PaddingConfig;
} I2cControllerConfig_t;
typedef enum {
I2C_PORT_SVD_SCL = 0,
I2C_PORT_GPIO,
} I2cPort_e;
I2C_PORT_SVD_SCL = 0,
I2C_PORT_GPIO,
} I2cPort_e;
typedef enum {
I2C_SPEED_FAST_50K = 0, //50 Kbits/s
@ -361,14 +361,14 @@ typedef enum {
I2C_SPEED_FAST_400K, //400 Kbits/s
I2C_SPEED_FAST_PLUS_1M, //1 Mbits/s (in fast mode)
I2C_SPEED_HIGH_1M, //1 Mbits/s (in high speed mode)
I2C_SPEED_HIGH_2M, //2.3 Mbits/s
I2C_SPEED_COUNT,
I2C_SPEED_HIGH_2M, //2.3 Mbits/s
I2C_SPEED_COUNT,
} I2cSpeed_e;
typedef enum {
I2C_CMD_READ = 0,
I2C_CMD_WRITE,
I2C_CMD_COUNT,
I2C_CMD_COUNT,
} I2cCmdType_e;
typedef enum {
@ -426,36 +426,36 @@ typedef enum {
PG_POWER_UP,
} PowerGatingSettings_e;
typedef struct {
typedef struct {
uint32_t a; // store in IEEE float format in this variable
uint32_t b; // store in IEEE float format in this variable
uint32_t c; // store in IEEE float format in this variable
} QuadraticInt_t;
typedef struct {
typedef struct {
uint32_t a; // store in fixed point, [31:20] signed integer, [19:0] fractional bits
uint32_t b; // store in fixed point, [31:20] signed integer, [19:0] fractional bits
uint32_t c; // store in fixed point, [31:20] signed integer, [19:0] fractional bits
} QuadraticFixedPoint_t;
typedef struct {
typedef struct {
uint32_t m; // store in IEEE float format in this variable
uint32_t b; // store in IEEE float format in this variable
} LinearInt_t;
typedef struct {
typedef struct {
uint32_t a; // store in IEEE float format in this variable
uint32_t b; // store in IEEE float format in this variable
uint32_t c; // store in IEEE float format in this variable
} DroopInt_t;
//Piecewise linear droop model, Sienna_Cichlid currently used only for GFX DFLL
//Piecewise linear droop model, Sienna_Cichlid currently used only for GFX DFLL
#define NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS 5
typedef enum {
PIECEWISE_LINEAR_FUSED_MODEL = 0,
PIECEWISE_LINEAR_PP_MODEL,
QUADRATIC_PP_MODEL,
PERPART_PIECEWISE_LINEAR_PP_MODEL,
PERPART_PIECEWISE_LINEAR_PP_MODEL,
} DfllDroopModelSelect_e;
typedef struct {
@ -464,17 +464,17 @@ typedef struct {
}PiecewiseLinearDroopInt_t;
typedef enum {
GFXCLK_SOURCE_PLL = 0,
GFXCLK_SOURCE_DFLL,
GFXCLK_SOURCE_COUNT,
} GFXCLK_SOURCE_e;
GFXCLK_SOURCE_PLL = 0,
GFXCLK_SOURCE_DFLL,
GFXCLK_SOURCE_COUNT,
} GFXCLK_SOURCE_e;
//Only Clks that have DPM descriptors are listed here
//Only Clks that have DPM descriptors are listed here
typedef enum {
PPCLK_GFXCLK = 0,
PPCLK_SOCCLK,
PPCLK_UCLK,
PPCLK_FCLK,
PPCLK_FCLK,
PPCLK_DCLK_0,
PPCLK_VCLK_0,
PPCLK_DCLK_1,
@ -552,18 +552,18 @@ typedef struct {
uint8_t VoltageMode; // 0 - AVFS only, 1- min(AVFS,SS), 2-SS only
uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM
uint8_t NumDiscreteLevels; // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used
uint8_t Padding;
uint8_t Padding;
LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz)
QuadraticInt_t SsCurve; // Slow-slow curve (GHz->V)
uint16_t SsFmin; // Fmin for SS curve. If SS curve is selected, will use V@SSFmin for F <= Fmin
uint16_t Padding16;
uint16_t Padding16;
} DpmDescriptor_t;
typedef enum {
PPT_THROTTLER_PPT0,
PPT_THROTTLER_PPT1,
PPT_THROTTLER_PPT2,
PPT_THROTTLER_PPT3,
PPT_THROTTLER_PPT3,
PPT_THROTTLER_COUNT
} PPT_THROTTLER_e;
@ -574,9 +574,9 @@ typedef enum {
TEMP_VR_GFX,
TEMP_VR_MEM0,
TEMP_VR_MEM1,
TEMP_VR_SOC,
TEMP_VR_SOC,
TEMP_LIQUID0,
TEMP_LIQUID1,
TEMP_LIQUID1,
TEMP_PLX,
TEMP_COUNT,
} TEMP_e;
@ -592,7 +592,7 @@ typedef enum {
CUSTOMER_VARIANT_FALCON,
CUSTOMER_VARIANT_COUNT,
} CUSTOMER_VARIANT_e;
// Used for 2-step UCLK DPM change workaround
typedef struct {
uint16_t Fmin;
@ -618,12 +618,12 @@ typedef struct {
uint16_t TdcLimitTau[TDC_THROTTLER_COUNT]; // Time constant of LPF in ms
uint16_t TemperatureLimit[TEMP_COUNT]; // Celcius
uint32_t FitLimit; // Failures in time (failures per million parts over the defined lifetime)
// SECTION: Power Configuration
uint8_t TotalPowerConfig; //0-TDP, 1-TGP, 2-TCP Estimated, 3-TCP Measured. Use defines from PwrConfig_e
uint8_t TotalPowerPadding[3];
uint8_t TotalPowerPadding[3];
// SECTION: APCC Settings
uint32_t ApccPlusResidencyLimit;
@ -639,14 +639,14 @@ typedef struct {
// SECTION: Throttler settings
uint32_t ThrottlerControlMask; // See Throtter masks defines
// SECTION: FW DSTATE Settings
// SECTION: FW DSTATE Settings
uint32_t FwDStateMask; // See FW DState masks defines
// SECTION: ULV Settings
uint16_t UlvVoltageOffsetSoc; // In mV(Q2)
uint16_t UlvVoltageOffsetGfx; // In mV(Q2)
uint16_t MinVoltageUlvGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX in ULV mode
uint16_t MinVoltageUlvGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX in ULV mode
uint16_t MinVoltageUlvSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC in ULV mode
uint16_t SocLIVmin; // In mV(Q2) Long Idle Vmin (deep ULV), for VDD_SOC
@ -671,7 +671,7 @@ typedef struct {
uint16_t VDDGFX_Vmin_LoTemp; // mV Q2
uint16_t VDDSOC_Vmin_HiTemp; // mV Q2
uint16_t VDDSOC_Vmin_LoTemp; // mV Q2
uint16_t VDDGFX_TVminHystersis; // Celcius
uint16_t VDDSOC_TVminHystersis; // Celcius
@ -694,9 +694,9 @@ typedef struct {
DroopInt_t PerPartDroopModelGfxDfll[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //GHz ->Vstore in IEEE float format
uint32_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz
uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:Div-1/8
// Used for MALL performance boost
uint16_t FclkBoostFreq; // In Mhz
uint16_t FclkParamPadding;
@ -708,32 +708,32 @@ typedef struct {
uint16_t MemMvddVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2)
// GFXCLK DPM
uint16_t GfxclkFgfxoffEntry; // in Mhz
uint16_t GfxclkFinit; // in Mhz
uint16_t GfxclkFidle; // in MHz
uint16_t GfxclkFinit; // in Mhz
uint16_t GfxclkFidle; // in MHz
uint8_t GfxclkSource; // 0 = PLL, 1 = DFLL
uint8_t GfxclkPadding;
// GFX GPO
// GFX GPO
uint8_t GfxGpoSubFeatureMask; // bit 0 = PACE, bit 1 = DEM
uint8_t GfxGpoEnabledWorkPolicyMask; //Any policy that GPO can be enabled
uint8_t GfxGpoDisabledWorkPolicyMask; //Any policy that GPO can be disabled
uint8_t GfxGpoPadding[1];
uint32_t GfxGpoVotingAllow; //For indicating which feature changes should result in a GPO table recalculation
uint32_t GfxGpoPadding32[4];
uint32_t GfxGpoPadding32[4];
uint16_t GfxDcsFopt; // Optimal GFXCLK for DCS in Mhz
uint16_t GfxDcsFclkFopt; // Optimal FCLK for DCS in Mhz
uint16_t GfxDcsUclkFopt; // Optimal UCLK for DCS in Mhz
uint16_t DcsGfxOffVoltage; //Voltage in mV(Q2) applied to VDDGFX when entering DCS GFXOFF phase
uint16_t DcsGfxOffVoltage; //Voltage in mV(Q2) applied to VDDGFX when entering DCS GFXOFF phase
uint16_t DcsMinGfxOffTime; //Minimum amount of time PMFW shuts GFX OFF as part of GFX DCS phase
uint16_t DcsMaxGfxOffTime; //Maximum amount of time PMFW can shut GFX OFF as part of GFX DCS phase at a stretch.
uint32_t DcsMinCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS.
uint16_t DcsExitHysteresis; //The min amount of time power credit accumulator should have a value > 0 before SMU exits the DCS throttling phase.
uint16_t DcsExitHysteresis; //The min amount of time power credit accumulator should have a value > 0 before SMU exits the DCS throttling phase.
uint16_t DcsTimeout; //This is the amount of time SMU FW waits for RLC to put GFX into GFXOFF before reverting to the fallback mechanism of throttling GFXCLK to Fmin.
uint32_t DcsParamPadding[5];
@ -743,9 +743,9 @@ typedef struct {
// UCLK section
uint8_t LowestUclkReservedForUlv; // Set this to 1 if UCLK DPM0 is reserved for ULV-mode only
uint8_t PaddingMem[3];
uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 4 DPM states, 0-P0, 1-P1, 2-P2, 3-P3.
// Used for 2-Step UCLK change workaround
UclkDpmChangeRange_t UclkDpmSrcFreqRange; // In Mhz
UclkDpmChangeRange_t UclkDpmTargFreqRange; // In Mhz
@ -755,8 +755,8 @@ typedef struct {
// Link DPM Settings
uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4
uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16
uint16_t LclkFreq[NUM_LINK_LEVELS];
uint16_t LclkFreq[NUM_LINK_LEVELS];
// SECTION: Fan Control
uint16_t FanStopTemp; //Celcius
uint16_t FanStartTemp; //Celcius
@ -767,36 +767,36 @@ typedef struct {
uint16_t FanAcousticLimitRpm;
uint16_t FanThrottlingRpm;
uint16_t FanMaximumRpm;
uint16_t MGpuFanBoostLimitRpm;
uint16_t MGpuFanBoostLimitRpm;
uint16_t FanTargetTemperature;
uint16_t FanTargetGfxclk;
uint16_t FanPadding16;
uint8_t FanTempInputSelect;
uint8_t FanPadding;
uint8_t FanZeroRpmEnable;
uint8_t FanZeroRpmEnable;
uint8_t FanTachEdgePerRev;
// The following are AFC override parameters. Leave at 0 to use FW defaults.
int16_t FuzzyFan_ErrorSetDelta;
int16_t FuzzyFan_ErrorRateSetDelta;
int16_t FuzzyFan_PwmSetDelta;
uint16_t FuzzyFan_Reserved;
// SECTION: AVFS
// SECTION: AVFS
// Overrides
uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT];
uint8_t dBtcGbGfxDfllModelSelect; //0 -> fused piece-wise model, 1 -> piece-wise linear(PPTable), 2 -> quadratic model(PPTable)
uint8_t dBtcGbGfxDfllModelSelect; //0 -> fused piece-wise model, 1 -> piece-wise linear(PPTable), 2 -> quadratic model(PPTable)
uint8_t Padding8_Avfs;
QuadraticInt_t qAvfsGb[AVFS_VOLTAGE_COUNT]; // GHz->V Override of fused curve
QuadraticInt_t qAvfsGb[AVFS_VOLTAGE_COUNT]; // GHz->V Override of fused curve
DroopInt_t dBtcGbGfxPll; // GHz->V BtcGb
DroopInt_t dBtcGbGfxDfll; // GHz->V BtcGb
DroopInt_t dBtcGbSoc; // GHz->V BtcGb
LinearInt_t qAgingGb[AVFS_VOLTAGE_COUNT]; // GHz->V
LinearInt_t qAgingGb[AVFS_VOLTAGE_COUNT]; // GHz->V
PiecewiseLinearDroopInt_t PiecewiseLinearDroopIntGfxDfll; //GHz ->Vstore in IEEE float format
QuadraticInt_t qStaticVoltageOffset[AVFS_VOLTAGE_COUNT]; // GHz->V
QuadraticInt_t qStaticVoltageOffset[AVFS_VOLTAGE_COUNT]; // GHz->V
uint16_t DcTol[AVFS_VOLTAGE_COUNT]; // mV Q2
@ -807,17 +807,17 @@ typedef struct {
uint16_t DcBtcMax[AVFS_VOLTAGE_COUNT]; // mV Q2
uint16_t DcBtcGb[AVFS_VOLTAGE_COUNT]; // mV Q2
// SECTION: XGMI
uint8_t XgmiDpmPstates[NUM_XGMI_LEVELS]; // 2 DPM states, high and low. 0-P0, 1-P1, 2-P2, 3-P3.
uint8_t XgmiDpmSpare[2];
// SECTION: Advanced Options
uint32_t DebugOverrides;
QuadraticInt_t ReservedEquation0;
QuadraticInt_t ReservedEquation1;
QuadraticInt_t ReservedEquation2;
QuadraticInt_t ReservedEquation3;
QuadraticInt_t ReservedEquation0;
QuadraticInt_t ReservedEquation1;
QuadraticInt_t ReservedEquation2;
QuadraticInt_t ReservedEquation3;
// SECTION: Sku Reserved
uint8_t CustomerVariant;
@ -825,17 +825,17 @@ typedef struct {
//VC BTC parameters are only applicable to VDD_GFX domain
uint8_t VcBtcEnabled;
uint16_t VcBtcVminT0; // T0_VMIN
uint16_t VcBtcFixedVminAgingOffset; // FIXED_VMIN_AGING_OFFSET
uint16_t VcBtcVmin2PsmDegrationGb; // VMIN_TO_PSM_DEGRADATION_GB
uint16_t VcBtcFixedVminAgingOffset; // FIXED_VMIN_AGING_OFFSET
uint16_t VcBtcVmin2PsmDegrationGb; // VMIN_TO_PSM_DEGRADATION_GB
uint32_t VcBtcPsmA; // A_PSM
uint32_t VcBtcPsmB; // B_PSM
uint32_t VcBtcVminA; // A_VMIN
uint32_t VcBtcVminB; // B_VMIN
uint32_t VcBtcVminB; // B_VMIN
//GPIO Board feature
uint16_t LedGpio; //GeneriA GPIO flag used to control the radeon LEDs
uint16_t GfxPowerStagesGpio; //Genlk_vsync GPIO flag used to control gfx power stages
uint16_t GfxPowerStagesGpio; //Genlk_vsync GPIO flag used to control gfx power stages
uint32_t SkuReserved[8];
@ -845,7 +845,7 @@ typedef struct {
uint32_t GamingClk[6];
// SECTION: I2C Control
I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS];
I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS];
uint8_t GpioScl; // GPIO Number for SCL Line, used only for CKSVII2C1
uint8_t GpioSda; // GPIO Number for SDA Line, used only for CKSVII2C1
@ -875,21 +875,21 @@ typedef struct {
uint16_t Mem0MaxCurrent; // in Amps
int8_t Mem0Offset; // in Amps
uint8_t Padding_TelemetryMem0;
uint16_t Mem1MaxCurrent; // in Amps
int8_t Mem1Offset; // in Amps
uint8_t Padding_TelemetryMem1;
uint32_t MvddRatio; // This is used for MVDD Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16)
// SECTION: GPIO Settings
uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching
uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching
uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event
uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event
uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event
uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event
uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event
uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event
uint8_t GthrGpio; // GPIO pin configured for GTHR Event
uint8_t GthrPolarity; // replace GPIO polarity for GTHR
@ -904,7 +904,7 @@ typedef struct {
uint8_t LedSpare1[2];
// SECTION: Clock Spread Spectrum
// GFXCLK PLL Spread Spectrum
uint8_t PllGfxclkSpreadEnabled; // on or off
uint8_t PllGfxclkSpreadPercent; // Q4.4
@ -914,7 +914,7 @@ typedef struct {
uint8_t DfllGfxclkSpreadEnabled; // on or off
uint8_t DfllGfxclkSpreadPercent; // Q4.4
uint16_t DfllGfxclkSpreadFreq; // kHz
// UCLK Spread Spectrum
uint16_t UclkSpreadPadding;
uint16_t UclkSpreadFreq; // kHz
@ -923,17 +923,17 @@ typedef struct {
uint8_t FclkSpreadEnabled; // on or off
uint8_t FclkSpreadPercent; // Q4.4
uint16_t FclkSpreadFreq; // kHz
// Section: Memory Config
uint32_t MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask.
uint32_t MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask.
uint8_t DramBitWidth; // For DRAM use only. See Dram Bit width type defines
uint8_t PaddingMem1[3];
// Section: Total Board Power
uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power
uint16_t BoardPowerPadding;
uint16_t BoardPowerPadding;
// SECTION: XGMI Training
uint8_t XgmiLinkSpeed [NUM_XGMI_PSTATE_LEVELS];
uint8_t XgmiLinkWidth [NUM_XGMI_PSTATE_LEVELS];
@ -947,7 +947,7 @@ typedef struct {
uint8_t PaddingUmcFlags[2];
// UCLK Spread Spectrum
uint8_t UclkSpreadPercent[16];
uint8_t UclkSpreadPercent[16];
// SECTION: Board Reserved
uint32_t BoardReserved[11];
@ -983,7 +983,7 @@ typedef struct {
// SECTION: Power Configuration
uint8_t TotalPowerConfig; //0-TDP, 1-TGP, 2-TCP Estimated, 3-TCP Measured. Use defines from PwrConfig_e
uint8_t TotalPowerPadding[3];
uint8_t TotalPowerPadding[3];
// SECTION: APCC Settings
uint32_t ApccPlusResidencyLimit;
@ -999,14 +999,14 @@ typedef struct {
// SECTION: Throttler settings
uint32_t ThrottlerControlMask; // See Throtter masks defines
// SECTION: FW DSTATE Settings
// SECTION: FW DSTATE Settings
uint32_t FwDStateMask; // See FW DState masks defines
// SECTION: ULV Settings
uint16_t UlvVoltageOffsetSoc; // In mV(Q2)
uint16_t UlvVoltageOffsetGfx; // In mV(Q2)
uint16_t MinVoltageUlvGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX in ULV mode
uint16_t MinVoltageUlvGfx; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_GFX in ULV mode
uint16_t MinVoltageUlvSoc; // In mV(Q2) Minimum Voltage ("Vmin") of VDD_SOC in ULV mode
uint16_t SocLIVmin;
@ -1068,12 +1068,12 @@ typedef struct {
uint16_t MemMvddVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2)
// GFXCLK DPM
uint16_t GfxclkFgfxoffEntry; // in Mhz
uint16_t GfxclkFinit; // in Mhz
uint16_t GfxclkFidle; // in MHz
uint16_t GfxclkFinit; // in Mhz
uint16_t GfxclkFidle; // in MHz
uint8_t GfxclkSource; // 0 = PLL, 1 = DFLL
uint8_t GfxclkPadding;
// GFX GPO
// GFX GPO
uint8_t GfxGpoSubFeatureMask; // bit 0 = PACE, bit 1 = DEM
uint8_t GfxGpoEnabledWorkPolicyMask; //Any policy that GPO can be enabled
uint8_t GfxGpoDisabledWorkPolicyMask; //Any policy that GPO can be disabled
@ -1086,14 +1086,14 @@ typedef struct {
uint16_t GfxDcsFclkFopt; // Optimal FCLK for DCS in Mhz
uint16_t GfxDcsUclkFopt; // Optimal UCLK for DCS in Mhz
uint16_t DcsGfxOffVoltage; //Voltage in mV(Q2) applied to VDDGFX when entering DCS GFXOFF phase
uint16_t DcsGfxOffVoltage; //Voltage in mV(Q2) applied to VDDGFX when entering DCS GFXOFF phase
uint16_t DcsMinGfxOffTime; //Minimum amount of time PMFW shuts GFX OFF as part of GFX DCS phase
uint16_t DcsMaxGfxOffTime; //Maximum amount of time PMFW can shut GFX OFF as part of GFX DCS phase at a stretch.
uint32_t DcsMinCreditAccum; //Min amount of positive credit accumulation before waking GFX up as part of DCS.
uint16_t DcsExitHysteresis; //The min amount of time power credit accumulator should have a value > 0 before SMU exits the DCS throttling phase.
uint16_t DcsExitHysteresis; //The min amount of time power credit accumulator should have a value > 0 before SMU exits the DCS throttling phase.
uint16_t DcsTimeout; //This is the amount of time SMU FW waits for RLC to put GFX into GFXOFF before reverting to the fallback mechanism of throttling GFXCLK to Fmin.
uint32_t DcsParamPadding[5];
@ -1115,7 +1115,7 @@ typedef struct {
// Link DPM Settings
uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4
uint8_t PcieLaneCount[NUM_LINK_LEVELS]; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16
uint16_t LclkFreq[NUM_LINK_LEVELS];
uint16_t LclkFreq[NUM_LINK_LEVELS];
// SECTION: Fan Control
uint16_t FanStopTemp; //Celcius
@ -1127,13 +1127,13 @@ typedef struct {
uint16_t FanAcousticLimitRpm;
uint16_t FanThrottlingRpm;
uint16_t FanMaximumRpm;
uint16_t MGpuFanBoostLimitRpm;
uint16_t MGpuFanBoostLimitRpm;
uint16_t FanTargetTemperature;
uint16_t FanTargetGfxclk;
uint16_t FanPadding16;
uint8_t FanTempInputSelect;
uint8_t FanPadding;
uint8_t FanZeroRpmEnable;
uint8_t FanZeroRpmEnable;
uint8_t FanTachEdgePerRev;
// The following are AFC override parameters. Leave at 0 to use FW defaults.
@ -1142,21 +1142,21 @@ typedef struct {
int16_t FuzzyFan_PwmSetDelta;
uint16_t FuzzyFan_Reserved;
// SECTION: AVFS
// SECTION: AVFS
// Overrides
uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT];
uint8_t dBtcGbGfxDfllModelSelect; //0 -> fused piece-wise model, 1 -> piece-wise linear(PPTable), 2 -> quadratic model(PPTable)
uint8_t dBtcGbGfxDfllModelSelect; //0 -> fused piece-wise model, 1 -> piece-wise linear(PPTable), 2 -> quadratic model(PPTable)
uint8_t Padding8_Avfs;
QuadraticInt_t qAvfsGb[AVFS_VOLTAGE_COUNT]; // GHz->V Override of fused curve
QuadraticInt_t qAvfsGb[AVFS_VOLTAGE_COUNT]; // GHz->V Override of fused curve
DroopInt_t dBtcGbGfxPll; // GHz->V BtcGb
DroopInt_t dBtcGbGfxDfll; // GHz->V BtcGb
DroopInt_t dBtcGbSoc; // GHz->V BtcGb
LinearInt_t qAgingGb[AVFS_VOLTAGE_COUNT]; // GHz->V
LinearInt_t qAgingGb[AVFS_VOLTAGE_COUNT]; // GHz->V
PiecewiseLinearDroopInt_t PiecewiseLinearDroopIntGfxDfll; //GHz ->Vstore in IEEE float format
QuadraticInt_t qStaticVoltageOffset[AVFS_VOLTAGE_COUNT]; // GHz->V
QuadraticInt_t qStaticVoltageOffset[AVFS_VOLTAGE_COUNT]; // GHz->V
uint16_t DcTol[AVFS_VOLTAGE_COUNT]; // mV Q2
@ -1185,16 +1185,16 @@ typedef struct {
//VC BTC parameters are only applicable to VDD_GFX domain
uint8_t VcBtcEnabled;
uint16_t VcBtcVminT0; // T0_VMIN
uint16_t VcBtcFixedVminAgingOffset; // FIXED_VMIN_AGING_OFFSET
uint16_t VcBtcVmin2PsmDegrationGb; // VMIN_TO_PSM_DEGRADATION_GB
uint16_t VcBtcFixedVminAgingOffset; // FIXED_VMIN_AGING_OFFSET
uint16_t VcBtcVmin2PsmDegrationGb; // VMIN_TO_PSM_DEGRADATION_GB
uint32_t VcBtcPsmA; // A_PSM
uint32_t VcBtcPsmB; // B_PSM
uint32_t VcBtcVminA; // A_VMIN
uint32_t VcBtcVminB; // B_VMIN
uint32_t VcBtcVminB; // B_VMIN
//GPIO Board feature
uint16_t LedGpio; //GeneriA GPIO flag used to control the radeon LEDs
uint16_t GfxPowerStagesGpio; //Genlk_vsync GPIO flag used to control gfx power stages
uint16_t GfxPowerStagesGpio; //Genlk_vsync GPIO flag used to control gfx power stages
uint32_t SkuReserved[63];
@ -1206,7 +1206,7 @@ typedef struct {
uint32_t GamingClk[6];
// SECTION: I2C Control
I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS];
I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS];
uint8_t GpioScl; // GPIO Number for SCL Line, used only for CKSVII2C1
uint8_t GpioSda; // GPIO Number for SDA Line, used only for CKSVII2C1
@ -1249,8 +1249,8 @@ typedef struct {
uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event
uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event
uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event
uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event
uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event
uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event
uint8_t GthrGpio; // GPIO pin configured for GTHR Event
uint8_t GthrPolarity; // replace GPIO polarity for GTHR
@ -1286,14 +1286,14 @@ typedef struct {
uint16_t FclkSpreadFreq; // kHz
// Section: Memory Config
uint32_t MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask.
uint32_t MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask.
uint8_t DramBitWidth; // For DRAM use only. See Dram Bit width type defines
uint8_t PaddingMem1[3];
// Section: Total Board Power
uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power
uint16_t BoardPowerPadding;
uint16_t BoardPowerPadding;
// SECTION: XGMI Training
uint8_t XgmiLinkSpeed [NUM_XGMI_PSTATE_LEVELS];
@ -1308,7 +1308,7 @@ typedef struct {
uint8_t PaddingUmcFlags[2];
// UCLK Spread Spectrum
uint8_t UclkSpreadPercent[16];
uint8_t UclkSpreadPercent[16];
// SECTION: Board Reserved
uint32_t BoardReserved[11];
@ -1328,15 +1328,15 @@ typedef struct {
uint16_t UclkAverageLpfTau;
uint16_t GfxActivityLpfTau;
uint16_t UclkActivityLpfTau;
uint16_t SocketPowerLpfTau;
uint16_t SocketPowerLpfTau;
uint16_t VcnClkAverageLpfTau;
uint16_t padding16;
uint16_t padding16;
} DriverSmuConfig_t;
typedef struct {
DriverSmuConfig_t DriverSmuConfig;
uint32_t Spare[7];
uint32_t Spare[7];
// Padding - ignore
uint32_t MmHubPadding[8]; // SMU internal use
} DriverSmuConfigExternal_t;
@ -1345,14 +1345,14 @@ typedef struct {
uint16_t GfxclkFmin; // MHz
uint16_t GfxclkFmax; // MHz
QuadraticInt_t CustomGfxVfCurve; // a: mV/MHz^2, b: mv/MHz, c: mV
uint16_t CustomCurveFmin; // MHz
uint16_t UclkFmin; // MHz
uint16_t CustomCurveFmin; // MHz
uint16_t UclkFmin; // MHz
uint16_t UclkFmax; // MHz
int16_t OverDrivePct; // %
uint16_t FanMaximumRpm;
uint16_t FanMinimumPwm;
uint16_t FanAcousticLimitRpm;
uint16_t FanTargetTemperature; // Degree Celcius
uint16_t FanTargetTemperature; // Degree Celcius
uint8_t FanLinearPwmPoints[NUM_OD_FAN_MAX_POINTS];
uint8_t FanLinearTempPoints[NUM_OD_FAN_MAX_POINTS];
uint16_t MaxOpTemp; // Degree Celcius
@ -1361,13 +1361,13 @@ typedef struct {
uint8_t FanZeroRpmStopTemp;
uint8_t FanMode;
uint8_t Padding[1];
} OverDriveTable_t;
} OverDriveTable_t;
typedef struct {
OverDriveTable_t OverDriveTable;
uint32_t Spare[8];
uint32_t Spare[8];
uint32_t MmHubPadding[8]; // SMU internal use
uint32_t MmHubPadding[8]; // SMU internal use
} OverDriveTableExternal_t;
typedef struct {
@ -1380,7 +1380,7 @@ typedef struct {
uint16_t AverageUclkFrequencyPreDs ;
uint16_t AverageUclkFrequencyPostDs ;
uint16_t AverageGfxActivity ;
uint16_t AverageUclkActivity ;
uint8_t CurrSocVoltageOffset ;
@ -1393,14 +1393,14 @@ typedef struct {
uint16_t TemperatureMem ;
uint16_t TemperatureVrGfx ;
uint16_t TemperatureVrMem0 ;
uint16_t TemperatureVrMem1 ;
uint16_t TemperatureVrSoc ;
uint16_t TemperatureVrMem1 ;
uint16_t TemperatureVrSoc ;
uint16_t TemperatureLiquid0 ;
uint16_t TemperatureLiquid1 ;
uint16_t TemperatureLiquid1 ;
uint16_t TemperaturePlx ;
uint16_t Padding16 ;
uint32_t ThrottlerStatus ;
uint32_t ThrottlerStatus ;
uint8_t LinkDpmLevel;
uint8_t CurrFanPwm;
uint16_t CurrFanSpeed;
@ -1414,9 +1414,9 @@ typedef struct {
//PMFW-4362
uint32_t EnergyAccumulator;
uint16_t AverageVclk0Frequency ;
uint16_t AverageDclk0Frequency ;
uint16_t AverageDclk0Frequency ;
uint16_t AverageVclk1Frequency ;
uint16_t AverageDclk1Frequency ;
uint16_t AverageDclk1Frequency ;
uint16_t VcnActivityPercentage ; //place holder, David N. to provide full sequence
uint8_t PcieRate ;
uint8_t PcieWidth ;
@ -1614,7 +1614,7 @@ typedef struct {
uint32_t Spare[1];
// Padding - ignore
uint32_t MmHubPadding[8]; // SMU internal use
uint32_t MmHubPadding[8]; // SMU internal use
} SmuMetricsExternal_t;
typedef struct {
@ -1622,7 +1622,7 @@ typedef struct {
uint16_t MaxClock; // This is either DCEFCLK or SOCCLK (in MHz)
uint16_t MinUclk;
uint16_t MaxUclk;
uint8_t WmSetting;
uint8_t Flags;
uint8_t Padding[2];
@ -1658,7 +1658,7 @@ typedef struct {
typedef struct {
uint16_t avgPsmCount[67];
uint16_t minPsmCount[67];
float avgPsmVoltage[67];
float avgPsmVoltage[67];
float minPsmVoltage[67];
} AvfsDebugTable_t;
@ -1673,7 +1673,7 @@ typedef struct {
uint8_t Padding;
uint8_t AvfsEn[AVFS_VOLTAGE_COUNT];
uint8_t OverrideVFT[AVFS_VOLTAGE_COUNT];
uint8_t OverrideAvfsGb[AVFS_VOLTAGE_COUNT];
@ -1729,7 +1729,7 @@ typedef struct {
uint8_t Gfx_IdleHystLimit;
uint8_t Gfx_FPS;
uint8_t Gfx_MinActiveFreqType;
uint8_t Gfx_BoosterFreqType;
uint8_t Gfx_BoosterFreqType;
uint8_t Gfx_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock.
uint16_t Gfx_MinActiveFreq; // MHz
uint16_t Gfx_BoosterFreq; // MHz
@ -1739,12 +1739,12 @@ typedef struct {
uint32_t Gfx_PD_Data_limit_c; // Q16
uint32_t Gfx_PD_Data_error_coeff; // Q16
uint32_t Gfx_PD_Data_error_rate_coeff; // Q16
uint8_t Fclk_ActiveHystLimit;
uint8_t Fclk_IdleHystLimit;
uint8_t Fclk_FPS;
uint8_t Fclk_MinActiveFreqType;
uint8_t Fclk_BoosterFreqType;
uint8_t Fclk_BoosterFreqType;
uint8_t Fclk_MinFreqStep; // Minimum delta between current and target frequeny in order for FW to change clock.
uint16_t Fclk_MinActiveFreq; // MHz
uint16_t Fclk_BoosterFreq; // MHz
@ -1754,7 +1754,7 @@ typedef struct {
uint32_t Fclk_PD_Data_limit_c; // Q16
uint32_t Fclk_PD_Data_error_coeff; // Q16
uint32_t Fclk_PD_Data_error_rate_coeff; // Q16
uint8_t Mem_ActiveHystLimit;
uint8_t Mem_IdleHystLimit;
uint8_t Mem_FPS;
@ -1780,19 +1780,19 @@ typedef struct {
typedef struct {
DpmActivityMonitorCoeffInt_t DpmActivityMonitorCoeffInt;
uint32_t MmHubPadding[8]; // SMU internal use
uint32_t MmHubPadding[8]; // SMU internal use
} DpmActivityMonitorCoeffIntExternal_t;
// Workload bits
#define WORKLOAD_PPLIB_DEFAULT_BIT 0
#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1
#define WORKLOAD_PPLIB_POWER_SAVING_BIT 2
#define WORKLOAD_PPLIB_VIDEO_BIT 3
#define WORKLOAD_PPLIB_VR_BIT 4
#define WORKLOAD_PPLIB_COMPUTE_BIT 5
#define WORKLOAD_PPLIB_CUSTOM_BIT 6
#define WORKLOAD_PPLIB_W3D_BIT 7
#define WORKLOAD_PPLIB_COUNT 8
#define WORKLOAD_PPLIB_DEFAULT_BIT 0
#define WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT 1
#define WORKLOAD_PPLIB_POWER_SAVING_BIT 2
#define WORKLOAD_PPLIB_VIDEO_BIT 3
#define WORKLOAD_PPLIB_VR_BIT 4
#define WORKLOAD_PPLIB_COMPUTE_BIT 5
#define WORKLOAD_PPLIB_CUSTOM_BIT 6
#define WORKLOAD_PPLIB_W3D_BIT 7
#define WORKLOAD_PPLIB_COUNT 8
// These defines are used with the following messages:
@ -1824,8 +1824,8 @@ typedef struct {
typedef struct {
RlcPaceFlopsPerByteOverride_t RlcPaceFlopsPerByteOverride;
uint32_t MmHubPadding[8]; // SMU internal use
uint32_t MmHubPadding[8]; // SMU internal use
} RlcPaceFlopsPerByteOverrideExternal_t;
// These defines are used with the SMC_MSG_SetUclkFastSwitch message.

2
sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu12_driver_if.h
View file

@ -25,7 +25,7 @@
#define SMU12_DRIVER_IF_H
// *** IMPORTANT ***
// SMU TEAM: Always increment the interface version if
// SMU TEAM: Always increment the interface version if
// any structure is changed in this file
#define SMU12_DRIVER_IF_VERSION 14

2
sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_0_7_ppsmc.h
View file

@ -95,7 +95,7 @@
//Resets
#define PPSMC_MSG_PrepareMp1ForUnload 0x2E
//DramLog Set DramLog SetDramSize
//DramLog Set DramLog SetDramSize
#define PPSMC_MSG_DramLogSetDramSize 0x2F
#define PPSMC_MSG_Mode1Reset 0x30

8
sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v11_0_ppsmc.h
View file

@ -66,14 +66,14 @@
#define PPSMC_MSG_SetSoftMinByFreq 0x1A
#define PPSMC_MSG_SetSoftMaxByFreq 0x1B
#define PPSMC_MSG_SetHardMinByFreq 0x1C
#define PPSMC_MSG_SetHardMaxByFreq 0x1D
#define PPSMC_MSG_SetHardMaxByFreq 0x1D
#define PPSMC_MSG_GetMinDpmFreq 0x1E
#define PPSMC_MSG_GetMaxDpmFreq 0x1F
#define PPSMC_MSG_GetDpmFreqByIndex 0x20
#define PPSMC_MSG_OverridePcieParameters 0x21
#define PPSMC_MSG_SetMinDeepSleepDcefclk 0x22
#define PPSMC_MSG_SetWorkloadMask 0x24
#define PPSMC_MSG_SetWorkloadMask 0x24
#define PPSMC_MSG_SetUclkFastSwitch 0x25
#define PPSMC_MSG_GetVoltageByDpm 0x26
#define PPSMC_MSG_SetVideoFps 0x27
@ -83,7 +83,7 @@
#define PPSMC_MSG_AllowGfxOff 0x29
#define PPSMC_MSG_DisallowGfxOff 0x2A
#define PPSMC_MSG_PowerUpVcn 0x2B
#define PPSMC_MSG_PowerDownVcn 0x2C
#define PPSMC_MSG_PowerDownVcn 0x2C
#define PPSMC_MSG_PowerUpJpeg 0x2D
#define PPSMC_MSG_PowerDownJpeg 0x2E
//reserve 0x29 to 0x30 for PG harvesting TBD
@ -112,7 +112,7 @@
#define PPSMC_MSG_ConfigureGfxDidt 0x3F
#define PPSMC_MSG_NumOfDisplays 0x40
#define PPSMC_MSG_SetMemoryChannelConfig 0x41
#define PPSMC_MSG_SetMemoryChannelConfig 0x41
#define PPSMC_MSG_SetGeminiMode 0x42
#define PPSMC_MSG_SetGeminiApertureHigh 0x43
#define PPSMC_MSG_SetGeminiApertureLow 0x44

4
sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_pmfw.h
View file

@ -30,7 +30,7 @@
#define ENABLE_DEBUG_FEATURES
// Firmware features
// Firmware features
// Feature Control Defines
#define FEATURE_CCLK_DPM_BIT 0
#define FEATURE_FAN_CONTROLLER_BIT 1
@ -92,7 +92,7 @@
#define FEATURE_ZSTATES_ECO_BIT 57
#define FEATURE_CC6_BIT 58
#define FEATURE_DS_UMCCLK_BIT 59
#define FEATURE_DS_HSPCLK_BIT 60
#define FEATURE_DS_HSPCLK_BIT 60
#define NUM_FEATURES 61
typedef struct {

26
sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_1_ppsmc.h
View file

@ -24,17 +24,17 @@
#ifndef SMU_13_0_1_PPSMC_H
#define SMU_13_0_1_PPSMC_H
/** @def PPS_PMFW_IF_VER
/** @def PPS_PMFW_IF_VER
* PPS (PPLib) to PMFW IF version 1.0
*/
#define PPS_PMFW_IF_VER "1.0" ///< Major.Minor
#define PPS_PMFW_IF_VER "1.0" ///< Major.Minor
/** @defgroup ResponseCodes PMFW Response Codes:
/** @defgroup ResponseCodes PMFW Response Codes:
* @{
*/
#define PPSMC_Result_OK 0x1 ///< Message Response OK
#define PPSMC_Result_Failed 0xFF ///< Message Response Failed
#define PPSMC_Result_UnknownCmd 0xFE ///< Message Response Unknown Command
#define PPSMC_Result_OK 0x1 ///< Message Response OK
#define PPSMC_Result_Failed 0xFF ///< Message Response Failed
#define PPSMC_Result_UnknownCmd 0xFE ///< Message Response Unknown Command
#define PPSMC_Result_CmdRejectedPrereq 0xFD ///< Message Response Command Failed Prerequisite
#define PPSMC_Result_CmdRejectedBusy 0xFC ///< Message Response Command Rejected due to PMFW is busy. Sender should retry sending this message
/** @}*/
@ -42,7 +42,7 @@
/** @defgroup definitions Message definitions
* @{
*/
#define PPSMC_MSG_TestMessage 0x01 ///< To check if PMFW is alive and responding. Requirement specified by PMFW team
#define PPSMC_MSG_TestMessage 0x01 ///< To check if PMFW is alive and responding. Requirement specified by PMFW team
#define PPSMC_MSG_GetSmuVersion 0x02 ///< Get PMFW version
#define PPSMC_MSG_GetDriverIfVersion 0x03 ///< Get PMFW_DRIVER_IF version
#define PPSMC_MSG_EnableGfxOff 0x04 ///< Enable GFXOFF
@ -55,7 +55,7 @@
#define PPSMC_MSG_ForcePowerDownGfx 0x0B ///< Force power down GFX, i.e. enter GFXOFF
#define PPSMC_MSG_PrepareMp1ForUnload 0x0C ///< Prepare PMFW for GFX driver unload
#define PPSMC_MSG_SetDriverDramAddrHigh 0x0D ///< Set high 32 bits of DRAM address for Driver table transfer
#define PPSMC_MSG_SetDriverDramAddrLow 0x0E ///< Set low 32 bits of DRAM address for Driver table transfer
#define PPSMC_MSG_SetDriverDramAddrLow 0x0E ///< Set low 32 bits of DRAM address for Driver table transfer
#define PPSMC_MSG_TransferTableSmu2Dram 0x0F ///< Transfer driver interface table from PMFW SRAM to DRAM
#define PPSMC_MSG_TransferTableDram2Smu 0x10 ///< Transfer driver interface table from DRAM to PMFW SRAM
#define PPSMC_MSG_GfxDeviceDriverReset 0x11 ///< Request GFX mode 2 reset
@ -84,14 +84,14 @@
#define PPSMC_MSG_QueryActiveWgp 0x28 ///< Query the anumber of active WGP number
#define PPSMC_Message_Count 0x29 ///< Total number of PPS messages
/** @}*/
/** @enum Mode_Reset_e
* Mode reset type, argument for PPSMC_MSG_GfxDeviceDriverReset
*/
/** @enum Mode_Reset_e
* Mode reset type, argument for PPSMC_MSG_GfxDeviceDriverReset
*/
typedef enum {
MODE1_RESET = 1, ///< Mode reset type 1
MODE2_RESET = 2 ///< Mode reset type 2
} Mode_Reset_e;
} Mode_Reset_e;
/** @}*/
#endif

32
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0_7_pptable.h
View file

@ -42,23 +42,23 @@
#define SMU_11_0_7_PP_POWERSAVINGCLOCK_VERSION 0x01 // Power Saving Clock Table Version 1.00
enum SMU_11_0_7_ODFEATURE_CAP {
SMU_11_0_7_ODCAP_GFXCLK_LIMITS = 0,
SMU_11_0_7_ODCAP_GFXCLK_CURVE,
SMU_11_0_7_ODCAP_UCLK_LIMITS,
SMU_11_0_7_ODCAP_POWER_LIMIT,
SMU_11_0_7_ODCAP_FAN_ACOUSTIC_LIMIT,
SMU_11_0_7_ODCAP_FAN_SPEED_MIN,
SMU_11_0_7_ODCAP_TEMPERATURE_FAN,
SMU_11_0_7_ODCAP_TEMPERATURE_SYSTEM,
SMU_11_0_7_ODCAP_MEMORY_TIMING_TUNE,
SMU_11_0_7_ODCAP_FAN_ZERO_RPM_CONTROL,
SMU_11_0_7_ODCAP_AUTO_UV_ENGINE,
SMU_11_0_7_ODCAP_AUTO_OC_ENGINE,
SMU_11_0_7_ODCAP_AUTO_OC_MEMORY,
SMU_11_0_7_ODCAP_GFXCLK_LIMITS = 0,
SMU_11_0_7_ODCAP_GFXCLK_CURVE,
SMU_11_0_7_ODCAP_UCLK_LIMITS,
SMU_11_0_7_ODCAP_POWER_LIMIT,
SMU_11_0_7_ODCAP_FAN_ACOUSTIC_LIMIT,
SMU_11_0_7_ODCAP_FAN_SPEED_MIN,
SMU_11_0_7_ODCAP_TEMPERATURE_FAN,
SMU_11_0_7_ODCAP_TEMPERATURE_SYSTEM,
SMU_11_0_7_ODCAP_MEMORY_TIMING_TUNE,
SMU_11_0_7_ODCAP_FAN_ZERO_RPM_CONTROL,
SMU_11_0_7_ODCAP_AUTO_UV_ENGINE,
SMU_11_0_7_ODCAP_AUTO_OC_ENGINE,
SMU_11_0_7_ODCAP_AUTO_OC_MEMORY,
SMU_11_0_7_ODCAP_FAN_CURVE,
SMU_11_0_ODCAP_AUTO_FAN_ACOUSTIC_LIMIT,
SMU_11_0_7_ODCAP_POWER_MODE,
SMU_11_0_7_ODCAP_COUNT,
SMU_11_0_7_ODCAP_POWER_MODE,
SMU_11_0_7_ODCAP_COUNT,
};
enum SMU_11_0_7_ODFEATURE_ID {
@ -178,7 +178,7 @@ struct smu_11_0_7_powerplay_table
uint32_t golden_revision; //PPGen use only: PP Table Revision on the Golden Data Base
uint16_t format_id; //PPGen use only: PPTable for different ASICs. For sienna_cichlid this should be 0x80
uint32_t platform_caps; //POWERPLAYABLE::ulPlatformCaps
uint8_t thermal_controller_type; //one of SMU_11_0_7_PP_THERMALCONTROLLER
uint16_t small_power_limit1;

6
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v11_0_pptable.h
View file

@ -145,14 +145,14 @@ struct smu_11_0_powerplay_table
uint32_t golden_revision;
uint16_t format_id;
uint32_t platform_caps; //POWERPLAYABLE::ulPlatformCaps
uint8_t thermal_controller_type; //one of SMU_11_0_PP_THERMALCONTROLLER
uint16_t small_power_limit1;
uint16_t small_power_limit2;
uint16_t boost_power_limit;
uint16_t od_turbo_power_limit; //Power limit setting for Turbo mode in Performance UI Tuning.
uint16_t od_power_save_power_limit; //Power limit setting for PowerSave/Optimal mode in Performance UI Tuning.
uint16_t od_turbo_power_limit; //Power limit setting for Turbo mode in Performance UI Tuning.
uint16_t od_power_save_power_limit; //Power limit setting for PowerSave/Optimal mode in Performance UI Tuning.
uint16_t software_shutdown_temp;
uint16_t reserve[6]; //Zero filled field reserved for future use

2
sys/dev/pci/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
View file

@ -139,7 +139,7 @@ static struct cmn2asic_mapping yellow_carp_table_map[SMU_TABLE_COUNT] = {
TAB_MAP_VALID(CUSTOM_DPM),
TAB_MAP_VALID(DPMCLOCKS),
};
static int yellow_carp_init_smc_tables(struct smu_context *smu)
{
struct smu_table_context *smu_table = &smu->smu_table;

10
sys/dev/pci/drm/include/linux/types.h
View file

@ -30,12 +30,12 @@ typedef uint32_t u32;
typedef int64_t s64;
typedef uint64_t u64;
typedef uint16_t __le16;
typedef uint16_t __be16;
typedef uint32_t __le32;
typedef uint16_t __le16;
typedef uint16_t __be16;
typedef uint32_t __le32;
typedef uint32_t __be32;
typedef uint64_t __le64;
typedef uint64_t __be64;
typedef uint64_t __le64;
typedef uint64_t __be64;
typedef bus_addr_t dma_addr_t;
typedef paddr_t phys_addr_t;

2
sys/dev/pci/drm/radeon/atombios.h
View file

@ -4865,7 +4865,7 @@ ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz
ulDentistVCOFreq: Dentist VCO clock in 10kHz unit.
ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit.
sDISPCLK_Voltage: Report Display clock voltage requirement.
ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Liano/Ontaio projects:
ATOM_DEVICE_CRT1_SUPPORT 0x0001
ATOM_DEVICE_CRT2_SUPPORT 0x0010

2
sys/dev/pci/drm/ttm/ttm_resource.c
View file

@ -717,7 +717,7 @@ ttm_kmap_iter_linear_io_init(struct ttm_kmap_iter_linear_io *iter_io,
&iter_io->dmap.bsh)) {
ret = -ENOMEM;
goto out_io_free;
}
}
iter_io->dmap.size = bus_size;
iosys_map_set_vaddr(&iter_io->dmap,
bus_space_vaddr(bdev->memt, iter_io->dmap.bsh));