SecBSD's official ports repository

devel/xtensa-esp32s2-elf/gcc/Makefile

@@ -0,0 +1,60 @@
+COMMENT =	gcc for ${CONFIG} cross-development
+
+V =		8.4.0
+VERSION =	${V}.2021.2
+PKGNAME =	${CONFIG}-gcc-${VERSION}
+REVISION =	1
+
+SHARED_LIBS +=  cc1plugin                 0.0 # 0.0
+SHARED_LIBS +=  cp1plugin                 0.0 # 0.0
+SHARED_LIBS +=  cc1                       0.0 # 0.0
+
+GH_ACCOUNT =	espressif
+GH_PROJECT =	gcc
+GH_TAGNAME =	esp-2021r2
+
+WANTLIB =	${COMPILER_LIBCXX} c gmp isl m mpc mpfr z
+
+SUBST_VARS +=	V
+
+LIBELF =	libelf-0.8.13
+MASTER_SITES0 =	https://github.com/earlephilhower/esp-quick-toolchain/raw/master/blobs/
+DISTFILES =	${DISTNAME}${EXTRACT_SUFX}
+DISTFILES +=	${LIBELF}${EXTRACT_SUFX}:0
+
+.if ${MACHINE_ARCH} == "powerpc64"
+PATCH_LIST =	patch-* vecstep-*
+.endif
+
+MODULES =		lang/python
+
+BUILD_DEPENDS +=	devel/${CONFIG}/binutils \
+			devel/${CONFIG}/newlib
+RUN_DEPENDS =		devel/${CONFIG}/binutils \
+			devel/${CONFIG}/newlib
+LIB_DEPENDS =		devel/gmp \
+			devel/libmpc \
+			devel/mpfr \
+			math/isl
+
+CONFIGURE_ENV +=	AR_FOR_TARGET="${INSTALLDIR}/bin/${CONFIG}-ar" \
+			RANLIB_FOR_TARGET="${INSTALLDIR}/bin/${CONFIG}-ranlib"
+CONFIGURE_ARGS +=	--with-as="${INSTALLDIR}/bin/${CONFIG}-as" \
+			--with-ld="${INSTALLDIR}/bin/${CONFIG}-ld" \
+			--with-sysroot="${INSTALLDIR}/${CONFIG}" \
+			--with-gmp="${LOCALBASE}" \
+			--with-isl="${LOCALBASE}" \
+			--enable-target-optspace \
+			--enable-gcov-custom-rtio \
+			--enable-libstdcxx-time=yes
+
+post-extract:
+	mv ${WRKDIR}/${LIBELF} ${WRKSRC}/libelf
+
+post-install:
+	chown -R ${SHAREOWN}:${SHAREGRP} \
+		${PREFIX}/lib/gcc/${CONFIG}/${V}/
+	${MODPY_BIN} ${MODPY_LIBDIR}/compileall.py ${PREFIX}/${CONFIG}/
+	@cd ${PREFIX}/${CONFIG}/bin && ln -s ${CONFIG}-gcc ${CONFIG}-cc
+
+.include <bsd.port.mk>

devel/xtensa-esp32s2-elf/gcc/distinfo

@@ -0,0 +1,4 @@
+SHA256 (gcc-esp-2021r2.tar.gz) = lJ1lgKB6lUmO2/DDU36oQNgDVk2HT995EnX17MlksJs=
+SHA256 (libelf-0.8.13.tar.gz) = WRqbTsgcHyBCqXqmBWTgy3nQQcUvqnQWrLOLyVvSx20=
+SIZE (gcc-esp-2021r2.tar.gz) = 102863056
+SIZE (libelf-0.8.13.tar.gz) = 148529

devel/xtensa-esp32s2-elf/gcc/patches/patch-include_xtensa-config_h

@@ -0,0 +1,127 @@
+Index: include/xtensa-config.h
+--- include/xtensa-config.h.orig
++++ include/xtensa-config.h
+@@ -1,5 +1,6 @@
+ /* Xtensa configuration settings.
+-   Copyright (C) 2001-2018 Free Software Foundation, Inc.
++   Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
++   Free Software Foundation, Inc.
+    Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica.
+ 
+    This program is free software; you can redistribute it and/or modify
+@@ -25,7 +26,7 @@
+    macros.  */
+ 
+ #undef XCHAL_HAVE_BE
+-#define XCHAL_HAVE_BE			1
++#define XCHAL_HAVE_BE			0
+ 
+ #undef XCHAL_HAVE_DENSITY
+ #define XCHAL_HAVE_DENSITY		1
+@@ -58,7 +59,7 @@
+ #define XCHAL_HAVE_MUL32		1
+ 
+ #undef XCHAL_HAVE_MUL32_HIGH
+-#define XCHAL_HAVE_MUL32_HIGH		0
++#define XCHAL_HAVE_MUL32_HIGH		1
+ 
+ #undef XCHAL_HAVE_DIV32
+ #define XCHAL_HAVE_DIV32		1
+@@ -73,7 +74,7 @@
+ #define XCHAL_HAVE_SEXT			1
+ 
+ #undef XCHAL_HAVE_LOOPS
+-#define XCHAL_HAVE_LOOPS		1
++#define XCHAL_HAVE_LOOPS		0
+ 
+ #undef XCHAL_HAVE_THREADPTR
+ #define XCHAL_HAVE_THREADPTR		1
+@@ -82,7 +83,7 @@
+ #define XCHAL_HAVE_RELEASE_SYNC		1
+ 
+ #undef XCHAL_HAVE_S32C1I
+-#define XCHAL_HAVE_S32C1I		1
++#define XCHAL_HAVE_S32C1I		0
+ 
+ #undef XCHAL_HAVE_BOOLEANS
+ #define XCHAL_HAVE_BOOLEANS		0
+@@ -102,13 +103,17 @@
+ #undef XCHAL_HAVE_FP_RSQRT
+ #define XCHAL_HAVE_FP_RSQRT		0
+ 
++#undef XCHAL_HAVE_DFP_ACCEL
++#define XCHAL_HAVE_DFP_ACCEL		0
++/* For backward compatibility */
+ #undef XCHAL_HAVE_DFP_accel
+-#define XCHAL_HAVE_DFP_accel			0
++#define XCHAL_HAVE_DFP_accel		XCHAL_HAVE_DFP_ACCEL
++
+ #undef XCHAL_HAVE_WINDOWED
+ #define XCHAL_HAVE_WINDOWED		1
+ 
+ #undef XCHAL_NUM_AREGS
+-#define XCHAL_NUM_AREGS			32
++#define XCHAL_NUM_AREGS			64
+ 
+ #undef XCHAL_HAVE_WIDE_BRANCHES
+ #define XCHAL_HAVE_WIDE_BRANCHES	0
+@@ -118,34 +123,31 @@
+ 
+ 
+ #undef XCHAL_ICACHE_SIZE
+-#define XCHAL_ICACHE_SIZE		16384
++#define XCHAL_ICACHE_SIZE		0
+ 
+ #undef XCHAL_DCACHE_SIZE
+-#define XCHAL_DCACHE_SIZE		16384
++#define XCHAL_DCACHE_SIZE		0
+ 
+ #undef XCHAL_ICACHE_LINESIZE
+-#define XCHAL_ICACHE_LINESIZE		32
++#define XCHAL_ICACHE_LINESIZE		16
+ 
+ #undef XCHAL_DCACHE_LINESIZE
+-#define XCHAL_DCACHE_LINESIZE		32
++#define XCHAL_DCACHE_LINESIZE		16
+ 
+ #undef XCHAL_ICACHE_LINEWIDTH
+-#define XCHAL_ICACHE_LINEWIDTH		5
++#define XCHAL_ICACHE_LINEWIDTH		4
+ 
+ #undef XCHAL_DCACHE_LINEWIDTH
+-#define XCHAL_DCACHE_LINEWIDTH		5
++#define XCHAL_DCACHE_LINEWIDTH		4
+ 
+ #undef XCHAL_DCACHE_IS_WRITEBACK
+-#define XCHAL_DCACHE_IS_WRITEBACK	1
++#define XCHAL_DCACHE_IS_WRITEBACK	0
+ 
+ 
+ #undef XCHAL_HAVE_MMU
+-#define XCHAL_HAVE_MMU			1
++#define XCHAL_HAVE_MMU			0
+ 
+-#undef XCHAL_MMU_MIN_PTE_PAGE_SIZE
+-#define XCHAL_MMU_MIN_PTE_PAGE_SIZE	12
+ 
+-
+ #undef XCHAL_HAVE_DEBUG
+ #define XCHAL_HAVE_DEBUG		1
+ 
+@@ -172,5 +174,16 @@
+ #define XSHAL_ABI			XTHAL_ABI_WINDOWED
+ #define XTHAL_ABI_WINDOWED		0
+ #define XTHAL_ABI_CALL0			1
++
++
++#undef XCHAL_M_STAGE
++#define XCHAL_M_STAGE			3
++
++#undef XTENSA_MARCH_LATEST
++#define XTENSA_MARCH_LATEST		270009
++
++#undef XTENSA_MARCH_EARLIEST
++#define XTENSA_MARCH_EARLIEST		270009
++
+ 
+ #endif /* !XTENSA_CONFIG_H */

devel/xtensa-esp32s2-elf/gcc/pkg/DESCR

@@ -0,0 +1 @@
+GNU cross compiler suite, configured for the xtensa-esp32s2-elf target.