127 lines
3 KiB
Text
127 lines
3 KiB
Text
Index: include/xtensa-config.h
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--- include/xtensa-config.h.orig
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+++ include/xtensa-config.h
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@@ -1,5 +1,6 @@
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/* Xtensa configuration settings.
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- Copyright (C) 2001-2018 Free Software Foundation, Inc.
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+ Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
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+ Free Software Foundation, Inc.
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Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica.
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This program is free software; you can redistribute it and/or modify
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@@ -25,7 +26,7 @@
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macros. */
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#undef XCHAL_HAVE_BE
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-#define XCHAL_HAVE_BE 1
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+#define XCHAL_HAVE_BE 0
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#undef XCHAL_HAVE_DENSITY
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#define XCHAL_HAVE_DENSITY 1
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@@ -58,7 +59,7 @@
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#define XCHAL_HAVE_MUL32 1
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#undef XCHAL_HAVE_MUL32_HIGH
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-#define XCHAL_HAVE_MUL32_HIGH 0
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+#define XCHAL_HAVE_MUL32_HIGH 1
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#undef XCHAL_HAVE_DIV32
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#define XCHAL_HAVE_DIV32 1
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@@ -73,7 +74,7 @@
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#define XCHAL_HAVE_SEXT 1
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#undef XCHAL_HAVE_LOOPS
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-#define XCHAL_HAVE_LOOPS 1
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+#define XCHAL_HAVE_LOOPS 0
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#undef XCHAL_HAVE_THREADPTR
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#define XCHAL_HAVE_THREADPTR 1
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@@ -82,7 +83,7 @@
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#define XCHAL_HAVE_RELEASE_SYNC 1
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#undef XCHAL_HAVE_S32C1I
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-#define XCHAL_HAVE_S32C1I 1
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+#define XCHAL_HAVE_S32C1I 0
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#undef XCHAL_HAVE_BOOLEANS
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#define XCHAL_HAVE_BOOLEANS 0
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@@ -102,13 +103,17 @@
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#undef XCHAL_HAVE_FP_RSQRT
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#define XCHAL_HAVE_FP_RSQRT 0
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+#undef XCHAL_HAVE_DFP_ACCEL
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+#define XCHAL_HAVE_DFP_ACCEL 0
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+/* For backward compatibility */
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#undef XCHAL_HAVE_DFP_accel
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-#define XCHAL_HAVE_DFP_accel 0
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+#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL
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+
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#undef XCHAL_HAVE_WINDOWED
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#define XCHAL_HAVE_WINDOWED 1
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#undef XCHAL_NUM_AREGS
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-#define XCHAL_NUM_AREGS 32
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+#define XCHAL_NUM_AREGS 64
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#undef XCHAL_HAVE_WIDE_BRANCHES
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#define XCHAL_HAVE_WIDE_BRANCHES 0
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@@ -118,34 +123,31 @@
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#undef XCHAL_ICACHE_SIZE
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-#define XCHAL_ICACHE_SIZE 16384
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+#define XCHAL_ICACHE_SIZE 0
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#undef XCHAL_DCACHE_SIZE
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-#define XCHAL_DCACHE_SIZE 16384
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+#define XCHAL_DCACHE_SIZE 0
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#undef XCHAL_ICACHE_LINESIZE
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-#define XCHAL_ICACHE_LINESIZE 32
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+#define XCHAL_ICACHE_LINESIZE 16
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#undef XCHAL_DCACHE_LINESIZE
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-#define XCHAL_DCACHE_LINESIZE 32
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+#define XCHAL_DCACHE_LINESIZE 16
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#undef XCHAL_ICACHE_LINEWIDTH
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-#define XCHAL_ICACHE_LINEWIDTH 5
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+#define XCHAL_ICACHE_LINEWIDTH 4
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#undef XCHAL_DCACHE_LINEWIDTH
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-#define XCHAL_DCACHE_LINEWIDTH 5
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+#define XCHAL_DCACHE_LINEWIDTH 4
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#undef XCHAL_DCACHE_IS_WRITEBACK
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-#define XCHAL_DCACHE_IS_WRITEBACK 1
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+#define XCHAL_DCACHE_IS_WRITEBACK 0
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#undef XCHAL_HAVE_MMU
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-#define XCHAL_HAVE_MMU 1
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+#define XCHAL_HAVE_MMU 0
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-#undef XCHAL_MMU_MIN_PTE_PAGE_SIZE
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-#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12
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-
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#undef XCHAL_HAVE_DEBUG
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#define XCHAL_HAVE_DEBUG 1
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@@ -172,5 +174,16 @@
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#define XSHAL_ABI XTHAL_ABI_WINDOWED
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#define XTHAL_ABI_WINDOWED 0
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#define XTHAL_ABI_CALL0 1
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+
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+
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+#undef XCHAL_M_STAGE
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+#define XCHAL_M_STAGE 3
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+
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+#undef XTENSA_MARCH_LATEST
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+#define XTENSA_MARCH_LATEST 270009
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+
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+#undef XTENSA_MARCH_EARLIEST
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+#define XTENSA_MARCH_EARLIEST 270009
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+
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#endif /* !XTENSA_CONFIG_H */
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