254 lines
10 KiB
C
254 lines
10 KiB
C
/*
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* Copyright 2017-2018 Kevin Brace. All Rights Reserved.
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* Copyright 2007-2015 OpenChrome Project
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* [https://www.freedesktop.org/wiki/Openchrome]
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* Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
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* Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sub license,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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/*
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* via_fp.h
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*
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* Header file for via_fp.c.
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*/
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#ifndef _VIA_FP_H_
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#define _VIA_FP_H_ 1
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/*
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* These FP DPA parameters were copied from VIA Technologies
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* xf86-video-via v83-44398 source code.
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*/
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/*
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* P4M890 chipset FP DPA parameters default setting.
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*/
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static VIADPARec viaDPAP4M890ClockDefault[] = {
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/* DVP0 Adjustment, DVP0 Clock Drive, DVP0 Data Drive,
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* DVP1 Adjustment, DVP1 Clock Drive, DVP1 Data Drive,
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* FPDP Low Adjustment, FPDP High Adjustment */
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{ 0x07, 0x00, 0x00,
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0x03, 0x00, 0x00,
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0x04, 0x08}
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};
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/*
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* P4M890 chipset FP DPA parameters for dot clock at or above 50 MHz
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* but below 70 MHz.
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*/
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static VIADPARec viaDPAP4M890Clock50M70M[] = {
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/* DVP0 Adjustment, DVP0 Clock Drive, DVP0 Data Drive,
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* DVP1 Adjustment, DVP1 Clock Drive, DVP1 Data Drive,
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* FPDP Low Adjustment, FPDP High Adjustment */
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{ 0x06, 0x00, 0x00,
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0x03, 0x00, 0x00,
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0x04, 0x08}
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};
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/*
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* P4M890 chipset FP DPA parameters for dot clock at or above 70 MHz
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* but below 100 MHz.
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*/
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static VIADPARec viaDPAP4M890Clock70M100M[] = {
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/* DVP0 Adjustment, DVP0 Clock Drive, DVP0 Data Drive,
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* DVP1 Adjustment, DVP1 Clock Drive, DVP1 Data Drive,
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* FPDP Low Adjustment, FPDP High Adjustment */
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{ 0x03, 0x00, 0x00,
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0x03, 0x00, 0x00,
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0x04, 0x08}
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};
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/*
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* P4M890 chipset FP DPA parameters for dot clock at or above 100 MHz
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* but below 150 MHz.
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*/
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static VIADPARec viaDPAP4M890Clock100M150M[] = {
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/* DVP0 Adjustment, DVP0 Clock Drive, DVP0 Data Drive,
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* DVP1 Adjustment, DVP1 Clock Drive, DVP1 Data Drive,
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* FPDP Low Adjustment, FPDP High Adjustment */
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{ 0x03, 0x00, 0x00,
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0x03, 0x00, 0x00,
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0x04, 0x01}
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};
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/*
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* P4M890 chipset FP DPA parameters for dot clock at or above 150 MHz.
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*/
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static VIADPARec viaDPAP4M890Clock150M[] = {
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/* DVP0 Adjustment, DVP0 Clock Drive, DVP0 Data Drive,
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* DVP1 Adjustment, DVP1 Clock Drive, DVP1 Data Drive,
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* FPDP Low Adjustment, FPDP High Adjustment */
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{ 0x01, 0x02, 0x02,
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0x03, 0x00, 0x00,
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0x04, 0x0D}
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};
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/*
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* P4M890 Chipset FP DPA (Digital Panel Adjustment?) Table
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*/
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static VIADPAInfoTableRec viaDPAFPP4M890[] = {
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{ VIA_DPA_CLK_RANGE_30M, viaDPAP4M890ClockDefault},
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{ VIA_DPA_CLK_RANGE_30M_50M, viaDPAP4M890ClockDefault},
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{ VIA_DPA_CLK_RANGE_50M_70M, viaDPAP4M890Clock50M70M},
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{ VIA_DPA_CLK_RANGE_70M_100M, viaDPAP4M890Clock70M100M},
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{ VIA_DPA_CLK_RANGE_100M_150M, viaDPAP4M890Clock100M150M},
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{ VIA_DPA_CLK_RANGE_150M, viaDPAP4M890Clock150M}
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};
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/*
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* K8M890 chipset FP DPA parameters default setting.
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*/
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static VIADPARec viaDPAK8M890ClockDefault[] = {
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/* DVP0 Adjustment, DVP0 Clock Drive, DVP0 Data Drive,
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* DVP1 Adjustment, DVP1 Clock Drive, DVP1 Data Drive,
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* FPDP Low Adjustment, FPDP High Adjustment */
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{ 0x04, 0x00, 0x00,
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0x03, 0x00, 0x00,
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0x04, 0x04}
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};
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/*
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* K8M890 chipset FP DPA parameters for dot clock at or above 50 MHz
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* but below 70 MHz.
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*/
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static VIADPARec viaDPAK8M890Clock50M70M[] = {
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/* DVP0 Adjustment, DVP0 Clock Drive, DVP0 Data Drive,
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* DVP1 Adjustment, DVP1 Clock Drive, DVP1 Data Drive,
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* FPDP Low Adjustment, FPDP High Adjustment */
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{ 0x06, 0x00, 0x00,
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0x03, 0x00, 0x00,
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0x04, 0x02}
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};
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/*
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* K8M890 chipset FP DPA parameters for dot clock at or above 70 MHz
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* but below 100 MHz.
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*/
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static VIADPARec viaDPAK8M890Clock70M100M[] = {
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/* DVP0 Adjustment, DVP0 Clock Drive, DVP0 Data Drive,
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* DVP1 Adjustment, DVP1 Clock Drive, DVP1 Data Drive,
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* FPDP Low Adjustment, FPDP High Adjustment */
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{ 0x02, 0x00, 0x00,
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0x03, 0x00, 0x00,
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0x02, 0x02}
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};
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/*
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* K8M890 chipset FP DPA parameters for dot clock at or above 100 MHz
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* but below 150 MHz.
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*/
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static VIADPARec viaDPAK8M890Clock100M150M[] = {
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/* DVP0 Adjustment, DVP0 Clock Drive, DVP0 Data Drive,
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* DVP1 Adjustment, DVP1 Clock Drive, DVP1 Data Drive,
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* FPDP Low Adjustment, FPDP High Adjustment */
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{ 0x02, 0x00, 0x00,
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0x03, 0x00, 0x00,
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0x02, 0x02}
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};
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/*
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* K8M890 chipset FP DPA parameters for dot clock at or above 150 MHz.
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*/
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static VIADPARec viaDPAK8M890Clock150M[] = {
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/* DVP0 Adjustment, DVP0 Clock Drive, DVP0 Data Drive,
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* DVP1 Adjustment, DVP1 Clock Drive, DVP1 Data Drive,
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* FPDP Low Adjustment, FPDP High Adjustment */
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{ 0x03, 0x00, 0x00,
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0x03, 0x00, 0x00,
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0x02, 0x02}
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};
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/*
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* K8M890 Chipset FP DPA (Digital Panel Adjustment?) Table
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*/
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static VIADPAInfoTableRec viaDPAFPK8M890[] = {
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{ VIA_DPA_CLK_RANGE_30M, viaDPAK8M890ClockDefault},
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{ VIA_DPA_CLK_RANGE_30M_50M, viaDPAK8M890ClockDefault},
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{ VIA_DPA_CLK_RANGE_50M_70M, viaDPAK8M890Clock50M70M},
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{ VIA_DPA_CLK_RANGE_70M_100M, viaDPAK8M890Clock70M100M},
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{ VIA_DPA_CLK_RANGE_100M_150M, viaDPAK8M890Clock100M150M},
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{ VIA_DPA_CLK_RANGE_150M, viaDPAK8M890Clock150M}
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};
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/*
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* P4M900 chipset FP DPA parameters default setting.
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*/
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static VIADPARec viaDPAP4M900ClockDefault[] = {
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/* DVP0 Adjustment, DVP0 Clock Drive, DVP0 Data Drive,
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* DVP1 Adjustment, DVP1 Clock Drive, DVP1 Data Drive,
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* FPDP Low Adjustment, FPDP High Adjustment */
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{ 0x07, 0x00, 0x00,
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0x03, 0x00, 0x00,
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0x08, 0x00}
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};
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/*
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* P4M900 chipset FP DPA parameters for dot clock at or above 100 MHz
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* but below 150 MHz.
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*/
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static VIADPARec viaDPAP4M900Clock100M150M[] = {
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/* DVP0 Adjustment, DVP0 Clock Drive, DVP0 Data Drive,
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* DVP1 Adjustment, DVP1 Clock Drive, DVP1 Data Drive,
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* FPDP Low Adjustment, FPDP High Adjustment */
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{ 0x03, 0x00, 0x01,
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0x03, 0x00, 0x00,
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0x08, 0x00}
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};
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/*
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* P4M900 chipset FP DPA parameters for dot clock at or above 150 MHz.
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*/
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static VIADPARec viaDPAP4M900Clock150M[] = {
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/* DVP0 Adjustment, DVP0 Clock Drive, DVP0 Data Drive,
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* DVP1 Adjustment, DVP1 Clock Drive, DVP1 Data Drive,
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* FPDP Low Adjustment, FPDP High Adjustment */
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{ 0x01, 0x02, 0x01,
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0x03, 0x00, 0x00,
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0x08, 0x00}
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};
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/*
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* P4M900 Chipset FP DPA (Digital Panel Adjustment?) Table
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*/
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static VIADPAInfoTableRec viaDPAFPP4M900[] = {
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{ VIA_DPA_CLK_RANGE_30M, viaDPAP4M900ClockDefault},
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{ VIA_DPA_CLK_RANGE_30M_50M, viaDPAP4M900ClockDefault},
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{ VIA_DPA_CLK_RANGE_50M_70M, viaDPAP4M900ClockDefault},
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{ VIA_DPA_CLK_RANGE_70M_100M, viaDPAP4M900ClockDefault},
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{ VIA_DPA_CLK_RANGE_100M_150M, viaDPAP4M900Clock100M150M},
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{ VIA_DPA_CLK_RANGE_150M, viaDPAP4M900Clock150M}
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};
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static VIA_DPA_INDEX_TABLE viaDPAIndexTable[] = {
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// {VIA_CX700, NULL, NULL},
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{VIA_P4M890, NULL, viaDPAFPP4M890},
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{VIA_K8M890, NULL, viaDPAFPK8M890},
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{VIA_P4M900, NULL, viaDPAFPP4M900},
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// {VIA_VX800, NULL, NULL}
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};
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#endif /* _VIA_FP_H_ */
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