975 lines
32 KiB
C
975 lines
32 KiB
C
/*
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* Copyright (c) 1993-1999 NVIDIA, Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "riva_local.h"
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#include "compiler.h"
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#include "riva_include.h"
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#include "riva_hw.h"
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#include "riva_tbl.h"
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/*
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* This file is an OS-agnostic file used to make RIVA 128 and RIVA TNT
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* operate identically (except TNT has more memory and better 3D quality.
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*/
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static int nv3Busy
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(
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RIVA_HW_INST *chip
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)
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{
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return ((chip->Rop->FifoFree < chip->FifoEmptyCount) || (chip->PGRAPH[0x000006B0/4] & 0x01));
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}
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static void vgaLockUnlock
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(
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RIVA_HW_INST *chip,
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Bool Lock
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)
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{
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CARD8 cr11;
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VGA_WR08(chip->PCIO, 0x3D4, 0x11);
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cr11 = VGA_RD08(chip->PCIO, 0x3D5);
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if(Lock) cr11 |= 0x80;
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else cr11 &= ~0x80;
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VGA_WR08(chip->PCIO, 0x3D5, cr11);
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}
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static void nv3LockUnlock
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(
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RIVA_HW_INST *chip,
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Bool Lock
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)
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{
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VGA_WR08(chip->PVIO, 0x3C4, 0x06);
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VGA_WR08(chip->PVIO, 0x3C5, Lock ? 0x99 : 0x57);
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vgaLockUnlock(chip, Lock);
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}
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static int ShowHideCursor
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(
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RIVA_HW_INST *chip,
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int ShowHide
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)
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{
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int current;
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current = chip->CurrentState->cursor1;
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chip->CurrentState->cursor1 = (chip->CurrentState->cursor1 & 0xFE) |
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(ShowHide & 0x01);
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VGA_WR08(chip->PCIO, 0x3D4, 0x31);
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VGA_WR08(chip->PCIO, 0x3D5, chip->CurrentState->cursor1);
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return (current & 0x01);
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}
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/****************************************************************************\
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* *
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* The video arbitration routines calculate some "magic" numbers. Fixes *
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* the snow seen when accessing the framebuffer without it. *
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* It just works (I hope). *
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* *
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\****************************************************************************/
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#define DEFAULT_GR_LWM 100
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#define DEFAULT_VID_LWM 100
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#define DEFAULT_GR_BURST_SIZE 256
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#define DEFAULT_VID_BURST_SIZE 128
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#define VIDEO 0
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#define GRAPHICS 1
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#define MPORT 2
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#define ENGINE 3
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#define GFIFO_SIZE 320
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#define GFIFO_SIZE_128 256
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#define MFIFO_SIZE 120
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#define VFIFO_SIZE 256
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#define ABS(a) (a>0?a:-a)
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typedef struct {
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int gdrain_rate;
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int vdrain_rate;
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int mdrain_rate;
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int gburst_size;
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int vburst_size;
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char vid_en;
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char gr_en;
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int wcmocc, wcgocc, wcvocc, wcvlwm, wcglwm;
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int by_gfacc;
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char vid_only_once;
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char gr_only_once;
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char first_vacc;
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char first_gacc;
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char first_macc;
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int vocc;
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int gocc;
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int mocc;
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char cur;
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char engine_en;
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char converged;
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int priority;
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} nv3_arb_info;
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typedef struct {
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int graphics_lwm;
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int video_lwm;
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int graphics_burst_size;
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int video_burst_size;
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int graphics_hi_priority;
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int media_hi_priority;
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int rtl_values;
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int valid;
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} nv3_fifo_info;
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typedef struct {
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char pix_bpp;
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char enable_video;
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char gr_during_vid;
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char enable_mp;
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int memory_width;
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int video_scale;
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int pclk_khz;
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int mclk_khz;
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int mem_page_miss;
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int mem_latency;
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char mem_aligned;
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} nv3_sim_state;
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static int nv3_iterate(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_arb_info *ainfo)
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{
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int iter = 0;
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int tmp;
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int vfsize, mfsize, gfsize;
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int mburst_size = 32;
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int mmisses, gmisses, vmisses;
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int misses;
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int vlwm, glwm;
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int last, next, cur;
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int max_gfsize ;
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long ns;
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vlwm = 0;
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glwm = 0;
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vfsize = 0;
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gfsize = 0;
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cur = ainfo->cur;
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mmisses = 2;
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gmisses = 2;
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vmisses = 2;
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if (ainfo->gburst_size == 128) max_gfsize = GFIFO_SIZE_128;
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else max_gfsize = GFIFO_SIZE;
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max_gfsize = GFIFO_SIZE;
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while (1)
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{
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if (ainfo->vid_en)
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{
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if (ainfo->wcvocc > ainfo->vocc) ainfo->wcvocc = ainfo->vocc;
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if (ainfo->wcvlwm > vlwm) ainfo->wcvlwm = vlwm ;
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ns = 1000000 * ainfo->vburst_size/(state->memory_width/8)/state->mclk_khz;
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vfsize = ns * ainfo->vdrain_rate / 1000000;
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vfsize = ainfo->wcvlwm - ainfo->vburst_size + vfsize;
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}
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if (state->enable_mp)
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{
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if (ainfo->wcmocc > ainfo->mocc) ainfo->wcmocc = ainfo->mocc;
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}
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if (ainfo->gr_en)
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{
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if (ainfo->wcglwm > glwm) ainfo->wcglwm = glwm ;
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if (ainfo->wcgocc > ainfo->gocc) ainfo->wcgocc = ainfo->gocc;
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ns = 1000000 * (ainfo->gburst_size/(state->memory_width/8))/state->mclk_khz;
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gfsize = (ns * (long) ainfo->gdrain_rate)/1000000;
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gfsize = ainfo->wcglwm - ainfo->gburst_size + gfsize;
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}
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mfsize = 0;
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if (!state->gr_during_vid && ainfo->vid_en)
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if (ainfo->vid_en && (ainfo->vocc < 0) && !ainfo->vid_only_once)
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next = VIDEO;
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else if (ainfo->mocc < 0)
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next = MPORT;
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else if (ainfo->gocc< ainfo->by_gfacc)
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next = GRAPHICS;
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else return (0);
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else switch (ainfo->priority)
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{
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case VIDEO:
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if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once)
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next = VIDEO;
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else if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once)
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next = GRAPHICS;
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else if (ainfo->mocc<0)
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next = MPORT;
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else return (0);
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break;
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case GRAPHICS:
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if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once)
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next = GRAPHICS;
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else if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once)
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next = VIDEO;
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else if (ainfo->mocc<0)
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next = MPORT;
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else return (0);
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break;
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default:
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if (ainfo->mocc<0)
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next = MPORT;
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else if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once)
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next = GRAPHICS;
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else if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once)
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next = VIDEO;
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else return (0);
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break;
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}
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last = cur;
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cur = next;
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iter++;
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switch (cur)
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{
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case VIDEO:
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if (last==cur) misses = 0;
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else if (ainfo->first_vacc) misses = vmisses;
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else misses = 1;
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ainfo->first_vacc = 0;
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if (last!=cur)
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{
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ns = 1000000 * (vmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz;
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vlwm = ns * ainfo->vdrain_rate/ 1000000;
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vlwm = ainfo->vocc - vlwm;
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}
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ns = 1000000*(misses*state->mem_page_miss + ainfo->vburst_size)/(state->memory_width/8)/state->mclk_khz;
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ainfo->vocc = ainfo->vocc + ainfo->vburst_size - ns*ainfo->vdrain_rate/1000000;
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ainfo->gocc = ainfo->gocc - ns*ainfo->gdrain_rate/1000000;
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ainfo->mocc = ainfo->mocc - ns*ainfo->mdrain_rate/1000000;
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break;
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case GRAPHICS:
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if (last==cur) misses = 0;
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else if (ainfo->first_gacc) misses = gmisses;
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else misses = 1;
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ainfo->first_gacc = 0;
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if (last!=cur)
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{
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ns = 1000000*(gmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz ;
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glwm = ns * ainfo->gdrain_rate/1000000;
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glwm = ainfo->gocc - glwm;
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}
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ns = 1000000*(misses*state->mem_page_miss + ainfo->gburst_size/(state->memory_width/8))/state->mclk_khz;
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ainfo->vocc = ainfo->vocc + 0 - ns*ainfo->vdrain_rate/1000000;
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ainfo->gocc = ainfo->gocc + ainfo->gburst_size - ns*ainfo->gdrain_rate/1000000;
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ainfo->mocc = ainfo->mocc + 0 - ns*ainfo->mdrain_rate/1000000;
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break;
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default:
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if (last==cur) misses = 0;
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else if (ainfo->first_macc) misses = mmisses;
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else misses = 1;
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ainfo->first_macc = 0;
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ns = 1000000*(misses*state->mem_page_miss + mburst_size/(state->memory_width/8))/state->mclk_khz;
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ainfo->vocc = ainfo->vocc + 0 - ns*ainfo->vdrain_rate/1000000;
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ainfo->gocc = ainfo->gocc + 0 - ns*ainfo->gdrain_rate/1000000;
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ainfo->mocc = ainfo->mocc + mburst_size - ns*ainfo->mdrain_rate/1000000;
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break;
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}
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if (iter>100)
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{
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ainfo->converged = 0;
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return (1);
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}
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ns = 1000000*ainfo->gburst_size/(state->memory_width/8)/state->mclk_khz;
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tmp = ns * ainfo->gdrain_rate/1000000;
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if (ABS(ainfo->gburst_size) + ((ABS(ainfo->wcglwm) + 16 ) & ~0x7) - tmp > max_gfsize)
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{
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ainfo->converged = 0;
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return (1);
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}
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ns = 1000000*ainfo->vburst_size/(state->memory_width/8)/state->mclk_khz;
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tmp = ns * ainfo->vdrain_rate/1000000;
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if (ABS(ainfo->vburst_size) + (ABS(ainfo->wcvlwm + 32) & ~0xf) - tmp> VFIFO_SIZE)
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{
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ainfo->converged = 0;
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return (1);
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}
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if (ABS(ainfo->gocc) > max_gfsize)
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{
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ainfo->converged = 0;
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return (1);
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}
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if (ABS(ainfo->vocc) > VFIFO_SIZE)
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{
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ainfo->converged = 0;
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return (1);
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}
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if (ABS(ainfo->mocc) > MFIFO_SIZE)
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{
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ainfo->converged = 0;
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return (1);
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}
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if (ABS(vfsize) > VFIFO_SIZE)
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{
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ainfo->converged = 0;
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return (1);
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}
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if (ABS(gfsize) > max_gfsize)
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{
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ainfo->converged = 0;
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return (1);
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}
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if (ABS(mfsize) > MFIFO_SIZE)
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{
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ainfo->converged = 0;
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return (1);
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}
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}
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}
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static char nv3_arb(nv3_fifo_info * res_info, nv3_sim_state * state, nv3_arb_info *ainfo)
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{
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long ens, vns, mns, gns;
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int mmisses, gmisses, vmisses, eburst_size, mburst_size;
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int refresh_cycle;
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refresh_cycle = 0;
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refresh_cycle = 2*(state->mclk_khz/state->pclk_khz) + 5;
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mmisses = 2;
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if (state->mem_aligned) gmisses = 2;
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else gmisses = 3;
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vmisses = 2;
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eburst_size = state->memory_width * 1;
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mburst_size = 32;
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gns = 1000000 * (gmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz;
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ainfo->by_gfacc = gns*ainfo->gdrain_rate/1000000;
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ainfo->wcmocc = 0;
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ainfo->wcgocc = 0;
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ainfo->wcvocc = 0;
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ainfo->wcvlwm = 0;
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ainfo->wcglwm = 0;
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ainfo->engine_en = 1;
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ainfo->converged = 1;
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if (ainfo->engine_en)
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{
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ens = 1000000*(state->mem_page_miss + eburst_size/(state->memory_width/8) +refresh_cycle)/state->mclk_khz;
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ainfo->mocc = state->enable_mp ? 0-ens*ainfo->mdrain_rate/1000000 : 0;
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ainfo->vocc = ainfo->vid_en ? 0-ens*ainfo->vdrain_rate/1000000 : 0;
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ainfo->gocc = ainfo->gr_en ? 0-ens*ainfo->gdrain_rate/1000000 : 0;
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ainfo->cur = ENGINE;
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ainfo->first_vacc = 1;
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ainfo->first_gacc = 1;
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ainfo->first_macc = 1;
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nv3_iterate(res_info, state,ainfo);
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}
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if (state->enable_mp)
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{
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mns = 1000000 * (mmisses*state->mem_page_miss + mburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz;
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ainfo->mocc = state->enable_mp ? 0 : mburst_size - mns*ainfo->mdrain_rate/1000000;
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ainfo->vocc = ainfo->vid_en ? 0 : 0- mns*ainfo->vdrain_rate/1000000;
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ainfo->gocc = ainfo->gr_en ? 0: 0- mns*ainfo->gdrain_rate/1000000;
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ainfo->cur = MPORT;
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ainfo->first_vacc = 1;
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ainfo->first_gacc = 1;
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ainfo->first_macc = 0;
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nv3_iterate(res_info, state,ainfo);
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}
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if (ainfo->gr_en)
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{
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ainfo->first_vacc = 1;
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ainfo->first_gacc = 0;
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ainfo->first_macc = 1;
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gns = 1000000*(gmisses*state->mem_page_miss + ainfo->gburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz;
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ainfo->gocc = ainfo->gburst_size - gns*ainfo->gdrain_rate/1000000;
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ainfo->vocc = ainfo->vid_en? 0-gns*ainfo->vdrain_rate/1000000 : 0;
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ainfo->mocc = state->enable_mp ? 0-gns*ainfo->mdrain_rate/1000000: 0;
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ainfo->cur = GRAPHICS;
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nv3_iterate(res_info, state,ainfo);
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}
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if (ainfo->vid_en)
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{
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ainfo->first_vacc = 0;
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ainfo->first_gacc = 1;
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ainfo->first_macc = 1;
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vns = 1000000*(vmisses*state->mem_page_miss + ainfo->vburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz;
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ainfo->vocc = ainfo->vburst_size - vns*ainfo->vdrain_rate/1000000;
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ainfo->gocc = ainfo->gr_en? (0-vns*ainfo->gdrain_rate/1000000) : 0;
|
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ainfo->mocc = state->enable_mp? 0-vns*ainfo->mdrain_rate/1000000 :0 ;
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ainfo->cur = VIDEO;
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nv3_iterate(res_info, state, ainfo);
|
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}
|
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if (ainfo->converged)
|
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{
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res_info->graphics_lwm = (int)ABS(ainfo->wcglwm) + 16;
|
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res_info->video_lwm = (int)ABS(ainfo->wcvlwm) + 32;
|
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res_info->graphics_burst_size = ainfo->gburst_size;
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res_info->video_burst_size = ainfo->vburst_size;
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res_info->graphics_hi_priority = (ainfo->priority == GRAPHICS);
|
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res_info->media_hi_priority = (ainfo->priority == MPORT);
|
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if (res_info->video_lwm > 160)
|
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{
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res_info->graphics_lwm = 256;
|
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res_info->video_lwm = 128;
|
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res_info->graphics_burst_size = 64;
|
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res_info->video_burst_size = 64;
|
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res_info->graphics_hi_priority = 0;
|
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res_info->media_hi_priority = 0;
|
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ainfo->converged = 0;
|
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return (0);
|
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}
|
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if (res_info->video_lwm > 128)
|
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{
|
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res_info->video_lwm = 128;
|
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}
|
|
return (1);
|
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}
|
|
else
|
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{
|
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res_info->graphics_lwm = 256;
|
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res_info->video_lwm = 128;
|
|
res_info->graphics_burst_size = 64;
|
|
res_info->video_burst_size = 64;
|
|
res_info->graphics_hi_priority = 0;
|
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res_info->media_hi_priority = 0;
|
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return (0);
|
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}
|
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}
|
|
static char nv3_get_param(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_arb_info *ainfo)
|
|
{
|
|
int done, g,v, p;
|
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|
|
done = 0;
|
|
for (p=0; p < 2; p++)
|
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{
|
|
for (g=128 ; g > 32; g= g>> 1)
|
|
{
|
|
for (v=128; v >=32; v = v>> 1)
|
|
{
|
|
ainfo->priority = p;
|
|
ainfo->gburst_size = g;
|
|
ainfo->vburst_size = v;
|
|
done = nv3_arb(res_info, state,ainfo);
|
|
if (done && (g==128))
|
|
if ((res_info->graphics_lwm + g) > 256)
|
|
done = 0;
|
|
if (done)
|
|
goto Done;
|
|
}
|
|
}
|
|
}
|
|
|
|
Done:
|
|
return done;
|
|
}
|
|
static void nv3CalcArbitration
|
|
(
|
|
nv3_fifo_info * res_info,
|
|
nv3_sim_state * state
|
|
)
|
|
{
|
|
nv3_fifo_info save_info;
|
|
nv3_arb_info ainfo;
|
|
char res_gr, res_vid;
|
|
|
|
ainfo.gr_en = 1;
|
|
ainfo.vid_en = state->enable_video;
|
|
ainfo.vid_only_once = 0;
|
|
ainfo.gr_only_once = 0;
|
|
ainfo.gdrain_rate = (int) state->pclk_khz * (state->pix_bpp/8);
|
|
ainfo.vdrain_rate = (int) state->pclk_khz * 2;
|
|
if (state->video_scale != 0)
|
|
ainfo.vdrain_rate = ainfo.vdrain_rate/state->video_scale;
|
|
ainfo.mdrain_rate = 33000;
|
|
res_info->rtl_values = 0;
|
|
if (!state->gr_during_vid && state->enable_video)
|
|
{
|
|
ainfo.gr_only_once = 1;
|
|
ainfo.gr_en = 1;
|
|
ainfo.gdrain_rate = 0;
|
|
res_vid = nv3_get_param(res_info, state, &ainfo);
|
|
res_vid = ainfo.converged;
|
|
save_info.video_lwm = res_info->video_lwm;
|
|
save_info.video_burst_size = res_info->video_burst_size;
|
|
ainfo.vid_en = 1;
|
|
ainfo.vid_only_once = 1;
|
|
ainfo.gr_en = 1;
|
|
ainfo.gdrain_rate = (int) state->pclk_khz * (state->pix_bpp/8);
|
|
ainfo.vdrain_rate = 0;
|
|
res_gr = nv3_get_param(res_info, state, &ainfo);
|
|
res_gr = ainfo.converged;
|
|
res_info->video_lwm = save_info.video_lwm;
|
|
res_info->video_burst_size = save_info.video_burst_size;
|
|
res_info->valid = res_gr & res_vid;
|
|
}
|
|
else
|
|
{
|
|
if (!ainfo.gr_en) ainfo.gdrain_rate = 0;
|
|
if (!ainfo.vid_en) ainfo.vdrain_rate = 0;
|
|
res_gr = nv3_get_param(res_info, state, &ainfo);
|
|
res_info->valid = ainfo.converged;
|
|
}
|
|
}
|
|
static void nv3UpdateArbitrationSettings
|
|
(
|
|
unsigned VClk,
|
|
unsigned pixelDepth,
|
|
unsigned *burst,
|
|
unsigned *lwm,
|
|
RIVA_HW_INST *chip
|
|
)
|
|
{
|
|
nv3_fifo_info fifo_data;
|
|
nv3_sim_state sim_data;
|
|
unsigned int M, N, P, pll, MClk;
|
|
|
|
pll = chip->PRAMDAC[0x00000504/4];
|
|
M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
|
|
MClk = (N * chip->CrystalFreqKHz / M) >> P;
|
|
sim_data.pix_bpp = (char)pixelDepth;
|
|
sim_data.enable_video = 0;
|
|
sim_data.enable_mp = 0;
|
|
sim_data.video_scale = 1;
|
|
sim_data.memory_width = (chip->PEXTDEV[0x00000000/4] & 0x10) ? 128 : 64;
|
|
sim_data.memory_width = 128;
|
|
|
|
sim_data.mem_latency = 9;
|
|
sim_data.mem_aligned = 1;
|
|
sim_data.mem_page_miss = 11;
|
|
sim_data.gr_during_vid = 0;
|
|
sim_data.pclk_khz = VClk;
|
|
sim_data.mclk_khz = MClk;
|
|
nv3CalcArbitration(&fifo_data, &sim_data);
|
|
if (fifo_data.valid)
|
|
{
|
|
int b = fifo_data.graphics_burst_size >> 4;
|
|
*burst = 0;
|
|
while (b >>= 1) (*burst)++;
|
|
*lwm = fifo_data.graphics_lwm >> 3;
|
|
}
|
|
else
|
|
{
|
|
*lwm = 0x24;
|
|
*burst = 0x2;
|
|
}
|
|
}
|
|
|
|
/****************************************************************************\
|
|
* *
|
|
* RIVA Mode State Routines *
|
|
* *
|
|
\****************************************************************************/
|
|
|
|
/*
|
|
* Calculate the Video Clock parameters for the PLL.
|
|
*/
|
|
static int CalcVClock
|
|
(
|
|
int clockIn,
|
|
int *clockOut,
|
|
int *mOut,
|
|
int *nOut,
|
|
int *pOut,
|
|
RIVA_HW_INST *chip
|
|
)
|
|
{
|
|
unsigned lowM, highM, highP;
|
|
unsigned DeltaNew, DeltaOld;
|
|
unsigned VClk, Freq;
|
|
unsigned M, N, P;
|
|
|
|
DeltaOld = 0xFFFFFFFF;
|
|
|
|
VClk = (unsigned)clockIn;
|
|
|
|
if (chip->CrystalFreqKHz == 13500)
|
|
{
|
|
lowM = 7;
|
|
highM = 12;
|
|
}
|
|
else
|
|
{
|
|
lowM = 8;
|
|
highM = 13;
|
|
}
|
|
|
|
highP = 3;
|
|
for (P = 0; P <= highP; P ++)
|
|
{
|
|
Freq = VClk << P;
|
|
if ((Freq >= 128000) && (Freq <= chip->MaxVClockFreqKHz))
|
|
{
|
|
for (M = lowM; M <= highM; M++)
|
|
{
|
|
N = (VClk << P) * M / chip->CrystalFreqKHz;
|
|
if(N <= 255) {
|
|
Freq = (chip->CrystalFreqKHz * N / M) >> P;
|
|
if (Freq > VClk)
|
|
DeltaNew = Freq - VClk;
|
|
else
|
|
DeltaNew = VClk - Freq;
|
|
if (DeltaNew < DeltaOld)
|
|
{
|
|
*mOut = M;
|
|
*nOut = N;
|
|
*pOut = P;
|
|
*clockOut = Freq;
|
|
DeltaOld = DeltaNew;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
return (DeltaOld != 0xFFFFFFFF);
|
|
}
|
|
/*
|
|
* Calculate extended mode parameters (SVGA) and save in a
|
|
* mode state structure.
|
|
*/
|
|
static void CalcStateExt
|
|
(
|
|
RIVA_HW_INST *chip,
|
|
RIVA_HW_STATE *state,
|
|
int bpp,
|
|
int width,
|
|
int hDisplaySize,
|
|
int height,
|
|
int dotClock,
|
|
int flags
|
|
)
|
|
{
|
|
int pixelDepth, VClk = 0, m = 0, n = 0, p = 0;
|
|
/*
|
|
* Save mode parameters.
|
|
*/
|
|
state->bpp = bpp; /* this is not bitsPerPixel, it's 8,15,16,32 */
|
|
state->width = width;
|
|
state->height = height;
|
|
/*
|
|
* Extended RIVA registers.
|
|
*/
|
|
pixelDepth = (bpp + 1)/8;
|
|
CalcVClock(dotClock, &VClk, &m, &n, &p, chip);
|
|
|
|
nv3UpdateArbitrationSettings(VClk,
|
|
pixelDepth * 8,
|
|
&(state->arbitration0),
|
|
&(state->arbitration1),
|
|
chip);
|
|
state->cursor0 = 0x00;
|
|
state->cursor1 = 0x78;
|
|
if (flags & V_DBLSCAN)
|
|
state->cursor1 |= 2;
|
|
state->cursor2 = 0x00000000;
|
|
state->pllsel = 0x10010100;
|
|
state->config = ((width + 31)/32)
|
|
| (((pixelDepth > 2) ? 3 : pixelDepth) << 8)
|
|
| 0x1000;
|
|
state->general = 0x00100100;
|
|
state->repaint1 = hDisplaySize < 1280 ? 0x06 : 0x02;
|
|
|
|
|
|
state->vpll = (p << 16) | (n << 8) | m;
|
|
state->repaint0 = (((width/8)*pixelDepth) & 0x700) >> 3;
|
|
state->pixel = pixelDepth > 2 ? 3 : pixelDepth;
|
|
state->offset = 0;
|
|
state->pitch = pixelDepth * width;
|
|
}
|
|
/*
|
|
* Load fixed function state and pre-calculated/stored state.
|
|
*/
|
|
#define LOAD_FIXED_STATE(tbl,dev) \
|
|
for (i = 0; i < sizeof(tbl##Table##dev)/8; i++) \
|
|
chip->dev[tbl##Table##dev[i][0]] = tbl##Table##dev[i][1]
|
|
#define LOAD_FIXED_STATE_8BPP(tbl,dev) \
|
|
for (i = 0; i < sizeof(tbl##Table##dev##_8BPP)/8; i++) \
|
|
chip->dev[tbl##Table##dev##_8BPP[i][0]] = tbl##Table##dev##_8BPP[i][1]
|
|
#define LOAD_FIXED_STATE_15BPP(tbl,dev) \
|
|
for (i = 0; i < sizeof(tbl##Table##dev##_15BPP)/8; i++) \
|
|
chip->dev[tbl##Table##dev##_15BPP[i][0]] = tbl##Table##dev##_15BPP[i][1]
|
|
#define LOAD_FIXED_STATE_16BPP(tbl,dev) \
|
|
for (i = 0; i < sizeof(tbl##Table##dev##_16BPP)/8; i++) \
|
|
chip->dev[tbl##Table##dev##_16BPP[i][0]] = tbl##Table##dev##_16BPP[i][1]
|
|
#define LOAD_FIXED_STATE_32BPP(tbl,dev) \
|
|
for (i = 0; i < sizeof(tbl##Table##dev##_32BPP)/8; i++) \
|
|
chip->dev[tbl##Table##dev##_32BPP[i][0]] = tbl##Table##dev##_32BPP[i][1]
|
|
static void UpdateFifoState
|
|
(
|
|
RIVA_HW_INST *chip
|
|
)
|
|
{
|
|
}
|
|
static void LoadStateExt
|
|
(
|
|
RIVA_HW_INST *chip,
|
|
RIVA_HW_STATE *state
|
|
)
|
|
{
|
|
int i;
|
|
|
|
/*
|
|
* Load HW fixed function state.
|
|
*/
|
|
LOAD_FIXED_STATE(Riva,PMC);
|
|
LOAD_FIXED_STATE(Riva,PTIMER);
|
|
/*
|
|
* Make sure frame buffer config gets set before loading PRAMIN.
|
|
*/
|
|
chip->PFB[0x00000200/4] = state->config;
|
|
LOAD_FIXED_STATE(nv3,PFIFO);
|
|
LOAD_FIXED_STATE(nv3,PRAMIN);
|
|
LOAD_FIXED_STATE(nv3,PGRAPH);
|
|
switch (state->bpp)
|
|
{
|
|
case 15:
|
|
case 16:
|
|
LOAD_FIXED_STATE_15BPP(nv3,PRAMIN);
|
|
LOAD_FIXED_STATE_15BPP(nv3,PGRAPH);
|
|
break;
|
|
case 24:
|
|
case 32:
|
|
LOAD_FIXED_STATE_32BPP(nv3,PRAMIN);
|
|
LOAD_FIXED_STATE_32BPP(nv3,PGRAPH);
|
|
break;
|
|
case 8:
|
|
default:
|
|
LOAD_FIXED_STATE_8BPP(nv3,PRAMIN);
|
|
LOAD_FIXED_STATE_8BPP(nv3,PGRAPH);
|
|
break;
|
|
}
|
|
for (i = 0x00000; i < 0x00800; i++)
|
|
chip->PRAMIN[0x00000502 + i] = (i << 12) | 0x03;
|
|
chip->PGRAPH[0x00000630/4] = state->offset;
|
|
chip->PGRAPH[0x00000634/4] = state->offset;
|
|
chip->PGRAPH[0x00000638/4] = state->offset;
|
|
chip->PGRAPH[0x0000063C/4] = state->offset;
|
|
chip->PGRAPH[0x00000650/4] = state->pitch;
|
|
chip->PGRAPH[0x00000654/4] = state->pitch;
|
|
chip->PGRAPH[0x00000658/4] = state->pitch;
|
|
chip->PGRAPH[0x0000065C/4] = state->pitch;
|
|
|
|
LOAD_FIXED_STATE(Riva,FIFO);
|
|
UpdateFifoState(chip);
|
|
|
|
/*
|
|
* Load HW mode state.
|
|
*/
|
|
VGA_WR08(chip->PCIO, 0x03D4, 0x19);
|
|
VGA_WR08(chip->PCIO, 0x03D5, state->repaint0);
|
|
VGA_WR08(chip->PCIO, 0x03D4, 0x1A);
|
|
VGA_WR08(chip->PCIO, 0x03D5, state->repaint1);
|
|
VGA_WR08(chip->PCIO, 0x03D4, 0x25);
|
|
VGA_WR08(chip->PCIO, 0x03D5, state->screen);
|
|
VGA_WR08(chip->PCIO, 0x03D4, 0x28);
|
|
VGA_WR08(chip->PCIO, 0x03D5, state->pixel);
|
|
VGA_WR08(chip->PCIO, 0x03D4, 0x2D);
|
|
VGA_WR08(chip->PCIO, 0x03D5, state->horiz);
|
|
VGA_WR08(chip->PCIO, 0x03D4, 0x1B);
|
|
VGA_WR08(chip->PCIO, 0x03D5, state->arbitration0);
|
|
VGA_WR08(chip->PCIO, 0x03D4, 0x20);
|
|
VGA_WR08(chip->PCIO, 0x03D5, state->arbitration1);
|
|
VGA_WR08(chip->PCIO, 0x03D4, 0x30);
|
|
VGA_WR08(chip->PCIO, 0x03D5, state->cursor0);
|
|
VGA_WR08(chip->PCIO, 0x03D4, 0x31);
|
|
VGA_WR08(chip->PCIO, 0x03D5, state->cursor1);
|
|
VGA_WR08(chip->PCIO, 0x03D4, 0x2F);
|
|
VGA_WR08(chip->PCIO, 0x03D5, state->cursor2);
|
|
VGA_WR08(chip->PCIO, 0x03D4, 0x39);
|
|
VGA_WR08(chip->PCIO, 0x03D5, state->interlace);
|
|
|
|
chip->PRAMDAC[0x00000508/4] = state->vpll;
|
|
chip->PRAMDAC[0x0000050C/4] = state->pllsel;
|
|
chip->PRAMDAC[0x00000600/4] = state->general;
|
|
|
|
/*
|
|
* Turn off VBlank enable and reset.
|
|
*/
|
|
chip->PCRTC[0x00000140/4] = 0;
|
|
chip->PCRTC[0x00000100/4] = chip->VBlankBit;
|
|
/*
|
|
* Set interrupt enable.
|
|
*/
|
|
chip->PMC[0x00000140/4] = chip->EnableIRQ & 0x01;
|
|
/*
|
|
* Set current state pointer.
|
|
*/
|
|
chip->CurrentState = state;
|
|
/*
|
|
* Reset FIFO free and empty counts.
|
|
*/
|
|
chip->FifoFreeCount = 0;
|
|
/* Free count from first subchannel */
|
|
chip->FifoEmptyCount = chip->Rop->FifoFree;
|
|
}
|
|
|
|
static void UnloadStateExt
|
|
(
|
|
RIVA_HW_INST *chip,
|
|
RIVA_HW_STATE *state
|
|
)
|
|
{
|
|
/*
|
|
* Save current HW state.
|
|
*/
|
|
VGA_WR08(chip->PCIO, 0x03D4, 0x19);
|
|
state->repaint0 = VGA_RD08(chip->PCIO, 0x03D5);
|
|
VGA_WR08(chip->PCIO, 0x03D4, 0x1A);
|
|
state->repaint1 = VGA_RD08(chip->PCIO, 0x03D5);
|
|
VGA_WR08(chip->PCIO, 0x03D4, 0x25);
|
|
state->screen = VGA_RD08(chip->PCIO, 0x03D5);
|
|
VGA_WR08(chip->PCIO, 0x03D4, 0x28);
|
|
state->pixel = VGA_RD08(chip->PCIO, 0x03D5);
|
|
VGA_WR08(chip->PCIO, 0x03D4, 0x2D);
|
|
state->horiz = VGA_RD08(chip->PCIO, 0x03D5);
|
|
VGA_WR08(chip->PCIO, 0x03D4, 0x1B);
|
|
state->arbitration0 = VGA_RD08(chip->PCIO, 0x03D5);
|
|
VGA_WR08(chip->PCIO, 0x03D4, 0x20);
|
|
state->arbitration1 = VGA_RD08(chip->PCIO, 0x03D5);
|
|
VGA_WR08(chip->PCIO, 0x03D4, 0x30);
|
|
state->cursor0 = VGA_RD08(chip->PCIO, 0x03D5);
|
|
VGA_WR08(chip->PCIO, 0x03D4, 0x31);
|
|
state->cursor1 = VGA_RD08(chip->PCIO, 0x03D5);
|
|
VGA_WR08(chip->PCIO, 0x03D4, 0x2F);
|
|
state->cursor2 = VGA_RD08(chip->PCIO, 0x03D5);
|
|
VGA_WR08(chip->PCIO, 0x03D4, 0x39);
|
|
state->interlace = VGA_RD08(chip->PCIO, 0x03D5);
|
|
state->vpll = chip->PRAMDAC[0x00000508/4];
|
|
state->pllsel = chip->PRAMDAC[0x0000050C/4];
|
|
state->general = chip->PRAMDAC[0x00000600/4];
|
|
state->config = chip->PFB[0x00000200/4];
|
|
state->offset = chip->PGRAPH[0x00000630/4];
|
|
state->pitch = chip->PGRAPH[0x00000650/4];
|
|
}
|
|
|
|
static void SetStartAddress
|
|
(
|
|
RIVA_HW_INST *chip,
|
|
unsigned start
|
|
)
|
|
{
|
|
int offset = start >> 2;
|
|
int pan = (start & 3) << 1;
|
|
unsigned char tmp;
|
|
|
|
/*
|
|
* Unlock extended registers.
|
|
*/
|
|
chip->LockUnlock(chip, 0);
|
|
/*
|
|
* Set start address.
|
|
*/
|
|
VGA_WR08(chip->PCIO, 0x3D4, 0x0D); VGA_WR08(chip->PCIO, 0x3D5, offset);
|
|
offset >>= 8;
|
|
VGA_WR08(chip->PCIO, 0x3D4, 0x0C); VGA_WR08(chip->PCIO, 0x3D5, offset);
|
|
offset >>= 8;
|
|
VGA_WR08(chip->PCIO, 0x3D4, 0x19); tmp = VGA_RD08(chip->PCIO, 0x3D5);
|
|
VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x01F) | (tmp & ~0x1F));
|
|
VGA_WR08(chip->PCIO, 0x3D4, 0x2D); tmp = VGA_RD08(chip->PCIO, 0x3D5);
|
|
VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x60) | (tmp & ~0x60));
|
|
/*
|
|
* 4 pixel pan register.
|
|
*/
|
|
offset = VGA_RD08(chip->PCIO, chip->IO + 0x0A);
|
|
VGA_WR08(chip->PCIO, 0x3C0, 0x13);
|
|
VGA_WR08(chip->PCIO, 0x3C0, pan);
|
|
}
|
|
/****************************************************************************\
|
|
* *
|
|
* Probe RIVA Chip Configuration *
|
|
* *
|
|
\****************************************************************************/
|
|
|
|
static void nv3GetConfig
|
|
(
|
|
RIVA_HW_INST *chip
|
|
)
|
|
{
|
|
/*
|
|
* Fill in chip configuration.
|
|
*/
|
|
if (chip->PFB[0x00000000/4] & 0x00000020)
|
|
{
|
|
if (((chip->PMC[0x00000000/4] & 0xF0) == 0x20)
|
|
&& ((chip->PMC[0x00000000/4] & 0x0F) >= 0x02))
|
|
{
|
|
/*
|
|
* SDRAM 128 ZX.
|
|
*/
|
|
chip->RamBandwidthKBytesPerSec = 800000;
|
|
switch (chip->PFB[0x00000000/4] & 0x03)
|
|
{
|
|
case 2:
|
|
chip->RamAmountKBytes = 1024 * 4;
|
|
break;
|
|
case 1:
|
|
chip->RamAmountKBytes = 1024 * 2;
|
|
break;
|
|
default:
|
|
chip->RamAmountKBytes = 1024 * 8;
|
|
break;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
chip->RamBandwidthKBytesPerSec = 1000000;
|
|
chip->RamAmountKBytes = 1024 * 8;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/*
|
|
* SGRAM 128.
|
|
*/
|
|
chip->RamBandwidthKBytesPerSec = 1000000;
|
|
switch (chip->PFB[0x00000000/4] & 0x00000003)
|
|
{
|
|
case 0:
|
|
chip->RamAmountKBytes = 1024 * 8;
|
|
break;
|
|
case 2:
|
|
chip->RamAmountKBytes = 1024 * 4;
|
|
break;
|
|
default:
|
|
chip->RamAmountKBytes = 1024 * 2;
|
|
break;
|
|
}
|
|
}
|
|
chip->CrystalFreqKHz = (chip->PEXTDEV[0x00000000/4] & 0x00000040) ? 14318 : 13500;
|
|
chip->CURSOR = &(chip->PRAMIN[0x00008000/4 - 0x0800/4]);
|
|
chip->VBlankBit = 0x00000100;
|
|
chip->MaxVClockFreqKHz = 256000;
|
|
/*
|
|
* Set chip functions.
|
|
*/
|
|
chip->Busy = nv3Busy;
|
|
chip->ShowHideCursor = ShowHideCursor;
|
|
chip->CalcStateExt = CalcStateExt;
|
|
chip->LoadStateExt = LoadStateExt;
|
|
chip->UnloadStateExt = UnloadStateExt;
|
|
chip->SetStartAddress = SetStartAddress;
|
|
chip->LockUnlock = nv3LockUnlock;
|
|
}
|
|
int RivaGetConfig
|
|
(
|
|
RivaPtr pRiva
|
|
)
|
|
{
|
|
RIVA_HW_INST *chip = &pRiva->riva;
|
|
|
|
nv3GetConfig(chip);
|
|
/*
|
|
* Fill in FIFO pointers.
|
|
*/
|
|
chip->Rop = (RivaRop *)&(chip->FIFO[0x00000000/4]);
|
|
chip->Clip = (RivaClip *)&(chip->FIFO[0x00002000/4]);
|
|
chip->Patt = (RivaPattern *)&(chip->FIFO[0x00004000/4]);
|
|
chip->Pixmap = (RivaPixmap *)&(chip->FIFO[0x00006000/4]);
|
|
chip->Blt = (RivaScreenBlt *)&(chip->FIFO[0x00008000/4]);
|
|
chip->Bitmap = (RivaBitmap *)&(chip->FIFO[0x0000A000/4]);
|
|
chip->Line = (RivaLine *)&(chip->FIFO[0x0000C000/4]);
|
|
return (0);
|
|
}
|