sync with OpenBSD -current
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53 changed files with 2169 additions and 443 deletions
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@ -94,6 +94,9 @@ extern "C" {
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*
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* %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines
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* for appending data.
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*
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* %AMDGPU_GEM_DOMAIN_DOORBELL Doorbell. It is an MMIO region for
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* signalling user mode queues.
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*/
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#define AMDGPU_GEM_DOMAIN_CPU 0x1
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#define AMDGPU_GEM_DOMAIN_GTT 0x2
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@ -101,12 +104,14 @@ extern "C" {
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#define AMDGPU_GEM_DOMAIN_GDS 0x8
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#define AMDGPU_GEM_DOMAIN_GWS 0x10
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#define AMDGPU_GEM_DOMAIN_OA 0x20
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#define AMDGPU_GEM_DOMAIN_DOORBELL 0x40
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#define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \
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AMDGPU_GEM_DOMAIN_GTT | \
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AMDGPU_GEM_DOMAIN_VRAM | \
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AMDGPU_GEM_DOMAIN_GDS | \
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AMDGPU_GEM_DOMAIN_GWS | \
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AMDGPU_GEM_DOMAIN_OA)
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AMDGPU_GEM_DOMAIN_OA | \
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AMDGPU_GEM_DOMAIN_DOORBELL)
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/* Flag that CPU access will be required for the case of VRAM domain */
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#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
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@ -140,6 +145,32 @@ extern "C" {
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* not require GTT memory accounting
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*/
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#define AMDGPU_GEM_CREATE_PREEMPTIBLE (1 << 11)
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/* Flag that BO can be discarded under memory pressure without keeping the
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* content.
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*/
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#define AMDGPU_GEM_CREATE_DISCARDABLE (1 << 12)
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/* Flag that BO is shared coherently between multiple devices or CPU threads.
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* May depend on GPU instructions to flush caches to system scope explicitly.
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*
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* This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and
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* may override the MTYPE selected in AMDGPU_VA_OP_MAP.
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*/
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#define AMDGPU_GEM_CREATE_COHERENT (1 << 13)
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/* Flag that BO should not be cached by GPU. Coherent without having to flush
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* GPU caches explicitly
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*
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* This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and
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* may override the MTYPE selected in AMDGPU_VA_OP_MAP.
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*/
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#define AMDGPU_GEM_CREATE_UNCACHED (1 << 14)
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/* Flag that BO should be coherent across devices when using device-level
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* atomics. May depend on GPU instructions to flush caches to device scope
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* explicitly, promoting them to system scope automatically.
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*
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* This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and
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* may override the MTYPE selected in AMDGPU_VA_OP_MAP.
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*/
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#define AMDGPU_GEM_CREATE_EXT_COHERENT (1 << 15)
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struct drm_amdgpu_gem_create_in {
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/** the requested memory size */
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@ -218,15 +249,17 @@ union drm_amdgpu_bo_list {
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/* unknown cause */
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#define AMDGPU_CTX_UNKNOWN_RESET 3
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/* indicate gpu reset occured after ctx created */
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/* indicate gpu reset occurred after ctx created */
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#define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0)
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/* indicate vram lost occured after ctx created */
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/* indicate vram lost occurred after ctx created */
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#define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1)
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/* indicate some job from this context once cause gpu hang */
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#define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2)
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/* indicate some errors are detected by RAS */
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#define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3)
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#define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4)
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/* indicate that the reset hasn't completed yet */
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#define AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS (1<<5)
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/* Context priority level */
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#define AMDGPU_CTX_PRIORITY_UNSET -2048
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@ -529,6 +562,8 @@ struct drm_amdgpu_gem_op {
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#define AMDGPU_VM_MTYPE_UC (4 << 5)
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/* Use Read Write MTYPE instead of default MTYPE */
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#define AMDGPU_VM_MTYPE_RW (5 << 5)
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/* don't allocate MALL */
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#define AMDGPU_VM_PAGE_NOALLOC (1 << 9)
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struct drm_amdgpu_gem_va {
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/** GEM object handle */
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@ -559,7 +594,8 @@ struct drm_amdgpu_gem_va {
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*/
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#define AMDGPU_HW_IP_VCN_ENC 7
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#define AMDGPU_HW_IP_VCN_JPEG 8
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#define AMDGPU_HW_IP_NUM 9
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#define AMDGPU_HW_IP_VPE 9
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#define AMDGPU_HW_IP_NUM 10
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#define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
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@ -572,6 +608,7 @@ struct drm_amdgpu_gem_va {
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#define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07
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#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08
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#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09
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#define AMDGPU_CHUNK_ID_CP_GFX_SHADOW 0x0a
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struct drm_amdgpu_cs_chunk {
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__u32 chunk_id;
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@ -688,6 +725,15 @@ struct drm_amdgpu_cs_chunk_data {
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};
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};
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#define AMDGPU_CS_CHUNK_CP_GFX_SHADOW_FLAGS_INIT_SHADOW 0x1
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struct drm_amdgpu_cs_chunk_cp_gfx_shadow {
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__u64 shadow_va;
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__u64 csa_va;
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__u64 gds_va;
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__u64 flags;
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};
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/*
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* Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU
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*
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@ -695,6 +741,7 @@ struct drm_amdgpu_cs_chunk_data {
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#define AMDGPU_IDS_FLAGS_FUSION 0x1
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#define AMDGPU_IDS_FLAGS_PREEMPTION 0x2
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#define AMDGPU_IDS_FLAGS_TMZ 0x4
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#define AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD 0x8
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/* indicate if acceleration can be working */
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#define AMDGPU_INFO_ACCEL_WORKING 0x00
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@ -747,6 +794,20 @@ struct drm_amdgpu_cs_chunk_data {
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#define AMDGPU_INFO_FW_DMCUB 0x14
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/* Subquery id: Query TOC firmware version */
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#define AMDGPU_INFO_FW_TOC 0x15
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/* Subquery id: Query CAP firmware version */
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#define AMDGPU_INFO_FW_CAP 0x16
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/* Subquery id: Query GFX RLCP firmware version */
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#define AMDGPU_INFO_FW_GFX_RLCP 0x17
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/* Subquery id: Query GFX RLCV firmware version */
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#define AMDGPU_INFO_FW_GFX_RLCV 0x18
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/* Subquery id: Query MES_KIQ firmware version */
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#define AMDGPU_INFO_FW_MES_KIQ 0x19
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/* Subquery id: Query MES firmware version */
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#define AMDGPU_INFO_FW_MES 0x1a
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/* Subquery id: Query IMU firmware version */
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#define AMDGPU_INFO_FW_IMU 0x1b
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/* Subquery id: Query VPE firmware version */
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#define AMDGPU_INFO_FW_VPE 0x1c
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/* number of bytes moved for TTM migration */
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#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
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@ -800,6 +861,10 @@ struct drm_amdgpu_cs_chunk_data {
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#define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8
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/* Subquery id: Query GPU stable pstate memory clock */
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#define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9
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/* Subquery id: Query GPU peak pstate shader clock */
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#define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK 0xa
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/* Subquery id: Query GPU peak pstate memory clock */
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#define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK 0xb
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/* Number of VRAM page faults on CPU access. */
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#define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E
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#define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F
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@ -839,6 +904,10 @@ struct drm_amdgpu_cs_chunk_data {
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#define AMDGPU_INFO_VIDEO_CAPS_DECODE 0
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/* Subquery id: Encode */
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#define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1
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/* Query the max number of IBs per gang per submission */
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#define AMDGPU_INFO_MAX_IBS 0x22
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/* query last page fault info */
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#define AMDGPU_INFO_GPUVM_FAULT 0x23
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#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
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#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
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@ -990,6 +1059,8 @@ struct drm_amdgpu_info_vbios {
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#define AMDGPU_VRAM_TYPE_DDR4 8
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#define AMDGPU_VRAM_TYPE_GDDR6 9
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#define AMDGPU_VRAM_TYPE_DDR5 10
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#define AMDGPU_VRAM_TYPE_LPDDR4 11
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#define AMDGPU_VRAM_TYPE_LPDDR5 12
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struct drm_amdgpu_info_device {
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/** PCI Device ID */
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@ -1015,7 +1086,8 @@ struct drm_amdgpu_info_device {
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__u32 enabled_rb_pipes_mask;
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__u32 num_rb_pipes;
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__u32 num_hw_gfx_contexts;
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__u32 _pad;
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/* PCIe version (the smaller of the GPU and the CPU/motherboard) */
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__u32 pcie_gen;
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__u64 ids_flags;
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/** Starting virtual address for UMDs. */
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__u64 virtual_address_offset;
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@ -1062,7 +1134,8 @@ struct drm_amdgpu_info_device {
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__u32 gs_prim_buffer_depth;
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/* max gs wavefront per vgt*/
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__u32 max_gs_waves_per_vgt;
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__u32 _pad1;
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/* PCIe number of lanes (the smaller of the GPU and the CPU/motherboard) */
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__u32 pcie_num_lanes;
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/* always on cu bitmap */
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__u32 cu_ao_bitmap[4][4];
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/** Starting high virtual address for UMDs. */
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@ -1073,6 +1146,26 @@ struct drm_amdgpu_info_device {
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__u32 pa_sc_tile_steering_override;
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/* disabled TCCs */
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__u64 tcc_disabled_mask;
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__u64 min_engine_clock;
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__u64 min_memory_clock;
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/* The following fields are only set on gfx11+, older chips set 0. */
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__u32 tcp_cache_size; /* AKA GL0, VMEM cache */
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__u32 num_sqc_per_wgp;
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__u32 sqc_data_cache_size; /* AKA SMEM cache */
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__u32 sqc_inst_cache_size;
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__u32 gl1c_cache_size;
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__u32 gl2c_cache_size;
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__u64 mall_size; /* AKA infinity cache */
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/* high 32 bits of the rb pipes mask */
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__u32 enabled_rb_pipes_mask_hi;
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/* shadow area size for gfx11 */
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__u32 shadow_size;
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/* shadow area base virtual alignment for gfx11 */
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__u32 shadow_alignment;
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/* context save area size for gfx11 */
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__u32 csa_size;
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/* context save area base virtual alignment for gfx11 */
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__u32 csa_alignment;
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};
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struct drm_amdgpu_info_hw_ip {
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@ -1087,7 +1180,8 @@ struct drm_amdgpu_info_hw_ip {
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__u32 ib_size_alignment;
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/** Bitmask of available rings. Bit 0 means ring 0, etc. */
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__u32 available_rings;
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__u32 _pad;
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/** version info: bits 23:16 major, 15:8 minor, 7:0 revision */
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__u32 ip_discovery_version;
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};
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struct drm_amdgpu_info_num_handles {
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@ -1139,6 +1233,20 @@ struct drm_amdgpu_info_video_caps {
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struct drm_amdgpu_info_video_codec_info codec_info[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT];
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};
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#define AMDGPU_VMHUB_TYPE_MASK 0xff
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#define AMDGPU_VMHUB_TYPE_SHIFT 0
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#define AMDGPU_VMHUB_TYPE_GFX 0
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#define AMDGPU_VMHUB_TYPE_MM0 1
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#define AMDGPU_VMHUB_TYPE_MM1 2
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#define AMDGPU_VMHUB_IDX_MASK 0xff00
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#define AMDGPU_VMHUB_IDX_SHIFT 8
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struct drm_amdgpu_info_gpuvm_fault {
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__u64 addr;
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__u32 status;
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__u32 vmhub;
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};
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/*
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* Supported GPU families
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*/
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@ -1152,7 +1260,12 @@ struct drm_amdgpu_info_video_caps {
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#define AMDGPU_FAMILY_RV 142 /* Raven */
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#define AMDGPU_FAMILY_NV 143 /* Navi10 */
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#define AMDGPU_FAMILY_VGH 144 /* Van Gogh */
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#define AMDGPU_FAMILY_GC_11_0_0 145 /* GC 11.0.0 */
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#define AMDGPU_FAMILY_YC 146 /* Yellow Carp */
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#define AMDGPU_FAMILY_GC_11_0_1 148 /* GC 11.0.1 */
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#define AMDGPU_FAMILY_GC_10_3_6 149 /* GC 10.3.6 */
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#define AMDGPU_FAMILY_GC_10_3_7 151 /* GC 10.3.7 */
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#define AMDGPU_FAMILY_GC_11_5_0 150 /* GC 11.5.0 */
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#if defined(__cplusplus)
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}
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@ -629,8 +629,8 @@ struct drm_gem_open {
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/**
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* DRM_CAP_VBLANK_HIGH_CRTC
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*
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* If set to 1, the kernel supports specifying a CRTC index in the high bits of
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* &drm_wait_vblank_request.type.
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* If set to 1, the kernel supports specifying a :ref:`CRTC index<crtc_index>`
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* in the high bits of &drm_wait_vblank_request.type.
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*
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* Starting kernel version 2.6.39, this capability is always set to 1.
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*/
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@ -667,8 +667,11 @@ struct drm_gem_open {
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* Bitfield of supported PRIME sharing capabilities. See &DRM_PRIME_CAP_IMPORT
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* and &DRM_PRIME_CAP_EXPORT.
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*
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* PRIME buffers are exposed as dma-buf file descriptors. See
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* Documentation/gpu/drm-mm.rst, section "PRIME Buffer Sharing".
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* Starting from kernel version 6.6, both &DRM_PRIME_CAP_IMPORT and
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* &DRM_PRIME_CAP_EXPORT are always advertised.
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*
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* PRIME buffers are exposed as dma-buf file descriptors.
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* See :ref:`prime_buffer_sharing`.
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*/
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#define DRM_CAP_PRIME 0x5
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/**
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@ -676,6 +679,8 @@ struct drm_gem_open {
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*
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* If this bit is set in &DRM_CAP_PRIME, the driver supports importing PRIME
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* buffers via the &DRM_IOCTL_PRIME_FD_TO_HANDLE ioctl.
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*
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* Starting from kernel version 6.6, this bit is always set in &DRM_CAP_PRIME.
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*/
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#define DRM_PRIME_CAP_IMPORT 0x1
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/**
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@ -683,6 +688,8 @@ struct drm_gem_open {
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*
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* If this bit is set in &DRM_CAP_PRIME, the driver supports exporting PRIME
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* buffers via the &DRM_IOCTL_PRIME_HANDLE_TO_FD ioctl.
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*
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* Starting from kernel version 6.6, this bit is always set in &DRM_CAP_PRIME.
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*/
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#define DRM_PRIME_CAP_EXPORT 0x2
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/**
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@ -700,7 +707,8 @@ struct drm_gem_open {
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/**
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* DRM_CAP_ASYNC_PAGE_FLIP
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*
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* If set to 1, the driver supports &DRM_MODE_PAGE_FLIP_ASYNC.
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* If set to 1, the driver supports &DRM_MODE_PAGE_FLIP_ASYNC for legacy
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* page-flips.
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*/
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#define DRM_CAP_ASYNC_PAGE_FLIP 0x7
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/**
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@ -750,17 +758,23 @@ struct drm_gem_open {
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/**
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* DRM_CAP_SYNCOBJ
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*
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* If set to 1, the driver supports sync objects. See
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* Documentation/gpu/drm-mm.rst, section "DRM Sync Objects".
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* If set to 1, the driver supports sync objects. See :ref:`drm_sync_objects`.
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*/
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#define DRM_CAP_SYNCOBJ 0x13
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/**
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* DRM_CAP_SYNCOBJ_TIMELINE
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*
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* If set to 1, the driver supports timeline operations on sync objects. See
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* Documentation/gpu/drm-mm.rst, section "DRM Sync Objects".
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* :ref:`drm_sync_objects`.
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*/
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#define DRM_CAP_SYNCOBJ_TIMELINE 0x14
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/**
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* DRM_CAP_ATOMIC_ASYNC_PAGE_FLIP
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*
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* If set to 1, the driver supports &DRM_MODE_PAGE_FLIP_ASYNC for atomic
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* commits.
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*/
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#define DRM_CAP_ATOMIC_ASYNC_PAGE_FLIP 0x15
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/* DRM_IOCTL_GET_CAP ioctl argument type */
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struct drm_get_cap {
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@ -830,6 +844,31 @@ struct drm_get_cap {
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*/
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#define DRM_CLIENT_CAP_WRITEBACK_CONNECTORS 5
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/**
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* DRM_CLIENT_CAP_CURSOR_PLANE_HOTSPOT
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*
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* Drivers for para-virtualized hardware (e.g. vmwgfx, qxl, virtio and
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* virtualbox) have additional restrictions for cursor planes (thus
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* making cursor planes on those drivers not truly universal,) e.g.
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* they need cursor planes to act like one would expect from a mouse
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* cursor and have correctly set hotspot properties.
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* If this client cap is not set the DRM core will hide cursor plane on
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* those virtualized drivers because not setting it implies that the
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* client is not capable of dealing with those extra restictions.
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* Clients which do set cursor hotspot and treat the cursor plane
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* like a mouse cursor should set this property.
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* The client must enable &DRM_CLIENT_CAP_ATOMIC first.
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*
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* Setting this property on drivers which do not special case
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* cursor planes (i.e. non-virtualized drivers) will return
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* EOPNOTSUPP, which can be used by userspace to gauge
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* requirements of the hardware/drivers they're running on.
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*
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* This capability is always supported for atomic-capable virtualized
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* drivers starting from kernel version 6.6.
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*/
|
||||
#define DRM_CLIENT_CAP_CURSOR_PLANE_HOTSPOT 6
|
||||
|
||||
/* DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */
|
||||
struct drm_set_client_cap {
|
||||
__u64 capability;
|
||||
|
|
@ -881,6 +920,7 @@ struct drm_syncobj_transfer {
|
|||
#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL (1 << 0)
|
||||
#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT (1 << 1)
|
||||
#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABLE (1 << 2) /* wait for time point to become available */
|
||||
#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_DEADLINE (1 << 3) /* set fence deadline to deadline_nsec */
|
||||
struct drm_syncobj_wait {
|
||||
__u64 handles;
|
||||
/* absolute timeout */
|
||||
|
|
@ -889,6 +929,14 @@ struct drm_syncobj_wait {
|
|||
__u32 flags;
|
||||
__u32 first_signaled; /* only valid when not waiting all */
|
||||
__u32 pad;
|
||||
/**
|
||||
* @deadline_nsec - fence deadline hint
|
||||
*
|
||||
* Deadline hint, in absolute CLOCK_MONOTONIC, to set on backing
|
||||
* fence(s) if the DRM_SYNCOBJ_WAIT_FLAGS_WAIT_DEADLINE flag is
|
||||
* set.
|
||||
*/
|
||||
__u64 deadline_nsec;
|
||||
};
|
||||
|
||||
struct drm_syncobj_timeline_wait {
|
||||
|
|
@ -901,6 +949,35 @@ struct drm_syncobj_timeline_wait {
|
|||
__u32 flags;
|
||||
__u32 first_signaled; /* only valid when not waiting all */
|
||||
__u32 pad;
|
||||
/**
|
||||
* @deadline_nsec - fence deadline hint
|
||||
*
|
||||
* Deadline hint, in absolute CLOCK_MONOTONIC, to set on backing
|
||||
* fence(s) if the DRM_SYNCOBJ_WAIT_FLAGS_WAIT_DEADLINE flag is
|
||||
* set.
|
||||
*/
|
||||
__u64 deadline_nsec;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_syncobj_eventfd
|
||||
* @handle: syncobj handle.
|
||||
* @flags: Zero to wait for the point to be signalled, or
|
||||
* &DRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABLE to wait for a fence to be
|
||||
* available for the point.
|
||||
* @point: syncobj timeline point (set to zero for binary syncobjs).
|
||||
* @fd: Existing eventfd to sent events to.
|
||||
* @pad: Must be zero.
|
||||
*
|
||||
* Register an eventfd to be signalled by a syncobj. The eventfd counter will
|
||||
* be incremented by one.
|
||||
*/
|
||||
struct drm_syncobj_eventfd {
|
||||
__u32 handle;
|
||||
__u32 flags;
|
||||
__u64 point;
|
||||
__s32 fd;
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
|
||||
|
|
@ -966,6 +1043,19 @@ extern "C" {
|
|||
#define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats)
|
||||
#define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version)
|
||||
#define DRM_IOCTL_MODESET_CTL DRM_IOW(0x08, struct drm_modeset_ctl)
|
||||
/**
|
||||
* DRM_IOCTL_GEM_CLOSE - Close a GEM handle.
|
||||
*
|
||||
* GEM handles are not reference-counted by the kernel. User-space is
|
||||
* responsible for managing their lifetime. For example, if user-space imports
|
||||
* the same memory object twice on the same DRM file description, the same GEM
|
||||
* handle is returned by both imports, and user-space needs to ensure
|
||||
* &DRM_IOCTL_GEM_CLOSE is performed once only. The same situation can happen
|
||||
* when a memory object is allocated, then exported and imported again on the
|
||||
* same DRM file description. The &DRM_IOCTL_MODE_GETFB2 IOCTL is an exception
|
||||
* and always returns fresh new GEM handles even if an existing GEM handle
|
||||
* already refers to the same memory object before the IOCTL is performed.
|
||||
*/
|
||||
#define DRM_IOCTL_GEM_CLOSE DRM_IOW (0x09, struct drm_gem_close)
|
||||
#define DRM_IOCTL_GEM_FLINK DRM_IOWR(0x0a, struct drm_gem_flink)
|
||||
#define DRM_IOCTL_GEM_OPEN DRM_IOWR(0x0b, struct drm_gem_open)
|
||||
|
|
@ -1006,7 +1096,37 @@ extern "C" {
|
|||
#define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock)
|
||||
#define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock)
|
||||
|
||||
/**
|
||||
* DRM_IOCTL_PRIME_HANDLE_TO_FD - Convert a GEM handle to a DMA-BUF FD.
|
||||
*
|
||||
* User-space sets &drm_prime_handle.handle with the GEM handle to export and
|
||||
* &drm_prime_handle.flags, and gets back a DMA-BUF file descriptor in
|
||||
* &drm_prime_handle.fd.
|
||||
*
|
||||
* The export can fail for any driver-specific reason, e.g. because export is
|
||||
* not supported for this specific GEM handle (but might be for others).
|
||||
*
|
||||
* Support for exporting DMA-BUFs is advertised via &DRM_PRIME_CAP_EXPORT.
|
||||
*/
|
||||
#define DRM_IOCTL_PRIME_HANDLE_TO_FD DRM_IOWR(0x2d, struct drm_prime_handle)
|
||||
/**
|
||||
* DRM_IOCTL_PRIME_FD_TO_HANDLE - Convert a DMA-BUF FD to a GEM handle.
|
||||
*
|
||||
* User-space sets &drm_prime_handle.fd with a DMA-BUF file descriptor to
|
||||
* import, and gets back a GEM handle in &drm_prime_handle.handle.
|
||||
* &drm_prime_handle.flags is unused.
|
||||
*
|
||||
* If an existing GEM handle refers to the memory object backing the DMA-BUF,
|
||||
* that GEM handle is returned. Therefore user-space which needs to handle
|
||||
* arbitrary DMA-BUFs must have a user-space lookup data structure to manually
|
||||
* reference-count duplicated GEM handles. For more information see
|
||||
* &DRM_IOCTL_GEM_CLOSE.
|
||||
*
|
||||
* The import can fail for any driver-specific reason, e.g. because import is
|
||||
* only supported for DMA-BUFs allocated on this DRM device.
|
||||
*
|
||||
* Support for importing DMA-BUFs is advertised via &DRM_PRIME_CAP_IMPORT.
|
||||
*/
|
||||
#define DRM_IOCTL_PRIME_FD_TO_HANDLE DRM_IOWR(0x2e, struct drm_prime_handle)
|
||||
|
||||
#define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30)
|
||||
|
|
@ -1044,10 +1164,40 @@ extern "C" {
|
|||
#define DRM_IOCTL_MODE_GETPROPBLOB DRM_IOWR(0xAC, struct drm_mode_get_blob)
|
||||
#define DRM_IOCTL_MODE_GETFB DRM_IOWR(0xAD, struct drm_mode_fb_cmd)
|
||||
#define DRM_IOCTL_MODE_ADDFB DRM_IOWR(0xAE, struct drm_mode_fb_cmd)
|
||||
/**
|
||||
* DRM_IOCTL_MODE_RMFB - Remove a framebuffer.
|
||||
*
|
||||
* This removes a framebuffer previously added via ADDFB/ADDFB2. The IOCTL
|
||||
* argument is a framebuffer object ID.
|
||||
*
|
||||
* Warning: removing a framebuffer currently in-use on an enabled plane will
|
||||
* disable that plane. The CRTC the plane is linked to may also be disabled
|
||||
* (depending on driver capabilities).
|
||||
*/
|
||||
#define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xAF, unsigned int)
|
||||
#define DRM_IOCTL_MODE_PAGE_FLIP DRM_IOWR(0xB0, struct drm_mode_crtc_page_flip)
|
||||
#define DRM_IOCTL_MODE_DIRTYFB DRM_IOWR(0xB1, struct drm_mode_fb_dirty_cmd)
|
||||
|
||||
/**
|
||||
* DRM_IOCTL_MODE_CREATE_DUMB - Create a new dumb buffer object.
|
||||
*
|
||||
* KMS dumb buffers provide a very primitive way to allocate a buffer object
|
||||
* suitable for scanout and map it for software rendering. KMS dumb buffers are
|
||||
* not suitable for hardware-accelerated rendering nor video decoding. KMS dumb
|
||||
* buffers are not suitable to be displayed on any other device than the KMS
|
||||
* device where they were allocated from. Also see
|
||||
* :ref:`kms_dumb_buffer_objects`.
|
||||
*
|
||||
* The IOCTL argument is a struct drm_mode_create_dumb.
|
||||
*
|
||||
* User-space is expected to create a KMS dumb buffer via this IOCTL, then add
|
||||
* it as a KMS framebuffer via &DRM_IOCTL_MODE_ADDFB and map it via
|
||||
* &DRM_IOCTL_MODE_MAP_DUMB.
|
||||
*
|
||||
* &DRM_CAP_DUMB_BUFFER indicates whether this IOCTL is supported.
|
||||
* &DRM_CAP_DUMB_PREFERRED_DEPTH and &DRM_CAP_DUMB_PREFER_SHADOW indicate
|
||||
* driver preferences for dumb buffers.
|
||||
*/
|
||||
#define DRM_IOCTL_MODE_CREATE_DUMB DRM_IOWR(0xB2, struct drm_mode_create_dumb)
|
||||
#define DRM_IOCTL_MODE_MAP_DUMB DRM_IOWR(0xB3, struct drm_mode_map_dumb)
|
||||
#define DRM_IOCTL_MODE_DESTROY_DUMB DRM_IOWR(0xB4, struct drm_mode_destroy_dumb)
|
||||
|
|
@ -1080,8 +1230,58 @@ extern "C" {
|
|||
#define DRM_IOCTL_SYNCOBJ_TRANSFER DRM_IOWR(0xCC, struct drm_syncobj_transfer)
|
||||
#define DRM_IOCTL_SYNCOBJ_TIMELINE_SIGNAL DRM_IOWR(0xCD, struct drm_syncobj_timeline_array)
|
||||
|
||||
/**
|
||||
* DRM_IOCTL_MODE_GETFB2 - Get framebuffer metadata.
|
||||
*
|
||||
* This queries metadata about a framebuffer. User-space fills
|
||||
* &drm_mode_fb_cmd2.fb_id as the input, and the kernels fills the rest of the
|
||||
* struct as the output.
|
||||
*
|
||||
* If the client is DRM master or has &CAP_SYS_ADMIN, &drm_mode_fb_cmd2.handles
|
||||
* will be filled with GEM buffer handles. Fresh new GEM handles are always
|
||||
* returned, even if another GEM handle referring to the same memory object
|
||||
* already exists on the DRM file description. The caller is responsible for
|
||||
* removing the new handles, e.g. via the &DRM_IOCTL_GEM_CLOSE IOCTL. The same
|
||||
* new handle will be returned for multiple planes in case they use the same
|
||||
* memory object. Planes are valid until one has a zero handle -- this can be
|
||||
* used to compute the number of planes.
|
||||
*
|
||||
* Otherwise, &drm_mode_fb_cmd2.handles will be zeroed and planes are valid
|
||||
* until one has a zero &drm_mode_fb_cmd2.pitches.
|
||||
*
|
||||
* If the framebuffer has a format modifier, &DRM_MODE_FB_MODIFIERS will be set
|
||||
* in &drm_mode_fb_cmd2.flags and &drm_mode_fb_cmd2.modifier will contain the
|
||||
* modifier. Otherwise, user-space must ignore &drm_mode_fb_cmd2.modifier.
|
||||
*
|
||||
* To obtain DMA-BUF FDs for each plane without leaking GEM handles, user-space
|
||||
* can export each handle via &DRM_IOCTL_PRIME_HANDLE_TO_FD, then immediately
|
||||
* close each unique handle via &DRM_IOCTL_GEM_CLOSE, making sure to not
|
||||
* double-close handles which are specified multiple times in the array.
|
||||
*/
|
||||
#define DRM_IOCTL_MODE_GETFB2 DRM_IOWR(0xCE, struct drm_mode_fb_cmd2)
|
||||
|
||||
#define DRM_IOCTL_SYNCOBJ_EVENTFD DRM_IOWR(0xCF, struct drm_syncobj_eventfd)
|
||||
|
||||
/**
|
||||
* DRM_IOCTL_MODE_CLOSEFB - Close a framebuffer.
|
||||
*
|
||||
* This closes a framebuffer previously added via ADDFB/ADDFB2. The IOCTL
|
||||
* argument is a framebuffer object ID.
|
||||
*
|
||||
* This IOCTL is similar to &DRM_IOCTL_MODE_RMFB, except it doesn't disable
|
||||
* planes and CRTCs. As long as the framebuffer is used by a plane, it's kept
|
||||
* alive. When the plane no longer uses the framebuffer (because the
|
||||
* framebuffer is replaced with another one, or the plane is disabled), the
|
||||
* framebuffer is cleaned up.
|
||||
*
|
||||
* This is useful to implement flicker-free transitions between two processes.
|
||||
*
|
||||
* Depending on the threat model, user-space may want to ensure that the
|
||||
* framebuffer doesn't expose any sensitive user information: closed
|
||||
* framebuffers attached to a plane can be read back by the next DRM master.
|
||||
*/
|
||||
#define DRM_IOCTL_MODE_CLOSEFB DRM_IOWR(0xD0, struct drm_mode_closefb)
|
||||
|
||||
/*
|
||||
* Device specific ioctls should only be in their respective headers
|
||||
* The device specific ioctl range is from 0x40 to 0x9f.
|
||||
|
|
@ -1093,25 +1293,50 @@ extern "C" {
|
|||
#define DRM_COMMAND_BASE 0x40
|
||||
#define DRM_COMMAND_END 0xA0
|
||||
|
||||
/*
|
||||
* Header for events written back to userspace on the drm fd. The
|
||||
* type defines the type of event, the length specifies the total
|
||||
* length of the event (including the header), and user_data is
|
||||
* typically a 64 bit value passed with the ioctl that triggered the
|
||||
* event. A read on the drm fd will always only return complete
|
||||
* events, that is, if for example the read buffer is 100 bytes, and
|
||||
* there are two 64 byte events pending, only one will be returned.
|
||||
/**
|
||||
* struct drm_event - Header for DRM events
|
||||
* @type: event type.
|
||||
* @length: total number of payload bytes (including header).
|
||||
*
|
||||
* Event types 0 - 0x7fffffff are generic drm events, 0x80000000 and
|
||||
* up are chipset specific.
|
||||
* This struct is a header for events written back to user-space on the DRM FD.
|
||||
* A read on the DRM FD will always only return complete events: e.g. if the
|
||||
* read buffer is 100 bytes large and there are two 64 byte events pending,
|
||||
* only one will be returned.
|
||||
*
|
||||
* Event types 0 - 0x7fffffff are generic DRM events, 0x80000000 and
|
||||
* up are chipset specific. Generic DRM events include &DRM_EVENT_VBLANK,
|
||||
* &DRM_EVENT_FLIP_COMPLETE and &DRM_EVENT_CRTC_SEQUENCE.
|
||||
*/
|
||||
struct drm_event {
|
||||
__u32 type;
|
||||
__u32 length;
|
||||
};
|
||||
|
||||
/**
|
||||
* DRM_EVENT_VBLANK - vertical blanking event
|
||||
*
|
||||
* This event is sent in response to &DRM_IOCTL_WAIT_VBLANK with the
|
||||
* &_DRM_VBLANK_EVENT flag set.
|
||||
*
|
||||
* The event payload is a struct drm_event_vblank.
|
||||
*/
|
||||
#define DRM_EVENT_VBLANK 0x01
|
||||
/**
|
||||
* DRM_EVENT_FLIP_COMPLETE - page-flip completion event
|
||||
*
|
||||
* This event is sent in response to an atomic commit or legacy page-flip with
|
||||
* the &DRM_MODE_PAGE_FLIP_EVENT flag set.
|
||||
*
|
||||
* The event payload is a struct drm_event_vblank.
|
||||
*/
|
||||
#define DRM_EVENT_FLIP_COMPLETE 0x02
|
||||
/**
|
||||
* DRM_EVENT_CRTC_SEQUENCE - CRTC sequence event
|
||||
*
|
||||
* This event is sent in response to &DRM_IOCTL_CRTC_QUEUE_SEQUENCE.
|
||||
*
|
||||
* The event payload is a struct drm_event_crtc_sequence.
|
||||
*/
|
||||
#define DRM_EVENT_CRTC_SEQUENCE 0x03
|
||||
|
||||
struct drm_event_vblank {
|
||||
|
|
|
|||
|
|
@ -88,6 +88,18 @@ extern "C" {
|
|||
*
|
||||
* The authoritative list of format modifier codes is found in
|
||||
* `include/uapi/drm/drm_fourcc.h`
|
||||
*
|
||||
* Open Source User Waiver
|
||||
* -----------------------
|
||||
*
|
||||
* Because this is the authoritative source for pixel formats and modifiers
|
||||
* referenced by GL, Vulkan extensions and other standards and hence used both
|
||||
* by open source and closed source driver stacks, the usual requirement for an
|
||||
* upstream in-kernel or open source userspace user does not apply.
|
||||
*
|
||||
* To ensure, as much as feasible, compatibility across stacks and avoid
|
||||
* confusion with incompatible enumerations stakeholders for all relevant driver
|
||||
* stacks should approve additions.
|
||||
*/
|
||||
|
||||
#define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \
|
||||
|
|
@ -311,6 +323,8 @@ extern "C" {
|
|||
* index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian
|
||||
*/
|
||||
#define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */
|
||||
#define DRM_FORMAT_NV20 fourcc_code('N', 'V', '2', '0') /* 2x1 subsampled Cr:Cb plane */
|
||||
#define DRM_FORMAT_NV30 fourcc_code('N', 'V', '3', '0') /* non-subsampled Cr:Cb plane */
|
||||
|
||||
/*
|
||||
* 2 plane YCbCr MSB aligned
|
||||
|
|
@ -645,6 +659,49 @@ extern "C" {
|
|||
*/
|
||||
#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12)
|
||||
|
||||
/*
|
||||
* Intel Color Control Surfaces (CCS) for display ver. 14 render compression.
|
||||
*
|
||||
* The main surface is tile4 and at plane index 0, the CCS is linear and
|
||||
* at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
|
||||
* main surface. In other words, 4 bits in CCS map to a main surface cache
|
||||
* line pair. The main surface pitch is required to be a multiple of four
|
||||
* tile4 widths.
|
||||
*/
|
||||
#define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS fourcc_mod_code(INTEL, 13)
|
||||
|
||||
/*
|
||||
* Intel Color Control Surfaces (CCS) for display ver. 14 media compression
|
||||
*
|
||||
* The main surface is tile4 and at plane index 0, the CCS is linear and
|
||||
* at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
|
||||
* main surface. In other words, 4 bits in CCS map to a main surface cache
|
||||
* line pair. The main surface pitch is required to be a multiple of four
|
||||
* tile4 widths. For semi-planar formats like NV12, CCS planes follow the
|
||||
* Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,
|
||||
* planes 2 and 3 for the respective CCS.
|
||||
*/
|
||||
#define I915_FORMAT_MOD_4_TILED_MTL_MC_CCS fourcc_mod_code(INTEL, 14)
|
||||
|
||||
/*
|
||||
* Intel Color Control Surface with Clear Color (CCS) for display ver. 14 render
|
||||
* compression.
|
||||
*
|
||||
* The main surface is tile4 and is at plane index 0 whereas CCS is linear
|
||||
* and at index 1. The clear color is stored at index 2, and the pitch should
|
||||
* be ignored. The clear color structure is 256 bits. The first 128 bits
|
||||
* represents Raw Clear Color Red, Green, Blue and Alpha color each represented
|
||||
* by 32 bits. The raw clear color is consumed by the 3d engine and generates
|
||||
* the converted clear color of size 64 bits. The first 32 bits store the Lower
|
||||
* Converted Clear Color value and the next 32 bits store the Higher Converted
|
||||
* Clear Color value when applicable. The Converted Clear Color values are
|
||||
* consumed by the DE. The last 64 bits are used to store Color Discard Enable
|
||||
* and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
|
||||
* corresponds to an area of 4x1 tiles in the main surface. The main surface
|
||||
* pitch is required to be a multiple of 4 tile widths.
|
||||
*/
|
||||
#define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC fourcc_mod_code(INTEL, 15)
|
||||
|
||||
/*
|
||||
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
|
||||
*
|
||||
|
|
|
|||
|
|
@ -312,16 +312,48 @@ struct drm_mode_set_plane {
|
|||
__u32 src_w;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_mode_get_plane - Get plane metadata.
|
||||
*
|
||||
* Userspace can perform a GETPLANE ioctl to retrieve information about a
|
||||
* plane.
|
||||
*
|
||||
* To retrieve the number of formats supported, set @count_format_types to zero
|
||||
* and call the ioctl. @count_format_types will be updated with the value.
|
||||
*
|
||||
* To retrieve these formats, allocate an array with the memory needed to store
|
||||
* @count_format_types formats. Point @format_type_ptr to this array and call
|
||||
* the ioctl again (with @count_format_types still set to the value returned in
|
||||
* the first ioctl call).
|
||||
*/
|
||||
struct drm_mode_get_plane {
|
||||
/**
|
||||
* @plane_id: Object ID of the plane whose information should be
|
||||
* retrieved. Set by caller.
|
||||
*/
|
||||
__u32 plane_id;
|
||||
|
||||
/** @crtc_id: Object ID of the current CRTC. */
|
||||
__u32 crtc_id;
|
||||
/** @fb_id: Object ID of the current fb. */
|
||||
__u32 fb_id;
|
||||
|
||||
/**
|
||||
* @possible_crtcs: Bitmask of CRTC's compatible with the plane. CRTC's
|
||||
* are created and they receive an index, which corresponds to their
|
||||
* position in the bitmask. Bit N corresponds to
|
||||
* :ref:`CRTC index<crtc_index>` N.
|
||||
*/
|
||||
__u32 possible_crtcs;
|
||||
/** @gamma_size: Never used. */
|
||||
__u32 gamma_size;
|
||||
|
||||
/** @count_format_types: Number of formats. */
|
||||
__u32 count_format_types;
|
||||
/**
|
||||
* @format_type_ptr: Pointer to ``__u32`` array of formats that are
|
||||
* supported by the plane. These formats do not require modifiers.
|
||||
*/
|
||||
__u64 format_type_ptr;
|
||||
};
|
||||
|
||||
|
|
@ -456,6 +488,9 @@ struct drm_mode_get_connector {
|
|||
* This is not an object ID. This is a per-type connector number. Each
|
||||
* (type, type_id) combination is unique across all connectors of a DRM
|
||||
* device.
|
||||
*
|
||||
* The (type, type_id) combination is not a stable identifier: the
|
||||
* type_id can change depending on the driver probe order.
|
||||
*/
|
||||
__u32 connector_type_id;
|
||||
|
||||
|
|
@ -509,22 +544,74 @@ struct drm_mode_get_connector {
|
|||
*/
|
||||
#define DRM_MODE_PROP_ATOMIC 0x80000000
|
||||
|
||||
/**
|
||||
* struct drm_mode_property_enum - Description for an enum/bitfield entry.
|
||||
* @value: numeric value for this enum entry.
|
||||
* @name: symbolic name for this enum entry.
|
||||
*
|
||||
* See struct drm_property_enum for details.
|
||||
*/
|
||||
struct drm_mode_property_enum {
|
||||
__u64 value;
|
||||
char name[DRM_PROP_NAME_LEN];
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_mode_get_property - Get property metadata.
|
||||
*
|
||||
* User-space can perform a GETPROPERTY ioctl to retrieve information about a
|
||||
* property. The same property may be attached to multiple objects, see
|
||||
* "Modeset Base Object Abstraction".
|
||||
*
|
||||
* The meaning of the @values_ptr field changes depending on the property type.
|
||||
* See &drm_property.flags for more details.
|
||||
*
|
||||
* The @enum_blob_ptr and @count_enum_blobs fields are only meaningful when the
|
||||
* property has the type &DRM_MODE_PROP_ENUM or &DRM_MODE_PROP_BITMASK. For
|
||||
* backwards compatibility, the kernel will always set @count_enum_blobs to
|
||||
* zero when the property has the type &DRM_MODE_PROP_BLOB. User-space must
|
||||
* ignore these two fields if the property has a different type.
|
||||
*
|
||||
* User-space is expected to retrieve values and enums by performing this ioctl
|
||||
* at least twice: the first time to retrieve the number of elements, the
|
||||
* second time to retrieve the elements themselves.
|
||||
*
|
||||
* To retrieve the number of elements, set @count_values and @count_enum_blobs
|
||||
* to zero, then call the ioctl. @count_values will be updated with the number
|
||||
* of elements. If the property has the type &DRM_MODE_PROP_ENUM or
|
||||
* &DRM_MODE_PROP_BITMASK, @count_enum_blobs will be updated as well.
|
||||
*
|
||||
* To retrieve the elements themselves, allocate an array for @values_ptr and
|
||||
* set @count_values to its capacity. If the property has the type
|
||||
* &DRM_MODE_PROP_ENUM or &DRM_MODE_PROP_BITMASK, allocate an array for
|
||||
* @enum_blob_ptr and set @count_enum_blobs to its capacity. Calling the ioctl
|
||||
* again will fill the arrays.
|
||||
*/
|
||||
struct drm_mode_get_property {
|
||||
__u64 values_ptr; /* values and blob lengths */
|
||||
__u64 enum_blob_ptr; /* enum and blob id ptrs */
|
||||
/** @values_ptr: Pointer to a ``__u64`` array. */
|
||||
__u64 values_ptr;
|
||||
/** @enum_blob_ptr: Pointer to a struct drm_mode_property_enum array. */
|
||||
__u64 enum_blob_ptr;
|
||||
|
||||
/**
|
||||
* @prop_id: Object ID of the property which should be retrieved. Set
|
||||
* by the caller.
|
||||
*/
|
||||
__u32 prop_id;
|
||||
/**
|
||||
* @flags: ``DRM_MODE_PROP_*`` bitfield. See &drm_property.flags for
|
||||
* a definition of the flags.
|
||||
*/
|
||||
__u32 flags;
|
||||
/**
|
||||
* @name: Symbolic property name. User-space should use this field to
|
||||
* recognize properties.
|
||||
*/
|
||||
char name[DRM_PROP_NAME_LEN];
|
||||
|
||||
/** @count_values: Number of elements in @values_ptr. */
|
||||
__u32 count_values;
|
||||
/* This is only used to count enum values, not blobs. The _blobs is
|
||||
* simply because of a historical reason, i.e. backwards compat. */
|
||||
/** @count_enum_blobs: Number of elements in @enum_blob_ptr. */
|
||||
__u32 count_enum_blobs;
|
||||
};
|
||||
|
||||
|
|
@ -579,41 +666,73 @@ struct drm_mode_fb_cmd {
|
|||
#define DRM_MODE_FB_INTERLACED (1<<0) /* for interlaced framebuffers */
|
||||
#define DRM_MODE_FB_MODIFIERS (1<<1) /* enables ->modifer[] */
|
||||
|
||||
/**
|
||||
* struct drm_mode_fb_cmd2 - Frame-buffer metadata.
|
||||
*
|
||||
* This struct holds frame-buffer metadata. There are two ways to use it:
|
||||
*
|
||||
* - User-space can fill this struct and perform a &DRM_IOCTL_MODE_ADDFB2
|
||||
* ioctl to register a new frame-buffer. The new frame-buffer object ID will
|
||||
* be set by the kernel in @fb_id.
|
||||
* - User-space can set @fb_id and perform a &DRM_IOCTL_MODE_GETFB2 ioctl to
|
||||
* fetch metadata about an existing frame-buffer.
|
||||
*
|
||||
* In case of planar formats, this struct allows up to 4 buffer objects with
|
||||
* offsets and pitches per plane. The pitch and offset order are dictated by
|
||||
* the format FourCC as defined by ``drm_fourcc.h``, e.g. NV12 is described as:
|
||||
*
|
||||
* YUV 4:2:0 image with a plane of 8-bit Y samples followed by an
|
||||
* interleaved U/V plane containing 8-bit 2x2 subsampled colour difference
|
||||
* samples.
|
||||
*
|
||||
* So it would consist of a Y plane at ``offsets[0]`` and a UV plane at
|
||||
* ``offsets[1]``.
|
||||
*
|
||||
* To accommodate tiled, compressed, etc formats, a modifier can be specified.
|
||||
* For more information see the "Format Modifiers" section. Note that even
|
||||
* though it looks like we have a modifier per-plane, we in fact do not. The
|
||||
* modifier for each plane must be identical. Thus all combinations of
|
||||
* different data layouts for multi-plane formats must be enumerated as
|
||||
* separate modifiers.
|
||||
*
|
||||
* All of the entries in @handles, @pitches, @offsets and @modifier must be
|
||||
* zero when unused. Warning, for @offsets and @modifier zero can't be used to
|
||||
* figure out whether the entry is used or not since it's a valid value (a zero
|
||||
* offset is common, and a zero modifier is &DRM_FORMAT_MOD_LINEAR).
|
||||
*/
|
||||
struct drm_mode_fb_cmd2 {
|
||||
/** @fb_id: Object ID of the frame-buffer. */
|
||||
__u32 fb_id;
|
||||
/** @width: Width of the frame-buffer. */
|
||||
__u32 width;
|
||||
/** @height: Height of the frame-buffer. */
|
||||
__u32 height;
|
||||
__u32 pixel_format; /* fourcc code from drm_fourcc.h */
|
||||
__u32 flags; /* see above flags */
|
||||
/**
|
||||
* @pixel_format: FourCC format code, see ``DRM_FORMAT_*`` constants in
|
||||
* ``drm_fourcc.h``.
|
||||
*/
|
||||
__u32 pixel_format;
|
||||
/**
|
||||
* @flags: Frame-buffer flags (see &DRM_MODE_FB_INTERLACED and
|
||||
* &DRM_MODE_FB_MODIFIERS).
|
||||
*/
|
||||
__u32 flags;
|
||||
|
||||
/*
|
||||
* In case of planar formats, this ioctl allows up to 4
|
||||
* buffer objects with offsets and pitches per plane.
|
||||
* The pitch and offset order is dictated by the fourcc,
|
||||
* e.g. NV12 (https://fourcc.org/yuv.php#NV12) is described as:
|
||||
*
|
||||
* YUV 4:2:0 image with a plane of 8 bit Y samples
|
||||
* followed by an interleaved U/V plane containing
|
||||
* 8 bit 2x2 subsampled colour difference samples.
|
||||
*
|
||||
* So it would consist of Y as offsets[0] and UV as
|
||||
* offsets[1]. Note that offsets[0] will generally
|
||||
* be 0 (but this is not required).
|
||||
*
|
||||
* To accommodate tiled, compressed, etc formats, a
|
||||
* modifier can be specified. The default value of zero
|
||||
* indicates "native" format as specified by the fourcc.
|
||||
* Vendor specific modifier token. Note that even though
|
||||
* it looks like we have a modifier per-plane, we in fact
|
||||
* do not. The modifier for each plane must be identical.
|
||||
* Thus all combinations of different data layouts for
|
||||
* multi plane formats must be enumerated as separate
|
||||
* modifiers.
|
||||
/**
|
||||
* @handles: GEM buffer handle, one per plane. Set to 0 if the plane is
|
||||
* unused. The same handle can be used for multiple planes.
|
||||
*/
|
||||
__u32 handles[4];
|
||||
__u32 pitches[4]; /* pitch for each plane */
|
||||
__u32 offsets[4]; /* offset of each plane */
|
||||
__u64 modifier[4]; /* ie, tiling, compress */
|
||||
/** @pitches: Pitch (aka. stride) in bytes, one per plane. */
|
||||
__u32 pitches[4];
|
||||
/** @offsets: Offset into the buffer in bytes, one per plane. */
|
||||
__u32 offsets[4];
|
||||
/**
|
||||
* @modifier: Format modifier, one per plane. See ``DRM_FORMAT_MOD_*``
|
||||
* constants in ``drm_fourcc.h``. All planes must use the same
|
||||
* modifier. Ignored unless &DRM_MODE_FB_MODIFIERS is set in @flags.
|
||||
*/
|
||||
__u64 modifier[4];
|
||||
};
|
||||
|
||||
#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01
|
||||
|
|
@ -718,6 +837,11 @@ struct drm_color_ctm {
|
|||
/*
|
||||
* Conversion matrix in S31.32 sign-magnitude
|
||||
* (not two's complement!) format.
|
||||
*
|
||||
* out matrix in
|
||||
* |R| |0 1 2| |R|
|
||||
* |G| = |3 4 5| x |G|
|
||||
* |B| |6 7 8| |B|
|
||||
*/
|
||||
__u64 matrix[9];
|
||||
};
|
||||
|
|
@ -762,7 +886,7 @@ struct hdr_metadata_infoframe {
|
|||
*/
|
||||
struct {
|
||||
__u16 x, y;
|
||||
} display_primaries[3];
|
||||
} display_primaries[3];
|
||||
/**
|
||||
* @white_point: White Point of Colorspace Data.
|
||||
* These are coded as unsigned 16-bit values in units of
|
||||
|
|
@ -773,7 +897,7 @@ struct hdr_metadata_infoframe {
|
|||
*/
|
||||
struct {
|
||||
__u16 x, y;
|
||||
} white_point;
|
||||
} white_point;
|
||||
/**
|
||||
* @max_display_mastering_luminance: Max Mastering Display Luminance.
|
||||
* This value is coded as an unsigned 16-bit value in units of 1 cd/m2,
|
||||
|
|
@ -819,12 +943,40 @@ struct hdr_output_metadata {
|
|||
};
|
||||
};
|
||||
|
||||
/**
|
||||
* DRM_MODE_PAGE_FLIP_EVENT
|
||||
*
|
||||
* Request that the kernel sends back a vblank event (see
|
||||
* struct drm_event_vblank) with the &DRM_EVENT_FLIP_COMPLETE type when the
|
||||
* page-flip is done.
|
||||
*/
|
||||
#define DRM_MODE_PAGE_FLIP_EVENT 0x01
|
||||
/**
|
||||
* DRM_MODE_PAGE_FLIP_ASYNC
|
||||
*
|
||||
* Request that the page-flip is performed as soon as possible, ie. with no
|
||||
* delay due to waiting for vblank. This may cause tearing to be visible on
|
||||
* the screen.
|
||||
*
|
||||
* When used with atomic uAPI, the driver will return an error if the hardware
|
||||
* doesn't support performing an asynchronous page-flip for this update.
|
||||
* User-space should handle this, e.g. by falling back to a regular page-flip.
|
||||
*
|
||||
* Note, some hardware might need to perform one last synchronous page-flip
|
||||
* before being able to switch to asynchronous page-flips. As an exception,
|
||||
* the driver will return success even though that first page-flip is not
|
||||
* asynchronous.
|
||||
*/
|
||||
#define DRM_MODE_PAGE_FLIP_ASYNC 0x02
|
||||
#define DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4
|
||||
#define DRM_MODE_PAGE_FLIP_TARGET_RELATIVE 0x8
|
||||
#define DRM_MODE_PAGE_FLIP_TARGET (DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE | \
|
||||
DRM_MODE_PAGE_FLIP_TARGET_RELATIVE)
|
||||
/**
|
||||
* DRM_MODE_PAGE_FLIP_FLAGS
|
||||
*
|
||||
* Bitmask of flags suitable for &drm_mode_crtc_page_flip_target.flags.
|
||||
*/
|
||||
#define DRM_MODE_PAGE_FLIP_FLAGS (DRM_MODE_PAGE_FLIP_EVENT | \
|
||||
DRM_MODE_PAGE_FLIP_ASYNC | \
|
||||
DRM_MODE_PAGE_FLIP_TARGET)
|
||||
|
|
@ -889,13 +1041,25 @@ struct drm_mode_crtc_page_flip_target {
|
|||
__u64 user_data;
|
||||
};
|
||||
|
||||
/* create a dumb scanout buffer */
|
||||
/**
|
||||
* struct drm_mode_create_dumb - Create a KMS dumb buffer for scanout.
|
||||
* @height: buffer height in pixels
|
||||
* @width: buffer width in pixels
|
||||
* @bpp: bits per pixel
|
||||
* @flags: must be zero
|
||||
* @handle: buffer object handle
|
||||
* @pitch: number of bytes between two consecutive lines
|
||||
* @size: size of the whole buffer in bytes
|
||||
*
|
||||
* User-space fills @height, @width, @bpp and @flags. If the IOCTL succeeds,
|
||||
* the kernel fills @handle, @pitch and @size.
|
||||
*/
|
||||
struct drm_mode_create_dumb {
|
||||
__u32 height;
|
||||
__u32 width;
|
||||
__u32 bpp;
|
||||
__u32 flags;
|
||||
/* handle, pitch, size will be returned */
|
||||
|
||||
__u32 handle;
|
||||
__u32 pitch;
|
||||
__u64 size;
|
||||
|
|
@ -918,11 +1082,53 @@ struct drm_mode_destroy_dumb {
|
|||
__u32 handle;
|
||||
};
|
||||
|
||||
/* page-flip flags are valid, plus: */
|
||||
/**
|
||||
* DRM_MODE_ATOMIC_TEST_ONLY
|
||||
*
|
||||
* Do not apply the atomic commit, instead check whether the hardware supports
|
||||
* this configuration.
|
||||
*
|
||||
* See &drm_mode_config_funcs.atomic_check for more details on test-only
|
||||
* commits.
|
||||
*/
|
||||
#define DRM_MODE_ATOMIC_TEST_ONLY 0x0100
|
||||
/**
|
||||
* DRM_MODE_ATOMIC_NONBLOCK
|
||||
*
|
||||
* Do not block while applying the atomic commit. The &DRM_IOCTL_MODE_ATOMIC
|
||||
* IOCTL returns immediately instead of waiting for the changes to be applied
|
||||
* in hardware. Note, the driver will still check that the update can be
|
||||
* applied before retuning.
|
||||
*/
|
||||
#define DRM_MODE_ATOMIC_NONBLOCK 0x0200
|
||||
/**
|
||||
* DRM_MODE_ATOMIC_ALLOW_MODESET
|
||||
*
|
||||
* Allow the update to result in temporary or transient visible artifacts while
|
||||
* the update is being applied. Applying the update may also take significantly
|
||||
* more time than a page flip. All visual artifacts will disappear by the time
|
||||
* the update is completed, as signalled through the vblank event's timestamp
|
||||
* (see struct drm_event_vblank).
|
||||
*
|
||||
* This flag must be set when the KMS update might cause visible artifacts.
|
||||
* Without this flag such KMS update will return a EINVAL error. What kind of
|
||||
* update may cause visible artifacts depends on the driver and the hardware.
|
||||
* User-space that needs to know beforehand if an update might cause visible
|
||||
* artifacts can use &DRM_MODE_ATOMIC_TEST_ONLY without
|
||||
* &DRM_MODE_ATOMIC_ALLOW_MODESET to see if it fails.
|
||||
*
|
||||
* To the best of the driver's knowledge, visual artifacts are guaranteed to
|
||||
* not appear when this flag is not set. Some sinks might display visual
|
||||
* artifacts outside of the driver's control.
|
||||
*/
|
||||
#define DRM_MODE_ATOMIC_ALLOW_MODESET 0x0400
|
||||
|
||||
/**
|
||||
* DRM_MODE_ATOMIC_FLAGS
|
||||
*
|
||||
* Bitfield of flags accepted by the &DRM_IOCTL_MODE_ATOMIC IOCTL in
|
||||
* &drm_mode_atomic.flags.
|
||||
*/
|
||||
#define DRM_MODE_ATOMIC_FLAGS (\
|
||||
DRM_MODE_PAGE_FLIP_EVENT |\
|
||||
DRM_MODE_PAGE_FLIP_ASYNC |\
|
||||
|
|
@ -1026,6 +1232,10 @@ struct drm_mode_destroy_blob {
|
|||
* struct drm_mode_create_lease - Create lease
|
||||
*
|
||||
* Lease mode resources, creating another drm_master.
|
||||
*
|
||||
* The @object_ids array must reference at least one CRTC, one connector and
|
||||
* one plane if &DRM_CLIENT_CAP_UNIVERSAL_PLANES is enabled. Alternatively,
|
||||
* the lease can be completely empty.
|
||||
*/
|
||||
struct drm_mode_create_lease {
|
||||
/** @object_ids: Pointer to array of object ids (__u32) */
|
||||
|
|
@ -1122,6 +1332,16 @@ struct drm_mode_rect {
|
|||
__s32 y2;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_mode_closefb
|
||||
* @fb_id: Framebuffer ID.
|
||||
* @pad: Must be zero.
|
||||
*/
|
||||
struct drm_mode_closefb {
|
||||
__u32 fb_id;
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue