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sync code with last improvements from OpenBSD

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This commit is contained in:
purplerain 2023-08-28 05:57:34 +00:00
commit 88965415ff
Signed by: purplerain
GPG key ID: F42C07F07E2E35B7
26235 changed files with 29195616 additions and 0 deletions
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2
lib/libdrm/tests/tegra/.gitignore vendored Normal file
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tegra-gr2d-fill
tegra-openclose

147
lib/libdrm/tests/tegra/drm-test-tegra.c Normal file
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/*
* Copyright © 2014 NVIDIA Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifdef HAVE_CONFIG_H
# include "config.h"
#endif
#include <errno.h>
#include <stdio.h>
#include "drm-test-tegra.h"
#include "tegra.h"
int drm_tegra_gr2d_open(struct drm_tegra *drm, struct drm_tegra_gr2d **gr2dp)
{
struct drm_tegra_gr2d *gr2d;
int err;
gr2d = calloc(1, sizeof(*gr2d));
if (!gr2d)
return -ENOMEM;
gr2d->drm = drm;
err = drm_tegra_channel_open(drm, DRM_TEGRA_GR2D, &gr2d->channel);
if (err < 0) {
free(gr2d);
return err;
}
*gr2dp = gr2d;
return 0;
}
int drm_tegra_gr2d_close(struct drm_tegra_gr2d *gr2d)
{
if (!gr2d)
return -EINVAL;
drm_tegra_channel_close(gr2d->channel);
free(gr2d);
return 0;
}
int drm_tegra_gr2d_fill(struct drm_tegra_gr2d *gr2d, struct drm_framebuffer *fb,
unsigned int x, unsigned int y, unsigned int width,
unsigned int height, uint32_t color)
{
struct drm_tegra_bo *fbo = fb->data;
struct drm_tegra_pushbuf *pushbuf;
struct drm_tegra_mapping *map;
struct drm_tegra_job *job;
uint32_t *ptr;
int err;
err = drm_tegra_job_new(gr2d->channel, &job);
if (err < 0)
return err;
err = drm_tegra_channel_map(gr2d->channel, fbo, 0, &map);
if (err < 0)
return err;
err = drm_tegra_job_get_pushbuf(job, &pushbuf);
if (err < 0)
return err;
err = drm_tegra_pushbuf_begin(pushbuf, 32, &ptr);
if (err < 0)
return err;
*ptr++ = HOST1X_OPCODE_SETCL(0, HOST1X_CLASS_GR2D, 0);
*ptr++ = HOST1X_OPCODE_MASK(0x9, 0x9);
*ptr++ = 0x0000003a;
*ptr++ = 0x00000000;
*ptr++ = HOST1X_OPCODE_MASK(0x1e, 0x7);
*ptr++ = 0x00000000;
*ptr++ = (2 << 16) | (1 << 6) | (1 << 2);
*ptr++ = 0x000000cc;
*ptr++ = HOST1X_OPCODE_MASK(0x2b, 0x9);
/* relocate destination buffer */
err = drm_tegra_pushbuf_relocate(pushbuf, &ptr, map, 0, 0, 0);
if (err < 0) {
fprintf(stderr, "failed to relocate buffer object: %d\n", err);
return err;
}
*ptr++ = fb->pitch;
*ptr++ = HOST1X_OPCODE_NONINCR(0x35, 1);
*ptr++ = color;
*ptr++ = HOST1X_OPCODE_NONINCR(0x46, 1);
*ptr++ = 0x00000000;
*ptr++ = HOST1X_OPCODE_MASK(0x38, 0x5);
*ptr++ = height << 16 | width;
*ptr++ = y << 16 | x;
err = drm_tegra_pushbuf_end(pushbuf, ptr);
if (err < 0) {
fprintf(stderr, "failed to update push buffer: %d\n", -err);
return err;
}
err = drm_tegra_job_submit(job, NULL);
if (err < 0) {
fprintf(stderr, "failed to submit job: %d\n", err);
return err;
}
err = drm_tegra_job_wait(job, 0);
if (err < 0) {
fprintf(stderr, "failed to wait for fence: %d\n", err);
return err;
}
drm_tegra_channel_unmap(map);
drm_tegra_job_free(job);
return 0;
}

55
lib/libdrm/tests/tegra/drm-test-tegra.h Normal file
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/*
* Copyright © 2014 NVIDIA Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef TEGRA_DRM_TEST_TEGRA_H
#define TEGRA_DRM_TEST_TEGRA_H
#include "drm-test.h"
#include "tegra.h"
#define HOST1X_OPCODE_SETCL(offset, classid, mask) \
((0x0 << 28) | (((offset) & 0xfff) << 16) | (((classid) & 0x3ff) << 6) | ((mask) & 0x3f))
#define HOST1X_OPCODE_INCR(offset, count) \
((0x1 << 28) | (((offset) & 0xfff) << 16) | ((count) & 0xffff))
#define HOST1X_OPCODE_NONINCR(offset, count) \
((0x2 << 28) | (((offset) & 0xfff) << 16) | ((count) & 0xffff))
#define HOST1X_OPCODE_MASK(offset, mask) \
((0x3 << 28) | (((offset) & 0xfff) << 16) | ((mask) & 0xffff))
#define HOST1X_OPCODE_IMM(offset, data) \
((0x4 << 28) | (((offset) & 0xfff) << 16) | ((data) & 0xffff))
#define HOST1X_OPCODE_EXTEND(subop, value) \
((0xe << 28) | (((subop) & 0xf) << 24) | ((value) & 0xffffff))
#define HOST1X_CLASS_GR2D 0x51
struct drm_tegra_gr2d {
struct drm_tegra *drm;
struct drm_tegra_channel *channel;
};
int drm_tegra_gr2d_open(struct drm_tegra *drm, struct drm_tegra_gr2d **gr2dp);
int drm_tegra_gr2d_close(struct drm_tegra_gr2d *gr2d);
int drm_tegra_gr2d_fill(struct drm_tegra_gr2d *gr2d, struct drm_framebuffer *fb,
unsigned int x, unsigned int y, unsigned int width,
unsigned int height, uint32_t color);
#endif

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/*
* Copyright © 2014 NVIDIA Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifdef HAVE_CONFIG_H
# include "config.h"
#endif
#include <errno.h>
#include <fcntl.h>
#include <stdbool.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include <sys/ioctl.h>
#include "xf86drm.h"
#include "xf86drmMode.h"
#include "drm_fourcc.h"
#include "drm-test.h"
static int drm_screen_probe_connector(struct drm_screen *screen,
drmModeConnectorPtr connector)
{
drmModeEncoderPtr encoder;
drmModeCrtcPtr crtc;
drmModeFBPtr fb;
encoder = drmModeGetEncoder(screen->fd, connector->encoder_id);
if (!encoder)
return -ENODEV;
crtc = drmModeGetCrtc(screen->fd, encoder->crtc_id);
if (!crtc) {
drmModeFreeEncoder(encoder);
return -ENODEV;
}
screen->old_fb = crtc->buffer_id;
fb = drmModeGetFB(screen->fd, crtc->buffer_id);
if (!fb) {
/* TODO: create new framebuffer */
drmModeFreeEncoder(encoder);
drmModeFreeCrtc(crtc);
return -ENOSYS;
}
screen->connector = connector->connector_id;
screen->old_fb = crtc->buffer_id;
screen->crtc = encoder->crtc_id;
/* TODO: check crtc->mode_valid */
screen->mode = crtc->mode;
screen->width = fb->width;
screen->height = fb->height;
screen->pitch = fb->pitch;
screen->depth = fb->depth;
screen->bpp = fb->bpp;
drmModeFreeEncoder(encoder);
drmModeFreeCrtc(crtc);
drmModeFreeFB(fb);
return 0;
}
int drm_screen_open(struct drm_screen **screenp, int fd)
{
drmModeConnectorPtr connector;
struct drm_screen *screen;
bool found = false;
drmModeResPtr res;
unsigned int i;
int err;
if (!screenp || fd < 0)
return -EINVAL;
screen = calloc(1, sizeof(*screen));
if (!screen)
return -ENOMEM;
screen->format = DRM_FORMAT_XRGB8888;
screen->fd = fd;
res = drmModeGetResources(fd);
if (!res) {
free(screen);
return -ENOMEM;
}
for (i = 0; i < (unsigned int)res->count_connectors; i++) {
connector = drmModeGetConnector(fd, res->connectors[i]);
if (!connector)
continue;
if (connector->connection != DRM_MODE_CONNECTED) {
drmModeFreeConnector(connector);
continue;
}
err = drm_screen_probe_connector(screen, connector);
if (err < 0) {
drmModeFreeConnector(connector);
continue;
}
drmModeFreeConnector(connector);
found = true;
break;
}
drmModeFreeResources(res);
if (!found) {
free(screen);
return -ENODEV;
}
*screenp = screen;
return 0;
}
int drm_screen_close(struct drm_screen *screen)
{
int err;
err = drmModeSetCrtc(screen->fd, screen->crtc, screen->old_fb, 0, 0,
&screen->connector, 1, &screen->mode);
if (err < 0) {
fprintf(stderr, "drmModeSetCrtc() failed: %m\n");
return -errno;
}
free(screen);
return 0;
}
int drm_framebuffer_new(struct drm_framebuffer **fbp,
struct drm_screen *screen, uint32_t handle,
unsigned int width, unsigned int height,
unsigned int pitch, uint32_t format,
void *data)
{
struct drm_framebuffer *fb;
uint32_t handles[4];
uint32_t pitches[4];
uint32_t offsets[4];
int err;
fb = calloc(1, sizeof(*fb));
if (!fb)
return -ENOMEM;
fb->fd = screen->fd;
fb->width = width;
fb->height = height;
fb->pitch = pitch;
fb->format = format;
fb->data = data;
handles[0] = handle;
pitches[0] = pitch;
offsets[0] = 0;
err = drmModeAddFB2(screen->fd, width, height, format, handles,
pitches, offsets, &fb->handle, 0);
if (err < 0)
return -errno;
*fbp = fb;
return 0;
}
int drm_framebuffer_free(struct drm_framebuffer *fb)
{
int err;
err = drmModeRmFB(fb->fd, fb->handle);
if (err < 0)
return -errno;
free(fb);
return 0;
}
int drm_screen_set_framebuffer(struct drm_screen *screen,
struct drm_framebuffer *fb)
{
int err;
err = drmModeSetCrtc(screen->fd, screen->crtc, fb->handle, 0, 0,
&screen->connector, 1, &screen->mode);
if (err < 0)
return -errno;
return 0;
}
int drm_open(const char *path)
{
int fd, err;
fd = open(path, O_RDWR);
if (fd < 0)
return -errno;
err = drmSetMaster(fd);
if (err < 0) {
close(fd);
return -errno;
}
return fd;
}
void drm_close(int fd)
{
drmDropMaster(fd);
close(fd);
}

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/*
* Copyright © 2014 NVIDIA Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef TEGRA_DRM_TEST_H
#define TEGRA_DRM_TEST_H
#include <stdint.h>
#include <stdlib.h>
#include "xf86drmMode.h"
struct drm_screen {
int fd;
unsigned int width;
unsigned int height;
unsigned int pitch;
unsigned int depth;
unsigned int bpp;
drmModeModeInfo mode;
uint32_t connector;
uint32_t old_fb;
uint32_t format;
uint32_t crtc;
};
struct drm_framebuffer {
unsigned int width;
unsigned int height;
unsigned int pitch;
uint32_t format;
uint32_t handle;
void *data;
int fd;
};
int drm_screen_open(struct drm_screen **screenp, int fd);
int drm_screen_close(struct drm_screen *screen);
int drm_screen_set_framebuffer(struct drm_screen *screen,
struct drm_framebuffer *fb);
int drm_framebuffer_new(struct drm_framebuffer **fbp,
struct drm_screen *screen, uint32_t handle,
unsigned int width, unsigned int height,
unsigned int pitch, uint32_t format,
void *data);
int drm_framebuffer_free(struct drm_framebuffer *fb);
int drm_open(const char *path);
void drm_close(int fd);
#endif

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/*
* Copyright © 2014 NVIDIA Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifdef HAVE_CONFIG_H
# include "config.h"
#endif
#include <errno.h>
#include <fcntl.h>
#include <stdbool.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include <sys/ioctl.h>
#include "xf86drm.h"
#include "xf86drmMode.h"
#include "drm_fourcc.h"
#include "drm-test-tegra.h"
#include "tegra.h"
int main(int argc, char *argv[])
{
uint32_t format = DRM_FORMAT_XRGB8888;
struct drm_tegra_gr2d *gr2d;
struct drm_framebuffer *fb;
struct drm_screen *screen;
unsigned int pitch, size;
struct drm_tegra_bo *bo;
struct drm_tegra *drm;
uint32_t handle;
int fd, err;
void *ptr;
fd = drm_open(argv[1]);
if (fd < 0) {
fprintf(stderr, "failed to open DRM device %s: %s\n", argv[1],
strerror(errno));
return 1;
}
err = drm_screen_open(&screen, fd);
if (err < 0) {
fprintf(stderr, "failed to open screen: %s\n", strerror(-err));
return 1;
}
err = drm_tegra_new(fd, &drm);
if (err < 0) {
fprintf(stderr, "failed to create Tegra DRM context: %s\n",
strerror(-err));
return 1;
}
err = drm_tegra_gr2d_open(drm, &gr2d);
if (err < 0) {
fprintf(stderr, "failed to open gr2d channel: %s\n",
strerror(-err));
return 1;
}
pitch = screen->width * screen->bpp / 8;
size = pitch * screen->height;
err = drm_tegra_bo_new(drm, 0, size, &bo);
if (err < 0) {
fprintf(stderr, "failed to create buffer object: %s\n",
strerror(-err));
return 1;
}
err = drm_tegra_bo_get_handle(bo, &handle);
if (err < 0) {
fprintf(stderr, "failed to get handle to buffer object: %s\n",
strerror(-err));
return 1;
}
err = drm_tegra_bo_map(bo, &ptr);
if (err < 0) {
fprintf(stderr, "failed to map buffer object: %s\n",
strerror(-err));
return 1;
}
memset(ptr, 0xff, size);
err = drm_framebuffer_new(&fb, screen, handle, screen->width,
screen->height, pitch, format, bo);
if (err < 0) {
fprintf(stderr, "failed to create framebuffer: %s\n",
strerror(-err));
return 1;
}
err = drm_screen_set_framebuffer(screen, fb);
if (err < 0) {
fprintf(stderr, "failed to display framebuffer: %s\n",
strerror(-err));
return 1;
}
sleep(1);
err = drm_tegra_gr2d_fill(gr2d, fb, fb->width / 4, fb->height / 4,
fb->width / 2, fb->height / 2, 0x00000000);
if (err < 0) {
fprintf(stderr, "failed to fill rectangle: %s\n",
strerror(-err));
return 1;
}
sleep(1);
drm_framebuffer_free(fb);
drm_tegra_bo_unref(bo);
drm_tegra_gr2d_close(gr2d);
drm_tegra_close(drm);
drm_screen_close(screen);
drm_close(fd);
return 0;
}

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lib/libdrm/tests/tegra/host1x.h Normal file
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/*
* Copyright © 2018 NVIDIA Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef HOST1X_H
#define HOST1X_H
#define HOST1X_OPCODE_SETCL(offset, classid, mask) \
((0x0 << 28) | (((offset) & 0xfff) << 16) | (((classid) & 0x3ff) << 6) | ((mask) & 0x3f))
#define HOST1X_OPCODE_INCR(offset, count) \
((0x1 << 28) | (((offset) & 0xfff) << 16) | ((count) & 0xffff))
#define HOST1X_CLASS_VIC 0x5d
#endif

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# Copyright © 2017 Intel Corporation
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
inc_tegra = include_directories('../../tegra')
libdrm_test = static_library(
'drm-test',
[files('drm-test.c', 'drm-test.h'), config_file ],
include_directories : [inc_root, inc_drm, inc_tegra],
link_with : libdrm,
)
libdrm_test_tegra = static_library(
'drm-test-tegra',
[files(
'drm-test-tegra.c',
'drm-test-tegra.h',
'vic.c',
'vic.h',
'vic30.c',
'vic30.h',
'vic40.c',
'vic40.h',
'vic41.c',
'vic41.h',
'vic42.c',
'vic42.h',
), config_file ],
include_directories : [inc_root, inc_drm, inc_tegra],
link_with : libdrm,
)
openclose = executable(
'tegra-openclose',
files('openclose.c'),
include_directories : [inc_root, inc_drm, inc_tegra],
c_args : libdrm_c_args,
link_with : [libdrm, libdrm_tegra],
install : with_install_tests,
)
gr2d_fill = executable(
'tegra-gr2d-fill',
files('gr2d-fill.c'),
include_directories : [inc_root, inc_drm, inc_tegra],
c_args : libdrm_c_args,
link_with : [libdrm, libdrm_tegra, libdrm_test, libdrm_test_tegra],
install : with_install_tests,
)
syncpt_wait = executable(
'tegra-syncpt-wait',
files('syncpt-wait.c'),
include_directories : [inc_root, inc_drm, inc_tegra],
c_args : libdrm_c_args,
link_with : [libdrm, libdrm_tegra, libdrm_test, libdrm_test_tegra],
install : with_install_tests,
)
syncpt_timeout = executable(
'tegra-syncpt-timeout',
files('syncpt-timeout.c'),
include_directories : [inc_root, inc_drm, inc_tegra],
c_args : libdrm_c_args,
link_with : [libdrm, libdrm_tegra, libdrm_test, libdrm_test_tegra],
install : with_install_tests,
)
vic_clear = executable(
'tegra-vic-clear',
files('vic-clear.c'),
include_directories : [inc_root, inc_drm, inc_tegra],
c_args : libdrm_c_args,
link_with : [libdrm, libdrm_tegra, libdrm_test, libdrm_test_tegra],
install : with_install_tests,
)
vic_blit = executable(
'tegra-vic-blit',
files('vic-blit.c'),
include_directories : [inc_root, inc_drm, inc_tegra],
c_args : libdrm_c_args,
link_with : [libdrm, libdrm_tegra, libdrm_test, libdrm_test_tegra],
install : with_install_tests,
)
vic_flip = executable(
'tegra-vic-flip',
files('vic-flip.c'),
include_directories : [inc_root, inc_drm, inc_tegra],
c_args : libdrm_c_args,
link_with : [libdrm, libdrm_tegra, libdrm_test, libdrm_test_tegra],
install : with_install_tests,
)

67
lib/libdrm/tests/tegra/openclose.c Normal file
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/*
* Copyright © 2014 NVIDIA Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <fcntl.h>
#include <stdio.h>
#include <unistd.h>
#include "xf86drm.h"
#include "tegra.h"
static const char default_device[] = "/dev/dri/card0";
int main(int argc, char *argv[])
{
struct drm_tegra *tegra;
drmVersionPtr version;
const char *device;
int err, fd;
if (argc < 2)
device = default_device;
else
device = argv[1];
fd = open(device, O_RDWR);
if (fd < 0)
return 1;
version = drmGetVersion(fd);
if (version) {
printf("Version: %d.%d.%d\n", version->version_major,
version->version_minor, version->version_patchlevel);
printf(" Name: %s\n", version->name);
printf(" Date: %s\n", version->date);
printf(" Description: %s\n", version->desc);
drmFreeVersion(version);
}
err = drm_tegra_new(fd, &tegra);
if (err < 0)
return 1;
drm_tegra_close(tegra);
close(fd);
return 0;
}

163
lib/libdrm/tests/tegra/syncpt-timeout.c Normal file
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/*
* Copyright © 2018 NVIDIA Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <errno.h>
#include <fcntl.h>
#include <stdio.h>
#include <string.h>
#include <unistd.h>
#include "tegra.h"
#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
static int channel_open(struct drm_tegra *drm,
struct drm_tegra_channel **channel)
{
static const struct {
enum drm_tegra_class class;
const char *name;
} classes[] = {
{ DRM_TEGRA_VIC, "VIC" },
{ DRM_TEGRA_GR2D, "GR2D" },
};
unsigned int i;
int err;
for (i = 0; i < ARRAY_SIZE(classes); i++) {
err = drm_tegra_channel_open(drm, classes[i].class, channel);
if (err < 0) {
fprintf(stderr, "failed to open channel to %s: %s\n",
classes[i].name, strerror(-err));
continue;
}
break;
}
return err;
}
int main(int argc, char *argv[])
{
const char *device = "/dev/dri/renderD128";
struct drm_tegra_syncpoint *syncpt;
struct drm_tegra_channel *channel;
struct drm_tegra_pushbuf *pushbuf;
struct drm_tegra_job *job;
struct drm_tegra *drm;
uint32_t *ptr;
int fd, err;
if (argc > 1)
device = argv[1];
fd = open(device, O_RDWR);
if (fd < 0) {
fprintf(stderr, "open() failed: %s\n", strerror(errno));
return 1;
}
err = drm_tegra_new(fd, &drm);
if (err < 0) {
fprintf(stderr, "failed to open Tegra device: %s\n", strerror(-err));
close(fd);
return 1;
}
err = drm_tegra_syncpoint_new(drm, &syncpt);
if (err < 0) {
fprintf(stderr, "failed to allocate syncpoint: %s\n", strerror(-err));
drm_tegra_close(drm);
close(fd);
return 1;
}
err = channel_open(drm, &channel);
if (err < 0) {
fprintf(stderr, "failed to open channel: %s\n", strerror(-err));
return 1;
}
err = drm_tegra_job_new(channel, &job);
if (err < 0) {
fprintf(stderr, "failed to create job: %s\n", strerror(-err));
return 1;
}
err = drm_tegra_job_get_pushbuf(job, &pushbuf);
if (err < 0) {
fprintf(stderr, "failed to create push buffer: %s\n", strerror(-err));
return 1;
}
err = drm_tegra_pushbuf_begin(pushbuf, 8, &ptr);
if (err < 0) {
fprintf(stderr, "failed to prepare push buffer: %s\n", strerror(-err));
return 1;
}
/*
* Empty command streams will be rejected, so we use this as an easy way
* to add something to the command stream. But this could be any other,
* valid command stream.
*/
err = drm_tegra_pushbuf_sync_cond(pushbuf, &ptr, syncpt,
DRM_TEGRA_SYNC_COND_IMMEDIATE);
if (err < 0) {
fprintf(stderr, "failed to push syncpoint: %s\n", strerror(-err));
return 1;
}
/* pretend that the syncpoint was incremented a second time */
err = drm_tegra_pushbuf_sync(pushbuf, syncpt, 1);
if (err < 0) {
fprintf(stderr, "failed to push syncpoint: %s\n", strerror(-err));
return 1;
}
err = drm_tegra_pushbuf_end(pushbuf, ptr);
if (err < 0) {
fprintf(stderr, "failed to update push buffer: %s\n", strerror(-err));
return 1;
}
err = drm_tegra_job_submit(job, NULL);
if (err < 0) {
fprintf(stderr, "failed to submit job: %s\n", strerror(-err));
return 1;
}
err = drm_tegra_job_wait(job, 250000);
if (err < 0) {
fprintf(stderr, "failed to wait for job: %s\n", strerror(-err));
return 1;
}
drm_tegra_job_free(job);
drm_tegra_channel_close(channel);
drm_tegra_syncpoint_free(syncpt);
drm_tegra_close(drm);
close(fd);
return 0;
}

151
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/*
* Copyright © 2018 NVIDIA Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <errno.h>
#include <fcntl.h>
#include <stdio.h>
#include <string.h>
#include <unistd.h>
#include "tegra.h"
#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
static int channel_open(struct drm_tegra *drm,
struct drm_tegra_channel **channel)
{
static const struct {
enum drm_tegra_class class;
const char *name;
} classes[] = {
{ DRM_TEGRA_VIC, "VIC" },
{ DRM_TEGRA_GR2D, "GR2D" },
};
unsigned int i;
int err;
for (i = 0; i < ARRAY_SIZE(classes); i++) {
err = drm_tegra_channel_open(drm, classes[i].class, channel);
if (err < 0) {
fprintf(stderr, "failed to open channel to %s: %s\n",
classes[i].name, strerror(-err));
continue;
}
break;
}
return err;
}
int main(int argc, char *argv[])
{
const char *device = "/dev/dri/renderD128";
struct drm_tegra_syncpoint *syncpt;
struct drm_tegra_channel *channel;
struct drm_tegra_pushbuf *pushbuf;
struct drm_tegra_job *job;
struct drm_tegra *drm;
uint32_t *ptr;
int fd, err;
if (argc > 1)
device = argv[1];
fd = open(device, O_RDWR);
if (fd < 0) {
fprintf(stderr, "open() failed: %s\n", strerror(errno));
return 1;
}
err = drm_tegra_new(fd, &drm);
if (err < 0) {
fprintf(stderr, "failed to open Tegra device: %s\n", strerror(-err));
close(fd);
return 1;
}
err = drm_tegra_syncpoint_new(drm, &syncpt);
if (err < 0) {
fprintf(stderr, "failed to allocate syncpoint: %s\n", strerror(-err));
drm_tegra_close(drm);
close(fd);
return 1;
}
err = channel_open(drm, &channel);
if (err < 0) {
fprintf(stderr, "failed to open channel: %s\n", strerror(-err));
return 1;
}
err = drm_tegra_job_new(channel, &job);
if (err < 0) {
fprintf(stderr, "failed to create job: %s\n", strerror(-err));
return 1;
}
err = drm_tegra_job_get_pushbuf(job, &pushbuf);
if (err < 0) {
fprintf(stderr, "failed to create push buffer: %s\n", strerror(-err));
return 1;
}
err = drm_tegra_pushbuf_begin(pushbuf, 4, &ptr);
if (err < 0) {
fprintf(stderr, "failed to prepare push buffer: %s\n", strerror(-err));
return 1;
}
err = drm_tegra_pushbuf_sync_cond(pushbuf, &ptr, syncpt,
DRM_TEGRA_SYNC_COND_IMMEDIATE);
if (err < 0) {
fprintf(stderr, "failed to push syncpoint: %s\n", strerror(-err));
return 1;
}
err = drm_tegra_pushbuf_end(pushbuf, ptr);
if (err < 0) {
fprintf(stderr, "failed to update push buffer: %s\n", strerror(-err));
return 1;
}
err = drm_tegra_job_submit(job, NULL);
if (err < 0) {
fprintf(stderr, "failed to submit job: %s\n", strerror(-err));
return 1;
}
err = drm_tegra_job_wait(job, 250000000);
if (err < 0) {
fprintf(stderr, "failed to wait for job: %s\n", strerror(-err));
return 1;
}
drm_tegra_job_free(job);
drm_tegra_channel_close(channel);
drm_tegra_syncpoint_free(syncpt);
drm_tegra_close(drm);
close(fd);
return 0;
}

333
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/*
* Copyright © 2018 NVIDIA Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <errno.h>
#include <fcntl.h>
#include <stdio.h>
#include <string.h>
#include <unistd.h>
#include "tegra.h"
#include "host1x.h"
#include "vic.h"
/* clear output image to red */
static int clear(struct vic *vic, struct drm_tegra_channel *channel,
struct vic_image *output)
{
struct drm_tegra_pushbuf *pushbuf;
struct drm_tegra_job *job;
uint32_t *ptr;
int err;
err = drm_tegra_job_new(channel, &job);
if (err < 0) {
fprintf(stderr, "failed to create job: %s\n", strerror(-err));
return 1;
}
err = drm_tegra_job_get_pushbuf(job, &pushbuf);
if (err < 0) {
fprintf(stderr, "failed to create push buffer: %s\n", strerror(-err));
return 1;
}
err = vic_clear(vic, output, 1023, 1023, 0, 0);
if (err < 0) {
fprintf(stderr, "failed to clear surface: %s\n", strerror(-err));
return err;
}
err = drm_tegra_pushbuf_begin(pushbuf, 32, &ptr);
if (err < 0) {
fprintf(stderr, "failed to prepare push buffer: %s\n", strerror(-err));
return err;
}
err = vic->ops->execute(vic, pushbuf, &ptr, output, NULL, 0);
if (err < 0) {
fprintf(stderr, "failed to execute operation: %s\n", strerror(-err));
return err;
}
err = drm_tegra_pushbuf_sync_cond(pushbuf, &ptr, vic->syncpt,
DRM_TEGRA_SYNC_COND_OP_DONE);
if (err < 0) {
fprintf(stderr, "failed to push syncpoint: %s\n", strerror(-err));
return err;
}
err = drm_tegra_pushbuf_end(pushbuf, ptr);
if (err < 0) {
fprintf(stderr, "failed to update push buffer: %s\n", strerror(-err));
return err;
}
err = drm_tegra_job_submit(job, NULL);
if (err < 0) {
fprintf(stderr, "failed to submit job: %s\n", strerror(-err));
return err;
}
err = drm_tegra_job_wait(job, 1000000000);
if (err < 0) {
fprintf(stderr, "failed to wait for job: %s\n", strerror(-err));
return err;
}
drm_tegra_job_free(job);
return 0;
}
/* fill bottom half of image to blue */
static int fill(struct vic *vic, struct drm_tegra_channel *channel,
struct vic_image *output)
{
struct drm_tegra_pushbuf *pushbuf;
struct drm_tegra_job *job;
uint32_t *ptr;
int err;
err = drm_tegra_job_new(channel, &job);
if (err < 0) {
fprintf(stderr, "failed to create job: %s\n", strerror(-err));
return 1;
}
err = drm_tegra_job_get_pushbuf(job, &pushbuf);
if (err < 0) {
fprintf(stderr, "failed to create push buffer: %s\n", strerror(-err));
return 1;
}
err = drm_tegra_pushbuf_begin(pushbuf, 32, &ptr);
if (err < 0) {
fprintf(stderr, "failed to prepare push buffer: %s\n", strerror(-err));
return err;
}
err = vic->ops->fill(vic, output, 0, output->height / 2, output->width - 1,
output->height -1, 1023, 0, 0, 1023);
if (err < 0) {
fprintf(stderr, "failed to fill surface: %s\n", strerror(-err));
return err;
}
err = vic->ops->execute(vic, pushbuf, &ptr, output, NULL, 0);
if (err < 0) {
fprintf(stderr, "failed to execute operation: %s\n", strerror(-err));
return err;
}
err = drm_tegra_pushbuf_sync_cond(pushbuf, &ptr, vic->syncpt,
DRM_TEGRA_SYNC_COND_OP_DONE);
if (err < 0) {
fprintf(stderr, "failed to push syncpoint: %s\n", strerror(-err));
return err;
}
err = drm_tegra_pushbuf_end(pushbuf, ptr);
if (err < 0) {
fprintf(stderr, "failed to update push buffer: %s\n", strerror(-err));
return err;
}
err = drm_tegra_job_submit(job, NULL);
if (err < 0) {
fprintf(stderr, "failed to submit job: %s\n", strerror(-err));
return err;
}
err = drm_tegra_job_wait(job, 1000000000);
if (err < 0) {
fprintf(stderr, "failed to wait for job: %s\n", strerror(-err));
return err;
}
drm_tegra_job_free(job);
return 0;
}
/* blit image */
static int blit(struct vic *vic, struct drm_tegra_channel *channel,
struct vic_image *output, struct vic_image *input)
{
struct drm_tegra_pushbuf *pushbuf;
struct drm_tegra_job *job;
uint32_t *ptr;
int err;
err = drm_tegra_job_new(channel, &job);
if (err < 0) {
fprintf(stderr, "failed to create job: %s\n", strerror(-err));
return 1;
}
err = drm_tegra_job_get_pushbuf(job, &pushbuf);
if (err < 0) {
fprintf(stderr, "failed to create push buffer: %s\n", strerror(-err));
return 1;
}
err = drm_tegra_pushbuf_begin(pushbuf, 32, &ptr);
if (err < 0) {
fprintf(stderr, "failed to prepare push buffer: %s\n", strerror(-err));
return err;
}
err = vic->ops->blit(vic, output, input);
if (err < 0) {
fprintf(stderr, "failed to blit surface: %s\n", strerror(-err));
return err;
}
err = vic->ops->execute(vic, pushbuf, &ptr, output, &input, 1);
if (err < 0) {
fprintf(stderr, "failed to execute operation: %s\n", strerror(-err));
return err;
}
err = drm_tegra_pushbuf_sync_cond(pushbuf, &ptr, vic->syncpt,
DRM_TEGRA_SYNC_COND_OP_DONE);
if (err < 0) {
fprintf(stderr, "failed to push syncpoint: %s\n", strerror(-err));
return err;
}
err = drm_tegra_pushbuf_end(pushbuf, ptr);
if (err < 0) {
fprintf(stderr, "failed to update push buffer: %s\n", strerror(-err));
return err;
}
err = drm_tegra_job_submit(job, NULL);
if (err < 0) {
fprintf(stderr, "failed to submit job: %s\n", strerror(-err));
return err;
}
err = drm_tegra_job_wait(job, 1000000000);
if (err < 0) {
fprintf(stderr, "failed to wait for job: %s\n", strerror(-err));
return err;
}
drm_tegra_job_free(job);
return 0;
}
int main(int argc, char *argv[])
{
const unsigned int format = VIC_PIXEL_FORMAT_A8R8G8B8;
const unsigned int kind = VIC_BLK_KIND_PITCH;
const unsigned int width = 16, height = 16;
const char *device = "/dev/dri/renderD128";
struct drm_tegra_channel *channel;
struct vic_image *input, *output;
struct drm_tegra *drm;
unsigned int version;
struct vic *vic;
int fd, err;
if (argc > 1)
device = argv[1];
fd = open(device, O_RDWR);
if (fd < 0) {
fprintf(stderr, "open() failed: %s\n", strerror(errno));
return 1;
}
err = drm_tegra_new(fd, &drm);
if (err < 0) {
fprintf(stderr, "failed to open Tegra device: %s\n", strerror(-err));
close(fd);
return 1;
}
err = drm_tegra_channel_open(drm, DRM_TEGRA_VIC, &channel);
if (err < 0) {
fprintf(stderr, "failed to open channel to VIC: %s\n", strerror(-err));
return 1;
}
version = drm_tegra_channel_get_version(channel);
printf("version: %08x\n", version);
err = vic_new(drm, channel, &vic);
if (err < 0) {
fprintf(stderr, "failed to create VIC: %s\n", strerror(-err));
return 1;
}
err = vic_image_new(vic, width, height, format, kind, DRM_TEGRA_CHANNEL_MAP_READ_WRITE,
&input);
if (err < 0) {
fprintf(stderr, "failed to create input image: %d\n", err);
return 1;
}
err = vic_image_new(vic, width, height, format, kind, DRM_TEGRA_CHANNEL_MAP_READ_WRITE,
&output);
if (err < 0) {
fprintf(stderr, "failed to create output image: %d\n", err);
return 1;
}
err = clear(vic, channel, input);
if (err < 0) {
fprintf(stderr, "failed to clear image: %s\n", strerror(-err));
return 1;
}
err = fill(vic, channel, input);
if (err < 0) {
fprintf(stderr, "failed to fill rectangle: %s\n", strerror(-err));
return 1;
}
err = blit(vic, channel, output, input);
if (err < 0) {
fprintf(stderr, "failed to blit image: %s\n", strerror(-err));
return 1;
}
printf("input: %ux%u\n", input->width, input->height);
vic_image_dump(input, stdout);
printf("output: %ux%u\n", output->width, output->height);
vic_image_dump(output, stdout);
vic_image_free(output);
vic_image_free(input);
vic_free(vic);
drm_tegra_channel_close(channel);
drm_tegra_close(drm);
close(fd);
return 0;
}

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/*
* Copyright © 2018 NVIDIA Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <errno.h>
#include <fcntl.h>
#include <stdio.h>
#include <string.h>
#include <unistd.h>
#include "util_math.h"
#include "tegra.h"
#include "host1x.h"
#include "vic.h"
#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
int main(int argc, char *argv[])
{
const unsigned int format = VIC_PIXEL_FORMAT_A8R8G8B8;
const unsigned int kind = VIC_BLK_KIND_PITCH;
const unsigned int width = 16, height = 16;
const char *device = "/dev/dri/renderD128";
struct drm_tegra_channel *channel;
struct drm_tegra_pushbuf *pushbuf;
struct drm_tegra_job *job;
struct vic_image *output;
struct drm_tegra *drm;
unsigned int version;
struct vic *vic;
uint32_t *pb;
int fd, err;
void *ptr;
if (argc > 1)
device = argv[1];
fd = open(device, O_RDWR);
if (fd < 0) {
fprintf(stderr, "open() failed: %s\n", strerror(errno));
return 1;
}
err = drm_tegra_new(fd, &drm);
if (err < 0) {
fprintf(stderr, "failed to open Tegra device: %s\n", strerror(-err));
close(fd);
return 1;
}
err = drm_tegra_channel_open(drm, DRM_TEGRA_VIC, &channel);
if (err < 0) {
fprintf(stderr, "failed to open channel to VIC: %s\n", strerror(-err));
return 1;
}
version = drm_tegra_channel_get_version(channel);
printf("version: %08x\n", version);
err = vic_new(drm, channel, &vic);
if (err < 0) {
fprintf(stderr, "failed to create VIC: %s\n", strerror(-err));
return 1;
}
err = vic_image_new(vic, width, height, format, kind, DRM_TEGRA_CHANNEL_MAP_READ_WRITE,
&output);
if (err < 0) {
fprintf(stderr, "failed to create output image: %d\n", err);
return 1;
}
printf("image: %zu bytes\n", output->size);
err = drm_tegra_bo_map(output->bo, &ptr);
if (err < 0) {
fprintf(stderr, "failed to map output image: %d\n", err);
return 1;
}
memset(ptr, 0xff, output->size);
drm_tegra_bo_unmap(output->bo);
printf("output: %ux%u\n", output->width, output->height);
vic_image_dump(output, stdout);
err = drm_tegra_job_new(channel, &job);
if (err < 0) {
fprintf(stderr, "failed to create job: %s\n", strerror(-err));
return 1;
}
err = drm_tegra_job_get_pushbuf(job, &pushbuf);
if (err < 0) {
fprintf(stderr, "failed to create push buffer: %s\n", strerror(-err));
return 1;
}
err = drm_tegra_pushbuf_begin(pushbuf, 32, &pb);
if (err < 0) {
fprintf(stderr, "failed to prepare push buffer: %s\n", strerror(-err));
return 1;
}
err = vic_clear(vic, output, 1023, 0, 0, 1023);
if (err < 0) {
fprintf(stderr, "failed to clear surface: %s\n", strerror(-err));
return err;
}
err = vic->ops->execute(vic, pushbuf, &pb, output, NULL, 0);
if (err < 0) {
fprintf(stderr, "failed to execute operation: %s\n", strerror(-err));
return 1;
}
err = drm_tegra_pushbuf_sync_cond(pushbuf, &pb, vic->syncpt,
DRM_TEGRA_SYNC_COND_OP_DONE);
if (err < 0) {
fprintf(stderr, "failed to push syncpoint: %s\n", strerror(-err));
return 1;
}
err = drm_tegra_pushbuf_end(pushbuf, pb);
if (err < 0) {
fprintf(stderr, "failed to update push buffer: %s\n", strerror(-err));
return 1;
}
err = drm_tegra_job_submit(job, NULL);
if (err < 0) {
fprintf(stderr, "failed to submit job: %s\n", strerror(-err));
return 1;
}
err = drm_tegra_job_wait(job, 1000000000);
if (err < 0) {
fprintf(stderr, "failed to wait for job: %s\n", strerror(-err));
return 1;
}
printf("output: %ux%u\n", output->width, output->height);
vic_image_dump(output, stdout);
drm_tegra_job_free(job);
vic_image_free(output);
vic_free(vic);
drm_tegra_channel_close(channel);
drm_tegra_close(drm);
close(fd);
return 0;
}

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/*
* Copyright © 2018 NVIDIA Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <errno.h>
#include <fcntl.h>
#include <stdio.h>
#include <string.h>
#include <unistd.h>
#include "tegra.h"
#include "host1x.h"
#include "vic.h"
/* clear output image to red */
static int clear(struct vic *vic, struct drm_tegra_channel *channel,
struct vic_image *output)
{
struct drm_tegra_pushbuf *pushbuf;
struct drm_tegra_job *job;
uint32_t *ptr;
int err;
err = drm_tegra_job_new(channel, &job);
if (err < 0) {
fprintf(stderr, "failed to create job: %s\n", strerror(-err));
return 1;
}
err = drm_tegra_job_get_pushbuf(job, &pushbuf);
if (err < 0) {
fprintf(stderr, "failed to create push buffer: %s\n", strerror(-err));
return 1;
}
err = drm_tegra_pushbuf_begin(pushbuf, 32, &ptr);
if (err < 0) {
fprintf(stderr, "failed to prepare push buffer: %s\n", strerror(-err));
return err;
}
err = vic_clear(vic, output, 1023, 0, 0, 1023);
if (err < 0) {
fprintf(stderr, "failed to clear surface: %s\n", strerror(-err));
return err;
}
err = vic->ops->execute(vic, pushbuf, &ptr, output, NULL, 0);
if (err < 0) {
fprintf(stderr, "failed to execute operation: %s\n", strerror(-err));
return err;
}
err = drm_tegra_pushbuf_sync_cond(pushbuf, &ptr, vic->syncpt,
DRM_TEGRA_SYNC_COND_OP_DONE);
if (err < 0) {
fprintf(stderr, "failed to push syncpoint: %s\n", strerror(-err));
return err;
}
err = drm_tegra_pushbuf_end(pushbuf, ptr);
if (err < 0) {
fprintf(stderr, "failed to update push buffer: %s\n", strerror(-err));
return err;
}
err = drm_tegra_job_submit(job, NULL);
if (err < 0) {
fprintf(stderr, "failed to submit job: %s\n", strerror(-err));
return err;
}
err = drm_tegra_job_wait(job, 1000000000);
if (err < 0) {
fprintf(stderr, "failed to wait for job: %s\n", strerror(-err));
return err;
}
drm_tegra_job_free(job);
return 0;
}
/* fill bottom half of image to blue */
static int fill(struct vic *vic, struct drm_tegra_channel *channel,
struct vic_image *output)
{
struct drm_tegra_pushbuf *pushbuf;
struct drm_tegra_job *job;
uint32_t *ptr;
int err;
err = drm_tegra_job_new(channel, &job);
if (err < 0) {
fprintf(stderr, "failed to create job: %s\n", strerror(-err));
return 1;
}
err = drm_tegra_job_get_pushbuf(job, &pushbuf);
if (err < 0) {
fprintf(stderr, "failed to create push buffer: %s\n", strerror(-err));
return 1;
}
err = drm_tegra_pushbuf_begin(pushbuf, 32, &ptr);
if (err < 0) {
fprintf(stderr, "failed to prepare push buffer: %s\n", strerror(-err));
return err;
}
err = vic->ops->fill(vic, output, 0, output->height / 2, output->width - 1,
output->height - 1, 0, 0, 1023, 1023);
if (err < 0) {
fprintf(stderr, "failed ot fill surface: %s\n", strerror(-err));
return err;
}
err = vic->ops->execute(vic, pushbuf, &ptr, output, NULL, 0);
if (err < 0) {
fprintf(stderr, "failed to execute operation: %s\n", strerror(-err));
return err;
}
err = drm_tegra_pushbuf_sync_cond(pushbuf, &ptr, vic->syncpt,
DRM_TEGRA_SYNC_COND_OP_DONE);
if (err < 0) {
fprintf(stderr, "failed to push syncpoint: %s\n", strerror(-err));
return err;
}
err = drm_tegra_pushbuf_end(pushbuf, ptr);
if (err < 0) {
fprintf(stderr, "failed to update push buffer: %s\n", strerror(-err));
return err;
}
err = drm_tegra_job_submit(job, NULL);
if (err < 0) {
fprintf(stderr, "failed to submit job: %s\n", strerror(-err));
return err;
}
err = drm_tegra_job_wait(job, 1000000000);
if (err < 0) {
fprintf(stderr, "failed to wait for job: %s\n", strerror(-err));
return err;
}
drm_tegra_job_free(job);
return 0;
}
/* flip image vertically */
static int flip(struct vic *vic, struct drm_tegra_channel *channel,
struct vic_image *output, struct vic_image *input)
{
struct drm_tegra_pushbuf *pushbuf;
struct drm_tegra_job *job;
uint32_t *ptr;
int err;
err = drm_tegra_job_new(channel, &job);
if (err < 0) {
fprintf(stderr, "failed to create job: %s\n", strerror(-err));
return 1;
}
err = drm_tegra_job_get_pushbuf(job, &pushbuf);
if (err < 0) {
fprintf(stderr, "failed to create push buffer: %s\n", strerror(-err));
return 1;
}
err = drm_tegra_pushbuf_begin(pushbuf, 32, &ptr);
if (err < 0) {
fprintf(stderr, "failed to prepare push buffer: %s\n", strerror(-err));
return err;
}
err = vic->ops->flip(vic, output, input);
if (err < 0) {
fprintf(stderr, "failed to flip: %s\n", strerror(-err));
return err;
}
err = vic->ops->execute(vic, pushbuf, &ptr, output, &input, 1);
if (err < 0) {
fprintf(stderr, "failed to execute operation: %s\n", strerror(-err));
return err;
}
err = drm_tegra_pushbuf_sync_cond(pushbuf, &ptr, vic->syncpt,
DRM_TEGRA_SYNC_COND_OP_DONE);
if (err < 0) {
fprintf(stderr, "failed to push syncpoint: %s\n", strerror(-err));
return err;
}
err = drm_tegra_pushbuf_end(pushbuf, ptr);
if (err < 0) {
fprintf(stderr, "failed to update push buffer: %s\n", strerror(-err));
return err;
}
err = drm_tegra_job_submit(job, NULL);
if (err < 0) {
fprintf(stderr, "failed to submit job: %s\n", strerror(-err));
return err;
}
err = drm_tegra_job_wait(job, 1000000000);
if (err < 0) {
fprintf(stderr, "failed to wait for job: %s\n", strerror(-err));
return err;
}
drm_tegra_job_free(job);
return 0;
}
int main(int argc, char *argv[])
{
const unsigned int format = VIC_PIXEL_FORMAT_A8R8G8B8;
const unsigned int kind = VIC_BLK_KIND_PITCH;
const unsigned int width = 16, height = 16;
const char *device = "/dev/dri/renderD128";
struct drm_tegra_channel *channel;
struct vic_image *input, *output;
struct drm_tegra *drm;
unsigned int version;
struct vic *vic;
int fd, err;
if (argc > 1)
device = argv[1];
fd = open(device, O_RDWR);
if (fd < 0) {
fprintf(stderr, "open() failed: %s\n", strerror(errno));
return 1;
}
err = drm_tegra_new(fd, &drm);
if (err < 0) {
fprintf(stderr, "failed to open Tegra device: %s\n", strerror(-err));
close(fd);
return 1;
}
err = drm_tegra_channel_open(drm, DRM_TEGRA_VIC, &channel);
if (err < 0) {
fprintf(stderr, "failed to open channel to VIC: %s\n", strerror(-err));
return 1;
}
version = drm_tegra_channel_get_version(channel);
printf("version: %08x\n", version);
err = vic_new(drm, channel, &vic);
if (err < 0) {
fprintf(stderr, "failed to create VIC: %s\n", strerror(-err));
return 1;
}
err = vic_image_new(vic, width, height, format, kind, DRM_TEGRA_CHANNEL_MAP_READ_WRITE,
&input);
if (err < 0) {
fprintf(stderr, "failed to create input image: %d\n", err);
return 1;
}
err = vic_image_new(vic, width, height, format, kind, DRM_TEGRA_CHANNEL_MAP_READ_WRITE,
&output);
if (err < 0) {
fprintf(stderr, "failed to create output image: %d\n", err);
return 1;
}
err = clear(vic, channel, input);
if (err < 0) {
fprintf(stderr, "failed to clear image: %s\n", strerror(-err));
return 1;
}
err = fill(vic, channel, input);
if (err < 0) {
fprintf(stderr, "failed to fill rectangle: %s\n", strerror(-err));
return 1;
}
err = flip(vic, channel, output, input);
if (err < 0) {
fprintf(stderr, "failed to flip image: %s\n", strerror(-err));
return 1;
}
printf("input: %ux%u\n", input->width, input->height);
vic_image_dump(input, stdout);
printf("output: %ux%u\n", output->width, output->height);
vic_image_dump(output, stdout);
vic_image_free(output);
vic_image_free(input);
vic_free(vic);
drm_tegra_channel_close(channel);
drm_tegra_close(drm);
close(fd);
return 0;
}

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/*
* Copyright © 2018 NVIDIA Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <errno.h>
#include <stdio.h> /* XXX remove */
#include <stdlib.h>
#include "util_math.h"
#include "tegra.h"
#include "host1x.h"
#include "vic.h"
#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
const struct vic_format_info *vic_format_get_info(unsigned int format)
{
static const struct vic_format_info formats[] = {
{ .format = VIC_PIXEL_FORMAT_A8R8G8B8, .cpp = 4 },
};
unsigned int i;
for (i = 0; i < ARRAY_SIZE(formats); i++) {
if (formats[i].format == format)
return &formats[i];
}
return 0;
}
int vic_image_new(struct vic *vic, unsigned int width, unsigned int height,
unsigned int format, unsigned int kind, uint32_t flags,
struct vic_image **imagep)
{
const struct vic_format_info *info = vic_format_get_info(format);
struct vic_image *image;
int err;
if (!info)
return -EINVAL;
image = calloc(1, sizeof(*image));
if (!image)
return -ENOMEM;
if (kind == VIC_BLK_KIND_PITCH)
image->align = 256;
else
image->align = 256; /* XXX */
image->width = width;
image->stride = ALIGN(width, image->align);
image->pitch = image->stride * info->cpp;
image->height = height;
image->format = format;
image->kind = kind;
image->size = image->pitch * image->height;
printf("image: %ux%u align: %zu stride: %u pitch: %u size: %zu\n",
image->width, image->height, image->align, image->stride,
image->pitch, image->size);
err = drm_tegra_bo_new(vic->drm, 0, image->size, &image->bo);
if (err < 0) {
free(image);
return err;
}
err = drm_tegra_channel_map(vic->channel, image->bo, flags, &image->map);
if (err < 0) {
drm_tegra_bo_unref(image->bo);
free(image);
return err;
}
*imagep = image;
return 0;
}
void vic_image_free(struct vic_image *image)
{
if (image) {
drm_tegra_channel_unmap(image->map);
drm_tegra_bo_unref(image->bo);
free(image);
}
}
void vic_image_dump(struct vic_image *image, FILE *fp)
{
unsigned int i, j;
void *ptr;
int err;
err = drm_tegra_bo_map(image->bo, &ptr);
if (err < 0)
return;
for (j = 0; j < image->height; j++) {
uint32_t *pixels = (uint32_t *)((unsigned long)ptr + j * image->pitch);
printf(" ");
for (i = 0; i < image->width; i++)
printf(" %08x", pixels[i]);
printf("\n");
}
drm_tegra_bo_unmap(image->bo);
}
/* from vic30.c */
int vic30_new(struct drm_tegra *drm, struct drm_tegra_channel *channel,
struct vic **vicp);
/* from vic40.c */
int vic40_new(struct drm_tegra *drm, struct drm_tegra_channel *channel,
struct vic **vicp);
/* from vic41.c */
int vic41_new(struct drm_tegra *drm, struct drm_tegra_channel *channel,
struct vic **vicp);
/* from vic42.c */
int vic42_new(struct drm_tegra *drm, struct drm_tegra_channel *channel,
struct vic **vicp);
int vic_new(struct drm_tegra *drm, struct drm_tegra_channel *channel,
struct vic **vicp)
{
unsigned int version;
version = drm_tegra_channel_get_version(channel);
switch (version) {
case 0x40:
return vic30_new(drm, channel, vicp);
case 0x21:
return vic40_new(drm, channel, vicp);
case 0x18:
return vic41_new(drm, channel, vicp);
case 0x19:
return vic42_new(drm, channel, vicp);
}
return -ENOTSUP;
}
void vic_free(struct vic *vic)
{
if (vic)
vic->ops->free(vic);
}
int vic_clear(struct vic *vic, struct vic_image *output, unsigned int alpha,
unsigned int red, unsigned int green, unsigned int blue)
{
return vic->ops->fill(vic, output, 0, 0, output->width - 1,
output->height - 1, alpha, red, green, blue);
}

181
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/*
* Copyright © 2018 NVIDIA Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef VIC_H
#define VIC_H
#include <stdio.h>
#include "host1x.h"
#define DXVAHD_FRAME_FORMAT_PROGRESSIVE 0
#define DXVAHD_FRAME_FORMAT_INTERLACED_TOP_FIELD_FIRST 1
#define DXVAHD_FRAME_FORMAT_INTERLACED_BOTTOM_FIELD_FIRST 2
#define DXVAHD_FRAME_FORMAT_TOP_FIELD 3
#define DXVAHD_FRAME_FORMAT_BOTTOM_FIELD 4
#define DXVAHD_FRAME_FORMAT_SUBPIC_PROGRESSIVE 5
#define DXVAHD_FRAME_FORMAT_SUBPIC_INTERLACED_TOP_FIELD_FIRST 6
#define DXVAHD_FRAME_FORMAT_SUBPIC_INTERLACED_BOTTOM_FIELD_FIRST 7
#define DXVAHD_FRAME_FORMAT_SUBPIC_TOP_FIELD 8
#define DXVAHD_FRAME_FORMAT_SUBPIC_BOTTOM_FIELD 9
#define DXVAHD_FRAME_FORMAT_TOP_FIELD_CHROMA_BOTTOM 10
#define DXVAHD_FRAME_FORMAT_BOTTOM_FIELD_CHROMA_TOP 11
#define DXVAHD_FRAME_FORMAT_SUBPIC_TOP_FIELD_CHROMA_BOTTOM 12
#define DXVAHD_FRAME_FORMAT_SUBPIC_BOTTOM_FIELD_CHROMA_TOP 13
#define DXVAHD_ALPHA_FILL_MODE_OPAQUE 0
#define DXVAHD_ALPHA_FILL_MODE_BACKGROUND 1
#define DXVAHD_ALPHA_FILL_MODE_DESTINATION 2
#define DXVAHD_ALPHA_FILL_MODE_SOURCE_STREAM 3
#define DXVAHD_ALPHA_FILL_MODE_COMPOSITED 4
#define DXVAHD_ALPHA_FILL_MODE_SOURCE_ALPHA 5
#define VIC_BLEND_SRCFACTC_K1 0
#define VIC_BLEND_SRCFACTC_K1_TIMES_DST 1
#define VIC_BLEND_SRCFACTC_NEG_K1_TIMES_DST 2
#define VIC_BLEND_SRCFACTC_K1_TIMES_SRC 3
#define VIC_BLEND_SRCFACTC_ZERO 4
#define VIC_BLEND_DSTFACTC_K1 0
#define VIC_BLEND_DSTFACTC_K2 1
#define VIC_BLEND_DSTFACTC_K1_TIMES_DST 2
#define VIC_BLEND_DSTFACTC_NEG_K1_TIMES_DST 3
#define VIC_BLEND_DSTFACTC_NEG_K1_TIMES_SRC 4
#define VIC_BLEND_DSTFACTC_ZERO 5
#define VIC_BLEND_DSTFACTC_ONE 6
#define VIC_BLEND_SRCFACTA_K1 0
#define VIC_BLEND_SRCFACTA_K2 1
#define VIC_BLEND_SRCFACTA_NEG_K1_TIMES_DST 2
#define VIC_BLEND_SRCFACTA_ZERO 3
#define VIC_BLEND_DSTFACTA_K2 0
#define VIC_BLEND_DSTFACTA_NEG_K1_TIMES_SRC 1
#define VIC_BLEND_DSTFACTA_ZERO 2
#define VIC_BLEND_DSTFACTA_ONE 3
#define VIC_BLK_KIND_PITCH 0
#define VIC_BLK_KIND_GENERIC_16Bx2 1
#define VIC_PIXEL_FORMAT_L8 1
#define VIC_PIXEL_FORMAT_R8 4
#define VIC_PIXEL_FORMAT_A8R8G8B8 32
#define VIC_PIXEL_FORMAT_R8G8B8A8 34
#define VIC_PIXEL_FORMAT_Y8_U8V8_N420 67
#define VIC_PIXEL_FORMAT_Y8_V8U8_N420 68
#define VIC_CACHE_WIDTH_16Bx16 0 /* BL16Bx2 */
#define VIC_CACHE_WIDTH_32Bx8 1 /* BL16Bx2 */
#define VIC_CACHE_WIDTH_64Bx4 2 /* BL16Bx2, PL */
#define VIC_CACHE_WIDTH_128Bx2 3 /* BL16Bx2, PL */
#define VIC_CACHE_WIDTH_256Bx1 4 /* PL */
struct vic_format_info {
unsigned int format;
unsigned int cpp;
};
#define VIC_UCLASS_INCR_SYNCPT 0x00
#define VIC_UCLASS_METHOD_OFFSET 0x10
#define VIC_UCLASS_METHOD_DATA 0x11
static inline void VIC_PUSH_METHOD(struct drm_tegra_pushbuf *pushbuf,
uint32_t **ptrp, uint32_t method,
uint32_t value)
{
*(*ptrp)++ = HOST1X_OPCODE_INCR(VIC_UCLASS_METHOD_OFFSET, 2);
*(*ptrp)++ = method >> 2;
*(*ptrp)++ = value;
}
static inline void VIC_PUSH_BUFFER(struct drm_tegra_pushbuf *pushbuf,
uint32_t **ptrp, uint32_t method,
struct drm_tegra_mapping *map,
unsigned long offset, unsigned long flags)
{
*(*ptrp)++ = HOST1X_OPCODE_INCR(VIC_UCLASS_METHOD_OFFSET, 2);
*(*ptrp)++ = method >> 2;
drm_tegra_pushbuf_relocate(pushbuf, ptrp, map, offset, 8, flags);
}
struct vic_image;
struct vic;
struct vic_ops {
int (*fill)(struct vic *vic, struct vic_image *output,
unsigned int left, unsigned int top,
unsigned int right, unsigned int bottom,
unsigned int alpha, unsigned red,
unsigned int green, unsigned int blue);
int (*blit)(struct vic *vic, struct vic_image *output,
struct vic_image *input);
int (*flip)(struct vic *vic, struct vic_image *output,
struct vic_image *input);
int (*execute)(struct vic *vic,
struct drm_tegra_pushbuf *pushbuf,
uint32_t **ptrp,
struct vic_image *output,
struct vic_image **inputs,
unsigned int num_inputs);
void (*free)(struct vic *vic);
};
struct vic {
struct drm_tegra *drm;
struct drm_tegra_channel *channel;
struct drm_tegra_syncpoint *syncpt;
const struct vic_ops *ops;
unsigned int version;
};
int vic_new(struct drm_tegra *drm, struct drm_tegra_channel *channel,
struct vic **vicp);
void vic_free(struct vic *vic);
int vic_clear(struct vic *vic, struct vic_image *output, unsigned int alpha,
unsigned int red, unsigned int green, unsigned int blue);
struct vic_image {
struct drm_tegra_bo *bo;
struct drm_tegra_mapping *map;
unsigned int width;
unsigned int stride;
unsigned int pitch;
unsigned int height;
unsigned int format;
unsigned int kind;
size_t align;
size_t size;
};
const struct vic_format_info *vic_format_get_info(unsigned int format);
int vic_image_new(struct vic *vic, unsigned int width, unsigned int height,
unsigned int format, unsigned int kind, uint32_t flags,
struct vic_image **imagep);
void vic_image_free(struct vic_image *image);
void vic_image_dump(struct vic_image *image, FILE *fp);
#endif

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/*
* Copyright © 2018 NVIDIA Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <errno.h>
#include <string.h>
#include "private.h"
#include "tegra.h"
#include "vic.h"
#include "vic30.h"
struct vic30 {
struct vic base;
struct {
struct drm_tegra_mapping *map;
struct drm_tegra_bo *bo;
} config;
struct {
struct drm_tegra_mapping *map;
struct drm_tegra_bo *bo;
} filter;
struct {
struct drm_tegra_mapping *map;
struct drm_tegra_bo *bo;
} hist;
};
static int vic30_fill(struct vic *v, struct vic_image *output,
unsigned int left, unsigned int top,
unsigned int right, unsigned int bottom,
unsigned int alpha, unsigned int red,
unsigned int green, unsigned int blue)
{
struct vic30 *vic = container_of(v, struct vic30, base);
ConfigStruct *c;
int err;
err = drm_tegra_bo_map(vic->config.bo, (void **)&c);
if (err < 0) {
fprintf(stderr, "failed to map configuration structure: %s\n",
strerror(-err));
return err;
}
memset(c, 0, sizeof(*c));
c->surfaceList0Struct.TargetRectLeft = left;
c->surfaceList0Struct.TargetRectTop = top;
c->surfaceList0Struct.TargetRectRight = right;
c->surfaceList0Struct.TargetRectBottom = bottom;
c->blending0Struct.PixelFormat = output->format;
c->blending0Struct.BackgroundAlpha = alpha;
c->blending0Struct.BackgroundR = red;
c->blending0Struct.BackgroundG = green;
c->blending0Struct.BackgroundB = blue;
c->blending0Struct.LumaWidth = output->stride - 1;
c->blending0Struct.LumaHeight = output->height - 1;
c->blending0Struct.ChromaWidth = 16383;
c->blending0Struct.ChromaWidth = 16383;
c->blending0Struct.TargetRectLeft = left;
c->blending0Struct.TargetRectTop = top;
c->blending0Struct.TargetRectRight = right;
c->blending0Struct.TargetRectBottom = bottom;
c->blending0Struct.SurfaceWidth = output->width - 1;
c->blending0Struct.SurfaceHeight = output->height - 1;
c->blending0Struct.BlkKind = output->kind;
c->blending0Struct.BlkHeight = 0;
c->fetchControl0Struct.TargetRectLeft = left;
c->fetchControl0Struct.TargetRectTop = top;
c->fetchControl0Struct.TargetRectRight = right;
c->fetchControl0Struct.TargetRectBottom = bottom;
drm_tegra_bo_unmap(vic->config.bo);
return 0;
}
static int vic30_blit(struct vic *v, struct vic_image *output,
struct vic_image *input)
{
struct vic30 *vic = container_of(v, struct vic30, base);
ColorConversionLumaAlphaStruct *ccla;
ColorConversionMatrixStruct *ccm;
ColorConversionClampStruct *ccc;
SurfaceListSurfaceStruct *s;
BlendingSurfaceStruct *b;
SurfaceCache0Struct *sc;
ConfigStruct *c;
int err;
err = drm_tegra_bo_map(vic->config.bo, (void **)&c);
if (err < 0) {
fprintf(stderr, "failed to map configuration structure: %s\n",
strerror(-err));
return err;
}
memset(c, 0, sizeof(*c));
c->surfaceList0Struct.TargetRectLeft = 0;
c->surfaceList0Struct.TargetRectTop = 0;
c->surfaceList0Struct.TargetRectRight = output->width - 1;
c->surfaceList0Struct.TargetRectBottom = output->height - 1;
c->blending0Struct.PixelFormat = output->format;
c->blending0Struct.BackgroundAlpha = 0;
c->blending0Struct.BackgroundR = 0;
c->blending0Struct.BackgroundG = 0;
c->blending0Struct.BackgroundB = 0;
c->blending0Struct.LumaWidth = output->stride - 1;
c->blending0Struct.LumaHeight = output->height - 1;
c->blending0Struct.ChromaWidth = 16383;
c->blending0Struct.ChromaWidth = 16383;
c->blending0Struct.TargetRectLeft = 0;
c->blending0Struct.TargetRectTop = 0;
c->blending0Struct.TargetRectRight = output->width - 1;
c->blending0Struct.TargetRectBottom = output->height - 1;
c->blending0Struct.SurfaceWidth = output->width - 1;
c->blending0Struct.SurfaceHeight = output->height - 1;
c->blending0Struct.BlkKind = output->kind;
c->blending0Struct.BlkHeight = 0;
c->fetchControl0Struct.TargetRectLeft = 0;
c->fetchControl0Struct.TargetRectTop = 0;
c->fetchControl0Struct.TargetRectRight = output->width - 1;
c->fetchControl0Struct.TargetRectBottom = output->height - 1;
/* setup fetch parameters for slot 0 */
c->fetchControl0Struct.Enable0 = 0x1;
c->fetchControl0Struct.Iir0 = 0x300;
/* setup cache parameters for slot 0 */
sc = &c->surfaceCache0Struct;
sc->PixelFormat0 = input->format;
/* setup surface configuration for slot 0 */
s = &c->surfaceListSurfaceStruct[0];
s->Enable = 1;
s->FrameFormat = DXVAHD_FRAME_FORMAT_PROGRESSIVE;
s->PixelFormat = input->format;
s->SurfaceWidth = input->width - 1;
s->SurfaceHeight = input->height - 1;
s->LumaWidth = input->stride - 1;
s->LumaHeight = input->height - 1;
s->ChromaWidth = 16383;
s->ChromaHeight = 16383;
s->CacheWidth = VIC_CACHE_WIDTH_256Bx1; //VIC_CACHE_WIDTH_16Bx16;
s->BlkKind = input->kind;
s->BlkHeight = 0;
s->DestRectLeft = 0;
s->DestRectTop = 0;
s->DestRectRight = output->width - 1;
s->DestRectBottom = output->height - 1;
s->SourceRectLeft = 0 << 16;
s->SourceRectTop = 0 << 16;
s->SourceRectRight = (input->width - 1) << 16;
s->SourceRectBottom = (input->height - 1) << 16;
/* setup color conversion for slot 0 */
ccla = &c->colorConversionLumaAlphaStruct[0];
ccla->PlanarAlpha = 1023;
ccla->ConstantAlpha = 0;
ccm = &c->colorConversionMatrixStruct[0];
ccm->c00 = 1023;
ccm->c11 = 1023;
ccm->c22 = 1023;
ccc = &c->colorConversionClampStruct[0];
ccc->low = 0;
ccc->high = 1023;
/* setup blending for slot 0 */
b = &c->blendingSurfaceStruct[0];
b->AlphaK1 = 1023;
b->SrcFactCMatchSelect = VIC_BLEND_SRCFACTC_K1;
b->SrcFactAMatchSelect = VIC_BLEND_SRCFACTA_K1;
b->DstFactCMatchSelect = VIC_BLEND_DSTFACTC_NEG_K1_TIMES_SRC;
b->DstFactAMatchSelect = VIC_BLEND_DSTFACTA_NEG_K1_TIMES_SRC;
drm_tegra_bo_unmap(vic->config.bo);
return 0;
}
static int vic30_flip(struct vic *v, struct vic_image *output,
struct vic_image *input)
{
struct vic30 *vic = container_of(v, struct vic30, base);
ColorConversionLumaAlphaStruct *ccla;
ColorConversionMatrixStruct *ccm;
ColorConversionClampStruct *ccc;
SurfaceListSurfaceStruct *s;
BlendingSurfaceStruct *b;
SurfaceCache0Struct *sc;
ConfigStruct *c;
int err;
err = drm_tegra_bo_map(vic->config.bo, (void **)&c);
if (err < 0) {
fprintf(stderr, "failed to map configuration structure: %s\n",
strerror(-err));
return err;
}
memset(c, 0, sizeof(*c));
c->surfaceList0Struct.TargetRectLeft = 0;
c->surfaceList0Struct.TargetRectTop = 0;
c->surfaceList0Struct.TargetRectRight = output->width - 1;
c->surfaceList0Struct.TargetRectBottom = output->height - 1;
c->blending0Struct.PixelFormat = output->format;
c->blending0Struct.BackgroundAlpha = 0;
c->blending0Struct.BackgroundR = 0;
c->blending0Struct.BackgroundG = 0;
c->blending0Struct.BackgroundB = 0;
c->blending0Struct.LumaWidth = output->stride - 1;
c->blending0Struct.LumaHeight = output->height - 1;
c->blending0Struct.ChromaWidth = 16383;
c->blending0Struct.ChromaWidth = 16383;
c->blending0Struct.TargetRectLeft = 0;
c->blending0Struct.TargetRectTop = 0;
c->blending0Struct.TargetRectRight = output->width - 1;
c->blending0Struct.TargetRectBottom = output->height - 1;
c->blending0Struct.SurfaceWidth = output->width - 1;
c->blending0Struct.SurfaceHeight = output->height - 1;
c->blending0Struct.BlkKind = output->kind;
c->blending0Struct.BlkHeight = 0;
c->blending0Struct.OutputFlipY = 1;
c->fetchControl0Struct.TargetRectLeft = 0;
c->fetchControl0Struct.TargetRectTop = 0;
c->fetchControl0Struct.TargetRectRight = output->width - 1;
c->fetchControl0Struct.TargetRectBottom = output->height - 1;
/* setup fetch parameters for slot 0 */
c->fetchControl0Struct.Enable0 = 0x1;
c->fetchControl0Struct.Iir0 = 0x300;
/* setup cache parameters for slot 0 */
sc = &c->surfaceCache0Struct;
sc->PixelFormat0 = input->format;
/* setup surface configuration for slot 0 */
s = &c->surfaceListSurfaceStruct[0];
s->Enable = 1;
s->FrameFormat = DXVAHD_FRAME_FORMAT_PROGRESSIVE;
s->PixelFormat = input->format;
s->SurfaceWidth = input->width - 1;
s->SurfaceHeight = input->height - 1;
s->LumaWidth = input->stride - 1;
s->LumaHeight = input->height - 1;
s->ChromaWidth = 16383;
s->ChromaHeight = 16383;
s->CacheWidth = VIC_CACHE_WIDTH_256Bx1;
s->BlkKind = input->kind;
s->BlkHeight = 0;
s->DestRectLeft = 0;
s->DestRectTop = 0;
s->DestRectRight = output->width - 1;
s->DestRectBottom = output->height - 1;
s->SourceRectLeft = 0 << 16;
s->SourceRectTop = 0 << 16;
s->SourceRectRight = (input->width - 1) << 16;
s->SourceRectBottom = (input->height - 1) << 16;
/* setup color conversion for slot 0 */
ccla = &c->colorConversionLumaAlphaStruct[0];
ccla->PlanarAlpha = 1023;
ccla->ConstantAlpha = 0;
ccm = &c->colorConversionMatrixStruct[0];
ccm->c00 = 1023;
ccm->c11 = 1023;
ccm->c22 = 1023;
ccc = &c->colorConversionClampStruct[0];
ccc->low = 0;
ccc->high = 1023;
/* setup blending for slot 0 */
b = &c->blendingSurfaceStruct[0];
b->AlphaK1 = 1023;
b->SrcFactCMatchSelect = VIC_BLEND_SRCFACTC_K1;
b->SrcFactAMatchSelect = VIC_BLEND_SRCFACTA_K1;
b->DstFactCMatchSelect = VIC_BLEND_DSTFACTC_NEG_K1_TIMES_SRC;
b->DstFactAMatchSelect = VIC_BLEND_DSTFACTA_NEG_K1_TIMES_SRC;
drm_tegra_bo_unmap(vic->config.bo);
return 0;
}
static int vic30_execute(struct vic *v, struct drm_tegra_pushbuf *pushbuf,
uint32_t **ptrp, struct vic_image *output,
struct vic_image **inputs, unsigned int num_inputs)
{
struct vic30 *vic = container_of(v, struct vic30, base);
unsigned int i;
if (num_inputs > 1)
return -EINVAL;
VIC_PUSH_METHOD(pushbuf, ptrp, NVA0B6_VIDEO_COMPOSITOR_SET_APPLICATION_ID, 1);
VIC_PUSH_METHOD(pushbuf, ptrp, NVA0B6_VIDEO_COMPOSITOR_SET_CONTROL_PARAMS, (sizeof(ConfigStruct) / 16) << 16);
VIC_PUSH_BUFFER(pushbuf, ptrp, NVA0B6_VIDEO_COMPOSITOR_SET_CONFIG_STRUCT_OFFSET, vic->config.map, 0, 0);
VIC_PUSH_BUFFER(pushbuf, ptrp, NVA0B6_VIDEO_COMPOSITOR_SET_HIST_OFFSET, vic->hist.map, 0, 0);
VIC_PUSH_BUFFER(pushbuf, ptrp, NVA0B6_VIDEO_COMPOSITOR_SET_OUTPUT_SURFACE_LUMA_OFFSET, output->map, 0, 0);
for (i = 0; i < num_inputs; i++)
VIC_PUSH_BUFFER(pushbuf, ptrp, NVA0B6_VIDEO_COMPOSITOR_SET_SURFACE0_SLOT0_LUMA_OFFSET, inputs[i]->map, 0, 0);
VIC_PUSH_METHOD(pushbuf, ptrp, NVA0B6_VIDEO_COMPOSITOR_EXECUTE, 1 << 8);
return 0;
}
static void vic30_free(struct vic *v)
{
struct vic30 *vic = container_of(v, struct vic30, base);
drm_tegra_channel_unmap(vic->hist.map);
drm_tegra_bo_unref(vic->hist.bo);
drm_tegra_channel_unmap(vic->filter.map);
drm_tegra_bo_unref(vic->filter.bo);
drm_tegra_channel_unmap(vic->config.map);
drm_tegra_bo_unref(vic->config.bo);
drm_tegra_syncpoint_free(v->syncpt);
free(vic);
}
static const struct vic_ops vic30_ops = {
.fill = vic30_fill,
.blit = vic30_blit,
.flip = vic30_flip,
.execute = vic30_execute,
.free = vic30_free,
};
int vic30_new(struct drm_tegra *drm, struct drm_tegra_channel *channel,
struct vic **vicp)
{
struct vic30 *vic;
void *ptr;
int err;
vic = calloc(1, sizeof(*vic));
if (!vic)
return -ENOMEM;
vic->base.drm = drm;
vic->base.channel = channel;
vic->base.ops = &vic30_ops;
vic->base.version = 0x40;
err = drm_tegra_syncpoint_new(drm, &vic->base.syncpt);
if (err < 0) {
fprintf(stderr, "failed to allocate syncpoint: %s\n", strerror(-err));
return err;
}
err = drm_tegra_bo_new(drm, 0, 16384, &vic->config.bo);
if (err < 0) {
fprintf(stderr, "failed to allocate configuration structure: %s\n",
strerror(-err));
return err;
}
err = drm_tegra_channel_map(channel, vic->config.bo, DRM_TEGRA_CHANNEL_MAP_READ,
&vic->config.map);
if (err < 0) {
fprintf(stderr, "failed to map configuration structure: %s\n",
strerror(-err));
return err;
}
err = drm_tegra_bo_new(drm, 0, 16384, &vic->filter.bo);
if (err < 0) {
fprintf(stderr, "failed to allocate filter buffer: %s\n",
strerror(-err));
return err;
}
err = drm_tegra_bo_map(vic->filter.bo, &ptr);
if (err < 0) {
fprintf(stderr, "failed to map filter buffer: %s\n", strerror(-err));
return err;
}
memset(ptr, 0, 16384);
drm_tegra_bo_unmap(vic->filter.bo);
err = drm_tegra_channel_map(channel, vic->filter.bo, DRM_TEGRA_CHANNEL_MAP_READ,
&vic->filter.map);
if (err < 0) {
fprintf(stderr, "failed to map filter buffer: %s\n",
strerror(-err));
return err;
}
err = drm_tegra_bo_new(drm, 0, 4096, &vic->hist.bo);
if (err < 0) {
fprintf(stderr, "failed to allocate history buffer: %s\n",
strerror(-err));
return err;
}
err = drm_tegra_bo_map(vic->hist.bo, &ptr);
if (err < 0) {
fprintf(stderr, "failed to map history buffer: %s\n", strerror(-err));
return err;
}
memset(ptr, 0, 4096);
drm_tegra_bo_unmap(vic->hist.bo);
err = drm_tegra_channel_map(channel, vic->hist.bo, DRM_TEGRA_CHANNEL_MAP_READ_WRITE,
&vic->hist.map);
if (err < 0) {
fprintf(stderr, "failed to map histogram buffer: %s\n",
strerror(-err));
return err;
}
if (vicp)
*vicp = &vic->base;
return 0;
}

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/*
* Copyright © 2018 NVIDIA Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef VIC30_H
#define VIC30_H
#include <stdint.h>
#define NVA0B6_VIDEO_COMPOSITOR_SET_APPLICATION_ID 0x200
#define NVA0B6_VIDEO_COMPOSITOR_EXECUTE 0x300
#define NVA0B6_VIDEO_COMPOSITOR_EXECUTE_AWAKEN (1 << 8)
#define NVA0B6_VIDEO_COMPOSITOR_SET_SURFACE0_SLOT0_LUMA_OFFSET 0x400
#define NVA0B6_VIDEO_COMPOSITOR_SET_SURFACE0_SLOT0_CHROMA_U_OFFSET 0x404
#define NVA0B6_VIDEO_COMPOSITOR_SET_SURFACE0_SLOT0_CHROMA_V_OFFSET 0x408
#define NVA0B6_VIDEO_COMPOSITOR_SET_CONTROL_PARAMS 0x700
#define NVA0B6_VIDEO_COMPOSITOR_SET_CONFIG_STRUCT_OFFSET 0x720
#define NVA0B6_VIDEO_COMPOSITOR_SET_PALETTE_OFFSET 0x724
#define NVA0B6_VIDEO_COMPOSITOR_SET_HIST_OFFSET 0x728
#define NVA0B6_VIDEO_COMPOSITOR_SET_OUTPUT_SURFACE_LUMA_OFFSET 0x730
#define NVA0B6_VIDEO_COMPOSITOR_SET_OUTPUT_SURFACE_CHROMA_U_OFFSET 0x734
#define NVA0B6_VIDEO_COMPOSITOR_SET_OUTPUT_SURFACE_CHROMA_V_OFFSET 0x738
#define VIC_PIXEL_FORMAT_L8 1
#define VIC_PIXEL_FORMAT_R8 4
#define VIC_PIXEL_FORMAT_A8R8G8B8 32
#define VIC_PIXEL_FORMAT_R8G8B8A8 34
#define VIC_PIXEL_FORMAT_Y8_U8V8_N420 67
#define VIC_PIXEL_FORMAT_Y8_V8U8_N420 68
#define VIC_BLK_KIND_PITCH 0
#define VIC_BLK_KIND_GENERIC_16Bx2 1
typedef struct {
uint64_t DeNoise0 : 1; /* 0 */
uint64_t CadenceDetect0 : 1; /* 1 */
uint64_t MotionMap0 : 1; /* 2 */
uint64_t MedianFilter0 : 1; /* 3 */
uint64_t DeNoise1 : 1; /* 4 */
uint64_t CadenceDetect1 : 1; /* 5 */
uint64_t MotionMap1 : 1; /* 6 */
uint64_t MedianFilter1 : 1; /* 7 */
uint64_t DeNoise2 : 1; /* 8 */
uint64_t CadenceDetect2 : 1; /* 9 */
uint64_t MotionMap2 : 1; /* 10 */
uint64_t MedianFilter2 : 1; /* 11 */
uint64_t DeNoise3 : 1; /* 12 */
uint64_t CadenceDetect3 : 1; /* 13 */
uint64_t MotionMap3 : 1; /* 14 */
uint64_t MedianFilter3 : 1; /* 15 */
uint64_t DeNoise4 : 1; /* 16 */
uint64_t CadenceDetect4 : 1; /* 17 */
uint64_t MotionMap4 : 1; /* 18 */
uint64_t MedianFilter4 : 1; /* 19 */
uint64_t IsEven0 : 1; /* 20 */
uint64_t IsEven1 : 1; /* 21 */
uint64_t IsEven2 : 1; /* 22 */
uint64_t IsEven3 : 1; /* 23 */
uint64_t IsEven4 : 1; /* 24 */
uint64_t MMapCombine0 : 1; /* 25 */
uint64_t MMapCombine1 : 1; /* 26 */
uint64_t MMapCombine2 : 1; /* 27 */
uint64_t MMapCombine3 : 1; /* 28 */
uint64_t MMapCombine4 : 1; /* 29 */
uint64_t reserved0 : 2; /* 31..30 */
uint64_t PixelFormat0 : 7; /* 38..32 */
uint64_t reserved1 : 1; /* 39 */
uint64_t PixelFormat1 : 7; /* 46..40 */
uint64_t reserved2 : 1; /* 47 */
uint64_t PixelFormat2 : 7; /* 54..48 */
uint64_t reserved3 : 1; /* 55 */
uint64_t PixelFormat3 : 7; /* 62..56 */
uint64_t reserved4 : 1; /* 63 */
uint64_t PixelFormat4 : 7; /* 70..64 */
uint64_t reserved5 : 1; /* 71 */
uint64_t reserved6 : 24; /* 95..72 */
uint64_t PPMotion0 : 1; /* 96 */
uint64_t PPMotion1 : 1; /* 97 */
uint64_t PPMotion2 : 1; /* 98 */
uint64_t PPMotion3 : 1; /* 99 */
uint64_t PPMotion4 : 1; /* 100 */
uint64_t reserved7 : 3; /* 103..101 */
uint64_t ChromaEven0 : 1; /* 104 */
uint64_t ChromaEven1 : 1; /* 105 */
uint64_t ChromaEven2 : 1; /* 106 */
uint64_t ChromaEven3 : 1; /* 107 */
uint64_t ChromaEven4 : 1; /* 108 */
uint64_t reserved8 : 3; /* 111..109 */
uint64_t AdvancedDenoise0 : 1; /* 112 */
uint64_t AdvancedDenoise1 : 1; /* 113 */
uint64_t AdvancedDenoise2 : 1; /* 114 */
uint64_t AdvancedDenoise3 : 1; /* 115 */
uint64_t AdvancedDenoise4 : 1; /* 116 */
uint64_t reserved9 : 3; /* 119..117 */
uint64_t reserved10 : 8; /* 127..120 */
} SurfaceCache0Struct;
typedef struct {
uint64_t ClearRectMask0 : 8; /* 7..0 */
uint64_t ClearRectMask1 : 8; /* 15..8 */
uint64_t ClearRectMask2 : 8; /* 23..16 */
uint64_t ClearRectMask3 : 8; /* 31..24 */
uint64_t ClearRectMask4 : 8; /* 39..32 */
uint64_t reserved0 : 22; /* 61..40 */
uint64_t OutputFlipX : 1; /* 62 */
uint64_t OutputFlipY : 1; /* 63 */
uint64_t TargetRectLeft : 14; /* 77..64 */
uint64_t reserved1 : 2; /* 79..78 */
uint64_t TargetRectRight : 14; /* 93..80 */
uint64_t reserved2 : 2; /* 95..94 */
uint64_t TargetRectTop : 14; /* 109..96 */
uint64_t reserved3 : 2; /* 111..110 */
uint64_t TargetRectBottom : 14; /* 125..112 */
uint64_t reserved4 : 2; /* 127..126 */
} SurfaceList0Struct;
typedef struct {
uint64_t ClearRect0Left : 14; /* 13..0 */
uint64_t reserved0 : 2; /* 15..14 */
uint64_t ClearRect0Right : 14; /* 29..16 */
uint64_t reserved1 : 2; /* 31..30 */
uint64_t ClearRect0Top : 14; /* 45..32 */
uint64_t reserved2 : 2; /* 47..46 */
uint64_t ClearRect0Bottom : 14; /* 61..48 */
uint64_t reserved3 : 2; /* 63..62 */
uint64_t ClearRect1Left : 14; /* 77..64 */
uint64_t reserved4 : 2; /* 79..78 */
uint64_t ClearRect1Right : 14; /* 93..80 */
uint64_t reserved5 : 2; /* 95..94 */
uint64_t ClearRect1Top : 14; /* 109..96 */
uint64_t reserved6 : 2; /* 111..110 */
uint64_t ClearRect1Bottom : 14; /* 125..112 */
uint64_t reserved7 : 2; /* 127..126 */
} SurfaceListClearRectStruct;
typedef struct {
uint64_t Enable : 1; /* 0 */
uint64_t FrameFormat : 4; /* 4..1 */
uint64_t PixelFormat : 7; /* 11..5 */
uint64_t reserved0 : 2; /* 13..12 */
uint64_t ChromaLocHoriz : 2; /* 15..14 */
uint64_t ChromaLocVert : 2; /* 17..16 */
uint64_t Panoramic : 12; /* 29..18 */
uint64_t reserved1 : 4; /* 33..30 */
uint64_t SurfaceWidth : 14; /* 47..34 */
uint64_t reserved2 : 1; /* 48 */
uint64_t SurfaceHeight : 14; /* 62..49 */
uint64_t reserved3 : 1; /* 63 */
uint64_t LumaWidth : 14; /* 77..64 */
uint64_t reserved4 : 1; /* 78 */
uint64_t LumaHeight : 14; /* 92..79 */
uint64_t reserved5 : 1; /* 93 */
uint64_t ChromaWidth : 14; /* 107..94 */
uint64_t reserved6 : 1; /* 108 */
uint64_t ChromaHeight : 14; /* 122..109 */
uint64_t reserved7 : 1; /* 123 */
uint64_t CacheWidth : 3; /* 126..124 */
uint64_t reserved8 : 1; /* 127 */
/* 128 */
uint64_t FilterLengthY : 2; /* 1..0 */
uint64_t FilterLengthX : 2; /* 3..2 */
uint64_t DetailFltClamp : 6; /* 9..4 */
uint64_t reserved9 : 2; /* 11..10 */
uint64_t LightLevel : 4; /* 15..12 */
uint64_t reserved10 : 4; /* 19..16 */
uint64_t reserved11 : 8; /* 27..20 */
uint64_t reserved12 : 32; /* 59..28 */
uint64_t BlkKind : 4; /* 63..60 */
uint64_t DestRectLeft : 14; /* 77..64 */
uint64_t reserved13 : 1; /* 78 */
uint64_t DestRectRight : 14; /* 92..79 */
uint64_t reserved14 : 1; /* 93 */
uint64_t DestRectTop : 14; /* 107..94 */
uint64_t reserved15 : 1; /* 108 */
uint64_t DestRectBottom : 14; /* 122..109 */
uint64_t reserved16 : 1; /* 123 */
uint64_t BlkHeight : 4; /* 127..124 */
/* 256 */
uint64_t SourceRectLeft : 30; /* 29..0 */
uint64_t reserved17 : 2; /* 31..30 */
uint64_t SourceRectRight : 30; /* 61..32 */
uint64_t reserved18 : 2; /* 63..62 */
uint64_t SourceRectTop : 30; /* 93..64 */
uint64_t reserved19 : 2; /* 95..94 */
uint64_t SourceRectBottom : 30; /* 125..96 */
uint64_t reserved20 : 2; /* 127..126 */
} SurfaceListSurfaceStruct;
typedef struct {
uint64_t l0 : 20; /* 19..0 */
uint64_t l1 : 20; /* 39..20 */
uint64_t l2 : 20; /* 59..40 */
uint64_t r_shift : 4; /* 63..60 */
uint64_t l3 : 20; /* 83..64 */
uint64_t PlanarAlpha : 10; /* 93..84 */
uint64_t ConstantAlpha : 1; /* 94 */
uint64_t ClipEnabled : 1; /* 95 */
uint64_t LumaKeyLower : 10; /* 105..96 */
uint64_t reserved6 : 3; /* 108..106 */
uint64_t StereoInterleave : 3; /* 111..109 */
uint64_t LumaKeyUpper : 10; /* 121..112 */
uint64_t reserved7 : 2; /* 123..122 */
uint64_t reserved8 : 1; /* 124 */
uint64_t LumaKeyEnabled : 1; /* 125 */
uint64_t reserved9 : 2; /* 127..126 */
} ColorConversionLumaAlphaStruct;
typedef struct {
uint64_t c00 : 20; /* 19..0 */
uint64_t c10 : 20; /* 39..20 */
uint64_t c20 : 20; /* 59..40 */
uint64_t r_shift : 4; /* 63..60 */
uint64_t c01 : 20; /* 83..64 */
uint64_t c11 : 20; /* 103..84 */
uint64_t c21 : 20; /* 123..104 */
uint64_t reserved0 : 4; /* 127..124 */
/* 128 */
uint64_t c02 : 20; /* 19..0 */
uint64_t c12 : 20; /* 39..20 */
uint64_t c22 : 20; /* 59..40 */
uint64_t reserved1 : 4; /* 63..60 */
uint64_t c03 : 20; /* 83..64 */
uint64_t c13 : 20; /* 103..84 */
uint64_t c23 : 20; /* 123..104 */
uint64_t reserved2 : 4; /* 127..124 */
} ColorConversionMatrixStruct;
typedef struct {
uint64_t low : 10; /* 9..0 */
uint64_t reserved0 : 6; /* 15..10 */
uint64_t high : 10; /* 25..16 */
uint64_t reserved1 : 6; /* 31..26 */
uint64_t reserved2 : 32; /* 63..32 */
uint64_t reserved3 : 32; /* 95..64 */
uint64_t reserved4 : 32; /* 127..96 */
} ColorConversionClampStruct;
typedef struct {
uint64_t PixelFormat : 7; /* 6..0 */
uint64_t reserved0 : 1; /* 7 */
uint64_t AlphaFillMode : 3; /* 10..8 */
uint64_t AlphaFillSlot : 3; /* 13..11 */
uint64_t BackgroundAlpha : 10; /* 23..14 */
uint64_t BackgroundR : 10; /* 33..24 */
uint64_t BackgroundG : 10; /* 43..34 */
uint64_t BackgroundB : 10; /* 53..44 */
uint64_t ChromaLocHoriz : 2; /* 55..54 */
uint64_t ChromaLocVert : 2; /* 57..56 */
uint64_t reserved1 : 6; /* 63..58 */
uint64_t LumaWidth : 14; /* 77..64 */
uint64_t reserved2 : 2; /* 79..78 */
uint64_t LumaHeight : 14; /* 93..80 */
uint64_t reserved3 : 2; /* 95..94 */
uint64_t ChromaWidth : 14; /* 109..96 */
uint64_t reserved4 : 2; /* 111..110 */
uint64_t ChromaHeight : 14; /* 125..112 */
uint64_t reserved5 : 2; /* 127..126 */
/* 128 */
uint64_t TargetRectLeft : 14; /* 13..0 */
uint64_t reserved6 : 2; /* 15..14 */
uint64_t TargetRectRight : 14; /* 29..16 */
uint64_t reserved7 : 2; /* 31..30 */
uint64_t TargetRectTop : 14; /* 45..32 */
uint64_t reserved8 : 2; /* 47..46 */
uint64_t TargetRectBottom : 14; /* 61..48 */
uint64_t reserved9 : 2; /* 63..62 */
uint64_t SurfaceWidth : 14; /* 77..64 */
uint64_t reserved10 : 2; /* 79..78 */
uint64_t SurfaceHeight : 14; /* 93..80 */
uint64_t reserved11 : 2; /* 95..94 */
uint64_t BlkKind : 4; /* 99..96 */
uint64_t BlkHeight : 4; /* 103..100 */
uint64_t OutputFlipX : 1; /* 104 */
uint64_t OutputFlipY : 1; /* 105 */
uint64_t OutputTranspose : 1; /* 106 */
uint64_t reserved12 : 21; /* 127..107 */
} Blending0Struct;
typedef struct {
uint64_t AlphaK1 : 10; /* 9..0 */
uint64_t reserved0 : 6; /* 15..10 */
uint64_t AlphaK2 : 10; /* 25..16 */
uint64_t reserved1 : 6; /* 31..26 */
uint64_t SrcFactCMatchSelect : 3; /* 34..32 */
uint64_t reserved2 : 1; /* 35 */
uint64_t DstFactCMatchSelect : 3; /* 38..36 */
uint64_t reserved3 : 1; /* 39 */
uint64_t SrcFactAMatchSelect : 3; /* 42..40 */
uint64_t reserved4 : 1; /* 43 */
uint64_t DstFactAMatchSelect : 3; /* 46..44 */
uint64_t reserved5 : 1; /* 47 */
uint64_t reserved6 : 4; /* 51..48 */
uint64_t reserved7 : 4; /* 55..52 */
uint64_t reserved8 : 4; /* 59..56 */
uint64_t reserved9 : 4; /* 63..60 */
uint64_t reserved10 : 2; /* 65..64 */
uint64_t OverrideR : 10; /* 75..66 */
uint64_t OverrideG : 10; /* 85..76 */
uint64_t OverrideB : 10; /* 95..86 */
uint64_t OverrideA : 10; /* 105..96 */
uint64_t reserved11 : 2; /* 107..106 */
uint64_t UseOverrideR : 1; /* 108 */
uint64_t UseOverrideG : 1; /* 109 */
uint64_t UseOverrideB : 1; /* 110 */
uint64_t UseOverrideA : 1; /* 111 */
uint64_t MaskR : 1; /* 112 */
uint64_t MaskG : 1; /* 113 */
uint64_t MaskB : 1; /* 114 */
uint64_t MaskA : 1; /* 115 */
uint64_t reserved12 : 12; /* 127..116 */
} BlendingSurfaceStruct;
typedef struct {
uint64_t TargetRectLeft : 14; /* 13..0 */
uint64_t reserved0 : 2; /* 15..14 */
uint64_t TargetRectRight : 14; /* 29..16 */
uint64_t reserved1 : 2; /* 31..30 */
uint64_t TargetRectTop : 14; /* 45..32 */
uint64_t reserved2 : 2; /* 47..46 */
uint64_t TargetRectBottom : 14; /* 61..48 */
uint64_t reserved3 : 2; /* 63..62 */
uint64_t Enable0 : 8; /* 71..64 */
uint64_t Enable1 : 8; /* 79..72 */
uint64_t Enable2 : 8; /* 87..80 */
uint64_t Enable3 : 8; /* 95..88 */
uint64_t Enable4 : 8; /* 103..96 */
uint64_t DownsampleHoriz : 11; /* 114..104 */
uint64_t reserved4 : 1; /* 115 */
uint64_t DownsampleVert : 11; /* 126..116 */
uint64_t reserved5 : 1; /* 127 */
/* 128 */
uint64_t FilterNoise0 : 10; /* 9..0 */
uint64_t FilterDetail0 : 10; /* 19..10 */
uint64_t FilterNoise1 : 10; /* 29..20 */
uint64_t reserved6 : 2; /* 31..30 */
uint64_t FilterDetail1 : 10; /* 41..32 */
uint64_t FilterNoise2 : 10; /* 51..42 */
uint64_t FilterDetail2 : 10; /* 61..52 */
uint64_t reserved7 : 2; /* 63..62 */
uint64_t FilterNoise3 : 10; /* 73..64 */
uint64_t FilterDetail3 : 10; /* 83..74 */
uint64_t FilterNoise4 : 10; /* 93..84 */
uint64_t reserved8 : 2; /* 95..94 */
uint64_t FilterDetail4 : 10; /* 105..96 */
uint64_t reserved9 : 22; /* 127..106 */
/* 256 */
uint64_t ChromaNoise0 : 10; /* 9..0 */
uint64_t ChromaDetail0 : 10; /* 19..10 */
uint64_t ChromaNoise1 : 10; /* 29..20 */
uint64_t reserved10 : 2; /* 31..30 */
uint64_t ChromaDetail1 : 10; /* 41..32 */
uint64_t ChromaNoise2 : 10; /* 51..42 */
uint64_t ChromaDetail2 : 10; /* 61..52 */
uint64_t reserved11 : 2; /* 63..62 */
uint64_t ChromaNoise3 : 10; /* 73..64 */
uint64_t ChromaDetail3 : 10; /* 83..74 */
uint64_t ChromaNoise4 : 10; /* 93..84 */
uint64_t reserved12 : 2; /* 95..94 */
uint64_t ChromaDetail4 : 10; /* 105..96 */
uint64_t reserved13 : 22; /* 127..106 */
/* 384 */
uint64_t Mode0 : 4; /* 3..0 */
uint64_t AccumWeight0 : 3; /* 6..4 */
uint64_t Iir0 : 11; /* 17..7 */
uint64_t reserved14 : 2; /* 19..18 */
uint64_t Mode1 : 4; /* 23..20 */
uint64_t AccumWeight1 : 3; /* 26..24 */
uint64_t Iir1 : 11; /* 37..27 */
uint64_t reserved15 : 2; /* 39..38 */
uint64_t Mode2 : 4; /* 43..40 */
uint64_t AccumWeight2 : 3; /* 46..44 */
uint64_t Iir2 : 11; /* 57..47 */
uint64_t reserved16 : 6; /* 63..58 */
uint64_t Mode3 : 4; /* 67..64 */
uint64_t AccumWeight3 : 3; /* 70..68 */
uint64_t Iir3 : 11; /* 81..71 */
uint64_t reserved17 : 2; /* 83..82 */
uint64_t Mode4 : 4; /* 87..84 */
uint64_t AccumWeight4 : 3; /* 90..88 */
uint64_t Iir4 : 11; /* 101..91 */
uint64_t reserved18 : 8; /* 109..102 */
uint64_t OutputFlipX : 1; /* 110 */
uint64_t OutputFlipY : 1; /* 111 */
uint64_t reserved19 : 10; /* 121..112 */
uint64_t reserved20 : 6; /* 127..122 */
} FetchControl0Struct;
typedef struct {
uint64_t f00 : 10; /* 9..0 */
uint64_t f10 : 10; /* 19..10 */
uint64_t f20 : 10; /* 29..20 */
uint64_t reserved0 : 2; /* 31..30 */
uint64_t f01 : 10; /* 41..32 */
uint64_t f11 : 10; /* 51..42 */
uint64_t f21 : 10; /* 61..52 */
uint64_t reserved1 : 2; /* 63..62 */
uint64_t f02 : 10; /* 73..64 */
uint64_t f12 : 10; /* 83..74 */
uint64_t f22 : 10; /* 93..84 */
uint64_t reserved2 : 2; /* 95..94 */
uint64_t f03 : 10; /* 105..96 */
uint64_t f13 : 10; /* 115..106 */
uint64_t f23 : 10; /* 125..116 */
uint64_t reserved3 : 2; /* 127..126 */
} FetchControlCoeffStruct;
typedef struct {
SurfaceCache0Struct surfaceCache0Struct;
SurfaceList0Struct surfaceList0Struct;
SurfaceListClearRectStruct surfaceListClearRectStruct[4];
SurfaceListSurfaceStruct surfaceListSurfaceStruct[5];
ColorConversionLumaAlphaStruct colorConversionLumaAlphaStruct[5];
ColorConversionMatrixStruct colorConversionMatrixStruct[5];
ColorConversionClampStruct colorConversionClampStruct[5];
Blending0Struct blending0Struct;
BlendingSurfaceStruct blendingSurfaceStruct[5];
FetchControl0Struct fetchControl0Struct;
FetchControlCoeffStruct fetchControlCoeffStruct[520];
} ConfigStruct;
#endif

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/*
* Copyright © 2018 NVIDIA Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <errno.h>
#include <string.h>
#include "private.h"
#include "tegra.h"
#include "vic.h"
#include "vic40.h"
struct vic40 {
struct vic base;
struct {
struct drm_tegra_mapping *map;
struct drm_tegra_bo *bo;
} config;
struct {
struct drm_tegra_mapping *map;
struct drm_tegra_bo *bo;
} filter;
};
static int vic40_fill(struct vic *v, struct vic_image *output,
unsigned int left, unsigned int top,
unsigned int right, unsigned int bottom,
unsigned int alpha, unsigned int red,
unsigned int green, unsigned int blue)
{
struct vic40 *vic = container_of(v, struct vic40, base);
ConfigStruct *c;
int err;
err = drm_tegra_bo_map(vic->config.bo, (void **)&c);
if (err < 0) {
fprintf(stderr, "failed to map configuration structure: %s\n",
strerror(-err));
return err;
}
memset(c, 0, sizeof(*c));
c->outputConfig.TargetRectTop = top;
c->outputConfig.TargetRectLeft = left;
c->outputConfig.TargetRectRight = right;
c->outputConfig.TargetRectBottom = bottom;
c->outputConfig.BackgroundAlpha = alpha;
c->outputConfig.BackgroundR = red;
c->outputConfig.BackgroundG = green;
c->outputConfig.BackgroundB = blue;
c->outputSurfaceConfig.OutPixelFormat = output->format;
c->outputSurfaceConfig.OutBlkKind = output->kind;
c->outputSurfaceConfig.OutBlkHeight = 0;
c->outputSurfaceConfig.OutSurfaceWidth = output->width - 1;
c->outputSurfaceConfig.OutSurfaceHeight = output->height - 1;
c->outputSurfaceConfig.OutLumaWidth = output->stride - 1;
c->outputSurfaceConfig.OutLumaHeight = output->height - 1;
c->outputSurfaceConfig.OutChromaWidth = 16383;
c->outputSurfaceConfig.OutChromaHeight = 16383;
drm_tegra_bo_unmap(vic->config.bo);
return 0;
}
static int vic40_blit(struct vic *v, struct vic_image *output,
struct vic_image *input)
{
struct vic40 *vic = container_of(v, struct vic40, base);
SlotSurfaceConfig *surface;
SlotConfig *slot;
ConfigStruct *c;
int err;
err = drm_tegra_bo_map(vic->config.bo, (void **)&c);
if (err < 0) {
fprintf(stderr, "failed to map configuration structure: %s\n",
strerror(-err));
return err;
}
memset(c, 0, sizeof(*c));
c->outputConfig.TargetRectTop = 0;
c->outputConfig.TargetRectLeft = 0;
c->outputConfig.TargetRectRight = output->width - 1;
c->outputConfig.TargetRectBottom = output->height - 1;
c->outputConfig.BackgroundAlpha = 1023;
c->outputConfig.BackgroundR = 1023;
c->outputConfig.BackgroundG = 1023;
c->outputConfig.BackgroundB = 1023;
c->outputSurfaceConfig.OutPixelFormat = output->format;
c->outputSurfaceConfig.OutBlkKind = output->kind;
c->outputSurfaceConfig.OutBlkHeight = 0;
c->outputSurfaceConfig.OutSurfaceWidth = output->width - 1;
c->outputSurfaceConfig.OutSurfaceHeight = output->height - 1;
c->outputSurfaceConfig.OutLumaWidth = output->stride - 1;
c->outputSurfaceConfig.OutLumaHeight = output->height - 1;
c->outputSurfaceConfig.OutChromaWidth = 16383;
c->outputSurfaceConfig.OutChromaHeight = 16383;
slot = &c->slotStruct[0].slotConfig;
slot->SlotEnable = 1;
slot->CurrentFieldEnable = 1;
slot->PlanarAlpha = 1023;
slot->ConstantAlpha = 1;
slot->SourceRectLeft = 0 << 16;
slot->SourceRectRight = (input->width - 1) << 16;
slot->SourceRectTop = 0 << 16;
slot->SourceRectBottom = (input->height - 1) << 16;
slot->DestRectLeft = 0;
slot->DestRectRight = output->width - 1;
slot->DestRectTop = 0;
slot->DestRectBottom = output->height - 1;
slot->SoftClampHigh = 1023;
surface = &c->slotStruct[0].slotSurfaceConfig;
surface->SlotPixelFormat = input->format;
surface->SlotBlkKind = input->kind;
surface->SlotBlkHeight = 0; /* XXX */
surface->SlotCacheWidth = VIC_CACHE_WIDTH_64Bx4; /* XXX */
surface->SlotSurfaceWidth = input->width - 1;
surface->SlotSurfaceHeight = input->height - 1;
surface->SlotLumaWidth = input->stride - 1;
surface->SlotLumaHeight = input->height - 1;
surface->SlotChromaWidth = 16383;
surface->SlotChromaHeight = 16383;
drm_tegra_bo_unmap(vic->config.bo);
return 0;
}
static int vic40_flip(struct vic *v, struct vic_image *output,
struct vic_image *input)
{
struct vic40 *vic = container_of(v, struct vic40, base);
SlotSurfaceConfig *surface;
SlotConfig *slot;
ConfigStruct *c;
int err;
err = drm_tegra_bo_map(vic->config.bo, (void **)&c);
if (err < 0) {
fprintf(stderr, "failed to map configuration structure: %s\n",
strerror(-err));
return err;
}
memset(c, 0, sizeof(*c));
c->outputConfig.TargetRectTop = 0;
c->outputConfig.TargetRectLeft = 0;
c->outputConfig.TargetRectRight = output->width - 1;
c->outputConfig.TargetRectBottom = output->height - 1;
c->outputConfig.BackgroundAlpha = 1023;
c->outputConfig.BackgroundR = 1023;
c->outputConfig.BackgroundG = 1023;
c->outputConfig.BackgroundB = 1023;
c->outputConfig.OutputFlipY = 1;
c->outputSurfaceConfig.OutPixelFormat = output->format;
c->outputSurfaceConfig.OutBlkKind = output->kind;
c->outputSurfaceConfig.OutBlkHeight = 0;
c->outputSurfaceConfig.OutSurfaceWidth = output->width - 1;
c->outputSurfaceConfig.OutSurfaceHeight = output->height - 1;
c->outputSurfaceConfig.OutLumaWidth = output->stride - 1;
c->outputSurfaceConfig.OutLumaHeight = output->height - 1;
c->outputSurfaceConfig.OutChromaWidth = 16383;
c->outputSurfaceConfig.OutChromaHeight = 16383;
slot = &c->slotStruct[0].slotConfig;
slot->SlotEnable = 1;
slot->CurrentFieldEnable = 1;
slot->PlanarAlpha = 1023;
slot->ConstantAlpha = 1;
slot->SourceRectLeft = 0 << 16;
slot->SourceRectRight = (input->width - 1) << 16;
slot->SourceRectTop = 0 << 16;
slot->SourceRectBottom = (input->height - 1) << 16;
slot->DestRectLeft = 0;
slot->DestRectRight = output->width - 1;
slot->DestRectTop = 0;
slot->DestRectBottom = output->height - 1;
slot->SoftClampHigh = 1023;
surface = &c->slotStruct[0].slotSurfaceConfig;
surface->SlotPixelFormat = input->format;
surface->SlotBlkKind = input->kind;
surface->SlotBlkHeight = 0; /* XXX */
surface->SlotCacheWidth = VIC_CACHE_WIDTH_64Bx4; /* XXX */
surface->SlotSurfaceWidth = input->width - 1;
surface->SlotSurfaceHeight = input->height - 1;
surface->SlotLumaWidth = input->stride - 1;
surface->SlotLumaHeight = input->height - 1;
surface->SlotChromaWidth = 16383;
surface->SlotChromaHeight = 16383;
drm_tegra_bo_unmap(vic->config.bo);
return 0;
}
static int vic40_execute(struct vic *v, struct drm_tegra_pushbuf *pushbuf,
uint32_t **ptrp, struct vic_image *output,
struct vic_image **inputs, unsigned int num_inputs)
{
struct vic40 *vic = container_of(v, struct vic40, base);
unsigned int i;
if (num_inputs > 1)
return -EINVAL;
VIC_PUSH_METHOD(pushbuf, ptrp, NVB0B6_VIDEO_COMPOSITOR_SET_APPLICATION_ID, 1);
VIC_PUSH_METHOD(pushbuf, ptrp, NVB0B6_VIDEO_COMPOSITOR_SET_CONTROL_PARAMS, (sizeof(ConfigStruct) / 16) << 16);
VIC_PUSH_BUFFER(pushbuf, ptrp, NVB0B6_VIDEO_COMPOSITOR_SET_CONFIG_STRUCT_OFFSET, vic->config.map, 0, 0);
VIC_PUSH_BUFFER(pushbuf, ptrp, NVB0B6_VIDEO_COMPOSITOR_SET_OUTPUT_SURFACE_LUMA_OFFSET, output->map, 0, 0);
for (i = 0; i < num_inputs; i++)
VIC_PUSH_BUFFER(pushbuf, ptrp, NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE0_SLOT0_LUMA_OFFSET, inputs[i]->map, 0, 0);
VIC_PUSH_METHOD(pushbuf, ptrp, NVB0B6_VIDEO_COMPOSITOR_EXECUTE, 1 << 8);
return 0;
}
static void vic40_free(struct vic *v)
{
struct vic40 *vic = container_of(v, struct vic40, base);
drm_tegra_channel_unmap(vic->filter.map);
drm_tegra_bo_unref(vic->filter.bo);
drm_tegra_channel_unmap(vic->config.map);
drm_tegra_bo_unref(vic->config.bo);
drm_tegra_syncpoint_free(v->syncpt);
free(vic);
}
static const struct vic_ops vic40_ops = {
.fill = vic40_fill,
.blit = vic40_blit,
.flip = vic40_flip,
.execute = vic40_execute,
.free = vic40_free,
};
int vic40_new(struct drm_tegra *drm, struct drm_tegra_channel *channel,
struct vic **vicp)
{
struct vic40 *vic;
void *ptr;
int err;
vic = calloc(1, sizeof(*vic));
if (!vic)
return -ENOMEM;
vic->base.drm = drm;
vic->base.channel = channel;
vic->base.ops = &vic40_ops;
vic->base.version = 0x21;
err = drm_tegra_syncpoint_new(drm, &vic->base.syncpt);
if (err < 0) {
fprintf(stderr, "failed to allocate syncpoint: %s\n", strerror(-err));
return err;
}
err = drm_tegra_bo_new(drm, 0, 16384, &vic->config.bo);
if (err < 0) {
fprintf(stderr, "failed to allocate configuration structurer: %s\n",
strerror(-err));
return err;
}
err = drm_tegra_channel_map(channel, vic->config.bo, DRM_TEGRA_CHANNEL_MAP_READ,
&vic->config.map);
if (err < 0) {
fprintf(stderr, "failed to map configuration structure: %s\n",
strerror(-err));
return err;
}
err = drm_tegra_bo_new(drm, 0, 16384, &vic->filter.bo);
if (err < 0) {
fprintf(stderr, "failed to allocate filter buffer: %s\n",
strerror(-err));
return err;
}
err = drm_tegra_bo_map(vic->filter.bo, &ptr);
if (err < 0) {
fprintf(stderr, "failed to map filter buffer: %s\n", strerror(-err));
return err;
}
memset(ptr, 0, 16384);
drm_tegra_bo_unmap(vic->filter.bo);
err = drm_tegra_channel_map(channel, vic->filter.bo, DRM_TEGRA_CHANNEL_MAP_READ,
&vic->filter.map);
if (err < 0) {
fprintf(stderr, "failed to map filter buffer: %s\n",
strerror(-err));
return err;
}
if (vicp)
*vicp = &vic->base;
return 0;
}

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/*
* Copyright © 2016-2018 NVIDIA Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef VIC40_H
#define VIC40_H
#include <stdint.h>
#define NVB0B6_VIDEO_COMPOSITOR_SET_APPLICATION_ID 0x00000200
#define NVB0B6_VIDEO_COMPOSITOR_EXECUTE 0x00000300
#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE0_SLOT0_LUMA_OFFSET 0x00000400
#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE0_SLOT0_CHROMA_U_OFFSET 0x00000404
#define NVB0B6_VIDEO_COMPOSITOR_SET_SURFACE0_SLOT0_CHROMA_V_OFFSET 0x00000408
#define NVB0B6_VIDEO_COMPOSITOR_SET_CONTROL_PARAMS 0x00000704
#define NVB0B6_VIDEO_COMPOSITOR_SET_CONFIG_STRUCT_OFFSET 0x00000708
#define NVB0B6_VIDEO_COMPOSITOR_SET_HIST_OFFSET 0x00000714
#define NVB0B6_VIDEO_COMPOSITOR_SET_OUTPUT_SURFACE_LUMA_OFFSET 0x00000720
typedef struct {
uint64_t SlotEnable : 1; /* 0 */
uint64_t DeNoise : 1; /* 1 */
uint64_t AdvancedDenoise : 1; /* 2 */
uint64_t CadenceDetect : 1; /* 3 */
uint64_t MotionMap : 1; /* 4 */
uint64_t MMapCombine : 1; /* 5 */
uint64_t IsEven : 1; /* 6 */
uint64_t ChromaEven : 1; /* 7 */
uint64_t CurrentFieldEnable : 1; /* 8 */
uint64_t PrevFieldEnable : 1; /* 9 */
uint64_t NextFieldEnable : 1; /* 10 */
uint64_t NextNrFieldEnable : 1; /* 11 */
uint64_t CurMotionFieldEnable : 1; /* 12 */
uint64_t PrevMotionFieldEnable : 1; /* 13 */
uint64_t PpMotionFieldEnable : 1; /* 14 */
uint64_t CombMotionFieldEnable : 1; /* 15 */
uint64_t FrameFormat : 4; /* 19..16 */
uint64_t FilterLengthY : 2; /* 21..20 */
uint64_t FilterLengthX : 2; /* 23..22 */
uint64_t Panoramic : 12; /* 35..24 */
uint64_t reserved1 : 22; /* 57..36 */
uint64_t DetailFltClamp : 6; /* 63..58 */
uint64_t FilterNoise : 10; /* 73..64 */
uint64_t FilterDetail : 10; /* 83..74 */
uint64_t ChromaNoise : 10; /* 93..84 */
uint64_t ChromaDetail : 10; /* 103..94 */
uint64_t DeinterlaceMode : 4; /* 107..104 */
uint64_t MotionAccumWeight : 3; /* 110..108 */
uint64_t NoiseIir : 11; /* 121..111 */
uint64_t LightLevel : 4; /* 125..122 */
uint64_t reserved4 : 2; /* 127..126 */
/* 128 */
uint64_t SoftClampLow : 10; /* 9..0 */
uint64_t SoftClampHigh : 10; /* 19..10 */
uint64_t reserved5 : 3; /* 22..20 */
uint64_t reserved6 : 9; /* 31..23 */
uint64_t PlanarAlpha : 10; /* 41..32 */
uint64_t ConstantAlpha : 1; /* 42 */
uint64_t StereoInterleave : 3; /* 45..43 */
uint64_t ClipEnabled : 1; /* 46 */
uint64_t ClearRectMask : 8; /* 54..47 */
uint64_t DegammaMode : 2; /* 56..55 */
uint64_t reserved7 : 1; /* 57 */
uint64_t DecompressEnable : 1; /* 58 */
uint64_t reserved9 : 5; /* 63..59 */
uint64_t DecompressCtbCount : 8; /* 71..64 */
uint64_t DecompressZbcColor : 32; /* 103..72 */
uint64_t reserved12 : 24; /* 127..104 */
/* 256 */
uint64_t SourceRectLeft : 30; /* 29..0 */
uint64_t reserved14 : 2; /* 31..30 */
uint64_t SourceRectRight : 30; /* 61..32 */
uint64_t reserved15 : 2; /* 63..62 */
uint64_t SourceRectTop : 30; /* 93..64 */
uint64_t reserved16 : 2; /* 95..94 */
uint64_t SourceRectBottom : 30; /* 125..96 */
uint64_t reserved17 : 2; /* 127..126 */
/* 384 */
uint64_t DestRectLeft : 14; /* 13..0 */
uint64_t reserved18 : 2; /* 15..14 */
uint64_t DestRectRight : 14; /* 29..16 */
uint64_t reserved19 : 2; /* 31..30 */
uint64_t DestRectTop : 14; /* 45..32 */
uint64_t reserved20 : 2; /* 47..46 */
uint64_t DestRectBottom : 14; /* 61..48 */
uint64_t reserved21 : 2; /* 63..62 */
uint64_t reserved22 : 32; /* 95..64 */
uint64_t reserved23 : 32; /* 127..96 */
} SlotConfig;
typedef struct {
uint64_t SlotPixelFormat : 7; /* 6..0 */
uint64_t SlotChromaLocHoriz : 2; /* 8..7 */
uint64_t SlotChromaLocVert : 2; /* 10..9 */
uint64_t SlotBlkKind : 4; /* 14..11 */
uint64_t SlotBlkHeight : 4; /* 18..15 */
uint64_t SlotCacheWidth : 3; /* 21..19 */
uint64_t reserved0 : 10; /* 31..22 */
uint64_t SlotSurfaceWidth : 14; /* 45..32 */
uint64_t SlotSurfaceHeight : 14; /* 59..46 */
uint64_t reserved1 : 4; /* 63..60 */
uint64_t SlotLumaWidth : 14; /* 77..64 */
uint64_t SlotLumaHeight : 14; /* 91..78 */
uint64_t reserved2 : 4; /* 95..92 */
uint64_t SlotChromaWidth : 14; /* 109..96 */
uint64_t SlotChromaHeight : 14; /* 123..110 */
uint64_t reserved3 : 4; /* 127..124 */
} SlotSurfaceConfig;
typedef struct {
uint64_t luma_coeff0 : 20; /* 19..0 */
uint64_t luma_coeff1 : 20; /* 39..20 */
uint64_t luma_coeff2 : 20; /* 59..40 */
uint64_t luma_r_shift : 4; /* 63..60 */
uint64_t luma_coeff3 : 20; /* 83..64 */
uint64_t LumaKeyLower : 10; /* 93..84 */
uint64_t LumaKeyUpper : 10; /* 103..94 */
uint64_t LumaKeyEnabled : 1; /* 104 */
uint64_t reserved0 : 2; /* 106..105 */
uint64_t reserved1 : 21; /* 127..107 */
} LumaKeyStruct;
typedef struct {
uint64_t matrix_coeff00 : 20; /* 19..0 */
uint64_t matrix_coeff10 : 20; /* 39..20 */
uint64_t matrix_coeff20 : 20; /* 59..40 */
uint64_t matrix_r_shift : 4; /* 63..60 */
uint64_t matrix_coeff01 : 20; /* 83..64 */
uint64_t matrix_coeff11 : 20; /* 103..84 */
uint64_t matrix_coeff21 : 20; /* 123..104 */
uint64_t reserved0 : 3; /* 126..124 */
uint64_t matrix_enable : 1; /* 127 */
/* 128 */
uint64_t matrix_coeff02 : 20; /* 19..0 */
uint64_t matrix_coeff12 : 20; /* 39..20 */
uint64_t matrix_coeff22 : 20; /* 59..40 */
uint64_t reserved1 : 4; /* 63..60 */
uint64_t matrix_coeff03 : 20; /* 83..64 */
uint64_t matrix_coeff13 : 20; /* 103..84 */
uint64_t matrix_coeff23 : 20; /* 123..104 */
uint64_t reserved2 : 4; /* 127..124 */
} MatrixStruct;
typedef struct {
uint64_t ClearRect0Left : 14; /* 13..0 */
uint64_t reserved0 : 2; /* 15..14 */
uint64_t ClearRect0Right : 14; /* 29..16 */
uint64_t reserved1 : 2; /* 31..30 */
uint64_t ClearRect0Top : 14; /* 45..32 */
uint64_t reserved2 : 2; /* 47..46 */
uint64_t ClearRect0Bottom : 14; /* 61..48 */
uint64_t reserved3 : 2; /* 63..62 */
uint64_t ClearRect1Left : 14; /* 77..64 */
uint64_t reserved4 : 2; /* 79..78 */
uint64_t ClearRect1Right : 14; /* 93..80 */
uint64_t reserved5 : 2; /* 95..94 */
uint64_t ClearRect1Top : 14; /* 109..96 */
uint64_t reserved6 : 2; /* 111..110 */
uint64_t ClearRect1Bottom : 14; /* 125..112 */
uint64_t reserved7 : 2; /* 127..126 */
} ClearRectStruct;
typedef struct {
uint64_t AlphaK1 : 10; /* 9..0 */
uint64_t reserved0 : 6; /* 15..10 */
uint64_t AlphaK2 : 10; /* 25..16 */
uint64_t reserved1 : 6; /* 31..26 */
uint64_t SrcFactCMatchSelect : 3; /* 34..32 */
uint64_t reserved2 : 1; /* 35 */
uint64_t DstFactCMatchSelect : 3; /* 38..36 */
uint64_t reserved3 : 1; /* 39 */
uint64_t SrcFactAMatchSelect : 3; /* 42..40 */
uint64_t reserved4 : 1; /* 43 */
uint64_t DstFactAMatchSelect : 3; /* 46..44 */
uint64_t reserved5 : 1; /* 47 */
uint64_t reserved6 : 4; /* 51..48 */
uint64_t reserved7 : 4; /* 55..52 */
uint64_t reserved8 : 4; /* 59..56 */
uint64_t reserved9 : 4; /* 63..60 */
uint64_t reserved10 : 2; /* 65..64 */
uint64_t OverrideR : 10; /* 75..66 */
uint64_t OverrideG : 10; /* 85..76 */
uint64_t OverrideB : 10; /* 95..86 */
uint64_t OverrideA : 10; /* 105..96 */
uint64_t reserved11 : 2; /* 107..106 */
uint64_t UseOverrideR : 1; /* 108 */
uint64_t UseOverrideG : 1; /* 109 */
uint64_t UseOverrideB : 1; /* 110 */
uint64_t UseOverrideA : 1; /* 111 */
uint64_t MaskR : 1; /* 112 */
uint64_t MaskG : 1; /* 113 */
uint64_t MaskB : 1; /* 114 */
uint64_t MaskA : 1; /* 115 */
uint64_t reserved12 : 12; /* 127..116 */
} BlendingSlotStruct;
typedef struct {
uint64_t AlphaFillMode : 3; /* 2..0 */
uint64_t AlphaFillSlot : 3; /* 5..3 */
uint64_t BackgroundAlpha : 10; /* 15..6 */
uint64_t BackgroundR : 10; /* 25..16 */
uint64_t BackgroundG : 10; /* 35..26 */
uint64_t BackgroundB : 10; /* 45..36 */
uint64_t RegammaMode : 2; /* 47..46 */
uint64_t OutputFlipX : 1; /* 48 */
uint64_t OutputFlipY : 1; /* 49 */
uint64_t OutputTranspose : 1; /* 50 */
uint64_t reserved1 : 1; /* 51 */
uint64_t reserved2 : 12; /* 63..52 */
uint64_t TargetRectLeft : 14; /* 77..64 */
uint64_t reserved3 : 2; /* 79..78 */
uint64_t TargetRectRight : 14; /* 93..80 */
uint64_t reserved4 : 2; /* 95..94 */
uint64_t TargetRectTop : 14; /* 109..96 */
uint64_t reserved5 : 2; /* 111..110 */
uint64_t TargetRectBottom : 14; /* 125..112 */
uint64_t reserved6 : 2; /* 127..126 */
} OutputConfig;
typedef struct {
uint64_t OutPixelFormat : 7; /* 6..0 */
uint64_t OutChromaLocHoriz : 2; /* 8..7 */
uint64_t OutChromaLocVert : 2; /* 10..9 */
uint64_t OutBlkKind : 4; /* 14..11 */
uint64_t OutBlkHeight : 4; /* 18..15 */
uint64_t reserved0 : 3; /* 21..19 */
uint64_t reserved1 : 10; /* 31..22 */
uint64_t OutSurfaceWidth : 14; /* 45..32 */
uint64_t OutSurfaceHeight : 14; /* 59..46 */
uint64_t reserved2 : 4; /* 63..60 */
uint64_t OutLumaWidth : 14; /* 77..64 */
uint64_t OutLumaHeight : 14; /* 91..78 */
uint64_t reserved3 : 4; /* 95..92 */
uint64_t OutChromaWidth : 14; /* 109..96 */
uint64_t OutChromaHeight : 14; /* 123..110 */
uint64_t reserved4 : 4; /* 127..124 */
} OutputSurfaceConfig;
typedef struct {
uint64_t DownsampleHoriz : 11; /* 10..0 */
uint64_t reserved0 : 5; /* 15..11 */
uint64_t DownsampleVert : 11; /* 26..16 */
uint64_t reserved1 : 5; /* 31..27 */
uint64_t reserved2 : 32; /* 63..32 */
uint64_t reserved3 : 32; /* 95..64 */
uint64_t reserved4 : 32; /* 127..96 */
} PipeConfig;
typedef struct {
SlotConfig slotConfig;
SlotSurfaceConfig slotSurfaceConfig;
LumaKeyStruct lumaKeyStruct;
MatrixStruct colorMatrixStruct;
MatrixStruct gamutMatrixStruct;
BlendingSlotStruct blendingSlotStruct;
} SlotStruct;
typedef struct {
PipeConfig pipeConfig;
OutputConfig outputConfig;
OutputSurfaceConfig outputSurfaceConfig;
MatrixStruct outColorMatrixStruct;
ClearRectStruct clearRectStruct[4];
SlotStruct slotStruct[8];
} ConfigStruct;
#endif

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/*
* Copyright © 2018 NVIDIA Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <errno.h>
#include <string.h>
#include "private.h"
#include "tegra.h"
#include "vic.h"
#include "vic41.h"
struct vic41 {
struct vic base;
struct {
struct drm_tegra_mapping *map;
struct drm_tegra_bo *bo;
} config;
struct {
struct drm_tegra_mapping *map;
struct drm_tegra_bo *bo;
} filter;
};
static int vic41_fill(struct vic *v, struct vic_image *output,
unsigned int left, unsigned int top,
unsigned int right, unsigned int bottom,
unsigned int alpha, unsigned int red,
unsigned int green, unsigned int blue)
{
struct vic41 *vic = container_of(v, struct vic41, base);
ConfigStruct *c;
int err;
err = drm_tegra_bo_map(vic->config.bo, (void **)&c);
if (err < 0) {
fprintf(stderr, "failed to map configuration structure: %s\n",
strerror(-err));
return err;
}
memset(c, 0, sizeof(*c));
c->outputConfig.TargetRectTop = top;
c->outputConfig.TargetRectLeft = left;
c->outputConfig.TargetRectRight = right;
c->outputConfig.TargetRectBottom = bottom;
c->outputConfig.BackgroundAlpha = alpha;
c->outputConfig.BackgroundR = red;
c->outputConfig.BackgroundG = green;
c->outputConfig.BackgroundB = blue;
c->outputSurfaceConfig.OutPixelFormat = output->format;
c->outputSurfaceConfig.OutBlkKind = output->kind;
c->outputSurfaceConfig.OutBlkHeight = 0;
c->outputSurfaceConfig.OutSurfaceWidth = output->width - 1;
c->outputSurfaceConfig.OutSurfaceHeight = output->height - 1;
c->outputSurfaceConfig.OutLumaWidth = output->stride - 1;
c->outputSurfaceConfig.OutLumaHeight = output->height - 1;
c->outputSurfaceConfig.OutChromaWidth = 16383;
c->outputSurfaceConfig.OutChromaHeight = 16383;
drm_tegra_bo_unmap(vic->config.bo);
return 0;
}
static int vic41_blit(struct vic *v, struct vic_image *output,
struct vic_image *input)
{
struct vic41 *vic = container_of(v, struct vic41, base);
SlotSurfaceConfig *surface;
SlotConfig *slot;
ConfigStruct *c;
int err;
err = drm_tegra_bo_map(vic->config.bo, (void **)&c);
if (err < 0) {
fprintf(stderr, "failed to map configuration structure: %s\n",
strerror(-err));
return err;
}
memset(c, 0, sizeof(*c));
c->outputConfig.TargetRectTop = 0;
c->outputConfig.TargetRectLeft = 0;
c->outputConfig.TargetRectRight = output->width - 1;
c->outputConfig.TargetRectBottom = output->height - 1;
c->outputConfig.BackgroundAlpha = 255;
c->outputConfig.BackgroundR = 1023;
c->outputConfig.BackgroundG = 1023;
c->outputConfig.BackgroundB = 1023;
c->outputSurfaceConfig.OutPixelFormat = output->format;
c->outputSurfaceConfig.OutBlkKind = output->kind;
c->outputSurfaceConfig.OutBlkHeight = 0;
c->outputSurfaceConfig.OutSurfaceWidth = output->width - 1;
c->outputSurfaceConfig.OutSurfaceHeight = output->height - 1;
c->outputSurfaceConfig.OutLumaWidth = output->stride - 1;
c->outputSurfaceConfig.OutLumaHeight = output->height - 1;
c->outputSurfaceConfig.OutChromaWidth = 16383;
c->outputSurfaceConfig.OutChromaHeight = 16383;
slot = &c->slotStruct[0].slotConfig;
slot->SlotEnable = 1;
slot->CurrentFieldEnable = 1;
slot->PlanarAlpha = 255;
slot->ConstantAlpha = 1;
slot->SourceRectLeft = 0 << 16;
slot->SourceRectRight = (input->width - 1) << 16;
slot->SourceRectTop = 0 << 16;
slot->SourceRectBottom = (input->height - 1) << 16;
slot->DestRectLeft = 0;
slot->DestRectRight = output->width - 1;
slot->DestRectTop = 0;
slot->DestRectBottom = output->height - 1;
slot->SoftClampHigh = 1023;
surface = &c->slotStruct[0].slotSurfaceConfig;
surface->SlotPixelFormat = input->format;
surface->SlotBlkKind = input->kind;
surface->SlotBlkHeight = 0; /* XXX */
surface->SlotCacheWidth = VIC_CACHE_WIDTH_64Bx4; /* XXX */
surface->SlotSurfaceWidth = input->width - 1;
surface->SlotSurfaceHeight = input->height - 1;
surface->SlotLumaWidth = input->stride - 1;
surface->SlotLumaHeight = input->height - 1;
surface->SlotChromaWidth = 16383;
surface->SlotChromaHeight = 16383;
drm_tegra_bo_unmap(vic->config.bo);
return 0;
}
static int vic41_flip(struct vic *v, struct vic_image *output,
struct vic_image *input)
{
struct vic41 *vic = container_of(v, struct vic41, base);
SlotSurfaceConfig *surface;
SlotConfig *slot;
ConfigStruct *c;
int err;
err = drm_tegra_bo_map(vic->config.bo, (void **)&c);
if (err < 0) {
fprintf(stderr, "failed to map configuration structure: %s\n",
strerror(-err));
return err;
}
memset(c, 0, sizeof(*c));
c->outputConfig.TargetRectTop = 0;
c->outputConfig.TargetRectLeft = 0;
c->outputConfig.TargetRectRight = output->width - 1;
c->outputConfig.TargetRectBottom = output->height - 1;
c->outputConfig.BackgroundAlpha = 255;
c->outputConfig.BackgroundR = 1023;
c->outputConfig.BackgroundG = 1023;
c->outputConfig.BackgroundB = 1023;
c->outputConfig.OutputFlipY = 1;
c->outputSurfaceConfig.OutPixelFormat = output->format;
c->outputSurfaceConfig.OutBlkKind = output->kind;
c->outputSurfaceConfig.OutBlkHeight = 0;
c->outputSurfaceConfig.OutSurfaceWidth = output->width - 1;
c->outputSurfaceConfig.OutSurfaceHeight = output->height - 1;
c->outputSurfaceConfig.OutLumaWidth = output->stride - 1;
c->outputSurfaceConfig.OutLumaHeight = output->height - 1;
c->outputSurfaceConfig.OutChromaWidth = 16383;
c->outputSurfaceConfig.OutChromaHeight = 16383;
slot = &c->slotStruct[0].slotConfig;
slot->SlotEnable = 1;
slot->CurrentFieldEnable = 1;
slot->PlanarAlpha = 255;
slot->ConstantAlpha = 1;
slot->SourceRectLeft = 0 << 16;
slot->SourceRectRight = (input->width - 1) << 16;
slot->SourceRectTop = 0 << 16;
slot->SourceRectBottom = (input->height - 1) << 16;
slot->DestRectLeft = 0;
slot->DestRectRight = output->width - 1;
slot->DestRectTop = 0;
slot->DestRectBottom = output->height - 1;
slot->SoftClampHigh = 1023;
surface = &c->slotStruct[0].slotSurfaceConfig;
surface->SlotPixelFormat = input->format;
surface->SlotBlkKind = input->kind;
surface->SlotBlkHeight = 0; /* XXX */
surface->SlotCacheWidth = VIC_CACHE_WIDTH_64Bx4; /* XXX */
surface->SlotSurfaceWidth = input->width - 1;
surface->SlotSurfaceHeight = input->height - 1;
surface->SlotLumaWidth = input->stride - 1;
surface->SlotLumaHeight = input->height - 1;
surface->SlotChromaWidth = 16383;
surface->SlotChromaHeight = 16383;
drm_tegra_bo_unmap(vic->config.bo);
return 0;
}
static int vic41_execute(struct vic *v, struct drm_tegra_pushbuf *pushbuf,
uint32_t **ptrp, struct vic_image *output,
struct vic_image **inputs, unsigned int num_inputs)
{
struct vic41 *vic = container_of(v, struct vic41, base);
unsigned int i;
if (num_inputs > 1)
return -EINVAL;
VIC_PUSH_METHOD(pushbuf, ptrp, NVB1B6_VIDEO_COMPOSITOR_SET_APPLICATION_ID, 1);
VIC_PUSH_METHOD(pushbuf, ptrp, NVB1B6_VIDEO_COMPOSITOR_SET_CONTROL_PARAMS, (sizeof(ConfigStruct) / 16) << 16);
VIC_PUSH_BUFFER(pushbuf, ptrp, NVB1B6_VIDEO_COMPOSITOR_SET_CONFIG_STRUCT_OFFSET, vic->config.map, 0, 0);
VIC_PUSH_BUFFER(pushbuf, ptrp, NVB1B6_VIDEO_COMPOSITOR_SET_FILTER_STRUCT_OFFSET, vic->filter.map, 0, 0);
VIC_PUSH_BUFFER(pushbuf, ptrp, NVB1B6_VIDEO_COMPOSITOR_SET_OUTPUT_SURFACE_LUMA_OFFSET, output->map, 0, 0);
for (i = 0; i < num_inputs; i++) {
uint32_t method = NVB1B6_VIDEO_COMPOSITOR_SET_SURFACE0_LUMA_OFFSET(0) + (i * 3) * 4;
VIC_PUSH_BUFFER(pushbuf, ptrp, method, inputs[i]->map, 0, 0);
}
VIC_PUSH_METHOD(pushbuf, ptrp, NVB1B6_VIDEO_COMPOSITOR_EXECUTE, 1 << 8);
return 0;
}
static void vic41_free(struct vic *v)
{
struct vic41 *vic = container_of(v, struct vic41, base);
drm_tegra_channel_unmap(vic->filter.map);
drm_tegra_bo_unref(vic->filter.bo);
drm_tegra_channel_unmap(vic->config.map);
drm_tegra_bo_unref(vic->config.bo);
drm_tegra_syncpoint_free(v->syncpt);
free(vic);
}
static const struct vic_ops vic41_ops = {
.fill = vic41_fill,
.blit = vic41_blit,
.flip = vic41_flip,
.execute = vic41_execute,
.free = vic41_free,
};
int vic41_new(struct drm_tegra *drm, struct drm_tegra_channel *channel,
struct vic **vicp)
{
struct vic41 *vic;
void *ptr;
int err;
vic = calloc(1, sizeof(*vic));
if (!vic)
return -ENOMEM;
vic->base.drm = drm;
vic->base.channel = channel;
vic->base.ops = &vic41_ops;
vic->base.version = 0x18;
err = drm_tegra_syncpoint_new(drm, &vic->base.syncpt);
if (err < 0) {
fprintf(stderr, "failed to allocate syncpoint: %s\n", strerror(-err));
return err;
}
err = drm_tegra_bo_new(drm, 0, 16384, &vic->config.bo);
if (err < 0) {
fprintf(stderr, "failed to allocate configuration structurer: %s\n",
strerror(-err));
return err;
}
err = drm_tegra_channel_map(channel, vic->config.bo, DRM_TEGRA_CHANNEL_MAP_READ,
&vic->config.map);
if (err < 0) {
fprintf(stderr, "failed to map configuration structure: %s\n",
strerror(-err));
return err;
}
err = drm_tegra_bo_new(drm, 0, 16384, &vic->filter.bo);
if (err < 0) {
fprintf(stderr, "failed to allocate filter buffer: %s\n",
strerror(-err));
return err;
}
err = drm_tegra_bo_map(vic->filter.bo, &ptr);
if (err < 0) {
fprintf(stderr, "failed to map filter buffer: %s\n", strerror(-err));
return err;
}
memset(ptr, 0, 16384);
drm_tegra_bo_unmap(vic->filter.bo);
err = drm_tegra_channel_map(channel, vic->filter.bo, DRM_TEGRA_CHANNEL_MAP_READ,
&vic->filter.map);
if (err < 0) {
fprintf(stderr, "failed to map filter buffer: %s\n",
strerror(-err));
return err;
}
if (vicp)
*vicp = &vic->base;
return 0;
}

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/*
* Copyright © 2018 NVIDIA Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef VIC41_H
#define VIC41_H
#include <stdint.h>
#define NVB1B6_VIDEO_COMPOSITOR_SET_APPLICATION_ID 0x00000200
#define NVB1B6_VIDEO_COMPOSITOR_EXECUTE 0x00000300
#define NVB1B6_VIDEO_COMPOSITOR_SET_PICTURE_INDEX 0x00000700
#define NVB1B6_VIDEO_COMPOSITOR_SET_CONTROL_PARAMS 0x00000704
#define NVB1B6_VIDEO_COMPOSITOR_SET_CONFIG_STRUCT_OFFSET 0x00000708
#define NVB1B6_VIDEO_COMPOSITOR_SET_FILTER_STRUCT_OFFSET 0x0000070c
#define NVB1B6_VIDEO_COMPOSITOR_SET_HIST_OFFSET 0x00000714
#define NVB1B6_VIDEO_COMPOSITOR_SET_OUTPUT_SURFACE_LUMA_OFFSET 0x00000720
#define NVB1B6_VIDEO_COMPOSITOR_SET_HISTORY_BUFFER_OFFSET(slot) (0x00000780 + (slot) * 4)
#define NVB1B6_VIDEO_COMPOSITOR_SET_SURFACE0_LUMA_OFFSET(slot) (0x00001200 + (slot) * 0x00000060)
#define NVB1B6_VIDEO_COMPOSITOR_SET_SURFACE0_CHROMA_U_OFFSET(slot) (0x00001204 + (slot) * 0x00000060)
#define NVB1B6_VIDEO_COMPOSITOR_SET_SURFACE0_CHROMA_V_OFFSET(slot) (0x00001208 + (slot) * 0x00000060)
#define NVB1B6_VIDEO_COMPOSITOR_SET_SURFACE1_LUMA_OFFSET(slot) (0x0000120c + (slot) * 0x00000060)
#define NVB1B6_VIDEO_COMPOSITOR_SET_SURFACE1_CHROMA_U_OFFSET(slot) (0x00001210 + (slot) * 0x00000060)
#define NVB1B6_VIDEO_COMPOSITOR_SET_SURFACE1_CHROMA_V_OFFSET(slot) (0x00001214 + (slot) * 0x00000060)
#define NVB1B6_VIDEO_COMPOSITOR_SET_SURFACE2_LUMA_OFFSET(slot) (0x00001218 + (slot) * 0x00000060)
#define NVB1B6_VIDEO_COMPOSITOR_SET_SURFACE2_CHROMA_U_OFFSET(slot) (0x0000121c + (slot) * 0x00000060)
#define NVB1B6_VIDEO_COMPOSITOR_SET_SURFACE2_CHROMA_V_OFFSET(slot) (0x00001220 + (slot) * 0x00000060)
#define NVB1B6_VIDEO_COMPOSITOR_SET_SURFACE3_LUMA_OFFSET(slot) (0x00001224 + (slot) * 0x00000060)
#define NVB1B6_VIDEO_COMPOSITOR_SET_SURFACE3_CHROMA_U_OFFSET(slot) (0x00001228 + (slot) * 0x00000060)
#define NVB1B6_VIDEO_COMPOSITOR_SET_SURFACE3_CHROMA_V_OFFSET(slot) (0x0000122c + (slot) * 0x00000060)
#define NVB1B6_VIDEO_COMPOSITOR_SET_SURFACE4_LUMA_OFFSET(slot) (0x00001230 + (slot) * 0x00000060)
#define NVB1B6_VIDEO_COMPOSITOR_SET_SURFACE4_CHROMA_U_OFFSET(slot) (0x00001234 + (slot) * 0x00000060)
#define NVB1B6_VIDEO_COMPOSITOR_SET_SURFACE4_CHROMA_V_OFFSET(slot) (0x00001238 + (slot) * 0x00000060)
#define NVB1B6_VIDEO_COMPOSITOR_SET_SURFACE5_LUMA_OFFSET(slot) (0x0000123c + (slot) * 0x00000060)
#define NVB1B6_VIDEO_COMPOSITOR_SET_SURFACE5_CHROMA_U_OFFSET(slot) (0x00001240 + (slot) * 0x00000060)
#define NVB1B6_VIDEO_COMPOSITOR_SET_SURFACE5_CHROMA_V_OFFSET(slot) (0x00001244 + (slot) * 0x00000060)
#define NVB1B6_VIDEO_COMPOSITOR_SET_SURFACE6_LUMA_OFFSET(slot) (0x00001248 + (slot) * 0x00000060)
#define NVB1B6_VIDEO_COMPOSITOR_SET_SURFACE6_CHROMA_U_OFFSET(slot) (0x0000124c + (slot) * 0x00000060)
#define NVB1B6_VIDEO_COMPOSITOR_SET_SURFACE6_CHROMA_V_OFFSET(slot) (0x00001250 + (slot) * 0x00000060)
#define NVB1B6_VIDEO_COMPOSITOR_SET_SURFACE7_LUMA_OFFSET(slot) (0x00001254 + (slot) * 0x00000060)
#define NVB1B6_VIDEO_COMPOSITOR_SET_SURFACE7_CHROMA_U_OFFSET(slot) (0x00001258 + (slot) * 0x00000060)
#define NVB1B6_VIDEO_COMPOSITOR_SET_SURFACE7_CHROMA_V_OFFSET(slot) (0x0000125c + (slot) * 0x00000060)
typedef struct {
uint64_t SlotEnable : 1; /* 0 */
uint64_t DeNoise : 1; /* 1 */
uint64_t AdvancedDenoise : 1; /* 2 */
uint64_t CadenceDetect : 1; /* 3 */
uint64_t MotionMap : 1; /* 4 */
uint64_t MMapCombine : 1; /* 5 */
uint64_t IsEven : 1; /* 6 */
uint64_t ChromaEven : 1; /* 7 */
uint64_t CurrentFieldEnable : 1; /* 8 */
uint64_t PrevFieldEnable : 1; /* 9 */
uint64_t NextFieldEnable : 1; /* 10 */
uint64_t NextNrFieldEnable : 1; /* 11 */
uint64_t CurMotionFieldEnable : 1; /* 12 */
uint64_t PrevMotionFieldEnable : 1; /* 13 */
uint64_t PpMotionFieldEnable : 1; /* 14 */
uint64_t CombMotionFieldEnable : 1; /* 15 */
uint64_t FrameFormat : 4; /* 19..16 */
uint64_t FilterLengthY : 2; /* 21..20 */
uint64_t FilterLengthX : 2; /* 23..22 */
uint64_t Panoramic : 12; /* 35..24 */
uint64_t ChromaUpLengthY : 2; /* 37..36 */
uint64_t ChromaUpLengthX : 2; /* 39..38 */
uint64_t reserved1 : 18; /* 57..40 */
uint64_t DetailFltClamp : 6; /* 63..58 */
uint64_t FilterNoise : 10; /* 73..64 */
uint64_t FilterDetail : 10; /* 83..74 */
uint64_t ChromaNoise : 10; /* 93..84 */
uint64_t ChromaDetail : 10; /* 103..94 */
uint64_t DeinterlaceMode : 4; /* 107..104 */
uint64_t MotionAccumWeight : 3; /* 110..108 */
uint64_t NoiseIir : 11; /* 121..111 */
uint64_t LightLevel : 4; /* 125..122 */
uint64_t reserved4 : 2; /* 127..126 */
/* 128 */
uint64_t SoftClampLow : 10; /* 9..0 */
uint64_t SoftClampHigh : 10; /* 19..10 */
uint64_t reserved5 : 12; /* 31..20 */
uint64_t reserved6 : 2; /* 33..32 */
uint64_t PlanarAlpha : 8; /* 41..34 */
uint64_t ConstantAlpha : 1; /* 42 */
uint64_t StereoInterleave : 3; /* 45..43 */
uint64_t ClipEnabled : 1; /* 46 */
uint64_t ClearRectMask : 8; /* 54..47 */
uint64_t DegammaMode : 2; /* 56..55 */
uint64_t reserved7 : 1; /* 57 */
uint64_t DecompressEnable : 1; /* 58 */
uint64_t DecompressKind : 4; /* 62..59 */
uint64_t reserved9 : 1; /* 63 */
uint64_t DecompressCtbCount : 8; /* 71..64 */
uint64_t DecompressZbcColor : 32; /* 103..72 */
uint64_t reserved12 : 24; /* 127..104 */
/* 256 */
uint64_t SourceRectLeft : 30; /* 29..0 */
uint64_t reserved14 : 2; /* 31..30 */
uint64_t SourceRectRight : 30; /* 61..32 */
uint64_t reserved15 : 2; /* 63..62 */
uint64_t SourceRectTop : 30; /* 93..64 */
uint64_t reserved16 : 2; /* 95..94 */
uint64_t SourceRectBottom : 30; /* 125..96 */
uint64_t reserved17 : 2; /* 127..126 */
/* 384 */
uint64_t DestRectLeft : 14; /* 13..0 */
uint64_t reserved18 : 2; /* 15..14 */
uint64_t DestRectRight : 14; /* 29..16 */
uint64_t reserved19 : 2; /* 31..30 */
uint64_t DestRectTop : 14; /* 45..32 */
uint64_t reserved20 : 2; /* 47..46 */
uint64_t DestRectBottom : 14; /* 61..48 */
uint64_t reserved21 : 2; /* 63..62 */
uint64_t reserved22 : 32; /* 95..64 */
uint64_t reserved23 : 32; /* 127..96 */
} SlotConfig;
typedef struct {
uint64_t SlotPixelFormat : 7; /* 6..0 */
uint64_t SlotChromaLocHoriz : 2; /* 8..7 */
uint64_t SlotChromaLocVert : 2; /* 10..9 */
uint64_t SlotBlkKind : 4; /* 14..11 */
uint64_t SlotBlkHeight : 4; /* 18..15 */
uint64_t SlotCacheWidth : 3; /* 21..19 */
uint64_t reserved0 : 10; /* 31..22 */
uint64_t SlotSurfaceWidth : 14; /* 45..32 */
uint64_t SlotSurfaceHeight : 14; /* 59..46 */
uint64_t reserved1 : 4; /* 63..60 */
uint64_t SlotLumaWidth : 14; /* 77..64 */
uint64_t SlotLumaHeight : 14; /* 91..78 */
uint64_t reserved2 : 4; /* 95..92 */
uint64_t SlotChromaWidth : 14; /* 109..96 */
uint64_t SlotChromaHeight : 14; /* 123..110 */
uint64_t reserved3 : 4; /* 127..124 */
} SlotSurfaceConfig;
typedef struct {
uint64_t luma_coeff0 : 20; /* 19..0 */
uint64_t luma_coeff1 : 20; /* 39..20 */
uint64_t luma_coeff2 : 20; /* 59..40 */
uint64_t luma_r_shift : 4; /* 63..60 */
uint64_t luma_coeff3 : 20; /* 83..64 */
uint64_t LumaKeyLower : 10; /* 93..84 */
uint64_t LumaKeyUpper : 10; /* 103..94 */
uint64_t LumaKeyEnabled : 1; /* 104 */
uint64_t reserved0 : 2; /* 106..105 */
uint64_t reserved1 : 21; /* 127..107 */
} LumaKeyStruct;
typedef struct {
uint64_t matrix_coeff00 : 20; /* 19..0 */
uint64_t matrix_coeff10 : 20; /* 39..20 */
uint64_t matrix_coeff20 : 20; /* 59..40 */
uint64_t matrix_r_shift : 4; /* 63..60 */
uint64_t matrix_coeff01 : 20; /* 83..64 */
uint64_t matrix_coeff11 : 20; /* 103..84 */
uint64_t matrix_coeff21 : 20; /* 123..104 */
uint64_t reserved0 : 3; /* 126..124 */
uint64_t matrix_enable : 1; /* 127 */
/* 128 */
uint64_t matrix_coeff02 : 20; /* 19..0 */
uint64_t matrix_coeff12 : 20; /* 39..20 */
uint64_t matrix_coeff22 : 20; /* 59..40 */
uint64_t reserved1 : 4; /* 63..60 */
uint64_t matrix_coeff03 : 20; /* 83..64 */
uint64_t matrix_coeff13 : 20; /* 103..84 */
uint64_t matrix_coeff23 : 20; /* 123..104 */
uint64_t reserved2 : 4; /* 127..124 */
} MatrixStruct;
typedef struct {
uint64_t ClearRect0Left : 14; /* 13..0 */
uint64_t reserved0 : 2; /* 15..14 */
uint64_t ClearRect0Right : 14; /* 29..16 */
uint64_t reserved1 : 2; /* 31..30 */
uint64_t ClearRect0Top : 14; /* 45..32 */
uint64_t reserved2 : 2; /* 47..46 */
uint64_t ClearRect0Bottom : 14; /* 61..48 */
uint64_t reserved3 : 2; /* 63..62 */
uint64_t ClearRect1Left : 14; /* 77..64 */
uint64_t reserved4 : 2; /* 79..78 */
uint64_t ClearRect1Right : 14; /* 93..80 */
uint64_t reserved5 : 2; /* 95..94 */
uint64_t ClearRect1Top : 14; /* 109..96 */
uint64_t reserved6 : 2; /* 111..110 */
uint64_t ClearRect1Bottom : 14; /* 125..112 */
uint64_t reserved7 : 2; /* 127..126 */
} ClearRectStruct;
typedef struct {
uint64_t reserved0 : 2; /* 1..0 */
uint64_t AlphaK1 : 8; /* 9..2 */
uint64_t reserved1 : 6; /* 17..10 */
uint64_t AlphaK2 : 8; /* 25..18 */
uint64_t reserved2 : 6; /* 31..26 */
uint64_t SrcFactCMatchSelect : 3; /* 34..32 */
uint64_t reserved3 : 1; /* 35 */
uint64_t DstFactCMatchSelect : 3; /* 38..36 */
uint64_t reserved4 : 1; /* 39 */
uint64_t SrcFactAMatchSelect : 3; /* 42..40 */
uint64_t reserved5 : 1; /* 43 */
uint64_t DstFactAMatchSelect : 3; /* 46..44 */
uint64_t reserved6 : 1; /* 47 */
uint64_t reserved7 : 4; /* 51..48 */
uint64_t reserved8 : 4; /* 55..52 */
uint64_t reserved9 : 4; /* 59..56 */
uint64_t reserved10 : 4; /* 63..60 */
uint64_t reserved11 : 2; /* 65..64 */
uint64_t OverrideR : 10; /* 75..66 */
uint64_t OverrideG : 10; /* 85..76 */
uint64_t OverrideB : 10; /* 95..86 */
uint64_t reserved12 : 2; /* 97..96 */
uint64_t OverrideA : 8; /* 105..98 */
uint64_t reserved13 : 2; /* 107..106 */
uint64_t UseOverrideR : 1; /* 108 */
uint64_t UseOverrideG : 1; /* 109 */
uint64_t UseOverrideB : 1; /* 110 */
uint64_t UseOverrideA : 1; /* 111 */
uint64_t MaskR : 1; /* 112 */
uint64_t MaskG : 1; /* 113 */
uint64_t MaskB : 1; /* 114 */
uint64_t MaskA : 1; /* 115 */
uint64_t reserved14 : 12; /* 127..116 */
} BlendingSlotStruct;
typedef struct {
uint64_t AlphaFillMode : 3; /* 2..0 */
uint64_t AlphaFillSlot : 3; /* 5..3 */
uint64_t reserved0 : 2; /* 6..5 */
uint64_t BackgroundAlpha : 8; /* 15..7 */
uint64_t BackgroundR : 10; /* 25..16 */
uint64_t BackgroundG : 10; /* 35..26 */
uint64_t BackgroundB : 10; /* 45..36 */
uint64_t RegammaMode : 2; /* 47..46 */
uint64_t OutputFlipX : 1; /* 48 */
uint64_t OutputFlipY : 1; /* 49 */
uint64_t OutputTranspose : 1; /* 50 */
uint64_t reserved1 : 1; /* 51 */
uint64_t reserved2 : 12; /* 63..52 */
uint64_t TargetRectLeft : 14; /* 77..64 */
uint64_t reserved3 : 2; /* 79..78 */
uint64_t TargetRectRight : 14; /* 93..80 */
uint64_t reserved4 : 2; /* 95..94 */
uint64_t TargetRectTop : 14; /* 109..96 */
uint64_t reserved5 : 2; /* 111..110 */
uint64_t TargetRectBottom : 14; /* 125..112 */
uint64_t reserved6 : 2; /* 127..126 */
} OutputConfig;
typedef struct {
uint64_t OutPixelFormat : 7; /* 6..0 */
uint64_t OutChromaLocHoriz : 2; /* 8..7 */
uint64_t OutChromaLocVert : 2; /* 10..9 */
uint64_t OutBlkKind : 4; /* 14..11 */
uint64_t OutBlkHeight : 4; /* 18..15 */
uint64_t reserved0 : 3; /* 21..19 */
uint64_t reserved1 : 10; /* 31..22 */
uint64_t OutSurfaceWidth : 14; /* 45..32 */
uint64_t OutSurfaceHeight : 14; /* 59..46 */
uint64_t reserved2 : 4; /* 63..60 */
uint64_t OutLumaWidth : 14; /* 77..64 */
uint64_t OutLumaHeight : 14; /* 91..78 */
uint64_t reserved3 : 4; /* 95..92 */
uint64_t OutChromaWidth : 14; /* 109..96 */
uint64_t OutChromaHeight : 14; /* 123..110 */
uint64_t reserved4 : 4; /* 127..124 */
} OutputSurfaceConfig;
typedef struct {
uint64_t f00 : 10; /* 9..0 */
uint64_t f10 : 10; /* 19..10 */
uint64_t f20 : 10; /* 29..20 */
uint64_t reserved0 : 2; /* 31..30 */
uint64_t f01 : 10; /* 41..32 */
uint64_t f11 : 10; /* 51..42 */
uint64_t f21 : 10; /* 61..52 */
uint64_t reserved1 : 2; /* 63..62 */
uint64_t f02 : 10; /* 73..64 */
uint64_t f12 : 10; /* 83..74 */
uint64_t f22 : 10; /* 93..84 */
uint64_t reserved2 : 2; /* 95..94 */
uint64_t f03 : 10; /* 105..96 */
uint64_t f13 : 10; /* 115..106 */
uint64_t f23 : 10; /* 125..116 */
uint64_t reserved3 : 2; /* 127..126 */
} FilterCoeffStruct;
typedef struct {
uint64_t DownsampleHoriz : 11; /* 10..0 */
uint64_t reserved0 : 5; /* 15..11 */
uint64_t DownsampleVert : 11; /* 26..16 */
uint64_t reserved1 : 5; /* 31..27 */
uint64_t reserved2 : 32; /* 63..32 */
uint64_t reserved3 : 32; /* 95..64 */
uint64_t reserved4 : 32; /* 127..96 */
} PipeConfig;
typedef struct {
uint64_t OldCadence : 32; /* 31..0 */
uint64_t OldDiff : 32; /* 63..32 */
uint64_t OldWeave : 32; /* 95..64 */
uint64_t OlderWeave : 32; /* 127..96 */
} SlotHistoryBuffer;
typedef struct {
uint64_t crc0 : 32; /* 31..0 */
uint64_t crc1 : 32; /* 63..32 */
uint64_t crc2 : 32; /* 95..64 */
uint64_t crc3 : 32; /* 127..96 */
} PartitionCrcStruct;
typedef struct {
uint64_t crc0 : 32; /* 31..0 */
uint64_t crc1 : 32; /* 63..32 */
} SlotCrcStruct;
typedef struct {
uint64_t ErrorStatus : 32; /* 31..0 */
uint64_t CycleCount : 32; /* 63..32 */
uint64_t reserved0 : 32; /* 95..64 */
uint64_t reserved1 : 32; /* 127..96 */
} StatusStruct;
typedef struct {
SlotConfig slotConfig;
SlotSurfaceConfig slotSurfaceConfig;
LumaKeyStruct lumaKeyStruct;
MatrixStruct colorMatrixStruct;
MatrixStruct gamutMatrixStruct;
BlendingSlotStruct blendingSlotStruct;
} SlotStruct;
typedef struct {
FilterCoeffStruct filterCoeffStruct[520];
} FilterStruct;
typedef struct {
PipeConfig pipeConfig;
OutputConfig outputConfig;
OutputSurfaceConfig outputSurfaceConfig;
MatrixStruct outColorMatrixStruct;
ClearRectStruct clearRectStruct[4];
SlotStruct slotStruct[16];
} ConfigStruct;
typedef struct {
PartitionCrcStruct partitionCrcStruct[4];
} InterfaceCrcStruct;
typedef struct {
SlotCrcStruct slotCrcStruct[16];
} InputCrcStruct;
#endif

342
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/*
* Copyright © 2018 NVIDIA Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <errno.h>
#include <string.h>
#include "private.h"
#include "tegra.h"
#include "vic.h"
#include "vic42.h"
struct vic42 {
struct vic base;
struct {
struct drm_tegra_mapping *map;
struct drm_tegra_bo *bo;
} config;
struct {
struct drm_tegra_mapping *map;
struct drm_tegra_bo *bo;
} filter;
};
static int vic42_fill(struct vic *v, struct vic_image *output,
unsigned int left, unsigned int top,
unsigned int right, unsigned int bottom,
unsigned int alpha, unsigned int red,
unsigned int green, unsigned int blue)
{
struct vic42 *vic = container_of(v, struct vic42, base);
ConfigStruct *c;
int err;
err = drm_tegra_bo_map(vic->config.bo, (void **)&c);
if (err < 0) {
fprintf(stderr, "failed to map configuration structure: %s\n",
strerror(-err));
return err;
}
memset(c, 0, sizeof(*c));
c->outputConfig.TargetRectTop = top;
c->outputConfig.TargetRectLeft = left;
c->outputConfig.TargetRectRight = right;
c->outputConfig.TargetRectBottom = bottom;
c->outputConfig.BackgroundAlpha = alpha;
c->outputConfig.BackgroundR = red;
c->outputConfig.BackgroundG = green;
c->outputConfig.BackgroundB = blue;
c->outputSurfaceConfig.OutPixelFormat = output->format;
c->outputSurfaceConfig.OutBlkKind = output->kind;
c->outputSurfaceConfig.OutBlkHeight = 0;
c->outputSurfaceConfig.OutSurfaceWidth = output->width - 1;
c->outputSurfaceConfig.OutSurfaceHeight = output->height - 1;
c->outputSurfaceConfig.OutLumaWidth = output->stride - 1;
c->outputSurfaceConfig.OutLumaHeight = output->height - 1;
c->outputSurfaceConfig.OutChromaWidth = 16383;
c->outputSurfaceConfig.OutChromaHeight = 16383;
drm_tegra_bo_unmap(vic->config.bo);
return 0;
}
static int vic42_blit(struct vic *v, struct vic_image *output,
struct vic_image *input)
{
struct vic42 *vic = container_of(v, struct vic42, base);
SlotSurfaceConfig *surface;
SlotConfig *slot;
ConfigStruct *c;
int err;
err = drm_tegra_bo_map(vic->config.bo, (void **)&c);
if (err < 0) {
fprintf(stderr, "failed to map configuration structure: %s\n",
strerror(-err));
return err;
}
memset(c, 0, sizeof(*c));
c->outputConfig.TargetRectTop = 0;
c->outputConfig.TargetRectLeft = 0;
c->outputConfig.TargetRectRight = output->width - 1;
c->outputConfig.TargetRectBottom = output->height - 1;
c->outputConfig.BackgroundAlpha = 255;
c->outputConfig.BackgroundR = 1023;
c->outputConfig.BackgroundG = 1023;
c->outputConfig.BackgroundB = 1023;
c->outputSurfaceConfig.OutPixelFormat = output->format;
c->outputSurfaceConfig.OutBlkKind = output->kind;
c->outputSurfaceConfig.OutBlkHeight = 0;
c->outputSurfaceConfig.OutSurfaceWidth = output->width - 1;
c->outputSurfaceConfig.OutSurfaceHeight = output->height - 1;
c->outputSurfaceConfig.OutLumaWidth = output->stride - 1;
c->outputSurfaceConfig.OutLumaHeight = output->height - 1;
c->outputSurfaceConfig.OutChromaWidth = 16383;
c->outputSurfaceConfig.OutChromaHeight = 16383;
slot = &c->slotStruct[0].slotConfig;
slot->SlotEnable = 1;
slot->CurrentFieldEnable = 1;
slot->PlanarAlpha = 255;
slot->ConstantAlpha = 1;
slot->SourceRectLeft = 0 << 16;
slot->SourceRectRight = (input->width - 1) << 16;
slot->SourceRectTop = 0 << 16;
slot->SourceRectBottom = (input->height - 1) << 16;
slot->DestRectLeft = 0;
slot->DestRectRight = output->width - 1;
slot->DestRectTop = 0;
slot->DestRectBottom = output->height - 1;
slot->SoftClampHigh = 1023;
surface = &c->slotStruct[0].slotSurfaceConfig;
surface->SlotPixelFormat = input->format;
surface->SlotBlkKind = input->kind;
surface->SlotBlkHeight = 0; /* XXX */
surface->SlotCacheWidth = VIC_CACHE_WIDTH_64Bx4; /* XXX */
surface->SlotSurfaceWidth = input->width - 1;
surface->SlotSurfaceHeight = input->height - 1;
surface->SlotLumaWidth = input->stride - 1;
surface->SlotLumaHeight = input->height - 1;
surface->SlotChromaWidth = 16383;
surface->SlotChromaHeight = 16383;
drm_tegra_bo_unmap(vic->config.bo);
return 0;
}
static int vic42_flip(struct vic *v, struct vic_image *output,
struct vic_image *input)
{
struct vic42 *vic = container_of(v, struct vic42, base);
SlotSurfaceConfig *surface;
SlotConfig *slot;
ConfigStruct *c;
int err;
err = drm_tegra_bo_map(vic->config.bo, (void **)&c);
if (err < 0) {
fprintf(stderr, "failed to map configuration structure: %s\n",
strerror(-err));
return err;
}
memset(c, 0, sizeof(*c));
c->outputConfig.TargetRectTop = 0;
c->outputConfig.TargetRectLeft = 0;
c->outputConfig.TargetRectRight = output->width - 1;
c->outputConfig.TargetRectBottom = output->height - 1;
c->outputConfig.BackgroundAlpha = 255;
c->outputConfig.BackgroundR = 1023;
c->outputConfig.BackgroundG = 1023;
c->outputConfig.BackgroundB = 1023;
c->outputConfig.OutputFlipY = 1;
c->outputSurfaceConfig.OutPixelFormat = output->format;
c->outputSurfaceConfig.OutBlkKind = output->kind;
c->outputSurfaceConfig.OutBlkHeight = 0;
c->outputSurfaceConfig.OutSurfaceWidth = output->width - 1;
c->outputSurfaceConfig.OutSurfaceHeight = output->height - 1;
c->outputSurfaceConfig.OutLumaWidth = output->stride - 1;
c->outputSurfaceConfig.OutLumaHeight = output->height - 1;
c->outputSurfaceConfig.OutChromaWidth = 16383;
c->outputSurfaceConfig.OutChromaHeight = 16383;
slot = &c->slotStruct[0].slotConfig;
slot->SlotEnable = 1;
slot->CurrentFieldEnable = 1;
slot->PlanarAlpha = 255;
slot->ConstantAlpha = 1;
slot->SourceRectLeft = 0 << 16;
slot->SourceRectRight = (input->width - 1) << 16;
slot->SourceRectTop = 0 << 16;
slot->SourceRectBottom = (input->height - 1) << 16;
slot->DestRectLeft = 0;
slot->DestRectRight = output->width - 1;
slot->DestRectTop = 0;
slot->DestRectBottom = output->height - 1;
slot->SoftClampHigh = 1023;
surface = &c->slotStruct[0].slotSurfaceConfig;
surface->SlotPixelFormat = input->format;
surface->SlotBlkKind = input->kind;
surface->SlotBlkHeight = 0; /* XXX */
surface->SlotCacheWidth = VIC_CACHE_WIDTH_64Bx4; /* XXX */
surface->SlotSurfaceWidth = input->width - 1;
surface->SlotSurfaceHeight = input->height - 1;
surface->SlotLumaWidth = input->stride - 1;
surface->SlotLumaHeight = input->height - 1;
surface->SlotChromaWidth = 16383;
surface->SlotChromaHeight = 16383;
drm_tegra_bo_unmap(vic->config.bo);
return 0;
}
static int vic42_execute(struct vic *v, struct drm_tegra_pushbuf *pushbuf,
uint32_t **ptrp, struct vic_image *output,
struct vic_image **inputs, unsigned int num_inputs)
{
struct vic42 *vic = container_of(v, struct vic42, base);
unsigned int i;
if (num_inputs > 1)
return -EINVAL;
VIC_PUSH_METHOD(pushbuf, ptrp, NVC5B6_VIDEO_COMPOSITOR_SET_APPLICATION_ID, 1);
VIC_PUSH_METHOD(pushbuf, ptrp, NVC5B6_VIDEO_COMPOSITOR_SET_CONTROL_PARAMS, (sizeof(ConfigStruct) / 16) << 16);
VIC_PUSH_BUFFER(pushbuf, ptrp, NVC5B6_VIDEO_COMPOSITOR_SET_CONFIG_STRUCT_OFFSET, vic->config.map, 0, 0);
VIC_PUSH_BUFFER(pushbuf, ptrp, NVC5B6_VIDEO_COMPOSITOR_SET_FILTER_STRUCT_OFFSET, vic->filter.map, 0, 0);
VIC_PUSH_BUFFER(pushbuf, ptrp, NVC5B6_VIDEO_COMPOSITOR_SET_OUTPUT_SURFACE_LUMA_OFFSET, output->map, 0, 0);
for (i = 0; i < num_inputs; i++) {
uint32_t method = NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE0_LUMA_OFFSET(0) + (i * 3) * 4;
VIC_PUSH_BUFFER(pushbuf, ptrp, method, inputs[i]->map, 0, 0);
}
VIC_PUSH_METHOD(pushbuf, ptrp, NVC5B6_VIDEO_COMPOSITOR_EXECUTE, 1 << 8);
return 0;
}
static void vic42_free(struct vic *v)
{
struct vic42 *vic = container_of(v, struct vic42, base);
drm_tegra_channel_unmap(vic->filter.map);
drm_tegra_bo_unref(vic->filter.bo);
drm_tegra_channel_unmap(vic->config.map);
drm_tegra_bo_unref(vic->config.bo);
drm_tegra_syncpoint_free(v->syncpt);
free(vic);
}
static const struct vic_ops vic42_ops = {
.fill = vic42_fill,
.blit = vic42_blit,
.flip = vic42_flip,
.execute = vic42_execute,
.free = vic42_free,
};
int vic42_new(struct drm_tegra *drm, struct drm_tegra_channel *channel,
struct vic **vicp)
{
struct vic42 *vic;
void *ptr;
int err;
vic = calloc(1, sizeof(*vic));
if (!vic)
return -ENOMEM;
vic->base.drm = drm;
vic->base.channel = channel;
vic->base.ops = &vic42_ops;
vic->base.version = 0x19;
err = drm_tegra_syncpoint_new(drm, &vic->base.syncpt);
if (err < 0) {
fprintf(stderr, "failed to allocate syncpoint: %s\n", strerror(-err));
return err;
}
err = drm_tegra_bo_new(drm, 0, 16384, &vic->config.bo);
if (err < 0) {
fprintf(stderr, "failed to allocate configuration structurer: %s\n",
strerror(-err));
return err;
}
err = drm_tegra_channel_map(channel, vic->config.bo, DRM_TEGRA_CHANNEL_MAP_READ,
&vic->config.map);
if (err < 0) {
fprintf(stderr, "failed to map configuration structure: %s\n",
strerror(-err));
return err;
}
err = drm_tegra_bo_new(drm, 0, 16384, &vic->filter.bo);
if (err < 0) {
fprintf(stderr, "failed to allocate filter buffer: %s\n",
strerror(-err));
return err;
}
err = drm_tegra_bo_map(vic->filter.bo, &ptr);
if (err < 0) {
fprintf(stderr, "failed to map filter buffer: %s\n", strerror(-err));
return err;
}
memset(ptr, 0, 16384);
drm_tegra_bo_unmap(vic->filter.bo);
err = drm_tegra_channel_map(channel, vic->filter.bo, DRM_TEGRA_CHANNEL_MAP_READ,
&vic->filter.map);
if (err < 0) {
fprintf(stderr, "failed to map filter buffer: %s\n",
strerror(-err));
return err;
}
if (vicp)
*vicp = &vic->base;
return 0;
}

597
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@ -0,0 +1,597 @@
/*
* Copyright © 2018 NVIDIA Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef VIC42_H
#define VIC42_H
#include <stdint.h>
#define NVC5B6_VIDEO_COMPOSITOR_SET_APPLICATION_ID 0x00000200
#define NVC5B6_VIDEO_COMPOSITOR_EXECUTE 0x00000300
#define NVC5B6_VIDEO_COMPOSITOR_SET_CONTROL_PARAMS 0x00000704
#define NVC5B6_VIDEO_COMPOSITOR_SET_CONFIG_STRUCT_OFFSET 0x00000708
#define NVC5B6_VIDEO_COMPOSITOR_SET_FILTER_STRUCT_OFFSET 0x0000070c
#define NVC5B6_VIDEO_COMPOSITOR_SET_HIST_OFFSET 0x00000714
#define NVC5B6_VIDEO_COMPOSITOR_SET_OUTPUT_SURFACE_LUMA_OFFSET 0x00000720
#define NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE0_LUMA_OFFSET(slot) (0x00001200 + (slot) * 0x00000060)
#define NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE0_CHROMA_U_OFFSET(slot) (0x00001204 + (slot) * 0x00000060)
#define NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE0_CHROMA_V_OFFSET(slot) (0x00001208 + (slot) * 0x00000060)
#define NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE1_LUMA_OFFSET(slot) (0x0000120c + (slot) * 0x00000060)
#define NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE1_CHROMA_U_OFFSET(slot) (0x00001210 + (slot) * 0x00000060)
#define NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE1_CHROMA_V_OFFSET(slot) (0x00001214 + (slot) * 0x00000060)
#define NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE2_LUMA_OFFSET(slot) (0x00001218 + (slot) * 0x00000060)
#define NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE2_CHROMA_U_OFFSET(slot) (0x0000121c + (slot) * 0x00000060)
#define NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE2_CHROMA_V_OFFSET(slot) (0x00001220 + (slot) * 0x00000060)
#define NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE3_LUMA_OFFSET(slot) (0x00001224 + (slot) * 0x00000060)
#define NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE3_CHROMA_U_OFFSET(slot) (0x00001228 + (slot) * 0x00000060)
#define NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE3_CHROMA_V_OFFSET(slot) (0x0000122c + (slot) * 0x00000060)
#define NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE4_LUMA_OFFSET(slot) (0x00001230 + (slot) * 0x00000060)
#define NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE4_CHROMA_U_OFFSET(slot) (0x00001234 + (slot) * 0x00000060)
#define NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE4_CHROMA_V_OFFSET(slot) (0x00001238 + (slot) * 0x00000060)
#define NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE5_LUMA_OFFSET(slot) (0x0000123c + (slot) * 0x00000060)
#define NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE5_CHROMA_U_OFFSET(slot) (0x00001240 + (slot) * 0x00000060)
#define NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE5_CHROMA_V_OFFSET(slot) (0x00001244 + (slot) * 0x00000060)
#define NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE6_LUMA_OFFSET(slot) (0x00001248 + (slot) * 0x00000060)
#define NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE6_CHROMA_U_OFFSET(slot) (0x0000124c + (slot) * 0x00000060)
#define NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE6_CHROMA_V_OFFSET(slot) (0x00001250 + (slot) * 0x00000060)
#define NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE7_LUMA_OFFSET(slot) (0x00001254 + (slot) * 0x00000060)
#define NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE7_CHROMA_U_OFFSET(slot) (0x00001258 + (slot) * 0x00000060)
#define NVC5B6_VIDEO_COMPOSITOR_SET_SURFACE7_CHROMA_V_OFFSET(slot) (0x0000125c + (slot) * 0x00000060)
typedef struct {
uint64_t SlotEnable : 1; /* 0 */
uint64_t DeNoise : 1; /* 1 */
uint64_t AdvancedDenoise : 1; /* 2 */
uint64_t CadenceDetect : 1; /* 3 */
uint64_t MotionMap : 1; /* 4 */
uint64_t MMapCombine : 1; /* 5 */
uint64_t IsEven : 1; /* 6 */
uint64_t ChromaEven : 1; /* 7 */
uint64_t CurrentFieldEnable : 1; /* 8 */
uint64_t PrevFieldEnable : 1; /* 9 */
uint64_t NextFieldEnable : 1; /* 10 */
uint64_t NextNrFieldEnable : 1; /* 11 */
uint64_t CurMotionFieldEnable : 1; /* 12 */
uint64_t PrevMotionFieldEnable : 1; /* 13 */
uint64_t PpMotionFieldEnable : 1; /* 14 */
uint64_t CombMotionFieldEnable : 1; /* 15 */
uint64_t FrameFormat : 4; /* 19..16 */
uint64_t FilterLengthY : 2; /* 21..20 */
uint64_t FilterLengthX : 2; /* 23..22 */
uint64_t Panoramic : 12; /* 35..24 */
uint64_t ChromaUpLengthY : 2; /* 37..36 */
uint64_t ChromaUpLengthX : 2; /* 39..38 */
uint64_t reserved1 : 18; /* 57..40 */
uint64_t DetailFltClamp : 6; /* 63..58 */
uint64_t FilterNoise : 10; /* 73..64 */
uint64_t FilterDetail : 10; /* 83..74 */
uint64_t ChromaNoise : 10; /* 93..84 */
uint64_t ChromaDetail : 10; /* 103..94 */
uint64_t DeinterlaceMode : 4; /* 107..104 */
uint64_t MotionAccumWeight : 3; /* 110..108 */
uint64_t NoiseIir : 11; /* 121..111 */
uint64_t LightLevel : 4; /* 125..122 */
uint64_t reserved4 : 2; /* 127..126 */
/* 128 */
uint64_t SoftClampLow : 10; /* 9..0 */
uint64_t SoftClampHigh : 10; /* 19..10 */
uint64_t reserved5 : 12; /* 31..20 */
uint64_t reserved6 : 2; /* 33..32 */
uint64_t PlanarAlpha : 8; /* 41..34 */
uint64_t ConstantAlpha : 1; /* 42 */
uint64_t StereoInterleave : 3; /* 45..43 */
uint64_t ClipEnabled : 1; /* 46 */
uint64_t ClearRectMask : 8; /* 54..47 */
uint64_t DegammaMode : 2; /* 56..55 */
uint64_t reserved7 : 1; /* 57 */
uint64_t DecompressEnable : 1; /* 58 */
uint64_t DecompressKind : 4; /* 62..59 */
uint64_t reserved9 : 1; /* 63 */
uint64_t DecompressCtbCount : 8; /* 71..64 */
uint64_t DecompressZbcColor : 32; /* 103..72 */
uint64_t reserved12 : 24; /* 127..104 */
/* 256 */
uint64_t SourceRectLeft : 30; /* 29..0 */
uint64_t reserved14 : 2; /* 31..30 */
uint64_t SourceRectRight : 30; /* 61..32 */
uint64_t reserved15 : 2; /* 63..62 */
uint64_t SourceRectTop : 30; /* 93..64 */
uint64_t reserved16 : 2; /* 95..94 */
uint64_t SourceRectBottom : 30; /* 125..96 */
uint64_t reserved17 : 2; /* 127..126 */
/* 384 */
uint64_t DestRectLeft : 14; /* 13..0 */
uint64_t reserved18 : 2; /* 15..14 */
uint64_t DestRectRight : 14; /* 29..16 */
uint64_t reserved19 : 2; /* 31..30 */
uint64_t DestRectTop : 14; /* 45..32 */
uint64_t reserved20 : 2; /* 47..46 */
uint64_t DestRectBottom : 14; /* 61..48 */
uint64_t reserved21 : 2; /* 63..62 */
uint64_t B16ScalerEnable : 1; /* 64 */
uint64_t reserved22 : 31; /* 95..65 */
uint64_t reserved23 : 32; /* 127..96 */
} SlotConfig;
typedef struct {
uint64_t SlotPixelFormat : 7; /* 6..0 */
uint64_t SlotChromaLocHORIZ : 2; /* 8..7 */
uint64_t SlotChromaLocVert : 2; /* 10..9 */
uint64_t SlotBlkKind : 4; /* 14..11 */
uint64_t SlotBlkHeight : 4; /* 18..15 */
uint64_t SlotCacheWidth : 3; /* 21..19 */
uint64_t reserved0 : 10; /* 31..22 */
uint64_t SlotSurfaceWidth : 14; /* 45..32 */
uint64_t SlotSurfaceHeight : 14; /* 59..46 */
uint64_t reserved1 : 4; /* 63..60 */
uint64_t SlotLumaWidth : 14; /* 77..64 */
uint64_t SlotLumaHeight : 14; /* 91..78 */
uint64_t reserved2 : 4; /* 95..92 */
uint64_t SlotChromaWidth : 14; /* 109..96 */
uint64_t SlotChromaHeight : 14; /* 123..110 */
uint64_t reserved3 : 4; /* 127..124 */
} SlotSurfaceConfig;
typedef struct {
uint64_t luma_coeff0 : 20; /* 19..0 */
uint64_t luma_coeff1 : 20; /* 39..20 */
uint64_t luma_coeff2 : 20; /* 59..40 */
uint64_t luma_r_shift : 4; /* 63..60 */
uint64_t luma_coeff3 : 20; /* 83..64 */
uint64_t LumaKeyLower : 10; /* 93..84 */
uint64_t LumaKeyUpper : 10; /* 103..94 */
uint64_t LumaKeyEnabled : 1; /* 104 */
uint64_t reserved0 : 2; /* 106..105 */
uint64_t reserved1 : 21; /* 127..107 */
} LumaKeyStruct;
typedef struct {
uint64_t matrix_coeff00 : 20; /* 19..0 */
uint64_t matrix_coeff10 : 20; /* 39..20 */
uint64_t matrix_coeff20 : 20; /* 59..40 */
uint64_t matrix_r_shift : 4; /* 63..60 */
uint64_t matrix_coeff01 : 20; /* 83..64 */
uint64_t matrix_coeff11 : 20; /* 103..84 */
uint64_t matrix_coeff21 : 20; /* 123..104 */
uint64_t reserved0 : 3; /* 126..124 */
uint64_t matrix_enable : 1; /* 127 */
/* 128 */
uint64_t matrix_coeff02 : 20; /* 19..0 */
uint64_t matrix_coeff12 : 20; /* 39..20 */
uint64_t matrix_coeff22 : 20; /* 59..40 */
uint64_t reserved1 : 4; /* 63..60 */
uint64_t matrix_coeff03 : 20; /* 83..64 */
uint64_t matrix_coeff13 : 20; /* 103..84 */
uint64_t matrix_coeff23 : 20; /* 123..104 */
uint64_t reserved2 : 4; /* 127..124 */
} MatrixStruct;
typedef struct {
uint64_t ClearRect0Left : 14; /* 13..0 */
uint64_t reserved0 : 2; /* 15..14 */
uint64_t ClearRect0Right : 14; /* 29..16 */
uint64_t reserved1 : 2; /* 31..30 */
uint64_t ClearRect0Top : 14; /* 45..32 */
uint64_t reserved2 : 2; /* 47..46 */
uint64_t ClearRect0Bottom : 14; /* 61..48 */
uint64_t reserved3 : 2; /* 63..62 */
uint64_t ClearRect1Left : 14; /* 77..64 */
uint64_t reserved4 : 2; /* 79..78 */
uint64_t ClearRect1Right : 14; /* 93..80 */
uint64_t reserved5 : 2; /* 95..94 */
uint64_t ClearRect1Top : 14; /* 109..96 */
uint64_t reserved6 : 2; /* 111..110 */
uint64_t ClearRect1Bottom : 14; /* 125..112 */
uint64_t reserved7 : 2; /* 127..126 */
} ClearRectStruct;
typedef struct {
uint64_t reserved0 : 2; /* 1..0 */
uint64_t AlphaK1 : 8; /* 9..2 */
uint64_t reserved1 : 6; /* 17..10 */
uint64_t AlphaK2 : 8; /* 25..18 */
uint64_t reserved2 : 6; /* 31..26 */
uint64_t SrcFactCMatchSelect : 3; /* 34..32 */
uint64_t reserved3 : 1; /* 35 */
uint64_t DstFactCMatchSelect : 3; /* 38..36 */
uint64_t reserved4 : 1; /* 39 */
uint64_t SrcFactAMatchSelect : 3; /* 42..40 */
uint64_t reserved5 : 1; /* 43 */
uint64_t DstFactAMatchSelect : 3; /* 46..44 */
uint64_t reserved6 : 1; /* 47 */
uint64_t reserved7 : 4; /* 51..48 */
uint64_t reserved8 : 4; /* 55..52 */
uint64_t reserved9 : 4; /* 59..56 */
uint64_t reserved10 : 4; /* 63..60 */
uint64_t reserved11 : 2; /* 65..64 */
uint64_t OverrideR : 10; /* 75..66 */
uint64_t OverrideG : 10; /* 85..76 */
uint64_t OverrideB : 10; /* 95..86 */
uint64_t reserved12 : 2; /* 97..96 */
uint64_t OverrideA : 8; /* 105..98 */
uint64_t reserved13 : 2; /* 107..106 */
uint64_t UseOverrideR : 1; /* 108 */
uint64_t UseOverrideG : 1; /* 109 */
uint64_t UseOverrideB : 1; /* 110 */
uint64_t UseOverrideA : 1; /* 111 */
uint64_t MaskR : 1; /* 112 */
uint64_t MaskG : 1; /* 113 */
uint64_t MaskB : 1; /* 114 */
uint64_t MaskA : 1; /* 115 */
uint64_t reserved14 : 12; /* 127..116 */
} BlendingSlotStruct;
typedef struct {
uint64_t AlphaFillMode : 3; /* 2..0 */
uint64_t AlphaFillSlot : 3; /* 5..3 */
uint64_t reserved0 : 2; /* 6..5 */
uint64_t BackgroundAlpha : 8; /* 15..7 */
uint64_t BackgroundR : 10; /* 25..16 */
uint64_t BackgroundG : 10; /* 35..26 */
uint64_t BackgroundB : 10; /* 45..36 */
uint64_t RegammaMode : 2; /* 47..46 */
uint64_t OutputFlipX : 1; /* 48 */
uint64_t OutputFlipY : 1; /* 49 */
uint64_t OutputTranspose : 1; /* 50 */
uint64_t reserved1 : 1; /* 51 */
uint64_t reserved2 : 12; /* 63..52 */
uint64_t TargetRectLeft : 14; /* 77..64 */
uint64_t reserved3 : 2; /* 79..78 */
uint64_t TargetRectRight : 14; /* 93..80 */
uint64_t reserved4 : 2; /* 95..94 */
uint64_t TargetRectTop : 14; /* 109..96 */
uint64_t reserved5 : 2; /* 111..110 */
uint64_t TargetRectBottom : 14; /* 125..112 */
uint64_t reserved6 : 2; /* 127..126 */
} OutputConfig;
typedef struct {
uint64_t OutPixelFormat : 7; /* 6..0 */
uint64_t OutChromaLocHoriz : 2; /* 8..7 */
uint64_t OutChromaLocVert : 2; /* 10..9 */
uint64_t OutBlkKind : 4; /* 14..11 */
uint64_t OutBlkHeight : 4; /* 18..15 */
uint64_t reserved0 : 3; /* 21..19 */
uint64_t reserved1 : 10; /* 31..22 */
uint64_t OutSurfaceWidth : 14; /* 45..32 */
uint64_t OutSurfaceHeight : 14; /* 59..46 */
uint64_t reserved2 : 4; /* 63..60 */
uint64_t OutLumaWidth : 14; /* 77..64 */
uint64_t OutLumaHeight : 14; /* 91..78 */
uint64_t reserved3 : 4; /* 95..92 */
uint64_t OutChromaWidth : 14; /* 109..96 */
uint64_t OutChromaHeight : 14; /* 123..110 */
uint64_t reserved4 : 4; /* 127..124 */
} OutputSurfaceConfig;
typedef struct {
uint64_t f00 : 10; /* 9..0 */
uint64_t f10 : 10; /* 19..10 */
uint64_t f20 : 10; /* 29..20 */
uint64_t reserved0 : 2; /* 31..30 */
uint64_t f01 : 10; /* 41..32 */
uint64_t f11 : 10; /* 51..42 */
uint64_t f21 : 10; /* 61..52 */
uint64_t reserved1 : 2; /* 63..62 */
uint64_t f02 : 10; /* 73..64 */
uint64_t f12 : 10; /* 83..74 */
uint64_t f22 : 10; /* 93..84 */
uint64_t reserved2 : 2; /* 95..94 */
uint64_t f03 : 10; /* 105..96 */
uint64_t f13 : 10; /* 115..106 */
uint64_t f23 : 10; /* 125..116 */
uint64_t reserved3 : 2; /* 127..126 */
} FilterCoeffStruct;
typedef struct {
uint64_t DownsampleHoriz : 11; /* 10..0 */
uint64_t reserved0 : 5; /* 15..11 */
uint64_t DownsampleVert : 11; /* 26..16 */
uint64_t reserved1 : 5; /* 31..27 */
uint64_t reserved2 : 32; /* 63..32 */
uint64_t reserved3 : 32; /* 95..64 */
uint64_t reserved4 : 32; /* 127..96 */
} PipeConfig;
typedef struct {
uint64_t OldCadence : 32; /* 31..0 */
uint64_t OldDiff : 32; /* 63..32 */
uint64_t OldWeave : 32; /* 95..64 */
uint64_t OlderWeave : 32; /* 127..96 */
} SlotHistoryBuffer;
typedef struct {
uint64_t crc0 : 32; /* 31..0 */
uint64_t crc1 : 32; /* 63..32 */
uint64_t crc2 : 32; /* 95..64 */
uint64_t crc3 : 32; /* 127..96 */
} PartitionCrcStruct;
typedef struct {
uint64_t crc0 : 32; /* 31..0 */
uint64_t crc1 : 32; /* 63..32 */
} SlotCrcStruct;
typedef struct {
uint64_t ErrorStatus : 32; /* 31..0 */
uint64_t CycleCount : 32; /* 63..32 */
uint64_t reserved0 : 32; /* 95..64 */
uint64_t reserved1 : 32; /* 127..96 */
} StatusStruct;
typedef struct {
uint64_t coeff_0 : 10; /* 9..0 */
uint64_t reserved0 : 6; /* 15..10 */
uint64_t coeff_1 : 10; /* 25..16 */
uint64_t reserved1 : 6; /* 31..26 */
uint64_t coeff_2 : 10; /* 41..32 */
uint64_t reserved2 : 6; /* 47..42 */
uint64_t coeff_3 : 10; /* 57..48 */
uint64_t reserved3 : 6; /* 63..58 */
} CoeffPhaseParamStruct;
typedef struct {
uint64_t GeoTranEn : 1; /* 0 */
uint64_t GeoTranMode : 2; /* 2..1 */
uint64_t IPTMode : 1; /* 3 */
uint64_t PixelFilterType : 2; /* 5..4 */
uint64_t PixelFormat : 7; /* 12..6 */
uint64_t CacheWidth : 3; /* 15..13 */
uint64_t SrcBlkKind : 4; /* 19..16 */
uint64_t SrcBlkHeight : 4; /* 23..20 */
uint64_t DestBlkKind : 4; /* 27..24 */
uint64_t DestBlkHeight : 4; /* 31..28 */
uint64_t MskBitMapEn : 1; /* 32 */
uint64_t MaskedPixelFillMode : 1; /* 33 */
uint64_t XSobelMode : 2; /* 35..34 */
uint64_t SubFrameEn : 1; /* 36 */
uint64_t reserved0 : 3; /* 39..37 */
uint64_t XSobelBlkKind : 4; /* 43..40 */
uint64_t XSobelBlkHeight : 4; /* 47..44 */
uint64_t XSobelDSBlkKind : 4; /* 51..48 */
uint64_t XSobelDSBlkHeight : 4; /* 55..52 */
uint64_t reserved1 : 8; /* 63..56 */
uint64_t NonFixedPatchEn : 1; /* 64 */
uint64_t HorRegionNum : 2; /* 66..65 */
uint64_t VerRegionNum : 2; /* 68..67 */
uint64_t reserved2 : 3; /* 71..69 */
uint64_t log2HorSpace_0 : 3; /* 74..72 */
uint64_t log2VerSpace_0 : 3; /* 77..75 */
uint64_t log2HorSpace_1 : 3; /* 80..78 */
uint64_t log2VerSpace_1 : 3; /* 83..81 */
uint64_t log2HorSpace_2 : 3; /* 86..84 */
uint64_t log2VerSpace_2 : 3; /* 89..87 */
uint64_t log2HorSpace_3 : 3; /* 92..90 */
uint64_t log2VerSpace_3 : 3; /* 95..93 */
uint64_t horRegionWidth_0 : 14; /* 109..96 */
uint64_t reserved3 : 2; /* 111..110 */
uint64_t horRegionWidth_1 : 14; /* 125..112 */
uint64_t reserved4 : 2; /* 127..126 */
uint64_t horRegionWidth_2 : 14; /* 141..128 */
uint64_t reserved5 : 2; /* 143..142 */
uint64_t horRegionWidth_3 : 14; /* 157..144 */
uint64_t reserved6 : 2; /* 159..158 */
uint64_t verRegionHeight_0 : 14; /* 173..160 */
uint64_t reserved7 : 2; /* 175..174 */
uint64_t verRegionHeight_1 : 14; /* 189..176 */
uint64_t reserved8 : 2; /* 191..190 */
uint64_t verRegionHeight_2 : 14; /* 205..192 */
uint64_t reserved9 : 2; /* 207..206 */
uint64_t verRegionHeight_3 : 14; /* 221..208 */
uint64_t reserved10 : 2; /* 223..222 */
uint64_t IPT_M11 : 32; /* 255..224 */
uint64_t IPT_M12 : 32; /* 287..256 */
uint64_t IPT_M13 : 32; /* 319..288 */
uint64_t IPT_M21 : 32; /* 351..320 */
uint64_t IPT_M22 : 32; /* 383..352 */
uint64_t IPT_M23 : 32; /* 415..384 */
uint64_t IPT_M31 : 32; /* 447..416 */
uint64_t IPT_M32 : 32; /* 479..448 */
uint64_t IPT_M33 : 32; /* 511..480 */
uint64_t SourceRectLeft : 14; /* 525..512 */
uint64_t reserved11 : 2; /* 527..526 */
uint64_t SourceRectRight : 14; /* 541..528 */
uint64_t reserved12 : 2; /* 543..542 */
uint64_t SourceRectTop : 14; /* 557..544 */
uint64_t reserved13 : 2; /* 559..558 */
uint64_t SourceRectBottom : 14; /* 573..560 */
uint64_t reserved14; /* 575..574 */
uint64_t SrcImgWidth : 14; /* 589..576 */
uint64_t reserved15 : 2; /* 591..590 */
uint64_t SrcImgHeight : 14; /* 605..592 */
uint64_t reserved16 : 2; /* 607..606 */
uint64_t SrcSfcLumaWidth : 14; /* 621..608 */
uint64_t reserved17 : 2; /* 623..622 */
uint64_t SrcSfcLumaHeight : 14; /* 637..624 */
uint64_t reserved18 : 2; /* 639..638 */
uint64_t SrcSfcChromaWidth : 14; /* 653..640 */
uint64_t reserved19 : 2; /* 655..654 */
uint64_t SrcSfcChromaHeight : 14; /* 669..656 */
uint64_t reserved20 : 2; /* 671..670 */
uint64_t DestRectLeft : 14; /* 685..672 */
uint64_t reserved21 : 2; /* 687..686 */
uint64_t DestRectRight : 14; /* 701..688 */
uint64_t reserved22 : 2; /* 703..702 */
uint64_t DestRectTop : 14; /* 717..704 */
uint64_t reserved23 : 2; /* 719..718 */
uint64_t DestRectBottom : 14; /* 733..720 */
uint64_t reserved24 : 2; /* 735..734 */
uint64_t SubFrameRectTop : 14; /* 749..736 */
uint64_t reserved25 : 2; /* 751..750 */
uint64_t SubFrameRectBottom : 14; /* 765..752 */
uint64_t reserved26 : 2; /* 767..766 */
uint64_t DestSfcLumaWidth : 14; /* 781..768 */
uint64_t reserved27 : 2; /* 783..782 */
uint64_t DestSfcLumaHeight : 14; /* 797..784 */
uint64_t reserved28 : 2; /* 799..798 */
uint64_t DestSfcChromaWidth : 14; /* 813..800 */
uint64_t reserved29 : 2; /* 815..814 */
uint64_t DestSfcChromaHeight : 14; /* 829..816 */
uint64_t reserved30 : 2; /* 831..830 */
uint64_t SparseWarpMapWidth : 14; /* 845..832 */
uint64_t reserved31 : 2; /* 847..846 */
uint64_t SparseWarpMapHeight : 14; /* 861..848 */
uint64_t reserved32 : 2; /* 863..862 */
uint64_t SparseWarpMapStride : 14; /* 877..864 */
uint64_t reserved33 : 2; /* 879..878 */
uint64_t MaskBitMapWidth : 14; /* 893..880 */
uint64_t reserved34 : 2; /* 895..894 */
uint64_t MaskBitMapHeight : 14; /* 909..896 */
uint64_t reserved35 : 2; /* 911..910 */
uint64_t MaskBitMapStride : 14; /* 925..912 */
uint64_t reserved36 : 2; /* 927..926 */
uint64_t XSobelWidth : 14; /* 941..928 */
uint64_t reserved37 : 2; /* 943..942 */
uint64_t XSobelHeight : 14; /* 957..944 */
uint64_t reserved38 : 2; /* 959..958 */
uint64_t XSobelStride : 14; /* 973..960 */
uint64_t reserved39 : 2; /* 975..974 */
uint64_t DSStride : 14; /* 989..976 */
uint64_t reserved40 : 2; /* 991..990 */
uint64_t XSobelTopOffset : 32; /* 1023..992 */
uint64_t reserved41 : 32; /* 1055..1024 */
uint64_t maskY : 16; /* 1071..1056 */
uint64_t maskU : 16; /* 1087..1072 */
uint64_t maskV : 16; /* 1103..1088 */
uint64_t reserved42 : 16; /* 1119..1104 */
} GeoTranConfigParamStruct;
typedef struct {
uint64_t TNR3En : 1; /* 0 */
uint64_t BetaBlendingEn : 1; /* 1 */
uint64_t AlphaBlendingEn : 1; /* 2 */
uint64_t AlphaSmoothEn : 1; /* 3 */
uint64_t TempAlphaRestrictEn : 1; /* 4 */
uint64_t AlphaClipEn : 1; /* 5 */
uint64_t BFRangeEn : 1; /* 6 */
uint64_t BFDomainEn : 1; /* 7 */
uint64_t BFRangeLumaShift : 4; /* 11..8 */
uint64_t BFRangeChromaShift : 4; /* 15..12 */
uint64_t SADMultiplier : 6; /* 21..16 */
uint64_t reserved1 : 2; /* 23..22 */
uint64_t SADWeightLuma : 6; /* 29..24 */
uint64_t reserved2 : 2; /* 31..30 */
uint64_t TempAlphaRestrictIncCap : 11; /* 42..32 */
uint64_t reserved3 : 5; /* 47..43 */
uint64_t AlphaScaleIIR : 11; /* 58..48 */
uint64_t reserved4 : 5; /* 63..59 */
uint64_t AlphaClipMaxLuma : 11; /* 74..64 */
uint64_t reserved5 : 5; /* 79..75 */
uint64_t AlphaClipMinLuma : 11; /* 90..80 */
uint64_t reserved6 : 5; /* 95..91 */
uint64_t AlphaClipMaxChroma : 11; /* 106..96 */
uint64_t reserved7 : 5; /* 111..107 */
uint64_t AlphaClipMinChroma : 11; /* 122..112 */
uint64_t reserved8 : 5; /* 127..123 */
uint64_t BetaCalcMaxBeta : 11; /* 138..128 */
uint64_t reserved9 : 5; /* 143..139 */
uint64_t BetaCalcMinBeta : 11; /* 154..144 */
uint64_t reserved10 : 5; /* 159..155 */
uint64_t BetaCalcBetaX1 : 11; /* 170..160 */
uint64_t reserved11 : 5; /* 175..171 */
uint64_t BetaCalcBetaX2 : 11; /* 186..176 */
uint64_t reserved12 : 5; /* 191..187 */
uint64_t BetaCalcStepBeta : 11; /* 202..192 */
uint64_t reserved13 : 5; /* 207..203 */
uint64_t reserved14 : 16; /* 223..208 */
uint64_t BFDomainLumaCoeffC00 : 7; /* 230..224 */
uint64_t reserved15 : 1; /* 231 */
uint64_t BFDomainLumaCoeffC01 : 7; /* 238..232 */
uint64_t reserved16 : 1; /* 239 */
uint64_t BFDomainLumaCoeffC02 : 7; /* 246..240 */
uint64_t reserved17 : 1; /* 247 */
uint64_t BFDomainLumaCoeffC11 : 7; /* 254..248 */
uint64_t reserved18 : 1; /* 255 */
uint64_t BFDomainLumaCoeffC12 : 7; /* 262..256 */
uint64_t reserved19 : 1; /* 263 */
uint64_t BFDomainLumaCoeffC22 : 7; /* 270..264 */
uint64_t reserved20 : 1; /* 271 */
uint64_t reserved21 : 16; /* 287..272 */
uint64_t BFDomainChromaCoeffC00 : 7; /* 294..288 */
uint64_t reserved22 : 1; /* 295 */
uint64_t BFDomainChromaCoeffC01 : 7; /* 302..296 */
uint64_t reserved23 : 1; /* 303 */
uint64_t BFDomainChromaCoeffC02 : 7; /* 310..304 */
uint64_t reserved24 : 1; /* 311 */
uint64_t BFDomainChromaCoeffC11 : 7; /* 318..312 */
uint64_t reserved25 : 1; /* 319 */
uint64_t BFDomainChromaCoeffC12 : 7; /* 326..320 */
uint64_t reserved26 : 1; /* 327 */
uint64_t BFDomainChromaCoeffC22 : 7; /* 334..328 */
uint64_t reserved27 : 1; /* 335 */
uint64_t reserved28 : 16; /* 351..336 */
uint64_t LeftBufSize : 32; /* 383..352 */
uint64_t TopBufSize : 32; /* 415..384 */
uint64_t AlphaSufStride : 14; /* 429..416 */
uint64_t reserved29 : 18; /* 447..430 */
} TNR3ConfigParamStruct;
typedef struct {
uint64_t item0 : 7; /* 6..0 */
uint64_t reserved0 : 9; /* 15..7 */
uint64_t item1 : 7; /* 22..16 */
uint64_t reserved1 : 9; /* 31..23 */
uint64_t item2 : 7; /* 38..32 */
uint64_t reserved2 : 9; /* 47..39 */
uint64_t item3 : 7; /* 54..48 */
uint64_t reserved3 : 9; /* 63..55 */
} BFRangeTableItems;
typedef struct {
SlotConfig slotConfig;
SlotSurfaceConfig slotSurfaceConfig;
LumaKeyStruct lumaKeyStruct;
MatrixStruct colorMatrixStruct;
MatrixStruct gamutMatrixStruct;
BlendingSlotStruct blendingSlotStruct;
} SlotStruct;
typedef struct {
FilterCoeffStruct filterCoeffStruct[520];
} FilterStruct;
typedef struct {
PipeConfig pipeConfig;
OutputConfig outputConfig;
OutputSurfaceConfig outputSurfaceConfig;
MatrixStruct outColorMatrixStruct;
ClearRectStruct clearRectStruct[4];
SlotStruct slotStruct[16];
} ConfigStruct;
typedef struct {
PartitionCrcStruct partitionCrcStruct[2];
} InterfaceCrcStruct;
typedef struct {
SlotCrcStruct slotCrcStruct[16];
} InputCrcStruct;
typedef struct {
GeoTranConfigParamStruct paramConfig;
CoeffPhaseParamStruct FilterCoeff[17];
TNR3ConfigParamStruct tnr3Config;
BFRangeTableItems BFRangeTableLuma[16];
BFRangeTableItems BFRangeTableChroma[16];
} GeoTranConfigStruct;
#endif