357 lines
11 KiB
C
357 lines
11 KiB
C
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/*
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* Copyright 2010 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors: Alex Deucher <alexander.deucher@amd.com>
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*
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*/
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#ifndef __EVERGREEN_STATE_H__
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#define __EVERGREEN_STATE_H__
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typedef int bool_t;
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#define CLEAR(x) memset (&x, 0, sizeof(x))
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/* Sequencer / thread handling */
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typedef struct {
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int ps_prio;
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int vs_prio;
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int gs_prio;
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int es_prio;
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int hs_prio;
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int ls_prio;
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int cs_prio;
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int num_ps_gprs;
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int num_vs_gprs;
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int num_gs_gprs;
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int num_es_gprs;
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int num_hs_gprs;
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int num_ls_gprs;
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int num_cs_gprs;
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int num_temp_gprs;
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int num_ps_threads;
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int num_vs_threads;
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int num_gs_threads;
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int num_es_threads;
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int num_hs_threads;
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int num_ls_threads;
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int num_ps_stack_entries;
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int num_vs_stack_entries;
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int num_gs_stack_entries;
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int num_es_stack_entries;
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int num_hs_stack_entries;
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int num_ls_stack_entries;
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} sq_config_t;
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/* Color buffer / render target */
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typedef struct {
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int id;
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int w;
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int h;
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uint64_t base;
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int format;
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int endian;
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int array_mode; // tiling
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int non_disp_tiling;
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int number_type;
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int read_size;
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int comp_swap;
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int tile_mode;
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int blend_clamp;
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int clear_color;
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int blend_bypass;
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int simple_float;
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int round_mode;
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int tile_compact;
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int source_format;
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int resource_type;
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int fast_clear;
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int compression;
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int rat;
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/* 2D related CB state */
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uint32_t pmask;
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int rop;
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int blend_enable;
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uint32_t blendcntl;
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struct radeon_bo *bo;
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struct radeon_surface *surface;
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} cb_config_t;
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/* Shader */
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typedef struct {
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uint64_t shader_addr;
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uint32_t shader_size;
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int num_gprs;
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int stack_size;
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int dx10_clamp;
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int clamp_consts;
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int export_mode;
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int uncached_first_inst;
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int single_round;
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int double_round;
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int allow_sdi;
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int allow_sd0;
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int allow_ddi;
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int allow_ddo;
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struct radeon_bo *bo;
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} shader_config_t;
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/* Shader consts */
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typedef struct {
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int type;
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int size_bytes;
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uint64_t const_addr;
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struct radeon_bo *bo;
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uint32_t *cpu_ptr;
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} const_config_t;
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/* Vertex buffer / vtx resource */
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typedef struct {
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int id;
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uint64_t vb_addr;
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uint32_t vtx_num_entries;
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uint32_t vtx_size_dw;
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int clamp_x;
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int format;
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int num_format_all;
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int format_comp_all;
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int srf_mode_all;
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int endian;
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int mem_req_size;
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int dst_sel_x;
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int dst_sel_y;
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int dst_sel_z;
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int dst_sel_w;
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int uncached;
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struct radeon_bo *bo;
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} vtx_resource_t;
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/* Texture resource */
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typedef struct {
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int id;
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int w;
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int h;
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int pitch;
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int depth;
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int dim;
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int array_mode;
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int tile_type;
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int format;
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uint64_t base;
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uint64_t mip_base;
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uint32_t size;
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int format_comp_x;
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int format_comp_y;
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int format_comp_z;
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int format_comp_w;
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int num_format_all;
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int srf_mode_all;
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int force_degamma;
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int endian;
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int dst_sel_x;
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int dst_sel_y;
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int dst_sel_z;
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int dst_sel_w;
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int base_level;
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int last_level;
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int base_array;
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int last_array;
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int perf_modulation;
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int interlaced;
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int min_lod;
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struct radeon_bo *bo;
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struct radeon_bo *mip_bo;
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struct radeon_surface *surface;
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} tex_resource_t;
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/* Texture sampler */
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typedef struct {
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int id;
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/* Clamping */
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int clamp_x, clamp_y, clamp_z;
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int border_color;
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/* Filtering */
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int xy_mag_filter, xy_min_filter;
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int z_filter;
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int mip_filter;
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bool_t high_precision_filter; /* ? */
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int perf_mip; /* ? 0-7 */
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int perf_z; /* ? 3 */
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/* LoD selection */
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int min_lod, max_lod; /* 0-0x3ff */
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int lod_bias; /* 0-0xfff (signed?) */
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int lod_bias2; /* ? 0-0xfff (signed?) */
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bool_t lod_uses_minor_axis; /* ? */
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/* Other stuff */
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bool_t point_sampling_clamp; /* ? */
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bool_t tex_array_override; /* ? */
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bool_t mc_coord_truncate; /* ? */
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bool_t force_degamma; /* ? */
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bool_t fetch_4; /* ? */
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bool_t sample_is_pcf; /* ? */
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bool_t type; /* ? */
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int depth_compare; /* only depth textures? */
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int chroma_key;
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int truncate_coord;
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bool_t disable_cube_wrap;
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} tex_sampler_t;
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/* Draw command */
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typedef struct {
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uint32_t prim_type;
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uint32_t vgt_draw_initiator;
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uint32_t index_type;
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uint32_t num_instances;
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uint32_t num_indices;
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} draw_config_t;
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#define BEGIN_BATCH(n) \
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do { \
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radeon_ddx_cs_start(pScrn, (n), __FILE__, __func__, __LINE__); \
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} while(0)
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#define END_BATCH() \
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do { \
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radeon_cs_end(info->cs, __FILE__, __func__, __LINE__); \
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} while(0)
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#define RELOC_BATCH(bo, rd, wd) \
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do { \
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int _ret; \
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_ret = radeon_cs_write_reloc(info->cs, (bo), (rd), (wd), 0); \
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if (_ret) ErrorF("reloc emit failure %d (%s %d)\n", _ret, __func__, __LINE__); \
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} while(0)
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#define E32(dword) \
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do { \
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radeon_cs_write_dword(info->cs, (dword)); \
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} while (0)
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#define EFLOAT(val) \
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do { \
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union { float f; uint32_t d; } a; \
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a.f = (val); \
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E32(a.d); \
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} while (0)
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#define PACK3(cmd, num) \
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do { \
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E32(RADEON_CP_PACKET3 | ((cmd) << 8) | ((((num) - 1) & 0x3fff) << 16)); \
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} while (0)
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/* write num registers, start at reg */
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/* If register falls in a special area, special commands are issued */
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#define PACK0(reg, num) \
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do { \
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if ((reg) >= SET_CONFIG_REG_offset && (reg) < SET_CONFIG_REG_end) { \
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PACK3(IT_SET_CONFIG_REG, (num) + 1); \
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E32(((reg) - SET_CONFIG_REG_offset) >> 2); \
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} else if ((reg) >= SET_CONTEXT_REG_offset && (reg) < SET_CONTEXT_REG_end) { \
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PACK3(IT_SET_CONTEXT_REG, (num) + 1); \
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E32(((reg) - SET_CONTEXT_REG_offset) >> 2); \
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} else if ((reg) >= SET_RESOURCE_offset && (reg) < SET_RESOURCE_end) { \
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PACK3(IT_SET_RESOURCE, num + 1); \
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E32(((reg) - SET_RESOURCE_offset) >> 2); \
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} else if ((reg) >= SET_SAMPLER_offset && (reg) < SET_SAMPLER_end) { \
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PACK3(IT_SET_SAMPLER, (num) + 1); \
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E32((reg - SET_SAMPLER_offset) >> 2); \
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} else if ((reg) >= SET_CTL_CONST_offset && (reg) < SET_CTL_CONST_end) { \
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PACK3(IT_SET_CTL_CONST, (num) + 1); \
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E32(((reg) - SET_CTL_CONST_offset) >> 2); \
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} else if ((reg) >= SET_LOOP_CONST_offset && (reg) < SET_LOOP_CONST_end) { \
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PACK3(IT_SET_LOOP_CONST, (num) + 1); \
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E32(((reg) - SET_LOOP_CONST_offset) >> 2); \
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} else if ((reg) >= SET_BOOL_CONST_offset && (reg) < SET_BOOL_CONST_end) { \
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PACK3(IT_SET_BOOL_CONST, (num) + 1); \
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E32(((reg) - SET_BOOL_CONST_offset) >> 2); \
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} else { \
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E32(CP_PACKET0 ((reg), (num) - 1)); \
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} \
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} while (0)
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/* write a single register */
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#define EREG(reg, val) \
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do { \
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PACK0((reg), 1); \
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E32((val)); \
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} while (0)
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void
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evergreen_start_3d(ScrnInfoPtr pScrn);
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void
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evergreen_set_render_target(ScrnInfoPtr pScrn, cb_config_t *cb_conf, uint32_t domain);
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void
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evergreen_set_blend_color(ScrnInfoPtr pScrn, float *color);
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void
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evergreen_cp_wait_vline_sync(ScrnInfoPtr pScrn, PixmapPtr pPix, xf86CrtcPtr crtc, int start, int stop);
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void
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evergreen_set_spi(ScrnInfoPtr pScrn, int vs_export_count, int num_interp);
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void
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evergreen_fs_setup(ScrnInfoPtr pScrn, shader_config_t *fs_conf, uint32_t domain);
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void
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evergreen_vs_setup(ScrnInfoPtr pScrn, shader_config_t *vs_conf, uint32_t domain);
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void
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evergreen_ps_setup(ScrnInfoPtr pScrn, shader_config_t *ps_conf, uint32_t domain);
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void
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evergreen_set_alu_consts(ScrnInfoPtr pScrn, const_config_t *const_conf, uint32_t domain);
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void
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evergreen_set_bool_consts(ScrnInfoPtr pScrn, int offset, uint32_t val);
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void
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evergreen_set_tex_resource(ScrnInfoPtr pScrn, tex_resource_t *tex_res, uint32_t domain);
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void
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evergreen_set_tex_sampler(ScrnInfoPtr pScrn, tex_sampler_t *s);
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void
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evergreen_set_screen_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2);
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void
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evergreen_set_vport_scissor(ScrnInfoPtr pScrn, int id, int x1, int y1, int x2, int y2);
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void
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evergreen_set_generic_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2);
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void
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evergreen_set_window_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2);
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void
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evergreen_set_clip_rect(ScrnInfoPtr pScrn, int id, int x1, int y1, int x2, int y2);
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void
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evergreen_set_default_state(ScrnInfoPtr pScrn);
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void
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cayman_set_default_state(ScrnInfoPtr pScrn);
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void
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evergreen_draw_auto(ScrnInfoPtr pScrn, draw_config_t *draw_conf);
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void evergreen_finish_op(ScrnInfoPtr pScrn, int vtx_size);
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extern Bool
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R600SetAccelState(ScrnInfoPtr pScrn,
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struct r600_accel_object *src0,
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struct r600_accel_object *src1,
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struct r600_accel_object *dst,
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uint32_t vs_offset, uint32_t ps_offset,
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int rop, Pixel planemask);
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extern Bool RADEONPrepareAccess_CS(PixmapPtr pPix, int index);
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extern void RADEONFinishAccess_CS(PixmapPtr pPix, int index);
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extern void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height,
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int depth, int usage_hint, int bitsPerPixel,
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int *new_pitch);
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extern void RADEONEXADestroyPixmap(ScreenPtr pScreen, void *driverPriv);
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extern Bool RADEONEXAPixmapIsOffscreen(PixmapPtr pPix);
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extern Bool RADEONEXASharePixmapBacking(PixmapPtr ppix, ScreenPtr secondary, void **handle_p);
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extern Bool RADEONEXASetSharedPixmapBacking(PixmapPtr ppix, void *handle);
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#endif
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