201 lines
7.6 KiB
C
201 lines
7.6 KiB
C
/* $OpenBSD: pciidevar.h,v 1.21 2015/09/10 18:10:34 deraadt Exp $ */
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/* $NetBSD: pciidevar.h,v 1.6 2001/01/12 16:04:00 bouyer Exp $ */
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/*
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* Copyright (c) 1998 Christopher G. Demetriou. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Christopher G. Demetriou
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* for the NetBSD Project.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DEV_PCI_PCIIDEVAR_H_
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#define _DEV_PCI_PCIIDEVAR_H_
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/*
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* PCI IDE driver exported software structures.
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*
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* Author: Christopher G. Demetriou, March 2, 1998.
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*/
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#include <dev/ata/atavar.h>
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#include <dev/ic/wdcreg.h>
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#include <dev/ic/wdcvar.h>
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/*
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* While standard PCI IDE controllers only have 2 channels, it is
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* common for PCI SATA controllers to have more. Here we define
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* the maximum number of channels that any one PCI IDE device can
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* have.
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*/
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#define PCIIDE_MAX_CHANNELS 4
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struct pciide_softc {
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struct wdc_softc sc_wdcdev; /* common wdc definitions */
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pci_chipset_tag_t sc_pc; /* PCI registers info */
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pcitag_t sc_tag;
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void *sc_pci_ih; /* PCI interrupt handle */
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int sc_dma_ok; /* bus-master DMA info */
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bus_space_tag_t sc_dma_iot;
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bus_space_handle_t sc_dma_ioh;
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bus_size_t sc_dma_iosz;
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bus_dma_tag_t sc_dmat;
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/*
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* Some controllers might have DMA restrictions other than
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* the norm.
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*/
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bus_size_t sc_dma_maxsegsz;
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bus_size_t sc_dma_boundary;
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/*
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* Used as a register save space by pciide_activate()
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*
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* sc_save[] is for the 6 pci regs starting at PCI_MAPREG_END + 0x18 --
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* most IDE chipsets need a subset of those saved. sc_save2 is for
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* up to 6 other registers, which specific chips might need saved.
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*/
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pcireg_t sc_save[6];
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pcireg_t sc_save2[6];
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/* Chip description */
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const struct pciide_product_desc *sc_pp;
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/* unmap/detach */
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void (*chip_unmap)(struct pciide_softc *, int);
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/* Chip revision */
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int sc_rev;
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/* common definitions */
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struct channel_softc *wdc_chanarray[PCIIDE_MAX_CHANNELS];
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/* internal bookkeeping */
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struct pciide_channel { /* per-channel data */
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struct channel_softc wdc_channel; /* generic part */
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const char *name;
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int hw_ok; /* hardware mapped & OK? */
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int compat; /* is it compat? */
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int dma_in_progress;
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void *ih; /* compat or pci handle */
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bus_space_handle_t ctl_baseioh; /* ctrl regs blk, native mode */
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/* DMA tables and DMA map for xfer, for each drive */
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struct pciide_dma_maps {
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bus_dmamap_t dmamap_table;
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struct idedma_table *dma_table;
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bus_dmamap_t dmamap_xfer;
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int dma_flags;
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} dma_maps[2];
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/*
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* Some controllers require certain bits to
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* always be set for proper operation of the
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* controller. Set those bits here, if they're
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* required.
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*/
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uint8_t idedma_cmd;
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} pciide_channels[PCIIDE_MAX_CHANNELS];
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/* Chip-specific private data */
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void *sc_cookie;
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size_t sc_cookielen;
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/* DMA registers access functions */
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u_int8_t (*sc_dmacmd_read)(struct pciide_softc *, int);
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void (*sc_dmacmd_write)(struct pciide_softc *, int, u_int8_t);
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u_int8_t (*sc_dmactl_read)(struct pciide_softc *, int);
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void (*sc_dmactl_write)(struct pciide_softc *, int, u_int8_t);
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void (*sc_dmatbl_write)(struct pciide_softc *, int, u_int32_t);
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};
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#define PCIIDE_DMACMD_READ(sc, chan) \
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(sc)->sc_dmacmd_read((sc), (chan))
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#define PCIIDE_DMACMD_WRITE(sc, chan, val) \
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(sc)->sc_dmacmd_write((sc), (chan), (val))
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#define PCIIDE_DMACTL_READ(sc, chan) \
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(sc)->sc_dmactl_read((sc), (chan))
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#define PCIIDE_DMACTL_WRITE(sc, chan, val) \
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(sc)->sc_dmactl_write((sc), (chan), (val))
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#define PCIIDE_DMATBL_WRITE(sc, chan, val) \
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(sc)->sc_dmatbl_write((sc), (chan), (val))
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int pciide_mapregs_compat( struct pci_attach_args *,
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struct pciide_channel *, int, bus_size_t *, bus_size_t *);
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int pciide_mapregs_native(struct pci_attach_args *,
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struct pciide_channel *, bus_size_t *, bus_size_t *,
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int (*pci_intr)(void *));
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void pciide_mapreg_dma(struct pciide_softc *,
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struct pci_attach_args *);
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int pciide_chansetup(struct pciide_softc *, int, pcireg_t);
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void pciide_mapchan(struct pci_attach_args *,
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struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *,
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int (*pci_intr)(void *));
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int pciide_chan_candisable(struct pciide_channel *);
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void pciide_map_compat_intr( struct pci_attach_args *,
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struct pciide_channel *, int, int);
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void pciide_unmap_compat_intr( struct pci_attach_args *,
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struct pciide_channel *, int, int);
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int pciide_compat_intr(void *);
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int pciide_pci_intr(void *);
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int pciide_intr_flag(struct pciide_channel *);
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u_int8_t pciide_dmacmd_read(struct pciide_softc *, int);
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void pciide_dmacmd_write(struct pciide_softc *, int, u_int8_t);
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u_int8_t pciide_dmactl_read(struct pciide_softc *, int);
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void pciide_dmactl_write(struct pciide_softc *, int, u_int8_t);
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void pciide_dmatbl_write(struct pciide_softc *, int, u_int32_t);
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void pciide_channel_dma_setup(struct pciide_channel *);
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int pciide_dma_table_setup(struct pciide_softc *, int, int);
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int pciide_dma_init(void *, int, int, void *, size_t, int);
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void pciide_dma_start(void *, int, int);
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int pciide_dma_finish(void *, int, int, int);
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void pciide_irqack(struct channel_softc *);
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void pciide_print_modes(struct pciide_channel *);
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void pciide_print_channels(int, pcireg_t);
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void default_chip_unmap(struct pciide_softc *, int);
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void pciide_unmapreg_dma(struct pciide_softc *);
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void pciide_chanfree(struct pciide_softc *, int);
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void pciide_unmap_chan(struct pciide_softc *, struct pciide_channel *, int);
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int pciide_unmapregs_compat(struct pciide_softc *,
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struct pciide_channel *);
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int pciide_unmapregs_native(struct pciide_softc *,
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struct pciide_channel *);
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int pciide_dma_table_free(struct pciide_softc *, int, int);
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void pciide_channel_dma_free(struct pciide_channel *);
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/*
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* Functions defined by machine-dependent code.
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*/
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#ifdef __i386__
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void gcsc_chip_map(struct pciide_softc *, struct pci_attach_args *);
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#endif
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/* Attach compat interrupt handler, returning handle or NULL if failed. */
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#if !defined(pciide_machdep_compat_intr_establish)
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void *pciide_machdep_compat_intr_establish(struct device *,
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struct pci_attach_args *, int, int (*)(void *), void *);
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void pciide_machdep_compat_intr_disestablish(pci_chipset_tag_t pc,
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void *);
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#endif
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#endif /* !_DEV_PCI_PCIIDEVAR_H_ */
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