304 lines
8.2 KiB
C
304 lines
8.2 KiB
C
/* $OpenBSD: if_gem_pci.c,v 1.41 2024/05/24 06:02:53 jsg Exp $ */
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/* $NetBSD: if_gem_pci.c,v 1.1 2001/09/16 00:11:42 eeh Exp $ */
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/*
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*
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* Copyright (C) 2001 Eduardo Horvath.
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* All rights reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/*
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* PCI bindings for Sun GEM ethernet controllers.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <net/if.h>
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#include <net/if_media.h>
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#include <netinet/in.h>
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#include <netinet/if_ether.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#ifdef __sparc64__
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#include <dev/ofw/openfirm.h>
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#endif
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#include <dev/mii/miivar.h>
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#include <dev/ic/gemreg.h>
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#include <dev/ic/gemvar.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcidevs.h>
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struct gem_pci_softc {
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struct gem_softc gsc_gem; /* GEM device */
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bus_space_tag_t gsc_memt;
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bus_space_handle_t gsc_memh;
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bus_size_t gsc_memsize;
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pci_chipset_tag_t gsc_pc;
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};
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int gem_match_pci(struct device *, void *, void *);
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void gem_attach_pci(struct device *, struct device *, void *);
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int gem_detach_pci(struct device *, int);
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int gem_pci_enaddr(struct gem_softc *, struct pci_attach_args *);
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const struct cfattach gem_pci_ca = {
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sizeof(struct gem_pci_softc), gem_match_pci, gem_attach_pci,
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gem_detach_pci
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};
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/*
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* Attach routines need to be split out to different bus-specific files.
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*/
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const struct pci_matchid gem_pci_devices[] = {
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{ PCI_VENDOR_SUN, PCI_PRODUCT_SUN_ERINETWORK },
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{ PCI_VENDOR_SUN, PCI_PRODUCT_SUN_GEMNETWORK },
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{ PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_INTREPID2_GMAC },
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{ PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_K2_GMAC },
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{ PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_PANGEA_GMAC },
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{ PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_SHASTA_GMAC },
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{ PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_UNINORTHGMAC },
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{ PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_UNINORTH2GMAC },
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};
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int
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gem_match_pci(struct device *parent, void *cf, void *aux)
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{
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return (pci_matchbyid((struct pci_attach_args *)aux, gem_pci_devices,
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nitems(gem_pci_devices)));
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}
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#define PROMHDR_PTR_DATA 0x18
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#define PROMDATA_PTR_VPD 0x08
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#define PROMDATA_DATA2 0x0a
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static const u_int8_t gem_promhdr[] = { 0x55, 0xaa };
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static const u_int8_t gem_promdat[] = {
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'P', 'C', 'I', 'R',
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PCI_VENDOR_SUN & 0xff, PCI_VENDOR_SUN >> 8,
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PCI_PRODUCT_SUN_GEMNETWORK & 0xff, PCI_PRODUCT_SUN_GEMNETWORK >> 8
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};
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static const u_int8_t gem_promdat2[] = {
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0x18, 0x00, /* structure length */
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0x00, /* structure revision */
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0x00, /* interface revision */
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PCI_SUBCLASS_NETWORK_ETHERNET, /* subclass code */
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PCI_CLASS_NETWORK /* class code */
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};
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int
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gem_pci_enaddr(struct gem_softc *sc, struct pci_attach_args *pa)
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{
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struct pci_vpd *vpd;
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bus_space_handle_t romh;
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bus_space_tag_t romt;
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bus_size_t romsize = 0;
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u_int8_t buf[32];
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pcireg_t address;
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int dataoff, vpdoff;
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int rv = -1;
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if (pci_mapreg_map(pa, PCI_ROM_REG, PCI_MAPREG_TYPE_MEM, 0,
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&romt, &romh, 0, &romsize, 0))
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return (-1);
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address = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ROM_REG);
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address |= PCI_ROM_ENABLE;
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pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG, address);
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bus_space_read_region_1(romt, romh, 0, buf, sizeof(buf));
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if (bcmp(buf, gem_promhdr, sizeof(gem_promhdr)))
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goto fail;
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dataoff = buf[PROMHDR_PTR_DATA] | (buf[PROMHDR_PTR_DATA + 1] << 8);
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if (dataoff < 0x1c)
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goto fail;
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bus_space_read_region_1(romt, romh, dataoff, buf, sizeof(buf));
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if (bcmp(buf, gem_promdat, sizeof(gem_promdat)) ||
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bcmp(buf + PROMDATA_DATA2, gem_promdat2, sizeof(gem_promdat2)))
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goto fail;
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vpdoff = buf[PROMDATA_PTR_VPD] | (buf[PROMDATA_PTR_VPD + 1] << 8);
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if (vpdoff < 0x1c)
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goto fail;
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bus_space_read_region_1(romt, romh, vpdoff, buf, sizeof(buf));
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/*
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* The VPD of gem is not in PCI 2.2 standard format. The length
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* in the resource header is in big endian.
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*/
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vpd = (struct pci_vpd *)(buf + 3);
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if (!PCI_VPDRES_ISLARGE(buf[0]) ||
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PCI_VPDRES_LARGE_NAME(buf[0]) != PCI_VPDRES_TYPE_VPD)
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goto fail;
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if (vpd->vpd_key0 != 'N' || vpd->vpd_key1 != 'A')
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goto fail;
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bcopy(buf + 6, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN);
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rv = 0;
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fail:
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if (romsize != 0)
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bus_space_unmap(romt, romh, romsize);
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address = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ROM_REG);
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address &= ~PCI_ROM_ENABLE;
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pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG, address);
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return (rv);
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}
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void
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gem_attach_pci(struct device *parent, struct device *self, void *aux)
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{
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struct pci_attach_args *pa = aux;
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struct gem_pci_softc *gsc = (void *)self;
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struct gem_softc *sc = &gsc->gsc_gem;
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pci_intr_handle_t ih;
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#ifdef __sparc64__
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/* XXX the following declarations should be elsewhere */
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extern void myetheraddr(u_char *);
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#endif
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const char *intrstr = NULL;
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int type, gotenaddr = 0;
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gsc->gsc_pc = pa->pa_pc;
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if (pa->pa_memt) {
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type = PCI_MAPREG_TYPE_MEM;
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sc->sc_bustag = pa->pa_memt;
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} else {
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type = PCI_MAPREG_TYPE_IO;
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sc->sc_bustag = pa->pa_iot;
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}
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sc->sc_dmatag = pa->pa_dmat;
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sc->sc_pci = 1; /* XXXXX should all be done in bus_dma. */
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switch (PCI_PRODUCT(pa->pa_id)) {
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case PCI_PRODUCT_SUN_GEMNETWORK:
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sc->sc_variant = GEM_SUN_GEM;
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break;
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case PCI_PRODUCT_SUN_ERINETWORK:
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sc->sc_variant = GEM_SUN_ERI;
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break;
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case PCI_PRODUCT_APPLE_K2_GMAC:
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sc->sc_variant = GEM_APPLE_K2_GMAC;
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break;
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default:
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sc->sc_variant = GEM_APPLE_GMAC;
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}
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#define PCI_GEM_BASEADDR 0x10
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if (pci_mapreg_map(pa, PCI_GEM_BASEADDR, type, 0,
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&gsc->gsc_memt, &gsc->gsc_memh, NULL, &gsc->gsc_memsize, 0) != 0) {
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printf(": can't map registers\n");
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return;
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}
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sc->sc_bustag = gsc->gsc_memt;
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sc->sc_h1 = gsc->gsc_memh;
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if (bus_space_subregion(sc->sc_bustag, sc->sc_h1,
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GEM_PCI_BANK2_OFFSET, GEM_PCI_BANK2_SIZE, &sc->sc_h2)) {
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printf(": unable to create bank 2 subregion\n");
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bus_space_unmap(gsc->gsc_memt, gsc->gsc_memh, gsc->gsc_memsize);
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return;
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}
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if (gem_pci_enaddr(sc, pa) == 0)
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gotenaddr = 1;
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#ifdef __sparc64__
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if (!gotenaddr) {
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if (OF_getprop(PCITAG_NODE(pa->pa_tag), "local-mac-address",
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sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN) <= 0)
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myetheraddr(sc->sc_arpcom.ac_enaddr);
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gotenaddr = 1;
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}
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#endif
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#ifdef __powerpc__
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if (!gotenaddr) {
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pci_ether_hw_addr(pa->pa_pc, sc->sc_arpcom.ac_enaddr);
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gotenaddr = 1;
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}
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#endif
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sc->sc_burst = 16; /* XXX */
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if (pci_intr_map(pa, &ih) != 0) {
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printf(": couldn't map interrupt\n");
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bus_space_unmap(gsc->gsc_memt, gsc->gsc_memh, gsc->gsc_memsize);
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return;
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}
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intrstr = pci_intr_string(pa->pa_pc, ih);
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sc->sc_ih = pci_intr_establish(pa->pa_pc,
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ih, IPL_NET | IPL_MPSAFE, gem_intr, sc, self->dv_xname);
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if (sc->sc_ih == NULL) {
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printf(": couldn't establish interrupt");
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if (intrstr != NULL)
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printf(" at %s", intrstr);
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printf("\n");
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bus_space_unmap(gsc->gsc_memt, gsc->gsc_memh, gsc->gsc_memsize);
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return;
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}
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printf(": %s", intrstr);
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/*
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* call the main configure
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*/
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gem_config(sc);
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}
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int
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gem_detach_pci(struct device *self, int flags)
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{
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struct gem_pci_softc *gsc = (void *)self;
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struct gem_softc *sc = &gsc->gsc_gem;
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timeout_del(&sc->sc_tick_ch);
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timeout_del(&sc->sc_rx_watchdog);
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gem_unconfig(sc);
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pci_intr_disestablish(gsc->gsc_pc, sc->sc_ih);
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bus_space_unmap(gsc->gsc_memt, gsc->gsc_memh, gsc->gsc_memsize);
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return (0);
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}
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