417 lines
11 KiB
C
417 lines
11 KiB
C
/* $OpenBSD: eephy.c,v 1.60 2022/04/06 18:59:29 naddy Exp $ */
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/*
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* Principal Author: Parag Patel
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* Copyright (c) 2001
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* Additional Copyright (c) 2001 by Traakan Software under same licence.
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* Secondary Author: Matthew Jacob
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*/
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/*
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* driver for the Marvell 88E1000 series external 1000/100/10-BT PHY.
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*/
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/*
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* Support added for the Marvell 88E1011 (Alaska) 1000/100/10baseTX and
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* 1000baseSX PHY.
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* Nathan Binkert <nate@openbsd.org>
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/socket.h>
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#include <net/if.h>
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#include <net/if_var.h>
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#include <net/if_media.h>
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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#include <dev/mii/miidevs.h>
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#include <dev/mii/eephyreg.h>
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int eephy_match(struct device *, void *, void *);
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void eephy_attach(struct device *, struct device *, void *);
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const struct cfattach eephy_ca = {
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sizeof (struct mii_softc), eephy_match, eephy_attach, mii_phy_detach
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};
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struct cfdriver eephy_cd = {
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NULL, "eephy", DV_DULL
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};
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int eephy_service(struct mii_softc *, struct mii_data *, int);
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void eephy_status(struct mii_softc *);
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void eephy_reset(struct mii_softc *);
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const struct mii_phy_funcs eephy_funcs = {
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eephy_service, eephy_status, eephy_reset,
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};
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static const struct mii_phydesc eephys[] = {
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{ MII_OUI_MARVELL, MII_MODEL_MARVELL_E1000_1,
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MII_STR_MARVELL_E1000_1 },
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{ MII_OUI_MARVELL, MII_MODEL_MARVELL_E1000_2,
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MII_STR_MARVELL_E1000_2 },
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{ MII_OUI_MARVELL, MII_MODEL_MARVELL_E1000_3,
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MII_STR_MARVELL_E1000_3 },
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{ MII_OUI_MARVELL, MII_MODEL_MARVELL_E1000_4,
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MII_STR_MARVELL_E1000_4 },
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{ MII_OUI_MARVELL, MII_MODEL_MARVELL_E1000S,
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MII_STR_MARVELL_E1000S },
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{ MII_OUI_MARVELL, MII_MODEL_MARVELL_E1011,
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MII_STR_MARVELL_E1011 },
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{ MII_OUI_MARVELL, MII_MODEL_MARVELL_E1111,
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MII_STR_MARVELL_E1111 },
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{ MII_OUI_MARVELL, MII_MODEL_MARVELL_E1112,
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MII_STR_MARVELL_E1112 },
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{ MII_OUI_MARVELL, MII_MODEL_MARVELL_E1116,
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MII_STR_MARVELL_E1116 },
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{ MII_OUI_MARVELL, MII_MODEL_MARVELL_E1116R,
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MII_STR_MARVELL_E1116R },
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{ MII_OUI_MARVELL, MII_MODEL_MARVELL_E1118,
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MII_STR_MARVELL_E1118 },
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{ MII_OUI_MARVELL, MII_MODEL_MARVELL_E1149,
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MII_STR_MARVELL_E1149 },
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{ MII_OUI_MARVELL, MII_MODEL_MARVELL_E1512,
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MII_STR_MARVELL_E1512 },
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{ MII_OUI_MARVELL, MII_MODEL_MARVELL_E1545,
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MII_STR_MARVELL_E1545 },
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{ MII_OUI_MARVELL, MII_MODEL_MARVELL_E3016,
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MII_STR_MARVELL_E3016},
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{ MII_OUI_MARVELL, MII_MODEL_MARVELL_E3082,
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MII_STR_MARVELL_E3082 },
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{ MII_OUI_MARVELL, MII_MODEL_MARVELL_PHYG65G,
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MII_STR_MARVELL_PHYG65G },
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{ MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1000_5,
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MII_STR_xxMARVELL_E1000_5 },
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{ MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1000_6,
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MII_STR_xxMARVELL_E1000_6 },
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{ MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1000_7,
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MII_STR_xxMARVELL_E1000_7 },
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{ MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1111,
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MII_STR_xxMARVELL_E1111 },
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{ 0, 0,
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NULL },
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};
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int
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eephy_match(struct device *parent, void *match, void *aux)
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{
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struct mii_attach_args *ma = aux;
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if (mii_phy_match(ma, eephys) != NULL)
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return (10);
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return (0);
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}
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void
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eephy_attach(struct device *parent, struct device *self, void *aux)
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{
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struct mii_softc *sc = (struct mii_softc *)self;
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struct mii_attach_args *ma = aux;
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struct mii_data *mii = ma->mii_data;
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const struct mii_phydesc *mpd;
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int reg, page;
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mpd = mii_phy_match(ma, eephys);
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printf(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2));
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sc->mii_inst = mii->mii_instance;
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sc->mii_phy = ma->mii_phyno;
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sc->mii_funcs = &eephy_funcs;
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sc->mii_model = MII_MODEL(ma->mii_id2);
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sc->mii_pdata = mii;
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sc->mii_flags = ma->mii_flags;
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/* XXX No loopback support yet, although the hardware can do it. */
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sc->mii_flags |= MIIF_NOLOOP;
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/* Make sure page 0 is selected. */
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PHY_WRITE(sc, E1000_EADR, 0);
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/* Switch to copper-only mode if necessary. */
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if (sc->mii_model == MII_MODEL_MARVELL_E1111 &&
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(sc->mii_flags & MIIF_HAVEFIBER) == 0) {
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/*
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* The onboard 88E1111 PHYs on the Sun X4100 M2 come
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* up with fiber/copper auto-selection enabled, even
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* though the machine only has copper ports. This
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* makes the chip autoselect to 1000baseX, and makes
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* it impossible to select any other media. So
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* disable fiber/copper autoselection.
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*/
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reg = PHY_READ(sc, E1000_ESSR);
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if ((reg & E1000_ESSR_HWCFG_MODE) == E1000_ESSR_RGMII_COPPER) {
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reg |= E1000_ESSR_DIS_FC;
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PHY_WRITE(sc, E1000_ESSR, reg);
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}
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}
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/* Switch to fiber-only mode if necessary. */
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if (sc->mii_model == MII_MODEL_MARVELL_E1112 &&
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sc->mii_flags & MIIF_HAVEFIBER) {
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page = PHY_READ(sc, E1000_EADR);
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PHY_WRITE(sc, E1000_EADR, 2);
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reg = PHY_READ(sc, E1000_SCR);
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reg &= ~E1000_SCR_MODE_MASK;
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reg |= E1000_SCR_MODE_1000BX;
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PHY_WRITE(sc, E1000_SCR, reg);
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PHY_WRITE(sc, E1000_EADR, page);
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}
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/* Switch to SGMII-to-copper mode if necessary. */
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if (sc->mii_model == MII_MODEL_MARVELL_E1512 &&
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sc->mii_flags & MIIF_SGMII) {
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page = PHY_READ(sc, E1000_EADR);
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PHY_WRITE(sc, E1000_EADR, 18);
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reg = PHY_READ(sc, E1000_GCR1);
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reg &= ~E1000_GCR1_MODE_MASK;
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reg |= E1000_GCR1_MODE_SGMII;
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reg |= E1000_GCR1_RESET;
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PHY_WRITE(sc, E1000_GCR1, reg);
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PHY_WRITE(sc, E1000_EADR, page);
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}
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PHY_RESET(sc);
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sc->mii_capabilities = PHY_READ(sc, E1000_SR) & ma->mii_capmask;
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if (sc->mii_capabilities & BMSR_EXTSTAT)
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sc->mii_extcapabilities = PHY_READ(sc, E1000_ESR);
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mii_phy_add_media(sc);
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}
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void
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eephy_reset(struct mii_softc *sc)
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{
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int reg, i;
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reg = PHY_READ(sc, E1000_CR);
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reg |= E1000_CR_RESET;
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PHY_WRITE(sc, E1000_CR, reg);
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for (i = 0; i < 500; i++) {
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DELAY(1);
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reg = PHY_READ(sc, E1000_CR);
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if (!(reg & E1000_CR_RESET))
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break;
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}
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/*
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* Initialize PHY Specific Control Register.
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*/
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reg = PHY_READ(sc, E1000_SCR);
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/* Assert CRS on transmit. */
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reg |= E1000_SCR_ASSERT_CRS_ON_TX;
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/* Enable auto crossover. */
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switch (sc->mii_model) {
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case MII_MODEL_MARVELL_E3016:
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case MII_MODEL_MARVELL_E3082:
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/* Bits are in a different position. */
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reg |= (E1000_SCR_AUTO_X_MODE >> 1);
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break;
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default:
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/* Automatic crossover causes problems for 1000baseX. */
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if (sc->mii_flags & MIIF_IS_1000X)
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reg &= ~E1000_SCR_AUTO_X_MODE;
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else
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reg |= E1000_SCR_AUTO_X_MODE;
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}
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/* Disable energy detect; only available on some models. */
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switch(sc->mii_model) {
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case MII_MODEL_MARVELL_E3016:
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reg &= ~E3000_SCR_EN_DETECT_MASK;
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break;
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case MII_MODEL_MARVELL_E1011:
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case MII_MODEL_MARVELL_E1111:
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case MII_MODEL_MARVELL_E1112:
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case MII_MODEL_MARVELL_PHYG65G:
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reg &= ~E1000_SCR_EN_DETECT_MASK;
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break;
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}
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/* Enable scrambler if necessary. */
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if (sc->mii_model == MII_MODEL_MARVELL_E3016)
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reg &= ~E3000_SCR_SCRAMBLER_DISABLE;
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/*
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* Store next page in the Link Partner Next Page register for
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* compatibility with 802.3ab.
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*/
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if (sc->mii_model == MII_MODEL_MARVELL_E3016)
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reg |= E3000_SCR_REG8_NEXT_PAGE;
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PHY_WRITE(sc, E1000_SCR, reg);
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/* 25 MHz TX_CLK should always work. */
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reg = PHY_READ(sc, E1000_ESCR);
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reg |= E1000_ESCR_TX_CLK_25;
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PHY_WRITE(sc, E1000_ESCR, reg);
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/* Configure LEDs if they were left unconfigured. */
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if (sc->mii_model == MII_MODEL_MARVELL_E3016 &&
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PHY_READ(sc, 0x16) == 0) {
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reg = (0x0b << 8) | (0x05 << 4) | 0x04; /* XXX */
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PHY_WRITE(sc, 0x16, reg);
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}
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/*
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* Do a software reset for these settings to take effect.
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* Disable autonegotiation, such that all capabilities get
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* advertised when it is switched back on.
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*/
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reg = PHY_READ(sc, E1000_CR);
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reg &= ~E1000_CR_AUTO_NEG_ENABLE;
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PHY_WRITE(sc, E1000_CR, reg | E1000_CR_RESET);
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}
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int
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eephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
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{
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struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
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int bmcr;
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if ((sc->mii_dev.dv_flags & DVF_ACTIVE) == 0)
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return (ENXIO);
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switch (cmd) {
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case MII_POLLSTAT:
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/*
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* If we're not polling our PHY instance, just return.
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*/
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if (IFM_INST(ife->ifm_media) != sc->mii_inst)
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return (0);
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break;
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case MII_MEDIACHG:
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/*
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* If the media indicates a different PHY instance,
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* isolate ourselves.
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*/
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if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
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bmcr = PHY_READ(sc, E1000_CR);
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PHY_WRITE(sc, E1000_CR, bmcr | E1000_CR_ISOLATE);
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return (0);
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}
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/*
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* If the interface is not up, don't do anything.
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*/
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if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
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break;
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mii_phy_setmedia(sc);
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/*
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* If autonegotiation is not enabled, we need a
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* software reset for the settings to take effect.
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*/
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if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
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bmcr = PHY_READ(sc, E1000_CR);
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PHY_WRITE(sc, E1000_CR, bmcr | E1000_CR_RESET);
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}
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break;
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case MII_TICK:
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/*
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* If we're not currently selected, just return.
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*/
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if (IFM_INST(ife->ifm_media) != sc->mii_inst)
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return (0);
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if (mii_phy_tick(sc) == EJUSTRETURN)
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return (0);
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break;
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case MII_DOWN:
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mii_phy_down(sc);
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return (0);
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}
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/* Update the media status. */
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mii_phy_status(sc);
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/* Callback if something changed. */
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mii_phy_update(sc, cmd);
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return (0);
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}
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void
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eephy_status(struct mii_softc *sc)
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{
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struct mii_data *mii = sc->mii_pdata;
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int bmcr, gsr, ssr;
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mii->mii_media_status = IFM_AVALID;
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mii->mii_media_active = IFM_ETHER;
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bmcr = PHY_READ(sc, E1000_CR);
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ssr = PHY_READ(sc, E1000_SSR);
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if (ssr & E1000_SSR_LINK)
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mii->mii_media_status |= IFM_ACTIVE;
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if (bmcr & E1000_CR_LOOPBACK)
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mii->mii_media_active |= IFM_LOOP;
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if (!(ssr & E1000_SSR_SPD_DPLX_RESOLVED)) {
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/* Erg, still trying, I guess... */
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mii->mii_media_active |= IFM_NONE;
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return;
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}
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if (sc->mii_flags & MIIF_IS_1000X) {
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mii->mii_media_active |= IFM_1000_SX;
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} else {
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if (ssr & E1000_SSR_1000MBS)
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mii->mii_media_active |= IFM_1000_T;
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else if (ssr & E1000_SSR_100MBS)
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mii->mii_media_active |= IFM_100_TX;
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else
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mii->mii_media_active |= IFM_10_T;
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}
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if (ssr & E1000_SSR_DUPLEX)
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mii->mii_media_active |= mii_phy_flowstatus(sc) | IFM_FDX;
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else
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mii->mii_media_active |= IFM_HDX;
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if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
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gsr = PHY_READ(sc, E1000_1GSR) | PHY_READ(sc, E1000_1GSR);
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if (gsr & E1000_1GSR_MS_CONFIG_RES)
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mii->mii_media_active |= IFM_ETH_MASTER;
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}
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}
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