440 lines
12 KiB
C
440 lines
12 KiB
C
/* $OpenBSD: if_rtw_cardbus.c,v 1.27 2022/04/06 18:59:28 naddy Exp $ */
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/* $NetBSD: if_rtw_cardbus.c,v 1.4 2004/12/20 21:05:34 dyoung Exp $ */
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/*-
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* Copyright (c) 2004, 2005 David Young. All rights reserved.
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*
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* Adapted for the RTL8180 by David Young.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of David Young may not be used to endorse or promote
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* products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David
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* Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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* OF SUCH DAMAGE.
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*/
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/*-
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* Copyright (c) 1999, 2000 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Cardbus front-end for the Realtek RTL8180 802.11 MAC/BBP driver.
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*
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* TBD factor with atw, tlp Cardbus front-ends?
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*/
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#include "bpfilter.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/mbuf.h>
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#include <sys/malloc.h>
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#include <sys/kernel.h>
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#include <sys/socket.h>
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#include <sys/ioctl.h>
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#include <sys/errno.h>
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#include <sys/device.h>
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#include <sys/endian.h>
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#include <net/if.h>
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#include <net/if_media.h>
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#include <netinet/in.h>
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#include <netinet/if_ether.h>
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#include <net80211/ieee80211_radiotap.h>
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#include <net80211/ieee80211_var.h>
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#if NBPFILTER > 0
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#include <net/bpf.h>
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#endif
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#include <machine/bus.h>
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#include <dev/ic/rtwreg.h>
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#include <dev/ic/rtwvar.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/cardbus/cardbusvar.h>
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/*
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* PCI configuration space registers used by the RTL8180.
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*/
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#define RTW_PCI_IOBA 0x10 /* i/o mapped base */
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#define RTW_PCI_MMBA 0x14 /* memory mapped base */
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struct rtw_cardbus_softc {
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struct rtw_softc sc_rtw; /* real RTL8180 softc */
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/* CardBus-specific goo. */
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void *sc_ih; /* interrupt handle */
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cardbus_devfunc_t sc_ct; /* our CardBus devfuncs */
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pcitag_t sc_tag; /* our CardBus tag */
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pci_chipset_tag_t sc_pc; /* PCI chipset */
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int sc_csr; /* CSR bits */
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bus_size_t sc_mapsize; /* size of the mapped bus space
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* region
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*/
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int sc_cben; /* CardBus enables */
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int sc_bar_reg; /* which BAR to use */
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pcireg_t sc_bar_val; /* value of the BAR */
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int sc_intrline; /* interrupt line */
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};
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int rtw_cardbus_match(struct device *, void *, void *);
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void rtw_cardbus_attach(struct device *, struct device *, void *);
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int rtw_cardbus_detach(struct device *, int);
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void rtw_cardbus_intr_ack(struct rtw_regs *);
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void rtw_cardbus_funcregen(struct rtw_regs *, int);
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const struct cfattach rtw_cardbus_ca = {
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sizeof(struct rtw_cardbus_softc), rtw_cardbus_match, rtw_cardbus_attach,
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rtw_cardbus_detach
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};
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void rtw_cardbus_setup(struct rtw_cardbus_softc *);
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int rtw_cardbus_enable(struct rtw_softc *);
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void rtw_cardbus_disable(struct rtw_softc *);
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void rtw_cardbus_power(struct rtw_softc *, int);
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const struct pci_matchid rtw_cardbus_devices[] = {
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{ PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8180 },
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#ifdef RTW_DEBUG
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{ PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8185 },
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{ PCI_VENDOR_BELKIN2, PCI_PRODUCT_BELKIN2_F5D7010 },
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#endif
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{ PCI_VENDOR_BELKIN2, PCI_PRODUCT_BELKIN2_F5D6020V3 },
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{ PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DWL610 }
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};
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int
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rtw_cardbus_match(struct device *parent, void *match, void *aux)
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{
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return (cardbus_matchbyid((struct cardbus_attach_args *)aux,
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rtw_cardbus_devices, nitems(rtw_cardbus_devices)));
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}
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void
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rtw_cardbus_intr_ack(struct rtw_regs *regs)
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{
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RTW_WRITE(regs, RTW_FER, RTW_FER_INTR);
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}
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void
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rtw_cardbus_funcregen(struct rtw_regs *regs, int enable)
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{
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u_int32_t reg;
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rtw_config0123_enable(regs, 1);
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reg = RTW_READ(regs, RTW_CONFIG3);
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if (enable) {
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RTW_WRITE(regs, RTW_CONFIG3, reg | RTW_CONFIG3_FUNCREGEN);
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} else {
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RTW_WRITE(regs, RTW_CONFIG3, reg & ~RTW_CONFIG3_FUNCREGEN);
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}
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rtw_config0123_enable(regs, 0);
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}
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void
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rtw_cardbus_attach(struct device *parent, struct device *self, void *aux)
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{
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struct rtw_cardbus_softc *csc = (void *)self;
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struct rtw_softc *sc = &csc->sc_rtw;
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struct rtw_regs *regs = &sc->sc_regs;
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struct cardbus_attach_args *ca = aux;
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cardbus_devfunc_t ct = ca->ca_ct;
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bus_addr_t adr;
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int rev;
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sc->sc_dmat = ca->ca_dmat;
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csc->sc_ct = ct;
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csc->sc_tag = ca->ca_tag;
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csc->sc_pc = ca->ca_pc;
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/*
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* Power management hooks.
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*/
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sc->sc_enable = rtw_cardbus_enable;
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sc->sc_disable = rtw_cardbus_disable;
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sc->sc_power = rtw_cardbus_power;
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sc->sc_intr_ack = rtw_cardbus_intr_ack;
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/* Get revision info. */
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rev = PCI_REVISION(ca->ca_class);
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RTW_DPRINTF(RTW_DEBUG_ATTACH,
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("%s: pass %d.%d signature %08x\n", sc->sc_dev.dv_xname,
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(rev >> 4) & 0xf, rev & 0xf,
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pci_conf_read(ca->ca_pc, csc->sc_tag, 0x80)));
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/*
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* Map the device.
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*/
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csc->sc_csr = PCI_COMMAND_MASTER_ENABLE;
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if (Cardbus_mapreg_map(ct, RTW_PCI_MMBA,
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PCI_MAPREG_TYPE_MEM, 0, ®s->r_bt, ®s->r_bh, &adr,
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&csc->sc_mapsize) == 0) {
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RTW_DPRINTF(RTW_DEBUG_ATTACH,
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("%s: %s mapped %lu bytes mem space\n",
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sc->sc_dev.dv_xname, __func__, (long)csc->sc_mapsize));
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csc->sc_cben = CARDBUS_MEM_ENABLE;
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csc->sc_csr |= PCI_COMMAND_MEM_ENABLE;
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csc->sc_bar_reg = RTW_PCI_MMBA;
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csc->sc_bar_val = adr | PCI_MAPREG_TYPE_MEM;
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} else if (Cardbus_mapreg_map(ct, RTW_PCI_IOBA,
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PCI_MAPREG_TYPE_IO, 0, ®s->r_bt, ®s->r_bh, &adr,
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&csc->sc_mapsize) == 0) {
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RTW_DPRINTF(RTW_DEBUG_ATTACH,
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("%s: %s mapped %lu bytes I/O space\n",
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sc->sc_dev.dv_xname, __func__, (long)csc->sc_mapsize));
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csc->sc_cben = CARDBUS_IO_ENABLE;
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csc->sc_csr |= PCI_COMMAND_IO_ENABLE;
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csc->sc_bar_reg = RTW_PCI_IOBA;
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csc->sc_bar_val = adr | PCI_MAPREG_TYPE_IO;
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} else {
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printf("%s: unable to map device registers\n",
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sc->sc_dev.dv_xname);
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return;
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}
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/*
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* Bring the chip out of powersave mode and initialize the
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* configuration registers.
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*/
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rtw_cardbus_setup(csc);
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/* Remember which interrupt line. */
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csc->sc_intrline = ca->ca_intrline;
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printf(": irq %d\n", csc->sc_intrline);
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/*
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* Finish off the attach.
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*/
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rtw_attach(sc);
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rtw_cardbus_funcregen(regs, 1);
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RTW_WRITE(regs, RTW_FEMR, RTW_FEMR_INTR);
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RTW_WRITE(regs, RTW_FER, RTW_FER_INTR);
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/*
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* Power down the socket.
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*/
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Cardbus_function_disable(csc->sc_ct);
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}
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int
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rtw_cardbus_detach(struct device *self, int flags)
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{
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struct rtw_cardbus_softc *csc = (void *)self;
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struct rtw_softc *sc = &csc->sc_rtw;
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struct rtw_regs *regs = &sc->sc_regs;
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struct cardbus_devfunc *ct = csc->sc_ct;
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int rv;
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#if defined(DIAGNOSTIC)
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if (ct == NULL)
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panic("%s: data structure lacks", sc->sc_dev.dv_xname);
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#endif
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rv = rtw_detach(sc);
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if (rv)
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return (rv);
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rtw_cardbus_funcregen(regs, 0);
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/*
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* Unhook the interrupt handler.
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*/
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if (csc->sc_ih != NULL)
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cardbus_intr_disestablish(ct->ct_cc, ct->ct_cf, csc->sc_ih);
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/*
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* Release bus space and close window.
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*/
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if (csc->sc_bar_reg != 0)
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Cardbus_mapreg_unmap(ct, csc->sc_bar_reg,
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regs->r_bt, regs->r_bh, csc->sc_mapsize);
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return (0);
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}
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int
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rtw_cardbus_enable(struct rtw_softc *sc)
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{
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struct rtw_cardbus_softc *csc = (void *) sc;
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cardbus_devfunc_t ct = csc->sc_ct;
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cardbus_chipset_tag_t cc = ct->ct_cc;
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cardbus_function_tag_t cf = ct->ct_cf;
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/*
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* Power on the socket.
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*/
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Cardbus_function_enable(ct);
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/*
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* Set up the PCI configuration registers.
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*/
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rtw_cardbus_setup(csc);
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/*
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* Map and establish the interrupt.
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*/
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csc->sc_ih = cardbus_intr_establish(cc, cf, csc->sc_intrline, IPL_NET,
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rtw_intr, sc, sc->sc_dev.dv_xname);
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if (csc->sc_ih == NULL) {
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printf("%s: unable to establish interrupt at %d\n",
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sc->sc_dev.dv_xname, csc->sc_intrline);
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Cardbus_function_disable(csc->sc_ct);
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return (1);
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}
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rtw_cardbus_funcregen(&sc->sc_regs, 1);
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RTW_WRITE(&sc->sc_regs, RTW_FEMR, RTW_FEMR_INTR);
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RTW_WRITE(&sc->sc_regs, RTW_FER, RTW_FER_INTR);
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return (0);
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}
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void
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rtw_cardbus_disable(struct rtw_softc *sc)
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{
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struct rtw_cardbus_softc *csc = (void *) sc;
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cardbus_devfunc_t ct = csc->sc_ct;
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cardbus_chipset_tag_t cc = ct->ct_cc;
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cardbus_function_tag_t cf = ct->ct_cf;
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RTW_WRITE(&sc->sc_regs, RTW_FEMR,
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RTW_READ(&sc->sc_regs, RTW_FEMR) & ~RTW_FEMR_INTR);
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rtw_cardbus_funcregen(&sc->sc_regs, 0);
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/* Unhook the interrupt handler. */
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cardbus_intr_disestablish(cc, cf, csc->sc_ih);
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csc->sc_ih = NULL;
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/* Power down the socket. */
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Cardbus_function_disable(ct);
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}
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void
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rtw_cardbus_power(struct rtw_softc *sc, int why)
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{
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RTW_DPRINTF(RTW_DEBUG_ATTACH,
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("%s: rtw_cardbus_power\n", sc->sc_dev.dv_xname));
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if (why == DVACT_RESUME)
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rtw_enable(sc);
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}
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void
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rtw_cardbus_setup(struct rtw_cardbus_softc *csc)
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{
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struct rtw_softc *sc = &csc->sc_rtw;
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cardbus_devfunc_t ct = csc->sc_ct;
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cardbus_chipset_tag_t cc = ct->ct_cc;
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pci_chipset_tag_t pc = csc->sc_pc;
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pcireg_t reg;
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int pmreg;
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if (pci_get_capability(pc, csc->sc_tag,
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PCI_CAP_PWRMGMT, &pmreg, 0)) {
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reg = pci_conf_read(pc, csc->sc_tag, pmreg + 4) & 0x03;
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#if 1 /* XXX Probably not right for CardBus. */
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if (reg == 3) {
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/*
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* The card has lost all configuration data in
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* this state, so punt.
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*/
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printf("%s: unable to wake up from power state D3\n",
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sc->sc_dev.dv_xname);
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return;
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}
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#endif
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if (reg != 0) {
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printf("%s: waking up from power state D%d\n",
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sc->sc_dev.dv_xname, reg);
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pci_conf_write(pc, csc->sc_tag,
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pmreg + 4, 0);
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}
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}
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/* Program the BAR. */
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pci_conf_write(pc, csc->sc_tag, csc->sc_bar_reg,
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csc->sc_bar_val);
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/* Make sure the right access type is on the CardBus bridge. */
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(*ct->ct_cf->cardbus_ctrl)(cc, csc->sc_cben);
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(*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE);
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/* Enable the appropriate bits in the PCI CSR. */
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reg = pci_conf_read(pc, csc->sc_tag,
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PCI_COMMAND_STATUS_REG);
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reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);
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reg |= csc->sc_csr;
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pci_conf_write(pc, csc->sc_tag, PCI_COMMAND_STATUS_REG,
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reg);
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/*
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* Make sure the latency timer is set to some reasonable
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* value.
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*/
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reg = pci_conf_read(pc, csc->sc_tag, PCI_BHLC_REG);
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if (PCI_LATTIMER(reg) < 0x20) {
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reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
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reg |= (0x20 << PCI_LATTIMER_SHIFT);
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pci_conf_write(pc, csc->sc_tag, PCI_BHLC_REG, reg);
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}
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}
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