148 lines
4 KiB
C
148 lines
4 KiB
C
/* $OpenBSD: if_dwqe_pci.c,v 1.3 2023/11/11 16:50:25 stsp Exp $ */
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/*
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* Copyright (c) 2023 Stefan Sperling <stsp@openbsd.org>
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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/*
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* Driver for the Intel Elkhart Lake ethernet controller.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcidevs.h>
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#include <net/if.h>
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#include <net/if_media.h>
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#include <netinet/in.h>
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#include <netinet/if_ether.h>
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#include <dev/mii/miivar.h>
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#include <dev/ic/dwqereg.h>
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#include <dev/ic/dwqevar.h>
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static const struct pci_matchid dwqe_pci_devices[] = {
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EHL_PSE0_RGMII_1G },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EHL_PSE0_SGMII_1G },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EHL_PSE0_SGMII_2G },
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#if 0
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EHL_PSE1_RGMII_1G },
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#endif
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EHL_PSE1_SGMII_1G },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EHL_PSE1_SGMII_2G },
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};
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struct dwqe_pci_softc {
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struct dwqe_softc sc_sc;
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pci_chipset_tag_t sc_pct;
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pcitag_t sc_pcitag;
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bus_size_t sc_mapsize;
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};
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int
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dwqe_pci_match(struct device *parent, void *cfdata, void *aux)
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{
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struct pci_attach_args *pa = aux;
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return pci_matchbyid(pa, dwqe_pci_devices, nitems(dwqe_pci_devices));
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}
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void
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dwqe_pci_attach(struct device *parent, struct device *self, void *aux)
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{
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struct pci_attach_args *pa = aux;
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struct dwqe_pci_softc *psc = (void *)self;
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struct dwqe_softc *sc = &psc->sc_sc;
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pci_intr_handle_t ih;
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pcireg_t memtype;
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int err;
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const char *intrstr;
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psc->sc_pct = pa->pa_pc;
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psc->sc_pcitag = pa->pa_tag;
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sc->sc_dmat = pa->pa_dmat;
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memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, PCI_MAPREG_START);
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err = pci_mapreg_map(pa, PCI_MAPREG_START, memtype, 0,
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&sc->sc_iot, &sc->sc_ioh, NULL, &psc->sc_mapsize, 0);
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if (err) {
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printf("%s: can't map mem space\n", DEVNAME(sc));
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return;
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}
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if (pci_intr_map_msi(pa, &ih) && pci_intr_map(pa, &ih)) {
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printf("%s: can't map interrupt\n", DEVNAME(sc));
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return;
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}
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intrstr = pci_intr_string(psc->sc_pct, ih);
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sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_NET | IPL_MPSAFE,
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dwqe_intr, psc, sc->sc_dev.dv_xname);
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if (sc->sc_ih == NULL) {
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printf(": can't establish interrupt");
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if (intrstr != NULL)
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printf(" at %s", intrstr);
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printf("\n");
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return;
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}
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switch (PCI_PRODUCT(pa->pa_id)) {
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case PCI_PRODUCT_INTEL_EHL_PSE0_RGMII_1G:
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sc->sc_phy_mode = DWQE_PHY_MODE_RGMII_ID;
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sc->sc_clk = GMAC_MAC_MDIO_ADDR_CR_250_300;
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sc->sc_clkrate = 200000000;
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break;
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case PCI_PRODUCT_INTEL_EHL_PSE0_SGMII_1G:
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case PCI_PRODUCT_INTEL_EHL_PSE0_SGMII_2G:
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case PCI_PRODUCT_INTEL_EHL_PSE1_SGMII_1G:
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case PCI_PRODUCT_INTEL_EHL_PSE1_SGMII_2G:
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sc->sc_phy_mode = DWQE_PHY_MODE_SGMII;
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sc->sc_clk = GMAC_MAC_MDIO_ADDR_CR_250_300;
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sc->sc_clkrate = 200000000;
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break;
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default:
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sc->sc_phy_mode = DWQE_PHY_MODE_UNKNOWN;
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break;
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}
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sc->sc_phyloc = MII_PHY_ANY;
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sc->sc_8xpbl = 1;
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sc->sc_txpbl = 32;
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sc->sc_rxpbl = 32;
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sc->sc_txfifo_size = 32768;
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sc->sc_rxfifo_size = 32768;
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sc->sc_axi_config = 1;
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sc->sc_wr_osr_lmt = 1;
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sc->sc_rd_osr_lmt = 1;
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sc->sc_blen[0] = 4;
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sc->sc_blen[1] = 8;
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sc->sc_blen[2] = 16;
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dwqe_lladdr_read(sc, sc->sc_lladdr);
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dwqe_reset(sc);
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dwqe_attach(sc);
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}
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const struct cfattach dwqe_pci_ca = {
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sizeof(struct dwqe_softc), dwqe_pci_match, dwqe_pci_attach
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};
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