771 lines
22 KiB
C
771 lines
22 KiB
C
/* $OpenBSD: gdt_pci.c,v 1.28 2024/05/24 06:02:53 jsg Exp $ */
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/*
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* Copyright (c) 1999, 2000 Niklas Hallqvist. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* This driver would not have written if it was not for the hardware donations
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* from both ICP-Vortex and Öko.neT. I want to thank them for their support.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/queue.h>
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#include <machine/bus.h>
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#include <scsi/scsi_all.h>
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#include <scsi/scsiconf.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/ic/gdtreg.h>
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#include <dev/ic/gdtvar.h>
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/* Product numbers for Fibre-Channel are greater than or equal to 0x200 */
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#define GDT_PCI_PRODUCT_FC 0x200
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#define GDT_DEVICE_ID_MIN 0x100
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#define GDT_DEVICE_ID_MAX 0x2ff
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#define GDT_DEVICE_ID_NEWRX 0x300
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#define GDT_DEVICE_ID_NEWRX2 0x301
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/* Mapping registers for various areas */
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#define GDT_PCI_DPMEM 0x10
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#define GDT_PCINEW_IOMEM 0x10
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#define GDT_PCINEW_IO 0x14
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#define GDT_PCINEW_DPMEM 0x18
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/* PCI SRAM structure */
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#define GDT_MAGIC 0x00 /* u_int32_t, controller ID from BIOS */
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#define GDT_NEED_DEINIT 0x04 /* u_int16_t, switch between BIOS/driver */
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#define GDT_SWITCH_SUPPORT 0x06 /* u_int8_t, see GDT_NEED_DEINIT */
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#define GDT_OS_USED 0x10 /* u_int8_t [16], OS code per service */
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#define GDT_FW_MAGIC 0x3c /* u_int8_t, controller ID from firmware */
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#define GDT_SRAM_SZ 0x40
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/* DPRAM PCI controllers */
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#define GDT_DPR_IF 0x00 /* interface area */
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#define GDT_6SR (0xff0 - GDT_SRAM_SZ)
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#define GDT_SEMA1 0xff1 /* volatile u_int8_t, command semaphore */
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#define GDT_IRQEN 0xff5 /* u_int8_t, board interrupts enable */
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#define GDT_EVENT 0xff8 /* u_int8_t, release event */
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#define GDT_IRQDEL 0xffc /* u_int8_t, acknowledge board interrupt */
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#define GDT_DPRAM_SZ 0x1000
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/* PLX register structure (new PCI controllers) */
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#define GDT_CFG_REG 0x00 /* u_int8_t, DPRAM cfg. (2: < 1MB, 0: any) */
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#define GDT_SEMA0_REG 0x40 /* volatile u_int8_t, command semaphore */
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#define GDT_SEMA1_REG 0x41 /* volatile u_int8_t, status semaphore */
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#define GDT_PLX_STATUS 0x44 /* volatile u_int16_t, command status */
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#define GDT_PLX_SERVICE 0x46 /* u_int16_t, service */
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#define GDT_PLX_INFO 0x48 /* u_int32_t [2], additional info */
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#define GDT_LDOOR_REG 0x60 /* u_int8_t, PCI to local doorbell */
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#define GDT_EDOOR_REG 0x64 /* volatile u_int8_t, local to PCI doorbell */
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#define GDT_CONTROL0 0x68 /* u_int8_t, control0 register (unused) */
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#define GDT_CONTROL1 0x69 /* u_int8_t, board interrupts enable */
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#define GDT_PLX_SZ 0x80
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/* DPRAM new PCI controllers */
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#define GDT_IC 0x00 /* interface */
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#define GDT_PCINEW_6SR (0x4000 - GDT_SRAM_SZ)
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/* SRAM structure */
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#define GDT_PCINEW_SZ 0x4000
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/* i960 register structure (PCI MPR controllers) */
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#define GDT_MPR_SEMA0 0x10 /* volatile u_int8_t, command semaphore */
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#define GDT_MPR_SEMA1 0x12 /* volatile u_int8_t, status semaphore */
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#define GDT_MPR_STATUS 0x14 /* volatile u_int16_t, command status */
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#define GDT_MPR_SERVICE 0x16 /* u_int16_t, service */
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#define GDT_MPR_INFO 0x18 /* u_int32_t [2], additional info */
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#define GDT_MPR_LDOOR 0x20 /* u_int8_t, PCI to local doorbell */
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#define GDT_MPR_EDOOR 0x2c /* volatile u_int8_t, locl to PCI doorbell */
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#define GDT_EDOOR_EN 0x34 /* u_int8_t, board interrupts enable */
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#define GDT_I960_SZ 0x1000
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/* DPRAM PCI MPR controllers */
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#define GDT_I960R 0x00 /* 4KB i960 registers */
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#define GDT_MPR_IC GDT_I960_SZ
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/* interface area */
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#define GDT_MPR_6SR (GDT_I960_SZ + 0x3000 - GDT_SRAM_SZ)
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/* SRAM structure */
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#define GDT_MPR_SZ 0x4000
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int gdt_pci_probe(struct device *, void *, void *);
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void gdt_pci_attach(struct device *, struct device *, void *);
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void gdt_pci_enable_intr(struct gdt_softc *);
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void gdt_pci_copy_cmd(struct gdt_softc *, struct gdt_ccb *);
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u_int8_t gdt_pci_get_status(struct gdt_softc *);
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void gdt_pci_intr(struct gdt_softc *, struct gdt_intr_ctx *);
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void gdt_pci_release_event(struct gdt_softc *, struct gdt_ccb *);
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void gdt_pci_set_sema0(struct gdt_softc *);
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int gdt_pci_test_busy(struct gdt_softc *);
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void gdt_pcinew_copy_cmd(struct gdt_softc *, struct gdt_ccb *);
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u_int8_t gdt_pcinew_get_status(struct gdt_softc *);
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void gdt_pcinew_intr(struct gdt_softc *, struct gdt_intr_ctx *);
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void gdt_pcinew_release_event(struct gdt_softc *, struct gdt_ccb *);
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void gdt_pcinew_set_sema0(struct gdt_softc *);
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int gdt_pcinew_test_busy(struct gdt_softc *);
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void gdt_mpr_copy_cmd(struct gdt_softc *, struct gdt_ccb *);
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u_int8_t gdt_mpr_get_status(struct gdt_softc *);
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void gdt_mpr_intr(struct gdt_softc *, struct gdt_intr_ctx *);
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void gdt_mpr_release_event(struct gdt_softc *, struct gdt_ccb *);
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void gdt_mpr_set_sema0(struct gdt_softc *);
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int gdt_mpr_test_busy(struct gdt_softc *);
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const struct cfattach gdt_pci_ca = {
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sizeof (struct gdt_softc), gdt_pci_probe, gdt_pci_attach
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};
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int
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gdt_pci_probe(struct device *parent, void *match, void *aux)
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{
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struct pci_attach_args *pa = aux;
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if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VORTEX &&
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((PCI_PRODUCT(pa->pa_id) >= GDT_DEVICE_ID_MIN &&
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PCI_PRODUCT(pa->pa_id) <= GDT_DEVICE_ID_MAX) ||
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PCI_PRODUCT(pa->pa_id) == GDT_DEVICE_ID_NEWRX ||
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PCI_PRODUCT(pa->pa_id) == GDT_DEVICE_ID_NEWRX2))
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return (1);
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if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL &&
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(PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_GDT_RAID1 ||
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PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_GDT_RAID2))
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return (1);
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return (0);
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}
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void
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gdt_pci_attach(struct device *parent, struct device *self, void *aux)
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{
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struct pci_attach_args *pa = aux;
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struct gdt_softc *sc = (void *)self;
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bus_space_tag_t dpmemt, iomemt, iot;
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bus_space_handle_t dpmemh, iomemh, ioh;
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bus_addr_t dpmembase, iomembase, iobase;
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bus_size_t dpmemsize, iomemsize, iosize;
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u_int16_t prod;
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u_int32_t status = 0;
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#define DPMEM_MAPPED 1
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#define IOMEM_MAPPED 2
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#define IO_MAPPED 4
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#define INTR_ESTABLISHED 8
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int retries;
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u_int8_t protocol;
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pci_intr_handle_t ih;
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const char *intrstr;
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printf(": ");
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sc->sc_class = 0;
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if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VORTEX) {
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prod = PCI_PRODUCT(pa->pa_id);
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switch (prod) {
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case PCI_PRODUCT_VORTEX_GDT_60X0:
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case PCI_PRODUCT_VORTEX_GDT_6000B:
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sc->sc_class = GDT_PCI;
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break;
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case PCI_PRODUCT_VORTEX_GDT_6X10:
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case PCI_PRODUCT_VORTEX_GDT_6X20:
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case PCI_PRODUCT_VORTEX_GDT_6530:
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case PCI_PRODUCT_VORTEX_GDT_6550:
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case PCI_PRODUCT_VORTEX_GDT_6X17:
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case PCI_PRODUCT_VORTEX_GDT_6X27:
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case PCI_PRODUCT_VORTEX_GDT_6537:
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case PCI_PRODUCT_VORTEX_GDT_6557:
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case PCI_PRODUCT_VORTEX_GDT_6X15:
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case PCI_PRODUCT_VORTEX_GDT_6X25:
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case PCI_PRODUCT_VORTEX_GDT_6535:
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case PCI_PRODUCT_VORTEX_GDT_6555:
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sc->sc_class = GDT_PCINEW;
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break;
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case PCI_PRODUCT_VORTEX_GDT_6X17RP:
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case PCI_PRODUCT_VORTEX_GDT_6X27RP:
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case PCI_PRODUCT_VORTEX_GDT_6537RP:
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case PCI_PRODUCT_VORTEX_GDT_6557RP:
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case PCI_PRODUCT_VORTEX_GDT_6X11RP:
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case PCI_PRODUCT_VORTEX_GDT_6X21RP:
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case PCI_PRODUCT_VORTEX_GDT_6X17RD:
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case PCI_PRODUCT_VORTEX_GDT_6X27RD:
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case PCI_PRODUCT_VORTEX_GDT_6537RD:
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case PCI_PRODUCT_VORTEX_GDT_6557RD:
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case PCI_PRODUCT_VORTEX_GDT_6X11RD:
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case PCI_PRODUCT_VORTEX_GDT_6X21RD:
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case PCI_PRODUCT_VORTEX_GDT_6X18RD:
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case PCI_PRODUCT_VORTEX_GDT_6X28RD:
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case PCI_PRODUCT_VORTEX_GDT_6X38RD:
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case PCI_PRODUCT_VORTEX_GDT_6X58RD:
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case PCI_PRODUCT_VORTEX_GDT_6518RS:
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case PCI_PRODUCT_VORTEX_GDT_7X18RN:
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case PCI_PRODUCT_VORTEX_GDT_7X28RN:
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case PCI_PRODUCT_VORTEX_GDT_7X38RN:
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case PCI_PRODUCT_VORTEX_GDT_7X58RN:
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case PCI_PRODUCT_VORTEX_GDT_6X19RD:
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case PCI_PRODUCT_VORTEX_GDT_6X29RD:
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case PCI_PRODUCT_VORTEX_GDT_7X19RN:
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case PCI_PRODUCT_VORTEX_GDT_7X29RN:
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case PCI_PRODUCT_VORTEX_GDT_7X43RN:
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sc->sc_class = GDT_MPR;
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}
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/* If we don't recognize it, determine class heuristically. */
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if (sc->sc_class == 0)
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sc->sc_class = prod < 0x100 ? GDT_PCINEW : GDT_MPR;
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if (prod >= GDT_PCI_PRODUCT_FC)
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sc->sc_class |= GDT_FC;
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} else if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) {
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sc->sc_class = GDT_MPR;
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}
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if (pci_mapreg_map(pa,
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GDT_CLASS(sc) == GDT_PCINEW ? GDT_PCINEW_DPMEM : GDT_PCI_DPMEM,
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PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, &dpmemt,
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&dpmemh, &dpmembase, &dpmemsize, 0)) {
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if (pci_mapreg_map(pa,
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GDT_CLASS(sc) == GDT_PCINEW ? GDT_PCINEW_DPMEM :
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GDT_PCI_DPMEM,
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PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M, 0,
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&dpmemt,&dpmemh, &dpmembase, &dpmemsize, 0)) {
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printf("cannot map DPMEM\n");
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goto bail_out;
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}
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}
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status |= DPMEM_MAPPED;
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sc->sc_dpmemt = dpmemt;
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sc->sc_dpmemh = dpmemh;
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sc->sc_dpmembase = dpmembase;
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sc->sc_dmat = pa->pa_dmat;
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/*
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* The GDT_PCINEW series also has two other regions to map.
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*/
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if (GDT_CLASS(sc) == GDT_PCINEW) {
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if (pci_mapreg_map(pa, GDT_PCINEW_IOMEM, PCI_MAPREG_TYPE_MEM,
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0, &iomemt, &iomemh, &iomembase, &iomemsize, 0)) {
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printf("can't map memory mapped i/o ports\n");
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goto bail_out;
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}
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status |= IOMEM_MAPPED;
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if (pci_mapreg_map(pa, GDT_PCINEW_IO, PCI_MAPREG_TYPE_IO, 0,
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&iot, &ioh, &iobase, &iosize, 0)) {
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printf("can't map i/o space\n");
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goto bail_out;
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}
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status |= IO_MAPPED;
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sc->sc_iot = iot;
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sc->sc_ioh = ioh;
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sc->sc_iobase = iobase;
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}
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switch (GDT_CLASS(sc)) {
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case GDT_PCI:
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bus_space_set_region_4(dpmemt, dpmemh, 0, 0,
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GDT_DPR_IF_SZ >> 2);
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if (bus_space_read_1(dpmemt, dpmemh, 0) != 0) {
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printf("can't write to DPMEM\n");
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goto bail_out;
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}
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#if 0
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/* disable board interrupts, deinit services */
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gdth_writeb(0xff, &dp6_ptr->io.irqdel);
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gdth_writeb(0x00, &dp6_ptr->io.irqen);
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gdth_writeb(0x00, &dp6_ptr->u.ic.S_Status);
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gdth_writeb(0x00, &dp6_ptr->u.ic.Cmd_Index);
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gdth_writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]);
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gdth_writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx);
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gdth_writeb(0, &dp6_ptr->io.event);
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retries = INIT_RETRIES;
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gdth_delay(20);
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while (gdth_readb(&dp6_ptr->u.ic.S_Status) != 0xff) {
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if (--retries == 0) {
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printk("initialization error (DEINIT failed)\n");
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gdth_munmap(ha->brd);
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return 0;
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}
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gdth_delay(1);
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}
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prot_ver = (unchar)gdth_readl(&dp6_ptr->u.ic.S_Info[0]);
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gdth_writeb(0, &dp6_ptr->u.ic.S_Status);
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gdth_writeb(0xff, &dp6_ptr->io.irqdel);
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if (prot_ver != PROTOCOL_VERSION) {
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printk("illegal protocol version\n");
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gdth_munmap(ha->brd);
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return 0;
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}
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ha->type = GDT_PCI;
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ha->ic_all_size = sizeof(dp6_ptr->u);
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/* special command to controller BIOS */
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gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[0]);
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gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[1]);
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gdth_writel(0x01, &dp6_ptr->u.ic.S_Info[2]);
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gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[3]);
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gdth_writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx);
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gdth_writeb(0, &dp6_ptr->io.event);
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retries = INIT_RETRIES;
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gdth_delay(20);
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while (gdth_readb(&dp6_ptr->u.ic.S_Status) != 0xfe) {
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if (--retries == 0) {
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printk("initialization error\n");
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gdth_munmap(ha->brd);
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return 0;
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}
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gdth_delay(1);
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}
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gdth_writeb(0, &dp6_ptr->u.ic.S_Status);
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gdth_writeb(0xff, &dp6_ptr->io.irqdel);
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#endif
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sc->sc_ic_all_size = GDT_DPRAM_SZ;
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sc->sc_copy_cmd = gdt_pci_copy_cmd;
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sc->sc_get_status = gdt_pci_get_status;
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sc->sc_intr = gdt_pci_intr;
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sc->sc_release_event = gdt_pci_release_event;
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sc->sc_set_sema0 = gdt_pci_set_sema0;
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sc->sc_test_busy = gdt_pci_test_busy;
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break;
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case GDT_PCINEW:
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bus_space_set_region_4(dpmemt, dpmemh, 0, 0,
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GDT_DPR_IF_SZ >> 2);
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if (bus_space_read_1(dpmemt, dpmemh, 0) != 0) {
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printf("cannot write to DPMEM\n");
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goto bail_out;
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}
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#if 0
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/* disable board interrupts, deinit services */
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outb(0x00,PTR2USHORT(&ha->plx->control1));
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outb(0xff,PTR2USHORT(&ha->plx->edoor_reg));
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gdth_writeb(0x00, &dp6c_ptr->u.ic.S_Status);
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gdth_writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index);
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gdth_writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]);
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gdth_writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx);
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outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
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retries = INIT_RETRIES;
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gdth_delay(20);
|
|
while (gdth_readb(&dp6c_ptr->u.ic.S_Status) != 0xff) {
|
|
if (--retries == 0) {
|
|
printk("initialization error (DEINIT failed)\n");
|
|
gdth_munmap(ha->brd);
|
|
return 0;
|
|
}
|
|
gdth_delay(1);
|
|
}
|
|
prot_ver = (unchar)gdth_readl(&dp6c_ptr->u.ic.S_Info[0]);
|
|
gdth_writeb(0, &dp6c_ptr->u.ic.Status);
|
|
if (prot_ver != PROTOCOL_VERSION) {
|
|
printk("illegal protocol version\n");
|
|
gdth_munmap(ha->brd);
|
|
return 0;
|
|
}
|
|
|
|
ha->type = GDT_PCINEW;
|
|
ha->ic_all_size = sizeof(dp6c_ptr->u);
|
|
|
|
/* special command to controller BIOS */
|
|
gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[0]);
|
|
gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[1]);
|
|
gdth_writel(0x01, &dp6c_ptr->u.ic.S_Info[2]);
|
|
gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[3]);
|
|
gdth_writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx);
|
|
|
|
outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
|
|
|
|
retries = INIT_RETRIES;
|
|
gdth_delay(20);
|
|
while (gdth_readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) {
|
|
if (--retries == 0) {
|
|
printk("initialization error\n");
|
|
gdth_munmap(ha->brd);
|
|
return 0;
|
|
}
|
|
gdth_delay(1);
|
|
}
|
|
gdth_writeb(0, &dp6c_ptr->u.ic.S_Status);
|
|
#endif
|
|
|
|
sc->sc_ic_all_size = GDT_PCINEW_SZ;
|
|
|
|
sc->sc_copy_cmd = gdt_pcinew_copy_cmd;
|
|
sc->sc_get_status = gdt_pcinew_get_status;
|
|
sc->sc_intr = gdt_pcinew_intr;
|
|
sc->sc_release_event = gdt_pcinew_release_event;
|
|
sc->sc_set_sema0 = gdt_pcinew_set_sema0;
|
|
sc->sc_test_busy = gdt_pcinew_test_busy;
|
|
|
|
break;
|
|
|
|
case GDT_MPR:
|
|
bus_space_write_4(dpmemt, dpmemh, GDT_MPR_IC, GDT_MPR_MAGIC);
|
|
if (bus_space_read_4(dpmemt, dpmemh, GDT_MPR_IC) !=
|
|
GDT_MPR_MAGIC) {
|
|
printf("cannot access DPMEM at 0x%lx (shadowed?)\n",
|
|
dpmembase);
|
|
goto bail_out;
|
|
}
|
|
|
|
/*
|
|
* XXX Here the Linux driver has a weird remapping logic I
|
|
* don't understand. My controller does not need it, and I
|
|
* cannot see what purpose it serves, therefore I did not
|
|
* do anything similar.
|
|
*/
|
|
|
|
bus_space_set_region_4(dpmemt, dpmemh, GDT_I960_SZ, 0,
|
|
GDT_DPR_IF_SZ >> 2);
|
|
|
|
/* Disable everything */
|
|
bus_space_write_1(dpmemt, dpmemh, GDT_EDOOR_EN,
|
|
bus_space_read_1(dpmemt, dpmemh, GDT_EDOOR_EN) | 4);
|
|
bus_space_write_1(dpmemt, dpmemh, GDT_MPR_EDOOR, 0xff);
|
|
bus_space_write_1(dpmemt, dpmemh, GDT_MPR_IC + GDT_S_STATUS,
|
|
0);
|
|
bus_space_write_1(dpmemt, dpmemh, GDT_MPR_IC + GDT_CMD_INDEX,
|
|
0);
|
|
|
|
bus_space_write_4(dpmemt, dpmemh, GDT_MPR_IC + GDT_S_INFO,
|
|
dpmembase);
|
|
bus_space_write_1(dpmemt, dpmemh, GDT_MPR_IC + GDT_S_CMD_INDX,
|
|
0xff);
|
|
bus_space_write_1(dpmemt, dpmemh, GDT_MPR_LDOOR, 1);
|
|
|
|
DELAY(20);
|
|
retries = GDT_RETRIES;
|
|
while (bus_space_read_1(dpmemt, dpmemh,
|
|
GDT_MPR_IC + GDT_S_STATUS) != 0xff) {
|
|
if (--retries == 0) {
|
|
printf("DEINIT failed (status 0x%x)\n",
|
|
bus_space_read_1(dpmemt, dpmemh,
|
|
GDT_MPR_IC + GDT_S_STATUS));
|
|
goto bail_out;
|
|
}
|
|
DELAY(1);
|
|
}
|
|
|
|
protocol = (u_int8_t)bus_space_read_4(dpmemt, dpmemh,
|
|
GDT_MPR_IC + GDT_S_INFO);
|
|
bus_space_write_1(dpmemt, dpmemh, GDT_MPR_IC + GDT_S_STATUS,
|
|
0);
|
|
if (protocol != GDT_PROTOCOL_VERSION) {
|
|
printf("unsupported protocol %d\n", protocol);
|
|
goto bail_out;
|
|
}
|
|
|
|
/* special commnd to controller BIOS */
|
|
bus_space_write_4(dpmemt, dpmemh, GDT_MPR_IC + GDT_S_INFO, 0);
|
|
bus_space_write_4(dpmemt, dpmemh,
|
|
GDT_MPR_IC + GDT_S_INFO + sizeof (u_int32_t), 0);
|
|
bus_space_write_4(dpmemt, dpmemh,
|
|
GDT_MPR_IC + GDT_S_INFO + 2 * sizeof (u_int32_t), 1);
|
|
bus_space_write_4(dpmemt, dpmemh,
|
|
GDT_MPR_IC + GDT_S_INFO + 3 * sizeof (u_int32_t), 0);
|
|
bus_space_write_1(dpmemt, dpmemh, GDT_MPR_IC + GDT_S_CMD_INDX,
|
|
0xfe);
|
|
bus_space_write_1(dpmemt, dpmemh, GDT_MPR_LDOOR, 1);
|
|
|
|
DELAY(20);
|
|
retries = GDT_RETRIES;
|
|
while (bus_space_read_1(dpmemt, dpmemh,
|
|
GDT_MPR_IC + GDT_S_STATUS) != 0xfe) {
|
|
if (--retries == 0) {
|
|
printf("initialization error\n");
|
|
goto bail_out;
|
|
}
|
|
DELAY(1);
|
|
}
|
|
|
|
bus_space_write_1(dpmemt, dpmemh, GDT_MPR_IC + GDT_S_STATUS,
|
|
0);
|
|
|
|
sc->sc_ic_all_size = GDT_MPR_SZ;
|
|
|
|
sc->sc_copy_cmd = gdt_mpr_copy_cmd;
|
|
sc->sc_get_status = gdt_mpr_get_status;
|
|
sc->sc_intr = gdt_mpr_intr;
|
|
sc->sc_release_event = gdt_mpr_release_event;
|
|
sc->sc_set_sema0 = gdt_mpr_set_sema0;
|
|
sc->sc_test_busy = gdt_mpr_test_busy;
|
|
}
|
|
|
|
if (pci_intr_map(pa, &ih)) {
|
|
printf("couldn't map interrupt\n");
|
|
goto bail_out;
|
|
}
|
|
intrstr = pci_intr_string(pa->pa_pc, ih);
|
|
sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, gdt_intr, sc,
|
|
sc->sc_dev.dv_xname);
|
|
if (sc->sc_ih == NULL) {
|
|
printf("couldn't establish interrupt");
|
|
if (intrstr != NULL)
|
|
printf(" at %s", intrstr);
|
|
printf("\n");
|
|
goto bail_out;
|
|
}
|
|
status |= INTR_ESTABLISHED;
|
|
if (intrstr != NULL)
|
|
printf("%s ", intrstr);
|
|
|
|
if (gdt_attach(sc))
|
|
goto bail_out;
|
|
|
|
gdt_pci_enable_intr(sc);
|
|
|
|
return;
|
|
|
|
bail_out:
|
|
if (status & DPMEM_MAPPED)
|
|
bus_space_unmap(dpmemt, dpmemh, dpmemsize);
|
|
if (status & IOMEM_MAPPED)
|
|
bus_space_unmap(iomemt, iomemh, iomembase);
|
|
if (status & IO_MAPPED)
|
|
bus_space_unmap(iot, ioh, iosize);
|
|
if (status & INTR_ESTABLISHED)
|
|
pci_intr_disestablish(pa->pa_pc, sc->sc_ih);
|
|
return;
|
|
}
|
|
|
|
/* Enable interrupts */
|
|
void
|
|
gdt_pci_enable_intr(struct gdt_softc *sc)
|
|
{
|
|
GDT_DPRINTF(GDT_D_INTR, ("gdt_pci_enable_intr(%p) ", sc));
|
|
|
|
switch(GDT_CLASS(sc)) {
|
|
case GDT_PCI:
|
|
bus_space_write_1(sc->sc_dpmemt, sc->sc_dpmemh, GDT_IRQDEL,
|
|
1);
|
|
bus_space_write_1(sc->sc_dpmemt, sc->sc_dpmemh,
|
|
GDT_CMD_INDEX, 0);
|
|
bus_space_write_1(sc->sc_dpmemt, sc->sc_dpmemh, GDT_IRQEN,
|
|
1);
|
|
break;
|
|
|
|
case GDT_PCINEW:
|
|
bus_space_write_1(sc->sc_iot, sc->sc_ioh, GDT_EDOOR_REG,
|
|
0xff);
|
|
bus_space_write_1(sc->sc_iot, sc->sc_ioh, GDT_CONTROL1, 3);
|
|
break;
|
|
|
|
case GDT_MPR:
|
|
bus_space_write_1(sc->sc_dpmemt, sc->sc_dpmemh,
|
|
GDT_MPR_EDOOR, 0xff);
|
|
bus_space_write_1(sc->sc_dpmemt, sc->sc_dpmemh, GDT_EDOOR_EN,
|
|
bus_space_read_1(sc->sc_dpmemt, sc->sc_dpmemh,
|
|
GDT_EDOOR_EN) & ~4);
|
|
break;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* "old" PCI controller-specific functions
|
|
*/
|
|
|
|
void
|
|
gdt_pci_copy_cmd(struct gdt_softc *sc, struct gdt_ccb *ccb)
|
|
{
|
|
/* XXX Not yet implemented */
|
|
}
|
|
|
|
u_int8_t
|
|
gdt_pci_get_status(struct gdt_softc *sc)
|
|
{
|
|
/* XXX Not yet implemented */
|
|
return (0);
|
|
}
|
|
|
|
void
|
|
gdt_pci_intr(struct gdt_softc *sc, struct gdt_intr_ctx *ctx)
|
|
{
|
|
/* XXX Not yet implemented */
|
|
}
|
|
|
|
void
|
|
gdt_pci_release_event(struct gdt_softc *sc, struct gdt_ccb *ccb)
|
|
{
|
|
/* XXX Not yet implemented */
|
|
}
|
|
|
|
void
|
|
gdt_pci_set_sema0(struct gdt_softc *sc)
|
|
{
|
|
bus_space_write_1(sc->sc_dpmemt, sc->sc_dpmemh, GDT_SEMA0, 1);
|
|
}
|
|
|
|
int
|
|
gdt_pci_test_busy(struct gdt_softc *sc)
|
|
{
|
|
/* XXX Not yet implemented */
|
|
return (0);
|
|
}
|
|
|
|
/*
|
|
* "new" PCI controller-specific functions
|
|
*/
|
|
|
|
void
|
|
gdt_pcinew_copy_cmd(struct gdt_softc *sc, struct gdt_ccb *ccb)
|
|
{
|
|
/* XXX Not yet implemented */
|
|
}
|
|
|
|
u_int8_t
|
|
gdt_pcinew_get_status(struct gdt_softc *sc)
|
|
{
|
|
/* XXX Not yet implemented */
|
|
return (0);
|
|
}
|
|
|
|
void
|
|
gdt_pcinew_intr(struct gdt_softc *sc, struct gdt_intr_ctx *ctx)
|
|
{
|
|
/* XXX Not yet implemented */
|
|
}
|
|
|
|
void
|
|
gdt_pcinew_release_event(struct gdt_softc *sc, struct gdt_ccb *ccb)
|
|
{
|
|
/* XXX Not yet implemented */
|
|
}
|
|
|
|
void
|
|
gdt_pcinew_set_sema0(struct gdt_softc *sc)
|
|
{
|
|
bus_space_write_1(sc->sc_iot, sc->sc_ioh, GDT_SEMA0_REG, 1);
|
|
}
|
|
|
|
int
|
|
gdt_pcinew_test_busy(struct gdt_softc *sc)
|
|
{
|
|
/* XXX Not yet implemented */
|
|
return (0);
|
|
}
|
|
|
|
/*
|
|
* MPR PCI controller-specific functions
|
|
*/
|
|
|
|
void
|
|
gdt_mpr_copy_cmd(struct gdt_softc *sc, struct gdt_ccb *ccb)
|
|
{
|
|
u_int16_t cp_count = roundup(sc->sc_cmd_len, sizeof (u_int32_t));
|
|
u_int16_t dp_offset = sc->sc_cmd_off;
|
|
u_int16_t cmd_no = sc->sc_cmd_cnt++;
|
|
|
|
GDT_DPRINTF(GDT_D_CMD, ("gdt_mpr_copy_cmd(%p) ", sc));
|
|
|
|
sc->sc_cmd_off += cp_count;
|
|
|
|
bus_space_write_2(sc->sc_dpmemt, sc->sc_dpmemh,
|
|
GDT_MPR_IC + GDT_COMM_QUEUE + cmd_no * GDT_COMM_Q_SZ + GDT_OFFSET,
|
|
GDT_DPMEM_COMMAND_OFFSET + dp_offset);
|
|
bus_space_write_2(sc->sc_dpmemt, sc->sc_dpmemh,
|
|
GDT_MPR_IC + GDT_COMM_QUEUE + cmd_no * GDT_COMM_Q_SZ + GDT_SERV_ID,
|
|
ccb->gc_service);
|
|
bus_space_write_raw_region_4(sc->sc_dpmemt, sc->sc_dpmemh,
|
|
GDT_MPR_IC + GDT_DPR_CMD + dp_offset, sc->sc_cmd, cp_count);
|
|
}
|
|
|
|
u_int8_t
|
|
gdt_mpr_get_status(struct gdt_softc *sc)
|
|
{
|
|
GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_get_status(%p) ", sc));
|
|
|
|
return bus_space_read_1(sc->sc_dpmemt, sc->sc_dpmemh, GDT_MPR_EDOOR);
|
|
}
|
|
|
|
void
|
|
gdt_mpr_intr(struct gdt_softc *sc, struct gdt_intr_ctx *ctx)
|
|
{
|
|
GDT_DPRINTF(GDT_D_INTR, ("gdt_mpr_intr(%p) ", sc));
|
|
|
|
if (ctx->istatus & 0x80) { /* error flag */
|
|
ctx->istatus &= ~0x80;
|
|
ctx->cmd_status = bus_space_read_2(sc->sc_dpmemt,
|
|
sc->sc_dpmemh, GDT_MPR_STATUS);
|
|
if (ctx->istatus == GDT_ASYNCINDEX) {
|
|
ctx->service = bus_space_read_2(sc->sc_dpmemt,
|
|
sc->sc_dpmemh, GDT_MPR_SERVICE);
|
|
ctx->info2 = bus_space_read_4(sc->sc_dpmemt,
|
|
sc->sc_dpmemh, GDT_MPR_INFO + sizeof (u_int32_t));
|
|
}
|
|
} else /* no error */
|
|
ctx->cmd_status = GDT_S_OK;
|
|
|
|
ctx->info =
|
|
bus_space_read_4(sc->sc_dpmemt, sc->sc_dpmemh, GDT_MPR_INFO);
|
|
|
|
if (gdt_polling) /* init. -> more info */
|
|
ctx->info2 = bus_space_read_4(sc->sc_dpmemt, sc->sc_dpmemh,
|
|
GDT_MPR_INFO + sizeof (u_int32_t));
|
|
bus_space_write_1(sc->sc_dpmemt, sc->sc_dpmemh, GDT_MPR_EDOOR, 0xff);
|
|
bus_space_write_1(sc->sc_dpmemt, sc->sc_dpmemh, GDT_MPR_SEMA1, 0);
|
|
}
|
|
|
|
void
|
|
gdt_mpr_release_event(struct gdt_softc *sc, struct gdt_ccb *ccb)
|
|
{
|
|
GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_release_event(%p) ", sc));
|
|
|
|
if (gdt_dec16(sc->sc_cmd + GDT_CMD_OPCODE) == GDT_INIT)
|
|
ccb->gc_service |= 0x80;
|
|
bus_space_write_1(sc->sc_dpmemt, sc->sc_dpmemh, GDT_MPR_LDOOR, 1);
|
|
}
|
|
|
|
void
|
|
gdt_mpr_set_sema0(struct gdt_softc *sc)
|
|
{
|
|
GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_set_sema0(%p) ", sc));
|
|
|
|
bus_space_write_1(sc->sc_dpmemt, sc->sc_dpmemh, GDT_MPR_SEMA0, 1);
|
|
}
|
|
|
|
int
|
|
gdt_mpr_test_busy(struct gdt_softc *sc)
|
|
{
|
|
GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_test_busy(%p) ", sc));
|
|
|
|
return (bus_space_read_1(sc->sc_dpmemt, sc->sc_dpmemh,
|
|
GDT_MPR_SEMA0) & 1);
|
|
}
|