580 lines
17 KiB
C
580 lines
17 KiB
C
/* $OpenBSD: if_wi_pci.c,v 1.56 2022/03/11 18:00:50 mpi Exp $ */
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/*
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* Copyright (c) 2001-2003 Todd C. Miller <millert@openbsd.org>
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* Sponsored in part by the Defense Advanced Research Projects
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* Agency (DARPA) and Air Force Research Laboratory, Air Force
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* Materiel Command, USAF, under agreement number F39502-99-1-0512.
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*/
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/*
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* PCI attachment for the Wavelan driver. There are two basic types
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* of PCI card supported:
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*
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* 1) Cards based on the Prism2.5 Mini-PCI chipset
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* 2) Cards that use a dumb PCMCIA->PCI bridge
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*
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* Only the first type are "true" PCI cards.
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*
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* The latter are simply PCMCIA cards (or the guts of same) with some
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* type of dumb PCMCIA->PCI bridge. They are "dumb" in that they
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* are not true PCMCIA bridges and really just serve to deal with
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* the different interrupt types and timings of the ISA vs. PCI bus.
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*
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* The following bridge types are supported:
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* o PLX 9052 (the most common)
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* o TMD 7160 (found in some NDC/Sohoware NCP130 cards)
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* o ACEX EP1K30 (really a PLD, found in Symbol cards and their OEMs)
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/timeout.h>
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#include <sys/socket.h>
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#include <sys/tree.h>
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#include <net/if.h>
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#include <net/if_media.h>
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#include <netinet/in.h>
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#include <netinet/if_ether.h>
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#include <net80211/ieee80211_var.h>
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#include <net80211/ieee80211_ioctl.h>
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#include <machine/bus.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/ic/if_wireg.h>
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#include <dev/ic/if_wi_ieee.h>
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#include <dev/ic/if_wivar.h>
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/* For printing CIS of the actual PCMCIA card */
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#define CIS_MFG_NAME_OFFSET 0x16
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#define CIS_INFO_SIZE 256
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const struct wi_pci_product *wi_pci_lookup(struct pci_attach_args *pa);
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int wi_pci_match(struct device *, void *, void *);
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void wi_pci_attach(struct device *, struct device *, void *);
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int wi_pci_activate(struct device *, int);
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void wi_pci_wakeup(struct wi_softc *);
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int wi_pci_acex_attach(struct pci_attach_args *pa, struct wi_softc *sc);
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int wi_pci_plx_attach(struct pci_attach_args *pa, struct wi_softc *sc);
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int wi_pci_tmd_attach(struct pci_attach_args *pa, struct wi_softc *sc);
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int wi_pci_native_attach(struct pci_attach_args *pa, struct wi_softc *sc);
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int wi_pci_common_attach(struct pci_attach_args *pa, struct wi_softc *sc);
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void wi_pci_plx_print_cis(struct wi_softc *);
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struct wi_pci_softc {
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struct wi_softc sc_wi; /* real softc */
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};
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const struct cfattach wi_pci_ca = {
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sizeof (struct wi_pci_softc), wi_pci_match, wi_pci_attach, NULL,
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wi_pci_activate
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};
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static const struct wi_pci_product {
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pci_vendor_id_t pp_vendor;
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pci_product_id_t pp_product;
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int (*pp_attach)(struct pci_attach_args *pa, struct wi_softc *sc);
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} wi_pci_products[] = {
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{ PCI_VENDOR_GLOBALSUN, PCI_PRODUCT_GLOBALSUN_GL24110P, wi_pci_plx_attach },
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{ PCI_VENDOR_GLOBALSUN, PCI_PRODUCT_GLOBALSUN_GL24110P02, wi_pci_plx_attach },
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{ PCI_VENDOR_GLOBALSUN, PCI_PRODUCT_GLOBALSUN_GL24110P03, wi_pci_plx_attach },
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{ PCI_VENDOR_GLOBALSUN, PCI_PRODUCT_GLOBALSUN_8031, wi_pci_plx_attach },
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{ PCI_VENDOR_EUMITCOM, PCI_PRODUCT_EUMITCOM_WL11000P, wi_pci_plx_attach },
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{ PCI_VENDOR_USR2, PCI_PRODUCT_USR2_WL11000P, wi_pci_plx_attach },
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{ PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3CRWE777A, wi_pci_plx_attach },
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{ PCI_VENDOR_NETGEAR, PCI_PRODUCT_NETGEAR_MA301, wi_pci_plx_attach },
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{ PCI_VENDOR_EFFICIENTNETS, PCI_PRODUCT_EFFICIENTNETS_SS1023, wi_pci_plx_attach },
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{ PCI_VENDOR_ADDTRON, PCI_PRODUCT_ADDTRON_AWA100, wi_pci_plx_attach },
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{ PCI_VENDOR_BELKIN, PCI_PRODUCT_BELKIN_F5D6000, wi_pci_plx_attach },
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{ PCI_VENDOR_NDC, PCI_PRODUCT_NDC_NCP130, wi_pci_plx_attach },
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{ PCI_VENDOR_NDC, PCI_PRODUCT_NDC_NCP130A2, wi_pci_tmd_attach },
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{ PCI_VENDOR_INTERSIL, PCI_PRODUCT_INTERSIL_MINI_PCI_WLAN, wi_pci_native_attach },
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{ PCI_VENDOR_INTERSIL, PCI_PRODUCT_INTERSIL_ISL3872, wi_pci_native_attach },
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{ PCI_VENDOR_SAMSUNG, PCI_PRODUCT_SAMSUNG_SWL2210P, wi_pci_native_attach },
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{ PCI_VENDOR_NORTEL, PCI_PRODUCT_NORTEL_211818A, wi_pci_acex_attach },
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{ PCI_VENDOR_SYMBOL, PCI_PRODUCT_SYMBOL_LA41X3, wi_pci_acex_attach },
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{ 0, 0, 0 }
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};
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const struct wi_pci_product *
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wi_pci_lookup(struct pci_attach_args *pa)
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{
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const struct wi_pci_product *pp;
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for (pp = wi_pci_products; pp->pp_product != 0; pp++) {
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if (PCI_VENDOR(pa->pa_id) == pp->pp_vendor &&
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PCI_PRODUCT(pa->pa_id) == pp->pp_product)
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return (pp);
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}
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return (NULL);
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}
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int
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wi_pci_match(struct device *parent, void *match, void *aux)
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{
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return (wi_pci_lookup(aux) != NULL);
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}
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void
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wi_pci_attach(struct device *parent, struct device *self, void *aux)
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{
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struct wi_softc *sc = (struct wi_softc *)self;
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struct pci_attach_args *pa = aux;
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const struct wi_pci_product *pp;
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pp = wi_pci_lookup(pa);
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if (pp->pp_attach(pa, sc) != 0)
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return;
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printf("\n");
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wi_attach(sc, &wi_func_io);
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}
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int
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wi_pci_activate(struct device *self, int act)
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{
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struct wi_softc *sc = (struct wi_softc *)self;
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struct ifnet *ifp = &sc->sc_ic.ic_if;
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switch (act) {
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case DVACT_SUSPEND:
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if (ifp->if_flags & IFF_RUNNING)
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wi_stop(sc);
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break;
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case DVACT_WAKEUP:
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if (ifp->if_flags & IFF_UP)
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wi_pci_wakeup(sc);
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break;
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}
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return (0);
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}
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void
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wi_pci_wakeup(struct wi_softc *sc)
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{
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int s;
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s = splnet();
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while (sc->wi_flags & WI_FLAGS_BUSY)
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tsleep_nsec(&sc->wi_flags, 0, "wipwr", INFSLP);
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sc->wi_flags |= WI_FLAGS_BUSY;
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wi_init(sc);
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sc->wi_flags &= ~WI_FLAGS_BUSY;
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wakeup(&sc->wi_flags);
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splx(s);
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}
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/*
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* ACEX EP1K30-based PCMCIA->PCI bridge attachment.
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*
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* The ACEX EP1K30 is a programmable logic device (PLD) used as a
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* PCMCIA->PCI bridge on the Symbol LA4123 and its OEM equivalents
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* (such as the Nortel E-mobility 211818-A). There are 3 I/O ports:
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* BAR0 at 0x10 appears to be a command port.
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* BAR1 at 0x14 contains COR at offset 0xe0.
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* BAR2 at 0x18 maps the actual PCMCIA card.
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*
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* The datasheet for the ACEX EP1K30 is available from Altera but that
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* doesn't really help much since we don't know how it is programmed.
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* Details for this attachment were gleaned from a version of the
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* Linux orinoco driver modified by Tobias Hoffmann based on
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* what he discovered from the Windows driver.
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*/
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int
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wi_pci_acex_attach(struct pci_attach_args *pa, struct wi_softc *sc)
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{
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bus_space_handle_t commandh, localh, ioh;
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bus_space_tag_t commandt, localt;
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bus_space_tag_t iot = pa->pa_iot;
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bus_size_t commandsize, localsize, iosize;
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int i;
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if (pci_mapreg_map(pa, WI_ACEX_CMDRES, PCI_MAPREG_TYPE_IO,
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0, &commandt, &commandh, NULL, &commandsize, 0) != 0) {
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printf(": can't map command i/o space\n");
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return (ENXIO);
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}
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if (pci_mapreg_map(pa, WI_ACEX_LOCALRES, PCI_MAPREG_TYPE_IO,
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0, &localt, &localh, NULL, &localsize, 0) != 0) {
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printf(": can't map local i/o space\n");
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bus_space_unmap(commandt, commandh, commandsize);
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return (ENXIO);
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}
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sc->wi_ltag = localt;
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sc->wi_lhandle = localh;
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if (pci_mapreg_map(pa, WI_TMD_IORES, PCI_MAPREG_TYPE_IO,
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0, &iot, &ioh, NULL, &iosize, 0) != 0) {
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printf(": can't map i/o space\n");
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bus_space_unmap(localt, localh, localsize);
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bus_space_unmap(commandt, commandh, commandsize);
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return (ENXIO);
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}
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sc->wi_btag = iot;
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sc->wi_bhandle = ioh;
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/*
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* Setup bridge chip.
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*/
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if (bus_space_read_4(commandt, commandh, 0) & 1) {
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printf(": bridge not ready\n");
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bus_space_unmap(iot, ioh, iosize);
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bus_space_unmap(localt, localh, localsize);
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bus_space_unmap(commandt, commandh, commandsize);
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return (ENXIO);
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}
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bus_space_write_4(commandt, commandh, 2, 0x118);
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bus_space_write_4(commandt, commandh, 2, 0x108);
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DELAY(30 * 1000);
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bus_space_write_4(commandt, commandh, 2, 0x8);
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for (i = 0; i < 30; i++) {
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DELAY(30 * 1000);
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if (bus_space_read_4(commandt, commandh, 0) & 0x10)
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break;
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}
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if (i == 30) {
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printf(": bridge timeout\n");
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bus_space_unmap(iot, ioh, iosize);
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bus_space_unmap(localt, localh, localsize);
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bus_space_unmap(commandt, commandh, commandsize);
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return (ENXIO);
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}
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if ((bus_space_read_4(localt, localh, 0xe0) & 1) ||
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(bus_space_read_4(localt, localh, 0xe2) & 1) ||
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(bus_space_read_4(localt, localh, 0xe4) & 1)) {
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printf(": failed bridge setup\n");
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bus_space_unmap(iot, ioh, iosize);
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bus_space_unmap(localt, localh, localsize);
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bus_space_unmap(commandt, commandh, commandsize);
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return (ENXIO);
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}
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if (wi_pci_common_attach(pa, sc) != 0) {
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bus_space_unmap(iot, ioh, iosize);
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bus_space_unmap(localt, localh, localsize);
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bus_space_unmap(commandt, commandh, commandsize);
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return (ENXIO);
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}
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/*
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* Enable I/O mode and level interrupts on the embedded PCMCIA
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* card.
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*/
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bus_space_write_1(localt, localh, WI_ACEX_COR_OFFSET, WI_COR_IOMODE);
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sc->wi_cor_offset = WI_ACEX_COR_OFFSET;
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/* Unmap registers we no longer need access to. */
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bus_space_unmap(commandt, commandh, commandsize);
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return (0);
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}
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/*
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* PLX 9052-based PCMCIA->PCI bridge attachment.
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*
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* These are often sold as "PCI wireless card adapters" and are
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* sold by several vendors. Most are simply rebadged versions of the
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* Eumitcom WL11000P or Global Sun Technology GL24110P02.
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* These cards use the PLX 9052 dumb bridge chip to connect a PCMCIA
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* wireless card to the PCI bus. Because it is a dumb bridge and
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* not a true PCMCIA bridge, the PCMCIA subsystem is not involved
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* (or even required). The PLX 9052 provides multiple PCI address
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* space mappings. The primary mappings at PCI registers 0x10 (mem)
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* and 0x14 (I/O) are for the PLX chip itself, *NOT* the PCMCIA card.
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* The mem and I/O spaces for the PCMCIA card are mapped to 0x18 and
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* 0x1C respectively.
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* The PLX 9050/9052 datasheet may be downloaded from PLX at
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* http://www.plxtech.com/products/toolbox/9050.htm
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*/
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int
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wi_pci_plx_attach(struct pci_attach_args *pa, struct wi_softc *sc)
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{
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bus_space_handle_t localh, ioh, memh;
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bus_space_tag_t localt;
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bus_space_tag_t iot = pa->pa_iot;
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bus_space_tag_t memt = pa->pa_memt;
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bus_size_t localsize, memsize, iosize;
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u_int32_t intcsr;
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if (pci_mapreg_map(pa, WI_PLX_MEMRES, PCI_MAPREG_TYPE_MEM, 0,
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&memt, &memh, NULL, &memsize, 0) != 0) {
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printf(": can't map mem space\n");
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return (ENXIO);
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}
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sc->wi_ltag = memt;
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sc->wi_lhandle = memh;
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if (pci_mapreg_map(pa, WI_PLX_IORES,
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PCI_MAPREG_TYPE_IO, 0, &iot, &ioh, NULL, &iosize, 0) != 0) {
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printf(": can't map i/o space\n");
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bus_space_unmap(memt, memh, memsize);
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return (ENXIO);
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}
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sc->wi_btag = iot;
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sc->wi_bhandle = ioh;
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/*
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* Some cards, such as the PLX version of the NDC NCP130,
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* don't have the PLX local registers mapped. In general
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* this is OK since on those cards the serial EEPROM has
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* already set things up for us.
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* As such, we don't consider an error here to be fatal.
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*/
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localsize = 0;
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if (pci_mapreg_type(pa->pa_pc, pa->pa_tag, WI_PLX_LOCALRES)
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== PCI_MAPREG_TYPE_IO) {
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if (pci_mapreg_map(pa, WI_PLX_LOCALRES, PCI_MAPREG_TYPE_IO,
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0, &localt, &localh, NULL, &localsize, 0) != 0)
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printf(": can't map PLX I/O space\n");
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}
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if (wi_pci_common_attach(pa, sc) != 0) {
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if (localsize)
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bus_space_unmap(localt, localh, localsize);
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bus_space_unmap(iot, ioh, iosize);
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bus_space_unmap(memt, memh, memsize);
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return (ENXIO);
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}
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if (localsize != 0) {
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intcsr = bus_space_read_4(localt, localh,
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WI_PLX_INTCSR);
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/*
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* The Netgear MA301 has local interrupt 1 active
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* when there is no card in the adapter. We bail
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* early in this case since our attempt to check
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* for the presence of a card later will hang the
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* MA301.
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*/
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if (intcsr & WI_PLX_LINT1STAT) {
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printf("\n%s: no PCMCIA card detected in bridge card\n",
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WI_PRT_ARG(sc));
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pci_intr_disestablish(pa->pa_pc, sc->sc_ih);
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if (localsize)
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bus_space_unmap(localt, localh, localsize);
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bus_space_unmap(iot, ioh, iosize);
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bus_space_unmap(memt, memh, memsize);
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return (ENXIO);
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}
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/*
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* Enable PCI interrupts on the PLX chip if they are
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* not already enabled. On most adapters the serial
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* EEPROM has done this for us but some (such as
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* the Netgear MA301) do not.
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*/
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if (!(intcsr & WI_PLX_INTEN)) {
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intcsr |= WI_PLX_INTEN;
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bus_space_write_4(localt, localh, WI_PLX_INTCSR,
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intcsr);
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}
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}
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/*
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* Enable I/O mode and level interrupts on the PCMCIA card.
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* The PCMCIA card's COR is the first byte after the CIS.
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*/
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bus_space_write_1(memt, memh, WI_PLX_COR_OFFSET, WI_COR_IOMODE);
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sc->wi_cor_offset = WI_PLX_COR_OFFSET;
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if (localsize != 0) {
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/*
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* Test the presence of a wi(4) card by writing
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* a magic number to the first software support
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* register and then reading it back.
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*/
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CSR_WRITE_2(sc, WI_SW0, WI_DRVR_MAGIC);
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DELAY(1000);
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if (CSR_READ_2(sc, WI_SW0) != WI_DRVR_MAGIC) {
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printf("\n%s: no PCMCIA card detected in bridge card\n",
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WI_PRT_ARG(sc));
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pci_intr_disestablish(pa->pa_pc, sc->sc_ih);
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if (localsize)
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bus_space_unmap(localt, localh, localsize);
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bus_space_unmap(iot, ioh, iosize);
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bus_space_unmap(memt, memh, memsize);
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return (ENXIO);
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}
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/* Unmap registers we no longer need access to. */
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bus_space_unmap(localt, localh, localsize);
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/* Print PCMCIA card's CIS strings. */
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wi_pci_plx_print_cis(sc);
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}
|
|
|
|
return (0);
|
|
}
|
|
|
|
/*
|
|
* TMD 7160-based PCMCIA->PCI bridge attachment.
|
|
*
|
|
* The TMD7160 dumb bridge chip is used on some versions of the
|
|
* NDC/Sohoware NCP130. The TMD7160 provides two PCI I/O registers.
|
|
* The first, at 0x14, maps to the Prism2 COR.
|
|
* The second, at 0x18, is for the Prism2 chip itself.
|
|
*
|
|
* The datasheet for the TMD7160 does not seem to be publicly available.
|
|
* Details for this attachment were gleaned from a version of the
|
|
* Linux WLAN driver modified by NDC.
|
|
*/
|
|
int
|
|
wi_pci_tmd_attach(struct pci_attach_args *pa, struct wi_softc *sc)
|
|
{
|
|
bus_space_handle_t localh, ioh;
|
|
bus_space_tag_t localt;
|
|
bus_space_tag_t iot = pa->pa_iot;
|
|
bus_size_t localsize, iosize;
|
|
|
|
if (pci_mapreg_map(pa, WI_TMD_LOCALRES, PCI_MAPREG_TYPE_IO,
|
|
0, &localt, &localh, NULL, &localsize, 0) != 0) {
|
|
printf(": can't map TMD I/O space\n");
|
|
return (ENXIO);
|
|
}
|
|
sc->wi_ltag = localt;
|
|
sc->wi_lhandle = localh;
|
|
|
|
if (pci_mapreg_map(pa, WI_TMD_IORES, PCI_MAPREG_TYPE_IO,
|
|
0, &iot, &ioh, NULL, &iosize, 0) != 0) {
|
|
printf(": can't map i/o space\n");
|
|
bus_space_unmap(localt, localh, localsize);
|
|
return (ENXIO);
|
|
}
|
|
sc->wi_btag = iot;
|
|
sc->wi_bhandle = ioh;
|
|
|
|
if (wi_pci_common_attach(pa, sc) != 0) {
|
|
bus_space_unmap(iot, ioh, iosize);
|
|
bus_space_unmap(localt, localh, localsize);
|
|
return (ENXIO);
|
|
}
|
|
|
|
/*
|
|
* Enable I/O mode and level interrupts on the embedded PCMCIA
|
|
* card. The PCMCIA card's COR is the first byte of BAR 0.
|
|
*/
|
|
bus_space_write_1(localt, localh, 0, WI_COR_IOMODE);
|
|
sc->wi_cor_offset = 0;
|
|
|
|
return (0);
|
|
}
|
|
|
|
int
|
|
wi_pci_native_attach(struct pci_attach_args *pa, struct wi_softc *sc)
|
|
{
|
|
bus_space_handle_t ioh;
|
|
bus_space_tag_t iot = pa->pa_iot;
|
|
bus_size_t iosize;
|
|
|
|
if (pci_mapreg_map(pa, WI_PCI_CBMA, PCI_MAPREG_TYPE_MEM,
|
|
0, &iot, &ioh, NULL, &iosize, 0) != 0) {
|
|
printf(": can't map mem space\n");
|
|
return (ENXIO);
|
|
}
|
|
sc->wi_ltag = iot;
|
|
sc->wi_lhandle = ioh;
|
|
sc->wi_btag = iot;
|
|
sc->wi_bhandle = ioh;
|
|
sc->sc_pci = 1;
|
|
|
|
if (wi_pci_common_attach(pa, sc) != 0) {
|
|
bus_space_unmap(iot, ioh, iosize);
|
|
return (ENXIO);
|
|
}
|
|
|
|
/* Do a soft reset of the HFA3842 MAC core */
|
|
bus_space_write_2(iot, ioh, WI_PCI_COR_OFFSET, WI_COR_SOFT_RESET);
|
|
DELAY(100*1000); /* 100 m sec */
|
|
bus_space_write_2(iot, ioh, WI_PCI_COR_OFFSET, WI_COR_CLEAR);
|
|
DELAY(100*1000); /* 100 m sec */
|
|
sc->wi_cor_offset = WI_PCI_COR_OFFSET;
|
|
|
|
return (0);
|
|
}
|
|
|
|
int
|
|
wi_pci_common_attach(struct pci_attach_args *pa, struct wi_softc *sc)
|
|
{
|
|
pci_intr_handle_t ih;
|
|
pci_chipset_tag_t pc = pa->pa_pc;
|
|
const char *intrstr;
|
|
|
|
/* Make sure interrupts are disabled. */
|
|
CSR_WRITE_2(sc, WI_INT_EN, 0);
|
|
CSR_WRITE_2(sc, WI_EVENT_ACK, 0xFFFF);
|
|
|
|
/* Map and establish the interrupt. */
|
|
if (pci_intr_map(pa, &ih)) {
|
|
printf(": couldn't map interrupt\n");
|
|
return (ENXIO);
|
|
}
|
|
intrstr = pci_intr_string(pc, ih);
|
|
sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, wi_intr, sc,
|
|
sc->sc_dev.dv_xname);
|
|
if (sc->sc_ih == NULL) {
|
|
printf(": couldn't establish interrupt");
|
|
if (intrstr != NULL)
|
|
printf(" at %s", intrstr);
|
|
printf("\n");
|
|
return (ENXIO);
|
|
}
|
|
printf(": %s", intrstr);
|
|
|
|
return (0);
|
|
}
|
|
|
|
void
|
|
wi_pci_plx_print_cis(struct wi_softc *sc)
|
|
{
|
|
int i, stringno;
|
|
char cisbuf[CIS_INFO_SIZE];
|
|
char *cis_strings[3];
|
|
u_int8_t value;
|
|
const u_int8_t cis_magic[] = {
|
|
0x01, 0x03, 0x00, 0x00, 0xff, 0x17, 0x04, 0x67
|
|
};
|
|
|
|
/* Make sure the CIS data is valid. */
|
|
for (i = 0; i < 8; i++) {
|
|
value = bus_space_read_1(sc->wi_ltag, sc->wi_lhandle, i * 2);
|
|
if (value != cis_magic[i])
|
|
return;
|
|
}
|
|
|
|
cis_strings[0] = cisbuf;
|
|
stringno = 0;
|
|
for (i = 0; i < CIS_INFO_SIZE && stringno < 3; i++) {
|
|
cisbuf[i] = bus_space_read_1(sc->wi_ltag,
|
|
sc->wi_lhandle, (CIS_MFG_NAME_OFFSET + i) * 2);
|
|
if (cisbuf[i] == '\0' && ++stringno < 3)
|
|
cis_strings[stringno] = &cisbuf[i + 1];
|
|
}
|
|
cisbuf[CIS_INFO_SIZE - 1] = '\0';
|
|
printf("\n%s: \"%s, %s, %s\"", WI_PRT_ARG(sc),
|
|
cis_strings[0], cis_strings[1], cis_strings[2]);
|
|
}
|