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sync code with last fixes and improvements from OpenBSD

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This commit is contained in:
purplerain 2023-07-27 09:35:44 +00:00
parent 58df21ce75
commit f960599e67
Signed by: purplerain
GPG key ID: F42C07F07E2E35B7
399 changed files with 7016 additions and 6902 deletions
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1
sys/.gitignore vendored
View file

@ -1,2 +1,3 @@
**/obj
**/tags
**/CVS

20
sys/arch/amd64/amd64/cpu.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: cpu.c,v 1.171 2023/07/21 04:04:51 guenther Exp $ */
/* $OpenBSD: cpu.c,v 1.173 2023/07/25 04:42:00 deraadt Exp $ */
/* $NetBSD: cpu.c,v 1.1 2003/04/26 18:39:26 fvdl Exp $ */
/*-
@ -1168,7 +1168,7 @@ void
cpu_fix_msrs(struct cpu_info *ci)
{
int family = ci->ci_family;
uint64_t msr;
uint64_t msr, nmsr;
if (!strcmp(cpu_vendor, "GenuineIntel")) {
if ((family > 6 || (family == 6 && ci->ci_model >= 0xd)) &&
@ -1211,11 +1211,17 @@ cpu_fix_msrs(struct cpu_info *ci)
* where LFENCE is always serializing.
*/
if (family >= 0x10 && family != 0x11) {
msr = rdmsr(MSR_DE_CFG);
if ((msr & DE_CFG_SERIALIZE_LFENCE) == 0) {
msr |= DE_CFG_SERIALIZE_LFENCE;
wrmsr(MSR_DE_CFG, msr);
}
nmsr = msr = rdmsr(MSR_DE_CFG);
nmsr |= DE_CFG_SERIALIZE_LFENCE;
if (msr != nmsr)
wrmsr(MSR_DE_CFG, nmsr);
}
if (family == 0x17 && ci->ci_model >= 0x31 &&
(cpu_ecxfeature & CPUIDECX_HV) == 0) {
nmsr = msr = rdmsr(MSR_DE_CFG);
nmsr |= DE_CFG_SERIALIZE_9;
if (msr != nmsr)
wrmsr(MSR_DE_CFG, nmsr);
}
}

52
sys/arch/amd64/amd64/identcpu.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: identcpu.c,v 1.134 2023/07/21 04:04:51 guenther Exp $ */
/* $OpenBSD: identcpu.c,v 1.135 2023/07/27 01:51:35 guenther Exp $ */
/* $NetBSD: identcpu.c,v 1.1 2003/04/26 18:39:28 fvdl Exp $ */
/*
@ -230,18 +230,47 @@ const struct {
}, cpu_cpuid_apmi_edx[] = {
{ CPUIDEDX_ITSC, "ITSC" },
}, cpu_amdspec_ebxfeatures[] = {
{ CPUIDEBX_IBPB, "IBPB" },
{ CPUIDEBX_IBRS, "IBRS" },
{ CPUIDEBX_STIBP, "STIBP" },
{ CPUIDEBX_SSBD, "SSBD" },
{ CPUIDEBX_VIRT_SSBD, "VIRTSSBD" },
{ CPUIDEBX_SSBD_NOTREQ, "SSBDNR" },
{ CPUIDEBX_INVLPGB, "INVLPGB" },
{ CPUIDEBX_IBPB, "IBPB" },
{ CPUIDEBX_IBRS, "IBRS" },
{ CPUIDEBX_STIBP, "STIBP" },
{ CPUIDEBX_IBRS_ALWAYSON, "IBRS_ALL" },
{ CPUIDEBX_STIBP_ALWAYSON, "STIBP_ALL" },
{ CPUIDEBX_IBRS_PREF, "IBRS_PREF" },
{ CPUIDEBX_IBRS_SAME_MODE, "IBRS_SM" },
{ CPUIDEBX_SSBD, "SSBD" },
{ CPUIDEBX_VIRT_SSBD, "VIRTSSBD" },
{ CPUIDEBX_SSBD_NOTREQ, "SSBDNR" },
}, cpu_xsave_extfeatures[] = {
{ XSAVE_XSAVEOPT, "XSAVEOPT" },
{ XSAVE_XSAVEC, "XSAVEC" },
{ XSAVE_XGETBV1, "XGETBV1" },
{ XSAVE_XSAVES, "XSAVES" },
{ XSAVE_XFD, "XFD" },
}, cpu_arch_cap_features[] = {
/* ARCH_CAP_RDCL_NO (not printed) == !MELTDOWN */
{ ARCH_CAP_IBRS_ALL, "IBRS_ALL" },
{ ARCH_CAP_RSBA, "RSBA" },
{ ARCH_CAP_SKIP_L1DFL_VMENTRY, "SKIP_L1DFL" },
{ ARCH_CAP_SSB_NO, "SSB_NO" },
{ ARCH_CAP_MDS_NO, "MDS_NO" },
{ ARCH_CAP_IF_PSCHANGE_MC_NO, "IF_PSCHANGE" },
{ ARCH_CAP_TSX_CTRL, "TSX_CTRL" },
{ ARCH_CAP_TAA_NO, "TAA_NO" },
{ ARCH_CAP_MCU_CONTROL, "MCU_CONTROL" },
{ ARCH_CAP_MISC_PACKAGE_CTLS, "MISC_PKG_CT" },
{ ARCH_CAP_ENERGY_FILTERING_CTL, "ENERGY_FILT" },
{ ARCH_CAP_DOITM, "DOITM" },
{ ARCH_CAP_SBDR_SSDP_NO, "SBDR_SSDP_N" },
{ ARCH_CAP_FBSDP_NO, "FBSDP_NO" },
{ ARCH_CAP_PSDP_NO, "PSDP_NO" },
{ ARCH_CAP_FB_CLEAR, "FB_CLEAR" },
{ ARCH_CAP_FB_CLEAR_CTRL, "FB_CLEAR_CT" },
{ ARCH_CAP_RRSBA, "RRSBA" },
{ ARCH_CAP_BHI_NO, "BHI_NO" },
{ ARCH_CAP_XAPIC_DISABLE_STATUS, "XAPIC_DIS" },
{ ARCH_CAP_OVERCLOCKING_STATUS, "OVERCLOCK" },
{ ARCH_CAP_PBRSB_NO, "PBRSB_NO" },
};
int
@ -674,7 +703,7 @@ identifycpu(struct cpu_info *ci)
ci->ci_feature_tpmflags |= TPM_ARAT;
}
/* AMD speculation control features */
/* speculation control features */
if (!strcmp(cpu_vendor, "AuthenticAMD")) {
if (ci->ci_pnfeatset >= 0x80000008) {
CPUID(0x80000008, dummy, ci->ci_feature_amdspec_ebx,
@ -685,6 +714,13 @@ identifycpu(struct cpu_info *ci)
printf(",%s",
cpu_amdspec_ebxfeatures[i].str);
}
} else if (!strcmp(cpu_vendor, "GenuineIntel") &&
(ci->ci_feature_sefflags_edx & SEFF0EDX_ARCH_CAP)) {
uint64_t msr = rdmsr(MSR_ARCH_CAPABILITIES);
for (i = 0; i < nitems(cpu_arch_cap_features); i++)
if (msr & cpu_arch_cap_features[i].bit)
printf(",%s", cpu_arch_cap_features[i].str);
}
/* xsave subfeatures */

24
sys/arch/amd64/amd64/locore.S
View file

@ -1,4 +1,4 @@
/* $OpenBSD: locore.S,v 1.136 2023/07/10 03:32:10 guenther Exp $ */
/* $OpenBSD: locore.S,v 1.138 2023/07/27 00:28:24 guenther Exp $ */
/* $NetBSD: locore.S,v 1.13 2004/03/25 18:33:17 drochner Exp $ */
/*
@ -473,31 +473,17 @@ bogus_proc_pmap:
#endif /* DIAGNOSTIC */
END(cpu_switchto)
ENTRY(cpu_idle_enter)
ret
lfence
END(cpu_idle_enter)
ENTRY(cpu_idle_leave)
ret
lfence
END(cpu_idle_leave)
/* placed here for correct static branch prediction in cpu_idle_* */
NENTRY(retpoline_rax)
JMP_RETPOLINE(rax)
ENTRY(cpu_idle_cycle)
RETGUARD_SETUP(cpu_idle_cycle, r11)
movq cpu_idle_cycle_fcn,%rax
cmpq $0,%rax
jne retpoline_rax
ENTRY(cpu_idle_cycle_hlt)
RETGUARD_SETUP(cpu_idle_cycle_hlt, r11)
sti
hlt
RETGUARD_CHECK(cpu_idle_cycle, r11)
RETGUARD_CHECK(cpu_idle_cycle_hlt, r11)
ret
lfence
END(cpu_idle_cycle)
END(cpu_idle_cycle_hlt)
/*
* savectx(struct pcb *pcb);

5
sys/arch/amd64/amd64/machdep.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: machdep.c,v 1.285 2023/07/10 03:32:10 guenther Exp $ */
/* $OpenBSD: machdep.c,v 1.286 2023/07/27 00:28:25 guenther Exp $ */
/* $NetBSD: machdep.c,v 1.3 2003/05/07 22:58:18 fvdl Exp $ */
/*-
@ -160,7 +160,8 @@ char machine[] = MACHINE;
/*
* switchto vectors
*/
void (*cpu_idle_cycle_fcn)(void) = NULL;
void cpu_idle_cycle_hlt(void);
void (*cpu_idle_cycle_fcn)(void) = &cpu_idle_cycle_hlt;
/* the following is used externally for concurrent handlers */
int setperf_prio = 0;

8
sys/arch/amd64/amd64/spl.S
View file

@ -1,4 +1,4 @@
/* $OpenBSD: spl.S,v 1.19 2022/12/01 00:26:15 guenther Exp $ */
/* $OpenBSD: spl.S,v 1.20 2023/07/27 00:30:07 guenther Exp $ */
/* $NetBSD: spl.S,v 1.3 2004/06/28 09:13:11 fvdl Exp $ */
/*
@ -122,7 +122,8 @@ KIDTVEC(spllower)
RETGUARD_PUSH(r11)
movl %edi,%ebx
leaq 1f(%rip),%r13 # address to resume loop at
1: movl %ebx,%eax # get cpl
1: endbr64
movl %ebx,%eax # get cpl
movq CPUVAR(IUNMASK)(,%rax,8),%rax
cli
andq CPUVAR(IPENDING),%rax # any non-masked bits left?
@ -153,7 +154,8 @@ KIDTVEC(doreti)
movq IF_PPL(%rsp),%rbx # get previous priority
decl CPUVAR(IDEPTH)
leaq 1f(%rip),%r13
1: movl %ebx,%eax
1: endbr64
movl %ebx,%eax
movq CPUVAR(IUNMASK)(,%rax,8),%rax
cli
andq CPUVAR(IPENDING),%rax

104
sys/arch/amd64/amd64/ucode.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: ucode.c,v 1.5 2019/06/28 21:54:05 bluhm Exp $ */
/* $OpenBSD: ucode.c,v 1.6 2023/07/23 01:46:37 jsg Exp $ */
/*
* Copyright (c) 2018 Stefan Fritsch <fritsch@genua.de>
* Copyright (c) 2018 Patrick Wildt <patrick@blueri.se>
@ -72,6 +72,8 @@ size_t cpu_ucode_size;
void cpu_ucode_setup(void);
void cpu_ucode_apply(struct cpu_info *);
struct mutex cpu_ucode_mtx = MUTEX_INITIALIZER(IPL_HIGH);
/* Intel */
void cpu_ucode_intel_apply(struct cpu_info *);
struct intel_ucode_header *
@ -82,7 +84,8 @@ int cpu_ucode_intel_match(struct intel_ucode_header *, uint32_t, uint32_t,
uint32_t cpu_ucode_intel_rev(void);
struct intel_ucode_header *cpu_ucode_intel_applied;
struct mutex cpu_ucode_intel_mtx = MUTEX_INITIALIZER(IPL_HIGH);
void cpu_ucode_amd_apply(struct cpu_info *);
void
cpu_ucode_setup(void)
@ -107,6 +110,99 @@ cpu_ucode_apply(struct cpu_info *ci)
{
if (strcmp(cpu_vendor, "GenuineIntel") == 0)
cpu_ucode_intel_apply(ci);
else if (strcmp(cpu_vendor, "AuthenticAMD") == 0)
cpu_ucode_amd_apply(ci);
}
#define AMD_MAGIC 0x00414d44
struct amd_equiv {
uint32_t id;
uint32_t a;
uint32_t b;
uint16_t eid;
uint16_t c;
} __packed;
struct amd_patch {
uint32_t type;
uint32_t len;
uint32_t a;
uint32_t level;
uint8_t c[16];
uint16_t eid;
} __packed;
void
cpu_ucode_amd_apply(struct cpu_info *ci)
{
uint64_t level;
uint32_t magic, tlen, i;
uint16_t eid = 0;
uint32_t sig, ebx, ecx, edx;
uint64_t start = 0;
if (cpu_ucode_data == NULL || cpu_ucode_size == 0) {
DPRINTF(("%s: no microcode provided\n", __func__));
return;
}
/*
* Grab a mutex, because we are not allowed to run updates
* simultaneously on HT siblings.
*/
mtx_enter(&cpu_ucode_mtx);
CPUID(1, sig, ebx, ecx, edx);
level = rdmsr(MSR_PATCH_LEVEL);
DPRINTF(("%s: cur patch level 0x%llx\n", __func__, level));
memcpy(&magic, cpu_ucode_data, 4);
if (magic != AMD_MAGIC) {
DPRINTF(("%s: bad magic %x\n", __func__, magic));
goto out;
}
memcpy(&tlen, &cpu_ucode_data[8], 4);
/* find equivalence id matching our cpu signature */
for (i = 12; i < 12 + tlen;) {
struct amd_equiv ae;
if (i + sizeof(ae) > cpu_ucode_size) {
DPRINTF(("%s: truncated etable\n", __func__));
goto out;
}
memcpy(&ae, &cpu_ucode_data[i], sizeof(ae));
i += sizeof(ae);
if (ae.id == sig)
eid = ae.eid;
}
/* look for newer patch with the equivalence id */
while (i < cpu_ucode_size) {
struct amd_patch ap;
if (i + sizeof(ap) > cpu_ucode_size) {
DPRINTF(("%s: truncated ptable\n", __func__));
goto out;
}
memcpy(&ap, &cpu_ucode_data[i], sizeof(ap));
if (ap.type == 1 && ap.eid == eid && ap.level > level)
start = (uint64_t)&cpu_ucode_data[i + 8];
if (i + ap.len + 8 > cpu_ucode_size) {
DPRINTF(("%s: truncated patch\n", __func__));
goto out;
}
i += ap.len + 8;
}
if (start != 0) {
wrmsr(MSR_PATCH_LOADER, start);
level = rdmsr(MSR_PATCH_LEVEL);
DPRINTF(("%s: new patch level 0x%llx\n", __func__, level));
}
out:
mtx_leave(&cpu_ucode_mtx);
}
void
@ -125,7 +221,7 @@ cpu_ucode_intel_apply(struct cpu_info *ci)
* Grab a mutex, because we are not allowed to run updates
* simultaneously on HT siblings.
*/
mtx_enter(&cpu_ucode_intel_mtx);
mtx_enter(&cpu_ucode_mtx);
old_rev = cpu_ucode_intel_rev();
update = cpu_ucode_intel_applied;
@ -159,7 +255,7 @@ cpu_ucode_intel_apply(struct cpu_info *ci)
}
out:
mtx_leave(&cpu_ucode_intel_mtx);
mtx_leave(&cpu_ucode_mtx);
}
struct intel_ucode_header *

10
sys/arch/amd64/amd64/vector.S
View file

@ -1,4 +1,4 @@
/* $OpenBSD: vector.S,v 1.92 2023/04/17 00:02:14 deraadt Exp $ */
/* $OpenBSD: vector.S,v 1.93 2023/07/27 00:30:07 guenther Exp $ */
/* $NetBSD: vector.S,v 1.5 2004/06/28 09:13:11 fvdl Exp $ */
/*
@ -551,6 +551,7 @@ IDTVEC(intr_lapic_ipi)
jae 2f
END(INTRENTRY_LABEL(intr_lapic_ipi))
KIDTVEC_FALLTHROUGH(resume_lapic_ipi)
endbr64
1:
incl CPUVAR(IDEPTH)
movl $IPL_IPI,CPUVAR(ILEVEL)
@ -757,6 +758,7 @@ IDTVEC(intr_lapic_ltimer)
jae 2f
END(INTRENTRY_LABEL(intr_lapic_ltimer))
KIDTVEC_FALLTHROUGH(resume_lapic_ltimer)
endbr64
1:
incl CPUVAR(IDEPTH)
movl $IPL_CLOCK,CPUVAR(ILEVEL)
@ -790,6 +792,7 @@ IDTVEC(intr_xen_upcall)
jae 2f
END(INTRENTRY_LABEL(intr_xen_upcall))
KIDTVEC_FALLTHROUGH(resume_xen_upcall)
endbr64
1:
incl CPUVAR(IDEPTH)
movl $IPL_NET,CPUVAR(ILEVEL)
@ -822,6 +825,7 @@ IDTVEC(intr_hyperv_upcall)
jae 2f
END(INTRENTRY_LABEL(intr_hyperv_upcall))
KIDTVEC_FALLTHROUGH(resume_hyperv_upcall)
endbr64
1:
incl CPUVAR(IDEPTH)
movl $IPL_NET,CPUVAR(ILEVEL)
@ -852,6 +856,7 @@ KIDTVEC(recurse_##name##num) ;\
INTR_RECURSE ;\
END(Xrecurse_##name##num) ;\
KIDTVEC_FALLTHROUGH(resume_##name##num) \
endbr64 ;\
movq $IREENT_MAGIC,TF_ERR(%rsp) ;\
movl %ebx,%r13d ;\
movq CPUVAR(ISOURCES) + (num) * 8, %r14 ;\
@ -1268,6 +1273,7 @@ NENTRY(retpoline_r13)
END(retpoline_r13)
KIDTVEC(softtty)
endbr64
movl $IPL_SOFTTTY, CPUVAR(ILEVEL)
sti
incl CPUVAR(IDEPTH)
@ -1278,6 +1284,7 @@ KIDTVEC(softtty)
END(Xsofttty)
KIDTVEC(softnet)
endbr64
movl $IPL_SOFTNET, CPUVAR(ILEVEL)
sti
incl CPUVAR(IDEPTH)
@ -1288,6 +1295,7 @@ KIDTVEC(softnet)
END(Xsoftnet)
KIDTVEC(softclock)
endbr64
movl $IPL_SOFTCLOCK, CPUVAR(ILEVEL)
sti
incl CPUVAR(IDEPTH)

6
sys/arch/amd64/include/cpu.h
View file

@ -1,4 +1,4 @@
/* $OpenBSD: cpu.h,v 1.155 2023/07/04 17:29:32 cheloha Exp $ */
/* $OpenBSD: cpu.h,v 1.158 2023/07/27 00:28:24 guenther Exp $ */
/* $NetBSD: cpu.h,v 1.1 2003/04/26 18:39:39 fvdl Exp $ */
/*-
@ -208,6 +208,7 @@ struct cpu_info {
u_int64_t ci_hz_aperf;
#if defined(GPROF) || defined(DDBPROF)
struct gmonparam *ci_gmon;
struct clockintr *ci_gmonclock;
#endif
u_int32_t ci_vmm_flags;
#define CI_VMM_VMX (1 << 0)
@ -403,7 +404,10 @@ void cpu_reset(void);
void x86_64_proc0_tss_ldt_init(void);
void cpu_proc_fork(struct proc *, struct proc *);
int amd64_pa_used(paddr_t);
#define cpu_idle_enter() do { /* nothing */ } while (0)
extern void (*cpu_idle_cycle_fcn)(void);
#define cpu_idle_cycle() (*cpu_idle_cycle_fcn)()
#define cpu_idle_leave() do { /* nothing */ } while (0)
struct region_descriptor;
void lgdt(struct region_descriptor *);

3
sys/arch/amd64/include/frameasm.h
View file

@ -1,4 +1,4 @@
/* $OpenBSD: frameasm.h,v 1.26 2023/04/17 00:02:14 deraadt Exp $ */
/* $OpenBSD: frameasm.h,v 1.27 2023/07/27 00:30:07 guenther Exp $ */
/* $NetBSD: frameasm.h,v 1.1 2003/04/26 18:39:40 fvdl Exp $ */
#ifndef _AMD64_MACHINE_FRAMEASM_H
@ -111,6 +111,7 @@ _ENTRY(INTRENTRY_LABEL(label)) /* from kernel */ \
* to return to. %r10 and %r11 are scratch.
*/
#define INTR_RECURSE \
endbr64 ; \
/* fake the iretq_frame */ ; \
movq %rsp,%r10 ; \
movl %ss,%r11d ; \

5
sys/arch/amd64/include/specialreg.h
View file

@ -1,4 +1,4 @@
/* $OpenBSD: specialreg.h,v 1.104 2023/07/21 04:04:51 guenther Exp $ */
/* $OpenBSD: specialreg.h,v 1.106 2023/07/27 01:51:35 guenther Exp $ */
/* $NetBSD: specialreg.h,v 1.1 2003/04/26 18:39:48 fvdl Exp $ */
/* $NetBSD: x86/specialreg.h,v 1.2 2003/04/25 21:54:30 fvdl Exp $ */
@ -334,12 +334,14 @@
/*
* AMD CPUID function 0x80000008 EBX bits
*/
#define CPUIDEBX_INVLPGB (1ULL << 3) /* INVLPG w/broadcast */
#define CPUIDEBX_IBPB (1ULL << 12) /* Speculation Control IBPB */
#define CPUIDEBX_IBRS (1ULL << 14) /* Speculation Control IBRS */
#define CPUIDEBX_STIBP (1ULL << 15) /* Speculation Control STIBP */
#define CPUIDEBX_IBRS_ALWAYSON (1ULL << 16) /* IBRS always on mode */
#define CPUIDEBX_STIBP_ALWAYSON (1ULL << 17) /* STIBP always on mode */
#define CPUIDEBX_IBRS_PREF (1ULL << 18) /* IBRS preferred */
#define CPUIDEBX_IBRS_SAME_MODE (1ULL << 19) /* IBRS not mode-specific */
#define CPUIDEBX_SSBD (1ULL << 24) /* Speculation Control SSBD */
#define CPUIDEBX_VIRT_SSBD (1ULL << 25) /* Virt Spec Control SSBD */
#define CPUIDEBX_SSBD_NOTREQ (1ULL << 26) /* SSBD not required */
@ -590,6 +592,7 @@
#define MSR_DE_CFG 0xc0011029 /* Decode Configuration */
#define DE_CFG_721 0x00000001 /* errata 721 */
#define DE_CFG_SERIALIZE_LFENCE (1 << 1) /* Enable serializing lfence */
#define DE_CFG_SERIALIZE_9 (1 << 9) /* Zenbleed chickenbit */
#define IPM_C1E_CMP_HLT 0x10000000
#define IPM_SMI_CMP_HLT 0x08000000

3
sys/arch/amd64/isa/clock.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: clock.c,v 1.39 2023/02/04 19:19:36 cheloha Exp $ */
/* $OpenBSD: clock.c,v 1.40 2023/07/25 18:16:19 cheloha Exp $ */
/* $NetBSD: clock.c,v 1.1 2003/04/26 18:39:50 fvdl Exp $ */
/*-
@ -519,7 +519,6 @@ setstatclockrate(int arg)
mc146818_write(NULL, MC_REGA,
MC_BASE_32_KHz | MC_RATE_1024_Hz);
}
clockintr_setstatclockrate(arg);
}
void

4
sys/arch/amd64/stand/boot/conf.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: conf.c,v 1.56 2023/04/25 10:06:12 kn Exp $ */
/* $OpenBSD: conf.c,v 1.57 2023/07/22 10:11:19 jsg Exp $ */
/*
* Copyright (c) 1996 Michael Shalayeff
@ -41,7 +41,7 @@
#include <biosdev.h>
#include <dev/cons.h>
const char version[] = "3.56";
const char version[] = "3.65";
int debug = 1;

4
sys/arch/amd64/stand/cdboot/conf.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: conf.c,v 1.50 2023/04/25 10:06:12 kn Exp $ */
/* $OpenBSD: conf.c,v 1.51 2023/07/22 10:11:19 jsg Exp $ */
/*
* Copyright (c) 2004 Tom Cosgrove
@ -42,7 +42,7 @@
#include <biosdev.h>
#include <dev/cons.h>
const char version[] = "3.56";
const char version[] = "3.65";
int debug = 1;

4
sys/arch/amd64/stand/efiboot/conf.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: conf.c,v 1.41 2023/04/25 10:11:20 kn Exp $ */
/* $OpenBSD: conf.c,v 1.42 2023/07/22 10:11:19 jsg Exp $ */
/*
* Copyright (c) 1996 Michael Shalayeff
@ -40,7 +40,7 @@
#include "efidev.h"
#include "efipxe.h"
const char version[] = "3.64";
const char version[] = "3.65";
#ifdef EFI_DEBUG
int debug = 0;

23
sys/arch/amd64/stand/efiboot/exec_i386.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: exec_i386.c,v 1.10 2023/02/23 19:48:21 miod Exp $ */
/* $OpenBSD: exec_i386.c,v 1.11 2023/07/22 10:11:19 jsg Exp $ */
/*
* Copyright (c) 1997-1998 Michael Shalayeff
@ -180,7 +180,8 @@ ucode_load(void)
CPUID(0, dummy, vendor[0], vendor[2], vendor[1]);
vendor[3] = 0; /* NULL-terminate */
if (strcmp((char *)vendor, "GenuineIntel") != 0)
if (strcmp((char *)vendor, "GenuineIntel") != 0 &&
strcmp((char *)vendor, "AuthenticAMD") != 0)
return;
CPUID(1, signature, dummy, dummy, dummy);
@ -192,8 +193,22 @@ ucode_load(void)
}
stepping = (signature >> 0) & 0x0f;
snprintf(path, sizeof(path), "%s:/etc/firmware/intel/%02x-%02x-%02x",
cmd.bootdev, family, model, stepping);
if (strcmp((char *)vendor, "GenuineIntel") == 0) {
snprintf(path, sizeof(path),
"%s:/etc/firmware/intel/%02x-%02x-%02x",
cmd.bootdev, family, model, stepping);
} else if (strcmp((char *)vendor, "AuthenticAMD") == 0) {
if (family < 0x10)
return;
else if (family <= 0x14)
snprintf(path, sizeof(path),
"%s:/etc/firmware/amd/microcode_amd.bin",
cmd.bootdev);
else
snprintf(path, sizeof(path),
"%s:/etc/firmware/amd/microcode_amd_fam%02xh.bin",
cmd.bootdev, family);
}
fd = open(path, O_RDONLY);
if (fd == -1)

23
sys/arch/amd64/stand/libsa/exec_i386.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: exec_i386.c,v 1.37 2022/07/11 19:45:02 kettenis Exp $ */
/* $OpenBSD: exec_i386.c,v 1.38 2023/07/22 10:11:19 jsg Exp $ */
/*
* Copyright (c) 1997-1998 Michael Shalayeff
@ -202,7 +202,8 @@ ucode_load(void)
CPUID(0, dummy, vendor[0], vendor[2], vendor[1]);
vendor[3] = 0; /* NULL-terminate */
if (strcmp((char *)vendor, "GenuineIntel") != 0)
if (strcmp((char *)vendor, "GenuineIntel") != 0 &&
strcmp((char *)vendor, "AuthenticAMD") != 0)
return;
CPUID(1, signature, dummy, dummy, dummy);
@ -214,8 +215,22 @@ ucode_load(void)
}
stepping = (signature >> 0) & 0x0f;
snprintf(path, sizeof(path), "%s:/etc/firmware/intel/%02x-%02x-%02x",
cmd.bootdev, family, model, stepping);
if (strcmp((char *)vendor, "GenuineIntel") == 0) {
snprintf(path, sizeof(path),
"%s:/etc/firmware/intel/%02x-%02x-%02x",
cmd.bootdev, family, model, stepping);
} else if (strcmp((char *)vendor, "AuthenticAMD") == 0) {
if (family < 0x10)
return;
else if (family <= 0x14)
snprintf(path, sizeof(path),
"%s:/etc/firmware/amd/microcode_amd.bin",
cmd.bootdev);
else
snprintf(path, sizeof(path),
"%s:/etc/firmware/amd/microcode_amd_fam%02xh.bin",
cmd.bootdev, family);
}
fd = open(path, O_RDONLY);
if (fd == -1)

4
sys/arch/amd64/stand/pxeboot/conf.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: conf.c,v 1.55 2023/04/25 10:06:12 kn Exp $ */
/* $OpenBSD: conf.c,v 1.56 2023/07/22 10:11:20 jsg Exp $ */
/*
* Copyright (c) 2004 Tom Cosgrove
@ -44,7 +44,7 @@
#include "pxeboot.h"
#include "pxe_net.h"
const char version[] = "3.56";
const char version[] = "3.65";
int debug = 0;
void (*sa_cleanup)(void) = pxe_shutdown;

3
sys/arch/arm/cortex/agtimer.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: agtimer.c,v 1.17 2023/02/04 19:19:36 cheloha Exp $ */
/* $OpenBSD: agtimer.c,v 1.18 2023/07/25 18:16:19 cheloha Exp $ */
/*
* Copyright (c) 2011 Dale Rahn <drahn@openbsd.org>
* Copyright (c) 2013 Patrick Wildt <patrick@blueri.se>
@ -288,7 +288,6 @@ agtimer_delay(u_int usecs)
void
agtimer_setstatclockrate(int newhz)
{
clockintr_setstatclockrate(newhz);
}
void

3
sys/arch/arm/cortex/amptimer.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: amptimer.c,v 1.16 2023/02/04 19:19:36 cheloha Exp $ */
/* $OpenBSD: amptimer.c,v 1.17 2023/07/25 18:16:19 cheloha Exp $ */
/*
* Copyright (c) 2011 Dale Rahn <drahn@openbsd.org>
*
@ -343,7 +343,6 @@ amptimer_delay(u_int usecs)
void
amptimer_setstatclockrate(int newhz)
{
clockintr_setstatclockrate(newhz);
}
void

3
sys/arch/arm/include/cpu.h
View file

@ -1,4 +1,4 @@
/* $OpenBSD: cpu.h,v 1.62 2023/01/17 02:27:14 cheloha Exp $ */
/* $OpenBSD: cpu.h,v 1.63 2023/07/25 18:16:19 cheloha Exp $ */
/* $NetBSD: cpu.h,v 1.34 2003/06/23 11:01:08 martin Exp $ */
/*
@ -198,6 +198,7 @@ struct cpu_info {
#ifdef GPROF
struct gmonparam *ci_gmon;
struct clockintr *ci_gmonclock;
#endif
struct clockintr_queue ci_queue;
char ci_panicbuf[512];

3
sys/arch/arm64/conf/GENERIC
View file

@ -1,4 +1,4 @@
# $OpenBSD: GENERIC,v 1.276 2023/07/19 20:27:20 kettenis Exp $
# $OpenBSD: GENERIC,v 1.277 2023/07/22 22:43:53 patrick Exp $
#
# GENERIC machine description file
#
@ -346,6 +346,7 @@ qcpon* at qcpmic?
qcpwm* at qcpmic?
qcrng* at fdt?
qcrtc* at qcpmic?
qcsdam* at qcpmic?
# Sunxi SoCs
sxipio* at fdt? early 1 # GPIO pins for leds & PHYs

3
sys/arch/arm64/conf/RAMDISK
View file

@ -1,4 +1,4 @@
# $OpenBSD: RAMDISK,v 1.208 2023/07/19 20:27:20 kettenis Exp $
# $OpenBSD: RAMDISK,v 1.209 2023/07/22 22:43:53 patrick Exp $
machine arm64
maxusers 4
@ -269,6 +269,7 @@ qcpon* at qcpmic?
qcpwm* at qcpmic?
qcrng* at fdt?
qcrtc* at qcpmic?
qcsdam* at qcpmic?
# Sunxi SoCs
sxipio* at fdt? early 1 # GPIO pins for leds & PHYs

3
sys/arch/arm64/dev/agtimer.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: agtimer.c,v 1.22 2023/02/04 19:19:36 cheloha Exp $ */
/* $OpenBSD: agtimer.c,v 1.23 2023/07/25 18:16:19 cheloha Exp $ */
/*
* Copyright (c) 2011 Dale Rahn <drahn@openbsd.org>
* Copyright (c) 2013 Patrick Wildt <patrick@blueri.se>
@ -354,7 +354,6 @@ agtimer_delay(u_int usecs)
void
agtimer_setstatclockrate(int newhz)
{
clockintr_setstatclockrate(newhz);
}
void

95
sys/arch/arm64/dev/apldart.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: apldart.c,v 1.16 2022/07/21 18:24:24 kettenis Exp $ */
/* $OpenBSD: apldart.c,v 1.17 2023/07/23 11:47:20 kettenis Exp $ */
/*
* Copyright (c) 2021 Mark Kettenis <kettenis@openbsd.org>
*
@ -28,6 +28,7 @@
#include <dev/ofw/openfirm.h>
#include <dev/ofw/ofw_misc.h>
#include <dev/ofw/ofw_power.h>
#include <dev/ofw/fdt.h>
/*
@ -161,6 +162,8 @@ struct apldart_softc {
struct machine_bus_dma_tag sc_bus_dmat;
struct iommu_device sc_id;
int sc_do_suspend;
};
struct apldart_map_state {
@ -187,9 +190,11 @@ void apldart_dmamem_free(bus_dma_tag_t, struct apldart_dmamem *);
int apldart_match(struct device *, void *, void *);
void apldart_attach(struct device *, struct device *, void *);
int apldart_activate(struct device *, int);
const struct cfattach apldart_ca = {
sizeof (struct apldart_softc), apldart_match, apldart_attach
sizeof (struct apldart_softc), apldart_match, apldart_attach, NULL,
apldart_activate
};
struct cfdriver apldart_cd = {
@ -255,8 +260,10 @@ apldart_attach(struct device *parent, struct device *self, void *aux)
}
sc->sc_dmat = faa->fa_dmat;
sc->sc_node = faa->fa_node;
power_domain_enable(sc->sc_node);
if (OF_is_compatible(sc->sc_node, "apple,t8110-dart")) {
params4 = HREAD4(sc, DART_T8110_PARAMS4);
sc->sc_nsid = params4 & DART_T8110_PARAMS4_NSID_MASK;
@ -321,6 +328,11 @@ apldart_attach(struct device *parent, struct device *self, void *aux)
}
}
/*
* We have full control over this DART, so do suspend it.
*/
sc->sc_do_suspend = 1;
/*
* Use bypass mode if supported. This avoids an issue with
* the USB3 controllers which need mappings entered into two
@ -433,6 +445,83 @@ apldart_attach(struct device *parent, struct device *self, void *aux)
iommu_device_register(&sc->sc_id);
}
void
apldart_suspend(struct apldart_softc *sc)
{
if (!sc->sc_do_suspend)
return;
power_domain_disable(sc->sc_node);
}
void
apldart_resume(struct apldart_softc *sc)
{
paddr_t pa;
int ntte, nl1, nl2;
uint32_t params2;
int sid, idx;
if (!sc->sc_do_suspend)
return;
power_domain_enable(sc->sc_node);
params2 = HREAD4(sc, DART_PARAMS2);
if (params2 & DART_PARAMS2_BYPASS_SUPPORT) {
for (sid = 0; sid < sc->sc_nsid; sid++)
HWRITE4(sc, DART_TCR(sc, sid), sc->sc_tcr_bypass);
return;
}
ntte = howmany(sc->sc_dvaend, DART_PAGE_SIZE);
nl2 = howmany(ntte, DART_PAGE_SIZE / sizeof(uint64_t));
nl1 = howmany(nl2, DART_PAGE_SIZE / sizeof(uint64_t));
/* Install page tables. */
for (sid = 0; sid < sc->sc_nsid; sid++) {
pa = APLDART_DMA_DVA(sc->sc_l1);
for (idx = 0; idx < nl1; idx++) {
HWRITE4(sc, DART_TTBR(sc, sid, idx),
(pa >> DART_TTBR_SHIFT) | sc->sc_ttbr_valid);
pa += DART_PAGE_SIZE;
}
}
sc->sc_flush_tlb(sc);
/* Enable all streams. */
for (idx = 0; idx < howmany(sc->sc_nsid, 32); idx++)
HWRITE4(sc, DART_SID_ENABLE(sc, idx), ~0);
/* Enable translations. */
for (sid = 0; sid < sc->sc_nsid; sid++)
HWRITE4(sc, DART_TCR(sc, sid), sc->sc_tcr_translate_enable);
if (OF_is_compatible(sc->sc_node, "apple,t8110-dart")) {
HWRITE4(sc, DART_T8110_ERROR, HREAD4(sc, DART_T8110_ERROR));
HWRITE4(sc, DART_T8110_ERROR_MASK, 0);
} else {
HWRITE4(sc, DART_T8020_ERROR, HREAD4(sc, DART_T8020_ERROR));
}
}
int
apldart_activate(struct device *self, int act)
{
struct apldart_softc *sc = (struct apldart_softc *)self;
switch (act) {
case DVACT_SUSPEND:
apldart_suspend(sc);
break;
case DVACT_RESUME:
apldart_resume(sc);
break;
}
return 0;
}
bus_dma_tag_t
apldart_map(void *cookie, uint32_t *cells, bus_dma_tag_t dmat)
{

23
sys/arch/arm64/dev/apldma.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: apldma.c,v 1.5 2022/11/26 21:35:22 kettenis Exp $ */
/* $OpenBSD: apldma.c,v 1.6 2023/07/26 11:09:24 kettenis Exp $ */
/*
* Copyright (c) 2022 Mark Kettenis <kettenis@openbsd.org>
*
@ -110,9 +110,11 @@ struct apldma_softc *apldma_sc;
int apldma_match(struct device *, void *, void *);
void apldma_attach(struct device *, struct device *, void *);
int apldma_activate(struct device *, int);
const struct cfattach apldma_ca = {
sizeof (struct apldma_softc), apldma_match, apldma_attach
sizeof (struct apldma_softc), apldma_match, apldma_attach, NULL,
apldma_activate
};
struct cfdriver apldma_cd = {
@ -197,6 +199,23 @@ unmap:
bus_space_unmap(sc->sc_iot, sc->sc_ioh, faa->fa_reg[0].size);
}
int
apldma_activate(struct device *self, int act)
{
struct apldma_softc *sc = (struct apldma_softc *)self;
switch (act) {
case DVACT_SUSPEND:
power_domain_disable(sc->sc_node);
break;
case DVACT_RESUME:
power_domain_enable(sc->sc_node);
break;
}
return 0;
}
void
apldma_fill_descriptors(struct apldma_channel *ac)
{

5
sys/arch/arm64/dev/aplmbox.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: aplmbox.c,v 1.5 2022/12/21 22:30:42 kettenis Exp $ */
/* $OpenBSD: aplmbox.c,v 1.6 2023/07/23 11:17:49 kettenis Exp $ */
/*
* Copyright (c) 2021 Mark Kettenis <kettenis@openbsd.org>
*
@ -25,6 +25,7 @@
#include <dev/ofw/openfirm.h>
#include <dev/ofw/ofw_misc.h>
#include <dev/ofw/ofw_power.h>
#include <dev/ofw/fdt.h>
#include <arm64/dev/aplmbox.h>
@ -111,6 +112,8 @@ aplmbox_attach(struct device *parent, struct device *self, void *aux)
printf("\n");
power_domain_enable(faa->fa_node);
sc->sc_md.md_node = faa->fa_node;
sc->sc_md.md_cookie = sc;
sc->sc_md.md_channel = aplmbox_channel;

32
sys/arch/arm64/dev/aplmca.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: aplmca.c,v 1.6 2023/02/03 13:20:21 kettenis Exp $ */
/* $OpenBSD: aplmca.c,v 1.7 2023/07/26 11:09:24 kettenis Exp $ */
/*
* Copyright (c) 2022 Mark Kettenis <kettenis@openbsd.org>
*
@ -152,9 +152,11 @@ const struct audio_hw_if aplmca_hw_if = {
int aplmca_match(struct device *, void *, void *);
void aplmca_attach(struct device *, struct device *, void *);
int aplmca_activate(struct device *, int);
const struct cfattach aplmca_ca = {
sizeof (struct aplmca_softc), aplmca_match, aplmca_attach
sizeof (struct aplmca_softc), aplmca_match, aplmca_attach, NULL,
aplmca_activate
};
struct cfdriver aplmca_cd = {
@ -223,6 +225,32 @@ aplmca_attach(struct device *parent, struct device *self, void *aux)
}
}
int
aplmca_activate(struct device *self, int act)
{
struct aplmca_softc *sc = (struct aplmca_softc *)self;
int i;
switch (act) {
case DVACT_SUSPEND:
for (i = 0; i < sc->sc_nclusters; i++) {
if (sc->sc_ad[i].ad_ac)
power_domain_disable_idx(sc->sc_node, i + 1);
}
power_domain_disable_idx(sc->sc_node, 0);
break;
case DVACT_RESUME:
power_domain_enable_idx(sc->sc_node, 0);
for (i = 0; i < sc->sc_nclusters; i++) {
if (sc->sc_ad[i].ad_ac)
power_domain_enable_idx(sc->sc_node, i + 1);
}
break;
}
return 0;
}
int
aplmca_dai_init(struct aplmca_softc *sc, int port)
{

5
sys/arch/arm64/dev/aplpinctrl.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: aplpinctrl.c,v 1.7 2023/03/23 11:40:42 jsg Exp $ */
/* $OpenBSD: aplpinctrl.c,v 1.8 2023/07/23 11:17:50 kettenis Exp $ */
/*
* Copyright (c) 2021 Mark Kettenis <kettenis@openbsd.org>
*
@ -28,6 +28,7 @@
#include <dev/ofw/openfirm.h>
#include <dev/ofw/ofw_gpio.h>
#include <dev/ofw/ofw_pinctrl.h>
#include <dev/ofw/ofw_power.h>
#include <dev/ofw/fdt.h>
#define APPLE_PIN(pinmux) ((pinmux) & 0xffff)
@ -136,6 +137,8 @@ aplpinctrl_attach(struct device *parent, struct device *self, void *aux)
return;
}
power_domain_enable(faa->fa_node);
pinctrl_register(faa->fa_node, aplpinctrl_pinctrl, sc);
OF_getpropintarray(faa->fa_node, "gpio-ranges",

4
sys/arch/arm64/dev/aplspi.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: aplspi.c,v 1.4 2022/04/06 18:59:26 naddy Exp $ */
/* $OpenBSD: aplspi.c,v 1.5 2023/07/23 11:17:50 kettenis Exp $ */
/*
* Copyright (c) 2021 Mark Kettenis <kettenis@openbsd.org>
*
@ -30,6 +30,7 @@
#include <dev/ofw/ofw_clock.h>
#include <dev/ofw/ofw_gpio.h>
#include <dev/ofw/ofw_pinctrl.h>
#include <dev/ofw/ofw_power.h>
#include <dev/ofw/fdt.h>
#define SPI_CLKCFG 0x00
@ -147,6 +148,7 @@ aplspi_attach(struct device *parent, struct device *self, void *aux)
sc->sc_pfreq = clock_get_frequency(sc->sc_node, NULL);
power_domain_enable(sc->sc_node);
pinctrl_byname(sc->sc_node, "default");
/* Configure CS# pin for manual control. */

3
sys/arch/arm64/include/cpu.h
View file

@ -1,4 +1,4 @@
/* $OpenBSD: cpu.h,v 1.37 2023/07/13 08:33:36 kettenis Exp $ */
/* $OpenBSD: cpu.h,v 1.38 2023/07/25 18:16:20 cheloha Exp $ */
/*
* Copyright (c) 2016 Dale Rahn <drahn@dalerahn.com>
*
@ -172,6 +172,7 @@ struct cpu_info {
#ifdef GPROF
struct gmonparam *ci_gmon;
struct clockintr *ci_gmonclock;
#endif
struct clockintr_queue ci_queue;
char ci_panicbuf[512];

3
sys/arch/armv7/omap/dmtimer.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: dmtimer.c,v 1.18 2023/02/04 19:19:36 cheloha Exp $ */
/* $OpenBSD: dmtimer.c,v 1.19 2023/07/25 18:16:19 cheloha Exp $ */
/*
* Copyright (c) 2007,2009 Dale Rahn <drahn@openbsd.org>
* Copyright (c) 2013 Raphael Graf <r@undefined.ch>
@ -317,7 +317,6 @@ dmtimer_delay(u_int usecs)
void
dmtimer_setstatclockrate(int newhz)
{
clockintr_setstatclockrate(newhz);
}

3
sys/arch/armv7/omap/gptimer.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: gptimer.c,v 1.19 2023/02/04 19:19:36 cheloha Exp $ */
/* $OpenBSD: gptimer.c,v 1.20 2023/07/25 18:16:19 cheloha Exp $ */
/*
* Copyright (c) 2007,2009 Dale Rahn <drahn@openbsd.org>
*
@ -326,7 +326,6 @@ gptimer_delay(u_int usecs)
void
gptimer_setstatclockrate(int newhz)
{
clockintr_setstatclockrate(newhz);
}

3
sys/arch/armv7/sunxi/sxitimer.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: sxitimer.c,v 1.20 2023/02/04 19:19:36 cheloha Exp $ */
/* $OpenBSD: sxitimer.c,v 1.21 2023/07/25 18:16:19 cheloha Exp $ */
/*
* Copyright (c) 2007,2009 Dale Rahn <drahn@openbsd.org>
* Copyright (c) 2013 Raphael Graf <r@undefined.ch>
@ -299,7 +299,6 @@ sxitimer_delay(u_int usecs)
void
sxitimer_setstatclockrate(int newhz)
{
clockintr_setstatclockrate(newhz);
}
u_int

21
sys/arch/i386/i386/machdep.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: machdep.c,v 1.663 2023/01/30 10:49:05 jsg Exp $ */
/* $OpenBSD: machdep.c,v 1.665 2023/07/25 04:42:02 deraadt Exp $ */
/* $NetBSD: machdep.c,v 1.214 1996/11/10 03:16:17 thorpej Exp $ */
/*-
@ -1639,6 +1639,7 @@ identifycpu(struct cpu_info *ci)
char *cpu_device = ci->ci_dev->dv_xname;
int skipspace;
extern uint32_t cpu_meltdown;
uint64_t msr, nmsr;
if (cpuid_level == -1) {
name = "486DX";
@ -1987,13 +1988,17 @@ identifycpu(struct cpu_info *ci)
*/
if (!strcmp(cpu_vendor, "AuthenticAMD")) {
if (ci->ci_family >= 0x10 && ci->ci_family != 0x11) {
uint64_t msr;
msr = rdmsr(MSR_DE_CFG);
if ((msr & DE_CFG_SERIALIZE_LFENCE) == 0) {
msr |= DE_CFG_SERIALIZE_LFENCE;
wrmsr(MSR_DE_CFG, msr);
}
nmsr = msr = rdmsr(MSR_DE_CFG);
nmsr |= DE_CFG_SERIALIZE_LFENCE;
if (msr != nmsr)
wrmsr(MSR_DE_CFG, nmsr);
}
if (family == 0x17 && ci->ci_model >= 0x31 &&
(cpu_ecxfeature & CPUIDECX_HV) == 0) {
nmsr = msr = rdmsr(MSR_DE_CFG);
nmsr |= DE_CFG_SERIALIZE_9;
if (msr != nmsr)
wrmsr(MSR_DE_CFG, nmsr);
}
}

104
sys/arch/i386/i386/ucode.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: ucode.c,v 1.3 2020/12/15 22:51:34 kettenis Exp $ */
/* $OpenBSD: ucode.c,v 1.4 2023/07/23 02:59:53 jsg Exp $ */
/*
* Copyright (c) 2018 Stefan Fritsch <fritsch@genua.de>
* Copyright (c) 2018 Patrick Wildt <patrick@blueri.se>
@ -72,6 +72,8 @@ size_t cpu_ucode_size;
void cpu_ucode_setup(void);
void cpu_ucode_apply(struct cpu_info *);
struct mutex cpu_ucode_mtx = MUTEX_INITIALIZER(IPL_HIGH);
/* Intel */
void cpu_ucode_intel_apply(struct cpu_info *);
struct intel_ucode_header *
@ -82,7 +84,8 @@ int cpu_ucode_intel_match(struct intel_ucode_header *, uint32_t, uint32_t,
uint32_t cpu_ucode_intel_rev(void);
struct intel_ucode_header *cpu_ucode_intel_applied;
struct mutex cpu_ucode_intel_mtx = MUTEX_INITIALIZER(IPL_HIGH);
void cpu_ucode_amd_apply(struct cpu_info *);
void
cpu_ucode_setup(void)
@ -130,6 +133,99 @@ cpu_ucode_apply(struct cpu_info *ci)
{
if (strcmp(cpu_vendor, "GenuineIntel") == 0)
cpu_ucode_intel_apply(ci);
else if (strcmp(cpu_vendor, "AuthenticAMD") == 0)
cpu_ucode_amd_apply(ci);
}
#define AMD_MAGIC 0x00414d44
struct amd_equiv {
uint32_t id;
uint32_t a;
uint32_t b;
uint16_t eid;
uint16_t c;
} __packed;
struct amd_patch {
uint32_t type;
uint32_t len;
uint32_t a;
uint32_t level;
uint8_t c[16];
uint16_t eid;
} __packed;
void
cpu_ucode_amd_apply(struct cpu_info *ci)
{
uint64_t level;
uint32_t magic, tlen, i;
uint16_t eid = 0;
uint32_t sig, ebx, ecx, edx;
uint64_t start = 0;
if (cpu_ucode_data == NULL || cpu_ucode_size == 0) {
DPRINTF(("%s: no microcode provided\n", __func__));
return;
}
/*
* Grab a mutex, because we are not allowed to run updates
* simultaneously on HT siblings.
*/
mtx_enter(&cpu_ucode_mtx);
CPUID(1, sig, ebx, ecx, edx);
level = rdmsr(MSR_PATCH_LEVEL);
DPRINTF(("%s: cur patch level 0x%llx\n", __func__, level));
memcpy(&magic, cpu_ucode_data, 4);
if (magic != AMD_MAGIC) {
DPRINTF(("%s: bad magic %x\n", __func__, magic));
goto out;
}
memcpy(&tlen, &cpu_ucode_data[8], 4);
/* find equivalence id matching our cpu signature */
for (i = 12; i < 12 + tlen;) {
struct amd_equiv ae;
if (i + sizeof(ae) > cpu_ucode_size) {
DPRINTF(("%s: truncated etable\n", __func__));
goto out;
}
memcpy(&ae, &cpu_ucode_data[i], sizeof(ae));
i += sizeof(ae);
if (ae.id == sig)
eid = ae.eid;
}
/* look for newer patch with the equivalence id */
while (i < cpu_ucode_size) {
struct amd_patch ap;
if (i + sizeof(ap) > cpu_ucode_size) {
DPRINTF(("%s: truncated ptable\n", __func__));
goto out;
}
memcpy(&ap, &cpu_ucode_data[i], sizeof(ap));
if (ap.type == 1 && ap.eid == eid && ap.level > level)
start = (uint64_t)&cpu_ucode_data[i + 8];
if (i + ap.len + 8 > cpu_ucode_size) {
DPRINTF(("%s: truncated patch\n", __func__));
goto out;
}
i += ap.len + 8;
}
if (start != 0) {
wrmsr(MSR_PATCH_LOADER, start);
level = rdmsr(MSR_PATCH_LEVEL);
DPRINTF(("%s: new patch level 0x%llx\n", __func__, level));
}
out:
mtx_leave(&cpu_ucode_mtx);
}
void
@ -148,7 +244,7 @@ cpu_ucode_intel_apply(struct cpu_info *ci)
* Grab a mutex, because we are not allowed to run updates
* simultaneously on HT siblings.
*/
mtx_enter(&cpu_ucode_intel_mtx);
mtx_enter(&cpu_ucode_mtx);
old_rev = cpu_ucode_intel_rev();
update = cpu_ucode_intel_applied;
@ -182,7 +278,7 @@ cpu_ucode_intel_apply(struct cpu_info *ci)
}
out:
mtx_leave(&cpu_ucode_intel_mtx);
mtx_leave(&cpu_ucode_mtx);
}
struct intel_ucode_header *

3
sys/arch/i386/include/cpu.h
View file

@ -1,4 +1,4 @@
/* $OpenBSD: cpu.h,v 1.181 2022/12/06 01:56:44 cheloha Exp $ */
/* $OpenBSD: cpu.h,v 1.182 2023/07/25 18:16:20 cheloha Exp $ */
/* $NetBSD: cpu.h,v 1.35 1996/05/05 19:29:26 christos Exp $ */
/*-
@ -168,6 +168,7 @@ struct cpu_info {
struct ksensor ci_sensor;
#if defined(GPROF) || defined(DDBPROF)
struct gmonparam *ci_gmon;
struct clockintr *ci_gmonclock;
#endif
struct clockintr_queue ci_queue;
char ci_panicbuf[512];

3
sys/arch/i386/include/specialreg.h
View file

@ -1,4 +1,4 @@
/* $OpenBSD: specialreg.h,v 1.82 2023/07/21 04:04:52 guenther Exp $ */
/* $OpenBSD: specialreg.h,v 1.83 2023/07/24 14:54:00 deraadt Exp $ */
/* $NetBSD: specialreg.h,v 1.7 1994/10/27 04:16:26 cgd Exp $ */
/*-
@ -529,6 +529,7 @@
#define MSR_DE_CFG 0xc0011029 /* Decode Configuration */
#define DE_CFG_721 0x00000001 /* errata 721 */
#define DE_CFG_SERIALIZE_LFENCE (1 << 1) /* Enable serializing lfence */
#define DE_CFG_SERIALIZE_9 (1 << 9) /* Zenbleed chickenbit */
#define IPM_C1E_CMP_HLT 0x10000000
#define IPM_SMI_CMP_HLT 0x08000000

3
sys/arch/i386/isa/clock.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: clock.c,v 1.64 2023/02/04 19:19:36 cheloha Exp $ */
/* $OpenBSD: clock.c,v 1.65 2023/07/25 18:16:20 cheloha Exp $ */
/* $NetBSD: clock.c,v 1.39 1996/05/12 23:11:54 mycroft Exp $ */
/*-
@ -663,7 +663,6 @@ setstatclockrate(int arg)
mc146818_write(NULL, MC_REGA,
MC_BASE_32_KHz | MC_RATE_1024_Hz);
}
clockintr_setstatclockrate(arg);
}
void

4
sys/arch/i386/stand/boot/conf.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: conf.c,v 1.77 2023/04/25 14:48:16 kn Exp $ */
/* $OpenBSD: conf.c,v 1.78 2023/07/22 10:11:20 jsg Exp $ */
/*
* Copyright (c) 1996 Michael Shalayeff
@ -42,7 +42,7 @@
#include <dev/cons.h>
#include "debug.h"
const char version[] = "3.45";
const char version[] = "3.65";
int debug = 1;

4
sys/arch/i386/stand/cdboot/conf.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: conf.c,v 1.44 2023/04/25 14:48:17 kn Exp $ */
/* $OpenBSD: conf.c,v 1.45 2023/07/22 10:11:20 jsg Exp $ */
/*
* Copyright (c) 2004 Tom Cosgrove
@ -43,7 +43,7 @@
#include <dev/cons.h>
#include "debug.h"
const char version[] = "3.45";
const char version[] = "3.65";
int debug = 1;
void (*sa_cleanup)(void) = NULL;

23
sys/arch/i386/stand/libsa/exec_i386.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: exec_i386.c,v 1.52 2022/07/07 00:56:47 daniel Exp $ */
/* $OpenBSD: exec_i386.c,v 1.53 2023/07/22 10:11:20 jsg Exp $ */
/*
* Copyright (c) 1997-1998 Michael Shalayeff
@ -190,7 +190,8 @@ ucode_load(void)
CPUID(0, dummy, vendor[0], vendor[2], vendor[1]);
vendor[3] = 0; /* NULL-terminate */
if (strcmp((char *)vendor, "GenuineIntel") != 0)
if (strcmp((char *)vendor, "GenuineIntel") != 0 &&
strcmp((char *)vendor, "AuthenticAMD") != 0)
return;
CPUID(1, signature, dummy, dummy, dummy);
@ -202,8 +203,22 @@ ucode_load(void)
}
stepping = (signature >> 0) & 0x0f;
snprintf(path, sizeof(path), "%s:/etc/firmware/intel/%02x-%02x-%02x",
cmd.bootdev, family, model, stepping);
if (strcmp((char *)vendor, "GenuineIntel") == 0) {
snprintf(path, sizeof(path),
"%s:/etc/firmware/intel/%02x-%02x-%02x",
cmd.bootdev, family, model, stepping);
} else if (strcmp((char *)vendor, "AuthenticAMD") == 0) {
if (family < 0x10)
return;
else if (family <= 0x14)
snprintf(path, sizeof(path),
"%s:/etc/firmware/amd/microcode_amd.bin",
cmd.bootdev);
else
snprintf(path, sizeof(path),
"%s:/etc/firmware/amd/microcode_amd_fam%02xh.bin",
cmd.bootdev, family);
}
fd = open(path, O_RDONLY);
if (fd == -1)

12
sys/arch/i386/stand/libsa/pciprobe.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: pciprobe.c,v 1.10 2014/03/29 18:09:29 guenther Exp $ */
/* $OpenBSD: pciprobe.c,v 1.11 2023/07/24 14:02:36 jsg Exp $ */
/*
* Copyright (c) 1997 Tobias Weingartner
@ -39,12 +39,12 @@ pciprobe(void)
{
bios_pciinfo_t bpi;
u_int32_t hw_chars, rev, rc, sig;
u_int32_t entry32;
u_int32_t entry32, lastbus;
/* PCI BIOS v2.0c+ - Installation Check */
__asm volatile(DOINT(0x1A) "; shll $8,%2; setc %b2"
: "=a" (hw_chars), "=b" (rev), "=c" (rc),
"=d" (sig), "=D" (entry32)
__asm volatile(DOINT(0x1A)
: "=a" (hw_chars), "=b" (rev), "=c" (lastbus),
"=d" (sig), "=D" (entry32), "=@ccc" (rc)
: "0" (0xB101), "4" (0x0)
: "cc");
@ -62,7 +62,7 @@ pciprobe(void)
bpi.pci_chars = hw_chars & 0xFFFF;
bpi.pci_rev = rev & 0xFFFF;
bpi.pci_entry32 = entry32;
bpi.pci_lastbus = (rc>>8) & 0xFF;
bpi.pci_lastbus = lastbus & 0xFF;
addbootarg(BOOTARG_PCIINFO, sizeof(bios_pciinfo_t), &bpi);
}

4
sys/arch/i386/stand/pxeboot/conf.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: conf.c,v 1.49 2023/04/25 14:48:17 kn Exp $ */
/* $OpenBSD: conf.c,v 1.50 2023/07/22 10:11:20 jsg Exp $ */
/*
* Copyright (c) 2004 Tom Cosgrove
@ -45,7 +45,7 @@
#include "pxeboot.h"
#include "pxe_net.h"
const char version[] = "3.45";
const char version[] = "3.65";
int debug = 1;
void (*sa_cleanup)(void) = pxe_shutdown;

9
sys/dev/fdt/exuart.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: exuart.c,v 1.11 2022/07/02 08:50:42 visa Exp $ */
/* $OpenBSD: exuart.c,v 1.12 2023/07/23 11:16:36 kettenis Exp $ */
/*
* Copyright (c) 2005 Dale Rahn <drahn@motorola.com>
*
@ -40,6 +40,7 @@
#include <dev/fdt/exuartreg.h>
#include <dev/ofw/openfirm.h>
#include <dev/ofw/ofw_power.h>
#include <dev/ofw/fdt.h>
#define DEVUNIT(x) (minor(x) & 0x7f)
@ -210,6 +211,10 @@ exuart_attach(struct device *parent, struct device *self, void *aux)
printf(": console");
}
printf("\n");
power_domain_enable(faa->fa_node);
if (OF_is_compatible(faa->fa_node, "apple,s5l-uart")) {
sc->sc_type = EXUART_TYPE_S5L;
sc->sc_rx_fifo_cnt_mask = EXUART_S5L_UFSTAT_RX_FIFO_CNT_MASK;
@ -270,8 +275,6 @@ exuart_attach(struct device *parent, struct device *self, void *aux)
if(sc->sc_si == NULL)
panic("%s: can't establish soft interrupt.",
sc->sc_dev.dv_xname);
printf("\n");
}
void

7
sys/dev/fdt/files.fdt
View file

@ -1,4 +1,4 @@
# $OpenBSD: files.fdt,v 1.195 2023/07/01 16:34:30 drahn Exp $
# $OpenBSD: files.fdt,v 1.196 2023/07/22 22:43:53 patrick Exp $
#
# Config file and device description for machine-independent FDT code.
# Included by ports that need it.
@ -761,6 +761,11 @@ device qcrtc
attach qcrtc at spmi
file dev/fdt/qcrtc.c qcrtc
# Qualcomm PMIC Shared Direct Access Memory
device qcsdam
attach qcsdam at spmi
file dev/fdt/qcsdam.c qcsdam
# TI TPS6598x Type-C controller
device tipd
attach tipd at i2c

25
sys/dev/fdt/qcrtc.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: qcrtc.c,v 1.2 2023/01/16 20:12:38 patrick Exp $ */
/* $OpenBSD: qcrtc.c,v 1.3 2023/07/22 22:48:35 patrick Exp $ */
/*
* Copyright (c) 2022 Patrick Wildt <patrick@blueri.se>
*
@ -25,6 +25,7 @@
#include <dev/fdt/spmivar.h>
#include <dev/ofw/openfirm.h>
#include <dev/ofw/ofw_misc.h>
#include <dev/ofw/fdt.h>
#include <dev/clock_subr.h>
@ -114,12 +115,14 @@ qcrtc_gettime(struct todr_chip_handle *handle, struct timeval *tv)
return error;
}
/* Retrieve RTC offset stored in UEFI. */
if (qcscm_uefi_rtc_get(&off) != 0)
return EIO;
/* Retrieve RTC offset from either NVRAM or UEFI. */
error = nvmem_read_cell(sc->sc_node, "offset", &off, sizeof(off));
if (error == ENXIO || (!error && off == 0))
error = qcscm_uefi_rtc_get(&off);
if (error)
return error;
/* Add RTC counter and 10y+1w to get seconds from epoch. */
tv->tv_sec = off + (reg + (10 * 365 * 86400 + 7 * 86400));
tv->tv_sec = off + reg;
tv->tv_usec = 0;
return 0;
}
@ -138,9 +141,11 @@ qcrtc_settime(struct todr_chip_handle *handle, struct timeval *tv)
return error;
}
/* Subtract RTC counter and 10y+1w to get offset for UEFI. */
off = tv->tv_sec - (reg + (10 * 365 * 86400 + 7 * 86400));
/* Store RTC offset in either NVRAM or UEFI. */
off = tv->tv_sec - reg;
error = nvmem_write_cell(sc->sc_node, "offset", &off, sizeof(off));
if (error == ENXIO)
error = qcscm_uefi_rtc_set(off);
/* Store offset in UEFI. */
return qcscm_uefi_rtc_set(off);
return error;
}

10
sys/dev/fdt/qcscm.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: qcscm.c,v 1.4 2023/05/17 23:12:04 patrick Exp $ */
/* $OpenBSD: qcscm.c,v 1.5 2023/07/22 22:48:35 patrick Exp $ */
/*
* Copyright (c) 2022 Patrick Wildt <patrick@blueri.se>
*
@ -90,6 +90,8 @@
#define EFI_VARIABLE_BOOTSERVICE_ACCESS 0x00000002
#define EFI_VARIABLE_RUNTIME_ACCESS 0x00000004
#define UNIX_GPS_EPOCH_OFFSET 315964800
struct qcscm_dmamem {
bus_dmamap_t qdm_map;
bus_dma_segment_t qdm_seg;
@ -703,7 +705,8 @@ qcscm_uefi_rtc_get(uint32_t *off)
&rtcinfosize) != 0)
return EIO;
*off = rtcinfo[0];
/* UEFI stores the offset based on GPS epoch */
*off = rtcinfo[0] + UNIX_GPS_EPOCH_OFFSET;
return 0;
}
@ -722,6 +725,9 @@ qcscm_uefi_rtc_set(uint32_t off)
&rtcinfosize) != 0)
return EIO;
/* UEFI stores the offset based on GPS epoch */
off -= UNIX_GPS_EPOCH_OFFSET;
/* No need to set if we're not changing anything */
if (rtcinfo[0] == off)
return 0;

119
sys/dev/fdt/qcsdam.c Normal file
View file

@ -0,0 +1,119 @@
/* $OpenBSD: qcsdam.c,v 1.1 2023/07/22 22:43:53 patrick Exp $ */
/*
* Copyright (c) 2023 Patrick Wildt <patrick@blueri.se>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <machine/bus.h>
#include <machine/fdt.h>
#include <dev/fdt/spmivar.h>
#include <dev/ofw/openfirm.h>
#include <dev/ofw/ofw_misc.h>
#include <dev/ofw/fdt.h>
struct qcsdam_softc {
struct device sc_dev;
spmi_tag_t sc_tag;
int8_t sc_sid;
uint16_t sc_addr;
struct nvmem_device sc_nd;
};
int qcsdam_match(struct device *, void *, void *);
void qcsdam_attach(struct device *, struct device *, void *);
const struct cfattach qcsdam_ca = {
sizeof (struct qcsdam_softc), qcsdam_match, qcsdam_attach
};
struct cfdriver qcsdam_cd = {
NULL, "qcsdam", DV_DULL
};
int qcsdam_nvmem_read(void *, bus_addr_t, void *, bus_size_t);
int qcsdam_nvmem_write(void *, bus_addr_t, const void *, bus_size_t);
int
qcsdam_match(struct device *parent, void *match, void *aux)
{
struct spmi_attach_args *saa = aux;
return OF_is_compatible(saa->sa_node, "qcom,spmi-sdam");
}
void
qcsdam_attach(struct device *parent, struct device *self, void *aux)
{
struct qcsdam_softc *sc = (struct qcsdam_softc *)self;
struct spmi_attach_args *saa = aux;
uint32_t reg;
if (OF_getpropintarray(saa->sa_node, "reg",
&reg, sizeof(reg)) != sizeof(reg)) {
printf(": can't find registers\n");
return;
}
sc->sc_tag = saa->sa_tag;
sc->sc_sid = saa->sa_sid;
sc->sc_addr = reg;
printf("\n");
sc->sc_nd.nd_node = saa->sa_node;
sc->sc_nd.nd_cookie = sc;
sc->sc_nd.nd_read = qcsdam_nvmem_read;
sc->sc_nd.nd_write = qcsdam_nvmem_write;
nvmem_register(&sc->sc_nd);
}
int
qcsdam_nvmem_read(void *cookie, bus_addr_t addr, void *data, bus_size_t size)
{
struct qcsdam_softc *sc = cookie;
int error;
error = spmi_cmd_read(sc->sc_tag, sc->sc_sid, SPMI_CMD_EXT_READL,
sc->sc_addr + addr, data, size);
if (error) {
printf("%s: error reading NVMEM\n", sc->sc_dev.dv_xname);
return error;
}
return 0;
}
int
qcsdam_nvmem_write(void *cookie, bus_addr_t addr, const void *data,
bus_size_t size)
{
struct qcsdam_softc *sc = cookie;
int error;
error = spmi_cmd_write(sc->sc_tag, sc->sc_sid, SPMI_CMD_EXT_WRITEL,
sc->sc_addr + addr, data, size);
if (error) {
printf("%s: error reading NVMEM\n", sc->sc_dev.dv_xname);
return error;
}
return 0;
}

28
sys/dev/fdt/tipd.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: tipd.c,v 1.2 2023/07/17 17:50:22 kettenis Exp $ */
/* $OpenBSD: tipd.c,v 1.3 2023/07/23 11:42:44 kettenis Exp $ */
/*
* Copyright (c) 2022 Mark Kettenis <kettenis@openbsd.org>
*
@ -42,6 +42,7 @@
#define TPS_SYSTEM_POWER_STATE 0x20
#define TPS_SYSTEM_POWER_STATE_S0 0
#define TPS_SYSTEM_POWER_STATE_S5 5
#define TPS_POWER_STATUS 0x3f
#define TPS_CMD(s) ((s[3] << 24) | (s[2] << 16) | (s[1] << 8) | s[0])
@ -59,6 +60,7 @@ struct tipd_softc {
void *sc_ih;
struct device_ports sc_ports;
uint32_t sc_status;
};
int tipd_match(struct device *, void *, void *);
@ -110,6 +112,7 @@ tipd_attach(struct device *parent, struct device *self, void *aux)
printf("\n");
tipd_read_4(sc, TPS_STATUS, &sc->sc_status);
tipd_write_8(sc, TPS_INT_MASK_1, CD_INT_PLUG_EVENT);
node = OF_getnodebyname(node, "connector");
@ -127,6 +130,9 @@ tipd_activate(struct device *self, int act)
int error;
switch (act) {
case DVACT_QUIESCE:
tipd_write_8(sc, TPS_INT_MASK_1, 0);
break;
case DVACT_SUSPEND:
state = TPS_SYSTEM_POWER_STATE_S5;
error = tipd_exec(sc, "SSPS", &state, sizeof(state), NULL, 0);
@ -139,6 +145,10 @@ tipd_activate(struct device *self, int act)
if (error)
printf("%s: powerup failed\n", sc->sc_dev.dv_xname);
break;
case DVACT_WAKEUP:
tipd_read_4(sc, TPS_STATUS, &sc->sc_status);
tipd_write_8(sc, TPS_INT_MASK_1, CD_INT_PLUG_EVENT);
break;
}
return 0;
@ -198,10 +208,18 @@ tipd_intr(void *arg)
if (error)
goto fail;
if (status & TPS_STATUS_PLUG_PRESENT)
tipd_connect(sc);
else
tipd_disconnect(sc);
/*
* We may get a spurious plug event upon resume. Make
* sure we only signal a new connection when the plug
* present state really changed.
*/
if ((status ^ sc->sc_status) & TPS_STATUS_PLUG_PRESENT) {
if (status & TPS_STATUS_PLUG_PRESENT)
tipd_connect(sc);
else
tipd_disconnect(sc);
sc->sc_status = status;
}
}
fail:

75
sys/dev/fdt/xhci_fdt.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: xhci_fdt.c,v 1.23 2023/04/03 01:55:00 dlg Exp $ */
/* $OpenBSD: xhci_fdt.c,v 1.24 2023/07/23 11:49:17 kettenis Exp $ */
/*
* Copyright (c) 2017 Mark Kettenis <kettenis@openbsd.org>
*
@ -56,13 +56,15 @@ struct xhci_fdt_softc {
int xhci_fdt_match(struct device *, void *, void *);
void xhci_fdt_attach(struct device *, struct device *, void *);
int xhci_fdt_activate(struct device *, int);
const struct cfattach xhci_fdt_ca = {
sizeof(struct xhci_fdt_softc), xhci_fdt_match, xhci_fdt_attach, NULL,
xhci_activate
xhci_fdt_activate
};
int xhci_cdns_init(struct xhci_fdt_softc *);
int xhci_cdns_attach(struct xhci_fdt_softc *);
int xhci_snps_attach(struct xhci_fdt_softc *);
int xhci_snps_init(struct xhci_fdt_softc *);
void xhci_init_phys(struct xhci_fdt_softc *);
@ -139,9 +141,9 @@ xhci_fdt_attach(struct device *parent, struct device *self, void *aux)
* functionality.
*/
if (OF_is_compatible(sc->sc_node, "cdns,usb3"))
error = xhci_cdns_init(sc);
error = xhci_cdns_attach(sc);
if (OF_is_compatible(sc->sc_node, "snps,dwc3"))
error = xhci_snps_init(sc);
error = xhci_snps_attach(sc);
if (error) {
printf(": can't initialize hardware\n");
goto disestablish_ret;
@ -170,6 +172,31 @@ unmap:
bus_space_unmap(sc->sc.iot, sc->sc.ioh, sc->sc.sc_size);
}
int
xhci_fdt_activate(struct device *self, int act)
{
struct xhci_fdt_softc *sc = (struct xhci_fdt_softc *)self;
int rv = 0;
switch (act) {
case DVACT_POWERDOWN:
rv = xhci_activate(self, act);
power_domain_disable(sc->sc_node);
break;
case DVACT_RESUME:
power_domain_enable(sc->sc_node);
if (OF_is_compatible(sc->sc_node, "snps,dwc3"))
xhci_snps_init(sc);
rv = xhci_activate(self, act);
break;
default:
rv = xhci_activate(self, act);
break;
}
return rv;
}
/*
* Cadence USB3 controller.
*/
@ -183,7 +210,7 @@ unmap:
#define OTG_STS_XHCI_READY (1 << 26)
int
xhci_cdns_init(struct xhci_fdt_softc *sc)
xhci_cdns_attach(struct xhci_fdt_softc *sc)
{
uint32_t did, sts;
int timo;
@ -251,6 +278,27 @@ xhci_snps_ep_get_cookie(void *cookie, struct endpoint *ep)
return cookie;
}
int
xhci_snps_attach(struct xhci_fdt_softc *sc)
{
/*
* On Apple hardware we need to reset the controller when we
* see a new connection.
*/
if (OF_is_compatible(sc->sc_node, "apple,dwc3")) {
sc->sc_usb_controller_port.up_cookie = sc;
sc->sc_usb_controller_port.up_connect = xhci_snps_connect;
task_set(&sc->sc_snps_connect_task, xhci_snps_do_connect, sc);
sc->sc_ports.dp_node = sc->sc_node;
sc->sc_ports.dp_cookie = &sc->sc_usb_controller_port;
sc->sc_ports.dp_ep_get_cookie = xhci_snps_ep_get_cookie;
device_ports_register(&sc->sc_ports, EP_USB_CONTROLLER_PORT);
}
return xhci_snps_init(sc);
}
int
xhci_snps_init(struct xhci_fdt_softc *sc)
{
@ -258,21 +306,6 @@ xhci_snps_init(struct xhci_fdt_softc *sc)
int node = sc->sc_node;
uint32_t reg;
/*
* On Apple hardware we need to reset the controller when we
* see a new connection.
*/
if (OF_is_compatible(node, "apple,dwc3")) {
sc->sc_usb_controller_port.up_cookie = sc;
sc->sc_usb_controller_port.up_connect = xhci_snps_connect;
task_set(&sc->sc_snps_connect_task, xhci_snps_do_connect, sc);
sc->sc_ports.dp_node = node;
sc->sc_ports.dp_cookie = &sc->sc_usb_controller_port;
sc->sc_ports.dp_ep_get_cookie = xhci_snps_ep_get_cookie;
device_ports_register(&sc->sc_ports, EP_USB_CONTROLLER_PORT);
}
/* We don't support device mode, so always force host mode. */
reg = bus_space_read_4(sc->sc.iot, sc->sc.ioh, USB3_GCTL);
reg &= ~USB3_GCTL_PRTCAPDIR_MASK;

14
sys/dev/ic/pckbc.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: pckbc.c,v 1.53 2019/11/30 18:18:34 cheloha Exp $ */
/* $OpenBSD: pckbc.c,v 1.54 2023/07/25 10:00:44 miod Exp $ */
/* $NetBSD: pckbc.c,v 1.5 2000/06/09 04:58:35 soda Exp $ */
/*
@ -514,12 +514,20 @@ pckbc_poll_data(pckbc_tag_t self, pckbc_slot_t slot)
* set scancode translation on
*/
int
pckbc_xt_translation(pckbc_tag_t self)
pckbc_xt_translation(pckbc_tag_t self, int *table)
{
struct pckbc_internal *t = self;
if (ISSET(t->t_flags, PCKBC_CANT_TRANSLATE))
#ifdef __sparc64__ /* only pckbc@ebus on sparc64 uses this */
if ((t->t_flags & PCKBC_CANT_TRANSLATE) != 0) {
/* Hardware lacks translation capability. Nothing to do! */
if (t->t_flags & PCKBC_FIXED_SET2)
*table = 2;
else /* PCKBC_FIXED_SET3 */
*table = 3;
return (-1);
}
#endif
if (t->t_cmdbyte & KC8_TRANS)
return (0);

15
sys/dev/ic/pckbcvar.h
View file

@ -1,4 +1,4 @@
/* $OpenBSD: pckbcvar.h,v 1.16 2017/03/11 11:55:03 mpi Exp $ */
/* $OpenBSD: pckbcvar.h,v 1.17 2023/07/25 10:00:44 miod Exp $ */
/* $NetBSD: pckbcvar.h,v 1.4 2000/06/09 04:58:35 soda Exp $ */
/*
@ -52,9 +52,14 @@ struct pckbc_internal {
u_char t_cmdbyte; /* shadow */
int t_flags;
#define PCKBC_CANT_TRANSLATE 0x0001 /* can't translate to XT scancodes */
#define PCKBC_NEED_AUXWRITE 0x0002 /* need auxwrite command to find aux */
int t_haveaux; /* controller has an aux port */
/* need auxwrite command to find aux */
#define PCKBC_NEED_AUXWRITE 0x0001
/* can't translate to XT scancodes, stuck to set #2 */
#define PCKBC_FIXED_SET2 0x0002
/* can't translate to XT scancodes, stuck to set #3 */
#define PCKBC_FIXED_SET3 0x0004
#define PCKBC_CANT_TRANSLATE (PCKBC_FIXED_SET2 | PCKBC_FIXED_SET3)
int t_haveaux; /* controller has an aux port */
struct pckbc_slotdata *t_slotdata[PCKBC_NSLOTS];
@ -100,7 +105,7 @@ int pckbc_poll_data(pckbc_tag_t, pckbc_slot_t);
int pckbc_poll_data1(bus_space_tag_t, bus_space_handle_t,
bus_space_handle_t, pckbc_slot_t, int);
void pckbc_set_poll(pckbc_tag_t, pckbc_slot_t, int);
int pckbc_xt_translation(pckbc_tag_t);
int pckbc_xt_translation(pckbc_tag_t, int *);
void pckbc_slot_enable(pckbc_tag_t, pckbc_slot_t, int);
void pckbc_attach(struct pckbc_softc *, int);

3
sys/dev/pci/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
View file

@ -2737,6 +2737,9 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence **ef)
if (!attachment->is_mapped)
continue;
if (attachment->bo_va->base.bo->tbo.pin_count)
continue;
kfd_mem_dmaunmap_attachment(mem, attachment);
ret = update_gpuvm_pte(mem, attachment, &sync_obj);
if (ret) {

12
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
View file

@ -1730,18 +1730,30 @@ int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
/* Insert partial mapping before the range */
if (!list_empty(&before->list)) {
struct amdgpu_bo *bo = before->bo_va->base.bo;
amdgpu_vm_it_insert(before, &vm->va);
if (before->flags & AMDGPU_PTE_PRT)
amdgpu_vm_prt_get(adev);
if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv &&
!before->bo_va->base.moved)
amdgpu_vm_bo_moved(&before->bo_va->base);
} else {
kfree(before);
}
/* Insert partial mapping after the range */
if (!list_empty(&after->list)) {
struct amdgpu_bo *bo = after->bo_va->base.bo;
amdgpu_vm_it_insert(after, &vm->va);
if (after->flags & AMDGPU_PTE_PRT)
amdgpu_vm_prt_get(adev);
if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv &&
!after->bo_va->base.moved)
amdgpu_vm_bo_moved(&after->bo_va->base);
} else {
kfree(after);
}

11
sys/dev/pci/drm/amd/amdgpu/nbio_v2_3.c
View file

@ -346,7 +346,7 @@ static void nbio_v2_3_init_registers(struct amdgpu_device *adev)
#define NAVI10_PCIE__LC_L0S_INACTIVITY_DEFAULT 0x00000000 // off by default, no gains over L1
#define NAVI10_PCIE__LC_L1_INACTIVITY_DEFAULT 0x00000009 // 1=1us, 9=1ms
#define NAVI10_PCIE__LC_L1_INACTIVITY_TBT_DEFAULT 0x0000000E // 4ms
#define NAVI10_PCIE__LC_L1_INACTIVITY_TBT_DEFAULT 0x0000000E // 400ms
static void nbio_v2_3_enable_aspm(struct amdgpu_device *adev,
bool enable)
@ -479,9 +479,12 @@ static void nbio_v2_3_program_aspm(struct amdgpu_device *adev)
WREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP5, data);
def = data = RREG32_PCIE(smnPCIE_LC_CNTL);
data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;
data |= 0x9 << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT;
data |= 0x1 << PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT;
data |= NAVI10_PCIE__LC_L0S_INACTIVITY_DEFAULT << PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT;
if (pci_is_thunderbolt_attached(adev->pdev))
data |= NAVI10_PCIE__LC_L1_INACTIVITY_TBT_DEFAULT << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT;
else
data |= NAVI10_PCIE__LC_L1_INACTIVITY_DEFAULT << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT;
data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
if (def != data)
WREG32_PCIE(smnPCIE_LC_CNTL, data);

4
sys/dev/pci/drm/amd/amdgpu/sdma_v4_0.c
View file

@ -2330,7 +2330,7 @@ const struct amd_ip_funcs sdma_v4_0_ip_funcs = {
static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = {
.type = AMDGPU_RING_TYPE_SDMA,
.align_mask = 0xf,
.align_mask = 0xff,
.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
.support_64bit_ptrs = true,
.secure_submission_supported = true,
@ -2400,7 +2400,7 @@ static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs_2nd_mmhub = {
static const struct amdgpu_ring_funcs sdma_v4_0_page_ring_funcs = {
.type = AMDGPU_RING_TYPE_SDMA,
.align_mask = 0xf,
.align_mask = 0xff,
.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
.support_64bit_ptrs = true,
.secure_submission_supported = true,

8
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
View file

@ -6974,7 +6974,13 @@ static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
drm_add_modes_noedid(connector, 640, 480);
} else {
amdgpu_dm_connector_ddc_get_modes(connector, edid);
amdgpu_dm_connector_add_common_modes(encoder, connector);
/* most eDP supports only timings from its edid,
* usually only detailed timings are available
* from eDP edid. timings which are not from edid
* may damage eDP
*/
if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
amdgpu_dm_connector_add_common_modes(encoder, connector);
amdgpu_dm_connector_add_freesync_modes(connector, edid);
}
amdgpu_dm_fbc_init(connector);

26
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
View file

@ -42,6 +42,30 @@
#include "dm_helpers.h"
#include "ddc_service_types.h"
static u32 edid_extract_panel_id(struct edid *edid)
{
return (u32)edid->mfg_id[0] << 24 |
(u32)edid->mfg_id[1] << 16 |
(u32)EDID_PRODUCT_ID(edid);
}
static void apply_edid_quirks(struct edid *edid, struct dc_edid_caps *edid_caps)
{
uint32_t panel_id = edid_extract_panel_id(edid);
switch (panel_id) {
/* Workaround for some monitors which does not work well with FAMS */
case drm_edid_encode_panel_id('S', 'A', 'M', 0x0E5E):
case drm_edid_encode_panel_id('S', 'A', 'M', 0x7053):
case drm_edid_encode_panel_id('S', 'A', 'M', 0x71AC):
DRM_DEBUG_DRIVER("Disabling FAMS on monitor with panel id %X\n", panel_id);
edid_caps->panel_patch.disable_fams = true;
break;
default:
return;
}
}
/* dm_helpers_parse_edid_caps
*
* Parse edid caps
@ -113,6 +137,8 @@ enum dc_edid_status dm_helpers_parse_edid_caps(
else
edid_caps->speaker_flags = DEFAULT_SPEAKER_LOCATION;
apply_edid_quirks(edid_buf, edid_caps);
kfree(sads);
kfree(sadb);

3
sys/dev/pci/drm/amd/display/dc/core/amdgpu_dc.c
View file

@ -1539,6 +1539,9 @@ bool dc_validate_boot_timing(const struct dc *dc,
return false;
}
if (dc->debug.force_odm_combine)
return false;
/* Check for enabled DIG to identify enabled display */
if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
return false;

10
sys/dev/pci/drm/amd/display/dc/dce112/dce112_resource.c
View file

@ -970,10 +970,12 @@ enum dc_status resource_map_phy_clock_resources(
|| dc_is_virtual_signal(pipe_ctx->stream->signal))
pipe_ctx->clock_source =
dc->res_pool->dp_clock_source;
else
pipe_ctx->clock_source = find_matching_pll(
&context->res_ctx, dc->res_pool,
stream);
else {
if (stream && stream->link && stream->link->link_enc)
pipe_ctx->clock_source = find_matching_pll(
&context->res_ctx, dc->res_pool,
stream);
}
if (pipe_ctx->clock_source == NULL)
return DC_NO_CLOCK_SOURCE_RESOURCE;

11
sys/dev/pci/drm/amd/display/dc/dcn20/dcn20_hwseq.c
View file

@ -1678,6 +1678,17 @@ static void dcn20_program_pipe(
if (hws->funcs.setup_vupdate_interrupt)
hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
if (hws->funcs.calculate_dccg_k1_k2_values && dc->res_pool->dccg->funcs->set_pixel_rate_div) {
unsigned int k1_div, k2_div;
hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div);
dc->res_pool->dccg->funcs->set_pixel_rate_div(
dc->res_pool->dccg,
pipe_ctx->stream_res.tg->inst,
k1_div, k2_div);
}
}
if (pipe_ctx->update_flags.bits.odm)

4
sys/dev/pci/drm/amd/display/dc/dcn32/dcn32_hwseq.c
View file

@ -1165,10 +1165,6 @@ unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsign
unsigned int odm_combine_factor = 0;
bool two_pix_per_container = false;
// For phantom pipes, use the same programming as the main pipes
if (pipe_ctx->stream->mall_stream_config.type == SUBVP_PHANTOM) {
stream = pipe_ctx->stream->mall_stream_config.paired_stream;
}
two_pix_per_container = optc2_is_two_pixels_per_containter(&stream->timing);
odm_combine_factor = get_odm_config(pipe_ctx, NULL);

2
sys/dev/pci/drm/amd/display/dc/dcn32/dcn32_optc.c
View file

@ -98,7 +98,7 @@ static void optc32_set_odm_combine(struct timing_generator *optc, int *opp_id, i
optc1->opp_count = opp_cnt;
}
static void optc32_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode)
void optc32_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode)
{
struct optc *optc1 = DCN10TG_FROM_TG(optc);

1
sys/dev/pci/drm/amd/display/dc/dcn32/dcn32_optc.h
View file

@ -250,5 +250,6 @@
SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh)
void dcn32_timing_generator_init(struct optc *optc1);
void optc32_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode);
#endif /* __DC_OPTC_DCN32_H__ */

2
sys/dev/pci/drm/amd/display/dmub/dmub_srv.h
View file

@ -471,7 +471,7 @@ struct dmub_notification {
* of a firmware to know if feature or functionality is supported or present.
*/
#define DMUB_FW_VERSION(major, minor, revision) \
((((major) & 0xFF) << 24) | (((minor) & 0xFF) << 16) | ((revision) & 0xFFFF))
((((major) & 0xFF) << 24) | (((minor) & 0xFF) << 16) | (((revision) & 0xFF) << 8))
/**
* dmub_srv_create() - creates the DMUB service.

1
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
View file

@ -168,6 +168,7 @@ struct smu_temperature_range {
int mem_crit_max;
int mem_emergency_max;
int software_shutdown_temp;
int software_shutdown_temp_offset;
};
struct smu_state_validation_block {

4
sys/dev/pci/drm/amd/pm/swsmu/inc/smu_v13_0.h
View file

@ -297,5 +297,9 @@ int smu_v13_0_get_pptable_from_firmware(struct smu_context *smu,
uint32_t *size,
uint32_t pptable_id);
int smu_v13_0_update_pcie_parameters(struct smu_context *smu,
uint32_t pcie_gen_cap,
uint32_t pcie_width_cap);
#endif
#endif

102
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0.c
View file

@ -1381,6 +1381,7 @@ static int smu_v13_0_irq_process(struct amdgpu_device *adev,
*/
uint32_t ctxid = entry->src_data[0];
uint32_t data;
uint32_t high;
if (client_id == SOC15_IH_CLIENTID_THM) {
switch (src_id) {
@ -1437,6 +1438,36 @@ static int smu_v13_0_irq_process(struct amdgpu_device *adev,
schedule_work(&smu->throttling_logging_work);
break;
case 0x8:
high = smu->thermal_range.software_shutdown_temp +
smu->thermal_range.software_shutdown_temp_offset;
high = min_t(typeof(high),
SMU_THERMAL_MAXIMUM_ALERT_TEMP,
high);
dev_emerg(adev->dev, "Reduce soft CTF limit to %d (by an offset %d)\n",
high,
smu->thermal_range.software_shutdown_temp_offset);
data = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
data = REG_SET_FIELD(data, THM_THERMAL_INT_CTRL,
DIG_THERM_INTH,
(high & 0xff));
data = data & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, data);
break;
case 0x9:
high = min_t(typeof(high),
SMU_THERMAL_MAXIMUM_ALERT_TEMP,
smu->thermal_range.software_shutdown_temp);
dev_emerg(adev->dev, "Recover soft CTF limit to %d\n", high);
data = RREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL);
data = REG_SET_FIELD(data, THM_THERMAL_INT_CTRL,
DIG_THERM_INTH,
(high & 0xff));
data = data & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, data);
break;
}
}
}
@ -2458,3 +2489,74 @@ int smu_v13_0_mode1_reset(struct smu_context *smu)
return ret;
}
/*
* Intel hosts such as Raptor Lake and Sapphire Rapids don't support dynamic
* speed switching. Until we have confirmation from Intel that a specific host
* supports it, it's safer that we keep it disabled for all.
*
* https://edc.intel.com/content/www/us/en/design/products/platforms/details/raptor-lake-s/13th-generation-core-processors-datasheet-volume-1-of-2/005/pci-express-support/
* https://gitlab.freedesktop.org/drm/amd/-/issues/2663
*/
static bool smu_v13_0_is_pcie_dynamic_switching_supported(void)
{
#if IS_ENABLED(CONFIG_X86)
#ifdef __linux__
struct cpuinfo_x86 *c = &cpu_data(0);
if (c->x86_vendor == X86_VENDOR_INTEL)
#else
if (strcmp(cpu_vendor, "GenuineIntel") == 0)
#endif
return false;
#endif
return true;
}
int smu_v13_0_update_pcie_parameters(struct smu_context *smu,
uint32_t pcie_gen_cap,
uint32_t pcie_width_cap)
{
struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
struct smu_13_0_pcie_table *pcie_table =
&dpm_context->dpm_tables.pcie_table;
int num_of_levels = pcie_table->num_of_link_levels;
uint32_t smu_pcie_arg;
int ret, i;
if (!smu_v13_0_is_pcie_dynamic_switching_supported()) {
if (pcie_table->pcie_gen[num_of_levels - 1] < pcie_gen_cap)
pcie_gen_cap = pcie_table->pcie_gen[num_of_levels - 1];
if (pcie_table->pcie_lane[num_of_levels - 1] < pcie_width_cap)
pcie_width_cap = pcie_table->pcie_lane[num_of_levels - 1];
/* Force all levels to use the same settings */
for (i = 0; i < num_of_levels; i++) {
pcie_table->pcie_gen[i] = pcie_gen_cap;
pcie_table->pcie_lane[i] = pcie_width_cap;
}
} else {
for (i = 0; i < num_of_levels; i++) {
if (pcie_table->pcie_gen[i] > pcie_gen_cap)
pcie_table->pcie_gen[i] = pcie_gen_cap;
if (pcie_table->pcie_lane[i] > pcie_width_cap)
pcie_table->pcie_lane[i] = pcie_width_cap;
}
}
for (i = 0; i < num_of_levels; i++) {
smu_pcie_arg = i << 16;
smu_pcie_arg |= pcie_table->pcie_gen[i] << 8;
smu_pcie_arg |= pcie_table->pcie_lane[i];
ret = smu_cmn_send_smc_msg_with_param(smu,
SMU_MSG_OverridePcieParameters,
smu_pcie_arg,
NULL);
if (ret)
return ret;
}
return 0;
}

34
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
View file

@ -1216,37 +1216,6 @@ static int smu_v13_0_0_force_clk_levels(struct smu_context *smu,
return ret;
}
static int smu_v13_0_0_update_pcie_parameters(struct smu_context *smu,
uint32_t pcie_gen_cap,
uint32_t pcie_width_cap)
{
struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
struct smu_13_0_pcie_table *pcie_table =
&dpm_context->dpm_tables.pcie_table;
uint32_t smu_pcie_arg;
int ret, i;
for (i = 0; i < pcie_table->num_of_link_levels; i++) {
if (pcie_table->pcie_gen[i] > pcie_gen_cap)
pcie_table->pcie_gen[i] = pcie_gen_cap;
if (pcie_table->pcie_lane[i] > pcie_width_cap)
pcie_table->pcie_lane[i] = pcie_width_cap;
smu_pcie_arg = i << 16;
smu_pcie_arg |= pcie_table->pcie_gen[i] << 8;
smu_pcie_arg |= pcie_table->pcie_lane[i];
ret = smu_cmn_send_smc_msg_with_param(smu,
SMU_MSG_OverridePcieParameters,
smu_pcie_arg,
NULL);
if (ret)
return ret;
}
return 0;
}
static const struct smu_temperature_range smu13_thermal_policy[] = {
{-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
{ 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
@ -1281,6 +1250,7 @@ static int smu_v13_0_0_get_thermal_temperature_range(struct smu_context *smu,
range->mem_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)*
SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
range->software_shutdown_temp_offset = pptable->SkuTable.FanAbnormalTempLimitOffset;
return 0;
}
@ -2036,7 +2006,7 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs = {
.feature_is_enabled = smu_cmn_feature_is_enabled,
.print_clk_levels = smu_v13_0_0_print_clk_levels,
.force_clk_levels = smu_v13_0_0_force_clk_levels,
.update_pcie_parameters = smu_v13_0_0_update_pcie_parameters,
.update_pcie_parameters = smu_v13_0_update_pcie_parameters,
.get_thermal_temperature_range = smu_v13_0_0_get_thermal_temperature_range,
.register_irq_handler = smu_v13_0_register_irq_handler,
.enable_thermal_alert = smu_v13_0_enable_thermal_alert,

34
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
View file

@ -1225,37 +1225,6 @@ static int smu_v13_0_7_force_clk_levels(struct smu_context *smu,
return ret;
}
static int smu_v13_0_7_update_pcie_parameters(struct smu_context *smu,
uint32_t pcie_gen_cap,
uint32_t pcie_width_cap)
{
struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
struct smu_13_0_pcie_table *pcie_table =
&dpm_context->dpm_tables.pcie_table;
uint32_t smu_pcie_arg;
int ret, i;
for (i = 0; i < pcie_table->num_of_link_levels; i++) {
if (pcie_table->pcie_gen[i] > pcie_gen_cap)
pcie_table->pcie_gen[i] = pcie_gen_cap;
if (pcie_table->pcie_lane[i] > pcie_width_cap)
pcie_table->pcie_lane[i] = pcie_width_cap;
smu_pcie_arg = i << 16;
smu_pcie_arg |= pcie_table->pcie_gen[i] << 8;
smu_pcie_arg |= pcie_table->pcie_lane[i];
ret = smu_cmn_send_smc_msg_with_param(smu,
SMU_MSG_OverridePcieParameters,
smu_pcie_arg,
NULL);
if (ret)
return ret;
}
return 0;
}
static const struct smu_temperature_range smu13_thermal_policy[] =
{
{-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
@ -1288,6 +1257,7 @@ static int smu_v13_0_7_get_thermal_temperature_range(struct smu_context *smu,
range->mem_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)*
SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
range->software_shutdown_temp_offset = pptable->SkuTable.FanAbnormalTempLimitOffset;
return 0;
}
@ -1751,7 +1721,7 @@ static const struct pptable_funcs smu_v13_0_7_ppt_funcs = {
.feature_is_enabled = smu_cmn_feature_is_enabled,
.print_clk_levels = smu_v13_0_7_print_clk_levels,
.force_clk_levels = smu_v13_0_7_force_clk_levels,
.update_pcie_parameters = smu_v13_0_7_update_pcie_parameters,
.update_pcie_parameters = smu_v13_0_update_pcie_parameters,
.get_thermal_temperature_range = smu_v13_0_7_get_thermal_temperature_range,
.register_irq_handler = smu_v13_0_register_irq_handler,
.enable_thermal_alert = smu_v13_0_enable_thermal_alert,

11
sys/dev/pci/drm/drm_atomic.c
View file

@ -140,6 +140,12 @@ drm_atomic_state_init(struct drm_device *dev, struct drm_atomic_state *state)
if (!state->planes)
goto fail;
/*
* Because drm_atomic_state can be committed asynchronously we need our
* own reference and cannot rely on the on implied by drm_file in the
* ioctl call.
*/
drm_dev_get(dev);
state->dev = dev;
drm_dbg_atomic(dev, "Allocated atomic state %p\n", state);
@ -299,7 +305,8 @@ EXPORT_SYMBOL(drm_atomic_state_clear);
void __drm_atomic_state_free(struct kref *ref)
{
struct drm_atomic_state *state = container_of(ref, typeof(*state), ref);
struct drm_mode_config *config = &state->dev->mode_config;
struct drm_device *dev = state->dev;
struct drm_mode_config *config = &dev->mode_config;
drm_atomic_state_clear(state);
@ -311,6 +318,8 @@ void __drm_atomic_state_free(struct kref *ref)
drm_atomic_state_default_release(state);
kfree(state);
}
drm_dev_put(dev);
}
EXPORT_SYMBOL(__drm_atomic_state_free);

11
sys/dev/pci/drm/drm_atomic_helper.c
View file

@ -1231,7 +1231,16 @@ disable_outputs(struct drm_device *dev, struct drm_atomic_state *old_state)
continue;
ret = drm_crtc_vblank_get(crtc);
WARN_ONCE(ret != -EINVAL, "driver forgot to call drm_crtc_vblank_off()\n");
/*
* Self-refresh is not a true "disable"; ensure vblank remains
* enabled.
*/
if (new_crtc_state->self_refresh_active)
WARN_ONCE(ret != 0,
"driver disabled vblank in self-refresh\n");
else
WARN_ONCE(ret != -EINVAL,
"driver forgot to call drm_crtc_vblank_off()\n");
if (ret == 0)
drm_crtc_vblank_put(crtc);
}

21
sys/dev/pci/drm/drm_client.c
View file

@ -122,13 +122,34 @@ EXPORT_SYMBOL(drm_client_init);
* drm_client_register() it is no longer permissible to call drm_client_release()
* directly (outside the unregister callback), instead cleanup will happen
* automatically on driver unload.
*
* Registering a client generates a hotplug event that allows the client
* to set up its display from pre-existing outputs. The client must have
* initialized its state to able to handle the hotplug event successfully.
*/
void drm_client_register(struct drm_client_dev *client)
{
struct drm_device *dev = client->dev;
int ret;
mutex_lock(&dev->clientlist_mutex);
list_add(&client->list, &dev->clientlist);
if (client->funcs && client->funcs->hotplug) {
/*
* Perform an initial hotplug event to pick up the
* display configuration for the client. This step
* has to be performed *after* registering the client
* in the list of clients, or a concurrent hotplug
* event might be lost; leaving the display off.
*
* Hold the clientlist_mutex as for a regular hotplug
* event.
*/
ret = client->funcs->hotplug(client);
if (ret)
drm_dbg_kms(dev, "client hotplug ret=%d\n", ret);
}
mutex_unlock(&dev->clientlist_mutex);
}
EXPORT_SYMBOL(drm_client_register);

1
sys/dev/pci/drm/drm_drv.c
View file

@ -1309,6 +1309,7 @@ drm_attach(struct device *parent, struct device *self, void *aux)
sc->sc_drm = dev;
kref_init(&dev->ref);
dev->dev = self;
dev->dev_private = parent;
dev->driver = da->driver;

4
sys/dev/pci/drm/drm_fb_helper.c
View file

@ -2717,10 +2717,6 @@ void drm_fbdev_generic_setup(struct drm_device *dev,
preferred_bpp = 32;
fb_helper->preferred_bpp = preferred_bpp;
ret = drm_fbdev_client_hotplug(&fb_helper->client);
if (ret)
drm_dbg_kms(dev, "client hotplug ret=%d\n", ret);
drm_client_register(&fb_helper->client);
}
EXPORT_SYMBOL(drm_fbdev_generic_setup);

1
sys/dev/pci/drm/i915/display/intel_display.c
View file

@ -5133,7 +5133,6 @@ copy_bigjoiner_crtc_state_modeset(struct intel_atomic_state *state,
saved_state->uapi = slave_crtc_state->uapi;
saved_state->scaler_state = slave_crtc_state->scaler_state;
saved_state->shared_dpll = slave_crtc_state->shared_dpll;
saved_state->dpll_hw_state = slave_crtc_state->dpll_hw_state;
saved_state->crc_enabled = slave_crtc_state->crc_enabled;
intel_crtc_free_hw_state(slave_crtc_state);

2
sys/dev/pci/drm/i915/gt/intel_gtt.c
View file

@ -611,7 +611,7 @@ __vm_create_scratch_for_read(struct i915_address_space *vm, unsigned long size)
if (IS_ERR(obj))
return ERR_CAST(obj);
i915_gem_object_set_cache_coherency(obj, I915_CACHING_CACHED);
i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC);
vma = i915_vma_instance(obj, vm, NULL);
if (IS_ERR(vma)) {

1
sys/dev/pci/drm/ttm/ttm_bo.c
View file

@ -1191,6 +1191,7 @@ int ttm_bo_swapout(struct ttm_buffer_object *bo, struct ttm_operation_ctx *ctx,
ret = ttm_bo_handle_move_mem(bo, evict_mem, true, &ctx, &hop);
if (unlikely(ret != 0)) {
WARN(ret == -EMULTIHOP, "Unexpected multihop in swaput - likely driver bug.\n");
ttm_resource_free(bo, &evict_mem);
goto out;
}
}

449
sys/dev/pckbc/pckbd.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: pckbd.c,v 1.48 2023/03/08 04:43:08 guenther Exp $ */
/* $OpenBSD: pckbd.c,v 1.50 2023/07/25 10:00:44 miod Exp $ */
/* $NetBSD: pckbd.c,v 1.24 2000/06/05 22:20:57 sommerfeld Exp $ */
/*-
@ -81,6 +81,7 @@
#include <dev/pckbc/pmsreg.h>
#include <dev/wscons/wsconsio.h>
#include <dev/wscons/wskbdraw.h>
#include <dev/wscons/wskbdvar.h>
#include <dev/wscons/wsksymdef.h>
#include <dev/wscons/wsksymvar.h>
@ -92,8 +93,8 @@ struct pckbd_internal {
pckbc_tag_t t_kbctag;
pckbc_slot_t t_kbcslot;
int t_translating;
int t_table;
int t_translating; /* nonzero if hardware performs translation */
int t_table; /* scan code set in use */
int t_lastchar;
int t_extended;
@ -214,11 +215,22 @@ int
pckbd_set_xtscancode(pckbc_tag_t kbctag, pckbc_slot_t kbcslot,
struct pckbd_internal *id)
{
int table = 3;
int table = 0;
if (pckbc_xt_translation(kbctag)) {
if (pckbc_xt_translation(kbctag, &table)) {
#ifdef DEBUG
printf("pckbd: enabling of translation failed\n");
#endif
#ifdef __sparc64__ /* only pckbc@ebus on sparc64 uses this */
/*
* If hardware lacks translation capability, stick to the
* table it is using.
*/
if (table != 0) {
id->t_translating = 0;
id->t_table = table;
return 0;
}
#endif
/*
* Since the keyboard controller can not translate scan
@ -233,6 +245,7 @@ pckbd_set_xtscancode(pckbc_tag_t kbctag, pckbc_slot_t kbcslot,
if (id != NULL)
id->t_translating = 0;
} else {
table = 3;
if (id != NULL) {
id->t_translating = 1;
if (id->t_table == 0) {
@ -493,107 +506,111 @@ pckbd_enable(void *v, int on)
return (0);
}
const u_int8_t pckbd_xtbl[] = {
/*
* Scan code set #2 translation tables
*/
const u_int8_t pckbd_xtbl2[] = {
/* 0x00 */
0,
0x43, /* F9 */
RAWKEY_f9,
0,
0x3f, /* F5 */
0x3d, /* F3 */
0x3b, /* F1 */
0x3c, /* F2 */
0x58, /* F12 */
0x40, /* F6 according to documentation */
0x44, /* F10 */
0x42, /* F8 */
0x40, /* F6 according to experimentation */
0x3e, /* F4 */
0x0f, /* Tab */
0x29, /* ` ~ */
RAWKEY_f5,
RAWKEY_f3,
RAWKEY_f1,
RAWKEY_f2,
RAWKEY_f12,
RAWKEY_f6, /* F6 according to documentation */
RAWKEY_f10,
RAWKEY_f8,
RAWKEY_f6, /* F6 according to experimentation */
RAWKEY_f4,
RAWKEY_Tab,
RAWKEY_grave,
0,
/* 0x10 */
0,
0x38, /* Left Alt */
0x2a, /* Left Shift */
RAWKEY_Alt_L,
RAWKEY_Shift_L,
0,
0x1d, /* Left Ctrl */
0x10, /* q */
0x02, /* 1 ! */
RAWKEY_Control_L,
RAWKEY_q,
RAWKEY_1,
0,
0,
0,
0x2c, /* z */
0x1f, /* s */
0x1e, /* a */
0x11, /* w */
0x03, /* 2 @ */
0,
RAWKEY_z,
RAWKEY_s,
RAWKEY_a,
RAWKEY_w,
RAWKEY_2,
RAWKEY_Meta_L,
/* 0x20 */
0,
0x2e, /* c */
0x2d, /* x */
0x20, /* d */
0x12, /* e */
0x05, /* 4 $ */
0x04, /* 3 # */
RAWKEY_c,
RAWKEY_x,
RAWKEY_d,
RAWKEY_e,
RAWKEY_4,
RAWKEY_3,
0,
0,
0x39, /* Space */
0x2f, /* v */
0x21, /* f */
0x14, /* t */
0x13, /* r */
0x06, /* 5 % */
RAWKEY_Meta_R,
RAWKEY_space,
RAWKEY_v,
RAWKEY_f,
RAWKEY_t,
RAWKEY_r,
RAWKEY_5,
0,
/* 0x30 */
0,
0x31, /* n */
0x30, /* b */
0x23, /* h */
0x22, /* g */
0x15, /* y */
0x07, /* 6 ^ */
RAWKEY_n,
RAWKEY_b,
RAWKEY_h,
RAWKEY_g,
RAWKEY_y,
RAWKEY_6,
0,
0,
0,
0x32, /* m */
0x24, /* j */
0x16, /* u */
0x08, /* 7 & */
0x09, /* 8 * */
RAWKEY_m,
RAWKEY_j,
RAWKEY_u,
RAWKEY_7,
RAWKEY_8,
0,
/* 0x40 */
0,
0x33, /* , < */
0x25, /* k */
0x17, /* i */
0x18, /* o */
0x0b, /* 0 ) */
0x0a, /* 9 ( */
RAWKEY_comma,
RAWKEY_k,
RAWKEY_i,
RAWKEY_o,
RAWKEY_0,
RAWKEY_9,
0,
0,
0x34, /* . > */
0x35, /* / ? */
0x26, /* l */
0x27, /* ; : */
0x19, /* p */
0x0c, /* - _ */
RAWKEY_period,
RAWKEY_slash,
RAWKEY_l,
RAWKEY_semicolon,
RAWKEY_p,
RAWKEY_minus,
0,
/* 0x50 */
0,
0,
0x28, /* ' " */
RAWKEY_apostrophe,
0,
0x1a, /* [ { */
0x0d, /* = + */
RAWKEY_bracketleft,
RAWKEY_equal,
0,
0,
0x3a, /* Caps Lock */
0x36, /* Right Shift */
0x1c, /* Return */
0x1b, /* ] } */
RAWKEY_Caps_Lock,
RAWKEY_Shift_R,
RAWKEY_Return,
RAWKEY_bracketright,
0,
0x2b, /* \ | */
RAWKEY_backslash,
0,
0,
/* 0x60 */
@ -603,42 +620,42 @@ const u_int8_t pckbd_xtbl[] = {
0,
0,
0,
0x0e, /* Back Space */
RAWKEY_BackSpace,
0,
0,
0x4f, /* KP 1 */
RAWKEY_KP_End,
0,
0x4b, /* KP 4 */
0x47, /* KP 7 */
RAWKEY_KP_Left,
RAWKEY_KP_Home,
0,
0,
0,
/* 0x70 */
0x52, /* KP 0 */
0x53, /* KP . */
0x50, /* KP 2 */
0x4c, /* KP 5 */
0x4d, /* KP 6 */
0x48, /* KP 8 */
0x01, /* Escape */
0x45, /* Num Lock */
0x57, /* F11 */
0x4e, /* KP + */
0x51, /* KP 3 */
0x4a, /* KP - */
0x37, /* KP * */
0x49, /* KP 9 */
0x46, /* Scroll Lock */
RAWKEY_KP_Insert,
RAWKEY_KP_Delete,
RAWKEY_KP_Down,
RAWKEY_KP_Begin,
RAWKEY_KP_Right,
RAWKEY_KP_Up,
RAWKEY_Escape,
RAWKEY_Num_Lock,
RAWKEY_f11,
RAWKEY_KP_Add,
RAWKEY_KP_Next,
RAWKEY_KP_Subtract,
RAWKEY_KP_Multiply,
RAWKEY_KP_Prior,
RAWKEY_Hold_Screen,
0,
/* 0x80 */
0,
0,
0,
0x41, /* F7 (produced as an actual 8 bit code) */
RAWKEY_f7,
0 /* Alt-Print Screen */
};
const u_int8_t pckbd_xtbl_ext[] = {
const u_int8_t pckbd_xtbl2_ext[] = {
/* 0x00 */
0,
0,
@ -657,10 +674,10 @@ const u_int8_t pckbd_xtbl_ext[] = {
0,
/* 0x10 */
0,
0x38, /* Right Alt */
RAWKEY_Alt_R,
0, /* E0 12, to be ignored */
0,
0x1d, /* Right Ctrl */
RAWKEY_Control_R,
0,
0,
0,
@ -717,7 +734,7 @@ const u_int8_t pckbd_xtbl_ext[] = {
0,
0,
0,
0x55, /* KP / */
RAWKEY_KP_Divide,
0,
0,
0,
@ -734,7 +751,7 @@ const u_int8_t pckbd_xtbl_ext[] = {
0,
0,
0,
0x1c, /* KP Return */
RAWKEY_KP_Enter,
0,
0,
0,
@ -750,34 +767,195 @@ const u_int8_t pckbd_xtbl_ext[] = {
0,
0,
0,
0x4f, /* End */
RAWKEY_End,
0,
0x4b, /* Left */
0x47, /* Home */
RAWKEY_Left,
RAWKEY_Home,
0,
0,
0,
/* 0x70 */
0x52, /* Insert */
0x53, /* Delete */
0x50, /* Down */
RAWKEY_Insert,
RAWKEY_Delete,
RAWKEY_Down,
0,
0x4d, /* Right */
0x48, /* Up */
RAWKEY_Right,
RAWKEY_Up,
0,
0,
0,
0,
0x51, /* Page Down */
RAWKEY_Next,
0,
0x37, /* Print Screen */
0x49, /* Page Up */
0x46, /* Ctrl-Break */
RAWKEY_Print_Screen,
RAWKEY_Prior,
0xc6, /* Ctrl-Break */
0
};
#ifdef __sparc64__ /* only pckbc@ebus on sparc64 uses this */
/*
* Translate scan codes from set 2 to set 1
* Scan code set #3 translation table
*/
const u_int8_t pckbd_xtbl3[] = {
/* 0x00 */
0,
RAWKEY_L5, /* Front */
RAWKEY_L1, /* Stop */
RAWKEY_L3, /* Props */
0,
RAWKEY_L7, /* Open */
RAWKEY_L9, /* Find */
RAWKEY_f1,
RAWKEY_Escape,
RAWKEY_L10, /* Cut */
0,
0,
0,
RAWKEY_Tab,
RAWKEY_grave,
RAWKEY_f2,
/* 0x10 */
RAWKEY_Help,
RAWKEY_Control_L,
RAWKEY_Shift_L,
0,
RAWKEY_Caps_Lock,
RAWKEY_q,
RAWKEY_1,
RAWKEY_f3,
0,
RAWKEY_Alt_L,
RAWKEY_z,
RAWKEY_s,
RAWKEY_a,
RAWKEY_w,
RAWKEY_2,
RAWKEY_f4,
/* 0x20 */
0,
RAWKEY_c,
RAWKEY_x,
RAWKEY_d,
RAWKEY_e,
RAWKEY_4,
RAWKEY_3,
RAWKEY_f5,
RAWKEY_L4, /* Undo */
RAWKEY_space,
RAWKEY_v,
RAWKEY_f,
RAWKEY_t,
RAWKEY_r,
RAWKEY_5,
RAWKEY_f6,
/* 0x30 */
RAWKEY_L2, /* Again */
RAWKEY_n,
RAWKEY_b,
RAWKEY_h,
RAWKEY_g,
RAWKEY_y,
RAWKEY_6,
RAWKEY_f7,
0,
RAWKEY_Alt_R,
RAWKEY_m,
RAWKEY_j,
RAWKEY_u,
RAWKEY_7,
RAWKEY_8,
RAWKEY_f8,
/* 0x40 */
0,
RAWKEY_comma,
RAWKEY_k,
RAWKEY_i,
RAWKEY_o,
RAWKEY_0,
RAWKEY_9,
RAWKEY_f9,
RAWKEY_L6, /* Copy */
RAWKEY_period,
RAWKEY_slash,
RAWKEY_l,
RAWKEY_semicolon,
RAWKEY_p,
RAWKEY_minus,
RAWKEY_f10,
/* 0x50 */
0,
0,
RAWKEY_apostrophe,
0,
RAWKEY_bracketleft,
RAWKEY_equal,
RAWKEY_f11,
RAWKEY_Print_Screen,
RAWKEY_Control_R,
RAWKEY_Shift_R,
RAWKEY_Return,
RAWKEY_bracketright,
RAWKEY_backslash,
0,
RAWKEY_f12,
RAWKEY_Hold_Screen,
/* 0x60 */
RAWKEY_Down,
RAWKEY_Left,
RAWKEY_Pause,
RAWKEY_Up,
RAWKEY_Delete,
RAWKEY_End,
RAWKEY_BackSpace,
RAWKEY_Insert,
RAWKEY_L8, /* Paste */
RAWKEY_KP_End,
RAWKEY_Right,
RAWKEY_KP_Left,
RAWKEY_KP_Home,
RAWKEY_Next,
RAWKEY_Home,
RAWKEY_Prior,
/* 0x70 */
RAWKEY_KP_Insert,
RAWKEY_KP_Delete,
RAWKEY_KP_Down,
RAWKEY_KP_Begin,
RAWKEY_KP_Right,
RAWKEY_KP_Up,
RAWKEY_Num_Lock,
RAWKEY_KP_Divide,
0,
RAWKEY_KP_Enter,
RAWKEY_KP_Next,
0,
RAWKEY_KP_Add,
RAWKEY_KP_Prior,
RAWKEY_KP_Multiply,
0,
/* 0x80 */
0,
0,
0,
0,
RAWKEY_KP_Subtract,
0,
0,
0,
0,
0,
0,
RAWKEY_Meta_L,
RAWKEY_Meta_R
};
#endif
/*
* Translate scan codes from set 2 or 3 to set 1
*/
int
pckbd_scancode_translate(struct pckbd_internal *id, int datain)
@ -790,24 +968,38 @@ pckbd_scancode_translate(struct pckbd_internal *id, int datain)
return 0; /* consume scancode */
}
/*
* Convert BREAK sequence (14 77 -> 1D 45)
*/
if (id->t_extended1 == 2 && datain == 0x14)
return 0x1d | id->t_releasing;
else if (id->t_extended1 == 1 && datain == 0x77)
return 0x45 | id->t_releasing;
switch (id->t_table) {
case 2:
/*
* Convert BREAK sequence (14 77 -> 1D 45)
*/
if (id->t_extended1 == 2 && datain == 0x14)
return 0x1d | id->t_releasing;
else if (id->t_extended1 == 1 && datain == 0x77)
return 0x45 | id->t_releasing;
if (id->t_extended != 0) {
if (datain >= sizeof pckbd_xtbl_ext)
if (id->t_extended != 0) {
if (datain >= sizeof pckbd_xtbl2_ext)
datain = 0;
else
datain = pckbd_xtbl2_ext[datain];
/* xtbl2_ext already has the upper bit set */
id->t_extended = 0;
} else {
if (datain >= sizeof pckbd_xtbl2)
datain = 0;
else
datain = pckbd_xtbl2[datain] & ~0x80;
}
break;
#ifdef __sparc64__ /* only pckbc@ebus on sparc64 uses this */
case 3:
if (datain >= sizeof pckbd_xtbl3)
datain = 0;
else
datain = pckbd_xtbl_ext[datain];
} else {
if (datain >= sizeof pckbd_xtbl)
datain = 0;
else
datain = pckbd_xtbl[datain];
datain = pckbd_xtbl3[datain] & ~0x80;
break;
#endif
}
if (datain == 0) {
@ -1021,11 +1213,8 @@ pckbd_hookup_bell(void (*fn)(void *, u_int, u_int, u_int, int), void *arg)
int
pckbd_cnattach(pckbc_tag_t kbctag)
{
pckbd_init(&pckbd_consdata, kbctag, PCKBC_KBD_SLOT, 1);
wskbd_cnattach(&pckbd_consops, &pckbd_consdata, &pckbd_keymapdata);
return (0);
}

11
sys/dev/wscons/wsemul_sun.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: wsemul_sun.c,v 1.36 2023/03/06 20:34:35 miod Exp $ */
/* $OpenBSD: wsemul_sun.c,v 1.37 2023/07/24 17:03:32 miod Exp $ */
/* $NetBSD: wsemul_sun.c,v 1.11 2000/01/05 11:19:36 drochner Exp $ */
/*
@ -617,13 +617,14 @@ wsemul_sun_output_control(struct wsemul_sun_emuldata *edp,
break;
case ';': /* argument terminator */
edp->nargs++;
if (edp->nargs < SUN_EMUL_NARGS)
edp->nargs++;
break;
default: /* end of escape sequence */
oargs = edp->nargs++;
if (edp->nargs > SUN_EMUL_NARGS)
edp->nargs = SUN_EMUL_NARGS;
oargs = edp->nargs;
if (edp->nargs < SUN_EMUL_NARGS)
edp->nargs++;
rc = wsemul_sun_control(edp, instate);
if (rc != 0) {
/* undo nargs progress */

27
sys/dev/wscons/wsemul_vt100.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: wsemul_vt100.c,v 1.45 2023/03/06 20:34:35 miod Exp $ */
/* $OpenBSD: wsemul_vt100.c,v 1.46 2023/07/24 17:03:32 miod Exp $ */
/* $NetBSD: wsemul_vt100.c,v 1.13 2000/04/28 21:56:16 mycroft Exp $ */
/*
@ -868,16 +868,12 @@ wsemul_vt100_output_dcs(struct wsemul_vt100_emuldata *edp,
(instate->inchar - '0');
break;
case ';': /* argument terminator */
edp->nargs++;
if (edp->nargs < VT100_EMUL_NARGS)
edp->nargs++;
break;
default:
edp->nargs++;
if (edp->nargs > VT100_EMUL_NARGS) {
#ifdef VT100_DEBUG
printf("vt100: too many arguments\n");
#endif
edp->nargs = VT100_EMUL_NARGS;
}
if (edp->nargs < VT100_EMUL_NARGS)
edp->nargs++;
newstate = VT100_EMUL_STATE_STRING;
switch (instate->inchar) {
case '$':
@ -1069,7 +1065,8 @@ wsemul_vt100_output_csi(struct wsemul_vt100_emuldata *edp,
(instate->inchar - '0');
break;
case ';': /* argument terminator */
edp->nargs++;
if (edp->nargs < VT100_EMUL_NARGS)
edp->nargs++;
break;
case '?': /* DEC specific */
case '>': /* DA query */
@ -1082,13 +1079,9 @@ wsemul_vt100_output_csi(struct wsemul_vt100_emuldata *edp,
edp->modif2 = (char)instate->inchar;
break;
default: /* end of escape sequence */
oargs = edp->nargs++;
if (edp->nargs > VT100_EMUL_NARGS) {
#ifdef VT100_DEBUG
printf("vt100: too many arguments\n");
#endif
edp->nargs = VT100_EMUL_NARGS;
}
oargs = edp->nargs;
if (edp->nargs < VT100_EMUL_NARGS)
edp->nargs++;
rc = wsemul_vt100_handle_csi(edp, instate);
if (rc != 0) {
edp->nargs = oargs;

4
sys/dev/wscons/wskbdraw.h
View file

@ -1,4 +1,4 @@
/* $OpenBSD: wskbdraw.h,v 1.3 2011/01/30 16:21:05 miod Exp $ */
/* $OpenBSD: wskbdraw.h,v 1.4 2023/07/24 19:28:40 miod Exp $ */
/*
* Copyright (c) 2005, Miodrag Vallat
@ -120,7 +120,6 @@
#define RAWKEY_less 0x56 /* < > on European keyboards */
#define RAWKEY_f11 0x57
#define RAWKEY_f12 0x58
#define RAWKEY_Print_Screen 0x67
#define RAWKEY_Pause 0x6a
#define RAWKEY_Meta_L 0x73
#define RAWKEY_Meta_R 0x74
@ -128,6 +127,7 @@
#define RAWKEY_KP_Enter 0x9c
#define RAWKEY_Control_R 0x9d
#define RAWKEY_KP_Divide 0xb5
#define RAWKEY_Print_Screen 0xb7
#define RAWKEY_Alt_R 0xb8
#define RAWKEY_Home 0xc7
#define RAWKEY_Up 0xc8

4
sys/kern/init_sysent.c
View file

@ -1,10 +1,10 @@
/* $OpenBSD: init_sysent.c,v 1.266 2023/05/18 10:24:28 mvs Exp $ */
/* $OpenBSD: init_sysent.c,v 1.267 2023/07/24 19:33:29 miod Exp $ */
/*
* System call switch table.
*
* DO NOT EDIT-- this file is automatically generated.
* created from; OpenBSD: syscalls.master,v 1.248 2023/05/18 10:23:19 mvs Exp
* created from; OpenBSD: syscalls.master,v 1.249 2023/07/24 19:32:23 miod Exp
*/
#include <sys/param.h>

61
sys/kern/kern_clock.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: kern_clock.c,v 1.108 2023/04/25 00:58:47 cheloha Exp $ */
/* $OpenBSD: kern_clock.c,v 1.109 2023/07/25 18:16:19 cheloha Exp $ */
/* $NetBSD: kern_clock.c,v 1.34 1996/06/09 04:51:03 briggs Exp $ */
/*-
@ -49,10 +49,6 @@
#include <sys/sched.h>
#include <sys/timetc.h>
#if defined(GPROF) || defined(DDBPROF)
#include <sys/gmon.h>
#endif
#include "dt.h"
#if NDT > 0
#include <dev/dt/dtvar.h>
@ -87,8 +83,6 @@ int schedhz;
int profhz;
int profprocs;
int ticks = INT_MAX - (15 * 60 * HZ);
static int psdiv, pscnt; /* prof => stat divider */
int psratio; /* ratio: prof / stat */
volatile unsigned long jiffies = ULONG_MAX - (10 * 60 * HZ);
@ -99,16 +93,13 @@ void
initclocks(void)
{
/*
* Set divisors to 1 (normal case) and let the machine-specific
* code do its bit.
* Let the machine-specific code do its bit.
*/
psdiv = pscnt = 1;
cpu_initclocks();
/*
* Compute profhz/stathz.
*/
psratio = profhz / stathz;
KASSERT(profhz >= stathz && profhz <= 1000000000);
KASSERT(profhz % stathz == 0);
profclock_period = 1000000000 / profhz;
inittimecounter();
}
@ -256,7 +247,6 @@ startprofclock(struct process *pr)
atomic_setbits_int(&pr->ps_flags, PS_PROFIL);
if (++profprocs == 1) {
s = splstatclock();
psdiv = pscnt = psratio;
setstatclockrate(profhz);
splx(s);
}
@ -275,7 +265,6 @@ stopprofclock(struct process *pr)
atomic_clearbits_int(&pr->ps_flags, PS_PROFIL);
if (--profprocs == 0) {
s = splstatclock();
psdiv = pscnt = 1;
setstatclockrate(stathz);
splx(s);
}
@ -289,35 +278,13 @@ stopprofclock(struct process *pr)
void
statclock(struct clockframe *frame)
{
#if defined(GPROF) || defined(DDBPROF)
struct gmonparam *g;
u_long i;
#endif
struct cpu_info *ci = curcpu();
struct schedstate_percpu *spc = &ci->ci_schedstate;
struct proc *p = curproc;
struct process *pr;
/*
* Notice changes in divisor frequency, and adjust clock
* frequency accordingly.
*/
if (spc->spc_psdiv != psdiv) {
spc->spc_psdiv = psdiv;
spc->spc_pscnt = psdiv;
if (psdiv == 1) {
setstatclockrate(stathz);
} else {
setstatclockrate(profhz);
}
}
if (CLKF_USERMODE(frame)) {
pr = p->p_p;
if (pr->ps_flags & PS_PROFIL)
addupc_intr(p, CLKF_PC(frame), 1);
if (--spc->spc_pscnt > 0)
return;
/*
* Came from user mode; CPU was in user state.
* If this process is being profiled record the tick.
@ -328,23 +295,6 @@ statclock(struct clockframe *frame)
else
spc->spc_cp_time[CP_USER]++;
} else {
#if defined(GPROF) || defined(DDBPROF)
/*
* Kernel statistics are just like addupc_intr, only easier.
*/
g = ci->ci_gmon;
if (g != NULL && g->state == GMON_PROF_ON) {
i = CLKF_PC(frame) - g->lowpc;
if (i < g->textsize) {
i /= HISTFRACTION * sizeof(*g->kcount);
g->kcount[i]++;
}
}
#endif
if (p != NULL && p->p_p->ps_flags & PS_PROFIL)
addupc_intr(p, PROC_PC(p), 1);
if (--spc->spc_pscnt > 0)
return;
/*
* Came from kernel mode, so we were:
* - spinning on a lock
@ -371,7 +321,6 @@ statclock(struct clockframe *frame)
spc->spc_cp_time[spc->spc_spinning ?
CP_SPIN : CP_IDLE]++;
}
spc->spc_pscnt = psdiv;
if (p != NULL) {
p->p_cpticks++;

126
sys/kern/kern_clockintr.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: kern_clockintr.c,v 1.27 2023/07/02 19:02:27 cheloha Exp $ */
/* $OpenBSD: kern_clockintr.c,v 1.28 2023/07/25 18:16:19 cheloha Exp $ */
/*
* Copyright (c) 2003 Dale Rahn <drahn@openbsd.org>
* Copyright (c) 2020 Mark Kettenis <kettenis@openbsd.org>
@ -32,39 +32,23 @@
/*
* Protection for global variables in this file:
*
* C Global clockintr configuration mutex (clockintr_mtx).
* I Immutable after initialization.
*/
struct mutex clockintr_mtx = MUTEX_INITIALIZER(IPL_CLOCK);
u_int clockintr_flags; /* [I] global state + behavior flags */
uint32_t hardclock_period; /* [I] hardclock period (ns) */
uint32_t schedclock_period; /* [I] schedclock period (ns) */
volatile u_int statclock_gen = 1; /* [C] statclock update generation */
volatile uint32_t statclock_avg; /* [C] average statclock period (ns) */
uint32_t statclock_min; /* [C] minimum statclock period (ns) */
uint32_t statclock_mask; /* [C] set of allowed offsets */
uint32_t stat_avg; /* [I] average stathz period (ns) */
uint32_t stat_min; /* [I] set of allowed offsets */
uint32_t stat_mask; /* [I] max offset from minimum (ns) */
uint32_t prof_avg; /* [I] average profhz period (ns) */
uint32_t prof_min; /* [I] minimum profhz period (ns) */
uint32_t prof_mask; /* [I] set of allowed offsets */
uint32_t statclock_avg; /* [I] average statclock period (ns) */
uint32_t statclock_min; /* [I] minimum statclock period (ns) */
uint32_t statclock_mask; /* [I] set of allowed offsets */
uint64_t clockintr_advance(struct clockintr *, uint64_t);
void clockintr_cancel(struct clockintr *);
void clockintr_cancel_locked(struct clockintr *);
struct clockintr *clockintr_establish(struct clockintr_queue *,
void (*)(struct clockintr *, void *));
uint64_t clockintr_expiration(const struct clockintr *);
void clockintr_hardclock(struct clockintr *, void *);
uint64_t clockintr_nsecuptime(const struct clockintr *);
void clockintr_schedclock(struct clockintr *, void *);
void clockintr_schedule(struct clockintr *, uint64_t);
void clockintr_schedule_locked(struct clockintr *, uint64_t);
void clockintr_stagger(struct clockintr *, uint64_t, u_int, u_int);
void clockintr_statclock(struct clockintr *, void *);
void clockintr_statvar_init(int, uint32_t *, uint32_t *, uint32_t *);
uint64_t clockqueue_next(const struct clockintr_queue *);
void clockqueue_reset_intrclock(struct clockintr_queue *);
uint64_t nsec_advance(uint64_t *, uint64_t, uint64_t);
@ -75,6 +59,8 @@ uint64_t nsec_advance(uint64_t *, uint64_t, uint64_t);
void
clockintr_init(u_int flags)
{
uint32_t half_avg, var;
KASSERT(CPU_IS_PRIMARY(curcpu()));
KASSERT(clockintr_flags == 0);
KASSERT(!ISSET(flags, ~CL_FLAG_MASK));
@ -83,12 +69,22 @@ clockintr_init(u_int flags)
hardclock_period = 1000000000 / hz;
KASSERT(stathz >= 1 && stathz <= 1000000000);
KASSERT(profhz >= stathz && profhz <= 1000000000);
KASSERT(profhz % stathz == 0);
clockintr_statvar_init(stathz, &stat_avg, &stat_min, &stat_mask);
clockintr_statvar_init(profhz, &prof_avg, &prof_min, &prof_mask);
SET(clockintr_flags, CL_STATCLOCK);
clockintr_setstatclockrate(stathz);
/*
* Compute the average statclock() period. Then find var, the
* largest power of two such that var <= statclock_avg / 2.
*/
statclock_avg = 1000000000 / stathz;
half_avg = statclock_avg / 2;
for (var = 1U << 31; var > half_avg; var /= 2)
continue;
/*
* Set a lower bound for the range using statclock_avg and var.
* The mask for that range is just (var - 1).
*/
statclock_min = statclock_avg - (var / 2);
statclock_mask = var - 1;
KASSERT(schedhz >= 0 && schedhz <= 1000000000);
if (schedhz != 0)
@ -479,70 +475,6 @@ clockintr_stagger(struct clockintr *cl, uint64_t period, u_int n, u_int count)
mtx_leave(&cq->cq_mtx);
}
/*
* Compute the period (avg) for the given frequency and a range around
* that period. The range is [min + 1, min + mask]. The range is used
* during dispatch to choose a new pseudorandom deadline for each statclock
* event.
*/
void
clockintr_statvar_init(int freq, uint32_t *avg, uint32_t *min, uint32_t *mask)
{
uint32_t half_avg, var;
KASSERT(!ISSET(clockintr_flags, CL_INIT | CL_STATCLOCK));
KASSERT(freq > 0 && freq <= 1000000000);
/* Compute avg, the average period. */
*avg = 1000000000 / freq;
/* Find var, the largest power of two such that var <= avg / 2. */
half_avg = *avg / 2;
for (var = 1U << 31; var > half_avg; var /= 2)
continue;
/* Using avg and var, set a lower bound for the range. */
*min = *avg - (var / 2);
/* The mask is just (var - 1). */
*mask = var - 1;
}
/*
* Update the statclock_* variables according to the given frequency.
* Must only be called after clockintr_statvar_init() initializes both
* stathz_* and profhz_*.
*/
void
clockintr_setstatclockrate(int freq)
{
u_int ogen;
KASSERT(ISSET(clockintr_flags, CL_STATCLOCK));
mtx_enter(&clockintr_mtx);
ogen = statclock_gen;
statclock_gen = 0;
membar_producer();
if (freq == stathz) {
statclock_avg = stat_avg;
statclock_min = stat_min;
statclock_mask = stat_mask;
} else if (freq == profhz) {
statclock_avg = prof_avg;
statclock_min = prof_min;
statclock_mask = prof_mask;
} else {
panic("%s: frequency is not stathz (%d) or profhz (%d): %d",
__func__, stathz, profhz, freq);
}
membar_producer();
statclock_gen = MAX(1, ogen + 1);
mtx_leave(&clockintr_mtx);
}
uint64_t
clockintr_nsecuptime(const struct clockintr *cl)
{
@ -577,24 +509,16 @@ void
clockintr_statclock(struct clockintr *cl, void *frame)
{
uint64_t count, expiration, i, uptime;
uint32_t mask, min, off;
u_int gen;
uint32_t off;
if (ISSET(clockintr_flags, CL_RNDSTAT)) {
do {
gen = statclock_gen;
membar_consumer();
min = statclock_min;
mask = statclock_mask;
membar_consumer();
} while (gen == 0 || gen != statclock_gen);
count = 0;
expiration = clockintr_expiration(cl);
uptime = clockintr_nsecuptime(cl);
while (expiration <= uptime) {
while ((off = (random() & mask)) == 0)
while ((off = (random() & statclock_mask)) == 0)
continue;
expiration += min + off;
expiration += statclock_min + off;
count++;
}
clockintr_schedule(cl, expiration);

18
sys/kern/kern_sched.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: kern_sched.c,v 1.79 2023/07/14 07:07:08 claudio Exp $ */
/* $OpenBSD: kern_sched.c,v 1.80 2023/07/25 18:16:19 cheloha Exp $ */
/*
* Copyright (c) 2007, 2008 Artur Grabowski <art@openbsd.org>
*
@ -21,6 +21,8 @@
#include <sys/proc.h>
#include <sys/kthread.h>
#include <sys/systm.h>
#include <sys/clockintr.h>
#include <sys/resourcevar.h>
#include <sys/task.h>
#include <sys/smr.h>
#include <sys/tracepoint.h>
@ -85,6 +87,15 @@ sched_init_cpu(struct cpu_info *ci)
spc->spc_idleproc = NULL;
if (spc->spc_profclock == NULL) {
spc->spc_profclock = clockintr_establish(&ci->ci_queue,
profclock);
if (spc->spc_profclock == NULL)
panic("%s: clockintr_establish profclock", __func__);
clockintr_stagger(spc->spc_profclock, profclock_period,
CPU_INFO_UNIT(ci), MAXCPUS);
}
kthread_create_deferred(sched_kthreads_create, ci);
LIST_INIT(&spc->spc_deadproc);
@ -214,6 +225,11 @@ sched_exit(struct proc *p)
timespecsub(&ts, &spc->spc_runtime, &ts);
timespecadd(&p->p_rtime, &ts, &p->p_rtime);
if (ISSET(spc->spc_schedflags, SPCF_PROFCLOCK)) {
atomic_clearbits_int(&spc->spc_schedflags, SPCF_PROFCLOCK);
clockintr_cancel(spc->spc_profclock);
}
LIST_INSERT_HEAD(&spc->spc_deadproc, p, p_hash);
#ifdef MULTIPROCESSOR

17
sys/kern/sched_bsd.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: sched_bsd.c,v 1.77 2023/07/11 07:02:43 claudio Exp $ */
/* $OpenBSD: sched_bsd.c,v 1.78 2023/07/25 18:16:19 cheloha Exp $ */
/* $NetBSD: kern_synch.c,v 1.37 1996/04/22 01:38:37 christos Exp $ */
/*-
@ -39,6 +39,7 @@
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/clockintr.h>
#include <sys/proc.h>
#include <sys/kernel.h>
#include <sys/malloc.h>
@ -349,6 +350,12 @@ mi_switch(void)
/* add the time counts for this thread to the process's total */
tuagg_unlocked(pr, p);
/* Stop the profclock if it's running. */
if (ISSET(spc->spc_schedflags, SPCF_PROFCLOCK)) {
atomic_clearbits_int(&spc->spc_schedflags, SPCF_PROFCLOCK);
clockintr_cancel(spc->spc_profclock);
}
/*
* Process is about to yield the CPU; clear the appropriate
* scheduling flags.
@ -393,6 +400,14 @@ mi_switch(void)
*/
KASSERT(p->p_cpu == curcpu());
/* Start the profclock if profil(2) is enabled. */
if (ISSET(p->p_p->ps_flags, PS_PROFIL)) {
atomic_setbits_int(&p->p_cpu->ci_schedstate.spc_schedflags,
SPCF_PROFCLOCK);
clockintr_advance(p->p_cpu->ci_schedstate.spc_profclock,
profclock_period);
}
nanouptime(&p->p_cpu->ci_schedstate.spc_runtime);
#ifdef MULTIPROCESSOR

70
sys/kern/subr_prof.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: subr_prof.c,v 1.35 2023/06/02 17:44:29 cheloha Exp $ */
/* $OpenBSD: subr_prof.c,v 1.36 2023/07/25 18:16:19 cheloha Exp $ */
/* $NetBSD: subr_prof.c,v 1.12 1996/04/22 01:38:50 christos Exp $ */
/*-
@ -34,13 +34,17 @@
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/atomic.h>
#include <sys/clockintr.h>
#include <sys/pledge.h>
#include <sys/proc.h>
#include <sys/resourcevar.h>
#include <sys/mount.h>
#include <sys/sysctl.h>
#include <sys/syscallargs.h>
#include <sys/user.h>
uint32_t profclock_period;
#if defined(GPROF) || defined(DDBPROF)
#include <sys/malloc.h>
@ -60,6 +64,8 @@ u_int gmon_cpu_count; /* [K] number of CPUs with profiling enabled */
extern char etext[];
void gmonclock(struct clockintr *, void *);
void
prof_init(void)
{
@ -95,6 +101,14 @@ prof_init(void)
/* Allocate and initialize one profiling buffer per CPU. */
CPU_INFO_FOREACH(cii, ci) {
ci->ci_gmonclock = clockintr_establish(&ci->ci_queue,
gmonclock);
if (ci->ci_gmonclock == NULL) {
printf("%s: clockintr_establish gmonclock\n", __func__);
return;
}
clockintr_stagger(ci->ci_gmonclock, profclock_period,
CPU_INFO_UNIT(ci), MAXCPUS);
cp = km_alloc(round_page(size), &kv_any, &kp_zero, &kd_nowait);
if (cp == NULL) {
printf("No memory for profiling.\n");
@ -124,8 +138,9 @@ prof_init(void)
}
int
prof_state_toggle(struct gmonparam *gp, int oldstate)
prof_state_toggle(struct cpu_info *ci, int oldstate)
{
struct gmonparam *gp = ci->ci_gmon;
int error = 0;
KERNEL_ASSERT_LOCKED();
@ -145,6 +160,7 @@ prof_state_toggle(struct gmonparam *gp, int oldstate)
if (error == 0) {
if (++gmon_cpu_count == 1)
startprofclock(&process0);
clockintr_advance(ci->ci_gmonclock, profclock_period);
}
break;
default:
@ -152,6 +168,7 @@ prof_state_toggle(struct gmonparam *gp, int oldstate)
gp->state = GMON_PROF_OFF;
/* FALLTHROUGH */
case GMON_PROF_OFF:
clockintr_cancel(ci->ci_gmonclock);
if (--gmon_cpu_count == 0)
stopprofclock(&process0);
#if !defined(GPROF)
@ -201,7 +218,7 @@ sysctl_doprof(int *name, u_int namelen, void *oldp, size_t *oldlenp, void *newp,
error = sysctl_int(oldp, oldlenp, newp, newlen, &gp->state);
if (error)
return (error);
return (prof_state_toggle(gp, state));
return prof_state_toggle(ci, state);
case GPROF_COUNT:
return (sysctl_struct(oldp, oldlenp, newp, newlen,
gp->kcount, gp->kcountsize));
@ -218,6 +235,31 @@ sysctl_doprof(int *name, u_int namelen, void *oldp, size_t *oldlenp, void *newp,
}
/* NOTREACHED */
}
void
gmonclock(struct clockintr *cl, void *cf)
{
uint64_t count;
struct clockframe *frame = cf;
struct gmonparam *g = curcpu()->ci_gmon;
u_long i;
count = clockintr_advance(cl, profclock_period);
if (count > ULONG_MAX)
count = ULONG_MAX;
/*
* Kernel statistics are just like addupc_intr(), only easier.
*/
if (!CLKF_USERMODE(frame) && g != NULL && g->state == GMON_PROF_ON) {
i = CLKF_PC(frame) - g->lowpc;
if (i < g->textsize) {
i /= HISTFRACTION * sizeof(*g->kcount);
g->kcount[i] += (u_long)count;
}
}
}
#endif /* GPROF || DDBPROF */
/*
@ -247,6 +289,7 @@ sys_profil(struct proc *p, void *v, register_t *retval)
return (EINVAL);
if (SCARG(uap, scale) == 0) {
stopprofclock(pr);
need_resched(curcpu());
return (0);
}
upp = &pr->ps_prof;
@ -259,10 +302,31 @@ sys_profil(struct proc *p, void *v, register_t *retval)
upp->pr_size = SCARG(uap, size);
startprofclock(pr);
splx(s);
need_resched(curcpu());
return (0);
}
void
profclock(struct clockintr *cl, void *cf)
{
uint64_t count;
struct clockframe *frame = cf;
struct proc *p = curproc;
count = clockintr_advance(cl, profclock_period);
if (count > ULONG_MAX)
count = ULONG_MAX;
if (CLKF_USERMODE(frame)) {
if (ISSET(p->p_p->ps_flags, PS_PROFIL))
addupc_intr(p, CLKF_PC(frame), (u_long)count);
} else {
if (p != NULL && ISSET(p->p_p->ps_flags, PS_PROFIL))
addupc_intr(p, PROC_PC(p), (u_long)count);
}
}
/*
* Scale is a fixed-point number with the binary point 16 bits
* into the value, and is <= 1.0. pc is at most 32 bits, so the

4
sys/kern/syscalls.c
View file

@ -1,10 +1,10 @@
/* $OpenBSD: syscalls.c,v 1.264 2023/05/18 10:24:28 mvs Exp $ */
/* $OpenBSD: syscalls.c,v 1.265 2023/07/24 19:33:29 miod Exp $ */
/*
* System call names.
*
* DO NOT EDIT-- this file is automatically generated.
* created from; OpenBSD: syscalls.master,v 1.248 2023/05/18 10:23:19 mvs Exp
* created from; OpenBSD: syscalls.master,v 1.249 2023/07/24 19:32:23 miod Exp
*/
const char *const syscallnames[] = {

4
sys/kern/syscalls.master
View file

@ -1,4 +1,4 @@
; $OpenBSD: syscalls.master,v 1.248 2023/05/18 10:23:19 mvs Exp $
; $OpenBSD: syscalls.master,v 1.249 2023/07/24 19:32:23 miod Exp $
; $NetBSD: syscalls.master,v 1.32 1996/04/23 10:24:21 mycroft Exp $
; @(#)syscalls.master 8.2 (Berkeley) 1/13/94
@ -279,7 +279,7 @@
139 OBSOL 4.2 sigreturn
140 STD NOLOCK { int sys_adjtime(const struct timeval *delta, \
struct timeval *olddelta); }
141 STD { int sys_getlogin_r(char *namebuf, u_int namelen); }
141 STD { int sys_getlogin_r(char *namebuf, size_t namelen); }
142 STD { int sys_getthrname(pid_t tid, char *name, size_t len); }
143 STD { int sys_setthrname(pid_t tid, const char *name); }
144 OBSOL ogetrlimit

5
sys/kern/uipc_socket.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: uipc_socket.c,v 1.305 2023/07/04 22:28:24 mvs Exp $ */
/* $OpenBSD: uipc_socket.c,v 1.306 2023/07/22 14:30:39 mvs Exp $ */
/* $NetBSD: uipc_socket.c,v 1.21 1996/02/04 02:17:52 christos Exp $ */
/*
@ -2366,7 +2366,8 @@ sobuf_print(struct sockbuf *sb,
(*pr)("\tsb_mbtail: %p\n", sb->sb_mbtail);
(*pr)("\tsb_lastrecord: %p\n", sb->sb_lastrecord);
(*pr)("\tsb_sel: ...\n");
(*pr)("\tsb_flags: %i\n", sb->sb_flags);
(*pr)("\tsb_flags: %04x\n", sb->sb_flags);
(*pr)("\tsb_state: %04x\n", sb->sb_state);
(*pr)("\tsb_timeo_nsecs: %llu\n", sb->sb_timeo_nsecs);
}

11
sys/net/if_loop.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: if_loop.c,v 1.96 2023/07/18 16:01:20 bluhm Exp $ */
/* $OpenBSD: if_loop.c,v 1.97 2023/07/21 22:24:41 bluhm Exp $ */
/* $NetBSD: if_loop.c,v 1.15 1996/05/07 02:40:33 thorpej Exp $ */
/*
@ -146,6 +146,7 @@ void lortrequest(struct ifnet *, int, struct rtentry *);
void loinput(struct ifnet *, struct mbuf *);
int looutput(struct ifnet *,
struct mbuf *, struct sockaddr *, struct rtentry *);
int lo_bpf_mtap(caddr_t, const struct mbuf *, u_int);
int loop_clone_create(struct if_clone *, int);
int loop_clone_destroy(struct ifnet *);
@ -177,6 +178,7 @@ loop_clone_create(struct if_clone *ifc, int unit)
IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4 |
IFCAP_CSUM_TCPv6 | IFCAP_CSUM_UDPv6 |
IFCAP_LRO | IFCAP_TSOv4 | IFCAP_TSOv6;
ifp->if_bpf_mtap = lo_bpf_mtap;
ifp->if_rtrequest = lortrequest;
ifp->if_ioctl = loioctl;
ifp->if_input = loinput;
@ -231,6 +233,13 @@ loop_clone_destroy(struct ifnet *ifp)
return (0);
}
int
lo_bpf_mtap(caddr_t if_bpf, const struct mbuf *m, u_int dir)
{
/* loopback dumps on output, disable input bpf */
return (0);
}
void
loinput(struct ifnet *ifp, struct mbuf *m)
{

11
sys/sys/clockintr.h
View file

@ -1,4 +1,4 @@
/* $OpenBSD: clockintr.h,v 1.8 2023/06/15 22:18:06 cheloha Exp $ */
/* $OpenBSD: clockintr.h,v 1.9 2023/07/25 18:16:19 cheloha Exp $ */
/*
* Copyright (c) 2020-2022 Scott Cheloha <cheloha@openbsd.org>
*
@ -112,8 +112,7 @@ struct clockintr_queue {
/* Global state flags. */
#define CL_INIT 0x00000001 /* global init done */
#define CL_STATCLOCK 0x00000002 /* statclock variables set */
#define CL_STATE_MASK 0x00000003
#define CL_STATE_MASK 0x00000001
/* Global behavior flags. */
#define CL_RNDSTAT 0x80000000 /* randomized statclock */
@ -122,13 +121,17 @@ struct clockintr_queue {
void clockintr_cpu_init(const struct intrclock *);
int clockintr_dispatch(void *);
void clockintr_init(u_int);
void clockintr_setstatclockrate(int);
void clockintr_trigger(void);
/*
* Kernel API
*/
uint64_t clockintr_advance(struct clockintr *, uint64_t);
void clockintr_cancel(struct clockintr *);
struct clockintr *clockintr_establish(struct clockintr_queue *,
void (*)(struct clockintr *, void *));
void clockintr_stagger(struct clockintr *, uint64_t, u_int, u_int);
void clockqueue_init(struct clockintr_queue *);
int sysctl_clockintr(int *, u_int, void *, size_t *, void *, size_t);

7
sys/sys/resourcevar.h
View file

@ -1,4 +1,4 @@
/* $OpenBSD: resourcevar.h,v 1.26 2023/04/25 00:58:47 cheloha Exp $ */
/* $OpenBSD: resourcevar.h,v 1.27 2023/07/25 18:16:19 cheloha Exp $ */
/* $NetBSD: resourcevar.h,v 1.12 1995/11/22 23:01:53 cgd Exp $ */
/*
@ -60,8 +60,13 @@ do { \
#include <lib/libkern/libkern.h> /* for KASSERT() */
struct clockintr;
extern uint32_t profclock_period;
void addupc_intr(struct proc *, u_long, u_long);
void addupc_task(struct proc *, u_long, u_int);
void profclock(struct clockintr *, void *);
void tuagg_unlocked(struct process *, struct proc *);
void tuagg(struct process *, struct proc *);
struct tusage;

8
sys/sys/sched.h
View file

@ -1,4 +1,4 @@
/* $OpenBSD: sched.h,v 1.57 2020/12/25 12:49:31 visa Exp $ */
/* $OpenBSD: sched.h,v 1.58 2023/07/25 18:16:19 cheloha Exp $ */
/* $NetBSD: sched.h,v 1.2 1999/02/28 18:14:58 ross Exp $ */
/*-
@ -90,6 +90,7 @@
#define SCHED_NQS 32 /* 32 run queues. */
struct clockintr;
struct smr_entry;
/*
@ -105,8 +106,8 @@ struct schedstate_percpu {
u_int64_t spc_cp_time[CPUSTATES]; /* CPU state statistics */
u_char spc_curpriority; /* usrpri of curproc */
int spc_rrticks; /* ticks until roundrobin() */
int spc_pscnt; /* prof/stat counter */
int spc_psdiv; /* prof/stat divisor */
struct clockintr *spc_profclock; /* [o] profclock handle */
u_int spc_nrun; /* procs on the run queues */
fixpt_t spc_ldavg; /* shortest load avg. for this cpu */
@ -137,6 +138,7 @@ struct cpustats {
#define SPCF_SWITCHCLEAR (SPCF_SEENRR|SPCF_SHOULDYIELD)
#define SPCF_SHOULDHALT 0x0004 /* CPU should be vacated */
#define SPCF_HALTED 0x0008 /* CPU has been halted */
#define SPCF_PROFCLOCK 0x0010 /* profclock() was started */
#define SCHED_PPQ (128 / SCHED_NQS) /* priorities per queue */
#define NICE_WEIGHT 2 /* priorities per nice level */

6
sys/sys/syscall.h
View file

@ -1,10 +1,10 @@
/* $OpenBSD: syscall.h,v 1.263 2023/05/18 10:24:28 mvs Exp $ */
/* $OpenBSD: syscall.h,v 1.264 2023/07/24 19:33:29 miod Exp $ */
/*
* System call numbers.
*
* DO NOT EDIT-- this file is automatically generated.
* created from; OpenBSD: syscalls.master,v 1.248 2023/05/18 10:23:19 mvs Exp
* created from; OpenBSD: syscalls.master,v 1.249 2023/07/24 19:32:23 miod Exp
*/
/* syscall: "syscall" ret: "int" args: "int" "..." */
@ -417,7 +417,7 @@
/* syscall: "adjtime" ret: "int" args: "const struct timeval *" "struct timeval *" */
#define SYS_adjtime 140
/* syscall: "getlogin_r" ret: "int" args: "char *" "u_int" */
/* syscall: "getlogin_r" ret: "int" args: "char *" "size_t" */
#define SYS_getlogin_r 141
/* syscall: "getthrname" ret: "int" args: "pid_t" "char *" "size_t" */

6
sys/sys/syscallargs.h
View file

@ -1,10 +1,10 @@
/* $OpenBSD: syscallargs.h,v 1.266 2023/05/18 10:24:28 mvs Exp $ */
/* $OpenBSD: syscallargs.h,v 1.267 2023/07/24 19:33:29 miod Exp $ */
/*
* System call argument lists.
*
* DO NOT EDIT-- this file is automatically generated.
* created from; OpenBSD: syscalls.master,v 1.248 2023/05/18 10:23:19 mvs Exp
* created from; OpenBSD: syscalls.master,v 1.249 2023/07/24 19:32:23 miod Exp
*/
#ifdef syscallarg
@ -714,7 +714,7 @@ struct sys_adjtime_args {
struct sys_getlogin_r_args {
syscallarg(char *) namebuf;
syscallarg(u_int) namelen;
syscallarg(size_t) namelen;
};
struct sys_getthrname_args {