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This commit is contained in:
purplerain 2023-05-02 22:23:09 +00:00
parent 01bad5edf2
commit f609457dcf
Signed by: purplerain
GPG key ID: F42C07F07E2E35B7
85 changed files with 1589 additions and 1491 deletions
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24
sys/dev/pci/drm/amd/amdgpu/ObjectID.h
View file

@ -1,5 +1,5 @@
/*
* Copyright 2006-2007 Advanced Micro Devices, Inc.
* Copyright 2006-2007 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -37,13 +37,13 @@
#define GRAPH_OBJECT_TYPE_CONNECTOR 0x3
#define GRAPH_OBJECT_TYPE_ROUTER 0x4
/* deleted */
#define GRAPH_OBJECT_TYPE_DISPLAY_PATH 0x6
#define GRAPH_OBJECT_TYPE_DISPLAY_PATH 0x6
#define GRAPH_OBJECT_TYPE_GENERIC 0x7
/****************************************************/
/* Encoder Object ID Definition */
/****************************************************/
#define ENCODER_OBJECT_ID_NONE 0x00
#define ENCODER_OBJECT_ID_NONE 0x00
/* Radeon Class Display Hardware */
#define ENCODER_OBJECT_ID_INTERNAL_LVDS 0x01
@ -96,7 +96,7 @@
/****************************************************/
/* Connector Object ID Definition */
/****************************************************/
#define CONNECTOR_OBJECT_ID_NONE 0x00
#define CONNECTOR_OBJECT_ID_NONE 0x00
#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I 0x01
#define CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I 0x02
#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D 0x03
@ -158,7 +158,7 @@
#define RESERVED1_ID_MASK 0x0800
#define OBJECT_TYPE_MASK 0x7000
#define RESERVED2_ID_MASK 0x8000
#define OBJECT_ID_SHIFT 0x00
#define ENUM_ID_SHIFT 0x08
#define OBJECT_TYPE_SHIFT 0x0C
@ -179,14 +179,14 @@
/* Encoder Object ID definition - Shared with BIOS */
/****************************************************/
/*
#define ENCODER_INTERNAL_LVDS_ENUM_ID1 0x2101
#define ENCODER_INTERNAL_LVDS_ENUM_ID1 0x2101
#define ENCODER_INTERNAL_TMDS1_ENUM_ID1 0x2102
#define ENCODER_INTERNAL_TMDS2_ENUM_ID1 0x2103
#define ENCODER_INTERNAL_DAC1_ENUM_ID1 0x2104
#define ENCODER_INTERNAL_DAC2_ENUM_ID1 0x2105
#define ENCODER_INTERNAL_SDVOA_ENUM_ID1 0x2106
#define ENCODER_INTERNAL_SDVOB_ENUM_ID1 0x2107
#define ENCODER_SIL170B_ENUM_ID1 0x2108
#define ENCODER_SIL170B_ENUM_ID1 0x2108
#define ENCODER_CH7303_ENUM_ID1 0x2109
#define ENCODER_CH7301_ENUM_ID1 0x210A
#define ENCODER_INTERNAL_DVO1_ENUM_ID1 0x210B
@ -200,8 +200,8 @@
#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1 0x2113
#define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1 0x2114
#define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1 0x2115
#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 0x2116
#define ENCODER_SI178_ENUM_ID1 0x2117
#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 0x2116
#define ENCODER_SI178_ENUM_ID1 0x2117
#define ENCODER_MVPU_FPGA_ENUM_ID1 0x2118
#define ENCODER_INTERNAL_DDI_ENUM_ID1 0x2119
#define ENCODER_VT1625_ENUM_ID1 0x211A
@ -316,7 +316,7 @@
#define ENCODER_SI178_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_SI178 << OBJECT_ID_SHIFT)
ENCODER_OBJECT_ID_SI178 << OBJECT_ID_SHIFT)
#define ENCODER_MVPU_FPGA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
@ -324,7 +324,7 @@
#define ENCODER_INTERNAL_DDI_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_INTERNAL_DDI << OBJECT_ID_SHIFT)
ENCODER_OBJECT_ID_INTERNAL_DDI << OBJECT_ID_SHIFT)
#define ENCODER_VT1625_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
@ -352,7 +352,7 @@
#define ENCODER_INTERNAL_KLDSCP_LVTMA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA << OBJECT_ID_SHIFT)
ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA << OBJECT_ID_SHIFT)
#define ENCODER_INTERNAL_UNIPHY1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\

2
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
View file

@ -6137,7 +6137,7 @@ int amdgpu_in_reset(struct amdgpu_device *adev)
{
return atomic_read(&adev->reset_domain->in_gpu_reset);
}
/**
* amdgpu_device_halt() - bring hardware to some kind of halt state
*

2
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
View file

@ -3418,7 +3418,7 @@ amdgpu_init_backlight(struct amdgpu_device *adev)
if (bd == NULL)
return;
drm_connector_list_iter_begin(dev, &conn_iter);
drm_for_each_connector_iter(connector, &conn_iter) {
if (connector->connector_type != DRM_MODE_CONNECTOR_LVDS &&

2
sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c
View file

@ -1100,7 +1100,7 @@ void amdgpu_bo_fini(struct amdgpu_device *adev)
arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
#else
drm_mtrr_del(0, adev->gmc.aper_base, adev->gmc.aper_size, DRM_MTRR_WC);
#endif
}
drm_dev_exit(idx);

2
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
View file

@ -101,7 +101,7 @@ amdgpu_vm_it_iter_next(struct amdgpu_bo_va_mapping *node, uint64_t start,
static void
amdgpu_vm_it_remove(struct amdgpu_bo_va_mapping *node,
struct rb_root_cached *root)
struct rb_root_cached *root)
{
rb_erase_cached(&node->rb, root);
}

4
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
View file

@ -1906,7 +1906,7 @@ static int gfx_v11_0_rlc_load_microcode(struct amdgpu_device *adev)
if (version_minor == 3)
gfx_v11_0_load_rlcp_rlcv_microcode(adev);
}
return 0;
}
@ -3348,7 +3348,7 @@ static int gfx_v11_0_cp_compute_load_microcode(struct amdgpu_device *adev)
}
memcpy(fw, fw_data, fw_size);
amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);

8
sys/dev/pci/drm/amd/amdgpu/imu_v11_0.c
View file

@ -58,7 +58,7 @@ static int imu_v11_0_init_microcode(struct amdgpu_device *adev)
imu_hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data;
adev->gfx.imu_fw_version = le32_to_cpu(imu_hdr->header.ucode_version);
//adev->gfx.imu_feature_version = le32_to_cpu(imu_hdr->ucode_feature_version);
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_IMU_I];
info->ucode_id = AMDGPU_UCODE_ID_IMU_I;
@ -240,9 +240,9 @@ static const struct imu_rlc_ram_golden imu_rlc_ram_golden_11[] =
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_BOT, 0x00000002, 0xe0000000),
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_TOP, 0x00000000, 0xe0000000),
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL2, 0x00020000, 0xe0000000),
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA0_UCODE_SELFLOAD_CONTROL, 0x00000210, 0),
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA1_UCODE_SELFLOAD_CONTROL, 0x00000210, 0),
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCPC_PSP_DEBUG, CPC_PSP_DEBUG__GPA_OVERRIDE_MASK, 0),
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA0_UCODE_SELFLOAD_CONTROL, 0x00000210, 0),
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA1_UCODE_SELFLOAD_CONTROL, 0x00000210, 0),
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCPC_PSP_DEBUG, CPC_PSP_DEBUG__GPA_OVERRIDE_MASK, 0),
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCPG_PSP_DEBUG, CPG_PSP_DEBUG__GPA_OVERRIDE_MASK, 0)
};

2
sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c
View file

@ -186,7 +186,7 @@ static int xgpu_ai_send_access_requests(struct amdgpu_device *adev,
/* Dummy REQ_GPU_INIT_DATA handling */
r = xgpu_ai_poll_msg(adev, IDH_REQ_GPU_INIT_DATA_READY);
/* version set to 0 since dummy */
adev->virt.req_init_data_ver = 0;
adev->virt.req_init_data_ver = 0;
}
return 0;

2
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
View file

@ -273,7 +273,7 @@ static int sdma_v5_0_init_microcode(struct amdgpu_device *adev)
if (ret)
return ret;
}
return ret;
}

2
sys/dev/pci/drm/amd/include/amd_shared.h
View file

@ -60,7 +60,7 @@ enum amd_apu_flags {
* acquires the list of IP blocks for the GPU in use on initialization.
* It can then operate on this list to perform standard driver operations
* such as: init, fini, suspend, resume, etc.
*
*
*
* IP block implementations are named using the following convention:
* <functionality>_v<version> (E.g.: gfx_v6_0).

534
sys/dev/pci/drm/amd/include/atomfirmware.h
View file

File diff suppressed because it is too large Load diff

4
sys/dev/pci/drm/amd/include/atomfirmwareid.h
View file

@ -1,12 +1,12 @@
/****************************************************************************\
*
*
* File Name atomfirmwareid.h
*
* Description ATOM BIOS command/data table ID definition header file
*
* Copyright 2016 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
* and associated documentation files (the "Software"), to deal in the Software without restriction,
* including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so,

22
sys/dev/pci/drm/amd/include/displayobject.h
View file

@ -1,14 +1,14 @@
/****************************************************************************\
*
*
* Module Name displayobjectsoc15.h
* Project
* Device
* Project
* Device
*
* Description Contains the common definitions for display objects for SoC15 products.
*
* Copyright 2014 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
* and associated documentation files (the "Software"), to deal in the Software without restriction,
* including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so,
@ -35,7 +35,7 @@
/****************************************************
* Display Object Type Definition
* Display Object Type Definition
*****************************************************/
enum display_object_type{
DISPLAY_OBJECT_TYPE_NONE =0x00,
@ -45,7 +45,7 @@ DISPLAY_OBJECT_TYPE_CONNECTOR =0x03
};
/****************************************************
* Encorder Object Type Definition
* Encorder Object Type Definition
*****************************************************/
enum encoder_object_type{
ENCODER_OBJECT_ID_NONE =0x00,
@ -56,11 +56,11 @@ ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 =0x03,
/****************************************************
* Connector Object ID Definition
* Connector Object ID Definition
*****************************************************/
enum connector_object_type{
CONNECTOR_OBJECT_ID_NONE =0x00,
CONNECTOR_OBJECT_ID_NONE =0x00,
CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D =0x01,
CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D =0x02,
CONNECTOR_OBJECT_ID_HDMI_TYPE_A =0x03,
@ -72,12 +72,12 @@ CONNECTOR_OBJECT_ID_OPM =0x07
/****************************************************
* Protection Object ID Definition
* Protection Object ID Definition
*****************************************************/
//No need
/****************************************************
* Object ENUM ID Definition
* Object ENUM ID Definition
*****************************************************/
enum object_enum_id{
@ -90,7 +90,7 @@ OBJECT_ENUM_ID6 =0x06
};
/****************************************************
*Object ID Bit definition
*Object ID Bit definition
*****************************************************/
enum object_id_bit{
OBJECT_ID_MASK =0x00FF,

2
sys/dev/pci/drm/amd/include/navi10_ip_offset.h
View file

@ -28,7 +28,7 @@
struct IP_BASE_INSTANCE {
unsigned int segment[MAX_SEGMENT];
};
struct IP_BASE {
struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
} __maybe_unused;

42
sys/dev/pci/drm/amd/include/pptable.h
View file

@ -133,7 +133,7 @@ typedef struct _ATOM_PPLIB_EXTENDEDHEADER
USHORT usUVDTableOffset; //points to ATOM_PPLIB_UVD_Table
USHORT usSAMUTableOffset; //points to ATOM_PPLIB_SAMU_Table
USHORT usPPMTableOffset; //points to ATOM_PPLIB_PPM_Table
USHORT usACPTableOffset; //points to ATOM_PPLIB_ACP_Table
USHORT usACPTableOffset; //points to ATOM_PPLIB_ACP_Table
/* points to ATOM_PPLIB_POWERTUNE_Table */
USHORT usPowerTuneTableOffset;
/* points to ATOM_PPLIB_CLOCK_Voltage_Dependency_Table for sclkVddgfxTable */
@ -223,14 +223,14 @@ typedef struct _ATOM_PPLIB_POWERPLAYTABLE3
typedef struct _ATOM_PPLIB_POWERPLAYTABLE4
{
ATOM_PPLIB_POWERPLAYTABLE3 basicTable3;
ULONG ulGoldenPPID; // PPGen use only
ULONG ulGoldenPPID; // PPGen use only
ULONG ulGoldenRevision; // PPGen use only
USHORT usVddcDependencyOnSCLKOffset;
USHORT usVddciDependencyOnMCLKOffset;
USHORT usVddcDependencyOnMCLKOffset;
USHORT usMaxClockVoltageOnDCOffset;
USHORT usVddcPhaseShedLimitsTableOffset; // Points to ATOM_PPLIB_PhaseSheddingLimits_Table
USHORT usMvddDependencyOnMCLKOffset;
USHORT usMvddDependencyOnMCLKOffset;
} ATOM_PPLIB_POWERPLAYTABLE4, *LPATOM_PPLIB_POWERPLAYTABLE4;
typedef struct _ATOM_PPLIB_POWERPLAYTABLE5
@ -376,21 +376,21 @@ typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO
UCHAR ucMaxHTLinkWidth; // From SBIOS - {2, 4, 8, 16}
UCHAR ucMinHTLinkWidth; // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled. Minimum down stream width could
USHORT usHTLinkFreq; // See definition ATOM_PPLIB_RS780_HTLINKFREQ_xxx or in MHz(>=200).
ULONG ulFlags;
ULONG ulFlags;
} ATOM_PPLIB_RS780_CLOCK_INFO;
#define ATOM_PPLIB_RS780_VOLTAGE_NONE 0
#define ATOM_PPLIB_RS780_VOLTAGE_LOW 1
#define ATOM_PPLIB_RS780_VOLTAGE_HIGH 2
#define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE 3
#define ATOM_PPLIB_RS780_VOLTAGE_NONE 0
#define ATOM_PPLIB_RS780_VOLTAGE_LOW 1
#define ATOM_PPLIB_RS780_VOLTAGE_HIGH 2
#define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE 3
#define ATOM_PPLIB_RS780_SPMCLK_NONE 0 // We cannot change the side port memory clock, leave it as it is.
#define ATOM_PPLIB_RS780_SPMCLK_LOW 1
#define ATOM_PPLIB_RS780_SPMCLK_HIGH 2
#define ATOM_PPLIB_RS780_HTLINKFREQ_NONE 0
#define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1
#define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2
#define ATOM_PPLIB_RS780_HTLINKFREQ_NONE 0
#define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1
#define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2
typedef struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO
{
@ -432,14 +432,14 @@ typedef struct _ATOM_PPLIB_CI_CLOCK_INFO
USHORT usMemoryClockLow;
UCHAR ucMemoryClockHigh;
UCHAR ucPCIEGen;
USHORT usPCIELane;
} ATOM_PPLIB_CI_CLOCK_INFO;
typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO{
USHORT usEngineClockLow; //clockfrequency & 0xFFFF. The unit is in 10khz
UCHAR ucEngineClockHigh; //clockfrequency >> 16.
UCHAR ucEngineClockHigh; //clockfrequency >> 16.
UCHAR vddcIndex; //2-bit vddc index;
USHORT tdpLimit;
//please initalize to 0
@ -464,10 +464,10 @@ typedef struct _ATOM_PPLIB_CZ_CLOCK_INFO {
typedef struct _ATOM_PPLIB_STATE_V2
{
//number of valid dpm levels in this state; Driver uses it to calculate the whole
//number of valid dpm levels in this state; Driver uses it to calculate the whole
//size of the state: sizeof(ATOM_PPLIB_STATE_V2) + (ucNumDPMLevels - 1) * sizeof(UCHAR)
UCHAR ucNumDPMLevels;
//a index to the array of nonClockInfos
UCHAR nonClockInfoIndex;
/**
@ -477,9 +477,9 @@ typedef struct _ATOM_PPLIB_STATE_V2
} ATOM_PPLIB_STATE_V2;
typedef struct _StateArray{
//how many states we have
//how many states we have
UCHAR ucNumEntries;
ATOM_PPLIB_STATE_V2 states[1];
}StateArray;
@ -487,10 +487,10 @@ typedef struct _StateArray{
typedef struct _ClockInfoArray{
//how many clock levels we have
UCHAR ucNumEntries;
//sizeof(ATOM_PPLIB_CLOCK_INFO)
UCHAR ucEntrySize;
UCHAR clockInfo[1];
}ClockInfoArray;
@ -500,7 +500,7 @@ typedef struct _NonClockInfoArray{
UCHAR ucNumEntries;
//sizeof(ATOM_PPLIB_NONCLOCK_INFO)
UCHAR ucEntrySize;
ATOM_PPLIB_NONCLOCK_INFO nonClockInfo[1];
}NonClockInfoArray;
@ -722,7 +722,7 @@ typedef struct _ATOM_PPLIB_PPM_Table
ULONG ulPlatformTDC;
ULONG ulSmallACPlatformTDC;
ULONG ulApuTDP;
ULONG ulDGpuTDP;
ULONG ulDGpuTDP;
ULONG ulDGpuUlvPower;
ULONG ulTjmax;
} ATOM_PPLIB_PPM_Table;

10
sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h
View file

@ -365,7 +365,7 @@ typedef struct {
uint16_t FanMaximumRpm;
uint16_t FanTargetTemperature;
uint16_t FanTargetGfxclk;
uint8_t FanZeroRpmEnable;
uint8_t FanZeroRpmEnable;
uint8_t FanTachEdgePerRev;
@ -659,8 +659,8 @@ typedef struct {
uint8_t Gfx_IdleHystLimit;
uint8_t Gfx_FPS;
uint8_t Gfx_MinActiveFreqType;
uint8_t Gfx_BoosterFreqType;
uint8_t Gfx_UseRlcBusy;
uint8_t Gfx_BoosterFreqType;
uint8_t Gfx_UseRlcBusy;
uint16_t Gfx_MinActiveFreq;
uint16_t Gfx_BoosterFreq;
uint16_t Gfx_PD_Data_time_constant;
@ -674,7 +674,7 @@ typedef struct {
uint8_t Soc_IdleHystLimit;
uint8_t Soc_FPS;
uint8_t Soc_MinActiveFreqType;
uint8_t Soc_BoosterFreqType;
uint8_t Soc_BoosterFreqType;
uint8_t Soc_UseRlcBusy;
uint16_t Soc_MinActiveFreq;
uint16_t Soc_BoosterFreq;
@ -690,7 +690,7 @@ typedef struct {
uint8_t Mem_FPS;
uint8_t Mem_MinActiveFreqType;
uint8_t Mem_BoosterFreqType;
uint8_t Mem_UseRlcBusy;
uint8_t Mem_UseRlcBusy;
uint16_t Mem_MinActiveFreq;
uint16_t Mem_BoosterFreq;
uint16_t Mem_PD_Data_time_constant;

4
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
View file

@ -1312,8 +1312,8 @@ struct pptable_funcs {
* @get_ecc_table: message SMU to get ECC INFO table.
*/
ssize_t (*get_ecc_info)(struct smu_context *smu, void *table);
/**
* @stb_collect_info: Collects Smart Trace Buffers data.
*/