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This commit is contained in:
purplerain 2023-07-10 00:10:46 +00:00
parent 2a351e0cdc
commit f57be82572
Signed by: purplerain
GPG key ID: F42C07F07E2E35B7
704 changed files with 20524 additions and 10572 deletions
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222
sys/dev/acpi/acpi.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: acpi.c,v 1.423 2023/07/06 06:58:07 deraadt Exp $ */
/* $OpenBSD: acpi.c,v 1.425 2023/07/08 08:01:10 tobhe Exp $ */
/*
* Copyright (c) 2005 Thorsten Lockert <tholo@sigmasoft.com>
* Copyright (c) 2005 Jordan Hargrave <jordan@openbsd.org>
@ -28,10 +28,6 @@
#include <sys/kthread.h>
#include <sys/sched.h>
#ifdef HIBERNATE
#include <sys/hibernate.h>
#endif
#include <machine/conf.h>
#include <machine/cpufunc.h>
@ -47,10 +43,6 @@
#include <dev/pci/pciidevar.h>
#include <machine/apmvar.h>
#define APMUNIT(dev) (minor(dev)&0xf0)
#define APMDEV(dev) (minor(dev)&0x0f)
#define APMDEV_NORMAL 0
#define APMDEV_CTL 8
#include "wd.h"
@ -3270,6 +3262,17 @@ acpi_foundsbs(struct aml_node *node, void *arg)
return (0);
}
int
acpi_batcount(struct acpi_softc *sc)
{
struct acpi_bat *bat;
int count = 0;
SLIST_FOREACH(bat, &sc->sc_bat, aba_link)
count++;
return count;
}
int
acpi_apminfo(struct apm_power_info *pi)
{
@ -3373,134 +3376,6 @@ acpi_apminfo(struct apm_power_info *pi)
return 0;
}
int
acpiopen(dev_t dev, int flag, int mode, struct proc *p)
{
int error = 0;
struct acpi_softc *sc;
int s;
if (!acpi_cd.cd_ndevs || APMUNIT(dev) != 0 ||
!(sc = acpi_cd.cd_devs[APMUNIT(dev)]))
return (ENXIO);
s = splbio();
switch (APMDEV(dev)) {
case APMDEV_CTL:
if (!(flag & FWRITE)) {
error = EINVAL;
break;
}
if (sc->sc_flags & SCFLAG_OWRITE) {
error = EBUSY;
break;
}
sc->sc_flags |= SCFLAG_OWRITE;
break;
case APMDEV_NORMAL:
if (!(flag & FREAD) || (flag & FWRITE)) {
error = EINVAL;
break;
}
sc->sc_flags |= SCFLAG_OREAD;
break;
default:
error = ENXIO;
break;
}
splx(s);
return (error);
}
int
acpiclose(dev_t dev, int flag, int mode, struct proc *p)
{
int error = 0;
struct acpi_softc *sc;
int s;
if (!acpi_cd.cd_ndevs || APMUNIT(dev) != 0 ||
!(sc = acpi_cd.cd_devs[APMUNIT(dev)]))
return (ENXIO);
s = splbio();
switch (APMDEV(dev)) {
case APMDEV_CTL:
sc->sc_flags &= ~SCFLAG_OWRITE;
break;
case APMDEV_NORMAL:
sc->sc_flags &= ~SCFLAG_OREAD;
break;
default:
error = ENXIO;
break;
}
splx(s);
return (error);
}
int
acpiioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p)
{
int error = 0;
struct acpi_softc *sc;
struct apm_power_info *pi = (struct apm_power_info *)data;
int s;
if (!acpi_cd.cd_ndevs || APMUNIT(dev) != 0 ||
!(sc = acpi_cd.cd_devs[APMUNIT(dev)]))
return (ENXIO);
s = splbio();
/* fake APM */
switch (cmd) {
case APM_IOC_SUSPEND:
case APM_IOC_STANDBY:
if ((flag & FWRITE) == 0) {
error = EBADF;
break;
}
acpi_addtask(sc, acpi_sleep_task, sc, SLEEP_SUSPEND);
acpi_wakeup(sc);
break;
#ifdef HIBERNATE
case APM_IOC_HIBERNATE:
if ((error = suser(p)) != 0)
break;
if ((flag & FWRITE) == 0) {
error = EBADF;
break;
}
if (get_hibernate_io_function(swdevt[0].sw_dev) == NULL) {
error = EOPNOTSUPP;
break;
}
acpi_addtask(sc, acpi_sleep_task, sc, SLEEP_HIBERNATE);
acpi_wakeup(sc);
break;
#endif
case APM_IOC_GETPOWER:
error = acpi_apminfo(pi);
break;
default:
error = ENOTTY;
}
splx(s);
return (error);
}
void acpi_filtdetach(struct knote *);
int acpi_filtread(struct knote *, long);
const struct filterops acpiread_filtops = {
.f_flags = FILTEROP_ISFD,
.f_attach = NULL,
.f_detach = acpi_filtdetach,
.f_event = acpi_filtread,
};
int acpi_evindex;
int
@ -3514,77 +3389,4 @@ acpi_record_event(struct acpi_softc *sc, u_int type)
return (0);
}
void
acpi_filtdetach(struct knote *kn)
{
struct acpi_softc *sc = kn->kn_hook;
int s;
s = splbio();
klist_remove_locked(&sc->sc_note, kn);
splx(s);
}
int
acpi_filtread(struct knote *kn, long hint)
{
/* XXX weird kqueue_scan() semantics */
if (hint && !kn->kn_data)
kn->kn_data = hint;
return (1);
}
int
acpikqfilter(dev_t dev, struct knote *kn)
{
struct acpi_softc *sc;
int s;
if (!acpi_cd.cd_ndevs || APMUNIT(dev) != 0 ||
!(sc = acpi_cd.cd_devs[APMUNIT(dev)]))
return (ENXIO);
switch (kn->kn_filter) {
case EVFILT_READ:
kn->kn_fop = &acpiread_filtops;
break;
default:
return (EINVAL);
}
kn->kn_hook = sc;
s = splbio();
klist_insert_locked(&sc->sc_note, kn);
splx(s);
return (0);
}
#else /* SMALL_KERNEL */
int
acpiopen(dev_t dev, int flag, int mode, struct proc *p)
{
return (ENXIO);
}
int
acpiclose(dev_t dev, int flag, int mode, struct proc *p)
{
return (ENXIO);
}
int
acpiioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p)
{
return (ENXIO);
}
int
acpikqfilter(dev_t dev, struct knote *kn)
{
return (EOPNOTSUPP);
}
#endif /* SMALL_KERNEL */

251
sys/dev/acpi/acpi_apm.c Normal file
View file

@ -0,0 +1,251 @@
/* $OpenBSD: acpi_apm.c,v 1.2 2023/07/08 14:44:43 tobhe Exp $ */
/*
* Copyright (c) 2005 Thorsten Lockert <tholo@sigmasoft.com>
* Copyright (c) 2005 Jordan Hargrave <jordan@openbsd.org>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/fcntl.h>
#include <dev/acpi/acpireg.h>
#include <dev/acpi/acpivar.h>
#include <dev/acpi/acpidev.h>
#include <dev/acpi/dsdt.h>
#include <machine/conf.h>
#include <machine/cpufunc.h>
#ifdef HIBERNATE
#include <sys/hibernate.h>
#endif
#include <machine/apmvar.h>
#define APMUNIT(dev) (minor(dev)&0xf0)
#define APMDEV(dev) (minor(dev)&0x0f)
#define APMDEV_NORMAL 0
#define APMDEV_CTL 8
#ifndef SMALL_KERNEL
int
acpiopen(dev_t dev, int flag, int mode, struct proc *p)
{
int error = 0;
struct acpi_softc *sc = acpi_softc;
int s;
s = splbio();
switch (APMDEV(dev)) {
case APMDEV_CTL:
if (!(flag & FWRITE)) {
error = EINVAL;
break;
}
if (sc->sc_flags & SCFLAG_OWRITE) {
error = EBUSY;
break;
}
sc->sc_flags |= SCFLAG_OWRITE;
break;
case APMDEV_NORMAL:
if (!(flag & FREAD) || (flag & FWRITE)) {
error = EINVAL;
break;
}
sc->sc_flags |= SCFLAG_OREAD;
break;
default:
error = ENXIO;
break;
}
splx(s);
return (error);
}
int
acpiclose(dev_t dev, int flag, int mode, struct proc *p)
{
int error = 0;
struct acpi_softc *sc = acpi_softc;
int s;
s = splbio();
switch (APMDEV(dev)) {
case APMDEV_CTL:
sc->sc_flags &= ~SCFLAG_OWRITE;
break;
case APMDEV_NORMAL:
sc->sc_flags &= ~SCFLAG_OREAD;
break;
default:
error = ENXIO;
break;
}
splx(s);
return (error);
}
int
acpiioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p)
{
int error = 0;
struct acpi_softc *sc = acpi_softc;
struct apm_power_info *pi = (struct apm_power_info *)data;
int s;
s = splbio();
/* fake APM */
switch (cmd) {
#ifdef SUSPEND
case APM_IOC_SUSPEND:
case APM_IOC_STANDBY:
if ((flag & FWRITE) == 0) {
error = EBADF;
break;
}
error = request_sleep(SLEEP_SUSPEND);
if (error)
break;
acpi_wakeup(sc);
break;
#ifdef HIBERNATE
case APM_IOC_HIBERNATE:
if ((error = suser(p)) != 0)
break;
if ((flag & FWRITE) == 0) {
error = EBADF;
break;
}
if (get_hibernate_io_function(swdevt[0].sw_dev) == NULL) {
error = EOPNOTSUPP;
break;
}
error = request_sleep(SLEEP_HIBERNATE);
if (error)
break;
acpi_wakeup(sc);
break;
#endif
#endif
case APM_IOC_GETPOWER:
error = acpi_apminfo(pi);
break;
default:
error = ENOTTY;
}
splx(s);
return (error);
}
void acpi_filtdetach(struct knote *);
int acpi_filtread(struct knote *, long);
const struct filterops acpiread_filtops = {
.f_flags = FILTEROP_ISFD,
.f_attach = NULL,
.f_detach = acpi_filtdetach,
.f_event = acpi_filtread,
};
int
acpikqfilter(dev_t dev, struct knote *kn)
{
struct acpi_softc *sc = acpi_softc;
int s;
switch (kn->kn_filter) {
case EVFILT_READ:
kn->kn_fop = &acpiread_filtops;
break;
default:
return (EINVAL);
}
kn->kn_hook = sc;
s = splbio();
klist_insert_locked(&sc->sc_note, kn);
splx(s);
return (0);
}
void
acpi_filtdetach(struct knote *kn)
{
struct acpi_softc *sc = kn->kn_hook;
int s;
s = splbio();
klist_remove_locked(&sc->sc_note, kn);
splx(s);
}
int
acpi_filtread(struct knote *kn, long hint)
{
/* XXX weird kqueue_scan() semantics */
if (hint && !kn->kn_data)
kn->kn_data = hint;
return (1);
}
#ifdef SUSPEND
int
request_sleep(int sleepmode)
{
struct acpi_softc *sc = acpi_softc;
#ifdef HIBERNATE
if (sleepmode == SLEEP_HIBERNATE) {
if (get_hibernate_io_function(swdevt[0].sw_dev) == NULL)
return EOPNOTSUPP;
}
#endif
acpi_addtask(sc, acpi_sleep_task, sc, sleepmode);
return 0;
}
#endif /* SUSPEND */
#else /* SMALL_KERNEL */
int
acpiopen(dev_t dev, int flag, int mode, struct proc *p)
{
return (ENXIO);
}
int
acpiclose(dev_t dev, int flag, int mode, struct proc *p)
{
return (ENXIO);
}
int
acpiioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p)
{
return (ENXIO);
}
int
acpikqfilter(dev_t dev, struct knote *kn)
{
return (EOPNOTSUPP);
}
#endif /* SMALL_KERNEL */

74
sys/dev/acpi/acpithinkpad.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: acpithinkpad.c,v 1.73 2023/05/20 12:02:46 kettenis Exp $ */
/* $OpenBSD: acpithinkpad.c,v 1.74 2023/07/07 07:37:59 claudio Exp $ */
/*
* Copyright (c) 2008 joshua stein <jcs@openbsd.org>
*
@ -906,16 +906,18 @@ thinkpad_battery_inhibit_charge(int state)
{
struct acpithinkpad_softc *sc = acpithinkpad_cd.cd_devs[0];
struct aml_value arg;
int battery = 1;
int battery, count;
uint64_t ret;
memset(&arg, 0, sizeof(arg));
arg.type = AML_OBJTYPE_INTEGER;
arg.v_integer = (0xffff << 8) | (battery << 4) | state;
if (aml_evalinteger(sc->sc_acpi, sc->sc_devnode, "BICS",
1, &arg, &ret) || (ret & THINKPAD_BATTERY_ERROR))
return EIO;
count = acpi_batcount(sc->sc_acpi);
for (battery = 1; battery <= count; battery++) {
memset(&arg, 0, sizeof(arg));
arg.type = AML_OBJTYPE_INTEGER;
arg.v_integer = (0xffff << 8) | (battery << 4) | state;
if (aml_evalinteger(sc->sc_acpi, sc->sc_devnode, "BICS",
1, &arg, &ret) || (ret & THINKPAD_BATTERY_ERROR))
return EIO;
}
return 0;
}
@ -924,16 +926,18 @@ thinkpad_battery_force_discharge(int state)
{
struct acpithinkpad_softc *sc = acpithinkpad_cd.cd_devs[0];
struct aml_value arg;
int battery = 1;
int battery, count;
uint64_t ret;
memset(&arg, 0, sizeof(arg));
arg.type = AML_OBJTYPE_INTEGER;
arg.v_integer = (battery << THINKPAD_BATTERY_SHIFT) | state;
if (aml_evalinteger(sc->sc_acpi, sc->sc_devnode, "BDSS",
1, &arg, &ret) || (ret & THINKPAD_BATTERY_ERROR))
return EIO;
count = acpi_batcount(sc->sc_acpi);
for (battery = 1; battery <= count; battery++) {
memset(&arg, 0, sizeof(arg));
arg.type = AML_OBJTYPE_INTEGER;
arg.v_integer = (battery << THINKPAD_BATTERY_SHIFT) | state;
if (aml_evalinteger(sc->sc_acpi, sc->sc_devnode, "BDSS",
1, &arg, &ret) || (ret & THINKPAD_BATTERY_ERROR))
return EIO;
}
return 0;
}
@ -980,19 +984,21 @@ thinkpad_battery_setchargestart(int start)
{
struct acpithinkpad_softc *sc = acpithinkpad_cd.cd_devs[0];
struct aml_value arg;
int battery = 1;
int battery, count;
uint64_t ret;
if (start >= hw_battery_chargestop)
return EINVAL;
memset(&arg, 0, sizeof(arg));
arg.type = AML_OBJTYPE_INTEGER;
arg.v_integer = (battery << THINKPAD_BATTERY_SHIFT) | start;
if (aml_evalinteger(sc->sc_acpi, sc->sc_devnode, "BCCS",
1, &arg, &ret) || (ret & THINKPAD_BATTERY_ERROR))
return EIO;
count = acpi_batcount(sc->sc_acpi);
for (battery = 1; battery <= count; battery++) {
memset(&arg, 0, sizeof(arg));
arg.type = AML_OBJTYPE_INTEGER;
arg.v_integer = (battery << THINKPAD_BATTERY_SHIFT) | start;
if (aml_evalinteger(sc->sc_acpi, sc->sc_devnode, "BCCS",
1, &arg, &ret) || (ret & THINKPAD_BATTERY_ERROR))
return EIO;
}
hw_battery_chargestart = start;
return 0;
}
@ -1002,7 +1008,7 @@ thinkpad_battery_setchargestop(int stop)
{
struct acpithinkpad_softc *sc = acpithinkpad_cd.cd_devs[0];
struct aml_value arg;
int battery = 1;
int battery, count;
uint64_t ret;
if (stop <= hw_battery_chargestart)
@ -1011,13 +1017,15 @@ thinkpad_battery_setchargestop(int stop)
if (stop == 100)
stop = 0;
memset(&arg, 0, sizeof(arg));
arg.type = AML_OBJTYPE_INTEGER;
arg.v_integer = (battery << THINKPAD_BATTERY_SHIFT) | stop;
if (aml_evalinteger(sc->sc_acpi, sc->sc_devnode, "BCSS",
1, &arg, &ret) || (ret & THINKPAD_BATTERY_ERROR))
return EIO;
count = acpi_batcount(sc->sc_acpi);
for (battery = 1; battery <= count; battery++) {
memset(&arg, 0, sizeof(arg));
arg.type = AML_OBJTYPE_INTEGER;
arg.v_integer = (battery << THINKPAD_BATTERY_SHIFT) | stop;
if (aml_evalinteger(sc->sc_acpi, sc->sc_devnode, "BCSS",
1, &arg, &ret) || (ret & THINKPAD_BATTERY_ERROR))
return EIO;
}
hw_battery_chargestop = (stop == 0) ? 100 : stop;
return 0;
}

3
sys/dev/acpi/acpivar.h
View file

@ -1,4 +1,4 @@
/* $OpenBSD: acpivar.h,v 1.123 2023/06/29 20:58:08 dv Exp $ */
/* $OpenBSD: acpivar.h,v 1.124 2023/07/07 07:37:59 claudio Exp $ */
/*
* Copyright (c) 2005 Thorsten Lockert <tholo@sigmasoft.com>
*
@ -385,6 +385,7 @@ void acpi_indicator(struct acpi_softc *, int);
void acpi_disable_allgpes(struct acpi_softc *);
void acpi_enable_wakegpes(struct acpi_softc *, int);
int acpi_batcount(struct acpi_softc *);
struct apm_power_info;
int acpi_apminfo(struct apm_power_info *);

89
sys/dev/acpi/dwiic_acpi.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: dwiic_acpi.c,v 1.21 2023/04/23 00:33:02 dlg Exp $ */
/* $OpenBSD: dwiic_acpi.c,v 1.22 2023/07/08 02:43:02 jcs Exp $ */
/*
* Synopsys DesignWare I2C controller
*
@ -50,6 +50,8 @@ int dwiic_acpi_found_ihidev(struct dwiic_softc *,
struct aml_node *, char *, struct dwiic_crs);
int dwiic_acpi_found_iatp(struct dwiic_softc *, struct aml_node *,
char *, struct dwiic_crs);
int dwiic_acpi_found_ietp(struct dwiic_softc *, struct aml_node *,
char *, struct dwiic_crs);
void dwiic_acpi_get_params(struct dwiic_softc *, char *, uint16_t *,
uint16_t *, uint32_t *);
void dwiic_acpi_power(struct dwiic_softc *, int);
@ -87,6 +89,63 @@ const char *ihidev_hids[] = {
NULL
};
const char *ietp_hids[] = {
"ELAN0000",
"ELAN0100",
"ELAN0600",
"ELAN0601",
"ELAN0602",
"ELAN0603",
"ELAN0604",
"ELAN0605",
"ELAN0606",
"ELAN0607",
"ELAN0608",
"ELAN0609",
"ELAN060B",
"ELAN060C",
"ELAN060F",
"ELAN0610",
"ELAN0611",
"ELAN0612",
"ELAN0615",
"ELAN0616",
"ELAN0617",
"ELAN0618",
"ELAN0619",
"ELAN061A",
"ELAN061B",
"ELAN061C",
"ELAN061D",
"ELAN061E",
"ELAN061F",
"ELAN0620",
"ELAN0621",
"ELAN0622",
"ELAN0623",
"ELAN0624",
"ELAN0625",
"ELAN0626",
"ELAN0627",
"ELAN0628",
"ELAN0629",
"ELAN062A",
"ELAN062B",
"ELAN062C",
"ELAN062D",
"ELAN062E", /* Lenovo V340 Whiskey Lake U */
"ELAN062F", /* Lenovo V340 Comet Lake U */
"ELAN0631",
"ELAN0632",
"ELAN0633", /* Lenovo S145 */
"ELAN0634", /* Lenovo V340 Ice lake */
"ELAN0635", /* Lenovo V1415-IIL */
"ELAN0636", /* Lenovo V1415-Dali */
"ELAN0637", /* Lenovo V1415-IGLR */
"ELAN1000",
NULL
};
const char *iatp_hids[] = {
"ATML0000",
"ATML0001",
@ -417,6 +476,8 @@ dwiic_acpi_found_hid(struct aml_node *node, void *arg)
return dwiic_acpi_found_ihidev(sc, node, dev, crs);
else if (dwiic_matchhids(dev, iatp_hids))
return dwiic_acpi_found_iatp(sc, node, dev, crs);
else if (dwiic_matchhids(dev, ietp_hids) || dwiic_matchhids(cdev, ietp_hids))
return dwiic_acpi_found_ietp(sc, node, dev, crs);
memset(&ia, 0, sizeof(ia));
ia.ia_tag = sc->sc_iba.iba_tag;
@ -504,6 +565,32 @@ dwiic_acpi_found_ihidev(struct dwiic_softc *sc, struct aml_node *node,
return 1;
}
int
dwiic_acpi_found_ietp(struct dwiic_softc *sc, struct aml_node *node,
char *dev, struct dwiic_crs crs)
{
struct i2c_attach_args ia;
memset(&ia, 0, sizeof(ia));
ia.ia_tag = sc->sc_iba.iba_tag;
ia.ia_size = 1;
ia.ia_name = "ietp";
ia.ia_addr = crs.i2c_addr;
ia.ia_cookie = dev;
if (sc->sc_poll_ihidev)
ia.ia_poll = 1;
if (!(crs.irq_int == 0 && crs.gpio_int_node == NULL))
ia.ia_intr = &crs;
if (config_found(sc->sc_iic, &ia, dwiic_i2c_print)) {
node->parent->attached = 1;
return 0;
}
return 1;
}
int
dwiic_acpi_found_iatp(struct dwiic_softc *sc, struct aml_node *node, char *dev,
struct dwiic_crs crs)

4
sys/dev/dt/dt_prov_static.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: dt_prov_static.c,v 1.19 2023/06/28 11:49:49 kn Exp $ */
/* $OpenBSD: dt_prov_static.c,v 1.20 2023/07/06 19:46:53 kn Exp $ */
/*
* Copyright (c) 2019 Martin Pieuchot <mpi@openbsd.org>
@ -92,6 +92,7 @@ DT_STATIC_PROBE2(smr, thread, "uint64_t", "uint64_t");
* reference counting, keep in sync with sys/refcnt.h
*/
DT_STATIC_PROBE0(refcnt, none);
DT_STATIC_PROBE3(refcnt, ethmulti, "void *", "int", "int");
DT_STATIC_PROBE3(refcnt, ifaddr, "void *", "int", "int");
DT_STATIC_PROBE3(refcnt, ifmaddr, "void *", "int", "int");
DT_STATIC_PROBE3(refcnt, inpcb, "void *", "int", "int");
@ -140,6 +141,7 @@ struct dt_probe *const dtps_static[] = {
&_DT_STATIC_P(smr, thread),
/* refcnt */
&_DT_STATIC_P(refcnt, none),
&_DT_STATIC_P(refcnt, ethmulti),
&_DT_STATIC_P(refcnt, ifaddr),
&_DT_STATIC_P(refcnt, ifmaddr),
&_DT_STATIC_P(refcnt, inpcb),

192
sys/dev/fdt/axppmic.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: axppmic.c,v 1.16 2022/09/03 18:05:10 kettenis Exp $ */
/* $OpenBSD: axppmic.c,v 1.17 2023/07/06 20:02:36 uaa Exp $ */
/*
* Copyright (c) 2017 Mark Kettenis <kettenis@openbsd.org>
*
@ -65,180 +65,180 @@ struct axppmic_regdata {
const char *name;
uint8_t ereg, emask, eval, dval;
uint8_t vreg, vmask;
uint32_t base, delta;
uint32_t base2, delta2;
uint32_t base, delta, nsteps;
uint32_t base2, delta2, nsteps2;
};
const struct axppmic_regdata axp209_regdata[] = {
{ "dcdc2", 0x12, (1 << 4), (1 << 4), (0 << 4),
0x23, 0x3f, 700000, 25000 },
0x23, 0x3f, 700000, 25000, 64 },
{ "dcdc3", 0x12, (1 << 1), (1 << 1), (0 << 1),
0x27, 0x3f, 700000, 25000 },
0x27, 0x7f, 700000, 25000, 113 },
/* LDO1 can't be controlled */
{ "ldo2", 0x12, (1 << 2), (1 << 2), (0 << 2),
0x28, 0xf0, 1800000, (100000 >> 4) },
0x28, 0xf0, 1800000, (100000 >> 4), (16 << 4) },
{ "ldo3", 0x12, (1 << 6), (1 << 6), (0 << 6),
0x29, 0x7f, 700000, 25000 },
0x29, 0x7f, 700000, 25000, 113 },
/* LDO4 voltage levels are complicated */
{ "ldo5", 0x90, 0x07, 0x03, 0x07,
0x91, 0xf0, 1800000, (100000 >> 4) },
0x91, 0xf0, 1800000, (100000 >> 4), (16 << 4) },
{ NULL }
};
const struct axppmic_regdata axp221_regdata[] = {
{ "dcdc1", 0x10, (1 << 1), (1 << 1), (0 << 1),
0x21, 0x1f, 1600000, 100000 },
0x21, 0x1f, 1600000, 100000, 19 },
{ "dcdc2", 0x10, (1 << 2), (1 << 2), (0 << 2),
0x22, 0x3f, 600000, 20000 },
0x22, 0x3f, 600000, 20000, 48 },
{ "dcdc3", 0x10, (1 << 3), (1 << 3), (0 << 3),
0x23, 0x3f, 600000, 20000 },
0x23, 0x3f, 600000, 20000, 64 },
{ "dcdc4", 0x10, (1 << 4), (1 << 4), (0 << 4),
0x24, 0x3f, 600000, 20000 },
0x24, 0x3f, 600000, 20000, 48 },
{ "dcdc5", 0x10, (1 << 5), (1 << 5), (0 << 5),
0x25, 0x1f, 1000000, 50000 },
0x25, 0x1f, 1000000, 50000, 32 },
{ "dc1sw", 0x12, (1 << 7), (1 << 7), (0 << 7) },
{ "dc5ldo", 0x10, (1 << 0), (1 << 0), (0 << 0),
0x1c, 0x07, 700000, 100000 },
0x1c, 0x07, 700000, 100000, 8 },
{ "aldo1", 0x10, (1 << 6), (1 << 6), (0 << 6),
0x28, 0x1f, 700000, 100000 },
0x28, 0x1f, 700000, 100000, 27 },
{ "aldo2", 0x10, (1 << 7), (1 << 7), (0 << 7),
0x29, 0x1f, 700000, 100000 },
0x29, 0x1f, 700000, 100000, 27 },
{ "aldo3", 0x13, (1 << 7), (1 << 7), (0 << 7),
0x2a, 0x1f, 700000, 100000 },
0x2a, 0x1f, 700000, 100000, 27 },
{ "dldo1", 0x12, (1 << 3), (1 << 3), (0 << 3),
0x15, 0x1f, 700000, 100000 },
0x15, 0x1f, 700000, 100000, 27 },
{ "dldo2", 0x12, (1 << 4), (1 << 4), (0 << 4),
0x16, 0x1f, 700000, 100000 },
0x16, 0x1f, 700000, 100000, 27 },
{ "dldo3", 0x12, (1 << 5), (1 << 5), (0 << 5),
0x17, 0x1f, 700000, 100000 },
0x17, 0x1f, 700000, 100000, 27 },
{ "dldo4", 0x12, (1 << 6), (1 << 6), (0 << 6),
0x18, 0x1f, 700000, 100000 },
0x18, 0x1f, 700000, 100000, 27 },
{ "eldo1", 0x12, (1 << 0), (1 << 0), (0 << 0),
0x19, 0x1f, 700000, 100000 },
0x19, 0x1f, 700000, 100000, 27 },
{ "eldo2", 0x12, (1 << 1), (1 << 1), (0 << 1),
0x1a, 0x1f, 700000, 100000 },
0x1a, 0x1f, 700000, 100000, 27 },
{ "eldo3", 0x12, (1 << 2), (1 << 2), (0 << 2),
0x1b, 0x1f, 700000, 100000 },
0x1b, 0x1f, 700000, 100000, 27 },
{ "ldo_io0", 0x90, 0x07, 0x03, 0x04,
0x91, 0x1f, 700000, 100000 },
0x91, 0x1f, 700000, 100000, 27 },
{ "ldo_io1", 0x92, 0x07, 0x03, 0x04,
0x93, 0x1f, 700000, 100000 },
0x93, 0x1f, 700000, 100000, 27 },
{ NULL }
};
const struct axppmic_regdata axp803_regdata[] = {
{ "dcdc1", 0x10, (1 << 0), (1 << 0), (0 << 0),
0x20, 0x1f, 1600000, 100000 },
0x20, 0x1f, 1600000, 100000, 19 },
{ "dcdc2", 0x10, (1 << 1), (1 << 1), (0 << 1),
0x21, 0x7f, 500000, 10000, 1220000, 20000 },
0x21, 0x7f, 500000, 10000, 71, 1220000, 20000, 5 },
{ "dcdc3", 0x10, (1 << 2), (1 << 2), (0 << 2),
0x22, 0x7f, 500000, 10000, 1220000, 20000 },
0x22, 0x7f, 500000, 10000, 71, 1220000, 20000, 5 },
{ "dcdc4", 0x10, (1 << 3), (1 << 3), (0 << 3),
0x23, 0x7f, 500000, 10000, 1220000, 20000 },
0x23, 0x7f, 500000, 10000, 71, 1220000, 20000, 5 },
{ "dcdc5", 0x10, (1 << 4), (1 << 4), (0 << 4),
0x24, 0x7f, 800000, 10000, 1140000, 20000 },
0x24, 0x7f, 800000, 10000, 33, 1140000, 20000, 36 },
{ "dcdc6", 0x10, (1 << 5), (1 << 5), (0 << 5),
0x25, 0x7f, 600000, 10000, 1120000, 20000 },
0x25, 0x7f, 600000, 10000, 51, 1120000, 20000, 21 },
{ "dc1sw", 0x12, (1 << 7), (1 << 7), (0 << 7) },
{ "aldo1", 0x13, (1 << 5), (1 << 5), (0 << 5),
0x28, 0x1f, 700000, 100000 },
0x28, 0x1f, 700000, 100000, 27 },
{ "aldo2", 0x13, (1 << 6), (1 << 6), (0 << 6),
0x29, 0x1f, 700000, 100000 },
0x29, 0x1f, 700000, 100000, 27 },
{ "aldo3", 0x13, (1 << 7), (1 << 7), (0 << 7),
0x2a, 0x1f, 700000, 100000 },
0x2a, 0x1f, 700000, 100000, 27 },
{ "dldo1", 0x12, (1 << 3), (1 << 3), (0 << 3),
0x15, 0x1f, 700000, 100000 },
0x15, 0x1f, 700000, 100000, 27 },
{ "dldo2", 0x12, (1 << 4), (1 << 4), (0 << 4),
0x16, 0x1f, 700000, 100000, 3400000, 200000 },
0x16, 0x1f, 700000, 100000, 27, 3400000, 200000, 5 },
{ "dldo3", 0x12, (1 << 5), (1 << 5), (0 << 5),
0x17, 0x1f, 700000, 100000 },
0x17, 0x1f, 700000, 100000, 27 },
{ "dldo4", 0x12, (1 << 6), (1 << 6), (0 << 6),
0x18, 0x1f, 700000, 100000 },
0x18, 0x1f, 700000, 100000, 27 },
{ "eldo1", 0x12, (1 << 0), (1 << 0), (0 << 0),
0x19, 0x1f, 700000, 50000 },
0x19, 0x1f, 700000, 50000, 25 },
{ "eldo2", 0x12, (1 << 1), (1 << 1), (0 << 1),
0x1a, 0x1f, 700000, 50000 },
0x1a, 0x1f, 700000, 50000, 25 },
{ "eldo3", 0x12, (1 << 2), (1 << 2), (0 << 2),
0x1b, 0x1f, 700000, 50000 },
0x1b, 0x1f, 700000, 50000, 25 },
{ "fldo1", 0x13, (1 << 2), (1 << 2), (0 << 2),
0x1c, 0x0f, 700000, 50000 },
0x1c, 0x0f, 700000, 50000, 16 },
{ "fldo2", 0x13, (1 << 3), (1 << 3), (0 << 3),
0x1d, 0x0f, 700000, 50000 },
0x1d, 0x0f, 700000, 50000, 16 },
{ "ldo-io0", 0x90, 0x07, 0x03, 0x04,
0x91, 0x1f, 700000, 100000 },
0x91, 0x1f, 700000, 100000, 27 },
{ "ldo-io1", 0x92, 0x07, 0x03, 0x04,
0x93, 0x1f, 700000, 100000 },
0x93, 0x1f, 700000, 100000, 27 },
{ NULL }
};
const struct axppmic_regdata axp806_regdata[] = {
{ "dcdca", 0x10, (1 << 0), (1 << 0), (0 << 0),
0x12, 0x7f, 600000, 10000, 1120000, 20000 },
0x12, 0x7f, 600000, 10000, 51, 1120000, 20000, 21 },
{ "dcdcb", 0x10, (1 << 1), (1 << 1), (0 << 1),
0x13, 0x1f, 1000000, 50000 },
0x13, 0x1f, 1000000, 50000, 32 },
{ "dcdcc", 0x10, (1 << 2), (1 << 2), (0 << 2),
0x14, 0x7f, 600000, 10000, 1120000, 20000 },
0x14, 0x7f, 600000, 10000, 51, 1120000, 20000, 21 },
{ "dcdcd", 0x10, (1 << 3), (1 << 3), (0 << 3),
0x15, 0x3f, 600000, 20000, 1600000, 100000 },
0x15, 0x3f, 600000, 20000, 46, 1600000, 100000, 18 },
{ "dcdce", 0x10, (1 << 4), (1 << 4), (0 << 4),
0x16, 0x1f, 1100000, 100000 },
0x16, 0x1f, 1100000, 100000, 24 },
{ "aldo1", 0x10, (1 << 5), (1 << 5), (0 << 5),
0x17, 0x1f, 700000, 100000 },
0x17, 0x1f, 700000, 100000, 27 },
{ "aldo2", 0x10, (1 << 6), (1 << 6), (0 << 6),
0x18, 0x1f, 700000, 100000 },
0x18, 0x1f, 700000, 100000, 27 },
{ "aldo3", 0x10, (1 << 7), (1 << 7), (0 << 7),
0x19, 0x1f, 700000, 100000 },
0x19, 0x1f, 700000, 100000, 27 },
{ "bldo1", 0x11, (1 << 0), (1 << 0), (0 << 0),
0x20, 0x0f, 700000, 100000 },
0x20, 0x0f, 700000, 100000, 13 },
{ "bldo2", 0x11, (1 << 1), (1 << 1), (0 << 1),
0x21, 0x0f, 700000, 100000 },
0x21, 0x0f, 700000, 100000, 13 },
{ "bldo3", 0x11, (1 << 2), (1 << 2), (0 << 2),
0x22, 0x0f, 700000, 100000 },
0x22, 0x0f, 700000, 100000, 13 },
{ "bldo4", 0x11, (1 << 3), (1 << 3), (0 << 3),
0x23, 0x0f, 700000, 100000 },
0x23, 0x0f, 700000, 100000, 13 },
{ "cldo1", 0x11, (1 << 4), (1 << 4), (0 << 4),
0x24, 0x1f, 700000, 100000 },
0x24, 0x1f, 700000, 100000 , 27},
{ "cldo2", 0x11, (1 << 5), (1 << 5), (0 << 5),
0x25, 0x1f, 700000, 100000, 3600000, 200000 },
0x25, 0x1f, 700000, 100000, 28, 3600000, 200000, 4 },
{ "cldo3", 0x11, (1 << 6), (1 << 6), (0 << 6),
0x26, 0x1f, 700000, 100000 },
0x26, 0x1f, 700000, 100000, 27 },
{ "sw", 0x11, (1 << 7), (1 << 7), (0 << 7) },
{ NULL }
};
const struct axppmic_regdata axp809_regdata[] = {
{ "dcdc1", 0x10, (1 << 1), (1 << 1), (0 << 1),
0x21, 0x1f, 1600000, 100000 },
0x21, 0x1f, 1600000, 100000, 19 },
{ "dcdc2", 0x10, (1 << 2), (1 << 2), (0 << 2),
0x22, 0x3f, 600000, 20000 },
0x22, 0x3f, 600000, 20000, 48 },
{ "dcdc3", 0x10, (1 << 3), (1 << 3), (0 << 3),
0x23, 0x3f, 600000, 20000 },
0x23, 0x3f, 600000, 20000, 64 },
{ "dcdc4", 0x10, (1 << 4), (1 << 4), (0 << 4),
0x24, 0x3f, 600000, 20000, 1800000, 100000 },
0x24, 0x3f, 600000, 20000, 48, 1800000, 100000, 9 },
{ "dcdc5", 0x10, (1 << 5), (1 << 5), (0 << 5),
0x25, 0x1f, 1000000, 50000 },
0x25, 0x1f, 1000000, 50000, 32 },
{ "dc5ldo", 0x10, (1 << 0), (1 << 0), (0 << 0),
0x1c, 0x07, 700000, 100000 },
0x1c, 0x07, 700000, 100000, 8 },
{ "aldo1", 0x10, (1 << 6), (1 << 6), (0 << 6),
0x28, 0x1f, 700000, 100000 },
0x28, 0x1f, 700000, 100000, 27 },
{ "aldo2", 0x10, (1 << 7), (1 << 7), (0 << 7),
0x29, 0x1f, 700000, 100000 },
0x29, 0x1f, 700000, 100000, 27 },
{ "aldo3", 0x12, (1 << 5), (1 << 5), (0 << 5),
0x2a, 0x1f, 700000, 100000 },
0x2a, 0x1f, 700000, 100000, 27 },
{ "dldo1", 0x12, (1 << 3), (1 << 3), (0 << 3),
0x15, 0x1f, 700000, 100000 },
0x15, 0x1f, 700000, 100000, 27, 3400000, 200000, 5 },
{ "dldo2", 0x12, (1 << 4), (1 << 4), (0 << 4),
0x16, 0x1f, 700000, 100000 },
0x16, 0x1f, 700000, 100000, 27 },
{ "eldo1", 0x12, (1 << 0), (1 << 0), (0 << 0),
0x19, 0x1f, 700000, 100000 },
0x19, 0x1f, 700000, 100000, 27 },
{ "eldo2", 0x12, (1 << 1), (1 << 1), (0 << 1),
0x1a, 0x1f, 700000, 100000 },
0x1a, 0x1f, 700000, 100000, 27 },
{ "eldo3", 0x12, (1 << 2), (1 << 2), (0 << 2),
0x1b, 0x1f, 700000, 100000 },
0x1b, 0x1f, 700000, 100000, 27 },
{ "ldo_io0", 0x90, 0x07, 0x03, 0x04,
0x91, 0x1f, 700000, 100000 },
0x91, 0x1f, 700000, 100000, 27 },
{ "ldo_io1", 0x92, 0x07, 0x03, 0x04,
0x93, 0x1f, 700000, 100000 },
0x93, 0x1f, 700000, 100000, 27 },
{ NULL }
};
@ -306,6 +306,7 @@ const struct axppmic_device axppmic_devices[] = {
{ "x-powers,axp209", "AXP209", axp209_regdata, axp209_sensdata },
{ "x-powers,axp221", "AXP221", axp221_regdata, axp221_sensdata },
{ "x-powers,axp223", "AXP223", axp221_regdata, axp221_sensdata },
{ "x-powers,axp305", "AXP305", axp806_regdata },
{ "x-powers,axp803", "AXP803", axp803_regdata, axp803_sensdata },
{ "x-powers,axp805", "AXP805", axp806_regdata },
{ "x-powers,axp806", "AXP806", axp806_regdata },
@ -511,7 +512,8 @@ axppmic_attach_common(struct axppmic_softc *sc, const char *name, int node)
sc->sc_sensdata = device->sensdata;
/* Switch AXP806 into master or slave mode. */
if (strcmp(name, "x-powers,axp805") == 0 ||
if (strcmp(name, "x-powers,axp305") == 0 ||
strcmp(name, "x-powers,axp805") == 0 ||
strcmp(name, "x-powers,axp806") == 0) {
if (OF_getproplen(node, "x-powers,master-mode") == 0 ||
OF_getproplen(node, "x-powers,self-working-mode") == 0) {
@ -626,8 +628,8 @@ struct axppmic_regulator {
uint8_t ar_eval, ar_dval;
uint8_t ar_vreg, ar_vmask;
uint32_t ar_base, ar_delta;
uint32_t ar_base2, ar_delta2;
uint32_t ar_base, ar_delta, ar_nsteps;
uint32_t ar_base2, ar_delta2, ar_nsteps2;
struct regulator_device ar_rd;
};
@ -676,6 +678,10 @@ axppmic_attach_regulator(struct axppmic_softc *sc, int node)
ar->ar_vmask = sc->sc_regdata[i].vmask;
ar->ar_base = sc->sc_regdata[i].base;
ar->ar_delta = sc->sc_regdata[i].delta;
ar->ar_nsteps = sc->sc_regdata[i].nsteps;
ar->ar_base2 = sc->sc_regdata[i].base2;
ar->ar_delta2 = sc->sc_regdata[i].delta2;
ar->ar_nsteps2 = sc->sc_regdata[i].nsteps2;
ar->ar_rd.rd_node = node;
ar->ar_rd.rd_cookie = ar;
@ -694,10 +700,11 @@ axppmic_get_voltage(void *cookie)
value = axppmic_read_reg(ar->ar_sc, ar->ar_vreg);
value &= ar->ar_vmask;
voltage = ar->ar_base + value * ar->ar_delta;
if (ar->ar_base2 > 0 && voltage > ar->ar_base2) {
value -= (ar->ar_base2 - ar->ar_base) / ar->ar_delta;
voltage = ar->ar_base2 + value * ar->ar_delta2;
if (ar->ar_base2 > 0 && value >= ar->ar_nsteps) {
voltage =
ar->ar_base2 + (value - ar->ar_nsteps) * ar->ar_delta2;
} else {
voltage = ar->ar_base + value * ar->ar_delta;
}
return voltage;
}
@ -710,17 +717,22 @@ axppmic_set_voltage(void *cookie, uint32_t voltage)
if (voltage < ar->ar_base)
return EINVAL;
value = (voltage - ar->ar_base) / ar->ar_delta;
if (ar->ar_base2 > 0 && voltage > ar->ar_base2) {
value = (ar->ar_base2 - ar->ar_base) / ar->ar_delta;
value += (voltage - ar->ar_base2) / ar->ar_delta2;
if (ar->ar_base2 > 0 && voltage >= ar->ar_base2) {
value = (voltage - ar->ar_base2) / ar->ar_delta2;
if (value >= ar->ar_nsteps2)
return EINVAL;
value += ar->ar_nsteps;
} else {
value = (voltage - ar->ar_base) / ar->ar_delta;
if (value >= ar->ar_nsteps)
return EINVAL;
}
if (value > ar->ar_vmask)
return EINVAL;
reg = axppmic_read_reg(ar->ar_sc, ar->ar_vreg);
reg &= ~ar->ar_vmask;
axppmic_write_reg(ar->ar_sc, ar->ar_vreg, reg | value);
axppmic_write_reg(ar->ar_sc, ar->ar_vreg,
(reg & ~ar->ar_vmask) | (value & ar->ar_vmask));
return 0;
}

2
sys/dev/fdt/if_dwge.c
View file

@ -475,7 +475,7 @@ dwge_attach(struct device *parent, struct device *self, void *aux)
sc->sc_fixed_media = IFM_ETHER | IFM_AUTO;
break;
}
if (OF_getpropbool(node, "full-duplex")) {
ifp->if_link_state = LINK_STATE_FULL_DUPLEX;
sc->sc_fixed_media |= IFM_FDX;

3
sys/dev/fdt/if_dwqe_fdt.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: if_dwqe_fdt.c,v 1.13 2023/07/04 12:58:42 kettenis Exp $ */
/* $OpenBSD: if_dwqe_fdt.c,v 1.14 2023/07/08 08:18:30 kettenis Exp $ */
/*
* Copyright (c) 2008, 2019 Mark Kettenis <kettenis@openbsd.org>
* Copyright (c) 2017, 2022 Patrick Wildt <patrick@blueri.se>
@ -141,6 +141,7 @@ dwqe_fdt_attach(struct device *parent, struct device *self, void *aux)
sc->sc_phyloc = OF_getpropint(node, "reg", MII_PHY_ANY);
else
sc->sc_phyloc = MII_PHY_ANY;
sc->sc_mii.mii_node = node;
pinctrl_byname(faa->fa_node, "default");

2
sys/dev/fdt/qccpu.c
View file

@ -279,7 +279,7 @@ qccpu_refresh_sensor(void *arg)
for (idx = 0; idx < NUM_GROUP; idx++) {
ioh = sc->sc_ioh[idx];
lval = (bus_space_read_4(iot, ioh, CPUF_DOMAIN_STATE)
>> CPUF_DOMAIN_STATE_LVAL_S) & CPUF_DOMAIN_STATE_LVAL_M;
sc->sc_hz_sensor[idx].value = 1000000ULL * lval * XO_FREQ_HZ;

143
sys/dev/fdt/rkclock.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: rkclock.c,v 1.77 2023/06/19 09:54:15 kettenis Exp $ */
/* $OpenBSD: rkclock.c,v 1.82 2023/07/09 16:33:49 patrick Exp $ */
/*
* Copyright (c) 2017, 2018 Mark Kettenis <kettenis@openbsd.org>
*
@ -3839,6 +3839,46 @@ const struct rkclock rk3588_clocks[] = {
SEL(5, 5), DIV(4, 0),
{ RK3588_PLL_GPLL, RK3588_PLL_CPLL }
},
{
RK3588_CLK_I2C1, RK3588_CRU_CLKSEL_CON(38),
SEL(6, 6), 0,
{ RK3588_CLK_200M_SRC , RK3588_CLK_100M_SRC },
},
{
RK3588_CLK_I2C2, RK3588_CRU_CLKSEL_CON(38),
SEL(7, 7), 0,
{ RK3588_CLK_200M_SRC , RK3588_CLK_100M_SRC },
},
{
RK3588_CLK_I2C3, RK3588_CRU_CLKSEL_CON(38),
SEL(8, 8), 0,
{ RK3588_CLK_200M_SRC , RK3588_CLK_100M_SRC },
},
{
RK3588_CLK_I2C4, RK3588_CRU_CLKSEL_CON(38),
SEL(9, 9), 0,
{ RK3588_CLK_200M_SRC , RK3588_CLK_100M_SRC },
},
{
RK3588_CLK_I2C5, RK3588_CRU_CLKSEL_CON(38),
SEL(10, 10), 0,
{ RK3588_CLK_200M_SRC , RK3588_CLK_100M_SRC },
},
{
RK3588_CLK_I2C6, RK3588_CRU_CLKSEL_CON(38),
SEL(11, 11), 0,
{ RK3588_CLK_200M_SRC , RK3588_CLK_100M_SRC },
},
{
RK3588_CLK_I2C7, RK3588_CRU_CLKSEL_CON(38),
SEL(12, 12), 0,
{ RK3588_CLK_200M_SRC , RK3588_CLK_100M_SRC },
},
{
RK3588_CLK_I2C8, RK3588_CRU_CLKSEL_CON(38),
SEL(13, 13), 0,
{ RK3588_CLK_200M_SRC , RK3588_CLK_100M_SRC },
},
{
RK3588_CLK_UART1_SRC, RK3588_CRU_CLKSEL_CON(41),
SEL(14, 14), DIV(13, 9),
@ -4066,6 +4106,11 @@ const struct rkclock rk3588_clocks[] = {
{ RK3588_ACLK_VOP_ROOT, 0 /* RK3588_ACLK_VOP_DIV2_SRC */ },
SET_PARENT
},
{
RK3588_CLK_I2C0, RK3588_CRU_CLKSEL_CON(3),
SEL(6, 6), 0,
{ RK3588_CLK_PMU1_200M_SRC, RK3588_CLK_PMU1_100M_SRC },
},
{
RK3588_CLK_PMU1_50M_SRC, RK3588_PMUCRU_CLKSEL_CON(0),
0, DIV(3, 0),
@ -4103,6 +4148,12 @@ const struct rkclock rk3588_clocks[] = {
{ RK3588_CLK_PMU1_400M_SRC, RK3588_CLK_PMU1_200M_SRC,
RK3588_CLK_PMU1_100M_SRC, RK3588_XIN24M }
},
{
RK3588_CLK_PMU1PWM, RK3588_PMUCRU_CLKSEL_CON(2),
SEL(10, 9), 0,
{ RK3588_CLK_PMU1_100M_SRC, RK3588_CLK_PMU1_50M_SRC,
RK3588_XIN24M }
},
{
RK3588_CLK_UART0_SRC, RK3588_PMUCRU_CLKSEL_CON(3),
0, DIV(11, 7),
@ -4121,17 +4172,47 @@ const struct rkclock rk3588_clocks[] = {
RK3588_CLK_REF_PIPE_PHY0_OSC_SRC, 0, 0, 0,
{ RK3588_XIN24M }
},
{
RK3588_CLK_REF_PIPE_PHY1_OSC_SRC, 0, 0, 0,
{ RK3588_XIN24M }
},
{
RK3588_CLK_REF_PIPE_PHY2_OSC_SRC, 0, 0, 0,
{ RK3588_XIN24M }
},
{
RK3588_CLK_REF_PIPE_PHY0_PLL_SRC, RK3588_CRU_CLKSEL_CON(176),
0, DIV(5, 0),
{ RK3588_PLL_PPLL }
},
{
RK3588_CLK_REF_PIPE_PHY1_PLL_SRC, RK3588_CRU_CLKSEL_CON(176),
0, DIV(11, 6),
{ RK3588_PLL_PPLL }
},
{
RK3588_CLK_REF_PIPE_PHY2_PLL_SRC, RK3588_CRU_CLKSEL_CON(177),
0, DIV(5, 0),
{ RK3588_PLL_PPLL }
},
{
RK3588_CLK_REF_PIPE_PHY0, RK3588_CRU_CLKSEL_CON(177),
SEL(6, 6), 0,
{ RK3588_CLK_REF_PIPE_PHY0_OSC_SRC,
RK3588_CLK_REF_PIPE_PHY0_PLL_SRC },
},
{
RK3588_CLK_REF_PIPE_PHY1, RK3588_CRU_CLKSEL_CON(177),
SEL(7, 7), 0,
{ RK3588_CLK_REF_PIPE_PHY1_OSC_SRC,
RK3588_CLK_REF_PIPE_PHY1_PLL_SRC },
},
{
RK3588_CLK_REF_PIPE_PHY2, RK3588_CRU_CLKSEL_CON(177),
SEL(8, 8), 0,
{ RK3588_CLK_REF_PIPE_PHY2_OSC_SRC,
RK3588_CLK_REF_PIPE_PHY2_PLL_SRC },
},
{
/* Sentinel */
}
@ -4337,22 +4418,82 @@ rk3588_reset(void *cookie, uint32_t *cells, int on)
uint32_t bit, mask, reg;
switch (idx) {
case RK3588_SRST_PCIE0_POWER_UP:
reg = RK3588_CRU_SOFTRST_CON(32);
bit = 13;
break;
case RK3588_SRST_PCIE1_POWER_UP:
reg = RK3588_CRU_SOFTRST_CON(32);
bit = 14;
break;
case RK3588_SRST_PCIE2_POWER_UP:
reg = RK3588_CRU_SOFTRST_CON(32);
bit = 15;
break;
case RK3588_SRST_PCIE3_POWER_UP:
reg = RK3588_CRU_SOFTRST_CON(33);
bit = 0;
break;
case RK3588_SRST_PCIE4_POWER_UP:
reg = RK3588_CRU_SOFTRST_CON(33);
bit = 1;
break;
case RK3588_SRST_P_PCIE0:
reg = RK3588_CRU_SOFTRST_CON(33);
bit = 12;
break;
case RK3588_SRST_P_PCIE1:
reg = RK3588_CRU_SOFTRST_CON(33);
bit = 13;
break;
case RK3588_SRST_P_PCIE2:
reg = RK3588_CRU_SOFTRST_CON(33);
bit = 14;
break;
case RK3588_SRST_P_PCIE3:
reg = RK3588_CRU_SOFTRST_CON(33);
bit = 15;
break;
case RK3588_SRST_P_PCIE4:
reg = RK3588_CRU_SOFTRST_CON(34);
bit = 0;
break;
case RK3588_SRST_A_USB3OTG0:
reg = RK3588_CRU_SOFTRST_CON(42);
bit = 4;
break;
case RK3588_SRST_A_USB3OTG1:
reg = RK3588_CRU_SOFTRST_CON(42);
bit = 7;
break;
case RK3588_SRST_REF_PIPE_PHY0:
reg = RK3588_CRU_SOFTRST_CON(77);
bit = 6;
break;
case RK3588_SRST_REF_PIPE_PHY1:
reg = RK3588_CRU_SOFTRST_CON(77);
bit = 7;
break;
case RK3588_SRST_REF_PIPE_PHY2:
reg = RK3588_CRU_SOFTRST_CON(77);
bit = 8;
break;
case RK3588_SRST_P_PCIE2_PHY0:
reg = RK3588_PHPTOPCRU_SOFTRST_CON(0);
bit = 5;
break;
case RK3588_SRST_P_PCIE2_PHY1:
reg = RK3588_PHPTOPCRU_SOFTRST_CON(0);
bit = 6;
break;
case RK3588_SRST_P_PCIE2_PHY2:
reg = RK3588_PHPTOPCRU_SOFTRST_CON(0);
bit = 7;
break;
case RK3588_SRST_PCIE30_PHY:
reg = RK3588_PHPTOPCRU_SOFTRST_CON(0);
bit = 10;
break;
default:
printf("%s: 0x%08x\n", __func__, idx);
return;

31
sys/dev/fdt/rkclock_clocks.h
View file

@ -394,6 +394,14 @@
#define RK3588_PLL_PPLL 8
#define RK3588_ACLK_BUS_ROOT 113
#define RK3588_CLK_I2C1 131
#define RK3588_CLK_I2C2 132
#define RK3588_CLK_I2C3 133
#define RK3588_CLK_I2C4 134
#define RK3588_CLK_I2C5 135
#define RK3588_CLK_I2C6 136
#define RK3588_CLK_I2C7 137
#define RK3588_CLK_I2C8 138
#define RK3588_CLK_UART1_SRC 168
#define RK3588_CLK_UART1_FRAC 169
#define RK3588_CLK_UART1 170
@ -449,6 +457,7 @@
#define RK3588_ACLK_VOP_ROOT 600
#define RK3588_ACLK_VOP 605
#define RK3588_ACLK_VOP_SUB_SRC 619
#define RK3588_CLK_I2C0 628
#define RK3588_CLK_PMU1_50M_SRC 639
#define RK3588_CLK_PMU1_100M_SRC 640
#define RK3588_CLK_PMU1_200M_SRC 641
@ -456,18 +465,40 @@
#define RK3588_PCLK_PMU1_ROOT 645
#define RK3588_PCLK_PMU0_ROOT 646
#define RK3588_HCLK_PMU_CM0_ROOT 647
#define RK3588_CLK_PMU1PWM 658
#define RK3588_CLK_UART0_SRC 664
#define RK3588_CLK_UART0_FRAC 665
#define RK3588_CLK_UART0 666
#define RK3588_SCLK_UART0 667
#define RK3588_CLK_REF_PIPE_PHY0_OSC_SRC 674
#define RK3588_CLK_REF_PIPE_PHY1_OSC_SRC 675
#define RK3588_CLK_REF_PIPE_PHY2_OSC_SRC 676
#define RK3588_CLK_REF_PIPE_PHY0_PLL_SRC 677
#define RK3588_CLK_REF_PIPE_PHY1_PLL_SRC 678
#define RK3588_CLK_REF_PIPE_PHY2_PLL_SRC 679
#define RK3588_CLK_REF_PIPE_PHY0 680
#define RK3588_CLK_REF_PIPE_PHY1 681
#define RK3588_CLK_REF_PIPE_PHY2 682
#define RK3588_PLL_SPLL 1022
#define RK3588_XIN24M 1023
#define RK3588_SRST_PCIE0_POWER_UP 294
#define RK3588_SRST_PCIE1_POWER_UP 295
#define RK3588_SRST_PCIE2_POWER_UP 296
#define RK3588_SRST_PCIE3_POWER_UP 297
#define RK3588_SRST_PCIE4_POWER_UP 298
#define RK3588_SRST_P_PCIE0 299
#define RK3588_SRST_P_PCIE1 300
#define RK3588_SRST_P_PCIE2 301
#define RK3588_SRST_P_PCIE3 302
#define RK3588_SRST_P_PCIE4 303
#define RK3588_SRST_A_USB3OTG0 338
#define RK3588_SRST_A_USB3OTG1 339
#define RK3588_SRST_REF_PIPE_PHY0 572
#define RK3588_SRST_REF_PIPE_PHY1 573
#define RK3588_SRST_REF_PIPE_PHY2 574
#define RK3588_SRST_P_PCIE2_PHY0 579
#define RK3588_SRST_P_PCIE2_PHY1 580
#define RK3588_SRST_P_PCIE2_PHY2 581
#define RK3588_SRST_PCIE30_PHY 584

115
sys/dev/fdt/rkpciephy.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: rkpciephy.c,v 1.1 2023/03/19 11:17:16 kettenis Exp $ */
/* $OpenBSD: rkpciephy.c,v 1.2 2023/07/08 09:12:28 patrick Exp $ */
/*
* Copyright (c) 2023 Mark Kettenis <kettenis@openbsd.org>
*
@ -28,7 +28,7 @@
#include <dev/ofw/ofw_misc.h>
#include <dev/ofw/fdt.h>
/* GRF registers */
/* RK3568 GRF registers */
#define GRF_PCIE30PHY_CON(idx) ((idx) * 4)
/* CON1 */
#define GRF_PCIE30PHY_DA_OCM 0x80008000
@ -42,6 +42,22 @@
#define GRF_PCIE30PHY_STATUS0 0x80
#define GRF_PCIE30PHY_SRAM_INIT_DONE (1 << 14)
/* RK3588 GRF registers */
#define RK3588_PCIE3PHY_GRF_CMN_CON(idx) ((idx) * 4)
#define RK3588_GRF_PCIE3PHY_DA_OCM ((0x1 << 24) | (1 << 8))
#define RK3588_GRF_PCIE3PHY_LANE_BIFURCATE_0_1 (1 << 0)
#define RK3588_GRF_PCIE3PHY_LANE_BIFURCATE_2_3 (1 << 1)
#define RK3588_GRF_PCIE3PHY_LANE_AGGREGATE (1 << 2)
#define RK3588_GRF_PCIE3PHY_LANE_MASK (0x7 << 16)
#define RK3588_PCIE3PHY_GRF_PHY0_STATUS1 0x904
#define RK3588_PCIE3PHY_GRF_PHY1_STATUS1 0xa04
#define RK3588_PCIE3PHY_SRAM_INIT_DONE (1 << 0)
#define RK3588_PHP_GRF_PCIESEL_CON 0x100
#define RK3588_PHP_GRF_PCIE0L0_PCIE3 (1 << 0)
#define RK3588_PHP_GRF_PCIE0L1_PCIE3 (1 << 1)
#define RK3588_PHP_GRF_PCIE0L0_MASK (0x1 << 16)
#define RK3588_PHP_GRF_PCIE0L1_MASK (0x1 << 17)
struct rkpciephy_softc {
struct device sc_dev;
bus_space_tag_t sc_iot;
@ -61,14 +77,16 @@ struct cfdriver rkpciephy_cd = {
NULL, "rkpciephy", DV_DULL
};
int rkpciephy_enable(void *, uint32_t *);
int rk3568_pciephy_enable(void *, uint32_t *);
int rk3588_pciephy_enable(void *, uint32_t *);
int
rkpciephy_match(struct device *parent, void *match, void *aux)
{
struct fdt_attach_args *faa = aux;
return OF_is_compatible(faa->fa_node, "rockchip,rk3568-pcie3-phy");
return (OF_is_compatible(faa->fa_node, "rockchip,rk3568-pcie3-phy") ||
OF_is_compatible(faa->fa_node, "rockchip,rk3588-pcie3-phy"));
}
void
@ -81,12 +99,15 @@ rkpciephy_attach(struct device *parent, struct device *self, void *aux)
sc->sc_pd.pd_node = faa->fa_node;
sc->sc_pd.pd_cookie = sc;
sc->sc_pd.pd_enable = rkpciephy_enable;
if (OF_is_compatible(faa->fa_node, "rockchip,rk3568-pcie3-phy"))
sc->sc_pd.pd_enable = rk3568_pciephy_enable;
if (OF_is_compatible(faa->fa_node, "rockchip,rk3588-pcie3-phy"))
sc->sc_pd.pd_enable = rk3588_pciephy_enable;
phy_register(&sc->sc_pd);
}
int
rkpciephy_enable(void *cookie, uint32_t *cells)
rk3568_pciephy_enable(void *cookie, uint32_t *cells)
{
struct rkpciephy_softc *sc = cookie;
struct regmap *rm;
@ -135,3 +156,85 @@ rkpciephy_enable(void *cookie, uint32_t *cells)
return 0;
}
int
rk3588_pciephy_enable(void *cookie, uint32_t *cells)
{
struct rkpciephy_softc *sc = cookie;
struct regmap *phy, *pipe;
int node = sc->sc_pd.pd_node;
uint32_t data_lanes[4] = { 1, 1, 1, 1 };
uint32_t grf, reg, stat;
int num_lanes, timo;
grf = OF_getpropint(node, "rockchip,phy-grf", 0);
phy = regmap_byphandle(grf);
if (phy == NULL)
return ENXIO;
clock_enable_all(node);
reset_assert(node, "phy");
delay(1);
regmap_write_4(phy, RK3588_PCIE3PHY_GRF_CMN_CON(0),
RK3588_GRF_PCIE3PHY_DA_OCM);
num_lanes = OF_getpropintarray(node, "data-lanes", data_lanes,
sizeof(data_lanes));
/* Use default setting in case of missing properties. */
if (num_lanes <= 0)
num_lanes = sizeof(data_lanes);
num_lanes /= sizeof(uint32_t);
reg = RK3588_GRF_PCIE3PHY_LANE_MASK;
/* If all links go to the first, aggregate toward x4 */
if (num_lanes >= 4 &&
data_lanes[0] == 1 && data_lanes[1] == 1 &&
data_lanes[2] == 1 && data_lanes[3] == 1) {
reg |= RK3588_GRF_PCIE3PHY_LANE_AGGREGATE;
} else {
/* If lanes 0+1 are not towards the same controller, split. */
if (num_lanes >= 2 && data_lanes[0] != data_lanes[1])
reg |= RK3588_GRF_PCIE3PHY_LANE_BIFURCATE_0_1;
/* If lanes 2+3 are not towards the same controller, split. */
if (num_lanes >= 4 && data_lanes[2] != data_lanes[3])
reg |= RK3588_GRF_PCIE3PHY_LANE_BIFURCATE_2_3;
}
regmap_write_4(phy, RK3588_PCIE3PHY_GRF_CMN_CON(0), reg);
grf = OF_getpropint(node, "rockchip,phy-grf", 0);
pipe = regmap_byphandle(grf);
if (pipe != NULL) {
reg = RK3588_PHP_GRF_PCIE0L0_MASK | RK3588_PHP_GRF_PCIE0L1_MASK;
/* If lane 1 is configured, move it from Combo to PCIE3 PHY */
if (num_lanes >= 2 && data_lanes[1] != 0) {
reg |= RK3588_PHP_GRF_PCIE0L0_PCIE3;
}
/* If lane 3 is configured, move it from Combo to PCIE3 PHY */
if (num_lanes >= 4 && data_lanes[3] != 0) {
reg |= RK3588_PHP_GRF_PCIE0L1_PCIE3;
}
regmap_write_4(pipe, RK3588_PHP_GRF_PCIESEL_CON, reg);
}
reset_deassert(node, "phy");
for (timo = 500; timo > 0; timo--) {
stat = regmap_read_4(phy, RK3588_PCIE3PHY_GRF_PHY0_STATUS1);
if (stat & RK3588_PCIE3PHY_SRAM_INIT_DONE)
break;
delay(100);
}
for (; timo > 0; timo--) {
stat = regmap_read_4(phy, RK3588_PCIE3PHY_GRF_PHY1_STATUS1);
if (stat & RK3588_PCIE3PHY_SRAM_INIT_DONE)
break;
delay(100);
}
if (timo == 0) {
printf("%s: timeout\n", sc->sc_dev.dv_xname);
return ETIMEDOUT;
}
return 0;
}

46
sys/dev/fdt/sncodec.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: sncodec.c,v 1.2 2023/02/04 18:58:19 kettenis Exp $ */
/* $OpenBSD: sncodec.c,v 1.3 2023/07/09 12:32:22 kettenis Exp $ */
/*
* Copyright (c) 2023 Mark Kettenis <kettenis@openbsd.org>
*
@ -36,6 +36,7 @@
#define MODE_CTRL_BOP_SRC (1 << 7)
#define MODE_CTRL_ISNS_PD (1 << 4)
#define MODE_CTRL_VSNS_PD (1 << 3)
#define MODE_CTRL_MODE_MASK (7 << 0)
#define MODE_CTRL_MODE_ACTIVE (0 << 0)
#define MODE_CTRL_MODE_MUTE (1 << 0)
#define MODE_CTRL_MODE_SHUTDOWN (2 << 0)
@ -67,7 +68,6 @@ uint8_t sncodec_bop_cfg[] = {
0x06, 0x3e, 0x37, 0x30, 0xff, 0xe6
};
struct sncodec_softc {
struct device sc_dev;
i2c_tag_t sc_tag;
@ -75,6 +75,7 @@ struct sncodec_softc {
struct dai_device sc_dai;
uint8_t sc_dvc;
uint8_t sc_mute;
};
int sncodec_match(struct device *, void *, void *);
@ -148,6 +149,7 @@ sncodec_attach(struct device *parent, struct device *self, void *aux)
/* Set volume to a reasonable level. */
sc->sc_dvc = DVC_LVL_30DB;
sc->sc_mute = MODE_CTRL_MODE_ACTIVE;
sncodec_write(sc, DVC, sc->sc_dvc);
/* Default to stereo downmix mode for now. */
@ -251,13 +253,14 @@ sncodec_set_tdm_slot(void *cookie, int slot)
}
/*
* Mixer controls; the gain of the TAS2770 is determined by the
* Mixer controls; the gain of the TAS2764 is determined by the
* amplifier gain and digital volume control setting, but we only
* expose the digital volume control setting through the mixer
* interface.
*/
enum {
SNCODEC_MASTER_VOL,
SNCODEC_MASTER_MUTE,
SNCODEC_OUTPUT_CLASS
};
@ -266,6 +269,7 @@ sncodec_set_port(void *priv, mixer_ctrl_t *mc)
{
struct sncodec_softc *sc = priv;
u_char level;
uint8_t mode;
switch (mc->dev) {
case SNCODEC_MASTER_VOL:
@ -273,6 +277,18 @@ sncodec_set_port(void *priv, mixer_ctrl_t *mc)
sc->sc_dvc = (DVC_LVL_MIN * (255 - level)) / 255;
sncodec_write(sc, DVC, sc->sc_dvc);
return 0;
case SNCODEC_MASTER_MUTE:
sc->sc_mute = mc->un.ord ?
MODE_CTRL_MODE_MUTE : MODE_CTRL_MODE_ACTIVE;
mode = sncodec_read(sc, MODE_CTRL);
if ((mode & MODE_CTRL_MODE_MASK) == MODE_CTRL_MODE_ACTIVE ||
(mode & MODE_CTRL_MODE_MASK) == MODE_CTRL_MODE_MUTE) {
mode &= ~MODE_CTRL_MODE_MASK;
mode |= sc->sc_mute;
sncodec_write(sc, MODE_CTRL, mode);
}
return 0;
}
return EINVAL;
@ -290,6 +306,10 @@ sncodec_get_port(void *priv, mixer_ctrl_t *mc)
level = 255 - ((255 * sc->sc_dvc) / DVC_LVL_MIN);
mc->un.value.level[AUDIO_MIXER_LEVEL_MONO] = level;
return 0;
case SNCODEC_MASTER_MUTE:
mc->un.ord = (sc->sc_mute == MODE_CTRL_MODE_MUTE);
return 0;
}
return EINVAL;
@ -301,7 +321,8 @@ sncodec_query_devinfo(void *priv, mixer_devinfo_t *di)
switch (di->index) {
case SNCODEC_MASTER_VOL:
di->mixer_class = SNCODEC_OUTPUT_CLASS;
di->next = di->prev = AUDIO_MIXER_LAST;
di->prev = AUDIO_MIXER_LAST;
di->next = SNCODEC_MASTER_MUTE;
strlcpy(di->label.name, AudioNmaster, sizeof(di->label.name));
di->type = AUDIO_MIXER_VALUE;
di->un.v.num_channels = 1;
@ -309,6 +330,21 @@ sncodec_query_devinfo(void *priv, mixer_devinfo_t *di)
sizeof(di->un.v.units.name));
return 0;
case SNCODEC_MASTER_MUTE:
di->mixer_class = SNCODEC_OUTPUT_CLASS;
di->prev = SNCODEC_MASTER_VOL;
di->next = AUDIO_MIXER_LAST;
strlcpy(di->label.name, AudioNmute, sizeof(di->label.name));
di->type = AUDIO_MIXER_ENUM;
di->un.e.num_mem = 2;
di->un.e.member[0].ord = 0;
strlcpy(di->un.e.member[0].label.name, AudioNoff,
MAX_AUDIO_DEV_LEN);
di->un.e.member[1].ord = 1;
strlcpy(di->un.e.member[1].label.name, AudioNon,
MAX_AUDIO_DEV_LEN);
return 0;
case SNCODEC_OUTPUT_CLASS:
di->mixer_class = SNCODEC_OUTPUT_CLASS;
di->next = di->prev = AUDIO_MIXER_LAST;
@ -327,7 +363,7 @@ sncodec_trigger_output(void *cookie, void *start, void *end, int blksize,
struct sncodec_softc *sc = cookie;
sncodec_write(sc, MODE_CTRL, MODE_CTRL_BOP_SRC |
MODE_CTRL_ISNS_PD | MODE_CTRL_VSNS_PD | MODE_CTRL_MODE_ACTIVE);
MODE_CTRL_ISNS_PD | MODE_CTRL_VSNS_PD | sc->sc_mute);
return 0;
}

2
sys/dev/gpio/gpiodcf.c
View file

@ -349,7 +349,7 @@ gpiodcf_mg_probe(void *xsc)
if (gettime() - sc->sc_last_mg < 57) {
DPRINTF(("\nunexpected gap, resync\n"));
sc->sc_sync = sc->sc_minute = 1;
goto cleanbits;
goto cleanbits;
}
/* extract bits w/o parity */

6
sys/dev/hid/hidkbd.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: hidkbd.c,v 1.8 2022/11/09 10:05:18 robert Exp $ */
/* $OpenBSD: hidkbd.c,v 1.9 2023/07/09 08:02:13 tobhe Exp $ */
/* $NetBSD: ukbd.c,v 1.85 2003/03/11 16:44:00 augustss Exp $ */
/*
@ -144,6 +144,7 @@ static const struct hidkbd_translation apple_fn_trans[] = {
{ 61, 129 }, /* F4 -> audio lower */
{ 62, 128 }, /* F5 -> audio raise */
#else
{ 63, 102 }, /* F6 -> sleep */
{ 67, 127 }, /* F10 -> audio mute */
{ 68, 129 }, /* F11 -> audio lower */
{ 69, 128 }, /* F12 -> audio raise */
@ -557,11 +558,12 @@ hidkbd_decode(struct hidkbd *kbd, struct hidkbd_data *ud)
wskbd_rawinput(kbd->sc_wskbddev, cbuf, j);
/*
* Pass audio and brightness keys to wskbd_input anyway.
* Pass audio, brightness and sleep keys to wskbd_input anyway.
*/
for (i = 0; i < nkeys; i++) {
key = ibuf[i];
switch (key & CODEMASK) {
case 102:
case 127:
case 128:
case 129:

7
sys/dev/i2c/files.i2c
View file

@ -1,4 +1,4 @@
# $OpenBSD: files.i2c,v 1.71 2022/11/11 15:25:13 matthieu Exp $
# $OpenBSD: files.i2c,v 1.72 2023/07/08 02:43:02 jcs Exp $
# $NetBSD: files.i2c,v 1.3 2003/10/20 16:24:10 briggs Exp $
define i2c {[addr = -1], [size = -1]}
@ -230,6 +230,11 @@ device iatp: wsmousedev
attach iatp at i2c
file dev/i2c/iatp.c iatp
# Elantech touchpad
device ietp: wsmousedev
attach ietp at i2c
file dev/i2c/ietp.c ietp
# Bosch BMC150 6-axis eCompass
device bgw
attach bgw at i2c

686
sys/dev/i2c/ietp.c Normal file
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@ -0,0 +1,686 @@
/* $OpenBSD: ietp.c,v 1.1 2023/07/08 02:43:02 jcs Exp $ */
/*
* elan-i2c driver
*
* Copyright (c) 2015, 2016 joshua stein <jcs@openbsd.org>
* Copyright (c) 2020, 2022 Vladimir Kondratyev <wulf@FreeBSD.org>
* Copyright (c) 2023 vladimir serbinenko <phcoder@gmail.com>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/* Protocol documentation: https://lkml.indiana.edu/hypermail/linux/kernel/1205.0/02551.html.
Based on FreeBSD ietp driver.
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/device.h>
#include <sys/malloc.h>
#include <sys/stdint.h>
#include <dev/i2c/i2cvar.h>
#include <dev/i2c/ietp.h>
#include <dev/wscons/wsconsio.h>
#include <dev/wscons/wsmousevar.h>
/* #define IETP_DEBUG */
#ifdef IETP_DEBUG
#define DPRINTF(x) printf x
#else
#define DPRINTF(x)
#endif
enum {
I2C_HID_CMD_DESCR = 0x0,
I2C_HID_CMD_RESET = 0x1,
I2C_HID_CMD_SET_POWER = 0x8,
};
#define I2C_HID_POWER_ON 0x0
#define I2C_HID_POWER_OFF 0x1
#define IETP_PATTERN 0x0100
#define IETP_UNIQUEID 0x0101
#define IETP_IC_TYPE 0x0103
#define IETP_OSM_VERSION 0x0103
#define IETP_NSM_VERSION 0x0104
#define IETP_TRACENUM 0x0105
#define IETP_MAX_X_AXIS 0x0106
#define IETP_MAX_Y_AXIS 0x0107
#define IETP_RESOLUTION 0x0108
#define IETP_PRESSURE 0x010A
#define IETP_CONTROL 0x0300
#define IETP_CTRL_ABSOLUTE 0x0001
#define IETP_CTRL_STANDARD 0x0000
#define IETP_REPORT_LEN_LO 31
#define IETP_REPORT_LEN_HI 36
#define IETP_MAX_FINGERS 5
#define IETP_REPORT_ID_LO 0x5D
#define IETP_REPORT_ID_HI 0x60
#define IETP_TOUCH_INFO 0
#define IETP_FINGER_DATA 1
#define IETP_FINGER_DATA_LEN 5
#define IETP_WH_DATA 31
#define IETP_TOUCH_LMB (1 << 0)
#define IETP_TOUCH_RMB (1 << 1)
#define IETP_TOUCH_MMB (1 << 2)
#define IETP_MAX_PRESSURE 255
#define IETP_FWIDTH_REDUCE 90
#define IETP_PRESSURE_BASE 25
int ietp_match(struct device *, void *, void *);
void ietp_attach(struct device *, struct device *, void *);
int ietp_detach(struct device *, int);
int ietp_activate(struct device *, int);
int ietp_intr(void *);
int ietp_reset(struct ietp_softc *);
int ietp_fetch_descriptor(struct ietp_softc *sc);
int ietp_set_power(struct ietp_softc *sc, int power);
int ietp_reset_cmd(struct ietp_softc *sc);
int32_t ietp_res2dpmm(uint8_t, bool);
int ietp_iic_read_reg(struct ietp_softc *, uint16_t, size_t, void *);
int ietp_iic_write_reg(struct ietp_softc *, uint16_t, uint16_t);
int ietp_iic_set_absolute_mode(struct ietp_softc *, bool);
const struct cfattach ietp_ca = {
sizeof(struct ietp_softc),
ietp_match,
ietp_attach,
ietp_detach,
ietp_activate,
};
const struct wsmouse_accessops ietp_mouse_access = {
ietp_enable,
ietp_ioctl,
ietp_disable
};
struct cfdriver ietp_cd = {
NULL, "ietp", DV_DULL
};
int
ietp_match(struct device *parent, void *match, void *aux)
{
struct i2c_attach_args *ia = aux;
if (strcmp(ia->ia_name, "ietp") == 0)
return (1);
return (0);
}
int32_t
ietp_res2dpmm(uint8_t res, bool hi_precision)
{
int32_t dpi;
dpi = hi_precision ? 300 + res * 100 : 790 + res * 10;
return (dpi * 10 /254);
}
void
ietp_attach(struct device *parent, struct device *self, void *aux)
{
struct ietp_softc *sc = (struct ietp_softc *)self;
struct i2c_attach_args *ia = aux;
uint16_t buf, reg;
uint8_t *buf8;
uint8_t pattern;
struct wsmousedev_attach_args a;
struct wsmousehw *hw;
sc->sc_tag = ia->ia_tag;
sc->sc_addr = ia->ia_addr;
ietp_fetch_descriptor(sc);
if (ia->ia_intr) {
printf(" %s", iic_intr_string(sc->sc_tag, ia->ia_intr));
sc->sc_ih = iic_intr_establish(sc->sc_tag, ia->ia_intr,
IPL_TTY, ietp_intr, sc, sc->sc_dev.dv_xname);
if (sc->sc_ih == NULL) {
printf(", can't establish interrupt");
return;
}
}
sc->sc_buttons = 0;
sc->sc_refcnt = 0;
buf8 = (uint8_t *)&buf;
if (ietp_iic_read_reg(sc, IETP_UNIQUEID, sizeof(buf), &buf) != 0) {
printf("%s: failed reading product ID\n", sc->sc_dev.dv_xname);
return;
}
sc->product_id = le16toh(buf);
if (ietp_iic_read_reg(sc, IETP_PATTERN, sizeof(buf), &buf) != 0) {
printf("%s: failed reading pattern\n", sc->sc_dev.dv_xname);
return;
}
pattern = buf == 0xFFFF ? 0 : buf8[1];
sc->hi_precision = pattern >= 0x02;
reg = pattern >= 0x01 ? IETP_IC_TYPE : IETP_OSM_VERSION;
if (ietp_iic_read_reg(sc, reg, sizeof(buf), &buf) != 0) {
printf("%s: failed reading IC type\n", sc->sc_dev.dv_xname);
return;
}
sc->ic_type = pattern >= 0x01 ? be16toh(buf) : buf8[1];
if (ietp_iic_read_reg(sc, IETP_NSM_VERSION, sizeof(buf), &buf) != 0) {
printf("%s: failed reading SM version\n", sc->sc_dev.dv_xname);
return;
}
sc->is_clickpad = (buf8[0] & 0x10) != 0;
if (ietp_iic_set_absolute_mode(sc, true) != 0) {
printf("%s: failed to set absolute mode\n", sc->sc_dev.dv_xname);
return;
}
if (ietp_iic_read_reg(sc, IETP_MAX_X_AXIS, sizeof(buf), &buf) != 0) {
printf("%s: failed reading max x\n", sc->sc_dev.dv_xname);
return;
}
sc->max_x = le16toh(buf);
if (ietp_iic_read_reg(sc, IETP_MAX_Y_AXIS, sizeof(buf), &buf) != 0) {
printf("%s: failed reading max y\n", sc->sc_dev.dv_xname);
return;
}
sc->max_y = le16toh(buf);
if (ietp_iic_read_reg(sc, IETP_TRACENUM, sizeof(buf), &buf) != 0) {
printf("%s: failed reading trace info\n", sc->sc_dev.dv_xname);
return;
}
sc->trace_x = sc->max_x / buf8[0];
sc->trace_y = sc->max_y / buf8[1];
if (ietp_iic_read_reg(sc, IETP_PRESSURE, sizeof(buf), &buf) != 0) {
printf("%s: failed reading pressure format\n", sc->sc_dev.dv_xname);
return;
}
sc->pressure_base = (buf8[0] & 0x10) ? 0 : IETP_PRESSURE_BASE;
if (ietp_iic_read_reg(sc, IETP_RESOLUTION, sizeof(buf), &buf) != 0) {
printf("%s: failed reading resolution\n", sc->sc_dev.dv_xname);
return;
}
/* Conversion from internal format to dot per mm */
sc->res_x = ietp_res2dpmm(buf8[0], sc->hi_precision);
sc->res_y = ietp_res2dpmm(buf8[1], sc->hi_precision);
sc->report_id = sc->hi_precision ?
IETP_REPORT_ID_HI : IETP_REPORT_ID_LO;
sc->report_len = sc->hi_precision ?
IETP_REPORT_LEN_HI : IETP_REPORT_LEN_LO;
sc->sc_ibuf = malloc(IETP_REPORT_LEN_HI + 12, M_DEVBUF, M_NOWAIT | M_ZERO);
sc->sc_isize = sc->report_len + 3;
a.accessops = &ietp_mouse_access;
a.accesscookie = sc;
sc->sc_wsmousedev = config_found(self, &a, wsmousedevprint);
hw = wsmouse_get_hw(sc->sc_wsmousedev);
hw->type = WSMOUSE_TYPE_TOUCHPAD;
hw->hw_type = sc->is_clickpad ? WSMOUSEHW_CLICKPAD : WSMOUSEHW_TOUCHPAD;
hw->x_min = 0;
hw->x_max = sc->max_x;
hw->y_min = 0;
hw->y_max = sc->max_y;
hw->h_res = sc->res_x;
hw->v_res = sc->res_y;
hw->mt_slots = IETP_MAX_FINGERS;
wsmouse_configure(sc->sc_wsmousedev, NULL, 0);
/* power down until we're opened */
if (ietp_set_power(sc, I2C_HID_POWER_OFF)) {
printf("%s: failed to power down\n", sc->sc_dev.dv_xname);
return;
}
DPRINTF(("%s: max_x=%d, max_y=%d, %s\n", sc->sc_dev.dv_xname,
sc->max_x, sc->max_y,
sc->is_clickpad ? "clickpad" : "touchpad"));
return;
}
int
ietp_detach(struct device *self, int flags)
{
struct ietp_softc *sc = (struct ietp_softc *)self;
if (sc->sc_ih != NULL) {
iic_intr_disestablish(sc->sc_tag, sc->sc_ih);
sc->sc_ih = NULL;
}
if (sc->sc_ibuf != NULL) {
free(sc->sc_ibuf, M_DEVBUF, sc->sc_isize);
sc->sc_ibuf = NULL;
}
return (0);
}
int
ietp_activate(struct device *self, int act)
{
struct ietp_softc *sc = (struct ietp_softc *)self;
DPRINTF(("%s(%d)\n", __func__, act));
switch (act) {
case DVACT_QUIESCE:
sc->sc_dying = 1;
if (ietp_set_power(sc, I2C_HID_POWER_OFF))
printf("%s: failed to power down\n",
sc->sc_dev.dv_xname);
break;
case DVACT_WAKEUP:
ietp_reset(sc);
sc->sc_dying = 0;
break;
}
config_activate_children(self, act);
return 0;
}
void
ietp_sleep(struct ietp_softc *sc, int ms)
{
if (cold)
delay(ms * 1000);
else
tsleep_nsec(&sc, PWAIT, "ietp", MSEC_TO_NSEC(ms));
}
int
ietp_iic_set_absolute_mode(struct ietp_softc *sc, bool enable)
{
static const struct {
uint16_t ic_type;
uint16_t product_id;
} special_fw[] = {
{ 0x0E, 0x05 }, { 0x0E, 0x06 }, { 0x0E, 0x07 }, { 0x0E, 0x09 },
{ 0x0E, 0x13 }, { 0x08, 0x26 },
};
uint16_t val;
int i, error;
bool require_wakeup;
error = 0;
/*
* Some ASUS touchpads need to be powered on to enter absolute mode.
*/
require_wakeup = false;
for (i = 0; i < nitems(special_fw); i++) {
if (sc->ic_type == special_fw[i].ic_type &&
sc->product_id == special_fw[i].product_id) {
require_wakeup = true;
break;
}
}
if (require_wakeup && ietp_set_power(sc, I2C_HID_POWER_ON) != 0) {
printf("%s: failed writing poweron command\n", sc->sc_dev.dv_xname);
return (EIO);
}
val = enable ? IETP_CTRL_ABSOLUTE : IETP_CTRL_STANDARD;
if (ietp_iic_write_reg(sc, IETP_CONTROL, val) != 0) {
printf("%s: failed setting absolute mode\n", sc->sc_dev.dv_xname);
error = EIO;
}
if (require_wakeup && ietp_set_power(sc, I2C_HID_POWER_OFF) != 0) {
printf("%s: failed writing poweroff command\n", sc->sc_dev.dv_xname);
error = EIO;
}
return (error);
}
int
ietp_iic_read_reg(struct ietp_softc *sc, uint16_t reg, size_t len, void *val)
{
uint8_t cmd[] = {
reg & 0xff,
reg >> 8,
};
return iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_addr,
&cmd, 2, val, len, 0);
}
int
ietp_iic_write_reg(struct ietp_softc *sc, uint16_t reg, uint16_t val)
{
uint8_t cmd[] = {
reg & 0xff,
reg >> 8,
val & 0xff,
val >> 8,
};
return iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, sc->sc_addr,
&cmd, 4, NULL, 0, 0);
}
int
ietp_set_power(struct ietp_softc *sc, int power)
{
int res = 1;
uint8_t cmd[] = {
htole16(sc->hid_desc.wCommandRegister) & 0xff,
htole16(sc->hid_desc.wCommandRegister) >> 8,
power,
I2C_HID_CMD_SET_POWER,
};
iic_acquire_bus(sc->sc_tag, 0);
DPRINTF(("%s: HID command I2C_HID_CMD_SET_POWER(%d)\n",
sc->sc_dev.dv_xname, power));
/* 22 00 00 08 */
res = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, sc->sc_addr,
&cmd, sizeof(cmd), NULL, 0, 0);
iic_release_bus(sc->sc_tag, 0);
return (res);
}
int
ietp_reset_cmd(struct ietp_softc *sc)
{
int res = 1;
uint8_t cmd[] = {
htole16(sc->hid_desc.wCommandRegister) & 0xff,
htole16(sc->hid_desc.wCommandRegister) >> 8,
0,
I2C_HID_CMD_RESET,
};
iic_acquire_bus(sc->sc_tag, 0);
DPRINTF(("%s: HID command I2C_HID_CMD_RESET\n",
sc->sc_dev.dv_xname));
/* 22 00 00 01 */
res = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, sc->sc_addr,
&cmd, sizeof(cmd), NULL, 0, 0);
iic_release_bus(sc->sc_tag, 0);
return (res);
}
int
ietp_fetch_descriptor(struct ietp_softc *sc)
{
int i, res = 1;
/*
* 5.2.2 - HID Descriptor Retrieval
* register is passed from the controller
*/
uint8_t cmd[] = {
1,
0,
};
iic_acquire_bus(sc->sc_tag, 0);
DPRINTF(("%s: HID command I2C_HID_CMD_DESCR at 0x1\n",
sc->sc_dev.dv_xname));
/* 20 00 */
res = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_addr,
&cmd, sizeof(cmd), &sc->hid_desc_buf,
sizeof(struct i2c_hid_desc), 0);
DPRINTF(("%s: HID descriptor:", sc->sc_dev.dv_xname));
for (i = 0; i < sizeof(struct i2c_hid_desc); i++)
DPRINTF((" %.2x", sc->hid_desc_buf[i]));
DPRINTF(("\n"));
iic_release_bus(sc->sc_tag, 0);
return (res);
}
int
ietp_reset(struct ietp_softc *sc)
{
DPRINTF(("%s: resetting\n", sc->sc_dev.dv_xname));
if (ietp_set_power(sc, I2C_HID_POWER_ON)) {
printf("%s: failed to power on\n", sc->sc_dev.dv_xname);
return (1);
}
ietp_sleep(sc, 100);
if (ietp_reset_cmd(sc)) {
printf("%s: failed to reset hardware\n", sc->sc_dev.dv_xname);
ietp_set_power(sc, I2C_HID_POWER_OFF);
return (1);
}
ietp_sleep(sc, 100);
return (0);
}
void
parse_input(struct ietp_softc *sc, u_char *report, int len)
{
uint8_t *fdata;
int32_t finger;
int32_t x, y, p;
int buttons = 0;
int s;
/* we seem to get 0 length reports sometimes, ignore them */
if (len == 0)
return;
if (len != sc->report_len) {
printf("%s: wrong report length (%d vs %d expected)", sc->sc_dev.dv_xname, len, (int) sc->report_len);
return;
}
s = spltty();
buttons = report[IETP_TOUCH_INFO] & 7;
if (sc->sc_buttons != buttons) {
wsmouse_buttons(sc->sc_wsmousedev, buttons);
sc->sc_buttons = buttons;
}
for (finger = 0, fdata = report + IETP_FINGER_DATA;
finger < IETP_MAX_FINGERS;
finger++, fdata += IETP_FINGER_DATA_LEN) {
if ((report[IETP_TOUCH_INFO] & (1 << (finger + 3))) != 0) {
if (sc->hi_precision) {
x = fdata[0] << 8 | fdata[1];
y = fdata[2] << 8 | fdata[3];
} else {
x = (fdata[0] & 0xf0) << 4 | fdata[1];
y = (fdata[0] & 0x0f) << 8 | fdata[2];
}
if (x > sc->max_x || y > sc->max_y) {
printf("%s: [%d] x=%d y=%d over max (%d, %d)\n",
sc->sc_dev.dv_xname, finger, x, y, sc->max_x, sc->max_y);
continue;
}
p = MIN((int32_t)fdata[4] + sc->pressure_base,
IETP_MAX_PRESSURE);
} else {
x = 0;
y = 0;
p = 0;
}
DPRINTF(("position: [finger=%d, x=%d, y=%d, p=%d]\n", finger, x, y, p));
wsmouse_mtstate(sc->sc_wsmousedev, finger, x, y, p);
}
wsmouse_input_sync(sc->sc_wsmousedev);
splx(s);
}
int
ietp_intr(void *arg)
{
struct ietp_softc *sc = arg;
int psize, i;
u_char *p;
u_int rep = 0;
if (sc->sc_dying)
return 1;
/*
* XXX: force I2C_F_POLL for now to avoid dwiic interrupting
* while we are interrupting
*/
iic_acquire_bus(sc->sc_tag, I2C_F_POLL);
iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_addr, NULL, 0,
sc->sc_ibuf, letoh16(sc->hid_desc.wMaxInputLength), I2C_F_POLL);
iic_release_bus(sc->sc_tag, I2C_F_POLL);
/*
* 6.1.1 - First two bytes are the packet length, which must be less
* than or equal to wMaxInputLength
*/
psize = sc->sc_ibuf[0] | sc->sc_ibuf[1] << 8;
if (psize <= 2 || psize > sc->sc_isize) {
DPRINTF(("%s: %s: invalid packet size (%d vs. %d)\n",
sc->sc_dev.dv_xname, __func__, psize,
sc->sc_isize));
return (1);
}
/* 3rd byte is the report id */
p = sc->sc_ibuf + 2;
psize -= 2;
rep = *p++;
psize--;
DPRINTF(("%s: %s: hid input (rep 0x%x):", sc->sc_dev.dv_xname, __func__,
rep));
for (i = 0; i < psize; i++) {
DPRINTF((" %.2x", p[i]));
}
DPRINTF(("\n"));
if (sc->sc_refcnt && rep == sc->report_id) {
parse_input(sc, p, psize);
}
return (1);
}
int
ietp_enable(void *dev)
{
struct ietp_softc *sc = dev;
DPRINTF(("%s: %s: refcnt=%d\n", sc->sc_dev.dv_xname,
__func__, sc->sc_refcnt));
if (sc->sc_refcnt++ || sc->sc_isize == 0)
return (0);
/* power on */
ietp_reset(sc);
return (0);
}
void
ietp_disable(void *dev)
{
struct ietp_softc *sc = dev;
DPRINTF(("%s: %s: refcnt=%d\n", sc->sc_dev.dv_xname,
__func__, sc->sc_refcnt));
if (--sc->sc_refcnt)
return;
/* no sub-devices open, conserve power */
if (ietp_set_power(sc, I2C_HID_POWER_OFF))
printf("%s: failed to power down\n", sc->sc_dev.dv_xname);
}
int
ietp_ioctl(void *dev, u_long cmd, caddr_t data, int flag,
struct proc *p)
{
struct ietp_softc *sc = dev;
struct wsmouse_calibcoords *wsmc = (struct wsmouse_calibcoords *)data;
switch (cmd) {
case WSMOUSEIO_GTYPE:
*(u_int *)data = WSMOUSE_TYPE_TOUCHPAD;
return 0;
case WSMOUSEIO_GCALIBCOORDS:
wsmc->minx = 0;
wsmc->maxx = sc->max_x;
wsmc->miny = 0;
wsmc->maxy = sc->max_y;
wsmc->swapxy = 0;
wsmc->resx = sc->res_x;
wsmc->resy = sc->res_y;
return 0;
}
return -1;
}

66
sys/dev/i2c/ietp.h Normal file
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@ -0,0 +1,66 @@
/* $OpenBSD: ietp.h,v 1.1 2023/07/08 02:43:02 jcs Exp $ */
/*
* Elantech touchpad I2C driver
*
* Copyright (c) 2015, 2016 joshua stein <jcs@openbsd.org>
* Copyright (c) 2020, 2022 Vladimir Kondratyev <wulf@FreeBSD.org>
* Copyright (c) 2023 vladimir serbinenko <phcoder@gmail.com>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "ihidev.h" // For i2c_hid_desc
struct ietp_softc {
struct device sc_dev;
i2c_tag_t sc_tag;
i2c_addr_t sc_addr;
void *sc_ih;
union {
uint8_t hid_desc_buf[sizeof(struct i2c_hid_desc)];
struct i2c_hid_desc hid_desc;
};
u_int sc_isize;
u_char *sc_ibuf;
int sc_refcnt;
int sc_dying;
struct device *sc_wsmousedev;
uint8_t sc_buttons;
uint8_t report_id;
size_t report_len;
uint16_t product_id;
uint16_t ic_type;
int32_t pressure_base;
uint16_t max_x;
uint16_t max_y;
uint16_t trace_x;
uint16_t trace_y;
uint16_t res_x; /* dots per mm */
uint16_t res_y;
bool hi_precision;
bool is_clickpad;
};
int ietp_open(struct ietp_softc *);
void ietp_close(struct ietp_softc *);
int ietp_ioctl(void *, u_long, caddr_t, int, struct proc *);
int ietp_enable(void *dev);
void ietp_disable(void *dev);

2
sys/dev/ic/amireg.h
View file

@ -47,7 +47,7 @@
#define AMI_MAXIOCTLCMDS 1 /* number of parallel ioctl calls */
#define AMI_MAXPROCS 2 /* number of processors on a channel */
#define AMI_MAXRAWCMDS 2 /* number of parallel processor cmds */
#define AMI_MAXFER (AMI_MAXOFFSETS * PAGE_SIZE)
#define AMI_QIDB 0x20

30
sys/dev/ic/an.c
View file

@ -205,7 +205,7 @@ an_attach(struct an_softc *sc)
return(EIO);
}
an_swap16((u_int16_t *)&sc->sc_config.an_macaddr, 3);
an_swap16((u_int16_t *)&sc->sc_config.an_macaddr, 3);
/* Read the card capabilities */
buflen = sizeof(sc->sc_caps);
@ -214,7 +214,7 @@ an_attach(struct an_softc *sc)
return(EIO);
}
an_swap16((u_int16_t *)&sc->sc_caps.an_oemaddr, 3);
an_swap16((u_int16_t *)&sc->sc_caps.an_oemaddr, 3);
an_swap16((u_int16_t *)&sc->sc_caps.an_rates, 4);
/* Read WEP settings from persistent memory */
@ -222,8 +222,8 @@ an_attach(struct an_softc *sc)
buflen = sizeof(struct an_rid_wepkey);
rid = AN_RID_WEP_VOLATILE; /* first persistent key */
while (an_read_rid(sc, rid, akey, &buflen) == 0) {
an_swap16((u_int16_t *)&akey->an_mac_addr, 3);
an_swap16((u_int16_t *)&akey->an_key, 8);
an_swap16((u_int16_t *)&akey->an_mac_addr, 3);
an_swap16((u_int16_t *)&akey->an_key, 8);
kid = akey->an_key_index;
DPRINTF(("an_attach: wep rid=0x%x len=%d(%d) index=0x%04x "
"mac[0]=%02x keylen=%d\n",
@ -260,7 +260,7 @@ an_attach(struct an_softc *sc)
printf("unknown (%x)", sc->sc_config.an_radiotype);
printf(", address %s\n", ether_sprintf(ic->ic_myaddr));
ifp->if_softc = sc;
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
ifp->if_ioctl = an_ioctl;
@ -783,14 +783,14 @@ an_mwrite_bap(struct an_softc *sc, int id, int off, struct mbuf *m, int totlen)
if ((mtod(m, u_long) & 0x1) || (len & 0x1)) {
m_copydata(m, 0, totlen, &sc->sc_buf.sc_txbuf);
cnt = (totlen + 1) / 2;
an_swap16((u_int16_t *)&sc->sc_buf.sc_txbuf, cnt);
an_swap16((u_int16_t *)&sc->sc_buf.sc_txbuf, cnt);
CSR_WRITE_MULTI_STREAM_2(sc, AN_DATA0,
sc->sc_buf.sc_val, cnt);
off += cnt * 2;
break;
}
cnt = len / 2;
an_swap16((u_int16_t *)mtod(m, u_int16_t *), cnt);
an_swap16((u_int16_t *)mtod(m, u_int16_t *), cnt);
CSR_WRITE_MULTI_STREAM_2(sc, AN_DATA0, mtod(m, u_int16_t *),
cnt);
off += len;
@ -961,7 +961,7 @@ an_init(struct ifnet *ifp)
sc->sc_txcur = sc->sc_txnext = 0;
IEEE80211_ADDR_COPY(sc->sc_config.an_macaddr, ic->ic_myaddr);
an_swap16((u_int16_t *)&sc->sc_config.an_macaddr, 3);
an_swap16((u_int16_t *)&sc->sc_config.an_macaddr, 3);
sc->sc_config.an_scanmode = AN_SCANMODE_ACTIVE;
sc->sc_config.an_authtype = AN_AUTHTYPE_OPEN; /*XXX*/
if (ic->ic_flags & IEEE80211_F_WEPON) {
@ -1014,7 +1014,7 @@ an_init(struct ifnet *ifp)
if (ic->ic_des_esslen)
memcpy(sc->sc_buf.sc_ssidlist.an_entry[0].an_ssid,
ic->ic_des_essid, ic->ic_des_esslen);
an_swap16((u_int16_t *)&sc->sc_buf.sc_ssidlist.an_entry[0].an_ssid, 16);
an_swap16((u_int16_t *)&sc->sc_buf.sc_ssidlist.an_entry[0].an_ssid, 16);
if ((error = an_write_rid(sc, AN_RID_SSIDLIST, &sc->sc_buf,
sizeof(sc->sc_buf.sc_ssidlist)))) {
printf("%s: failed to write ssid list\n", ifp->if_xname);
@ -1172,7 +1172,7 @@ an_start(struct ifnet *ifp)
struct mbuf mb;
struct an_tx_radiotap_header *tap = &sc->sc_txtap;
tap->at_rate =
tap->at_rate =
ic->ic_bss->ni_rates.rs_rates[ic->ic_bss->ni_txrate];
tap->at_chan_freq =
ic->ic_bss->ni_chan->ic_freq;
@ -1556,9 +1556,9 @@ an_write_wepkey(struct an_softc *sc, int type, struct an_wepkey *keys, int kid)
akey->an_key_len = keys[i].an_wep_keylen;
akey->an_key_index = i;
akey->an_mac_addr[0] = 1; /* default mac */
an_swap16((u_int16_t *)&akey->an_mac_addr, 3);
an_swap16((u_int16_t *)&akey->an_mac_addr, 3);
memcpy(akey->an_key, keys[i].an_wep_key, keys[i].an_wep_keylen);
an_swap16((u_int16_t *)&akey->an_key, 8);
an_swap16((u_int16_t *)&akey->an_key, 8);
if ((error = an_write_rid(sc, type, akey, sizeof(*akey))) != 0)
return error;
}
@ -1566,7 +1566,7 @@ an_write_wepkey(struct an_softc *sc, int type, struct an_wepkey *keys, int kid)
memset(akey, 0, sizeof(struct an_rid_wepkey));
akey->an_key_index = 0xffff;
akey->an_mac_addr[0] = kid;
an_swap16((u_int16_t *)&akey->an_mac_addr, 3);
an_swap16((u_int16_t *)&akey->an_mac_addr, 3);
akey->an_key_len = 0;
memset(akey->an_key, 0, sizeof(akey->an_key));
error = an_write_rid(sc, type, akey, sizeof(*akey));
@ -1594,8 +1594,8 @@ an_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
case IEEE80211_S_RUN:
buflen = sizeof(sc->sc_buf);
an_read_rid(sc, AN_RID_STATUS, &sc->sc_buf, &buflen);
an_swap16((u_int16_t *)&sc->sc_buf.sc_status.an_cur_bssid, 3);
an_swap16((u_int16_t *)&sc->sc_buf.sc_status.an_ssid, 16);
an_swap16((u_int16_t *)&sc->sc_buf.sc_status.an_cur_bssid, 3);
an_swap16((u_int16_t *)&sc->sc_buf.sc_status.an_ssid, 16);
IEEE80211_ADDR_COPY(ni->ni_bssid,
sc->sc_buf.sc_status.an_cur_bssid);
IEEE80211_ADDR_COPY(ni->ni_macaddr, ni->ni_bssid);

6
sys/dev/ic/ar5008.c
View file

@ -1341,7 +1341,7 @@ ar5008_swba_intr(struct athn_softc *sc)
wh = mtod(m, struct ieee80211_frame *);
wh->i_fc[1] |= IEEE80211_FC1_MORE_DATA;
}
if (sc->ops.tx(sc, m, ni, ATHN_TXFLAG_CAB) != 0) {
ieee80211_release_node(ic, ni);
ifp->if_oerrors++;
@ -1559,7 +1559,7 @@ ar5008_tx(struct athn_softc *sc, struct mbuf *m, struct ieee80211_node *ni,
} else {
/* Use fallback table of the node. */
int txrate;
if (ni->ni_flags & IEEE80211_NODE_HT)
txrate = ATHN_NUM_LEGACY_RATES + ni->ni_txmcs;
else
@ -1684,7 +1684,7 @@ ar5008_tx(struct athn_softc *sc, struct mbuf *m, struct ieee80211_node *ni,
ds->ds_ctl0 |= AR_TXC0_CTS_ENABLE;
}
}
/*
/*
* Disable multi-rate retries when protection is used.
* The RTS/CTS frame's duration field is fixed and won't be
* updated by hardware when the data rate changes.

2
sys/dev/ic/ar5211.c
View file

@ -651,7 +651,7 @@ ar5k_ar5211_reset(struct ath_hal *hal, HAL_OPMODE op_mode, HAL_CHANNEL *channel,
ar5k_ar5211_set_gpio_intr(hal, 0, 0);
}
/*
/*
* Disable beacons and reset the register
*/
AR5K_REG_DISABLE_BITS(AR5K_AR5211_BEACON,

4
sys/dev/ic/ar5212.c
View file

@ -828,7 +828,7 @@ ar5k_ar5212_reset(struct ath_hal *hal, HAL_OPMODE op_mode, HAL_CHANNEL *channel,
AR5K_REG_WRITE(AR5K_AR5212_PHY_SDELAY, AR5K_AR5212_PHY_SDELAY_32MHZ);
AR5K_REG_WRITE(AR5K_AR5212_PHY_SPENDING, hal->ah_phy_spending);
/*
/*
* Disable beacons and reset the register
*/
AR5K_REG_DISABLE_BITS(AR5K_AR5212_BEACON,
@ -2998,7 +2998,7 @@ ar5k_ar5212_txpower(struct ath_hal *hal, HAL_CHANNEL *channel, u_int txpower)
/* Initialize TX power table */
ar5k_txpower_table(hal, channel, txpower);
/*
/*
* Write TX power values
*/
for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {

2
sys/dev/ic/ar5xxx.c
View file

@ -1160,7 +1160,7 @@ ar5k_ar5111_chan2athchan(u_int ieee, struct ar5k_athchan_2ghz *athchan)
{
int channel;
/* Cast this value to catch negative channel numbers (>= -19) */
/* Cast this value to catch negative channel numbers (>= -19) */
channel = (int)ieee;
/*

4
sys/dev/ic/ar9003.c
View file

@ -1291,7 +1291,7 @@ ar9003_swba_intr(struct athn_softc *sc)
wh = mtod(m, struct ieee80211_frame *);
wh->i_fc[1] |= IEEE80211_FC1_MORE_DATA;
}
if (sc->ops.tx(sc, m, ni, ATHN_TXFLAG_CAB) != 0) {
ieee80211_release_node(ic, ni);
ifp->if_oerrors++;
@ -1610,7 +1610,7 @@ ar9003_tx(struct athn_softc *sc, struct mbuf *m, struct ieee80211_node *ni,
ds->ds_ctl11 |= AR_TXC11_CTS_ENABLE;
}
}
/*
/*
* Disable multi-rate retries when protection is used.
* The RTS/CTS frame's duration field is fixed and won't be
* updated by hardware when the data rate changes.

8
sys/dev/ic/ath.c
View file

@ -38,7 +38,7 @@
*
* This software is derived from work of Atsushi Onoe; his contribution
* is greatly appreciated. It has been modified for OpenBSD to use an
* open source HAL instead of the original binary-only HAL.
* open source HAL instead of the original binary-only HAL.
*/
#include "bpfilter.h"
@ -1375,7 +1375,7 @@ ath_beacon_config(struct ath_softc *sc)
bs.bs_nextdtim = nexttbtt;
/*
* Calculate the number of consecutive beacons to miss
* before taking a BMISS interrupt.
* before taking a BMISS interrupt.
* Note that we clamp the result to at most 7 beacons.
*/
bs.bs_bmissthreshold = ic->ic_bmissthres;
@ -1834,7 +1834,7 @@ ath_rx_proc(void *arg, int npending)
* discard the frame.
*/
/*
/*
* Enable this if you want to see error
* frames in Monitor mode.
*/
@ -2011,7 +2011,7 @@ ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni,
pktlen = m0->m_pkthdr.len;
if (ath_softcrypto && iswep) {
k = ieee80211_get_txkey(ic, wh, ni);
k = ieee80211_get_txkey(ic, wh, ni);
if ((m0 = ieee80211_encrypt(ic, m0, k)) == NULL)
return ENOMEM;
wh = mtod(m0, struct ieee80211_frame *);

2
sys/dev/ic/athnreg.h
View file

@ -282,7 +282,7 @@
/* Bits for AR_MIRT. */
#define AR_MIRT_RATE_THRES_M 0x0000ffff
#define AR_MIRT_RATE_THRES_S 0
#define AR_MIRT_RATE_THRES_S 0
/* Bits for AR_TIMT. */
#define AR_TIMT_LAST_M 0x0000ffff

2
sys/dev/ic/athnvar.h
View file

@ -82,7 +82,7 @@ struct athn_tx_buf {
int bf_txmcs;
int bf_txflags;
#define ATHN_TXFLAG_PAPRD (1 << 0)
#define ATHN_TXFLAG_CAB (1 << 1)
#define ATHN_TXFLAG_CAB (1 << 1)
};
struct athn_txq {

6
sys/dev/ic/athvar.h
View file

@ -161,8 +161,8 @@ struct ath_tx_radiotap_header {
u_int8_t wt_antenna;
} __packed;
/*
* driver-specific node
/*
* driver-specific node
*/
struct ath_node {
struct ieee80211_node an_node; /* base class */
@ -289,7 +289,7 @@ struct ath_softc {
gpio_pin_t sc_gpio_pins[ATH_MAXGPIO];
};
/* unaligned little endian access */
/* unaligned little endian access */
#define LE_READ_2(p) \
((u_int16_t) \
((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8)))

6
sys/dev/ic/atw.c
View file

@ -797,7 +797,7 @@ atw_attach(struct atw_softc *sc)
#ifndef IEEE80211_STA_ONLY
ic->ic_caps |= IEEE80211_C_IBSS;
#endif
ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b;
ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b;
/*
* Call MI attach routines.
@ -3442,7 +3442,7 @@ atw_compute_duration1(int len, int use_ack, uint32_t flags, int rate,
*
* wh: 802.11 header
*
* len: packet length
* len: packet length
*
* rate: MSDU speed, units 500kb/s
*
@ -3620,7 +3620,7 @@ atw_start(struct ifnet *ifp)
m0 = ieee80211_encrypt(ic, m0, k);
if (m0 == NULL) {
ifp->if_oerrors++;
break;
break;
}
}
}

18
sys/dev/ic/atwreg.h
View file

@ -221,7 +221,7 @@
#define ATW_C_FRCTL_CTX_DATA (1<<22) /* 0: set by CSR28
* 1: random
*/
#define ATW_C_FRCTL_RSVFRM (1<<21) /* 1: receive "reserved"
#define ATW_C_FRCTL_RSVFRM (1<<21) /* 1: receive "reserved"
* frames, 0: ignore
* reserved frames
*/
@ -342,7 +342,7 @@
#define ATW_IER_REIE (1<<12) /* RX packet filled its first
* descriptor
*/
#define ATW_IER_RCIE (1<<6) /* completed RX */
#define ATW_IER_RCIE (1<<6) /* completed RX */
#define ATW_IER_TDUIE (1<<2) /* transmit descriptor
* unavailable
*/
@ -417,7 +417,7 @@
/* Running - close transmit descriptor */
#define ATW_TEST0_TS_CLOSE LSHIFT(7, ATW_TEST0_TS_MASK)
/* ADM8211C/CR registers */
/* ADM8211C/CR registers */
/* Suspended */
#define ATW_C_TEST0_TS_SUSPENDED LSHIFT(4, ATW_TEST0_TS_MASK)
/* Descriptor write */
@ -676,7 +676,7 @@
#define ATW_PAR0_PAB2_MASK 0xff0000 /* MAC address byte 2 */
#define ATW_PAR0_PAB3_MASK 0xff000000 /* MAC address byte 3 */
#define ATW_C_PAR1_CTD 0xffff0000 /* Continuous Tx pattern */
#define ATW_C_PAR1_CTD 0xffff0000 /* Continuous Tx pattern */
#define ATW_PAR1_PAB5_MASK 0xff00 /* MAC address byte 5 */
#define ATW_PAR1_PAB4_MASK 0xff /* MAC address byte 4 */
@ -880,8 +880,8 @@
/* Function Event/Status registers */
#define ATW_FER_INTR (1<<15) /* interrupt: set regardless of mask */
#define ATW_FER_GWAKE (1<<4) /* general wake-up: set regardless of mask */
#define ATW_FER_INTR (1<<15) /* interrupt: set regardless of mask */
#define ATW_FER_GWAKE (1<<4) /* general wake-up: set regardless of mask */
#define ATW_FEMR_INTR_EN (1<<15) /* enable INTA# */
#define ATW_FEMR_WAKEUP_EN (1<<14) /* enable wake-up */
@ -939,7 +939,7 @@
#define ATW_SR_CHECKSUM (0x7e/2) /* for data 0x00-0x7d */
#define ATW_SR_CIS (0x80/2) /* Cardbus CIS */
/* Tx descriptor */
/* Tx descriptor */
struct atw_txdesc {
u_int32_t at_ctl;
#define at_stat at_ctl
@ -973,7 +973,7 @@ struct atw_txdesc {
#define ATW_TXFLAG_TBS2_MASK 0xfff000 /* at_buf2 byte count */
#define ATW_TXFLAG_TBS1_MASK 0xfff /* at_buf1 byte count */
/* Rx descriptor */
/* Rx descriptor */
struct atw_rxdesc {
u_int32_t ar_stat;
u_int32_t ar_ctl;
@ -989,7 +989,7 @@ struct atw_rxdesc {
#define ATW_RXCTL_RBS1_MASK 0xfff /* ar_buf1 byte count */
#define ATW_RXSTAT_OWN (1<<31) /* 1: NIC may fill descriptor */
#define ATW_RXSTAT_ES (1<<30) /* error summary, 0 on
#define ATW_RXSTAT_ES (1<<30) /* error summary, 0 on
* success
*/
#define ATW_RXSTAT_SQL (1<<29) /* has signal quality (?) */

2
sys/dev/ic/bcmgenetvar.h
View file

@ -64,7 +64,7 @@ struct genet_softc {
enum genet_phy_mode sc_phy_mode;
void *sc_ih;
struct arpcom sc_ac;
#define sc_lladdr sc_ac.ac_enaddr
struct mii_data sc_mii;

48
sys/dev/ic/bt463.c
View file

@ -59,7 +59,7 @@
*/
/* This code was derived from and originally located in sys/dev/pci/
* NetBSD: tga_bt463.c,v 1.5 2000/03/04 10:27:59 elric Exp
* NetBSD: tga_bt463.c,v 1.5 2000/03/04 10:27:59 elric Exp
*/
#include <sys/param.h>
@ -134,7 +134,7 @@ struct bt463data {
* around, and is probably
* struct tga_devconfig *
*/
int (*ramdac_sched_update)(void *, void (*)(void *));
void (*ramdac_wr)(void *, u_int, u_int8_t);
u_int8_t (*ramdac_rd)(void *, u_int);
@ -151,7 +151,7 @@ struct bt463data {
/* When we're doing console initialization, there's no
* way to get our cookie back to the video card's softc
* before we call sched_update. So we stash it here,
* before we call sched_update. So we stash it here,
* and bt463_update will look for it here first.
*/
static struct bt463data *console_data;
@ -177,7 +177,7 @@ inline void bt463_wraddr(struct bt463data *, u_int16_t);
void bt463_update(void *);
/*****************************************************************************/
/*
@ -254,9 +254,9 @@ bt463_init(rc)
/*
* Setup:
* reg 0: 4:1 multiplexing, 25/75 blink.
* reg 1: Overlay mapping: mapped to common palette,
* reg 1: Overlay mapping: mapped to common palette,
* 14 window type entries, 24-plane configuration mode,
* 4 overlay planes, underlays disabled, no cursor.
* 4 overlay planes, underlays disabled, no cursor.
* reg 2: sync-on-green enabled, pedestal enabled.
*/
@ -307,7 +307,7 @@ bt463_init(rc)
* Entry 0: 24-plane truecolor, overlays enabled, bypassed.
*
* Lookup table bypass: yes ( 1 << 23 & 0x800000) 800000
* Colormap address: 0x000 (0x000 << 17 & 0x7e0000) 0
* Colormap address: 0x000 (0x000 << 17 & 0x7e0000) 0
* Overlay mask: 0xf ( 0xf << 13 & 0x01e000) 1e000
* Overlay location: P<27:24> ( 0 << 12 & 0x001000) 0
* Display mode: Truecolor ( 0 << 9 & 0x000e00) 000
@ -315,14 +315,14 @@ bt463_init(rc)
* Plane shift: 0 ( 0 << 0 & 0x00001f) 0
* --------
* 0x81e100
*/
*/
data->window_type[0] = 0x81e100;
/* Entry 1: 8-plane pseudocolor in the bottom 8 bits,
* overlays enabled, colormap starting at 0.
/* Entry 1: 8-plane pseudocolor in the bottom 8 bits,
* overlays enabled, colormap starting at 0.
*
* Lookup table bypass: no ( 0 << 23 & 0x800000) 0
* Colormap address: 0x000 (0x000 << 17 & 0x7e0000) 0
* Colormap address: 0x000 (0x000 << 17 & 0x7e0000) 0
* Overlay mask: 0xf ( 0xf << 13 & 0x01e000) 0x1e000
* Overlay location: P<27:24> ( 0 << 12 & 0x001000) 0
* Display mode: Pseudocolor ( 1 << 9 & 0x000e00) 0x200
@ -330,15 +330,15 @@ bt463_init(rc)
* Plane shift: 16 ( 0x10 << 0 & 0x00001f) 10
* --------
* 0x01e310
*/
*/
data->window_type[1] = 0x01e310;
/* The colormap interface to the world only supports one colormap,
* so having an entry for the 'alternate' colormap in the bt463
/* The colormap interface to the world only supports one colormap,
* so having an entry for the 'alternate' colormap in the bt463
* probably isn't useful.
*/
/* Fill the remaining table entries with clones of entry 0 until we
/* Fill the remaining table entries with clones of entry 0 until we
* figure out a better use for them.
*/
@ -494,7 +494,7 @@ bt463_get_curcmap(rc, cursorp)
#ifdef BT463_DEBUG
int bt463_store(void *v)
{
struct bt463data *data = (struct bt463data *)v;
struct bt463data *data = (struct bt463data *)v;
data->changed = DATA_ALL_CHANGED;
data->ramdac_sched_update(data->cookie, bt463_update);
@ -506,7 +506,7 @@ int bt463_store(void *v)
int bt463_readback(void *v)
{
struct bt463data *data = (struct bt463data *)v;
struct bt463data *data = (struct bt463data *)v;
data->ramdac_sched_update(data->cookie, bt463_copyback);
printf("Scheduled bt463 copyback\n");
@ -540,7 +540,7 @@ bt463_debug(v)
return 0;
}
void
void
bt463_copyback(p)
void *p;
{
@ -583,7 +583,7 @@ bt463_update(p)
/* The Bt463 won't accept window type data except during a blanking
* interval, so we do this early in the interrupt.
* Blanking the screen might also be a good idea, but it can cause
* Blanking the screen might also be a good idea, but it can cause
* unpleasant flashing and is hard to do from this side of the
* ramdac interface.
*/
@ -596,7 +596,7 @@ bt463_update(p)
BTWNREG(data, (data->window_type[i] >> 16) & 0xff); /* B16-23 */
}
}
if (v & DATA_CURCMAP_CHANGED) {
bt463_wraddr(data, BT463_IREG_CURSOR_COLOR_0);
/* spit out the cursor data */
@ -606,16 +606,16 @@ bt463_update(p)
BTWNREG(data, data->curcmap_b[i]);
}
}
if (v & DATA_CMAP_CHANGED) {
bt463_wraddr(data, BT463_IREG_CPALETTE_RAM);
/* spit out the colormap data */
for (i = 0; i < BT463_NCMAP_ENTRIES; i++) {
data->ramdac_wr(data->cookie, BT463_REG_CMAP_DATA,
data->ramdac_wr(data->cookie, BT463_REG_CMAP_DATA,
data->cmap_r[i]);
data->ramdac_wr(data->cookie, BT463_REG_CMAP_DATA,
data->ramdac_wr(data->cookie, BT463_REG_CMAP_DATA,
data->cmap_g[i]);
data->ramdac_wr(data->cookie, BT463_REG_CMAP_DATA,
data->ramdac_wr(data->cookie, BT463_REG_CMAP_DATA,
data->cmap_b[i]);
}
}

6
sys/dev/ic/bt485.c
View file

@ -29,7 +29,7 @@
*/
/* This code was derived from and originally located in sys/dev/pci/
* NetBSD: tga_bt485.c,v 1.4 1999/03/24 05:51:21 mrg Exp
* NetBSD: tga_bt485.c,v 1.4 1999/03/24 05:51:21 mrg Exp
*/
#include <sys/param.h>
@ -93,7 +93,7 @@ struct bt485data {
* around, and is probably
* struct tga_devconfig *
*/
int (*ramdac_sched_update)(void *, void (*)(void *));
void (*ramdac_wr)(void *, u_int, u_int8_t);
u_int8_t (*ramdac_rd)(void *, u_int);
@ -576,7 +576,7 @@ bt485_update(vp)
for (i = 0; i < count; i++)
data->ramdac_wr(data->cookie, BT485_REG_CURSOR_RAM,
data->curimage[i]);
/*
* Write the cursor mask data:
* set addr[9:8] to 2,

10
sys/dev/ic/bt485reg.h
View file

@ -6,17 +6,17 @@
* All rights reserved.
*
* Author: Chris G. Demetriou
*
*
* Permission to use, copy, modify and distribute this software and
* its documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU

12
sys/dev/ic/bt8xx.h
View file

@ -172,7 +172,7 @@ struct meteor_video {
#define METEOR_SIG_FIELD 0x00010000 /* signal every field */
/* following structure is used to coordinate the synchronous */
struct meteor_mem {
/* kernel write only */
int frame_size; /* row*columns*depth */
@ -296,7 +296,7 @@ struct eeProm {
#define TVTUNER_GETSTATUS _IOR('x', 34, unsigned int) /* get tuner status */
#define TVTUNER_SETFREQ _IOW('x', 35, unsigned int) /* set frequency */
#define TVTUNER_GETFREQ _IOR('x', 36, unsigned int) /* get frequency */
#define BT848_SHUE _IOW('x', 37, int) /* set hue */
#define BT848_GHUE _IOR('x', 37, int) /* get hue */
@ -333,9 +333,9 @@ struct eeProm {
/* Read/Write the BT848's I2C bus directly
* b7-b0: data (read/write)
* b15-b8: internal peripheral register (write)
* b15-b8: internal peripheral register (write)
* b23-b16: i2c addr (write)
* b31-b24: 1 = write, 0 = read
* b31-b24: 1 = write, 0 = read
*/
#define BT848_I2CWR _IOWR('x', 57, u_int) /* i2c read-write */
@ -460,10 +460,10 @@ struct bktr_remote {
/*control receiver*/
/*returns raw data*/
/*
* Direct access to GPIO pins. You must add BKTR_GPIO_ACCESS to your kernel
* configuration file to use these
* configuration file to use these
*/
#define BT848_GPIO_SET_EN _IOW('x', 72, int) /* set gpio_out_en */
#define BT848_GPIO_GET_EN _IOR('x', 73, int) /* get gpio_out_en */

4
sys/dev/ic/bwfm.c
View file

@ -656,7 +656,7 @@ bwfm_rate2vhtmcs(int *mcs, int *ss, uint32_t txrate)
{
const struct ieee80211_vht_rateset *rs;
int i, j;
*mcs = -1;
*ss = -1;
/* TODO: Select specific ratesets based on BSS channel width. */
@ -677,7 +677,7 @@ bwfm_rate2htmcs(uint32_t txrate)
{
const struct ieee80211_ht_rateset *rs;
int i, j;
/* TODO: Select specific ratesets based on BSS channel width. */
for (i = 0; i < IEEE80211_HT_NUM_RATESETS; i++) {
rs = &ieee80211_std_ratesets_11n[i];

18
sys/dev/ic/bwi.c
View file

@ -2,14 +2,14 @@
/*
* Copyright (c) 2007 The DragonFly Project. All rights reserved.
*
*
* This code is derived from software contributed to The DragonFly Project
* by Sepherosa Ziehau <sepherosa@gmail.com>
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
@ -19,7 +19,7 @@
* 3. Neither the name of The DragonFly Project nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific, prior written permission.
*
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
@ -32,7 +32,7 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
*
* $DragonFly: src/sys/dev/netif/bwi/bwimac.c,v 1.1 2007/09/08 06:15:54 sephe Exp $
*/
@ -7044,7 +7044,7 @@ bwi_init_statechg(struct bwi_softc *sc, int statechg)
goto back;
bwi_bbp_power_on(sc, BWI_CLOCK_MODE_DYN);
IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl));
bwi_set_bssid(sc, bwi_zero_addr); /* Clear BSSID */
@ -7514,7 +7514,7 @@ bwi_dma_alloc(struct bwi_softc *sc)
switch (sc->sc_bus_space) {
case BWI_BUS_SPACE_30BIT:
/*
/*
* 30bit devices must use bounce buffers but
* otherwise work like 32bit devices.
*/
@ -8701,7 +8701,7 @@ bwi_ack_rate(struct ieee80211_node *ni, uint8_t rate)
for (i = 0; i < rs->rs_nrates; ++i) {
uint8_t rate1 = rs->rs_rates[i] & IEEE80211_RATE_VAL;
if (rate1 > rate) {
if (ack_rate != 0)
return ack_rate;
@ -8759,7 +8759,7 @@ bwi_ack_rate(struct ieee80211_node *ni, uint8_t rate)
#define IEEE80211_OFDM_SIGNAL_TIME 4
#define IEEE80211_OFDM_PLCP_SERVICE_NBITS 16
#define IEEE80211_OFDM_TAIL_NBITS 6
#define IEEE80211_OFDM_TAIL_NBITS 6
#define IEEE80211_OFDM_NBITS(frmlen) \
(IEEE80211_OFDM_PLCP_SERVICE_NBITS + \

10
sys/dev/ic/bwireg.h
View file

@ -2,14 +2,14 @@
/*
* Copyright (c) 2007 The DragonFly Project. All rights reserved.
*
*
* This code is derived from software contributed to The DragonFly Project
* by Sepherosa Ziehau <sepherosa@gmail.com>
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
@ -19,7 +19,7 @@
* 3. Neither the name of The DragonFly Project nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific, prior written permission.
*
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
@ -32,7 +32,7 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
*
* $DragonFly: src/sys/dev/netif/bwi/if_bwireg.h,v 1.1 2007/09/08 06:15:54 sephe Exp $
*/

18
sys/dev/ic/bwivar.h
View file

@ -2,14 +2,14 @@
/*
* Copyright (c) 2007 The DragonFly Project. All rights reserved.
*
*
* This code is derived from software contributed to The DragonFly Project
* by Sepherosa Ziehau <sepherosa@gmail.com>
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
@ -19,7 +19,7 @@
* 3. Neither the name of The DragonFly Project nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific, prior written permission.
*
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
@ -32,7 +32,7 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
*
* $DragonFly: src/sys/dev/netif/bwi/if_bwivar.h,v 1.1 2007/09/08 06:15:54 sephe Exp $
*/
@ -553,7 +553,7 @@ struct bwi_softc {
struct timeout sc_led_blink_end_ch;
int sc_led_blink_offdur;
struct bwi_led sc_leds[BWI_LED_MAX];
enum bwi_bus_space sc_bus_space;
/* bounce buffers for 30 bit bus space devices */
@ -596,7 +596,7 @@ struct bwi_softc {
void (*sc_txeof_status)(struct bwi_softc *);
int (*sc_enable)(struct bwi_softc *);
int (*sc_enable)(struct bwi_softc *);
void (*sc_disable)(struct bwi_softc *);
void (*sc_conf_write)(void *, uint32_t, uint32_t);
@ -610,14 +610,14 @@ struct bwi_softc {
#if NBPFILTER > 0
caddr_t sc_drvbpf;
union {
struct bwi_rx_radiotap_hdr th;
uint8_t pad[64];
} sc_rxtapu;
#define sc_rxtap sc_rxtapu.th
int sc_rxtap_len;
union {
struct bwi_tx_radiotap_hdr th;
uint8_t pad[64];

2
sys/dev/ic/cacreg.h
View file

@ -247,5 +247,5 @@ struct cac_sgb {
u_int32_t length; /* length of S/G segment */
u_int32_t addr; /* physical address of block */
} __packed;
#endif /* !_IC_CACREG_H_ */

2
sys/dev/ic/cacvar.h
View file

@ -104,7 +104,7 @@ struct cac_softc {
const struct cac_linkage *sc_cl;
caddr_t sc_ccbs;
paddr_t sc_ccbs_paddr;
SIMPLEQ_HEAD(, cac_ccb) sc_ccb_free;
SIMPLEQ_HEAD(, cac_ccb) sc_ccb_free;
SIMPLEQ_HEAD(, cac_ccb) sc_ccb_queue;
struct cac_drive_info *sc_dinfos;
int (*sc_ioctl)(struct device *, u_long, caddr_t);

2
sys/dev/ic/com.c
View file

@ -1162,7 +1162,7 @@ cominit(bus_space_tag_t iot, bus_space_handle_t ioh, int rate, int frequency)
}
#ifdef COM_CONSOLE
void
void
comcnprobe(struct consdev *cp)
{
bus_space_handle_t ioh;

6
sys/dev/ic/cy.c
View file

@ -159,7 +159,7 @@ cy_probe_common(bus_space_tag_t memt, bus_space_handle_t memh, int bustype)
}
#ifdef CY_DEBUG
printf("firmware version 0x%x\n", firmware_ver);
#endif
#endif
if ((firmware_ver & 0xf0) != 0x40)
break;
@ -216,7 +216,7 @@ cy_attach(struct device *parent, struct device *self)
/* Set cy_clock depending on firmware version */
if (cd_read_reg_sc(sc, cy_chip, CD1400_GFRCR) <= 0x46)
cy_clock = CY_CLOCK;
else
else
cy_clock = CY_CLOCK_60;
/* set up a receive timeout period (1ms) */
@ -964,7 +964,7 @@ cy_poll(void *arg)
doesn't change RTS if RTSCTS is on */
cd_write_reg(cy, CD1400_CAR,
port & CD1400_CAR_CHAN);
if ((cd_read_reg(cy,
CD1400_MSVR1) & CD1400_MSVR1_RTS) == 0) {
cd_write_reg(cy, CD1400_MSVR1,

2
sys/dev/ic/cyreg.h
View file

@ -85,7 +85,7 @@
#define RX_DTR_THRESHOLD 9
/*
* Maximum number of ports per card
* Maximum number of ports per card
*/
#define CY_MAX_PORTS (CD1400_NO_OF_CHANNELS * CY_MAX_CD1400s)

18
sys/dev/ic/dc.c
View file

@ -534,7 +534,7 @@ dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame)
frame->mii_opcode = DC_MII_READOP;
frame->mii_turnaround = 0;
frame->mii_data = 0;
/*
* Sync the PHYs.
*/
@ -606,7 +606,7 @@ dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame)
/*
* Sync the PHYs.
*/
*/
dc_mii_sync(sc);
dc_mii_send(sc, frame->mii_stdelim, 2);
@ -946,7 +946,7 @@ dc_setfilt_21143(struct dc_softc *sc)
bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,
offsetof(struct dc_list_data, dc_sbuf[0]),
sizeof(struct dc_list_data) -
sizeof(struct dc_list_data) -
offsetof(struct dc_list_data, dc_sbuf[0]),
BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
@ -1592,7 +1592,7 @@ dc_attach(struct dc_softc *sc)
case DC_TYPE_21143:
case DC_TYPE_21145:
case DC_TYPE_ASIX:
dc_read_eeprom(sc, (caddr_t)&sc->sc_arpcom.ac_enaddr,
dc_read_eeprom(sc, (caddr_t)&sc->sc_arpcom.ac_enaddr,
DC_EE_NODEADDR, 3, 0);
break;
case DC_TYPE_AL981:
@ -1668,7 +1668,7 @@ hasmac:
BUS_DMA_NOWAIT, &sc->sc_rx_sparemap) != 0) {
printf(": can't create rx spare map\n");
return;
}
}
for (i = 0; i < DC_TX_LIST_CNT; i++) {
if (bus_dmamap_create(sc->sc_dmat, MCLBYTES,
@ -2023,7 +2023,7 @@ dc_pnic_rx_bug_war(struct dc_softc *sc, int idx)
* frame reception.
*/
dc_newbuf(sc, i, m);
bcopy(ptr, mtod(m, char *), total_len);
bcopy(ptr, mtod(m, char *), total_len);
cur_rx->dc_status = htole32(rxstat | DC_RXSTAT_FIRSTFRAG);
}
@ -2148,7 +2148,7 @@ dc_rxeof(struct dc_softc *sc)
}
}
/* No errors; receive the packet. */
/* No errors; receive the packet. */
total_len -= ETHER_CRC_LEN;
m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN);
@ -2703,10 +2703,10 @@ dc_init(void *xsc)
break;
case 16:
DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG);
break;
break;
case 8:
DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG);
break;
break;
case 0:
default:
DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE);

2
sys/dev/ic/dc21040reg.h
View file

@ -421,7 +421,7 @@ typedef struct {
#define TULIP_GP_ZX346_FULLDUPLEX 0x00000004 /* Full Duplex Sensed */
#define TULIP_GP_ZX34X_LB102 0x00000002 /* 100tx twister LB */
#define TULIP_GP_ZX34X_NLB101 0x00000001 /* PDT/PDR LB */
#define TULIP_GP_ZX34X_INIT 0x00000009
#define TULIP_GP_ZX34X_INIT 0x00000009
/*
* Compex's OUI. We need to twiddle a bit on their 21041 card.

4
sys/dev/ic/dcreg.h
View file

@ -573,7 +573,7 @@ struct dc_mii_frame {
/*
* Special ASIX-specific bits in the ASIX NETCFG register (CSR6).
*/
#define DC_AX_NETCFG_RX_BROAD 0x00000100
#define DC_AX_NETCFG_RX_BROAD 0x00000100
/*
* RX Filter Index Register values
@ -665,7 +665,7 @@ struct dc_mii_frame {
DC_SETBIT(sc, DC_PN_GPIO, ((r) << 4)); \
DC_CLRBIT(sc, DC_PN_GPIO, (r)); \
}
/* shortcut MII access register */
#define DC_PN_MII_DATA 0x0000FFFF
#define DC_PN_MII_RESERVER 0x00020000

2
sys/dev/ic/dl10019.c
View file

@ -210,7 +210,7 @@ dl10019_mii_writereg(struct device *self, int phy, int reg, int val)
{
struct ne2000_softc *nsc = (void *) self;
const struct mii_bitbang_ops *ops;
ops = (nsc->sc_type == NE2000_TYPE_DL10022) ?
&dl10022_mii_bitbang_ops : &dl10019_mii_bitbang_ops;

2
sys/dev/ic/dp8390reg.h
View file

@ -358,7 +358,7 @@
* algorithm to allow prioritization of nodes.
*/
#define ED_TCR_OFST 0x10
/*
* bits 5, 6, and 7 are unused/reserved
*/

2
sys/dev/ic/dwhdmi.c
View file

@ -526,7 +526,7 @@ dwhdmi_audio_init(struct dwhdmi_softc *sc)
val &= ~HDMI_AUD_CONF0_I2S_IN_EN;
val |= (1 << 0); /* XXX 2ch */
dwhdmi_write(sc, HDMI_AUD_CONF0, val);
val = (16 << 0);
dwhdmi_write(sc, HDMI_AUD_CONF1, val);

2
sys/dev/ic/dwiic.c
View file

@ -176,7 +176,7 @@ dwiic_init(struct dwiic_softc *sc)
sc->tx_fifo_depth = tx_fifo_depth;
if (rx_fifo_depth > 1 && rx_fifo_depth < sc->rx_fifo_depth)
sc->rx_fifo_depth = rx_fifo_depth;
dwiic_write(sc, DW_IC_TX_TL, sc->tx_fifo_depth / 2);
dwiic_write(sc, DW_IC_RX_TL, 0);

32
sys/dev/ic/elink3.c
View file

@ -65,7 +65,7 @@
#include <dev/ic/elink3reg.h>
/*
* Structure to map media-present bits in boards to
* Structure to map media-present bits in boards to
* ifmedia codes and printable media names. Used for table-driven
* ifmedia initialization.
*/
@ -79,11 +79,11 @@ struct ep_media {
/*
* ep_media table for Vortex/Demon/Boomerang:
* map from media-present bits in register RESET_OPTIONS+2
* map from media-present bits in register RESET_OPTIONS+2
* to ifmedia "media words" and printable names.
*
* XXX indexed directly by INTERNAL_CONFIG default_media field,
* (i.e., EPMEDIA_ constants) forcing order of entries.
* (i.e., EPMEDIA_ constants) forcing order of entries.
* Note that 3 is reserved.
*/
const struct ep_media ep_vortex_media[] = {
@ -288,14 +288,14 @@ epconfig(struct ep_softc *sc, u_short chipset, u_int8_t *enaddr)
* packets. Commands only take an 11-bit parameter, and 11 bits
* isn't enough to hold a full-size packet length.
* Commands to these cards implicitly upshift a packet size
* or threshold by 2 bits.
* or threshold by 2 bits.
* To detect cards with large-packet support, we probe by setting
* the transmit threshold register, then change windows and
* read back the threshold register directly, and see if the
* threshold value was shifted or not.
*/
bus_space_write_2(iot, ioh, EP_COMMAND,
SET_TX_AVAIL_THRESH | EP_LARGEWIN_PROBE );
SET_TX_AVAIL_THRESH | EP_LARGEWIN_PROBE );
GO_WINDOW(5);
i = bus_space_read_2(iot, ioh, EP_W5_TX_AVAIL_THRESH);
GO_WINDOW(1);
@ -319,7 +319,7 @@ epconfig(struct ep_softc *sc, u_short chipset, u_int8_t *enaddr)
timeout_set(&sc->sc_epmbuffill_tmo, epmbuffill, sc);
/*
* Ensure Tx-available interrupts are enabled for
* Ensure Tx-available interrupts are enabled for
* start the interface.
* XXX should be in epinit()?
*/
@ -340,7 +340,7 @@ epconfig(struct ep_softc *sc, u_short chipset, u_int8_t *enaddr)
ether_ifattach(ifp);
/*
* Finish configuration:
* Finish configuration:
* determine chipset if the front-end couldn't do so,
* show board details, set media.
*/
@ -545,11 +545,11 @@ ep_vortex_probemedia(struct ep_softc *sc)
medium_name, (autoselect) ? "/autoselect" : "");
/* sc->sc_media = ep_vortex_media[default_media].epm_ifdata;*/
#ifdef notyet
#ifdef notyet
/*
* Set default: either the active interface the card
* reads from the EEPROM, or if autoselect is true,
* whatever we find is actually connected.
* whatever we find is actually connected.
*
* XXX autoselect not yet implemented.
*/
@ -666,7 +666,7 @@ epinit(struct ep_softc *sc)
}
/*
* Set multicast receive filter.
* Set multicast receive filter.
* elink3 hardware has no selective multicast filter in hardware.
* Enable reception of all multicasts and filter in software.
*/
@ -818,7 +818,7 @@ epsetmedia(struct ep_softc *sc, int medium)
printf("%s unknown media 0x%x\n", sc->sc_dev.dv_xname, medium);
#endif
break;
}
/*
@ -839,7 +839,7 @@ epsetmedia(struct ep_softc *sc, int medium)
#endif
config1 = config1 & ~CONFIG_MEDIAMASK;
config1 |= (medium << CONFIG_MEDIAMASK_SHIFT);
#if defined(EP_DEBUG)
printf("epsetmedia: %s: medium 0x%x, 0x%x to EP_W3_CONFIG\n",
sc->sc_dev.dv_xname, medium, config1);
@ -888,7 +888,7 @@ ep_media_status(struct ifnet *ifp, struct ifmediareq *req)
/* XXX read from softc when we start autosensing media */
req->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media;
switch (sc->ep_chipset) {
case EP_CHIPSET_VORTEX:
case EP_CHIPSET_BOOMERANG:
@ -898,7 +898,7 @@ ep_media_status(struct ifnet *ifp, struct ifmediareq *req)
config1 = bus_space_read_2(iot, ioh, EP_W3_INTERNAL_CONFIG + 2);
GO_WINDOW(1);
config1 =
config1 =
(config1 & CONFIG_MEDIAMASK) >> CONFIG_MEDIAMASK_SHIFT;
req->ifm_active = ep_default_to_media[config1];
@ -1056,7 +1056,7 @@ readcheck:
if ((status & S_INTR_LATCH) == 0) {
/*
* No interrupt, read the packet and continue
* Is this supposed to happen? Is my motherboard
* Is this supposed to happen? Is my motherboard
* completely busted?
*/
epread(sc);
@ -1227,7 +1227,7 @@ epintr(void *arg)
eptxstat(sc);
epstart(ifp);
}
}
}
/* no more interrupts */
return (ret);

6
sys/dev/ic/elink3reg.h
View file

@ -104,7 +104,7 @@
#define EP_W2_ADDR_1 0x01
#define EP_W2_ADDR_0 0x00
/*
/*
* Window 3 registers. FIFO Management.
*/
/* Read */
@ -234,7 +234,7 @@
#define SET_TX_AVAIL_THRESH (u_short) (0x12<<11)
#define SET_TX_START_THRESH (u_short) (0x13<<11)
#define START_DMA (u_short) (0x14<<11) /* busmaster-only */
# define START_DMA_TX (START_DMA | 0x0)) /* busmaster-only */
# define START_DMA_TX (START_DMA | 0x0) /* busmaster-only */
# define START_DMA_RX (START_DMA | 0x1) /* busmaster-only */
#define STATS_ENABLE (u_short) (0x15<<11)
#define STATS_DISABLE (u_short) (0x16<<11)
@ -350,7 +350,7 @@
* 4-5: ram speed
* 6-7: rom size
* 8-15: reserved
*
*
* 16-17: ram split (5:3, 3:1, or 1:1).
* 18-19: reserved
* 20-22: selected media type

16
sys/dev/ic/fxp.c
View file

@ -283,7 +283,7 @@ int
fxp_activate(struct device *self, int act)
{
struct fxp_softc *sc = (struct fxp_softc *)self;
struct ifnet *ifp = &sc->sc_arpcom.ac_if;
struct ifnet *ifp = &sc->sc_arpcom.ac_if;
int rv = 0;
switch (act) {
@ -794,7 +794,7 @@ fxp_intr(void *arg)
while ((statack = CSR_READ_2(sc, FXP_CSR_SCB_STATUS)) &
FXP_SCB_STATACK_MASK) {
claimed = 1;
rnr = (statack & (FXP_SCB_STATACK_RNR |
rnr = (statack & (FXP_SCB_STATACK_RNR |
FXP_SCB_STATACK_SWI)) ? 1 : 0;
/*
* First ACK all the interrupts in this pass.
@ -1414,7 +1414,7 @@ fxp_init(void *xsc)
ifq_clr_oactive(&ifp->if_snd);
/*
* Request a software generated interrupt that will be used to
* Request a software generated interrupt that will be used to
* (re)start the RU processing. If we direct the chip to start
* receiving from the start of queue now, instead of letting the
* interrupt handler first process all received packets, we run
@ -1707,7 +1707,7 @@ fxp_mc_setup(struct fxp_softc *sc, int doit)
if (doit == 0)
return;
/*
/*
* Initialize multicast setup descriptor.
*/
mcsp->cb_status = htole16(0);
@ -1763,13 +1763,13 @@ struct ucode {
} const ucode_table[] = {
{ FXP_REV_82558_A4, D101_CPUSAVER_DWORD,
0, 0,
"fxp-d101a" },
"fxp-d101a" },
{ FXP_REV_82558_B0, D101_CPUSAVER_DWORD,
0, 0,
"fxp-d101b0" },
{ FXP_REV_82559_A0, D101M_CPUSAVER_DWORD,
{ FXP_REV_82559_A0, D101M_CPUSAVER_DWORD,
D101M_CPUSAVER_BUNDLE_MAX_DWORD, D101M_CPUSAVER_MIN_SIZE_DWORD,
"fxp-d101ma" },
@ -1792,7 +1792,7 @@ struct ucode {
{ FXP_REV_82551_10, D102_E_CPUSAVER_DWORD,
D102_E_CPUSAVER_BUNDLE_MAX_DWORD, D102_E_CPUSAVER_MIN_SIZE_DWORD,
"fxp-d102e" },
{ 0, 0,
0, 0,
NULL }
@ -1862,7 +1862,7 @@ reloadit:
if (uc->min_size_mask_offset)
*((u_int16_t *)&cbp->ucode[uc->min_size_mask_offset]) =
htole16(sc->sc_min_size_mask);
FXP_UCODE_SYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
/*

4
sys/dev/ic/fxpreg.h
View file

@ -263,7 +263,7 @@ struct fxp_stats {
};
#define FXP_STATS_DUMP_COMPLETE 0xa005
#define FXP_STATS_DR_COMPLETE 0xa007
/*
* Serial EEPROM control register bits
*/
@ -343,7 +343,7 @@ struct fxp_cb_ucode {
volatile u_int32_t ucode[MAXUCODESIZE];
};
/*
/*
* Chip revision values.
*/
#define FXP_REV_82557_A 0 /* 82557 A */

20
sys/dev/ic/fxpvar.h
View file

@ -1,19 +1,19 @@
/* $OpenBSD: fxpvar.h,v 1.38 2022/01/09 05:42:38 jsg Exp $ */
/* $NetBSD: if_fxpvar.h,v 1.1 1997/06/05 02:01:58 thorpej Exp $ */
/*
/*
* Copyright (c) 1995, David Greenman
* All rights reserved.
*
*
* Modifications to support NetBSD:
* Copyright (c) 1997 Jason R. Thorpe. All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice unmodified, this list of conditions, and the following
* disclaimer.
* disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
@ -46,7 +46,7 @@
#define FXP_NTXCB 128
/*
* Minimum and maximum number of receive frame area buffers.
* Minimum and maximum number of receive frame area buffers.
*/
#define FXP_NRFABUFS_MIN 4
#define FXP_NRFABUFS_MAX 64 /* These are large so choose wisely. */
@ -57,7 +57,7 @@
* microcode is loaded.
*/
#ifndef FXP_INT_DELAY
#define FXP_INT_DELAY 128
#define FXP_INT_DELAY 128
#endif
/*
@ -69,7 +69,7 @@
#define FXP_BUNDLE_MAX 16
#endif
/*
/*
* Bit-mask describing minimum size frame that will be bundled.
* This is only effective if the Intel microcode is loaded.
* This is not present in all microcode revisions. Disabled by default,
@ -137,7 +137,7 @@ struct fxp_softc {
struct fxp_ctrl *sc_ctrl;
bus_dmamap_t sc_rxmaps[FXP_NRFABUFS_MAX];
int sc_rxfree;
u_int32_t sc_revision; /* chip revision */
u_int32_t sc_revision; /* chip revision */
u_int16_t sc_int_delay; /* interrupt delay value for ucode */
u_int16_t sc_bundle_max; /* max # frames per interrupt (ucode) */
u_int16_t sc_min_size_mask; /* bit-mask describing the minimum
@ -190,7 +190,7 @@ void fxp_wakeup(struct fxp_softc *);
#define FXP_STATS_SYNC(sc, p) \
bus_dmamap_sync((sc)->sc_dmat, (sc)->tx_cb_map, \
offsetof(struct fxp_ctrl, stats), sizeof(struct fxp_stats), (p))
offsetof(struct fxp_ctrl, stats), sizeof(struct fxp_stats), (p))
#define FXP_MBUF_SYNC(sc, m, p) \
bus_dmamap_sync((sc)->sc_dmat, (m), 0, (m)->dm_mapsize, (p))

2
sys/dev/ic/gdtreg.h
View file

@ -84,7 +84,7 @@
#define GDT_RELEASE_ALL 17 /* release all devices */
#define GDT_RESET_BUS 18 /* reset bus */
#define GDT_SCAN_START 19 /* start device scan */
#define GDT_SCAN_END 20 /* stop device scan */
#define GDT_SCAN_END 20 /* stop device scan */
/* IOCTL command defines */
#define GDT_SCSI_DR_INFO 0x00 /* SCSI drive info */

2
sys/dev/ic/gdtvar.h
View file

@ -82,7 +82,7 @@ struct gdt_ccb {
u_int8_t gc_cmd_index;
u_int8_t gc_flags;
#define GDT_GCF_CMD_MASK 0x3
#define GDT_GCF_UNUSED 0
#define GDT_GCF_UNUSED 0
#define GDT_GCF_INTERNAL 1
#define GDT_GCF_SCREEN 2
#define GDT_GCF_SCSI 3

2
sys/dev/ic/gemreg.h
View file

@ -441,7 +441,7 @@
#define GEM_MII_SLINK_STATUS 0x905c /* serial link status */
/* GEM_MII_CONTROL bits */
/*
/*
* DO NOT TOUCH THIS REGISTER ON ERI -- IT HARD HANGS.
*/
#define GEM_MII_CONTROL_RESET 0x00008000

12
sys/dev/ic/hme.c
View file

@ -41,7 +41,7 @@
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/mbuf.h>
#include <sys/mbuf.h>
#include <sys/syslog.h>
#include <sys/socket.h>
#include <sys/device.h>
@ -220,7 +220,7 @@ hme_config(struct hme_softc *sc)
/* Initialize ifmedia structures and MII info */
mii->mii_ifp = ifp;
mii->mii_readreg = hme_mii_readreg;
mii->mii_readreg = hme_mii_readreg;
mii->mii_writereg = hme_mii_writereg;
mii->mii_statchg = hme_mii_statchg;
@ -533,7 +533,7 @@ hme_init(struct hme_softc *sc)
/*
* Init seed for backoff
* (source suggested by manual: low 10 bits of MAC address)
*/
*/
v = ((ea[4] << 8) | ea[5]) & 0x3fff;
bus_space_write_4(t, mac, HME_MACI_RANDSEED, v);
@ -980,7 +980,7 @@ hme_mii_readreg(struct device *self, int phy, int reg)
v |= HME_MIF_CFG_PHY;
bus_space_write_4(t, mif, HME_MIFI_CFG, v);
/* Enable MII drivers on external transceiver */
/* Enable MII drivers on external transceiver */
v = xif_cfg = bus_space_read_4(t, mac, HME_MACI_XIF);
if (phy == HME_PHYAD_EXTERNAL)
v |= HME_MAC_XIF_MIIENABLE;
@ -1037,7 +1037,7 @@ hme_mii_writereg(struct device *self, int phy, int reg, int val)
v |= HME_MIF_CFG_PHY;
bus_space_write_4(t, mif, HME_MIFI_CFG, v);
/* Enable MII drivers on external transceiver */
/* Enable MII drivers on external transceiver */
v = xif_cfg = bus_space_read_4(t, mac, HME_MACI_XIF);
if (phy == HME_PHYAD_EXTERNAL)
v |= HME_MAC_XIF_MIIENABLE;
@ -1233,7 +1233,7 @@ hme_iff(struct hme_softc *sc)
ETHER_FIRST_MULTI(step, ac, enm);
while (enm != NULL) {
crc = ether_crc32_le(enm->enm_addrlo,
ETHER_ADDR_LEN) >> 26;
ETHER_ADDR_LEN) >> 26;
/* Set the corresponding bit in the filter. */
hash[crc >> 4] |= 1 << (crc & 0xf);

26
sys/dev/ic/i82365.c
View file

@ -465,7 +465,7 @@ pcic_event_process(struct pcic_handle *h, struct pcic_event *pe)
}
}
splx(s);
DPRINTF(("%s: insertion event\n", h->ph_parent->dv_xname));
pcic_attach_card(h);
break;
@ -824,7 +824,7 @@ pcic_power(int why, void *arg)
}
}
int
int
pcic_chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size,
struct pcmcia_mem_handle *pcmhp)
{
@ -862,7 +862,7 @@ pcic_chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size,
pcmhp->size = size;
pcmhp->mhandle = mhandle;
pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE;
DPRINTF(("pcic_chip_mem_alloc bus addr 0x%lx+0x%lx\n",
(u_long) addr, (u_long) size));
@ -873,7 +873,7 @@ pcic_chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size,
return (1);
}
void
void
pcic_chip_mem_free(pcmcia_chipset_handle_t pch, struct pcmcia_mem_handle *pcmhp)
{
struct pcic_handle *h = (struct pcic_handle *) pch;
@ -938,7 +938,7 @@ static struct mem_map_index_st {
},
};
void
void
pcic_chip_do_mem_map(struct pcic_handle *h, int win)
{
int reg;
@ -992,7 +992,7 @@ pcic_chip_do_mem_map(struct pcic_handle *h, int win)
#endif
}
int
int
pcic_chip_mem_map(pcmcia_chipset_handle_t pch, int kind, bus_addr_t card_addr,
bus_size_t size, struct pcmcia_mem_handle *pcmhp, bus_size_t *offsetp,
int *windowp)
@ -1057,7 +1057,7 @@ pcic_chip_mem_map(pcmcia_chipset_handle_t pch, int kind, bus_addr_t card_addr,
return (0);
}
void
void
pcic_chip_mem_unmap(pcmcia_chipset_handle_t pch, int window)
{
struct pcic_handle *h = (struct pcic_handle *) pch;
@ -1073,7 +1073,7 @@ pcic_chip_mem_unmap(pcmcia_chipset_handle_t pch, int window)
h->memalloc &= ~(1 << window);
}
int
int
pcic_chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start,
bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp)
{
@ -1158,7 +1158,7 @@ pcic_chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start,
return (0);
}
void
void
pcic_chip_io_free(pcmcia_chipset_handle_t pch, struct pcmcia_io_handle *pcihp)
{
bus_space_tag_t iot = pcihp->iot;
@ -1215,7 +1215,7 @@ static struct io_map_index_st {
},
};
void
void
pcic_chip_do_io_map(struct pcic_handle *h, int win)
{
int reg;
@ -1243,7 +1243,7 @@ pcic_chip_do_io_map(struct pcic_handle *h, int win)
pcic_write(h, PCIC_ADDRWIN_ENABLE, reg);
}
int
int
pcic_chip_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset,
bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp)
{
@ -1288,7 +1288,7 @@ pcic_chip_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset,
return (0);
}
void
void
pcic_chip_io_unmap(pcmcia_chipset_handle_t pch, int window)
{
struct pcic_handle *h = (struct pcic_handle *) pch;
@ -1337,7 +1337,7 @@ pcic_chip_socket_enable(pcmcia_chipset_handle_t pch)
pcic_write(h, PCIC_PWRCTL, 0);
/*
/*
* wait 300ms until power fails (Tpf). Then, wait 100ms since
* we are changing Vcc (Toff).
*/

2
sys/dev/ic/i8237reg.h
View file

@ -11,6 +11,6 @@
#define DMA37MD_LOOP 0x10 /* auto-initialize mode */
#define DMA37MD_SINGLE 0x40 /* single pass mode */
#define DMA37MD_CASCADE 0xc0 /* cascade mode */
#define DMA37SM_CLEAR 0x00 /* clear mask bit */
#define DMA37SM_SET 0x04 /* set mask bit */

2
sys/dev/ic/i82596reg.h
View file

@ -270,7 +270,7 @@ struct __ie_recv_buf_desc {
* All commands share this in common.
*-
struct __ie_cmd_common {
u_int16_t ie_cmd_status; // status of this command
u_int16_t ie_cmd_status; // status of this command
u_int16_t ie_cmd_cmd; // command word
u_int16_t ie_cmd_link; // link to next command
} __packed;

2
sys/dev/ic/i82596var.h
View file

@ -278,7 +278,7 @@ struct ie_softc {
int i82596_intr(void *);
int i82596_probe(struct ie_softc *);
int i82596_proberam(struct ie_softc *);
void i82596_attach(struct ie_softc *, const char *, u_int8_t *,
void i82596_attach(struct ie_softc *, const char *, u_int8_t *,
uint64_t *, int, uint64_t);
int i82596_start_cmd(struct ie_softc *, int, int, int, int);

2
sys/dev/ic/i82802reg.h
View file

@ -29,7 +29,7 @@
/*
* Intel 82802AB/82802AC Firmware Hub
*
* see: ftp://download.intel.com/design/chipsets/datashts/29065804.pdf
* see: ftp://download.intel.com/design/chipsets/datashts/29065804.pdf
* and http://www.intel.com/Assets/PDF/manual/298029.pdf
*/

2
sys/dev/ic/ibm561.c
View file

@ -80,7 +80,7 @@ struct ramdac_funcs ibm561_funcsstruct = {
NULL, /* check_curcmap; not needed */
NULL, /* set_curcmap; not needed */
NULL, /* get_curcmap; not needed */
ibm561_set_dotclock,
ibm561_set_dotclock,
};
/*

16
sys/dev/ic/if_wi.c
View file

@ -157,7 +157,7 @@ STATIC int wi_get_txpower(struct wi_softc *, struct ieee80211_txpower *);
STATIC int wi_get_debug(struct wi_softc *, struct wi_req *);
STATIC int wi_set_debug(struct wi_softc *, struct wi_req *);
STATIC void wi_do_hostencrypt(struct wi_softc *, caddr_t, int);
STATIC void wi_do_hostencrypt(struct wi_softc *, caddr_t, int);
STATIC int wi_do_hostdecrypt(struct wi_softc *, caddr_t, int);
STATIC int wi_alloc_nicmem_io(struct wi_softc *, int, int *);
@ -674,7 +674,7 @@ wi_rxeof(struct wi_softc *sc)
"wi_status=0x%x)\n", sc->sc_dev.dv_xname,
rxlen, letoh16(rx_frame.wi_status));
m_freem(m);
ifp->if_ierrors++;
ifp->if_ierrors++;
return;
}
@ -776,7 +776,7 @@ wi_rxeof(struct wi_softc *sc)
if (sc->sc_ic.ic_if.if_flags & IFF_DEBUG)
printf(WI_PRT_FMT ": Error decrypting incoming packet.\n", WI_PRT_ARG(sc));
m_freem(m);
ifp->if_ierrors++;
ifp->if_ierrors++;
return;
}
len -= IEEE80211_WEP_IVLEN +
@ -900,7 +900,7 @@ wi_update_stats(struct wi_softc *sc)
if (sc->wi_flags & WI_FLAGS_BUS_USB) {
wi_read_data(sc, id, 4 + i*2, (char *)&t, 2);
t = letoh16(t);
} else
} else
t = CSR_READ_2(sc, WI_DATA1);
#ifdef WI_HERMES_STATS_WAR
if (t > 0xF000)
@ -2046,7 +2046,7 @@ wi_scan_timeout(void *arg)
WI_PRT_ARG(sc), sc->wi_scan_lock);
/* Wakeup the userland */
wakeup(&sc->wi_scan_lock);
wakeup(&sc->wi_scan_lock);
sc->wi_scan_lock = 0;
}
@ -2566,7 +2566,7 @@ wi_detach(struct wi_softc *sc)
if (ifp->if_flags & IFF_RUNNING)
wi_stop(sc);
if (sc->wi_flags & WI_FLAGS_ATTACHED) {
sc->wi_flags &= ~WI_FLAGS_ATTACHED;
}
@ -2966,7 +2966,7 @@ wi_set_txpower(struct wi_softc *sc, struct ieee80211_txpower *txpower)
sc->wi_flags |= WI_FLAGS_TXPOWER;
sc->wi_txpower = txpower->i_val;
}
}
}
/* Set ALC */
cmd = WI_CMD_DEBUG | (WI_DEBUG_CONFBITS << 8);
@ -3035,7 +3035,7 @@ wi_get_txpower(struct wi_softc *sc, struct ieee80211_txpower *txpower)
txpower->i_mode = IEEE80211_TXPOWER_MODE_FIXED;
else
txpower->i_mode = IEEE80211_TXPOWER_MODE_AUTO;
return (0);
}

2
sys/dev/ic/if_wi_hostap.c
View file

@ -640,7 +640,7 @@ wihap_auth_req(struct wi_softc *sc, struct wi_frame *rxfrm,
for (i = 0; i < 32; i++)
challenge[i] = sta->challenge[i] =
arc4random();
if (sc->sc_ic.ic_if.if_flags & IFF_DEBUG)
printf("\tchallenge: 0x%x 0x%x ...\n",
challenge[0], challenge[1]);

2
sys/dev/ic/if_wi_ieee.h
View file

@ -355,7 +355,7 @@ struct wi_apinfo {
int quality; /* Quality */
int namelen; /* Length of SSID string */
char name[32]; /* SSID string */
int capinfo; /* Capability info. */
int capinfo; /* Capability info. */
int interval; /* BSS Beacon Interval */
int rate; /* Data Rate */
};

2
sys/dev/ic/iosf.c
View file

@ -157,7 +157,7 @@ iosf_mbi_mdr_modify(struct iosf_mbi *mbi, uint8_t port, uint8_t op,
mdr = (*mbi->mbi_mdr_rd)(mbi, mcr, mcrx);
CLR(mdr, mask);
SET(mdr, bits & mask);
SET(mdr, bits & mask);
(*mbi->mbi_mdr_wr)(mbi, mcr, mcrx, mdr);
mtx_leave(&iosf_mbi_mtx);

16
sys/dev/ic/lemac.c
View file

@ -349,17 +349,17 @@ lemac_read_macaddr(unsigned char *hwaddr, const bus_space_tag_t iot,
{
int cksum, rom_cksum;
unsigned char addrbuf[6];
if (!skippat) {
int idx, idx2, found, octet;
static u_char testpat[] = {
0xFF, 0, 0x55, 0xAA, 0xFF, 0, 0x55, 0xAA
};
idx2 = found = 0;
for (idx = 0; idx < 32; idx++) {
octet = bus_space_read_1(iot, ioh, ioreg);
if (octet == testpat[idx2]) {
if (++idx2 == sizeof(testpat)) {
++found;
@ -423,7 +423,7 @@ lemac_read_macaddr(unsigned char *hwaddr, const bus_space_tag_t iot,
rom_cksum = bus_space_read_1(iot, ioh, ioreg);
rom_cksum |= bus_space_read_1(iot, ioh, ioreg) << 8;
if (cksum != rom_cksum)
return (-1);
return (0);
@ -489,7 +489,7 @@ lemac_multicast_filter(struct lemac_softc *sc)
sc->sc_if.if_flags &= ~IFF_ALLMULTI;
}
/*
/*
* Do a hard reset of the board;
*/
void
@ -512,7 +512,7 @@ lemac_reset(struct lemac_softc *const sc)
* is important because functions hereafter may rely on information
* read from the EEPROM.
*/
if ((data = lemac_read_eeprom(sc)) != LEMAC_EEP_CKSUM) {
if ((data = lemac_read_eeprom(sc)) != LEMAC_EEP_CKSUM) {
printf("%s: reset: EEPROM checksum failed (0x%x)\n",
sc->sc_if.if_xname, data);
return;
@ -621,7 +621,7 @@ lemac_init(struct lemac_softc *const sc)
}
}
void
void
lemac_ifstart(struct ifnet *ifp)
{
struct lemac_softc *const sc = LEMAC_IFP_TO_SOFTC(ifp);
@ -976,7 +976,7 @@ lemac_ifattach(struct lemac_softc *sc)
lemac_read_macaddr(sc->sc_arpcom.ac_enaddr, sc->sc_iot, sc->sc_ioh,
LEMAC_REG_APD, 0);
printf(": %s\n", sc->sc_prodname);
printf("%s: address %s, %dKB RAM, %s\n", ifp->if_xname,

2
sys/dev/ic/lemacreg.h
View file

@ -133,7 +133,7 @@
/* Transmit Done Queue Status Definitions */
#define LEMAC_TDQ_COL 0x03 /* Collision Mask */
#define LEMAC_TDQ_COL 0x03 /* Collision Mask */
#define LEMAC_TDQ_NOCOL 0x00 /* No Collisions */
#define LEMAC_TDQ_ONECOL 0x01 /* One Collision */
#define LEMAC_TDQ_MULCOL 0x02 /* Multiple Collisions */

6
sys/dev/ic/lm78.c
View file

@ -159,8 +159,8 @@ const struct lm_sensor w83627ehf_sensors[] = {
{ NULL }
};
/*
* w83627dhg is almost identical to w83627ehf, except that
/*
* w83627dhg is almost identical to w83627ehf, except that
* it has 9 instead of 10 voltage sensors
*/
const struct lm_sensor w83627dhg_sensors[] = {
@ -859,7 +859,7 @@ wb_refresh_fanrpm(struct lm_softc *sc, int n)
struct ksensor *sensor = &sc->sensors[n];
int fan, data, divisor = 0;
/*
/*
* This is madness; the fan divisor bits are scattered all
* over the place.
*/

2
sys/dev/ic/lm78var.h
View file

@ -26,7 +26,7 @@
#define LM_FAN2 0x29 /* FAN2 reading */
#define LM_FAN3 0x2a /* FAN3 reading */
#define LM_CONFIG 0x40 /* Configuration */
#define LM_CONFIG 0x40 /* Configuration */
#define LM_ISR1 0x41 /* Interrupt Status 1 */
#define LM_ISR2 0x42 /* Interrupt Status 2 */
#define LM_SMI1 0x43 /* SMI# Mask 1 */

28
sys/dev/ic/lpt.c
View file

@ -16,25 +16,25 @@
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This software is a component of "386BSD" developed by
* This software is a component of "386BSD" developed by
* William F. Jolitz, TeleMuse.
* 4. Neither the name of the developer nor the name "386BSD"
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS A COMPONENT OF 386BSD DEVELOPED BY WILLIAM F. JOLITZ
* AND IS INTENDED FOR RESEARCH AND EDUCATIONAL PURPOSES ONLY. THIS
* SOFTWARE SHOULD NOT BE CONSIDERED TO BE A COMMERCIAL PRODUCT.
* THE DEVELOPER URGES THAT USERS WHO REQUIRE A COMMERCIAL PRODUCT
* THIS SOFTWARE IS A COMPONENT OF 386BSD DEVELOPED BY WILLIAM F. JOLITZ
* AND IS INTENDED FOR RESEARCH AND EDUCATIONAL PURPOSES ONLY. THIS
* SOFTWARE SHOULD NOT BE CONSIDERED TO BE A COMMERCIAL PRODUCT.
* THE DEVELOPER URGES THAT USERS WHO REQUIRE A COMMERCIAL PRODUCT
* NOT MAKE USE OF THIS WORK.
*
* FOR USERS WHO WISH TO UNDERSTAND THE 386BSD SYSTEM DEVELOPED
* BY WILLIAM F. JOLITZ, WE RECOMMEND THE USER STUDY WRITTEN
* REFERENCES SUCH AS THE "PORTING UNIX TO THE 386" SERIES
* (BEGINNING JANUARY 1991 "DR. DOBBS JOURNAL", USA AND BEGINNING
* JUNE 1991 "UNIX MAGAZIN", GERMANY) BY WILLIAM F. JOLITZ AND
* LYNNE GREER JOLITZ, AS WELL AS OTHER BOOKS ON UNIX AND THE
* ON-LINE 386BSD USER MANUAL BEFORE USE. A BOOK DISCUSSING THE INTERNALS
* BY WILLIAM F. JOLITZ, WE RECOMMEND THE USER STUDY WRITTEN
* REFERENCES SUCH AS THE "PORTING UNIX TO THE 386" SERIES
* (BEGINNING JANUARY 1991 "DR. DOBBS JOURNAL", USA AND BEGINNING
* JUNE 1991 "UNIX MAGAZIN", GERMANY) BY WILLIAM F. JOLITZ AND
* LYNNE GREER JOLITZ, AS WELL AS OTHER BOOKS ON UNIX AND THE
* ON-LINE 386BSD USER MANUAL BEFORE USE. A BOOK DISCUSSING THE INTERNALS
* OF 386BSD ENTITLED "386BSD FROM THE INSIDE OUT" WILL BE AVAILABLE LATE 1992.
*
* THIS SOFTWARE IS PROVIDED BY THE DEVELOPER ``AS IS'' AND
@ -358,7 +358,7 @@ lptpushbytes(struct lpt_softc *sc)
return 0;
}
/*
/*
* Copy a line from user space to a local buffer, then call putc to get the
* chars moved to the output queue.
*/
@ -448,7 +448,7 @@ lpt_activate(struct device *self, int act)
lpt_control, LPC_SELECT);
delay(100);
}
bus_space_write_1(sc->sc_iot, sc->sc_ioh, lpt_control,
LPC_SELECT | LPC_NINIT);
@ -470,6 +470,6 @@ lpt_activate(struct device *self, int act)
fail:
break;
}
return (0);
}

22
sys/dev/ic/lptvar.h
View file

@ -16,25 +16,25 @@
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This software is a component of "386BSD" developed by
* This software is a component of "386BSD" developed by
* William F. Jolitz, TeleMuse.
* 4. Neither the name of the developer nor the name "386BSD"
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS A COMPONENT OF 386BSD DEVELOPED BY WILLIAM F. JOLITZ
* AND IS INTENDED FOR RESEARCH AND EDUCATIONAL PURPOSES ONLY. THIS
* SOFTWARE SHOULD NOT BE CONSIDERED TO BE A COMMERCIAL PRODUCT.
* THE DEVELOPER URGES THAT USERS WHO REQUIRE A COMMERCIAL PRODUCT
* THIS SOFTWARE IS A COMPONENT OF 386BSD DEVELOPED BY WILLIAM F. JOLITZ
* AND IS INTENDED FOR RESEARCH AND EDUCATIONAL PURPOSES ONLY. THIS
* SOFTWARE SHOULD NOT BE CONSIDERED TO BE A COMMERCIAL PRODUCT.
* THE DEVELOPER URGES THAT USERS WHO REQUIRE A COMMERCIAL PRODUCT
* NOT MAKE USE OF THIS WORK.
*
* FOR USERS WHO WISH TO UNDERSTAND THE 386BSD SYSTEM DEVELOPED
* BY WILLIAM F. JOLITZ, WE RECOMMEND THE USER STUDY WRITTEN
* REFERENCES SUCH AS THE "PORTING UNIX TO THE 386" SERIES
* (BEGINNING JANUARY 1991 "DR. DOBBS JOURNAL", USA AND BEGINNING
* JUNE 1991 "UNIX MAGAZIN", GERMANY) BY WILLIAM F. JOLITZ AND
* LYNNE GREER JOLITZ, AS WELL AS OTHER BOOKS ON UNIX AND THE
* ON-LINE 386BSD USER MANUAL BEFORE USE. A BOOK DISCUSSING THE INTERNALS
* BY WILLIAM F. JOLITZ, WE RECOMMEND THE USER STUDY WRITTEN
* REFERENCES SUCH AS THE "PORTING UNIX TO THE 386" SERIES
* (BEGINNING JANUARY 1991 "DR. DOBBS JOURNAL", USA AND BEGINNING
* JUNE 1991 "UNIX MAGAZIN", GERMANY) BY WILLIAM F. JOLITZ AND
* LYNNE GREER JOLITZ, AS WELL AS OTHER BOOKS ON UNIX AND THE
* ON-LINE 386BSD USER MANUAL BEFORE USE. A BOOK DISCUSSING THE INTERNALS
* OF 386BSD ENTITLED "386BSD FROM THE INSIDE OUT" WILL BE AVAILABLE LATE 1992.
*
* THIS SOFTWARE IS PROVIDED BY THE DEVELOPER ``AS IS'' AND

6
sys/dev/ic/lsi64854.c
View file

@ -307,7 +307,7 @@ lsi64854_setup(struct lsi64854_softc *sc, caddr_t *addr, size_t *len,
DPRINTF(LDB_ANY, ("dma_setup: dmasize = %ld\n", (long)sc->sc_dmasize));
/*
* XXX what length?
* XXX what length?
*/
if (sc->sc_rev == DMAREV_HME) {
@ -322,7 +322,7 @@ lsi64854_setup(struct lsi64854_softc *sc, caddr_t *addr, size_t *len,
sc->sc_dvmaaddr = *sc->sc_dmaaddr;
if (bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap,
*sc->sc_dmaaddr, sc->sc_dmasize,
NULL /* kernel address */,
NULL /* kernel address */,
BUS_DMA_NOWAIT | BUS_DMA_STREAMING))
panic("%s: cannot allocate DVMA address",
sc->sc_dev.dv_xname);
@ -563,7 +563,7 @@ lsi64854_setup_pp(struct lsi64854_softc *sc, caddr_t *addr, size_t *len,
sc->sc_dvmaaddr = *sc->sc_dmaaddr;
if (bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap,
*sc->sc_dmaaddr, sc->sc_dmasize,
NULL /* kernel address */,
NULL /* kernel address */,
BUS_DMA_NOWAIT/*|BUS_DMA_COHERENT*/))
panic("%s: pp cannot allocate DVMA address",
sc->sc_dev.dv_xname);

2
sys/dev/ic/malo.c
View file

@ -1922,7 +1922,7 @@ malo_hexdump(void *buf, int len)
printf("%4i:", i);
l = min(sizeof(b), len - i);
bcopy(buf + i, b, l);
for (j = 0; j < sizeof(b); j++) {
if (j % 2 == 0)
printf(" ");

4
sys/dev/ic/max2820reg.h
View file

@ -163,7 +163,7 @@
#define MAX2820_RECEIVE_1C_DEFAULT LSHIFT(7, MAX2820_RECEIVE_1C_MASK)
#define MAX2820_RECEIVE_DL_DEFAULT LSHIFT(1, MAX2820_RECEIVE_DL_MASK)
#define MAX2820_RECEIVE_SF_DEFAULT LSHIFT(0, MAX2820_RECEIVE_SF)
#define MAX2820_RECEIVE_BW_DEFAULT MAX2820_RECEIVE_BW_7_5MHZ
#define MAX2820_RECEIVE_BW_DEFAULT MAX2820_RECEIVE_BW_7_5MHZ
#define MAX2820A_RECEIVE 4 /* Receiver Settings Register,
* MAX2820A/MAX2821A
@ -172,7 +172,7 @@
#define MAX2820A_RECEIVE_2C_MASK 0xe00
#define MAX2820A_RECEIVE_2C_DEFAULT LSHIFT(7, MAX2820A_RECEIVE_2C_MASK)
/* VGA DC Offset Nulling Parameter 1 */
#define MAX2820A_RECEIVE_1C_MASK 0x1c0
#define MAX2820A_RECEIVE_1C_MASK 0x1c0
#define MAX2820A_RECEIVE_1C_DEFAULT LSHIFT(7, MAX2820A_RECEIVE_1C_MASK)
#define MAX2820A_RECEIVE_RSVD0_MASK 0x38
#define MAX2820A_RECEIVE_RSVD0_DEFAULT LSHIFT(2, MAX2820A_RECEIVE_RSVD0_MASK)

10
sys/dev/ic/mc146818reg.h
View file

@ -4,17 +4,17 @@
/*
* Copyright (c) 1995 Carnegie-Mellon University.
* All rights reserved.
*
*
* Permission to use, copy, modify and distribute this software and
* its documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU

4
sys/dev/ic/mc6845.h
View file

@ -20,8 +20,8 @@
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL

2
sys/dev/ic/mpi.c
View file

@ -1358,7 +1358,7 @@ mpi_scsi_cmd(struct scsi_xfer *xs)
if (sc->sc_porttype != MPI_PORTFACTS_PORTTYPE_SCSI &&
(link->quirks & SDEV_NOTAGS))
io->tagging = MPI_SCSIIO_ATTR_UNTAGGED;
else
else
io->tagging = MPI_SCSIIO_ATTR_SIMPLE_Q;
memcpy(io->cdb, &xs->cmd, xs->cmdlen);

2
sys/dev/ic/mtd8xx.c
View file

@ -908,7 +908,7 @@ mtd_rxeof(struct mtd_softc *sc)
}
}
/* No errors; receive the packet. */
/* No errors; receive the packet. */
total_len -= ETHER_CRC_LEN;
bus_dmamap_sync(sc->sc_dmat, sc->mtd_cdata.mtd_rx_chain[i].sd_map,

2
sys/dev/ic/ncr53c9xreg.h
View file

@ -196,7 +196,7 @@
/*
The following registers are only on the ESP406/FAS408. The
documentation refers to them as "Control Register Set #1".
These are the registers that are visible when bit 7 of
These are the registers that are visible when bit 7 of
register 0x0d is set. This bit is common to both register sets.
*/

4
sys/dev/ic/nvmereg.h
View file

@ -238,8 +238,8 @@ struct nvme_cqe {
#define NVM_ADMIN_DEL_IOSQ 0x00 /* Delete I/O Submission Queue */
#define NVM_ADMIN_ADD_IOSQ 0x01 /* Create I/O Submission Queue */
#define NVM_ADMIN_GET_LOG_PG 0x02 /* Get Log Page */
#define NVM_ADMIN_DEL_IOCQ 0x04 /* Delete I/O Completion Queue */
#define NVM_ADMIN_ADD_IOCQ 0x05 /* Create I/O Completion Queue */
#define NVM_ADMIN_DEL_IOCQ 0x04 /* Delete I/O Completion Queue */
#define NVM_ADMIN_ADD_IOCQ 0x05 /* Create I/O Completion Queue */
#define NVM_ADMIN_IDENTIFY 0x06 /* Identify */
#define NVM_ADMIN_ABORT 0x08 /* Abort */
#define NVM_ADMIN_SET_FEATURES 0x09 /* Set Features */

4
sys/dev/ic/osiopvar.h
View file

@ -69,8 +69,8 @@
#define osiop_read_4(sc, reg) \
bus_space_read_4((sc)->sc_bst, (sc)->sc_reg, reg)
#define osiop_write_4(sc, reg, val) \
bus_space_write_4((sc)->sc_bst, (sc)->sc_reg, reg, val)
bus_space_write_4((sc)->sc_bst, (sc)->sc_reg, reg, val)
/*
* The largest single request will be MAXPHYS bytes which will require
* at most MAXPHYS/NBPG+1 chain elements to describe, i.e. if none of

2
sys/dev/ic/p9000.h
View file

@ -161,7 +161,7 @@
/*
* Parameter engine
*/
*/
/* Status register */
#define P9000_PE_STATUS 0x00000000

18
sys/dev/ic/pcdisplay_subr.c
View file

@ -6,17 +6,17 @@
* All rights reserved.
*
* Author: Chris G. Demetriou
*
*
* Permission to use, copy, modify and distribute this software and
* its documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
@ -99,7 +99,7 @@ pcdisplay_cursor(void *id, int on, int row, int col)
else
scr->mem[off] = scr->cursortmp;
}
scr->vc_crow = row;
scr->vc_ccol = col;
@ -175,13 +175,13 @@ pcdisplay_getchar(void *id, int row, int col, struct wsdisplay_charcell *cell)
int off;
int s;
u_int16_t data;
off = row * scr->type->ncols + col;
/* XXX bounds check? */
s = spltty();
if (scr->active)
data = (bus_space_read_2(memt, memh,
data = (bus_space_read_2(memt, memh,
scr->dispoffset + off * 2));
else
data = (scr->mem[off]);

2
sys/dev/ic/pckbcvar.h
View file

@ -45,7 +45,7 @@ typedef int pckbc_slot_t;
* external representation (pckbc_tag_t),
* needed early for console operation
*/
struct pckbc_internal {
struct pckbc_internal {
bus_space_tag_t t_iot;
bus_space_handle_t t_ioh_d, t_ioh_c; /* data port, cmd port */
bus_addr_t t_addr;

12
sys/dev/ic/pgt.c
View file

@ -358,7 +358,7 @@ pgt_load_firmware(struct pgt_softc *sc)
DELAY(PGT_WRITEIO_DELAY);
free(ucode, M_DEVBUF, 0);
return (0);
}
@ -449,7 +449,7 @@ pgt_reset(struct pgt_softc *sc)
DELAY(PGT_WRITEIO_DELAY);
/* await only the initialization interrupt */
pgt_write_4_flush(sc, PGT_REG_INT_EN, PGT_INT_STAT_INIT);
pgt_write_4_flush(sc, PGT_REG_INT_EN, PGT_INT_STAT_INIT);
DELAY(PGT_WRITEIO_DELAY);
return (0);
@ -531,7 +531,7 @@ trying_again:
} else {
/* await all interrupts */
pgt_write_4_flush(sc, PGT_REG_INT_EN,
PGT_INT_STAT_SOURCES);
PGT_INT_STAT_SOURCES);
DELAY(PGT_WRITEIO_DELAY);
ic->ic_if.if_flags |= IFF_RUNNING;
}
@ -678,8 +678,8 @@ pgt_update_intr(struct pgt_softc *sc, int hack)
{
/* priority order */
enum pgt_queue pqs[PGT_QUEUE_COUNT] = {
PGT_QUEUE_MGMT_TX, PGT_QUEUE_MGMT_RX,
PGT_QUEUE_DATA_HIGH_TX, PGT_QUEUE_DATA_HIGH_RX,
PGT_QUEUE_MGMT_TX, PGT_QUEUE_MGMT_RX,
PGT_QUEUE_DATA_HIGH_TX, PGT_QUEUE_DATA_HIGH_RX,
PGT_QUEUE_DATA_LOW_TX, PGT_QUEUE_DATA_LOW_RX
};
struct mbuf *m;
@ -756,7 +756,7 @@ pgt_update_intr(struct pgt_softc *sc, int hack)
/*
* This is the deferred completion for received management frames
* and where we queue network frames for stack input.
* and where we queue network frames for stack input.
*/
dirtycount = sc->sc_dirtyq_count[PGT_QUEUE_MGMT_RX];
while (!TAILQ_EMPTY(&sc->sc_dirtyq[PGT_QUEUE_MGMT_RX])) {

2
sys/dev/ic/pgtreg.h
View file

@ -90,7 +90,7 @@
* set of indices that gives the index (modulo queue size) of the current
* progress in each. Nearly all configuration is done from the management
* queue interface. Almost every structure is little-endian.
*/
*/
enum pgt_queue {
PGT_QUEUE_DATA_LOW_RX = 0,
PGT_QUEUE_DATA_LOW_TX = 1,

2
sys/dev/ic/pgtvar.h
View file

@ -160,7 +160,7 @@ struct pgt_softc {
#define SC_DEBUG_RXFRAG 0x00000200
#define SC_DEBUG_RXETHER 0x00000400
bus_space_tag_t sc_iotag;
bus_space_handle_t sc_iohandle;
bus_space_handle_t sc_iohandle;
bus_dma_tag_t sc_dmat;
bus_dmamap_t sc_cbdmam;

2
sys/dev/ic/ramdac.h
View file

@ -42,7 +42,7 @@ struct ramdac_funcs {
struct ramdac_cookie *(*ramdac_register)(void *,
int (*)(void *, void (*)(void *)),
void (*)(void *, u_int, u_int8_t),
u_int8_t (*)(void *, u_int));
u_int8_t (*)(void *, u_int));
void (*ramdac_init)(struct ramdac_cookie *);
int (*ramdac_set_cmap)(struct ramdac_cookie *,

2
sys/dev/ic/rt2661.c
View file

@ -415,7 +415,7 @@ rt2661_wakeup(void *xsc)
struct ifnet *ifp = &sc->sc_ic.ic_if;
if (ifp->if_flags & IFF_UP)
rt2661_init(ifp);
rt2661_init(ifp);
}
int

4
sys/dev/ic/rt2860.c
View file

@ -2715,7 +2715,7 @@ rt5390_rf_wakeup(struct rt2860_softc *sc)
{
uint32_t tmp;
uint8_t rf;
rf = rt3090_rf_read(sc, 1);
rf |= RT3070_RF_BLOCK | RT3070_PLL_PD | RT3070_RX0_PD |
RT3070_TX0_PD;
@ -3670,7 +3670,7 @@ rt2860_init(struct ifnet *ifp)
printf("%s: could not enable wlan\n",
sc->sc_dev.dv_xname);
rt2860_stop(ifp, 1);
return error;
return error;
}
}

2
sys/dev/ic/rtl80x9reg.h
View file

@ -56,7 +56,7 @@
*/
#define NERTL_RTL3_EECR 0x01 /* EEPROM Command Register */
#define RTL3_EECR_EEM1 0x80 /* EEPROM Operating Mode */
#define RTL3_EECR_EEM0 0x40
#define RTL3_EECR_EEM0 0x40
/* 0 0 Normal operation */
/* 0 1 Auto-load */
/* 1 0 9346 programming */

10
sys/dev/ic/rtl81x9reg.h
View file

@ -211,7 +211,7 @@
#define RL_HWREV_8168GU 0x50800000
#define RL_HWREV_8168H 0x54000000
#define RL_HWREV_8168FP 0x54800000
#define RL_HWREV_8411B 0x5c800000
#define RL_HWREV_8411B 0x5c800000
#define RL_HWREV_8139 0x60000000
#define RL_HWREV_8139A 0x70000000
#define RL_HWREV_8139AG 0x70800000
@ -373,7 +373,7 @@
#define RL_9346_ADDR_LEN 6 /* 93C46 1K: 128x16 */
#define RL_9356_ADDR_LEN 8 /* 93C56 2K: 256x16 */
#define RL_9346_WRITE 0x5
#define RL_9346_READ 0x6
#define RL_9346_ERASE 0x7
@ -495,7 +495,7 @@
#define RL_BUSFREQ_33MHZ 0x00
#define RL_BUSFREQ_66MHZ 0x01
#define RL_BUSWIDTH_32BITS 0x00
#define RL_BUSWIDTH_64BITS 0x08
@ -519,7 +519,7 @@
/* C+ early transmit threshold */
#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */
#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */
/*
* Gigabit PHY access register (8169 only)
@ -772,7 +772,7 @@ struct re_stats {
#define RL_ADDR_LO(y) ((u_int64_t) (y) & 0xFFFFFFFF)
#define RL_ADDR_HI(y) ((u_int64_t) (y) >> 32)
#define RL_JUMBO_FRAMELEN (9 * 1024)
#define RL_JUMBO_FRAMELEN (9 * 1024)
#define RL_JUMBO_MTU_4K \
((4 * 1024) - ETHER_HDR_LEN - ETHER_CRC_LEN - ETHER_VLAN_ENCAP_LEN)
#define RL_JUMBO_MTU_6K \

22
sys/dev/ic/rtsx.c
View file

@ -31,7 +31,7 @@
#include <dev/sdmmc/sdmmcvar.h>
#include <dev/sdmmc/sdmmc_ioreg.h>
/*
/*
* We use three DMA buffers: a command buffer, a data buffer, and a buffer for
* ADMA transfer descriptors which describe scatter-gather (SG) I/O operations.
*
@ -232,7 +232,7 @@ rtsx_attach(struct rtsx_softc *sc, bus_space_tag_t iot,
/* Now handle cards discovered during attachment. */
if (ISSET(sc->flags, RTSX_F_CARD_PRESENT))
rtsx_card_insert(sc);
return 0;
unmap_adma:
@ -729,7 +729,7 @@ rtsx_read(struct rtsx_softc *sc, u_int16_t addr, u_int8_t *val)
{
int tries = 1024;
u_int32_t reg;
WRITE4(sc, RTSX_HAIMR, RTSX_HAIMR_BUSY |
(u_int32_t)((addr & 0x3FFF) << 16));
@ -783,10 +783,10 @@ rtsx_read_phy(struct rtsx_softc *sc, u_int8_t addr, u_int16_t *val)
if (!(rwctl & RTSX_PHY_BUSY))
break;
}
if (timeout == 0)
return ETIMEDOUT;
RTSX_READ(sc, RTSX_PHY_DATA0, &data0);
RTSX_READ(sc, RTSX_PHY_DATA1, &data1);
*val = data0 | (data1 << 8);
@ -811,10 +811,10 @@ rtsx_write_phy(struct rtsx_softc *sc, u_int8_t addr, u_int16_t val)
if (!(rwctl & RTSX_PHY_BUSY))
break;
}
if (timeout == 0)
return ETIMEDOUT;
return 0;
}
@ -837,7 +837,7 @@ rtsx_read_cfg(struct rtsx_softc *sc, u_int8_t func, u_int16_t addr,
if (tries == 0)
return EIO;
RTSX_READ(sc, RTSX_CFGDATA0, &data0);
RTSX_READ(sc, RTSX_CFGDATA1, &data1);
RTSX_READ(sc, RTSX_CFGDATA2, &data2);
@ -880,7 +880,7 @@ rtsx_write_cfg(struct rtsx_softc *sc, u_int8_t func, u_int16_t addr,
if (tries == 0)
return EIO;
return 0;
}
#endif
@ -1050,7 +1050,7 @@ rtsx_xfer(struct rtsx_softc *sc, struct sdmmc_command *cmd, u_int32_t *cmdbuf)
ncmd = 0;
rtsx_hostcmd(cmdbuf, &ncmd, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2,
0xff, cfg2);
0xff, cfg2);
/* Queue commands to configure data transfer size. */
rtsx_hostcmd(cmdbuf, &ncmd,
@ -1262,7 +1262,7 @@ rtsx_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd)
/* Queue commands to set SD command index and argument. */
rtsx_hostcmd(cmdbuf, &ncmd,
RTSX_WRITE_REG_CMD, RTSX_SD_CMD0, 0xff, 0x40 | cmd->c_opcode);
RTSX_WRITE_REG_CMD, RTSX_SD_CMD0, 0xff, 0x40 | cmd->c_opcode);
rtsx_hostcmd(cmdbuf, &ncmd,
RTSX_WRITE_REG_CMD, RTSX_SD_CMD1, 0xff, cmd->c_arg >> 24);
rtsx_hostcmd(cmdbuf, &ncmd,

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