sync code with last improvements from OpenBSD
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4de47ea988
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F42C07F07E2E35B7
142 changed files with 4045 additions and 1295 deletions
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@ -1295,7 +1295,6 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
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void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);
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int amdgpu_device_pci_reset(struct amdgpu_device *adev);
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bool amdgpu_device_need_post(struct amdgpu_device *adev);
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bool amdgpu_sg_display_supported(struct amdgpu_device *adev);
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bool amdgpu_device_pcie_dynamic_switching_supported(void);
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bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev);
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bool amdgpu_device_aspm_support_quirk(void);
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@ -120,7 +120,6 @@ static int amdgpu_cs_p1_user_fence(struct amdgpu_cs_parser *p,
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struct drm_gem_object *gobj;
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struct amdgpu_bo *bo;
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unsigned long size;
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int r;
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gobj = drm_gem_object_lookup(p->filp, data->handle);
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if (gobj == NULL)
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@ -132,23 +131,14 @@ static int amdgpu_cs_p1_user_fence(struct amdgpu_cs_parser *p,
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drm_gem_object_put(gobj);
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size = amdgpu_bo_size(bo);
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if (size != PAGE_SIZE || (data->offset + 8) > size) {
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r = -EINVAL;
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goto error_unref;
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}
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if (size != PAGE_SIZE || data->offset > (size - 8))
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return -EINVAL;
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if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
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r = -EINVAL;
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goto error_unref;
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}
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if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
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return -EINVAL;
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*offset = data->offset;
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return 0;
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error_unref:
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amdgpu_bo_unref(&bo);
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return r;
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}
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static int amdgpu_cs_p1_bo_handles(struct amdgpu_cs_parser *p,
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@ -1354,32 +1354,6 @@ bool amdgpu_device_need_post(struct amdgpu_device *adev)
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return true;
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}
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/*
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* On APUs with >= 64GB white flickering has been observed w/ SG enabled.
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* Disable S/G on such systems until we have a proper fix.
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* https://gitlab.freedesktop.org/drm/amd/-/issues/2354
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* https://gitlab.freedesktop.org/drm/amd/-/issues/2735
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*/
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bool amdgpu_sg_display_supported(struct amdgpu_device *adev)
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{
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switch (amdgpu_sg_display) {
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case -1:
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break;
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case 0:
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return false;
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case 1:
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return true;
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default:
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return false;
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}
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if ((totalram_pages() << (PAGE_SHIFT - 10)) +
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(adev->gmc.real_vram_size / 1024) >= 64000000) {
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DRM_WARN("Disabling S/G due to >=64GB RAM\n");
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return false;
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}
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return true;
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}
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/*
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* Intel hosts such as Raptor Lake and Sapphire Rapids don't support dynamic
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* speed switching. Until we have confirmation from Intel that a specific host
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@ -1267,11 +1267,15 @@ static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_
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pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
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page_table_start.high_part = (u32)(adev->gmc.gart_start >> 44) & 0xF;
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page_table_start.low_part = (u32)(adev->gmc.gart_start >> 12);
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page_table_end.high_part = (u32)(adev->gmc.gart_end >> 44) & 0xF;
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page_table_end.low_part = (u32)(adev->gmc.gart_end >> 12);
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page_table_base.high_part = upper_32_bits(pt_base) & 0xF;
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page_table_start.high_part = upper_32_bits(adev->gmc.gart_start >>
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AMDGPU_GPU_PAGE_SHIFT);
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page_table_start.low_part = lower_32_bits(adev->gmc.gart_start >>
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AMDGPU_GPU_PAGE_SHIFT);
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page_table_end.high_part = upper_32_bits(adev->gmc.gart_end >>
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AMDGPU_GPU_PAGE_SHIFT);
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page_table_end.low_part = lower_32_bits(adev->gmc.gart_end >>
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AMDGPU_GPU_PAGE_SHIFT);
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page_table_base.high_part = upper_32_bits(pt_base);
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page_table_base.low_part = lower_32_bits(pt_base);
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pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18;
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@ -1636,8 +1640,9 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
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}
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break;
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}
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if (init_data.flags.gpu_vm_support)
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init_data.flags.gpu_vm_support = amdgpu_sg_display_supported(adev);
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if (init_data.flags.gpu_vm_support &&
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(amdgpu_sg_display == 0))
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init_data.flags.gpu_vm_support = false;
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if (init_data.flags.gpu_vm_support)
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adev->mode_info.gpu_vm_support = true;
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@ -290,7 +290,8 @@ static void dccg32_set_dpstreamclk(
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struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
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/* set the dtbclk_p source */
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dccg32_set_dtbclk_p_src(dccg, src, otg_inst);
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/* always program refclk as DTBCLK. No use-case expected to require DPREFCLK as refclk */
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dccg32_set_dtbclk_p_src(dccg, DTBCLK0, otg_inst);
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/* enabled to select one of the DTBCLKs for pipe */
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switch (dp_hpo_inst) {
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@ -4133,7 +4133,9 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
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}
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if (v->OutputFormat[k] == dm_420 && v->HActive[k] > DCN31_MAX_FMT_420_BUFFER_WIDTH
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&& v->ODMCombineEnablePerState[i][k] != dm_odm_combine_mode_4to1) {
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if (v->HActive[k] / 2 > DCN31_MAX_FMT_420_BUFFER_WIDTH) {
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if (v->Output[k] == dm_hdmi) {
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FMTBufferExceeded = true;
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} else if (v->HActive[k] / 2 > DCN31_MAX_FMT_420_BUFFER_WIDTH) {
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v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
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v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine4To1;
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@ -4225,7 +4225,9 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_
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}
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if (v->OutputFormat[k] == dm_420 && v->HActive[k] > DCN314_MAX_FMT_420_BUFFER_WIDTH
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&& v->ODMCombineEnablePerState[i][k] != dm_odm_combine_mode_4to1) {
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if (v->HActive[k] / 2 > DCN314_MAX_FMT_420_BUFFER_WIDTH) {
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if (v->Output[k] == dm_hdmi) {
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FMTBufferExceeded = true;
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} else if (v->HActive[k] / 2 > DCN314_MAX_FMT_420_BUFFER_WIDTH) {
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v->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_4to1;
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v->PlaneRequiredDISPCLK = v->PlaneRequiredDISPCLKWithODMCombine4To1;
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@ -3454,6 +3454,7 @@ bool dml32_CalculatePrefetchSchedule(
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double TimeForFetchingMetaPTE = 0;
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double TimeForFetchingRowInVBlank = 0;
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double LinesToRequestPrefetchPixelData = 0;
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double LinesForPrefetchBandwidth = 0;
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unsigned int HostVMDynamicLevelsTrips;
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double trip_to_mem;
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double Tvm_trips;
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@ -3883,11 +3884,15 @@ bool dml32_CalculatePrefetchSchedule(
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TimeForFetchingMetaPTE = Tvm_oto;
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TimeForFetchingRowInVBlank = Tr0_oto;
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*PrefetchBandwidth = prefetch_bw_oto;
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/* Clamp to oto for bandwidth calculation */
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LinesForPrefetchBandwidth = dst_y_prefetch_oto;
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} else {
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*DestinationLinesForPrefetch = dst_y_prefetch_equ;
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TimeForFetchingMetaPTE = Tvm_equ;
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TimeForFetchingRowInVBlank = Tr0_equ;
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*PrefetchBandwidth = prefetch_bw_equ;
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/* Clamp to equ for bandwidth calculation */
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LinesForPrefetchBandwidth = dst_y_prefetch_equ;
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}
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*DestinationLinesToRequestVMInVBlank = dml_ceil(4.0 * TimeForFetchingMetaPTE / LineTime, 1.0) / 4.0;
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@ -3895,7 +3900,7 @@ bool dml32_CalculatePrefetchSchedule(
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*DestinationLinesToRequestRowInVBlank =
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dml_ceil(4.0 * TimeForFetchingRowInVBlank / LineTime, 1.0) / 4.0;
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LinesToRequestPrefetchPixelData = *DestinationLinesForPrefetch -
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LinesToRequestPrefetchPixelData = LinesForPrefetchBandwidth -
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*DestinationLinesToRequestVMInVBlank - 2 * *DestinationLinesToRequestRowInVBlank;
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#ifdef __DML_VBA_DEBUG__
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@ -231,6 +231,7 @@ static const struct edid_quirk {
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/* OSVR HDK and HDK2 VR Headsets */
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EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP),
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EDID_QUIRK('A', 'U', 'O', 0x1111, EDID_QUIRK_NON_DESKTOP),
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};
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/*
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@ -1,4 +1,4 @@
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/* $OpenBSD: mbg.c,v 1.34 2023/04/10 04:21:20 jsg Exp $ */
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/* $OpenBSD: mbg.c,v 1.35 2023/09/25 15:38:46 deraadt Exp $ */
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/*
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* Copyright (c) 2006, 2007 Marc Balmer <mbalmer@openbsd.org>
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@ -160,7 +160,8 @@ const struct pci_matchid mbg_devices[] = {
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{ PCI_VENDOR_MEINBERG, PCI_PRODUCT_MEINBERG_PCI32 },
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{ PCI_VENDOR_MEINBERG, PCI_PRODUCT_MEINBERG_PCI509 },
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{ PCI_VENDOR_MEINBERG, PCI_PRODUCT_MEINBERG_PCI511 },
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{ PCI_VENDOR_MEINBERG, PCI_PRODUCT_MEINBERG_PEX511 }
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{ PCI_VENDOR_MEINBERG, PCI_PRODUCT_MEINBERG_PEX511 },
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{ PCI_VENDOR_MEINBERG, PCI_PRODUCT_MEINBERG_PZF180PEX }
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};
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int
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@ -246,6 +247,7 @@ mbg_attach(struct device *parent, struct device *self, void *aux)
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sensor_task_register(sc, mbg_task, 10);
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break;
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case PCI_PRODUCT_MEINBERG_GPS170PCI:
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case PCI_PRODUCT_MEINBERG_PZF180PEX:
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t_trust = 4 * 24 * 60 * 60; /* four days */
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sc->sc_read = mbg_read_asic;
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sensor_task_register(sc, mbg_task_hr, 1);
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@ -1,4 +1,4 @@
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$OpenBSD: pcidevs,v 1.2050 2023/09/07 02:11:26 daniel Exp $
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$OpenBSD: pcidevs,v 1.2051 2023/09/25 15:37:36 deraadt Exp $
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/* $NetBSD: pcidevs,v 1.30 1997/06/24 06:20:24 thorpej Exp $ */
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/*
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@ -7305,6 +7305,7 @@ product MEINBERG PCI32 0x0101 PCI32
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product MEINBERG PCI509 0x0102 PCI509
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product MEINBERG PCI511 0x0104 PCI511
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product MEINBERG PEX511 0x0105 PEX511
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product MEINBERG PZF180PEX 0x0106 PZF180PEX
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product MEINBERG GPS170PCI 0x0204 GPS170PCI
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/* Mellanox */
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@ -2,7 +2,7 @@
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* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
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*
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* generated from:
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* OpenBSD: pcidevs,v 1.2049 2023/09/07 01:41:09 jsg Exp
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* OpenBSD: pcidevs,v 1.2051 2023/09/25 15:37:36 deraadt Exp
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*/
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/* $NetBSD: pcidevs,v 1.30 1997/06/24 06:20:24 thorpej Exp $ */
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@ -7310,6 +7310,7 @@
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#define PCI_PRODUCT_MEINBERG_PCI509 0x0102 /* PCI509 */
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#define PCI_PRODUCT_MEINBERG_PCI511 0x0104 /* PCI511 */
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#define PCI_PRODUCT_MEINBERG_PEX511 0x0105 /* PEX511 */
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#define PCI_PRODUCT_MEINBERG_PZF180PEX 0x0106 /* PZF180PEX */
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#define PCI_PRODUCT_MEINBERG_GPS170PCI 0x0204 /* GPS170PCI */
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/* Mellanox */
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@ -2,7 +2,7 @@
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* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
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*
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* generated from:
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* OpenBSD: pcidevs,v 1.2049 2023/09/07 01:41:09 jsg Exp
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* OpenBSD: pcidevs,v 1.2051 2023/09/25 15:37:36 deraadt Exp
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*/
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/* $NetBSD: pcidevs,v 1.30 1997/06/24 06:20:24 thorpej Exp $ */
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@ -26355,6 +26355,10 @@ static const struct pci_known_product pci_known_products[] = {
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PCI_VENDOR_MEINBERG, PCI_PRODUCT_MEINBERG_PEX511,
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"PEX511",
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},
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{
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PCI_VENDOR_MEINBERG, PCI_PRODUCT_MEINBERG_PZF180PEX,
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"PZF180PEX",
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},
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{
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PCI_VENDOR_MEINBERG, PCI_PRODUCT_MEINBERG_GPS170PCI,
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"GPS170PCI",
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