sync with OpenBSD -current
This commit is contained in:
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72a51d0b15
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GPG key ID:
F42C07F07E2E35B7
15 changed files with 633 additions and 114 deletions
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@ -31,7 +31,7 @@ POSSIBILITY OF SUCH DAMAGE.
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***************************************************************************/
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/* $OpenBSD: if_em.c,v 1.368 2023/12/03 00:19:25 jsg Exp $ */
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/* $OpenBSD: if_em.c,v 1.370 2023/12/31 08:42:33 mglocker Exp $ */
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/* $FreeBSD: if_em.c,v 1.46 2004/09/29 18:28:28 mlaier Exp $ */
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#include <dev/pci/if_em.h>
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@ -285,11 +285,14 @@ int em_allocate_transmit_structures(struct em_softc *);
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int em_allocate_desc_rings(struct em_softc *);
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int em_rxfill(struct em_queue *);
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void em_rxrefill(void *);
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void em_rxrefill_locked(struct em_queue *);
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int em_rxeof(struct em_queue *);
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void em_receive_checksum(struct em_softc *, struct em_rx_desc *,
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struct mbuf *);
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u_int em_transmit_checksum_setup(struct em_queue *, struct mbuf *, u_int,
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u_int32_t *, u_int32_t *);
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u_int em_tso_setup(struct em_queue *, struct mbuf *, u_int, u_int32_t *,
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u_int32_t *);
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u_int em_tx_ctx_setup(struct em_queue *, struct mbuf *, u_int, u_int32_t *,
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u_int32_t *);
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void em_iff(struct em_softc *);
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@ -1022,7 +1025,7 @@ em_intr(void *arg)
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if (ifp->if_flags & IFF_RUNNING) {
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em_txeof(que);
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if (em_rxeof(que))
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em_rxrefill(que);
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em_rxrefill_locked(que);
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}
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/* Link status change */
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@ -1187,7 +1190,7 @@ em_flowstatus(struct em_softc *sc)
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*
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* This routine maps the mbufs to tx descriptors.
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*
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* return 0 on success, positive on failure
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* return 0 on failure, positive on success
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**********************************************************************/
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u_int
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em_encap(struct em_queue *que, struct mbuf *m)
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@ -1235,7 +1238,15 @@ em_encap(struct em_queue *que, struct mbuf *m)
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}
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if (sc->hw.mac_type >= em_82575 && sc->hw.mac_type <= em_i210) {
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used += em_tx_ctx_setup(que, m, head, &txd_upper, &txd_lower);
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if (ISSET(m->m_pkthdr.csum_flags, M_TCP_TSO)) {
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used += em_tso_setup(que, m, head, &txd_upper,
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&txd_lower);
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if (!used)
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return (used);
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} else {
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used += em_tx_ctx_setup(que, m, head, &txd_upper,
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&txd_lower);
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}
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} else if (sc->hw.mac_type >= em_82543) {
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used += em_transmit_checksum_setup(que, m, head,
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&txd_upper, &txd_lower);
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@ -1568,6 +1579,21 @@ em_update_link_status(struct em_softc *sc)
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ifp->if_link_state = link_state;
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if_link_state_change(ifp);
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}
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/* Disable TSO for 10/100 speeds to avoid some hardware issues */
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switch (sc->link_speed) {
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case SPEED_10:
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case SPEED_100:
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if (sc->hw.mac_type >= em_82575 && sc->hw.mac_type <= em_i210) {
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ifp->if_capabilities &= ~IFCAP_TSOv4;
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ifp->if_capabilities &= ~IFCAP_TSOv6;
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}
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break;
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case SPEED_1000:
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if (sc->hw.mac_type >= em_82575 && sc->hw.mac_type <= em_i210)
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ifp->if_capabilities |= IFCAP_TSOv4 | IFCAP_TSOv6;
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break;
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}
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}
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/*********************************************************************
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@ -1987,6 +2013,7 @@ em_setup_interface(struct em_softc *sc)
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if (sc->hw.mac_type >= em_82575 && sc->hw.mac_type <= em_i210) {
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ifp->if_capabilities |= IFCAP_CSUM_IPv4;
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ifp->if_capabilities |= IFCAP_CSUM_TCPv6 | IFCAP_CSUM_UDPv6;
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ifp->if_capabilities |= IFCAP_TSOv4 | IFCAP_TSOv6;
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}
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/*
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@ -2230,9 +2257,9 @@ em_setup_transmit_structures(struct em_softc *sc)
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for (i = 0; i < sc->sc_tx_slots; i++) {
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pkt = &que->tx.sc_tx_pkts_ring[i];
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error = bus_dmamap_create(sc->sc_dmat, MAX_JUMBO_FRAME_SIZE,
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error = bus_dmamap_create(sc->sc_dmat, EM_TSO_SIZE,
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EM_MAX_SCATTER / (sc->pcix_82544 ? 2 : 1),
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MAX_JUMBO_FRAME_SIZE, 0, BUS_DMA_NOWAIT, &pkt->pkt_map);
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EM_TSO_SEG_SIZE, 0, BUS_DMA_NOWAIT, &pkt->pkt_map);
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if (error != 0) {
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printf("%s: Unable to create TX DMA map\n",
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DEVNAME(sc));
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@ -2404,6 +2431,81 @@ em_free_transmit_structures(struct em_softc *sc)
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}
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}
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u_int
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em_tso_setup(struct em_queue *que, struct mbuf *mp, u_int head,
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u_int32_t *olinfo_status, u_int32_t *cmd_type_len)
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{
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struct ether_extracted ext;
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struct e1000_adv_tx_context_desc *TD;
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uint32_t vlan_macip_lens = 0, type_tucmd_mlhl = 0, mss_l4len_idx = 0;
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uint32_t paylen = 0;
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uint8_t iphlen = 0;
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*olinfo_status = 0;
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*cmd_type_len = 0;
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TD = (struct e1000_adv_tx_context_desc *)&que->tx.sc_tx_desc_ring[head];
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#if NVLAN > 0
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if (ISSET(mp->m_flags, M_VLANTAG)) {
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uint32_t vtag = mp->m_pkthdr.ether_vtag;
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vlan_macip_lens |= vtag << E1000_ADVTXD_VLAN_SHIFT;
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*cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
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}
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#endif
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ether_extract_headers(mp, &ext);
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if (ext.tcp == NULL)
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goto out;
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vlan_macip_lens |= (sizeof(*ext.eh) << E1000_ADVTXD_MACLEN_SHIFT);
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if (ext.ip4) {
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iphlen = ext.ip4->ip_hl << 2;
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type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4;
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*olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
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#ifdef INET6
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} else if (ext.ip6) {
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iphlen = sizeof(*ext.ip6);
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type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV6;
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#endif
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} else {
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goto out;
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}
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*cmd_type_len |= E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS;
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*cmd_type_len |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DCMD_TSE;
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paylen = mp->m_pkthdr.len - sizeof(*ext.eh) - iphlen -
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(ext.tcp->th_off << 2);
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*olinfo_status |= paylen << E1000_ADVTXD_PAYLEN_SHIFT;
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vlan_macip_lens |= iphlen;
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type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
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type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP;
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*olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
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mss_l4len_idx |= mp->m_pkthdr.ph_mss << E1000_ADVTXD_MSS_SHIFT;
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mss_l4len_idx |= (ext.tcp->th_off << 2) << E1000_ADVTXD_L4LEN_SHIFT;
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/* 82575 needs the queue index added */
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if (que->sc->hw.mac_type == em_82575)
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mss_l4len_idx |= (que->me & 0xff) << 4;
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htolem32(&TD->vlan_macip_lens, vlan_macip_lens);
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htolem32(&TD->type_tucmd_mlhl, type_tucmd_mlhl);
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htolem32(&TD->u.seqnum_seed, 0);
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htolem32(&TD->mss_l4len_idx, mss_l4len_idx);
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tcpstat_add(tcps_outpkttso, (paylen + mp->m_pkthdr.ph_mss - 1) /
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mp->m_pkthdr.ph_mss);
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return 1;
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out:
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tcpstat_inc(tcps_outbadtso);
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return 0;
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}
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u_int
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em_tx_ctx_setup(struct em_queue *que, struct mbuf *mp, u_int head,
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u_int32_t *olinfo_status, u_int32_t *cmd_type_len)
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em_rxrefill(void *arg)
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{
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struct em_queue *que = arg;
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int s;
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s = splnet();
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em_rxrefill_locked(que);
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splx(s);
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}
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void
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em_rxrefill_locked(struct em_queue *que)
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{
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struct em_softc *sc = que->sc;
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if (em_rxfill(que))
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@ -3954,7 +4066,7 @@ em_queue_intr_msix(void *vque)
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if (ifp->if_flags & IFF_RUNNING) {
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em_txeof(que);
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if (em_rxeof(que))
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em_rxrefill(que);
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em_rxrefill_locked(que);
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}
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em_enable_queue_intr_msix(que);
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***************************************************************************/
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/* $FreeBSD: if_em.h,v 1.26 2004/09/01 23:22:41 pdeuskar Exp $ */
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/* $OpenBSD: if_em.h,v 1.80 2022/01/09 05:42:50 jsg Exp $ */
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/* $OpenBSD: if_em.h,v 1.81 2023/12/31 08:42:33 mglocker Exp $ */
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#ifndef _EM_H_DEFINED_
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#define _EM_H_DEFINED_
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@ -55,11 +55,14 @@ POSSIBILITY OF SUCH DAMAGE.
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#include <net/if.h>
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#include <net/if_media.h>
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#include <net/route.h>
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#include <netinet/in.h>
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#include <netinet/ip.h>
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#include <netinet/if_ether.h>
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#include <netinet/tcp.h>
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#include <netinet/tcp_timer.h>
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#include <netinet/tcp_var.h>
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#include <netinet/udp.h>
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#if NBPFILTER > 0
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@ -269,6 +272,7 @@ typedef int boolean_t;
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#define EM_MAX_SCATTER 64
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#define EM_TSO_SIZE 65535
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#define EM_TSO_SEG_SIZE 4096 /* Max dma segment size */
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struct em_packet {
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int pkt_eop; /* Index of the desc to watch */
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@ -31,7 +31,7 @@
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*******************************************************************************/
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/* $OpenBSD: if_em_hw.h,v 1.90 2023/12/03 00:19:25 jsg Exp $ */
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/* $OpenBSD: if_em_hw.h,v 1.91 2023/12/31 08:42:33 mglocker Exp $ */
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/* $FreeBSD: if_em_hw.h,v 1.15 2005/05/26 23:32:02 tackerman Exp $ */
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/* if_em_hw.h
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@ -2150,6 +2150,7 @@ struct e1000_adv_tx_context_desc {
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#define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
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#define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */
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#define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */
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#define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
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#define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
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/* Adv Transmit Descriptor Config Masks */
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@ -2160,6 +2161,10 @@ struct e1000_adv_tx_context_desc {
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#define E1000_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */
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#define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
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/* Req requires Markers and CRC */
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#define E1000_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
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#define E1000_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
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/* Multiple Receive Queue Control */
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#define E1000_MRQC_ENABLE_MASK 0x00000003
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#define E1000_MRQC_ENABLE_RSS_2Q 0x00000001
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@ -1,4 +1,4 @@
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/* $OpenBSD: if_iwx.c,v 1.179 2023/12/20 07:33:32 stsp Exp $ */
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/* $OpenBSD: if_iwx.c,v 1.180 2023/12/30 16:55:44 stsp Exp $ */
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/*
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* Copyright (c) 2014, 2016 genua gmbh <info@genua.de>
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@ -10696,7 +10696,7 @@ static const struct iwx_dev_info iwx_dev_info_table[] = {
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_IWX_DEV_INFO(IWX_CFG_ANY, IWX_CFG_ANY,
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IWX_CFG_MAC_TYPE_SO, IWX_CFG_ANY,
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IWX_CFG_RF_TYPE_HR1, IWX_CFG_ANY,
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IWX_CFG_160, IWX_CFG_ANY, IWX_CFG_NO_CDB, IWX_CFG_ANY,
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IWX_CFG_NO_160, IWX_CFG_ANY, IWX_CFG_NO_CDB, IWX_CFG_ANY,
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iwx_cfg_so_a0_hr_b0), /* ax101 */
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_IWX_DEV_INFO(IWX_CFG_ANY, IWX_CFG_ANY,
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IWX_CFG_MAC_TYPE_SO, IWX_CFG_ANY,
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@ -10713,7 +10713,7 @@ static const struct iwx_dev_info iwx_dev_info_table[] = {
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_IWX_DEV_INFO(IWX_CFG_ANY, IWX_CFG_ANY,
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IWX_CFG_MAC_TYPE_SOF, IWX_CFG_ANY,
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IWX_CFG_RF_TYPE_HR1, IWX_CFG_ANY,
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IWX_CFG_160, IWX_CFG_ANY, IWX_CFG_NO_CDB, IWX_CFG_ANY,
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IWX_CFG_NO_160, IWX_CFG_ANY, IWX_CFG_NO_CDB, IWX_CFG_ANY,
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iwx_cfg_so_a0_hr_b0), /* AX101 */
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_IWX_DEV_INFO(IWX_CFG_ANY, IWX_CFG_ANY,
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IWX_CFG_MAC_TYPE_SOF, IWX_CFG_ANY,
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@ -1,4 +1,4 @@
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/* $OpenBSD: if_ixl.c,v 1.93 2023/11/10 15:51:20 bluhm Exp $ */
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/* $OpenBSD: if_ixl.c,v 1.94 2023/12/30 17:52:27 bluhm Exp $ */
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/*
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* Copyright (c) 2013-2015, Intel Corporation
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@ -900,7 +900,7 @@ struct ixl_rx_wb_desc_32 {
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uint64_t qword3;
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} __packed __aligned(16);
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#define IXL_TX_PKT_DESCS 32
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#define IXL_TX_PKT_DESCS 8
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#define IXL_TX_QUEUE_ALIGN 128
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#define IXL_RX_QUEUE_ALIGN 128
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