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sync with OpenBSD -current

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This commit is contained in:
purplerain 2024-04-26 00:31:56 +00:00
parent 87d00f0a9c
commit f41d8bece2
Signed by: purplerain
GPG key ID: F42C07F07E2E35B7
26 changed files with 342 additions and 151 deletions
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4
sys/dev/ic/dwqe.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: dwqe.c,v 1.18 2024/03/29 08:19:40 stsp Exp $ */
/* $OpenBSD: dwqe.c,v 1.19 2024/04/25 08:51:37 jmatthew Exp $ */
/*
* Copyright (c) 2008, 2019 Mark Kettenis <kettenis@openbsd.org>
* Copyright (c) 2017, 2022 Patrick Wildt <patrick@blueri.se>
@ -213,6 +213,8 @@ dwqe_attach(struct dwqe_softc *sc)
/* Disable interrupts. */
dwqe_write(sc, GMAC_INT_EN, 0);
dwqe_write(sc, GMAC_CHAN_INTR_ENA(0), 0);
dwqe_write(sc, GMAC_MMC_RX_INT_MASK, 0xffffffff);
dwqe_write(sc, GMAC_MMC_TX_INT_MASK, 0xffffffff);
return 0;
}

44
sys/dev/ic/dwqereg.h
View file

@ -1,4 +1,4 @@
/* $OpenBSD: dwqereg.h,v 1.5 2023/11/11 16:32:56 stsp Exp $ */
/* $OpenBSD: dwqereg.h,v 1.7 2024/04/25 11:37:39 stsp Exp $ */
/*
* Copyright (c) 2008, 2019 Mark Kettenis <kettenis@openbsd.org>
* Copyright (c) 2017, 2022 Patrick Wildt <patrick@blueri.se>
@ -83,6 +83,8 @@
#define GMAC_MAC_MDIO_DATA 0x0204
#define GMAC_MAC_ADDR0_HI 0x0300
#define GMAC_MAC_ADDR0_LO 0x0304
#define GMAC_MMC_RX_INT_MASK 0x070c
#define GMAC_MMC_TX_INT_MASK 0x0710
#define GMAC_MTL_OPERATION_MODE 0x0c00
#define GMAC_MTL_FRPE (1 << 15)
@ -233,14 +235,44 @@ struct dwqe_desc {
#define TDES3_FS (1 << 29)
#define TDES3_OWN (1U << 31)
/* Rx bits */
/* Rx bits (read format; host to device) */
#define RDES3_BUF1V (1 << 24)
#define RDES3_BUF2V (1 << 25)
#define RDES3_IC (1 << 30)
#define RDES3_OWN (1U << 31)
/* Rx bits (writeback format; device to host) */
#define RDES1_IP_PAYLOAD_TYPE 0x7
#define RDES1_IP_PAYLOAD_UNKNOWN 0x0
#define RDES1_IP_PAYLOAD_UDP 0x1
#define RDES1_IP_PAYLOAD_TCP 0x2
#define RDES1_IP_PAYLOAD_ICMP 0x3
#define RDES1_IP_HDR_ERROR (1 << 3)
#define RDES1_IPV4_HDR (1 << 4)
#define RDES1_IPV6_HDR (1 << 5)
#define RDES1_IP_CSUM_BYPASS (1 << 6)
#define RDES1_IP_PAYLOAD_ERROR (1 << 7)
#define RDES3_LENGTH (0x7fff << 0)
#define RDES3_ES (1 << 15)
#define RDES3_LENTYPE 0x70000
#define RDES3_LENTYPE_LENGTH (0x0 << 16)
#define RDES3_LENTYPE_TYPE (0x1 << 16)
/* 0x2 is reserved */
#define RDES3_LENTYPE_ARP (0x3 << 16)
#define RDES3_LENTYPE_VLAN (0x4 << 16)
#define RDES3_LENTYPE_2VLAN (0x5 << 16)
#define RDES3_LENTYPE_MACCTL (0x6 << 16)
#define RDES3_LENTYPE_OAM (0x7 << 16)
#define RDES3_DE (1 << 19)
#define RDES3_RE (1 << 20)
#define RDES3_OE (1 << 21)
#define RDES3_RWT (1 << 22)
#define RDES3_GP (1 << 23)
#define RDES3_CE (1 << 24)
#define RDES3_BUF1V (1 << 24)
#define RDES3_IC (1 << 30)
#define RDES3_OWN (1U << 31)
#define RDES3_LENGTH (0x7fff << 0)
#define RDES3_RDES0_VALID (1 << 25)
#define RDES3_RDES1_VALID (1 << 26)
#define RDES3_RDES2_VALID (1 << 27)
#define RDES3_LD (1 << 28)
#define RDES3_FD (1 << 29)
#define RDES3_CTXT (1 << 30)
/* Bit 31 is the OWN bit, as in "read" format. */