sync with OpenBSD -current
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fe7a6999d9
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f21e607a91
19 changed files with 138 additions and 64 deletions
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@ -1616,7 +1616,7 @@ static void gfx_v11_0_setup_rb(struct amdgpu_device *adev)
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active_rb_bitmap |= (0x3 << (i * rb_bitmap_width_per_sa));
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}
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active_rb_bitmap |= global_active_rb_bitmap;
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active_rb_bitmap &= global_active_rb_bitmap;
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adev->gfx.config.backend_enable_mask = active_rb_bitmap;
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adev->gfx.config.num_rbs = hweight32(active_rb_bitmap);
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}
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@ -449,10 +449,8 @@ static bool soc21_need_full_reset(struct amdgpu_device *adev)
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{
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switch (adev->ip_versions[GC_HWIP][0]) {
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case IP_VERSION(11, 0, 0):
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return amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC);
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case IP_VERSION(11, 0, 2):
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case IP_VERSION(11, 0, 3):
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return false;
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default:
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return true;
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}
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@ -804,10 +802,35 @@ static int soc21_common_suspend(void *handle)
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return soc21_common_hw_fini(adev);
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}
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static bool soc21_need_reset_on_resume(struct amdgpu_device *adev)
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{
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u32 sol_reg1, sol_reg2;
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/* Will reset for the following suspend abort cases.
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* 1) Only reset dGPU side.
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* 2) S3 suspend got aborted and TOS is active.
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*/
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if (!(adev->flags & AMD_IS_APU) && adev->in_s3 &&
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!adev->suspend_complete) {
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sol_reg1 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
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drm_msleep(100);
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sol_reg2 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
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return (sol_reg1 != sol_reg2);
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}
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return false;
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}
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static int soc21_common_resume(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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if (soc21_need_reset_on_resume(adev)) {
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dev_info(adev->dev, "S3 suspend aborted, resetting...");
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soc21_asic_reset(adev);
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}
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return soc21_common_hw_init(adev);
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}
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@ -1980,6 +1980,7 @@ static int unmap_queues_cpsch(struct device_queue_manager *dqm,
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pr_err("HIQ MQD's queue_doorbell_id0 is not 0, Queue preemption time out\n");
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while (halt_if_hws_hang)
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schedule();
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kfd_hws_hang(dqm);
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return -ETIME;
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}
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@ -6126,19 +6126,16 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
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if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
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mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket);
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if (stream->link->psr_settings.psr_feature_enabled || stream->link->replay_settings.replay_feature_enabled) {
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if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
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stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST ||
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stream->signal == SIGNAL_TYPE_EDP) {
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//
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// should decide stream support vsc sdp colorimetry capability
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// before building vsc info packet
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//
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stream->use_vsc_sdp_for_colorimetry = false;
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if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
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stream->use_vsc_sdp_for_colorimetry =
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aconnector->dc_sink->is_vsc_sdp_colorimetry_supported;
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} else {
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if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED)
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stream->use_vsc_sdp_for_colorimetry = true;
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}
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stream->use_vsc_sdp_for_colorimetry = stream->link->dpcd_caps.dpcd_rev.raw >= 0x14 &&
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stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED;
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if (stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22)
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tf = TRANSFER_FUNC_GAMMA_22;
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mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf);
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@ -99,20 +99,25 @@ static int dcn316_get_active_display_cnt_wa(
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return display_count;
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}
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static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)
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static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context,
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bool safe_to_lower, bool disable)
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{
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struct dc *dc = clk_mgr_base->ctx->dc;
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int i;
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for (i = 0; i < dc->res_pool->pipe_count; ++i) {
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struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
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struct pipe_ctx *pipe = safe_to_lower
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? &context->res_ctx.pipe_ctx[i]
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: &dc->current_state->res_ctx.pipe_ctx[i];
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if (pipe->top_pipe || pipe->prev_odm_pipe)
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continue;
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if (pipe->stream && (pipe->stream->dpms_off || pipe->plane_state == NULL ||
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dc_is_virtual_signal(pipe->stream->signal))) {
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if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal) ||
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!pipe->stream->link_enc)) {
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if (disable) {
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pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);
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if (pipe->stream_res.tg && pipe->stream_res.tg->funcs->immediate_disable_crtc)
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pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);
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reset_sync_context_for_pipe(dc, context, i);
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} else
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pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
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@ -207,11 +212,11 @@ static void dcn316_update_clocks(struct clk_mgr *clk_mgr_base,
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}
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if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
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dcn316_disable_otg_wa(clk_mgr_base, context, true);
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dcn316_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true);
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clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
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dcn316_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
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dcn316_disable_otg_wa(clk_mgr_base, context, false);
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dcn316_disable_otg_wa(clk_mgr_base, context, safe_to_lower, false);
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update_dispclk = true;
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}
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@ -226,8 +226,18 @@ static int smu_v13_0_4_system_features_control(struct smu_context *smu, bool en)
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struct amdgpu_device *adev = smu->adev;
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int ret = 0;
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if (!en && !adev->in_s0ix)
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if (!en && !adev->in_s0ix) {
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/* Adds a GFX reset as workaround just before sending the
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* MP1_UNLOAD message to prevent GC/RLC/PMFW from entering
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* an invalid state.
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*/
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ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset,
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SMU_RESET_MODE_2, NULL);
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if (ret)
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return ret;
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ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL);
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}
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return ret;
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}
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@ -777,6 +777,7 @@ int drm_client_modeset_probe(struct drm_client_dev *client, unsigned int width,
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unsigned int total_modes_count = 0;
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struct drm_client_offset *offsets;
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unsigned int connector_count = 0;
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/* points to modes protected by mode_config.mutex */
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struct drm_display_mode **modes;
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struct drm_crtc **crtcs;
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int i, ret = 0;
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@ -855,7 +856,6 @@ int drm_client_modeset_probe(struct drm_client_dev *client, unsigned int width,
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drm_client_pick_crtcs(client, connectors, connector_count,
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crtcs, modes, 0, width, height);
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}
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mutex_unlock(&dev->mode_config.mutex);
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drm_client_modeset_release(client);
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@ -885,6 +885,7 @@ int drm_client_modeset_probe(struct drm_client_dev *client, unsigned int width,
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modeset->y = offset->y;
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}
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}
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mutex_unlock(&dev->mode_config.mutex);
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mutex_unlock(&client->modeset_mutex);
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out:
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@ -2462,7 +2462,7 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
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if (IS_DG2(i915))
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intel_cdclk_pcode_pre_notify(state);
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if (pipe == INVALID_PIPE ||
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if (new_cdclk_state->disable_pipes ||
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old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) {
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drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
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@ -2494,7 +2494,7 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
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if (IS_DG2(i915))
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intel_cdclk_pcode_post_notify(state);
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if (pipe != INVALID_PIPE &&
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if (!new_cdclk_state->disable_pipes &&
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old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) {
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drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
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@ -2946,6 +2946,7 @@ static struct intel_global_state *intel_cdclk_duplicate_state(struct intel_globa
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return NULL;
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cdclk_state->pipe = INVALID_PIPE;
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cdclk_state->disable_pipes = false;
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return &cdclk_state->base;
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}
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@ -3124,6 +3125,8 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
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if (ret)
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return ret;
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new_cdclk_state->disable_pipes = true;
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drm_dbg_kms(&dev_priv->drm,
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"Modeset required for cdclk change\n");
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}
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@ -51,6 +51,9 @@ struct intel_cdclk_state {
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/* bitmask of active pipes */
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u8 active_pipes;
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/* update cdclk with pipes disabled */
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bool disable_pipes;
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};
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int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
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@ -4111,7 +4111,12 @@ static bool m_n_equal(const struct intel_link_m_n *m_n_1,
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static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1,
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const struct intel_crtc_state *crtc_state2)
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{
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/*
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* FIXME the modeset sequence is currently wrong and
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* can't deal with bigjoiner + port sync at the same time.
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*/
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return crtc_state1->hw.active && crtc_state2->hw.active &&
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!crtc_state1->bigjoiner_pipes && !crtc_state2->bigjoiner_pipes &&
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crtc_state1->output_types == crtc_state2->output_types &&
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crtc_state1->output_format == crtc_state2->output_format &&
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crtc_state1->lane_count == crtc_state2->lane_count &&
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@ -111,6 +111,13 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
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if (!intel_vrr_is_capable(connector))
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return;
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/*
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* FIXME all joined pipes share the same transcoder.
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* Need to account for that during VRR toggle/push/etc.
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*/
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if (crtc_state->bigjoiner_pipes)
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return;
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if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
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return;
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