sync code with last improvements from OpenBSD
This commit is contained in:
parent
085b88af82
commit
ecb53bfacf
22 changed files with 1201 additions and 743 deletions
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@ -32,17 +32,13 @@
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*
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* static int remove_conflicting_framebuffers(struct pci_dev *pdev)
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* {
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* bool primary = false;
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* resource_size_t base, size;
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* int ret;
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*
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* base = pci_resource_start(pdev, 0);
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* size = pci_resource_len(pdev, 0);
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* #ifdef CONFIG_X86
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* primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
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* #endif
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*
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* return drm_aperture_remove_conflicting_framebuffers(base, size, primary,
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* return drm_aperture_remove_conflicting_framebuffers(base, size,
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* &example_driver);
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* }
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*
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@ -165,7 +161,6 @@ EXPORT_SYMBOL(devm_aperture_acquire_from_firmware);
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* drm_aperture_remove_conflicting_framebuffers - remove existing framebuffers in the given range
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* @base: the aperture's base address in physical memory
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* @size: aperture size in bytes
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* @primary: also kick vga16fb if present
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* @req_driver: requesting DRM driver
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*
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* This function removes graphics device drivers which use the memory range described by
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@ -175,9 +170,9 @@ EXPORT_SYMBOL(devm_aperture_acquire_from_firmware);
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* 0 on success, or a negative errno code otherwise
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*/
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int drm_aperture_remove_conflicting_framebuffers(resource_size_t base, resource_size_t size,
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bool primary, const struct drm_driver *req_driver)
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const struct drm_driver *req_driver)
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{
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return aperture_remove_conflicting_devices(base, size, primary, req_driver->name);
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return aperture_remove_conflicting_devices(base, size, false, req_driver->name);
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}
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EXPORT_SYMBOL(drm_aperture_remove_conflicting_framebuffers);
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@ -165,14 +165,60 @@ static u32 preparser_disable(bool state)
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return MI_ARB_CHECK | 1 << 8 | state;
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}
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u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv_reg)
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static i915_reg_t gen12_get_aux_inv_reg(struct intel_engine_cs *engine)
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{
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u32 gsi_offset = gt->uncore->gsi_offset;
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switch (engine->id) {
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case RCS0:
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return GEN12_CCS_AUX_INV;
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case BCS0:
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return GEN12_BCS0_AUX_INV;
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case VCS0:
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return GEN12_VD0_AUX_INV;
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case VCS2:
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return GEN12_VD2_AUX_INV;
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case VECS0:
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return GEN12_VE0_AUX_INV;
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case CCS0:
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return GEN12_CCS0_AUX_INV;
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default:
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return INVALID_MMIO_REG;
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}
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}
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static bool gen12_needs_ccs_aux_inv(struct intel_engine_cs *engine)
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{
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i915_reg_t reg = gen12_get_aux_inv_reg(engine);
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if (IS_PONTEVECCHIO(engine->i915))
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return false;
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/*
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* So far platforms supported by i915 having flat ccs do not require
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* AUX invalidation. Check also whether the engine requires it.
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*/
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return i915_mmio_reg_valid(reg) && !HAS_FLAT_CCS(engine->i915);
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}
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u32 *gen12_emit_aux_table_inv(struct intel_engine_cs *engine, u32 *cs)
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{
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i915_reg_t inv_reg = gen12_get_aux_inv_reg(engine);
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u32 gsi_offset = engine->gt->uncore->gsi_offset;
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if (!gen12_needs_ccs_aux_inv(engine))
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return cs;
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*cs++ = MI_LOAD_REGISTER_IMM(1) | MI_LRI_MMIO_REMAP_EN;
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*cs++ = i915_mmio_reg_offset(inv_reg) + gsi_offset;
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*cs++ = AUX_INV;
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*cs++ = MI_NOOP;
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*cs++ = MI_SEMAPHORE_WAIT_TOKEN |
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MI_SEMAPHORE_REGISTER_POLL |
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MI_SEMAPHORE_POLL |
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MI_SEMAPHORE_SAD_EQ_SDD;
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*cs++ = 0;
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*cs++ = i915_mmio_reg_offset(inv_reg) + gsi_offset;
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*cs++ = 0;
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*cs++ = 0;
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return cs;
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}
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@ -181,7 +227,11 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
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{
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struct intel_engine_cs *engine = rq->engine;
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if (mode & EMIT_FLUSH) {
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/*
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* On Aux CCS platforms the invalidation of the Aux
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* table requires quiescing memory traffic beforehand
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*/
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if (mode & EMIT_FLUSH || gen12_needs_ccs_aux_inv(engine)) {
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u32 flags = 0;
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u32 *cs;
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@ -236,10 +286,9 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
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else if (engine->class == COMPUTE_CLASS)
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flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
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if (!HAS_FLAT_CCS(rq->engine->i915))
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count = 8 + 4;
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else
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count = 8;
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count = 8;
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if (gen12_needs_ccs_aux_inv(rq->engine))
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count += 8;
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cs = intel_ring_begin(rq, count);
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if (IS_ERR(cs))
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@ -254,11 +303,7 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
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cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR);
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if (!HAS_FLAT_CCS(rq->engine->i915)) {
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/* hsdes: 1809175790 */
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cs = gen12_emit_aux_table_inv(rq->engine->gt, cs,
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GEN12_CCS_AUX_INV);
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}
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cs = gen12_emit_aux_table_inv(engine, cs);
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*cs++ = preparser_disable(false);
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intel_ring_advance(rq, cs);
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@ -269,21 +314,14 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
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int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode)
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{
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intel_engine_mask_t aux_inv = 0;
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u32 cmd, *cs;
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u32 cmd = 4;
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u32 *cs;
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cmd = 4;
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if (mode & EMIT_INVALIDATE) {
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cmd += 2;
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if (!HAS_FLAT_CCS(rq->engine->i915) &&
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(rq->engine->class == VIDEO_DECODE_CLASS ||
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rq->engine->class == VIDEO_ENHANCEMENT_CLASS)) {
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aux_inv = rq->engine->mask &
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~GENMASK(_BCS(I915_MAX_BCS - 1), BCS0);
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if (aux_inv)
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cmd += 4;
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}
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if (gen12_needs_ccs_aux_inv(rq->engine))
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cmd += 8;
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}
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cs = intel_ring_begin(rq, cmd);
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*cs++ = 0; /* upper addr */
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*cs++ = 0; /* value */
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if (aux_inv) { /* hsdes: 1809175790 */
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if (rq->engine->class == VIDEO_DECODE_CLASS)
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cs = gen12_emit_aux_table_inv(rq->engine->gt,
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cs, GEN12_VD0_AUX_INV);
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else
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cs = gen12_emit_aux_table_inv(rq->engine->gt,
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cs, GEN12_VE0_AUX_INV);
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}
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cs = gen12_emit_aux_table_inv(rq->engine, cs);
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if (mode & EMIT_INVALIDATE)
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*cs++ = preparser_disable(false);
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@ -13,6 +13,7 @@
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#include "intel_gt_regs.h"
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#include "intel_gpu_commands.h"
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struct intel_engine_cs;
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struct intel_gt;
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struct i915_request;
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@ -46,7 +47,7 @@ u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs);
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u32 *gen11_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs);
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u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs);
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u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv_reg);
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u32 *gen12_emit_aux_table_inv(struct intel_engine_cs *engine, u32 *cs);
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static inline u32 *
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__gen8_emit_pipe_control(u32 *batch, u32 flags0, u32 flags1, u32 offset)
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@ -120,6 +120,7 @@
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#define MI_SEMAPHORE_TARGET(engine) ((engine)<<15)
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#define MI_SEMAPHORE_WAIT MI_INSTR(0x1c, 2) /* GEN8+ */
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#define MI_SEMAPHORE_WAIT_TOKEN MI_INSTR(0x1c, 3) /* GEN12+ */
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#define MI_SEMAPHORE_REGISTER_POLL (1 << 16)
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#define MI_SEMAPHORE_POLL (1 << 15)
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#define MI_SEMAPHORE_SAD_GT_SDD (0 << 12)
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#define MI_SEMAPHORE_SAD_GTE_SDD (1 << 12)
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@ -1301,10 +1301,7 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs)
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IS_DG2_G11(ce->engine->i915))
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cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE, 0);
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/* hsdes: 1809175790 */
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if (!HAS_FLAT_CCS(ce->engine->i915))
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cs = gen12_emit_aux_table_inv(ce->engine->gt,
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cs, GEN12_CCS_AUX_INV);
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cs = gen12_emit_aux_table_inv(ce->engine, cs);
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/* Wa_16014892111 */
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if (IS_DG2(ce->engine->i915))
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PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE,
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0);
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/* hsdes: 1809175790 */
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if (!HAS_FLAT_CCS(ce->engine->i915)) {
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if (ce->engine->class == VIDEO_DECODE_CLASS)
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cs = gen12_emit_aux_table_inv(ce->engine->gt,
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cs, GEN12_VD0_AUX_INV);
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else if (ce->engine->class == VIDEO_ENHANCEMENT_CLASS)
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cs = gen12_emit_aux_table_inv(ce->engine->gt,
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cs, GEN12_VE0_AUX_INV);
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}
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return cs;
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return gen12_emit_aux_table_inv(ce->engine, cs);
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}
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static void
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@ -603,7 +603,6 @@ static int i915_pcode_init(struct drm_i915_private *i915)
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static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
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{
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struct pci_dev *pdev = dev_priv->drm.pdev;
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struct pci_dev *root_pdev;
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int ret;
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if (i915_inject_probe_failure(dev_priv))
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intel_bw_init_hw(dev_priv);
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/*
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* FIXME: Temporary hammer to avoid freezing the machine on our DGFX
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* This should be totally removed when we handle the pci states properly
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* on runtime PM and on s2idle cases.
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*/
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#ifdef notyet
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root_pdev = pcie_find_root_port(pdev);
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if (root_pdev)
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pci_d3cold_disable(root_pdev);
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#endif
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return 0;
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err_msi:
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STUB();
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#ifdef notyet
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struct pci_dev *pdev = dev_priv->drm.pdev;
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struct pci_dev *root_pdev;
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i915_perf_fini(dev_priv);
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if (pdev->msi_enabled)
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pci_disable_msi(pdev);
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root_pdev = pcie_find_root_port(pdev);
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if (root_pdev)
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pci_d3cold_enable(root_pdev);
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#endif
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}
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@ -1785,6 +1768,8 @@ static int intel_runtime_suspend(struct device *kdev)
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{
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struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
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struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
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struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
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struct pci_dev *root_pdev;
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struct intel_gt *gt;
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int ret, i;
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@ -1834,6 +1819,15 @@ static int intel_runtime_suspend(struct device *kdev)
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drm_err(&dev_priv->drm,
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"Unclaimed access detected prior to suspending\n");
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/*
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* FIXME: Temporary hammer to avoid freezing the machine on our DGFX
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* This should be totally removed when we handle the pci states properly
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* on runtime PM.
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*/
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root_pdev = pcie_find_root_port(pdev);
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if (root_pdev)
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pci_d3cold_disable(root_pdev);
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rpm->suspended = true;
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/*
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@ -1872,6 +1866,8 @@ static int intel_runtime_resume(struct device *kdev)
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{
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struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
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struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
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struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
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struct pci_dev *root_pdev;
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struct intel_gt *gt;
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int ret, i;
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@ -1885,6 +1881,11 @@ static int intel_runtime_resume(struct device *kdev)
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intel_opregion_notify_adapter(dev_priv, PCI_D0);
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rpm->suspended = false;
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root_pdev = pcie_find_root_port(pdev);
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if (root_pdev)
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pci_d3cold_enable(root_pdev);
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if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
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drm_dbg(&dev_priv->drm,
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"Unclaimed access during suspend, bios?\n");
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@ -1525,7 +1525,7 @@ enum drm_dp_phy {
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#define DP_BRANCH_OUI_HEADER_SIZE 0xc
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#define DP_RECEIVER_CAP_SIZE 0xf
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#define DP_DSC_RECEIVER_CAP_SIZE 0xf
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#define DP_DSC_RECEIVER_CAP_SIZE 0x10 /* DSC Capabilities 0x60 through 0x6F */
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#define EDP_PSR_RECEIVER_CAP_SIZE 2
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#define EDP_DISPLAY_CTL_CAP_SIZE 3
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#define DP_LTTPR_COMMON_CAP_SIZE 8
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@ -13,14 +13,13 @@ int devm_aperture_acquire_from_firmware(struct drm_device *dev, resource_size_t
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resource_size_t size);
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int drm_aperture_remove_conflicting_framebuffers(resource_size_t base, resource_size_t size,
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bool primary, const struct drm_driver *req_driver);
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const struct drm_driver *req_driver);
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int drm_aperture_remove_conflicting_pci_framebuffers(struct pci_dev *pdev,
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const struct drm_driver *req_driver);
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/**
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* drm_aperture_remove_framebuffers - remove all existing framebuffers
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* @primary: also kick vga16fb if present
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* @req_driver: requesting DRM driver
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*
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* This function removes all graphics device drivers. Use this function on systems
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@ -30,9 +29,9 @@ int drm_aperture_remove_conflicting_pci_framebuffers(struct pci_dev *pdev,
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* 0 on success, or a negative errno code otherwise
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*/
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static inline int
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drm_aperture_remove_framebuffers(bool primary, const struct drm_driver *req_driver)
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drm_aperture_remove_framebuffers(const struct drm_driver *req_driver)
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{
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return drm_aperture_remove_conflicting_framebuffers(0, (resource_size_t)-1, primary,
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return drm_aperture_remove_conflicting_framebuffers(0, (resource_size_t)-1,
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req_driver);
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}
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