sync with OpenBSD -current
This commit is contained in:
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f4dadbf64a
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GPG key ID:
F42C07F07E2E35B7
13 changed files with 143 additions and 28 deletions
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@ -1,4 +1,4 @@
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/* $OpenBSD: rkclock.c,v 1.86 2024/03/02 19:48:13 kettenis Exp $ */
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/* $OpenBSD: rkclock.c,v 1.87 2024/03/06 14:55:22 kettenis Exp $ */
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/*
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* Copyright (c) 2017, 2018 Mark Kettenis <kettenis@openbsd.org>
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*
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@ -1043,6 +1043,21 @@ const struct rkclock rk3308_clocks[] = {
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SEL(15, 14), DIV(6, 0),
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{ RK3308_PLL_DPLL, RK3308_PLL_VPLL0, RK3308_XIN24M }
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},
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{
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RK3308_CLK_SPI0, RK3308_CRU_CLKSEL_CON(30),
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SEL(15, 14), DIV(6, 0),
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{ RK3308_PLL_DPLL, RK3308_PLL_VPLL0, RK3308_XIN24M }
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},
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{
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RK3308_CLK_SPI1, RK3308_CRU_CLKSEL_CON(31),
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SEL(15, 14), DIV(6, 0),
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{ RK3308_PLL_DPLL, RK3308_PLL_VPLL0, RK3308_XIN24M }
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},
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{
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RK3308_CLK_SPI2, RK3308_CRU_CLKSEL_CON(32),
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SEL(15, 14), DIV(6, 0),
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{ RK3308_PLL_DPLL, RK3308_PLL_VPLL0, RK3308_XIN24M }
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},
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{
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RK3308_CLK_TSADC, RK3308_CRU_CLKSEL_CON(33),
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0, DIV(10, 0),
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@ -1531,6 +1546,11 @@ const struct rkclock rk3328_clocks[] = {
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SEL(15, 14), DIV(13, 0),
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{ RK3328_PLL_CPLL, RK3328_PLL_GPLL, RK3328_XIN24M }
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},
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{
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RK3328_CLK_SPI, RK3328_CRU_CLKSEL_CON(24),
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SEL(7, 7), DIV(6, 0),
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{ RK3328_PLL_CPLL, RK3328_PLL_GPLL }
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},
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{
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RK3328_CLK_SDMMC, RK3328_CRU_CLKSEL_CON(30),
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SEL(9, 8), DIV(7, 0),
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@ -2256,6 +2276,31 @@ const struct rkclock rk3399_clocks[] = {
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SEL(15, 15), DIV(14, 8),
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{ RK3399_PLL_CPLL, RK3399_PLL_GPLL }
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},
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{
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RK3399_CLK_SPI0, RK3399_CRU_CLKSEL_CON(59),
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SEL(7, 7), DIV(6, 0),
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{ RK3399_PLL_CPLL, RK3399_PLL_GPLL }
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},
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{
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RK3399_CLK_SPI1, RK3399_CRU_CLKSEL_CON(59),
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SEL(15, 15), DIV(14, 8),
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{ RK3399_PLL_CPLL, RK3399_PLL_GPLL }
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},
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{
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RK3399_CLK_SPI2, RK3399_CRU_CLKSEL_CON(60),
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SEL(7, 7), DIV(6, 0),
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{ RK3399_PLL_CPLL, RK3399_PLL_GPLL }
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},
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{
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RK3399_CLK_SPI4, RK3399_CRU_CLKSEL_CON(60),
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SEL(15, 15), DIV(14, 8),
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{ RK3399_PLL_CPLL, RK3399_PLL_GPLL }
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},
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{
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RK3399_CLK_SPI5, RK3399_CRU_CLKSEL_CON(58),
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SEL(15, 15), DIV(14, 8),
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{ RK3399_PLL_CPLL, RK3399_PLL_GPLL }
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},
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{
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RK3399_CLK_SDMMC, RK3399_CRU_CLKSEL_CON(16),
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SEL(10, 8), DIV(6, 0),
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@ -3284,6 +3329,26 @@ const struct rkclock rk3568_clocks[] = {
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RK3568_CLK_I2C5, 0, 0, 0,
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{ RK3568_CLK_I2C }
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},
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{
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RK3568_CLK_SPI0, RK3568_CRU_CLKSEL_CON(72),
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SEL(1, 0), 0,
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{ RK3568_GPLL_200M, RK3568_XIN24M, RK3568_CPLL_100M }
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},
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{
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RK3568_CLK_SPI1, RK3568_CRU_CLKSEL_CON(72),
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SEL(3, 2), 0,
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{ RK3568_GPLL_200M, RK3568_XIN24M, RK3568_CPLL_100M }
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},
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{
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RK3568_CLK_SPI2, RK3568_CRU_CLKSEL_CON(72),
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SEL(5, 4), 0,
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{ RK3568_GPLL_200M, RK3568_XIN24M, RK3568_CPLL_100M }
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},
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{
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RK3568_CLK_SPI3, RK3568_CRU_CLKSEL_CON(72),
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SEL(7, 6), 0,
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{ RK3568_GPLL_200M, RK3568_XIN24M, RK3568_CPLL_100M }
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},
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{
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RK3568_SCLK_GMAC0, RK3568_CRU_CLKSEL_CON(31),
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SEL(2, 2), 0,
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@ -57,6 +57,9 @@
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#define RK3308_CLK_UART3 20
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#define RK3308_CLK_UART4 21
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#define RK3308_CLK_PWM0 26
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#define RK3308_CLK_SPI0 27
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#define RK3308_CLK_SPI1 28
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#define RK3308_CLK_SPI2 29
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#define RK3308_CLK_TSADC 36
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#define RK3308_CLK_SARADC 37
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#define RK3308_CLK_CRYPTO 41
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@ -103,6 +106,7 @@
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#define RK3328_ARMCLK 6
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#define RK3328_CLK_RTC32K 30
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#define RK3328_CLK_SPI 32
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#define RK3328_CLK_SDMMC 33
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#define RK3328_CLK_SDIO 34
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#define RK3328_CLK_EMMC 35
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@ -171,6 +175,11 @@
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#define RK3399_CLK_I2C5 68
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#define RK3399_CLK_I2C6 69
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#define RK3399_CLK_I2C7 70
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#define RK3399_CLK_SPI0 71
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#define RK3399_CLK_SPI1 72
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#define RK3399_CLK_SPI2 73
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#define RK3399_CLK_SPI4 74
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#define RK3399_CLK_SPI5 75
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#define RK3399_CLK_SDMMC 76
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#define RK3399_CLK_SDIO 77
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#define RK3399_CLK_EMMC 78
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@ -326,6 +335,10 @@
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#define RK3568_CLK_I2C3 332
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#define RK3568_CLK_I2C4 334
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#define RK3568_CLK_I2C5 336
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#define RK3568_CLK_SPI0 338
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#define RK3568_CLK_SPI1 340
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#define RK3568_CLK_SPI2 342
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#define RK3568_CLK_SPI3 344
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#define RK3568_SCLK_GMAC0 386
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#define RK3568_SCLK_GMAC0_RGMII_SPEED 387
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#define RK3568_SCLK_GMAC0_RMII_SPEED 388
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@ -1,4 +1,4 @@
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/* $OpenBSD: sxiccmu.c,v 1.37 2024/03/04 04:11:52 deraadt Exp $ */
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/* $OpenBSD: sxiccmu.c,v 1.38 2024/03/07 01:04:16 kevlo Exp $ */
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/*
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* Copyright (c) 2007,2009 Dale Rahn <drahn@openbsd.org>
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* Copyright (c) 2013 Artturi Alm
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@ -1265,12 +1265,15 @@ sxiccmu_a80_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)
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#define D1_RISCV_CLK_SEL_HOSC (0 << 24)
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#define D1_RISCV_CLK_SEL_PLL_CPU (5 << 24)
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#define D1_RISCV_DIV_CFG_FACTOR_M(x) (((x) >> 0) & 0x1f)
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#define D1_PSI_CLK_REG 0x0510
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#define D1_PSI_CLK_FACTOR_N(x) (((x) >> 8) & 0x3)
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#define D1_PSI_CLK_FACTOR_M(x) (((x) >> 0) & 0x3)
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uint32_t
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sxiccmu_d1_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)
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{
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uint32_t parent;
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uint32_t reg;
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uint32_t reg, freq;
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uint32_t m, n;
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switch (idx) {
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@ -1301,6 +1304,13 @@ sxiccmu_d1_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)
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}
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m = D1_RISCV_DIV_CFG_FACTOR_M(reg) + 1;
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return sxiccmu_ccu_get_frequency(sc, &parent) / m;
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case D1_CLK_PSI_AHB:
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reg = SXIREAD4(sc, D1_PSI_CLK_REG);
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/* assume PLL_PERIPH0 source */
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freq = sxiccmu_d1_get_frequency(sc, D1_CLK_PLL_PERIPH0);
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m = D1_PSI_CLK_FACTOR_M(reg) + 1;
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n = 1 << D1_PSI_CLK_FACTOR_N(reg);
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return freq / (m * n);
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}
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printf("%s: 0x%08x\n", __func__, idx);
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@ -364,6 +364,7 @@ const struct sxiccmu_ccu_bit sun9i_a80_mmc_gates[] = {
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#define D1_CLK_PLL_CPU 0
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#define D1_CLK_PLL_PERIPH0 5
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#define D1_CLK_PSI_AHB 23
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#define D1_CLK_APB1 25
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#define D1_CLK_MMC0 56
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#define D1_CLK_MMC1 57
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@ -377,6 +378,7 @@ const struct sxiccmu_ccu_bit sun9i_a80_mmc_gates[] = {
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#define D1_CLK_BUS_UART3 65
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#define D1_CLK_BUS_UART4 66
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#define D1_CLK_BUS_UART5 67
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#define D1_CLK_BUS_EMAC 77
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#define D1_CLK_USB_OHCI0 97
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#define D1_CLK_USB_OHCI1 98
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#define D1_CLK_BUS_OHCI0 99
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@ -400,6 +402,7 @@ const struct sxiccmu_ccu_bit sun20i_d1_gates[] = {
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[D1_CLK_BUS_UART3] = { 0x090c, 3, D1_CLK_APB1 },
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[D1_CLK_BUS_UART4] = { 0x090c, 4, D1_CLK_APB1 },
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[D1_CLK_BUS_UART5] = { 0x090c, 5, D1_CLK_APB1 },
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[D1_CLK_BUS_EMAC] = { 0x097c, 0, D1_CLK_PSI_AHB },
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[D1_CLK_USB_OHCI0] = { 0x0a70, 31 },
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[D1_CLK_USB_OHCI1] = { 0x0a74, 31 },
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[D1_CLK_BUS_OHCI0] = { 0x0a8c, 0 },
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@ -989,6 +992,7 @@ const struct sxiccmu_ccu_bit sun9i_a80_mmc_resets[] = {
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#define D1_RST_BUS_UART3 21
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#define D1_RST_BUS_UART4 22
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#define D1_RST_BUS_UART5 23
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#define D1_RST_BUS_EMAC 30
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#define D1_RST_USB_PHY0 40
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#define D1_RST_USB_PHY1 41
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#define D1_RST_BUS_OHCI0 42
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@ -1006,6 +1010,7 @@ const struct sxiccmu_ccu_bit sun20i_d1_resets[] = {
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[D1_RST_BUS_UART3] = { 0x090c, 19 },
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[D1_RST_BUS_UART4] = { 0x090c, 20 },
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[D1_RST_BUS_UART5] = { 0x090c, 21 },
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[D1_RST_BUS_EMAC] = { 0x097c, 16 },
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[D1_RST_USB_PHY0] = { 0x0a70, 30 },
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[D1_RST_USB_PHY1] = { 0x0a74, 30 },
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[D1_RST_BUS_OHCI0] = { 0x0a8c, 16 },
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@ -141,10 +141,6 @@ static const struct pci_matchid amdgpu_devices[] = {
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{0x1002, 0x73AF },
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{0x1002, 0x73BF },
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/* Van Gogh */
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{0x1002, 0x1435 }, /* Custom GPU 0932 */
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{0x1002, 0x163F }, /* Custom GPU 0405 */
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/* Yellow Carp */
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{0x1002, 0x164D },
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{0x1002, 0x1681 },
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@ -197,6 +193,14 @@ static const struct pci_matchid amdgpu_devices[] = {
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* display/dc/core/dc_resource.c resource_parse_asic_id()
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*/
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/* GC 9.4.3, APU/dGPU, "Aqua Vanjaram" */
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{0x1002, 0x74a0 }, /* Instinct MI300A APU */
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{0x1002, 0x74a1 }, /* Instinct MI300X dGPU */
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/* GC 10.3.1, DCN 3.0.1, APU, "Van Gogh" */
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{0x1002, 0x1435 }, /* Custom GPU 0932 */
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{0x1002, 0x163f }, /* Custom GPU 0405 */
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/* GC 10.3.6, DCN 3.1.5, APU, Ryzen 7000 "Raphael" */
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{0x1002, 0x164e }, /* Radeon 610M */
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@ -213,7 +217,7 @@ static const struct pci_matchid amdgpu_devices[] = {
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/* GC 11.0.2, DCN 3.2.1, dGPU, "Navi 33" */
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{0x1002, 0x7480 }, /* Radeon RX 7600S, 7700S, 7600M XT,
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7600, Pro W7600 */
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7600, 7600 XT, Pro W7600 */
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{0x1002, 0x7483 }, /* Radeon RX 7600M */
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{0x1002, 0x7489 }, /* Radeon Pro W7500 */
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@ -225,4 +229,5 @@ static const struct pci_matchid amdgpu_devices[] = {
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{0x1002, 0x15c8 }, /* Radeon 740M */
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/* GC 11.5.0, DCN 3.5.0, APU, linux >= 6.7 */
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/* GC 11.5.1, DCN 3.5.0, APU, linux >= 6.9 */
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};
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@ -1,4 +1,4 @@
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/* $OpenBSD: if_ix.c,v 1.209 2024/02/15 10:56:53 mglocker Exp $ */
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/* $OpenBSD: if_ix.c,v 1.211 2024/03/07 17:09:02 jan Exp $ */
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/******************************************************************************
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@ -1932,7 +1932,9 @@ ixgbe_setup_interface(struct ix_softc *sc)
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ifp->if_capabilities |= IFCAP_TSOv4 | IFCAP_TSOv6;
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if (sc->hw.mac.type != ixgbe_mac_82598EB) {
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#ifndef __sparc64__
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ifp->if_xflags |= IFXF_LRO;
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#endif
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ifp->if_capabilities |= IFCAP_LRO;
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}
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@ -3174,10 +3176,10 @@ ixgbe_rxeof(struct rx_ring *rxr)
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if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
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if (rxbuf->fmp) {
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m_freem(rxbuf->fmp);
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rxbuf->fmp = NULL;
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} else {
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m_freem(mp);
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}
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m_freem(mp);
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rxbuf->fmp = NULL;
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rxbuf->buf = NULL;
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goto next_desc;
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}
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@ -3224,6 +3226,8 @@ ixgbe_rxeof(struct rx_ring *rxr)
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sendmp = mp;
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sendmp->m_pkthdr.len = 0;
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sendmp->m_pkthdr.ph_mss = 0;
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} else {
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mp->m_flags &= ~M_PKTHDR;
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}
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sendmp->m_pkthdr.len += mp->m_len;
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/*
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@ -1,4 +1,4 @@
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$OpenBSD: pcidevs,v 1.2067 2024/03/06 00:05:18 jsg Exp $
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$OpenBSD: pcidevs,v 1.2068 2024/03/06 07:01:24 jsg Exp $
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/* $NetBSD: pcidevs,v 1.30 1997/06/24 06:20:24 thorpej Exp $ */
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/*
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@ -2151,6 +2151,8 @@ product ATI NAVI32_2 0x747e Navi 32
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product ATI NAVI33_1 0x7480 Navi 33
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product ATI NAVI33_2 0x7483 Navi 33
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product ATI NAVI33_3 0x7489 Navi 33
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product ATI MI300A 0x74a0 MI300A
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product ATI MI300X 0x74a1 MI300X
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product ATI RADEON_9000IGP 0x7834 Radeon 9000/9100 IGP
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product ATI RADEON_RS350IGP 0x7835 Radeon RS350IGP
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product ATI RS690_HB 0x7910 RS690 Host
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@ -2,7 +2,7 @@
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* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
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*
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* generated from:
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* OpenBSD: pcidevs,v 1.2067 2024/03/06 00:05:18 jsg Exp
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* OpenBSD: pcidevs,v 1.2068 2024/03/06 07:01:24 jsg Exp
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*/
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/* $NetBSD: pcidevs,v 1.30 1997/06/24 06:20:24 thorpej Exp $ */
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@ -2156,6 +2156,8 @@
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#define PCI_PRODUCT_ATI_NAVI33_1 0x7480 /* Navi 33 */
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#define PCI_PRODUCT_ATI_NAVI33_2 0x7483 /* Navi 33 */
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#define PCI_PRODUCT_ATI_NAVI33_3 0x7489 /* Navi 33 */
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#define PCI_PRODUCT_ATI_MI300A 0x74a0 /* MI300A */
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#define PCI_PRODUCT_ATI_MI300X 0x74a1 /* MI300X */
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#define PCI_PRODUCT_ATI_RADEON_9000IGP 0x7834 /* Radeon 9000/9100 IGP */
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#define PCI_PRODUCT_ATI_RADEON_RS350IGP 0x7835 /* Radeon RS350IGP */
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#define PCI_PRODUCT_ATI_RS690_HB 0x7910 /* RS690 Host */
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@ -2,7 +2,7 @@
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* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
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*
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* generated from:
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* OpenBSD: pcidevs,v 1.2067 2024/03/06 00:05:18 jsg Exp
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* OpenBSD: pcidevs,v 1.2068 2024/03/06 07:01:24 jsg Exp
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*/
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|
||||
/* $NetBSD: pcidevs,v 1.30 1997/06/24 06:20:24 thorpej Exp $ */
|
||||
|
|
@ -6743,6 +6743,14 @@ static const struct pci_known_product pci_known_products[] = {
|
|||
PCI_VENDOR_ATI, PCI_PRODUCT_ATI_NAVI33_3,
|
||||
"Navi 33",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_ATI, PCI_PRODUCT_ATI_MI300A,
|
||||
"MI300A",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_ATI, PCI_PRODUCT_ATI_MI300X,
|
||||
"MI300X",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_ATI, PCI_PRODUCT_ATI_RADEON_9000IGP,
|
||||
"Radeon 9000/9100 IGP",
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue