sync with OpenBSD -current
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GPG key ID:
F42C07F07E2E35B7
69 changed files with 3745 additions and 3354 deletions
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@ -1,4 +1,4 @@
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/* $OpenBSD: if_qwz_pci.c,v 1.1 2024/08/14 14:40:46 patrick Exp $ */
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/* $OpenBSD: if_qwz_pci.c,v 1.3 2024/08/16 00:26:54 patrick Exp $ */
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/*
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* Copyright 2023 Stefan Sperling <stsp@openbsd.org>
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@ -116,11 +116,12 @@
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#define ATH12K_PCI_WINDOW_VALUE_MASK GENMASK(24, 19)
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#define ATH12K_PCI_WINDOW_START 0x80000
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#define ATH12K_PCI_WINDOW_RANGE_MASK GENMASK(18, 0)
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#define ATH12K_PCI_WINDOW_STATIC_MASK GENMASK(31, 6)
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/* BAR0 + 4k is always accessible, and no need to force wakeup. */
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#define ATH12K_PCI_ACCESS_ALWAYS_OFF 0xFE0 /* 4K - 32 = 0xFE0 */
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#define TCSR_SOC_HW_VERSION 0x0224
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#define TCSR_SOC_HW_VERSION 0x1b00000
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#define TCSR_SOC_HW_VERSION_MAJOR_MASK GENMASK(11, 8)
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#define TCSR_SOC_HW_VERSION_MINOR_MASK GENMASK(7, 0)
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@ -145,7 +146,7 @@
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#define PCIE_PCIE_PARF_LTSSM 0x1e081b0
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#define PARM_LTSSM_VALUE 0x111
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#define GCC_GCC_PCIE_HOT_RST 0x1e402bc
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#define GCC_GCC_PCIE_HOT_RST 0x1e38338
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#define GCC_GCC_PCIE_HOT_RST_VAL 0x10
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#define PCIE_PCIE_INT_ALL_CLEAR 0x1e08228
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@ -170,6 +171,9 @@
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#define WLAON_QFPROM_PWR_CTRL_REG 0x01f8031c
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#define QFPROM_PWR_CTRL_VDD4BLOW_MASK 0x4
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#define PCI_MHIREGLEN_REG 0x1e0e100
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#define PCI_MHI_REGION_END 0x1e0effc
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/*
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* mhi.h
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*/
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@ -374,11 +378,9 @@ struct qwz_pci_softc {
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struct qwz_dmamem *cmd_ctxt;
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struct qwz_pci_xfer_ring xfer_rings[4];
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#define QWZ_PCI_XFER_RING_LOOPBACK_OUTBOUND 0
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#define QWZ_PCI_XFER_RING_LOOPBACK_INBOUND 1
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#define QWZ_PCI_XFER_RING_IPCR_OUTBOUND 2
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#define QWZ_PCI_XFER_RING_IPCR_INBOUND 3
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struct qwz_pci_xfer_ring xfer_rings[2];
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#define QWZ_PCI_XFER_RING_IPCR_OUTBOUND 0
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#define QWZ_PCI_XFER_RING_IPCR_INBOUND 1
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struct qwz_pci_event_ring event_rings[QWZ_NUM_EVENT_CTX];
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struct qwz_pci_cmd_ring cmd_ring;
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};
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@ -482,28 +484,14 @@ struct qwz_pci_ops {
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};
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static const struct qwz_pci_ops qwz_pci_ops_qca6390 = {
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static const struct qwz_pci_ops qwz_pci_ops_wcn7850 = {
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.wakeup = qwz_pci_bus_wake_up,
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.release = qwz_pci_bus_release,
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#if notyet
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.get_msi_irq = qwz_pci_get_msi_irq,
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#endif
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.window_write32 = qwz_pci_window_write32,
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.window_read32 = qwz_pci_window_read32,
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.alloc_xfer_rings = qwz_pci_alloc_xfer_rings_qca6390,
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};
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static const struct qwz_pci_ops qwz_pci_ops_qcn9074 = {
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.wakeup = NULL,
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.release = NULL,
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#if notyet
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.get_msi_irq = qwz_pci_get_msi_irq,
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#endif
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.window_write32 = qwz_pci_window_write32,
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.window_read32 = qwz_pci_window_read32,
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.alloc_xfer_rings = qwz_pci_alloc_xfer_rings_qcn9074,
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};
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const struct cfattach qwz_pci_ca = {
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sizeof(struct qwz_pci_softc),
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qwz_pci_match,
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@ -512,16 +500,8 @@ const struct cfattach qwz_pci_ca = {
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qwz_activate
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};
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/* XXX pcidev */
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#define PCI_PRODUCT_QUALCOMM_QCA6390 0x1101
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#define PCI_PRODUCT_QUALCOMM_QCN9074 0x1104
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static const struct pci_matchid qwz_pci_devices[] = {
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#if notyet
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{ PCI_VENDOR_QUALCOMM, PCI_PRODUCT_QUALCOMM_QCA6390 },
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{ PCI_VENDOR_QUALCOMM, PCI_PRODUCT_QUALCOMM_QCN9074 },
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#endif
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{ PCI_VENDOR_QUALCOMM, PCI_PRODUCT_QUALCOMM_QCNFA765 }
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{ PCI_VENDOR_QUALCOMM, PCI_PRODUCT_QUALCOMM_WCN7850 }
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};
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int
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@ -535,8 +515,8 @@ qwz_pci_init_qmi_ce_config(struct qwz_softc *sc)
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{
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struct qwz_qmi_ce_cfg *cfg = &sc->qmi_ce_cfg;
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qwz_ce_get_shadow_config(sc, &cfg->shadow_reg_v2,
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&cfg->shadow_reg_v2_len);
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qwz_ce_get_shadow_config(sc, &cfg->shadow_reg_v3,
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&cfg->shadow_reg_v3_len);
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}
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const struct qwz_msi_config qwz_msi_config_one_msi = {
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@ -551,17 +531,6 @@ const struct qwz_msi_config qwz_msi_config_one_msi = {
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};
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const struct qwz_msi_config qwz_msi_config[] = {
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{
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.total_vectors = 32,
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.total_users = 4,
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.users = (struct qwz_msi_user[]) {
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{ .name = "MHI", .num_vectors = 3, .base_vector = 0 },
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{ .name = "CE", .num_vectors = 10, .base_vector = 3 },
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{ .name = "WAKE", .num_vectors = 1, .base_vector = 13 },
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{ .name = "DP", .num_vectors = 18, .base_vector = 14 },
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},
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.hw_rev = ATH12K_HW_QCA6390_HW20,
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},
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{
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.total_vectors = 16,
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.total_users = 3,
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@ -570,38 +539,7 @@ const struct qwz_msi_config qwz_msi_config[] = {
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{ .name = "CE", .num_vectors = 5, .base_vector = 3 },
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{ .name = "DP", .num_vectors = 8, .base_vector = 8 },
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},
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.hw_rev = ATH12K_HW_QCN9074_HW10,
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},
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{
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.total_vectors = 32,
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.total_users = 4,
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.users = (struct qwz_msi_user[]) {
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{ .name = "MHI", .num_vectors = 3, .base_vector = 0 },
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{ .name = "CE", .num_vectors = 10, .base_vector = 3 },
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{ .name = "WAKE", .num_vectors = 1, .base_vector = 13 },
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{ .name = "DP", .num_vectors = 18, .base_vector = 14 },
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},
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.hw_rev = ATH12K_HW_WCN6855_HW20,
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},
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{
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.total_vectors = 32,
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.total_users = 4,
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.users = (struct qwz_msi_user[]) {
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{ .name = "MHI", .num_vectors = 3, .base_vector = 0 },
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{ .name = "CE", .num_vectors = 10, .base_vector = 3 },
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{ .name = "WAKE", .num_vectors = 1, .base_vector = 13 },
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{ .name = "DP", .num_vectors = 18, .base_vector = 14 },
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},
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.hw_rev = ATH12K_HW_WCN6855_HW21,
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},
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{
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.total_vectors = 28,
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.total_users = 2,
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.users = (struct qwz_msi_user[]) {
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{ .name = "CE", .num_vectors = 10, .base_vector = 0 },
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{ .name = "DP", .num_vectors = 18, .base_vector = 10 },
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},
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.hw_rev = ATH12K_HW_WCN6750_HW10,
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.hw_rev = ATH12K_HW_WCN7850_HW20,
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},
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};
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@ -745,7 +683,6 @@ qwz_pci_attach(struct device *parent, struct device *self, void *aux)
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struct ieee80211com *ic = &sc->sc_ic;
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struct ifnet *ifp = &ic->ic_if;
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uint32_t soc_hw_version_major, soc_hw_version_minor;
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const struct qwz_pci_ops *pci_ops;
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struct pci_attach_args *pa = aux;
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pci_intr_handle_t ih;
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pcireg_t memtype, reg;
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@ -885,54 +822,22 @@ qwz_pci_attach(struct device *parent, struct device *self, void *aux)
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pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0);
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switch (PCI_PRODUCT(pa->pa_id)) {
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case PCI_PRODUCT_QUALCOMM_QCA6390:
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qwz_pci_read_hw_version(sc, &soc_hw_version_major,
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&soc_hw_version_minor);
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switch (soc_hw_version_major) {
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case 2:
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sc->sc_hw_rev = ATH12K_HW_QCA6390_HW20;
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break;
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default:
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printf(": unsupported QCA6390 SOC version: %d %d\n",
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soc_hw_version_major, soc_hw_version_minor);
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return;
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}
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pci_ops = &qwz_pci_ops_qca6390;
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psc->max_chan = QWZ_MHI_CONFIG_QCA6390_MAX_CHANNELS;
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break;
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case PCI_PRODUCT_QUALCOMM_QCN9074:
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pci_ops = &qwz_pci_ops_qcn9074;
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sc->sc_hw_rev = ATH12K_HW_QCN9074_HW10;
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psc->max_chan = QWZ_MHI_CONFIG_QCA9074_MAX_CHANNELS;
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break;
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case PCI_PRODUCT_QUALCOMM_QCNFA765:
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case PCI_PRODUCT_QUALCOMM_WCN7850:
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sc->static_window_map = 0;
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psc->sc_pci_ops = &qwz_pci_ops_wcn7850;
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sc->id.bdf_search = ATH12K_BDF_SEARCH_BUS_AND_BOARD;
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qwz_pci_read_hw_version(sc, &soc_hw_version_major,
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&soc_hw_version_minor);
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switch (soc_hw_version_major) {
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case 2:
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switch (soc_hw_version_minor) {
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case 0x00:
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case 0x01:
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sc->sc_hw_rev = ATH12K_HW_WCN6855_HW20;
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break;
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case 0x10:
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case 0x11:
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sc->sc_hw_rev = ATH12K_HW_WCN6855_HW21;
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break;
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default:
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goto unsupported_wcn6855_soc;
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}
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sc->sc_hw_rev = ATH12K_HW_WCN7850_HW20;
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break;
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default:
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unsupported_wcn6855_soc:
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printf(": unsupported WCN6855 SOC version: %d %d\n",
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soc_hw_version_major, soc_hw_version_minor);
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printf(": unknown hardware version found for WCN785: "
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"%d\n", soc_hw_version_major);
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return;
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}
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pci_ops = &qwz_pci_ops_qca6390;
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psc->max_chan = QWZ_MHI_CONFIG_QCA6390_MAX_CHANNELS;
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break;
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default:
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@ -940,9 +845,6 @@ unsupported_wcn6855_soc:
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return;
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}
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/* register PCI ops */
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psc->sc_pci_ops = pci_ops;
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error = qwz_pcic_init_msi_config(sc);
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if (error)
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goto err_pci_free_region;
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@ -1020,8 +922,6 @@ unsupported_wcn6855_soc:
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if (sc->sc_nswq == NULL)
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goto err_ce_free;
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qwz_pci_init_qmi_ce_config(sc);
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error = qwz_pcic_config_irq(sc, pa);
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if (error) {
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printf("%s: failed to config irq: %d\n",
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@ -1227,7 +1127,7 @@ qwz_pci_alloc_xfer_ring(struct qwz_softc *sc, struct qwz_pci_xfer_ring *ring,
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memset(ring->data, 0, sizeof(ring->data));
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for (i = 0; i < ring->num_elements; i++) {
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struct qwz_xfer_data *xfer = &ring->data[i];
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err = bus_dmamap_create(sc->sc_dmat, QWZ_PCI_XFER_MAX_DATA_SIZE,
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1, QWZ_PCI_XFER_MAX_DATA_SIZE, 0, BUS_DMA_NOWAIT,
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&xfer->map);
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@ -1296,18 +1196,6 @@ qwz_pci_alloc_xfer_rings_qca6390(struct qwz_pci_softc *psc)
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struct qwz_softc *sc = &psc->sc_sc;
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int ret;
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ret = qwz_pci_alloc_xfer_ring(sc,
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&psc->xfer_rings[QWZ_PCI_XFER_RING_LOOPBACK_OUTBOUND],
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0, MHI_CHAN_TYPE_OUTBOUND, 0, 32);
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if (ret)
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goto fail;
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ret = qwz_pci_alloc_xfer_ring(sc,
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&psc->xfer_rings[QWZ_PCI_XFER_RING_LOOPBACK_INBOUND],
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1, MHI_CHAN_TYPE_INBOUND, 0, 32);
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if (ret)
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goto fail;
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ret = qwz_pci_alloc_xfer_ring(sc,
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&psc->xfer_rings[QWZ_PCI_XFER_RING_IPCR_OUTBOUND],
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20, MHI_CHAN_TYPE_OUTBOUND, 1, 64);
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@ -1332,18 +1220,6 @@ qwz_pci_alloc_xfer_rings_qcn9074(struct qwz_pci_softc *psc)
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struct qwz_softc *sc = &psc->sc_sc;
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int ret;
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ret = qwz_pci_alloc_xfer_ring(sc,
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&psc->xfer_rings[QWZ_PCI_XFER_RING_LOOPBACK_OUTBOUND],
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0, MHI_CHAN_TYPE_OUTBOUND, 1, 32);
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if (ret)
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goto fail;
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ret = qwz_pci_alloc_xfer_ring(sc,
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&psc->xfer_rings[QWZ_PCI_XFER_RING_LOOPBACK_INBOUND],
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1, MHI_CHAN_TYPE_INBOUND, 1, 32);
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if (ret)
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goto fail;
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ret = qwz_pci_alloc_xfer_ring(sc,
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&psc->xfer_rings[QWZ_PCI_XFER_RING_IPCR_OUTBOUND],
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20, MHI_CHAN_TYPE_OUTBOUND, 1, 32);
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@ -1602,11 +1478,13 @@ qwz_pcic_ext_irq_config(struct qwz_softc *sc, struct pci_attach_args *pa)
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struct qwz_pci_softc *psc = (struct qwz_pci_softc *)sc;
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int i, ret, num_vectors = 0;
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uint32_t msi_data_start = 0;
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uint32_t base_vector = 0;
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uint32_t base_idx, base_vector = 0;
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if (!test_bit(ATH12K_FLAG_MULTI_MSI_VECTORS, sc->sc_flags))
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return 0;
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base_idx = ATH12K_PCI_IRQ_CE0_OFFSET + CE_COUNT_MAX;
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ret = qwz_pcic_get_user_msi_vector(sc, "DP", &num_vectors,
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&msi_data_start, &base_vector);
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if (ret < 0)
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@ -1618,7 +1496,7 @@ qwz_pcic_ext_irq_config(struct qwz_softc *sc, struct pci_attach_args *pa)
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irq_grp->sc = sc;
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irq_grp->grp_id = i;
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#if 0
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#if 0
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init_dummy_netdev(&irq_grp->napi_ndev);
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netif_napi_add(&irq_grp->napi_ndev, &irq_grp->napi,
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ath12k_pcic_ext_grp_napi_poll);
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@ -1635,7 +1513,7 @@ qwz_pcic_ext_irq_config(struct qwz_softc *sc, struct pci_attach_args *pa)
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}
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irq_grp->num_irq = num_irq;
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irq_grp->irqs[0] = ATH12K_PCI_IRQ_DP_OFFSET + i;
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irq_grp->irqs[0] = base_idx + i;
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if (num_irq) {
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int irq_idx = irq_grp->irqs[0];
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@ -1805,13 +1683,13 @@ qwz_pci_bus_release(struct qwz_softc *sc)
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uint32_t
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qwz_pci_get_window_start(struct qwz_softc *sc, uint32_t offset)
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{
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if (!sc->hw_params.static_window_map)
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if (!sc->static_window_map)
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return ATH12K_PCI_WINDOW_START;
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if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < ATH12K_PCI_WINDOW_RANGE_MASK)
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/* if offset lies within DP register range, use 3rd window */
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return 3 * ATH12K_PCI_WINDOW_START;
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else if ((offset ^ HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(sc)) <
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else if ((offset ^ HAL_SEQ_WCSS_UMAC_CE0_SRC_REG) <
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ATH12K_PCI_WINDOW_RANGE_MASK)
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/* if offset lies within CE register range, use 2nd window */
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return 2 * ATH12K_PCI_WINDOW_START;
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@ -1829,6 +1707,12 @@ qwz_pci_select_window(struct qwz_softc *sc, uint32_t offset)
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lockdep_assert_held(&ab_pci->window_lock);
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#endif
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/*
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* Preserve the static window configuration and reset only
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* dynamic window.
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*/
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window |= psc->register_window & ATH12K_PCI_WINDOW_STATIC_MASK;
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|
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if (window != psc->register_window) {
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qwz_pci_write(sc, ATH12K_PCI_WINDOW_REG_ADDRESS,
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ATH12K_PCI_WINDOW_ENABLE_BIT | window);
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|
@ -1837,6 +1721,12 @@ qwz_pci_select_window(struct qwz_softc *sc, uint32_t offset)
|
|||
}
|
||||
}
|
||||
|
||||
static inline bool
|
||||
qwz_pci_is_offset_within_mhi_region(uint32_t offset)
|
||||
{
|
||||
return (offset >= PCI_MHIREGLEN_REG && offset <= PCI_MHI_REGION_END);
|
||||
}
|
||||
|
||||
void
|
||||
qwz_pci_window_write32(struct qwz_softc *sc, uint32_t offset, uint32_t value)
|
||||
{
|
||||
|
|
@ -1849,8 +1739,15 @@ qwz_pci_window_write32(struct qwz_softc *sc, uint32_t offset, uint32_t value)
|
|||
spin_lock_bh(&ab_pci->window_lock);
|
||||
#endif
|
||||
qwz_pci_select_window(sc, offset);
|
||||
qwz_pci_write(sc, window_start +
|
||||
(offset & ATH12K_PCI_WINDOW_RANGE_MASK), value);
|
||||
|
||||
if (qwz_pci_is_offset_within_mhi_region(offset)) {
|
||||
offset = offset - PCI_MHIREGLEN_REG;
|
||||
qwz_pci_write(sc, offset & ATH12K_PCI_WINDOW_RANGE_MASK,
|
||||
value);
|
||||
} else {
|
||||
qwz_pci_write(sc, window_start +
|
||||
(offset & ATH12K_PCI_WINDOW_RANGE_MASK), value);
|
||||
}
|
||||
#if notyet
|
||||
spin_unlock_bh(&ab_pci->window_lock);
|
||||
#endif
|
||||
|
|
@ -1872,8 +1769,15 @@ qwz_pci_window_read32(struct qwz_softc *sc, uint32_t offset)
|
|||
spin_lock_bh(&ab_pci->window_lock);
|
||||
#endif
|
||||
qwz_pci_select_window(sc, offset);
|
||||
val = qwz_pci_read(sc, window_start +
|
||||
(offset & ATH12K_PCI_WINDOW_RANGE_MASK));
|
||||
|
||||
if (qwz_pci_is_offset_within_mhi_region(offset)) {
|
||||
offset = offset - PCI_MHIREGLEN_REG;
|
||||
val = qwz_pci_read(sc,
|
||||
offset & ATH12K_PCI_WINDOW_RANGE_MASK);
|
||||
} else {
|
||||
val = qwz_pci_read(sc, window_start +
|
||||
(offset & ATH12K_PCI_WINDOW_RANGE_MASK));
|
||||
}
|
||||
#if notyet
|
||||
spin_unlock_bh(&ab_pci->window_lock);
|
||||
#endif
|
||||
|
|
@ -2120,7 +2024,7 @@ qwz_pci_msi_config(struct qwz_softc *sc, bool enable)
|
|||
else
|
||||
val &= ~PCI_MSI_MC_MSIE;
|
||||
|
||||
pci_conf_write(psc->sc_pc, psc->sc_tag, psc->sc_msi_off + PCI_MSI_MC,
|
||||
pci_conf_write(psc->sc_pc, psc->sc_tag, psc->sc_msi_off + PCI_MSI_MC,
|
||||
val);
|
||||
}
|
||||
|
||||
|
|
@ -2189,7 +2093,7 @@ qwz_pci_power_up(struct qwz_softc *sc)
|
|||
if (error)
|
||||
return error;
|
||||
|
||||
if (sc->hw_params.static_window_map)
|
||||
if (sc->static_window_map)
|
||||
qwz_pci_select_static_window(sc);
|
||||
|
||||
return 0;
|
||||
|
|
@ -3273,7 +3177,7 @@ qwz_mhi_fw_load_bhi(struct qwz_pci_softc *psc, uint8_t *data, size_t len)
|
|||
qwz_pci_write(sc, psc->bhi_off + MHI_BHI_IMGADDR_LOW,
|
||||
paddr & 0xffffffff);
|
||||
qwz_pci_write(sc, psc->bhi_off + MHI_BHI_IMGSIZE, len);
|
||||
|
||||
|
||||
/* Set a random transaction sequence number. */
|
||||
do {
|
||||
seq = arc4random_uniform(MHI_BHI_TXDB_SEQNUM_BMSK);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue