sync with OpenBSD -current
This commit is contained in:
parent
e247f83c76
commit
b5dda3c267
GPG key ID:
F42C07F07E2E35B7
69 changed files with 3745 additions and 3354 deletions
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@ -3593,6 +3593,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
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rw_init(&adev->grbm_idx_mutex, "grbmidx");
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rw_init(&adev->mn_lock, "agpumn");
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rw_init(&adev->virt.vf_errors.lock, "vferr");
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rw_init(&adev->virt.rlcg_reg_lock, "vrlcg");
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hash_init(adev->mn_hash);
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rw_init(&adev->psp.mutex, "agpsp");
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rw_init(&adev->notifier_lock, "agnf");
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@ -258,9 +258,8 @@ amdgpu_job_prepare_job(struct drm_sched_job *sched_job,
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struct dma_fence *fence = NULL;
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int r;
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/* Ignore soft recovered fences here */
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r = drm_sched_entity_error(s_entity);
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if (r && r != -ENODATA)
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if (r)
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goto error;
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if (!fence && job->gang_submit)
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@ -334,7 +334,7 @@ static ssize_t ta_if_invoke_debugfs_write(struct file *fp, const char *buf, size
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set_ta_context_funcs(psp, ta_type, &context);
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if (!context->initialized) {
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if (!context || !context->initialized) {
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dev_err(adev->dev, "TA is not initialized\n");
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ret = -EINVAL;
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goto err_free_shared_buf;
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@ -1800,12 +1800,15 @@ static void amdgpu_ras_interrupt_process_handler(struct work_struct *work)
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int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
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struct ras_dispatch_if *info)
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{
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struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
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struct ras_ih_data *data = &obj->ih_data;
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struct ras_manager *obj;
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struct ras_ih_data *data;
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obj = amdgpu_ras_find_obj(adev, &info->head);
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if (!obj)
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return -EINVAL;
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data = &obj->ih_data;
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if (data->inuse == 0)
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return 0;
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@ -1004,6 +1004,9 @@ static u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v
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scratch_reg1 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg1;
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scratch_reg2 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg2;
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scratch_reg3 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg3;
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mutex_lock(&adev->virt.rlcg_reg_lock);
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if (reg_access_ctrl->spare_int)
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spare_int = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->spare_int;
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@ -1059,6 +1062,9 @@ static u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v
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}
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ret = readl(scratch_reg0);
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mutex_unlock(&adev->virt.rlcg_reg_lock);
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return ret;
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}
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@ -263,6 +263,8 @@ struct amdgpu_virt {
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/* the ucode id to signal the autoload */
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uint32_t autoload_ucode_id;
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struct rwlock rlcg_reg_lock;
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};
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struct amdgpu_video_codec_info;
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@ -102,6 +102,11 @@ static int amdgpu_vm_sdma_prepare(struct amdgpu_vm_update_params *p,
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if (!r)
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r = amdgpu_sync_push_to_job(&sync, p->job);
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amdgpu_sync_free(&sync);
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if (r) {
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p->num_dw_left = 0;
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amdgpu_job_free(p->job);
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}
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return r;
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}
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@ -2632,7 +2632,8 @@ static int dm_suspend(void *handle)
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dm->cached_dc_state = dc_copy_state(dm->dc->current_state);
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dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
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if (dm->cached_dc_state)
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dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
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amdgpu_dm_commit_zero_streams(dm->dc);
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@ -6487,7 +6488,8 @@ static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
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aconnector->dc_sink = aconnector->dc_link->local_sink ?
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aconnector->dc_link->local_sink :
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aconnector->dc_em_sink;
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dc_sink_retain(aconnector->dc_sink);
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if (aconnector->dc_sink)
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dc_sink_retain(aconnector->dc_sink);
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}
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}
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@ -7300,7 +7302,8 @@ static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
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drm_add_modes_noedid(connector, 1920, 1080);
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} else {
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amdgpu_dm_connector_ddc_get_modes(connector, edid);
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amdgpu_dm_connector_add_common_modes(encoder, connector);
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if (encoder)
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amdgpu_dm_connector_add_common_modes(encoder, connector);
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amdgpu_dm_connector_add_freesync_modes(connector, edid);
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}
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amdgpu_dm_fbc_init(connector);
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@ -1266,6 +1266,9 @@ static bool is_dsc_need_re_compute(
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}
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}
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if (new_stream_on_link_num == 0)
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return false;
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/* check current_state if there stream on link but it is not in
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* new request state
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*/
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@ -162,7 +162,12 @@ static void set_hpo_fixed_vs_pe_retimer_dp_link_test_pattern(struct dc_link *lin
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link_res->hpo_dp_link_enc->funcs->set_link_test_pattern(
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link_res->hpo_dp_link_enc, tp_params);
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}
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link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_SET_SOURCE_PATTERN);
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// Give retimer extra time to lock before updating DP_TRAINING_PATTERN_SET to TPS1
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if (tp_params->dp_phy_pattern == DP_TEST_PATTERN_128b_132b_TPS1_TRAINING_MODE)
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drm_msleep(30);
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}
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static void set_hpo_fixed_vs_pe_retimer_dp_lane_settings(struct dc_link *link,
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@ -927,7 +927,7 @@ static int pp_dpm_switch_power_profile(void *handle,
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enum PP_SMC_POWER_PROFILE type, bool en)
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{
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struct pp_hwmgr *hwmgr = handle;
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long workload;
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long workload[1];
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uint32_t index;
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if (!hwmgr || !hwmgr->pm_en)
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@ -945,12 +945,12 @@ static int pp_dpm_switch_power_profile(void *handle,
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hwmgr->workload_mask &= ~(1 << hwmgr->workload_prority[type]);
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index = fls(hwmgr->workload_mask);
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index = index > 0 && index <= Workload_Policy_Max ? index - 1 : 0;
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workload = hwmgr->workload_setting[index];
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workload[0] = hwmgr->workload_setting[index];
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} else {
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hwmgr->workload_mask |= (1 << hwmgr->workload_prority[type]);
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index = fls(hwmgr->workload_mask);
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index = index <= Workload_Policy_Max ? index - 1 : 0;
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workload = hwmgr->workload_setting[index];
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workload[0] = hwmgr->workload_setting[index];
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}
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if (type == PP_SMC_POWER_PROFILE_COMPUTE &&
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@ -960,7 +960,7 @@ static int pp_dpm_switch_power_profile(void *handle,
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}
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if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
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hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, &workload, 0);
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hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, workload, 0);
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return 0;
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}
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@ -269,7 +269,7 @@ int psm_adjust_power_state_dynamic(struct pp_hwmgr *hwmgr, bool skip_display_set
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struct pp_power_state *new_ps)
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{
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uint32_t index;
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long workload;
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long workload[1];
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if (hwmgr->not_vf) {
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if (!skip_display_settings)
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@ -294,10 +294,10 @@ int psm_adjust_power_state_dynamic(struct pp_hwmgr *hwmgr, bool skip_display_set
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if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
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index = fls(hwmgr->workload_mask);
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index = index > 0 && index <= Workload_Policy_Max ? index - 1 : 0;
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workload = hwmgr->workload_setting[index];
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workload[0] = hwmgr->workload_setting[index];
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if (hwmgr->power_profile_mode != workload && hwmgr->hwmgr_func->set_power_profile_mode)
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hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, &workload, 0);
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if (hwmgr->power_profile_mode != workload[0] && hwmgr->hwmgr_func->set_power_profile_mode)
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hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, workload, 0);
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}
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return 0;
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@ -2957,6 +2957,7 @@ static int smu7_update_edc_leakage_table(struct pp_hwmgr *hwmgr)
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static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
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{
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struct amdgpu_device *adev = hwmgr->adev;
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struct smu7_hwmgr *data;
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int result = 0;
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@ -2993,40 +2994,37 @@ static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
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/* Initalize Dynamic State Adjustment Rule Settings */
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result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
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if (0 == result) {
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struct amdgpu_device *adev = hwmgr->adev;
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if (result)
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goto fail;
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data->is_tlu_enabled = false;
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data->is_tlu_enabled = false;
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hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
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hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
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SMU7_MAX_HARDWARE_POWERLEVELS;
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hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
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hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
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hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
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hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
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data->pcie_gen_cap = adev->pm.pcie_gen_mask;
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if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
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data->pcie_spc_cap = 20;
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else
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data->pcie_spc_cap = 16;
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data->pcie_lane_cap = adev->pm.pcie_mlw_mask;
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data->pcie_gen_cap = adev->pm.pcie_gen_mask;
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if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
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data->pcie_spc_cap = 20;
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else
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data->pcie_spc_cap = 16;
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data->pcie_lane_cap = adev->pm.pcie_mlw_mask;
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hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
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/* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
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hwmgr->platform_descriptor.clockStep.engineClock = 500;
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hwmgr->platform_descriptor.clockStep.memoryClock = 500;
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smu7_thermal_parameter_init(hwmgr);
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} else {
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/* Ignore return value in here, we are cleaning up a mess. */
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smu7_hwmgr_backend_fini(hwmgr);
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}
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hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
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/* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
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hwmgr->platform_descriptor.clockStep.engineClock = 500;
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hwmgr->platform_descriptor.clockStep.memoryClock = 500;
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smu7_thermal_parameter_init(hwmgr);
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result = smu7_update_edc_leakage_table(hwmgr);
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if (result) {
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smu7_hwmgr_backend_fini(hwmgr);
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return result;
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}
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if (result)
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goto fail;
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return 0;
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fail:
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smu7_hwmgr_backend_fini(hwmgr);
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return result;
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}
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static int smu7_force_dpm_highest(struct pp_hwmgr *hwmgr)
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@ -3316,8 +3314,7 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
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const struct pp_power_state *current_ps)
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{
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struct amdgpu_device *adev = hwmgr->adev;
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struct smu7_power_state *smu7_ps =
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cast_phw_smu7_power_state(&request_ps->hardware);
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struct smu7_power_state *smu7_ps;
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uint32_t sclk;
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uint32_t mclk;
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struct PP_Clocks minimum_clocks = {0};
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@ -3334,6 +3331,10 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
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uint32_t latency;
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bool latency_allowed = false;
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smu7_ps = cast_phw_smu7_power_state(&request_ps->hardware);
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if (!smu7_ps)
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return -EINVAL;
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data->battery_state = (PP_StateUILabel_Battery ==
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request_ps->classification.ui_label);
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data->mclk_ignore_signal = false;
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@ -1065,16 +1065,18 @@ static int smu8_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
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struct pp_power_state *prequest_ps,
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const struct pp_power_state *pcurrent_ps)
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{
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struct smu8_power_state *smu8_ps =
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cast_smu8_power_state(&prequest_ps->hardware);
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const struct smu8_power_state *smu8_current_ps =
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cast_const_smu8_power_state(&pcurrent_ps->hardware);
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struct smu8_power_state *smu8_ps;
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const struct smu8_power_state *smu8_current_ps;
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struct smu8_hwmgr *data = hwmgr->backend;
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struct PP_Clocks clocks = {0, 0, 0, 0};
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bool force_high;
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smu8_ps = cast_smu8_power_state(&prequest_ps->hardware);
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smu8_current_ps = cast_const_smu8_power_state(&pcurrent_ps->hardware);
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if (!smu8_ps || !smu8_current_ps)
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return -EINVAL;
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smu8_ps->need_dfs_bypass = true;
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data->battery_state = (PP_StateUILabel_Battery == prequest_ps->classification.ui_label);
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@ -3259,8 +3259,7 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
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const struct pp_power_state *current_ps)
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{
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struct amdgpu_device *adev = hwmgr->adev;
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struct vega10_power_state *vega10_ps =
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cast_phw_vega10_power_state(&request_ps->hardware);
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struct vega10_power_state *vega10_ps;
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uint32_t sclk;
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uint32_t mclk;
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struct PP_Clocks minimum_clocks = {0};
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@ -3278,6 +3277,10 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
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uint32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
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uint32_t latency;
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vega10_ps = cast_phw_vega10_power_state(&request_ps->hardware);
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if (!vega10_ps)
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return -EINVAL;
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data->battery_state = (PP_StateUILabel_Battery ==
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request_ps->classification.ui_label);
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@ -3415,13 +3418,17 @@ static int vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, co
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const struct vega10_power_state *vega10_ps =
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cast_const_phw_vega10_power_state(states->pnew_state);
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struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
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uint32_t sclk = vega10_ps->performance_levels
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[vega10_ps->performance_level_count - 1].gfx_clock;
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struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
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uint32_t mclk = vega10_ps->performance_levels
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[vega10_ps->performance_level_count - 1].mem_clock;
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uint32_t sclk, mclk;
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uint32_t i;
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if (vega10_ps == NULL)
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return -EINVAL;
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sclk = vega10_ps->performance_levels
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[vega10_ps->performance_level_count - 1].gfx_clock;
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mclk = vega10_ps->performance_levels
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[vega10_ps->performance_level_count - 1].mem_clock;
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for (i = 0; i < sclk_table->count; i++) {
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if (sclk == sclk_table->dpm_levels[i].value)
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break;
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@ -3728,6 +3735,9 @@ static int vega10_generate_dpm_level_enable_mask(
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cast_const_phw_vega10_power_state(states->pnew_state);
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int i;
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if (vega10_ps == NULL)
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return -EINVAL;
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PP_ASSERT_WITH_CODE(!vega10_trim_dpm_states(hwmgr, vega10_ps),
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"Attempt to Trim DPM States Failed!",
|
||||
return -1);
|
||||
|
|
@ -4995,6 +5005,8 @@ static int vega10_check_states_equal(struct pp_hwmgr *hwmgr,
|
|||
|
||||
vega10_psa = cast_const_phw_vega10_power_state(pstate1);
|
||||
vega10_psb = cast_const_phw_vega10_power_state(pstate2);
|
||||
if (vega10_psa == NULL || vega10_psb == NULL)
|
||||
return -EINVAL;
|
||||
|
||||
/* If the two states don't even have the same number of performance levels
|
||||
* they cannot be the same state.
|
||||
|
|
@ -5128,6 +5140,8 @@ static int vega10_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
|
|||
return -EINVAL;
|
||||
|
||||
vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
|
||||
if (vega10_ps == NULL)
|
||||
return -EINVAL;
|
||||
|
||||
vega10_ps->performance_levels
|
||||
[vega10_ps->performance_level_count - 1].gfx_clock =
|
||||
|
|
@ -5179,6 +5193,8 @@ static int vega10_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
|
|||
return -EINVAL;
|
||||
|
||||
vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
|
||||
if (vega10_ps == NULL)
|
||||
return -EINVAL;
|
||||
|
||||
vega10_ps->performance_levels
|
||||
[vega10_ps->performance_level_count - 1].mem_clock =
|
||||
|
|
@ -5420,6 +5436,9 @@ static void vega10_odn_update_power_state(struct pp_hwmgr *hwmgr)
|
|||
return;
|
||||
|
||||
vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
|
||||
if (vega10_ps == NULL)
|
||||
return;
|
||||
|
||||
max_level = vega10_ps->performance_level_count - 1;
|
||||
|
||||
if (vega10_ps->performance_levels[max_level].gfx_clock !=
|
||||
|
|
@ -5442,6 +5461,9 @@ static void vega10_odn_update_power_state(struct pp_hwmgr *hwmgr)
|
|||
|
||||
ps = (struct pp_power_state *)((unsigned long)(hwmgr->ps) + hwmgr->ps_size * (hwmgr->num_ps - 1));
|
||||
vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
|
||||
if (vega10_ps == NULL)
|
||||
return;
|
||||
|
||||
max_level = vega10_ps->performance_level_count - 1;
|
||||
|
||||
if (vega10_ps->performance_levels[max_level].gfx_clock !=
|
||||
|
|
@ -5632,6 +5654,8 @@ static int vega10_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_
|
|||
return -EINVAL;
|
||||
|
||||
vega10_ps = cast_const_phw_vega10_power_state(state);
|
||||
if (vega10_ps == NULL)
|
||||
return -EINVAL;
|
||||
|
||||
i = index > vega10_ps->performance_level_count - 1 ?
|
||||
vega10_ps->performance_level_count - 1 : index;
|
||||
|
|
|
|||
|
|
@ -1846,7 +1846,7 @@ static int smu_adjust_power_state_dynamic(struct smu_context *smu,
|
|||
{
|
||||
int ret = 0;
|
||||
int index = 0;
|
||||
long workload;
|
||||
long workload[1];
|
||||
struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
|
||||
|
||||
if (!skip_display_settings) {
|
||||
|
|
@ -1886,10 +1886,10 @@ static int smu_adjust_power_state_dynamic(struct smu_context *smu,
|
|||
smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
|
||||
index = fls(smu->workload_mask);
|
||||
index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
|
||||
workload = smu->workload_setting[index];
|
||||
workload[0] = smu->workload_setting[index];
|
||||
|
||||
if (smu->power_profile_mode != workload)
|
||||
smu_bump_power_profile_mode(smu, &workload, 0);
|
||||
if (smu->power_profile_mode != workload[0])
|
||||
smu_bump_power_profile_mode(smu, workload, 0);
|
||||
}
|
||||
|
||||
return ret;
|
||||
|
|
@ -1939,7 +1939,7 @@ static int smu_switch_power_profile(void *handle,
|
|||
{
|
||||
struct smu_context *smu = handle;
|
||||
struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
|
||||
long workload;
|
||||
long workload[1];
|
||||
uint32_t index;
|
||||
|
||||
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
|
||||
|
|
@ -1952,17 +1952,17 @@ static int smu_switch_power_profile(void *handle,
|
|||
smu->workload_mask &= ~(1 << smu->workload_prority[type]);
|
||||
index = fls(smu->workload_mask);
|
||||
index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
|
||||
workload = smu->workload_setting[index];
|
||||
workload[0] = smu->workload_setting[index];
|
||||
} else {
|
||||
smu->workload_mask |= (1 << smu->workload_prority[type]);
|
||||
index = fls(smu->workload_mask);
|
||||
index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
|
||||
workload = smu->workload_setting[index];
|
||||
workload[0] = smu->workload_setting[index];
|
||||
}
|
||||
|
||||
if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
|
||||
smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)
|
||||
smu_bump_power_profile_mode(smu, &workload, 0);
|
||||
smu_bump_power_profile_mode(smu, workload, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4034,6 +4034,7 @@ static int drm_dp_mst_handle_up_req(struct drm_dp_mst_topology_mgr *mgr)
|
|||
if (up_req->msg.req_type == DP_CONNECTION_STATUS_NOTIFY) {
|
||||
const struct drm_dp_connection_status_notify *conn_stat =
|
||||
&up_req->msg.u.conn_stat;
|
||||
bool handle_csn;
|
||||
|
||||
drm_dbg_kms(mgr->dev, "Got CSN: pn: %d ldps:%d ddps: %d mcs: %d ip: %d pdt: %d\n",
|
||||
conn_stat->port_number,
|
||||
|
|
@ -4042,6 +4043,16 @@ static int drm_dp_mst_handle_up_req(struct drm_dp_mst_topology_mgr *mgr)
|
|||
conn_stat->message_capability_status,
|
||||
conn_stat->input_port,
|
||||
conn_stat->peer_device_type);
|
||||
|
||||
mutex_lock(&mgr->probe_lock);
|
||||
handle_csn = mgr->mst_primary->link_address_sent;
|
||||
mutex_unlock(&mgr->probe_lock);
|
||||
|
||||
if (!handle_csn) {
|
||||
drm_dbg_kms(mgr->dev, "Got CSN before finish topology probing. Skip it.");
|
||||
kfree(up_req);
|
||||
goto out;
|
||||
}
|
||||
} else if (up_req->msg.req_type == DP_RESOURCE_STATUS_NOTIFY) {
|
||||
const struct drm_dp_resource_status_notify *res_stat =
|
||||
&up_req->msg.u.resource_stat;
|
||||
|
|
|
|||
|
|
@ -879,6 +879,11 @@ int drm_client_modeset_probe(struct drm_client_dev *client, unsigned int width,
|
|||
|
||||
kfree(modeset->mode);
|
||||
modeset->mode = drm_mode_duplicate(dev, mode);
|
||||
if (!modeset->mode) {
|
||||
ret = -ENOMEM;
|
||||
break;
|
||||
}
|
||||
|
||||
drm_connector_get(connector);
|
||||
modeset->connectors[modeset->num_connectors++] = connector;
|
||||
modeset->x = offset->x;
|
||||
|
|
|
|||
|
|
@ -325,6 +325,41 @@ out:
|
|||
return i915_error_to_vmf_fault(err);
|
||||
}
|
||||
|
||||
static void set_address_limits(struct vm_area_struct *area,
|
||||
struct i915_vma *vma,
|
||||
unsigned long obj_offset,
|
||||
unsigned long *start_vaddr,
|
||||
unsigned long *end_vaddr)
|
||||
{
|
||||
unsigned long vm_start, vm_end, vma_size; /* user's memory parameters */
|
||||
long start, end; /* memory boundaries */
|
||||
|
||||
/*
|
||||
* Let's move into the ">> PAGE_SHIFT"
|
||||
* domain to be sure not to lose bits
|
||||
*/
|
||||
vm_start = area->vm_start >> PAGE_SHIFT;
|
||||
vm_end = area->vm_end >> PAGE_SHIFT;
|
||||
vma_size = vma->size >> PAGE_SHIFT;
|
||||
|
||||
/*
|
||||
* Calculate the memory boundaries by considering the offset
|
||||
* provided by the user during memory mapping and the offset
|
||||
* provided for the partial mapping.
|
||||
*/
|
||||
start = vm_start;
|
||||
start -= obj_offset;
|
||||
start += vma->gtt_view.partial.offset;
|
||||
end = start + vma_size;
|
||||
|
||||
start = max_t(long, start, vm_start);
|
||||
end = min_t(long, end, vm_end);
|
||||
|
||||
/* Let's move back into the "<< PAGE_SHIFT" domain */
|
||||
*start_vaddr = (unsigned long)start << PAGE_SHIFT;
|
||||
*end_vaddr = (unsigned long)end << PAGE_SHIFT;
|
||||
}
|
||||
|
||||
static vm_fault_t vm_fault_gtt(struct vm_fault *vmf)
|
||||
{
|
||||
#define MIN_CHUNK_PAGES (SZ_1M >> PAGE_SHIFT)
|
||||
|
|
@ -337,14 +372,18 @@ static vm_fault_t vm_fault_gtt(struct vm_fault *vmf)
|
|||
struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
|
||||
bool write = area->vm_flags & VM_WRITE;
|
||||
struct i915_gem_ww_ctx ww;
|
||||
unsigned long obj_offset;
|
||||
unsigned long start, end; /* memory boundaries */
|
||||
intel_wakeref_t wakeref;
|
||||
struct i915_vma *vma;
|
||||
pgoff_t page_offset;
|
||||
unsigned long pfn;
|
||||
int srcu;
|
||||
int ret;
|
||||
|
||||
/* We don't use vmf->pgoff since that has the fake offset */
|
||||
obj_offset = area->vm_pgoff - drm_vma_node_start(&mmo->vma_node);
|
||||
page_offset = (vmf->address - area->vm_start) >> PAGE_SHIFT;
|
||||
page_offset += obj_offset;
|
||||
|
||||
trace_i915_gem_object_fault(obj, page_offset, true, write);
|
||||
|
||||
|
|
@ -437,12 +476,14 @@ retry:
|
|||
if (ret)
|
||||
goto err_unpin;
|
||||
|
||||
set_address_limits(area, vma, obj_offset, &start, &end);
|
||||
|
||||
pfn = (ggtt->gmadr.start + i915_ggtt_offset(vma)) >> PAGE_SHIFT;
|
||||
pfn += (start - area->vm_start) >> PAGE_SHIFT;
|
||||
pfn += obj_offset - vma->gtt_view.partial.offset;
|
||||
|
||||
/* Finally, remap it using the new GTT offset */
|
||||
ret = remap_io_mapping(area,
|
||||
area->vm_start + (vma->gtt_view.partial.offset << PAGE_SHIFT),
|
||||
(ggtt->gmadr.start + i915_ggtt_offset(vma)) >> PAGE_SHIFT,
|
||||
min_t(u64, vma->size, area->vm_end - area->vm_start),
|
||||
&ggtt->iomap);
|
||||
ret = remap_io_mapping(area, start, pfn, end - start, &ggtt->iomap);
|
||||
if (ret)
|
||||
goto err_fence;
|
||||
|
||||
|
|
@ -655,6 +696,41 @@ remap_io_mapping(pmap_t pm, vm_prot_t mapprot,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static void set_address_limits(struct vm_map_entry *entry,
|
||||
struct i915_vma *vma,
|
||||
unsigned long obj_offset,
|
||||
unsigned long *start_vaddr,
|
||||
unsigned long *end_vaddr)
|
||||
{
|
||||
unsigned long vm_start, vm_end, vma_size; /* user's memory parameters */
|
||||
long start, end; /* memory boundaries */
|
||||
|
||||
/*
|
||||
* Let's move into the ">> PAGE_SHIFT"
|
||||
* domain to be sure not to lose bits
|
||||
*/
|
||||
vm_start = entry->start >> PAGE_SHIFT;
|
||||
vm_end = entry->end >> PAGE_SHIFT;
|
||||
vma_size = vma->size >> PAGE_SHIFT;
|
||||
|
||||
/*
|
||||
* Calculate the memory boundaries by considering the offset
|
||||
* provided by the user during memory mapping and the offset
|
||||
* provided for the partial mapping.
|
||||
*/
|
||||
start = vm_start;
|
||||
start -= obj_offset;
|
||||
start += vma->gtt_view.partial.offset;
|
||||
end = start + vma_size;
|
||||
|
||||
start = max_t(long, start, vm_start);
|
||||
end = min_t(long, end, vm_end);
|
||||
|
||||
/* Let's move back into the "<< PAGE_SHIFT" domain */
|
||||
*start_vaddr = (unsigned long)start << PAGE_SHIFT;
|
||||
*end_vaddr = (unsigned long)end << PAGE_SHIFT;
|
||||
}
|
||||
|
||||
static int
|
||||
vm_fault_gtt(struct i915_mmap_offset *mmo, struct uvm_faultinfo *ufi,
|
||||
vaddr_t vaddr, vm_prot_t access_type)
|
||||
|
|
@ -668,13 +744,16 @@ vm_fault_gtt(struct i915_mmap_offset *mmo, struct uvm_faultinfo *ufi,
|
|||
struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
|
||||
int write = !!(access_type & PROT_WRITE);
|
||||
struct i915_gem_ww_ctx ww;
|
||||
unsigned long obj_offset;
|
||||
unsigned long start, end; /* memory boundaries */
|
||||
intel_wakeref_t wakeref;
|
||||
struct i915_vma *vma;
|
||||
pgoff_t page_offset;
|
||||
unsigned long pfn;
|
||||
int srcu;
|
||||
int ret;
|
||||
|
||||
/* We don't use vmf->pgoff since that has the fake offset */
|
||||
obj_offset = entry->offset - drm_vma_node_start(&mmo->vma_node);
|
||||
page_offset = (vaddr - entry->start) >> PAGE_SHIFT;
|
||||
|
||||
trace_i915_gem_object_fault(obj, page_offset, true, write);
|
||||
|
|
@ -768,11 +847,15 @@ retry:
|
|||
if (ret)
|
||||
goto err_unpin;
|
||||
|
||||
set_address_limits(entry, vma, obj_offset, &start, &end);
|
||||
|
||||
pfn = (ggtt->gmadr.start + i915_ggtt_offset(vma)) >> PAGE_SHIFT;
|
||||
pfn += (start - entry->start) >> PAGE_SHIFT;
|
||||
pfn += obj_offset - vma->gtt_view.partial.offset;
|
||||
|
||||
/* Finally, remap it using the new GTT offset */
|
||||
ret = remap_io_mapping(ufi->orig_map->pmap, entry->protection,
|
||||
entry->start + (vma->gtt_view.partial.offset << PAGE_SHIFT),
|
||||
(ggtt->gmadr.start + i915_ggtt_offset(vma)) >> PAGE_SHIFT,
|
||||
min_t(u64, vma->size, entry->end - entry->start));
|
||||
start, pfn, end - start);
|
||||
if (ret)
|
||||
goto err_fence;
|
||||
|
||||
|
|
@ -1507,6 +1590,8 @@ int i915_gem_fb_mmap(struct drm_i915_gem_object *obj, struct vm_area_struct *vma
|
|||
mmo = mmap_offset_attach(obj, mmap_type, NULL);
|
||||
if (IS_ERR(mmo))
|
||||
return PTR_ERR(mmo);
|
||||
|
||||
vma->vm_pgoff += drm_vma_node_start(&mmo->vma_node);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -114,8 +114,8 @@ typedef struct _ATOM_PPLIB_EXTENDEDHEADER
|
|||
USHORT usUVDTableOffset; //points to ATOM_PPLIB_UVD_Table
|
||||
USHORT usSAMUTableOffset; //points to ATOM_PPLIB_SAMU_Table
|
||||
USHORT usPPMTableOffset; //points to ATOM_PPLIB_PPM_Table
|
||||
USHORT usACPTableOffset; //points to ATOM_PPLIB_ACP_Table
|
||||
USHORT usPowerTuneTableOffset; //points to ATOM_PPLIB_POWERTUNE_Table
|
||||
USHORT usACPTableOffset; //points to ATOM_PPLIB_ACP_Table
|
||||
USHORT usPowerTuneTableOffset; //points to ATOM_PPLIB_POWERTUNE_Table
|
||||
} ATOM_PPLIB_EXTENDEDHEADER;
|
||||
|
||||
//// ATOM_PPLIB_POWERPLAYTABLE::ulPlatformCaps
|
||||
|
|
@ -196,14 +196,14 @@ typedef struct _ATOM_PPLIB_POWERPLAYTABLE3
|
|||
typedef struct _ATOM_PPLIB_POWERPLAYTABLE4
|
||||
{
|
||||
ATOM_PPLIB_POWERPLAYTABLE3 basicTable3;
|
||||
ULONG ulGoldenPPID; // PPGen use only
|
||||
ULONG ulGoldenPPID; // PPGen use only
|
||||
ULONG ulGoldenRevision; // PPGen use only
|
||||
USHORT usVddcDependencyOnSCLKOffset;
|
||||
USHORT usVddciDependencyOnMCLKOffset;
|
||||
USHORT usVddcDependencyOnMCLKOffset;
|
||||
USHORT usMaxClockVoltageOnDCOffset;
|
||||
USHORT usVddcPhaseShedLimitsTableOffset; // Points to ATOM_PPLIB_PhaseSheddingLimits_Table
|
||||
USHORT usMvddDependencyOnMCLKOffset;
|
||||
USHORT usMvddDependencyOnMCLKOffset;
|
||||
} ATOM_PPLIB_POWERPLAYTABLE4, *LPATOM_PPLIB_POWERPLAYTABLE4;
|
||||
|
||||
typedef struct _ATOM_PPLIB_POWERPLAYTABLE5
|
||||
|
|
@ -347,23 +347,23 @@ typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO
|
|||
UCHAR ucPadding; // For proper alignment and size.
|
||||
USHORT usVDDC; // For the 780, use: None, Low, High, Variable
|
||||
UCHAR ucMaxHTLinkWidth; // From SBIOS - {2, 4, 8, 16}
|
||||
UCHAR ucMinHTLinkWidth; // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled. Minimum down stream width could
|
||||
UCHAR ucMinHTLinkWidth; // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled. Minimum down stream width could
|
||||
USHORT usHTLinkFreq; // See definition ATOM_PPLIB_RS780_HTLINKFREQ_xxx or in MHz(>=200).
|
||||
ULONG ulFlags;
|
||||
ULONG ulFlags;
|
||||
} ATOM_PPLIB_RS780_CLOCK_INFO;
|
||||
|
||||
#define ATOM_PPLIB_RS780_VOLTAGE_NONE 0
|
||||
#define ATOM_PPLIB_RS780_VOLTAGE_LOW 1
|
||||
#define ATOM_PPLIB_RS780_VOLTAGE_HIGH 2
|
||||
#define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE 3
|
||||
#define ATOM_PPLIB_RS780_VOLTAGE_NONE 0
|
||||
#define ATOM_PPLIB_RS780_VOLTAGE_LOW 1
|
||||
#define ATOM_PPLIB_RS780_VOLTAGE_HIGH 2
|
||||
#define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE 3
|
||||
|
||||
#define ATOM_PPLIB_RS780_SPMCLK_NONE 0 // We cannot change the side port memory clock, leave it as it is.
|
||||
#define ATOM_PPLIB_RS780_SPMCLK_LOW 1
|
||||
#define ATOM_PPLIB_RS780_SPMCLK_HIGH 2
|
||||
|
||||
#define ATOM_PPLIB_RS780_HTLINKFREQ_NONE 0
|
||||
#define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1
|
||||
#define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2
|
||||
#define ATOM_PPLIB_RS780_HTLINKFREQ_NONE 0
|
||||
#define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1
|
||||
#define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2
|
||||
|
||||
typedef struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO
|
||||
{
|
||||
|
|
@ -405,14 +405,14 @@ typedef struct _ATOM_PPLIB_CI_CLOCK_INFO
|
|||
|
||||
USHORT usMemoryClockLow;
|
||||
UCHAR ucMemoryClockHigh;
|
||||
|
||||
|
||||
UCHAR ucPCIEGen;
|
||||
USHORT usPCIELane;
|
||||
} ATOM_PPLIB_CI_CLOCK_INFO;
|
||||
|
||||
typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO{
|
||||
USHORT usEngineClockLow; //clockfrequency & 0xFFFF. The unit is in 10khz
|
||||
UCHAR ucEngineClockHigh; //clockfrequency >> 16.
|
||||
UCHAR ucEngineClockHigh; //clockfrequency >> 16.
|
||||
UCHAR vddcIndex; //2-bit vddc index;
|
||||
USHORT tdpLimit;
|
||||
//please initalize to 0
|
||||
|
|
@ -423,10 +423,10 @@ typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO{
|
|||
|
||||
typedef struct _ATOM_PPLIB_STATE_V2
|
||||
{
|
||||
//number of valid dpm levels in this state; Driver uses it to calculate the whole
|
||||
//number of valid dpm levels in this state; Driver uses it to calculate the whole
|
||||
//size of the state: struct_size(ATOM_PPLIB_STATE_V2, clockInfoIndex, ucNumDPMLevels)
|
||||
UCHAR ucNumDPMLevels;
|
||||
|
||||
|
||||
//a index to the array of nonClockInfos
|
||||
UCHAR nonClockInfoIndex;
|
||||
/**
|
||||
|
|
@ -436,20 +436,20 @@ typedef struct _ATOM_PPLIB_STATE_V2
|
|||
} ATOM_PPLIB_STATE_V2;
|
||||
|
||||
typedef struct _StateArray{
|
||||
//how many states we have
|
||||
//how many states we have
|
||||
UCHAR ucNumEntries;
|
||||
|
||||
ATOM_PPLIB_STATE_V2 states[] __counted_by(ucNumEntries);
|
||||
|
||||
ATOM_PPLIB_STATE_V2 states[] /* __counted_by(ucNumEntries) */;
|
||||
}StateArray;
|
||||
|
||||
|
||||
typedef struct _ClockInfoArray{
|
||||
//how many clock levels we have
|
||||
UCHAR ucNumEntries;
|
||||
|
||||
|
||||
//sizeof(ATOM_PPLIB_CLOCK_INFO)
|
||||
UCHAR ucEntrySize;
|
||||
|
||||
|
||||
UCHAR clockInfo[] __counted_by(ucNumEntries);
|
||||
}ClockInfoArray;
|
||||
|
||||
|
|
@ -459,7 +459,7 @@ typedef struct _NonClockInfoArray{
|
|||
UCHAR ucNumEntries;
|
||||
//sizeof(ATOM_PPLIB_NONCLOCK_INFO)
|
||||
UCHAR ucEntrySize;
|
||||
|
||||
|
||||
ATOM_PPLIB_NONCLOCK_INFO nonClockInfo[] __counted_by(ucNumEntries);
|
||||
}NonClockInfoArray;
|
||||
|
||||
|
|
@ -680,7 +680,7 @@ typedef struct _ATOM_PPLIB_PPM_Table
|
|||
ULONG ulPlatformTDC;
|
||||
ULONG ulSmallACPlatformTDC;
|
||||
ULONG ulApuTDP;
|
||||
ULONG ulDGpuTDP;
|
||||
ULONG ulDGpuTDP;
|
||||
ULONG ulDGpuUlvPower;
|
||||
ULONG ulTjmax;
|
||||
} ATOM_PPLIB_PPM_Table;
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $OpenBSD: if_qwz_pci.c,v 1.1 2024/08/14 14:40:46 patrick Exp $ */
|
||||
/* $OpenBSD: if_qwz_pci.c,v 1.3 2024/08/16 00:26:54 patrick Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright 2023 Stefan Sperling <stsp@openbsd.org>
|
||||
|
|
@ -116,11 +116,12 @@
|
|||
#define ATH12K_PCI_WINDOW_VALUE_MASK GENMASK(24, 19)
|
||||
#define ATH12K_PCI_WINDOW_START 0x80000
|
||||
#define ATH12K_PCI_WINDOW_RANGE_MASK GENMASK(18, 0)
|
||||
#define ATH12K_PCI_WINDOW_STATIC_MASK GENMASK(31, 6)
|
||||
|
||||
/* BAR0 + 4k is always accessible, and no need to force wakeup. */
|
||||
#define ATH12K_PCI_ACCESS_ALWAYS_OFF 0xFE0 /* 4K - 32 = 0xFE0 */
|
||||
|
||||
#define TCSR_SOC_HW_VERSION 0x0224
|
||||
#define TCSR_SOC_HW_VERSION 0x1b00000
|
||||
#define TCSR_SOC_HW_VERSION_MAJOR_MASK GENMASK(11, 8)
|
||||
#define TCSR_SOC_HW_VERSION_MINOR_MASK GENMASK(7, 0)
|
||||
|
||||
|
|
@ -145,7 +146,7 @@
|
|||
#define PCIE_PCIE_PARF_LTSSM 0x1e081b0
|
||||
#define PARM_LTSSM_VALUE 0x111
|
||||
|
||||
#define GCC_GCC_PCIE_HOT_RST 0x1e402bc
|
||||
#define GCC_GCC_PCIE_HOT_RST 0x1e38338
|
||||
#define GCC_GCC_PCIE_HOT_RST_VAL 0x10
|
||||
|
||||
#define PCIE_PCIE_INT_ALL_CLEAR 0x1e08228
|
||||
|
|
@ -170,6 +171,9 @@
|
|||
#define WLAON_QFPROM_PWR_CTRL_REG 0x01f8031c
|
||||
#define QFPROM_PWR_CTRL_VDD4BLOW_MASK 0x4
|
||||
|
||||
#define PCI_MHIREGLEN_REG 0x1e0e100
|
||||
#define PCI_MHI_REGION_END 0x1e0effc
|
||||
|
||||
/*
|
||||
* mhi.h
|
||||
*/
|
||||
|
|
@ -374,11 +378,9 @@ struct qwz_pci_softc {
|
|||
struct qwz_dmamem *cmd_ctxt;
|
||||
|
||||
|
||||
struct qwz_pci_xfer_ring xfer_rings[4];
|
||||
#define QWZ_PCI_XFER_RING_LOOPBACK_OUTBOUND 0
|
||||
#define QWZ_PCI_XFER_RING_LOOPBACK_INBOUND 1
|
||||
#define QWZ_PCI_XFER_RING_IPCR_OUTBOUND 2
|
||||
#define QWZ_PCI_XFER_RING_IPCR_INBOUND 3
|
||||
struct qwz_pci_xfer_ring xfer_rings[2];
|
||||
#define QWZ_PCI_XFER_RING_IPCR_OUTBOUND 0
|
||||
#define QWZ_PCI_XFER_RING_IPCR_INBOUND 1
|
||||
struct qwz_pci_event_ring event_rings[QWZ_NUM_EVENT_CTX];
|
||||
struct qwz_pci_cmd_ring cmd_ring;
|
||||
};
|
||||
|
|
@ -482,28 +484,14 @@ struct qwz_pci_ops {
|
|||
};
|
||||
|
||||
|
||||
static const struct qwz_pci_ops qwz_pci_ops_qca6390 = {
|
||||
static const struct qwz_pci_ops qwz_pci_ops_wcn7850 = {
|
||||
.wakeup = qwz_pci_bus_wake_up,
|
||||
.release = qwz_pci_bus_release,
|
||||
#if notyet
|
||||
.get_msi_irq = qwz_pci_get_msi_irq,
|
||||
#endif
|
||||
.window_write32 = qwz_pci_window_write32,
|
||||
.window_read32 = qwz_pci_window_read32,
|
||||
.alloc_xfer_rings = qwz_pci_alloc_xfer_rings_qca6390,
|
||||
};
|
||||
|
||||
static const struct qwz_pci_ops qwz_pci_ops_qcn9074 = {
|
||||
.wakeup = NULL,
|
||||
.release = NULL,
|
||||
#if notyet
|
||||
.get_msi_irq = qwz_pci_get_msi_irq,
|
||||
#endif
|
||||
.window_write32 = qwz_pci_window_write32,
|
||||
.window_read32 = qwz_pci_window_read32,
|
||||
.alloc_xfer_rings = qwz_pci_alloc_xfer_rings_qcn9074,
|
||||
};
|
||||
|
||||
const struct cfattach qwz_pci_ca = {
|
||||
sizeof(struct qwz_pci_softc),
|
||||
qwz_pci_match,
|
||||
|
|
@ -512,16 +500,8 @@ const struct cfattach qwz_pci_ca = {
|
|||
qwz_activate
|
||||
};
|
||||
|
||||
/* XXX pcidev */
|
||||
#define PCI_PRODUCT_QUALCOMM_QCA6390 0x1101
|
||||
#define PCI_PRODUCT_QUALCOMM_QCN9074 0x1104
|
||||
|
||||
static const struct pci_matchid qwz_pci_devices[] = {
|
||||
#if notyet
|
||||
{ PCI_VENDOR_QUALCOMM, PCI_PRODUCT_QUALCOMM_QCA6390 },
|
||||
{ PCI_VENDOR_QUALCOMM, PCI_PRODUCT_QUALCOMM_QCN9074 },
|
||||
#endif
|
||||
{ PCI_VENDOR_QUALCOMM, PCI_PRODUCT_QUALCOMM_QCNFA765 }
|
||||
{ PCI_VENDOR_QUALCOMM, PCI_PRODUCT_QUALCOMM_WCN7850 }
|
||||
};
|
||||
|
||||
int
|
||||
|
|
@ -535,8 +515,8 @@ qwz_pci_init_qmi_ce_config(struct qwz_softc *sc)
|
|||
{
|
||||
struct qwz_qmi_ce_cfg *cfg = &sc->qmi_ce_cfg;
|
||||
|
||||
qwz_ce_get_shadow_config(sc, &cfg->shadow_reg_v2,
|
||||
&cfg->shadow_reg_v2_len);
|
||||
qwz_ce_get_shadow_config(sc, &cfg->shadow_reg_v3,
|
||||
&cfg->shadow_reg_v3_len);
|
||||
}
|
||||
|
||||
const struct qwz_msi_config qwz_msi_config_one_msi = {
|
||||
|
|
@ -551,17 +531,6 @@ const struct qwz_msi_config qwz_msi_config_one_msi = {
|
|||
};
|
||||
|
||||
const struct qwz_msi_config qwz_msi_config[] = {
|
||||
{
|
||||
.total_vectors = 32,
|
||||
.total_users = 4,
|
||||
.users = (struct qwz_msi_user[]) {
|
||||
{ .name = "MHI", .num_vectors = 3, .base_vector = 0 },
|
||||
{ .name = "CE", .num_vectors = 10, .base_vector = 3 },
|
||||
{ .name = "WAKE", .num_vectors = 1, .base_vector = 13 },
|
||||
{ .name = "DP", .num_vectors = 18, .base_vector = 14 },
|
||||
},
|
||||
.hw_rev = ATH12K_HW_QCA6390_HW20,
|
||||
},
|
||||
{
|
||||
.total_vectors = 16,
|
||||
.total_users = 3,
|
||||
|
|
@ -570,38 +539,7 @@ const struct qwz_msi_config qwz_msi_config[] = {
|
|||
{ .name = "CE", .num_vectors = 5, .base_vector = 3 },
|
||||
{ .name = "DP", .num_vectors = 8, .base_vector = 8 },
|
||||
},
|
||||
.hw_rev = ATH12K_HW_QCN9074_HW10,
|
||||
},
|
||||
{
|
||||
.total_vectors = 32,
|
||||
.total_users = 4,
|
||||
.users = (struct qwz_msi_user[]) {
|
||||
{ .name = "MHI", .num_vectors = 3, .base_vector = 0 },
|
||||
{ .name = "CE", .num_vectors = 10, .base_vector = 3 },
|
||||
{ .name = "WAKE", .num_vectors = 1, .base_vector = 13 },
|
||||
{ .name = "DP", .num_vectors = 18, .base_vector = 14 },
|
||||
},
|
||||
.hw_rev = ATH12K_HW_WCN6855_HW20,
|
||||
},
|
||||
{
|
||||
.total_vectors = 32,
|
||||
.total_users = 4,
|
||||
.users = (struct qwz_msi_user[]) {
|
||||
{ .name = "MHI", .num_vectors = 3, .base_vector = 0 },
|
||||
{ .name = "CE", .num_vectors = 10, .base_vector = 3 },
|
||||
{ .name = "WAKE", .num_vectors = 1, .base_vector = 13 },
|
||||
{ .name = "DP", .num_vectors = 18, .base_vector = 14 },
|
||||
},
|
||||
.hw_rev = ATH12K_HW_WCN6855_HW21,
|
||||
},
|
||||
{
|
||||
.total_vectors = 28,
|
||||
.total_users = 2,
|
||||
.users = (struct qwz_msi_user[]) {
|
||||
{ .name = "CE", .num_vectors = 10, .base_vector = 0 },
|
||||
{ .name = "DP", .num_vectors = 18, .base_vector = 10 },
|
||||
},
|
||||
.hw_rev = ATH12K_HW_WCN6750_HW10,
|
||||
.hw_rev = ATH12K_HW_WCN7850_HW20,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -745,7 +683,6 @@ qwz_pci_attach(struct device *parent, struct device *self, void *aux)
|
|||
struct ieee80211com *ic = &sc->sc_ic;
|
||||
struct ifnet *ifp = &ic->ic_if;
|
||||
uint32_t soc_hw_version_major, soc_hw_version_minor;
|
||||
const struct qwz_pci_ops *pci_ops;
|
||||
struct pci_attach_args *pa = aux;
|
||||
pci_intr_handle_t ih;
|
||||
pcireg_t memtype, reg;
|
||||
|
|
@ -885,54 +822,22 @@ qwz_pci_attach(struct device *parent, struct device *self, void *aux)
|
|||
pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0);
|
||||
|
||||
switch (PCI_PRODUCT(pa->pa_id)) {
|
||||
case PCI_PRODUCT_QUALCOMM_QCA6390:
|
||||
qwz_pci_read_hw_version(sc, &soc_hw_version_major,
|
||||
&soc_hw_version_minor);
|
||||
switch (soc_hw_version_major) {
|
||||
case 2:
|
||||
sc->sc_hw_rev = ATH12K_HW_QCA6390_HW20;
|
||||
break;
|
||||
default:
|
||||
printf(": unsupported QCA6390 SOC version: %d %d\n",
|
||||
soc_hw_version_major, soc_hw_version_minor);
|
||||
return;
|
||||
}
|
||||
|
||||
pci_ops = &qwz_pci_ops_qca6390;
|
||||
psc->max_chan = QWZ_MHI_CONFIG_QCA6390_MAX_CHANNELS;
|
||||
break;
|
||||
case PCI_PRODUCT_QUALCOMM_QCN9074:
|
||||
pci_ops = &qwz_pci_ops_qcn9074;
|
||||
sc->sc_hw_rev = ATH12K_HW_QCN9074_HW10;
|
||||
psc->max_chan = QWZ_MHI_CONFIG_QCA9074_MAX_CHANNELS;
|
||||
break;
|
||||
case PCI_PRODUCT_QUALCOMM_QCNFA765:
|
||||
case PCI_PRODUCT_QUALCOMM_WCN7850:
|
||||
sc->static_window_map = 0;
|
||||
psc->sc_pci_ops = &qwz_pci_ops_wcn7850;
|
||||
sc->id.bdf_search = ATH12K_BDF_SEARCH_BUS_AND_BOARD;
|
||||
qwz_pci_read_hw_version(sc, &soc_hw_version_major,
|
||||
&soc_hw_version_minor);
|
||||
switch (soc_hw_version_major) {
|
||||
case 2:
|
||||
switch (soc_hw_version_minor) {
|
||||
case 0x00:
|
||||
case 0x01:
|
||||
sc->sc_hw_rev = ATH12K_HW_WCN6855_HW20;
|
||||
break;
|
||||
case 0x10:
|
||||
case 0x11:
|
||||
sc->sc_hw_rev = ATH12K_HW_WCN6855_HW21;
|
||||
break;
|
||||
default:
|
||||
goto unsupported_wcn6855_soc;
|
||||
}
|
||||
sc->sc_hw_rev = ATH12K_HW_WCN7850_HW20;
|
||||
break;
|
||||
default:
|
||||
unsupported_wcn6855_soc:
|
||||
printf(": unsupported WCN6855 SOC version: %d %d\n",
|
||||
soc_hw_version_major, soc_hw_version_minor);
|
||||
printf(": unknown hardware version found for WCN785: "
|
||||
"%d\n", soc_hw_version_major);
|
||||
return;
|
||||
}
|
||||
|
||||
pci_ops = &qwz_pci_ops_qca6390;
|
||||
psc->max_chan = QWZ_MHI_CONFIG_QCA6390_MAX_CHANNELS;
|
||||
break;
|
||||
default:
|
||||
|
|
@ -940,9 +845,6 @@ unsupported_wcn6855_soc:
|
|||
return;
|
||||
}
|
||||
|
||||
/* register PCI ops */
|
||||
psc->sc_pci_ops = pci_ops;
|
||||
|
||||
error = qwz_pcic_init_msi_config(sc);
|
||||
if (error)
|
||||
goto err_pci_free_region;
|
||||
|
|
@ -1020,8 +922,6 @@ unsupported_wcn6855_soc:
|
|||
if (sc->sc_nswq == NULL)
|
||||
goto err_ce_free;
|
||||
|
||||
qwz_pci_init_qmi_ce_config(sc);
|
||||
|
||||
error = qwz_pcic_config_irq(sc, pa);
|
||||
if (error) {
|
||||
printf("%s: failed to config irq: %d\n",
|
||||
|
|
@ -1227,7 +1127,7 @@ qwz_pci_alloc_xfer_ring(struct qwz_softc *sc, struct qwz_pci_xfer_ring *ring,
|
|||
memset(ring->data, 0, sizeof(ring->data));
|
||||
for (i = 0; i < ring->num_elements; i++) {
|
||||
struct qwz_xfer_data *xfer = &ring->data[i];
|
||||
|
||||
|
||||
err = bus_dmamap_create(sc->sc_dmat, QWZ_PCI_XFER_MAX_DATA_SIZE,
|
||||
1, QWZ_PCI_XFER_MAX_DATA_SIZE, 0, BUS_DMA_NOWAIT,
|
||||
&xfer->map);
|
||||
|
|
@ -1296,18 +1196,6 @@ qwz_pci_alloc_xfer_rings_qca6390(struct qwz_pci_softc *psc)
|
|||
struct qwz_softc *sc = &psc->sc_sc;
|
||||
int ret;
|
||||
|
||||
ret = qwz_pci_alloc_xfer_ring(sc,
|
||||
&psc->xfer_rings[QWZ_PCI_XFER_RING_LOOPBACK_OUTBOUND],
|
||||
0, MHI_CHAN_TYPE_OUTBOUND, 0, 32);
|
||||
if (ret)
|
||||
goto fail;
|
||||
|
||||
ret = qwz_pci_alloc_xfer_ring(sc,
|
||||
&psc->xfer_rings[QWZ_PCI_XFER_RING_LOOPBACK_INBOUND],
|
||||
1, MHI_CHAN_TYPE_INBOUND, 0, 32);
|
||||
if (ret)
|
||||
goto fail;
|
||||
|
||||
ret = qwz_pci_alloc_xfer_ring(sc,
|
||||
&psc->xfer_rings[QWZ_PCI_XFER_RING_IPCR_OUTBOUND],
|
||||
20, MHI_CHAN_TYPE_OUTBOUND, 1, 64);
|
||||
|
|
@ -1332,18 +1220,6 @@ qwz_pci_alloc_xfer_rings_qcn9074(struct qwz_pci_softc *psc)
|
|||
struct qwz_softc *sc = &psc->sc_sc;
|
||||
int ret;
|
||||
|
||||
ret = qwz_pci_alloc_xfer_ring(sc,
|
||||
&psc->xfer_rings[QWZ_PCI_XFER_RING_LOOPBACK_OUTBOUND],
|
||||
0, MHI_CHAN_TYPE_OUTBOUND, 1, 32);
|
||||
if (ret)
|
||||
goto fail;
|
||||
|
||||
ret = qwz_pci_alloc_xfer_ring(sc,
|
||||
&psc->xfer_rings[QWZ_PCI_XFER_RING_LOOPBACK_INBOUND],
|
||||
1, MHI_CHAN_TYPE_INBOUND, 1, 32);
|
||||
if (ret)
|
||||
goto fail;
|
||||
|
||||
ret = qwz_pci_alloc_xfer_ring(sc,
|
||||
&psc->xfer_rings[QWZ_PCI_XFER_RING_IPCR_OUTBOUND],
|
||||
20, MHI_CHAN_TYPE_OUTBOUND, 1, 32);
|
||||
|
|
@ -1602,11 +1478,13 @@ qwz_pcic_ext_irq_config(struct qwz_softc *sc, struct pci_attach_args *pa)
|
|||
struct qwz_pci_softc *psc = (struct qwz_pci_softc *)sc;
|
||||
int i, ret, num_vectors = 0;
|
||||
uint32_t msi_data_start = 0;
|
||||
uint32_t base_vector = 0;
|
||||
uint32_t base_idx, base_vector = 0;
|
||||
|
||||
if (!test_bit(ATH12K_FLAG_MULTI_MSI_VECTORS, sc->sc_flags))
|
||||
return 0;
|
||||
|
||||
base_idx = ATH12K_PCI_IRQ_CE0_OFFSET + CE_COUNT_MAX;
|
||||
|
||||
ret = qwz_pcic_get_user_msi_vector(sc, "DP", &num_vectors,
|
||||
&msi_data_start, &base_vector);
|
||||
if (ret < 0)
|
||||
|
|
@ -1618,7 +1496,7 @@ qwz_pcic_ext_irq_config(struct qwz_softc *sc, struct pci_attach_args *pa)
|
|||
|
||||
irq_grp->sc = sc;
|
||||
irq_grp->grp_id = i;
|
||||
#if 0
|
||||
#if 0
|
||||
init_dummy_netdev(&irq_grp->napi_ndev);
|
||||
netif_napi_add(&irq_grp->napi_ndev, &irq_grp->napi,
|
||||
ath12k_pcic_ext_grp_napi_poll);
|
||||
|
|
@ -1635,7 +1513,7 @@ qwz_pcic_ext_irq_config(struct qwz_softc *sc, struct pci_attach_args *pa)
|
|||
}
|
||||
|
||||
irq_grp->num_irq = num_irq;
|
||||
irq_grp->irqs[0] = ATH12K_PCI_IRQ_DP_OFFSET + i;
|
||||
irq_grp->irqs[0] = base_idx + i;
|
||||
|
||||
if (num_irq) {
|
||||
int irq_idx = irq_grp->irqs[0];
|
||||
|
|
@ -1805,13 +1683,13 @@ qwz_pci_bus_release(struct qwz_softc *sc)
|
|||
uint32_t
|
||||
qwz_pci_get_window_start(struct qwz_softc *sc, uint32_t offset)
|
||||
{
|
||||
if (!sc->hw_params.static_window_map)
|
||||
if (!sc->static_window_map)
|
||||
return ATH12K_PCI_WINDOW_START;
|
||||
|
||||
if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < ATH12K_PCI_WINDOW_RANGE_MASK)
|
||||
/* if offset lies within DP register range, use 3rd window */
|
||||
return 3 * ATH12K_PCI_WINDOW_START;
|
||||
else if ((offset ^ HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(sc)) <
|
||||
else if ((offset ^ HAL_SEQ_WCSS_UMAC_CE0_SRC_REG) <
|
||||
ATH12K_PCI_WINDOW_RANGE_MASK)
|
||||
/* if offset lies within CE register range, use 2nd window */
|
||||
return 2 * ATH12K_PCI_WINDOW_START;
|
||||
|
|
@ -1829,6 +1707,12 @@ qwz_pci_select_window(struct qwz_softc *sc, uint32_t offset)
|
|||
lockdep_assert_held(&ab_pci->window_lock);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Preserve the static window configuration and reset only
|
||||
* dynamic window.
|
||||
*/
|
||||
window |= psc->register_window & ATH12K_PCI_WINDOW_STATIC_MASK;
|
||||
|
||||
if (window != psc->register_window) {
|
||||
qwz_pci_write(sc, ATH12K_PCI_WINDOW_REG_ADDRESS,
|
||||
ATH12K_PCI_WINDOW_ENABLE_BIT | window);
|
||||
|
|
@ -1837,6 +1721,12 @@ qwz_pci_select_window(struct qwz_softc *sc, uint32_t offset)
|
|||
}
|
||||
}
|
||||
|
||||
static inline bool
|
||||
qwz_pci_is_offset_within_mhi_region(uint32_t offset)
|
||||
{
|
||||
return (offset >= PCI_MHIREGLEN_REG && offset <= PCI_MHI_REGION_END);
|
||||
}
|
||||
|
||||
void
|
||||
qwz_pci_window_write32(struct qwz_softc *sc, uint32_t offset, uint32_t value)
|
||||
{
|
||||
|
|
@ -1849,8 +1739,15 @@ qwz_pci_window_write32(struct qwz_softc *sc, uint32_t offset, uint32_t value)
|
|||
spin_lock_bh(&ab_pci->window_lock);
|
||||
#endif
|
||||
qwz_pci_select_window(sc, offset);
|
||||
qwz_pci_write(sc, window_start +
|
||||
(offset & ATH12K_PCI_WINDOW_RANGE_MASK), value);
|
||||
|
||||
if (qwz_pci_is_offset_within_mhi_region(offset)) {
|
||||
offset = offset - PCI_MHIREGLEN_REG;
|
||||
qwz_pci_write(sc, offset & ATH12K_PCI_WINDOW_RANGE_MASK,
|
||||
value);
|
||||
} else {
|
||||
qwz_pci_write(sc, window_start +
|
||||
(offset & ATH12K_PCI_WINDOW_RANGE_MASK), value);
|
||||
}
|
||||
#if notyet
|
||||
spin_unlock_bh(&ab_pci->window_lock);
|
||||
#endif
|
||||
|
|
@ -1872,8 +1769,15 @@ qwz_pci_window_read32(struct qwz_softc *sc, uint32_t offset)
|
|||
spin_lock_bh(&ab_pci->window_lock);
|
||||
#endif
|
||||
qwz_pci_select_window(sc, offset);
|
||||
val = qwz_pci_read(sc, window_start +
|
||||
(offset & ATH12K_PCI_WINDOW_RANGE_MASK));
|
||||
|
||||
if (qwz_pci_is_offset_within_mhi_region(offset)) {
|
||||
offset = offset - PCI_MHIREGLEN_REG;
|
||||
val = qwz_pci_read(sc,
|
||||
offset & ATH12K_PCI_WINDOW_RANGE_MASK);
|
||||
} else {
|
||||
val = qwz_pci_read(sc, window_start +
|
||||
(offset & ATH12K_PCI_WINDOW_RANGE_MASK));
|
||||
}
|
||||
#if notyet
|
||||
spin_unlock_bh(&ab_pci->window_lock);
|
||||
#endif
|
||||
|
|
@ -2120,7 +2024,7 @@ qwz_pci_msi_config(struct qwz_softc *sc, bool enable)
|
|||
else
|
||||
val &= ~PCI_MSI_MC_MSIE;
|
||||
|
||||
pci_conf_write(psc->sc_pc, psc->sc_tag, psc->sc_msi_off + PCI_MSI_MC,
|
||||
pci_conf_write(psc->sc_pc, psc->sc_tag, psc->sc_msi_off + PCI_MSI_MC,
|
||||
val);
|
||||
}
|
||||
|
||||
|
|
@ -2189,7 +2093,7 @@ qwz_pci_power_up(struct qwz_softc *sc)
|
|||
if (error)
|
||||
return error;
|
||||
|
||||
if (sc->hw_params.static_window_map)
|
||||
if (sc->static_window_map)
|
||||
qwz_pci_select_static_window(sc);
|
||||
|
||||
return 0;
|
||||
|
|
@ -3273,7 +3177,7 @@ qwz_mhi_fw_load_bhi(struct qwz_pci_softc *psc, uint8_t *data, size_t len)
|
|||
qwz_pci_write(sc, psc->bhi_off + MHI_BHI_IMGADDR_LOW,
|
||||
paddr & 0xffffffff);
|
||||
qwz_pci_write(sc, psc->bhi_off + MHI_BHI_IMGSIZE, len);
|
||||
|
||||
|
||||
/* Set a random transaction sequence number. */
|
||||
do {
|
||||
seq = arc4random_uniform(MHI_BHI_TXDB_SEQNUM_BMSK);
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
$OpenBSD: pcidevs,v 1.2083 2024/08/10 11:00:14 jsg Exp $
|
||||
$OpenBSD: pcidevs,v 1.2084 2024/08/15 11:25:37 patrick Exp $
|
||||
/* $NetBSD: pcidevs,v 1.30 1997/06/24 06:20:24 thorpej Exp $ */
|
||||
|
||||
/*
|
||||
|
|
@ -8645,6 +8645,7 @@ product QLOGIC ISP8432 0x8432 ISP8432
|
|||
product QUALCOMM SC8280XP_PCIE 0x010e SC8280XP PCIe
|
||||
product QUALCOMM X1E80100_PCIE 0x0111 X1E80100 PCIe
|
||||
product QUALCOMM QCNFA765 0x1103 QCNFA765
|
||||
product QUALCOMM WCN7850 0x1107 WCN7850
|
||||
|
||||
/* Quancom products */
|
||||
product QUANCOM PWDOG1 0x0010 PWDOG1
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
|
||||
*
|
||||
* generated from:
|
||||
* OpenBSD: pcidevs,v 1.2083 2024/08/10 11:00:14 jsg Exp
|
||||
* OpenBSD: pcidevs,v 1.2084 2024/08/15 11:25:37 patrick Exp
|
||||
*/
|
||||
/* $NetBSD: pcidevs,v 1.30 1997/06/24 06:20:24 thorpej Exp $ */
|
||||
|
||||
|
|
@ -8650,6 +8650,7 @@
|
|||
#define PCI_PRODUCT_QUALCOMM_SC8280XP_PCIE 0x010e /* SC8280XP PCIe */
|
||||
#define PCI_PRODUCT_QUALCOMM_X1E80100_PCIE 0x0111 /* X1E80100 PCIe */
|
||||
#define PCI_PRODUCT_QUALCOMM_QCNFA765 0x1103 /* QCNFA765 */
|
||||
#define PCI_PRODUCT_QUALCOMM_WCN7850 0x1107 /* WCN7850 */
|
||||
|
||||
/* Quancom products */
|
||||
#define PCI_PRODUCT_QUANCOM_PWDOG1 0x0010 /* PWDOG1 */
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
|
||||
*
|
||||
* generated from:
|
||||
* OpenBSD: pcidevs,v 1.2083 2024/08/10 11:00:14 jsg Exp
|
||||
* OpenBSD: pcidevs,v 1.2084 2024/08/15 11:25:37 patrick Exp
|
||||
*/
|
||||
|
||||
/* $NetBSD: pcidevs,v 1.30 1997/06/24 06:20:24 thorpej Exp $ */
|
||||
|
|
@ -31207,6 +31207,10 @@ static const struct pci_known_product pci_known_products[] = {
|
|||
PCI_VENDOR_QUALCOMM, PCI_PRODUCT_QUALCOMM_QCNFA765,
|
||||
"QCNFA765",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_QUALCOMM, PCI_PRODUCT_QUALCOMM_WCN7850,
|
||||
"WCN7850",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_QUANCOM, PCI_PRODUCT_QUANCOM_PWDOG1,
|
||||
"PWDOG1",
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue