sync with OpenBSD -current
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GPG key ID:
F42C07F07E2E35B7
69 changed files with 3745 additions and 3354 deletions
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@ -1,4 +1,4 @@
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/* $OpenBSD: acpisurface.c,v 1.2 2022/04/06 18:59:27 naddy Exp $ */
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/* $OpenBSD: acpisurface.c,v 1.3 2024/08/15 17:30:40 deraadt Exp $ */
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/*
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* Copyright (c) 2018 Mike Larkin <mlarkin@openbsd.org>
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*
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@ -136,7 +136,7 @@ surface_hotkey(struct aml_node *node, int notify_type, void *arg)
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case SURFACE_POWER_BUTTON_RELEASED:
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DPRINTF("%s: power button released\n", __func__);
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acpi_addtask(sc->sc_acpi, acpi_powerdown_task,
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sc->sc_acpi, 0);
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sc->sc_acpi, 0);
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break;
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case SURFACE_WINDOWS_KEY_PRESSED:
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DPRINTF("%s: windows key pressed\n", __func__);
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3464
sys/dev/ic/qwz.c
3464
sys/dev/ic/qwz.c
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
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@ -1,4 +1,4 @@
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/* $OpenBSD: qwzvar.h,v 1.1 2024/08/14 14:40:46 patrick Exp $ */
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/* $OpenBSD: qwzvar.h,v 1.4 2024/08/16 00:26:54 patrick Exp $ */
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/*
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* Copyright (c) 2018-2019 The Linux Foundation.
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@ -64,6 +64,7 @@ struct ath12k_hw_ring_mask {
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uint8_t reo_status[ATH12K_EXT_IRQ_GRP_NUM_MAX];
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uint8_t rxdma2host[ATH12K_EXT_IRQ_GRP_NUM_MAX];
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uint8_t host2rxdma[ATH12K_EXT_IRQ_GRP_NUM_MAX];
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uint8_t tx_mon_dest[ATH12K_EXT_IRQ_GRP_NUM_MAX];
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};
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#define ATH12K_FW_DIR "qwz"
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@ -74,7 +75,6 @@ struct ath12k_hw_ring_mask {
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#define ATH12K_DEFAULT_CAL_FILE "caldata"
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#define ATH12K_AMSS_FILE "amss"
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#define ATH12K_M3_FILE "m3"
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#define ATH12K_REGDB_FILE "regdb"
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#define QWZ_FW_BUILD_ID_MASK "QC_IMAGE_VERSION_STRING="
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@ -88,29 +88,36 @@ struct ath12k_hw_tcl2wbm_rbm_map {
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* enum hal_rx_buf_return_buf_manager
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*
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* @HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST: Buffer returned to WBM idle buffer list
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* @HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST: Descriptor returned to WBM idle
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* descriptor list.
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* @HAL_RX_BUF_RBM_WBM_CHIP0_IDLE_DESC_LIST: Descriptor returned to WBM idle
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* descriptor list, where the chip 0 WBM is chosen in case of a
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* multi-chip config
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* @HAL_RX_BUF_RBM_FW_BM: Buffer returned to FW
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* @HAL_RX_BUF_RBM_SW0_BM: For Tx completion -- returned to host
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* @HAL_RX_BUF_RBM_SW1_BM: For Tx completion -- returned to host
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* @HAL_RX_BUF_RBM_SW2_BM: For Tx completion -- returned to host
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* @HAL_RX_BUF_RBM_SW3_BM: For Rx release -- returned to host
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* @HAL_RX_BUF_RBM_SW4_BM: For Tx completion -- returned to host
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* @HAL_RX_BUF_RBM_SW5_BM: For ring 5 -- returned to host
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* @HAL_RX_BUF_RBM_SW6_BM: For ring 6 -- returned to host
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*/
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enum hal_rx_buf_return_buf_manager {
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HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST,
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HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST,
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HAL_RX_BUF_RBM_WBM_CHIP0_IDLE_DESC_LIST,
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HAL_RX_BUF_RBM_FW_BM,
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HAL_RX_BUF_RBM_SW0_BM,
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HAL_RX_BUF_RBM_SW1_BM,
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HAL_RX_BUF_RBM_SW2_BM,
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HAL_RX_BUF_RBM_SW3_BM,
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HAL_RX_BUF_RBM_SW4_BM,
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HAL_RX_BUF_RBM_SW5_BM,
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HAL_RX_BUF_RBM_SW6_BM,
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};
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struct ath12k_hw_hal_params {
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enum hal_rx_buf_return_buf_manager rx_buf_rbm;
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const struct ath12k_hw_tcl2wbm_rbm_map *tcl2wbm_rbm_map;
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uint32_t wbm2sw_cc_enable;
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};
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struct hal_tx_info {
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@ -190,6 +197,7 @@ struct ath12k_hw_params {
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bool rxdma1_enable;
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int num_rxmda_per_pdev;
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int num_rxdma_dst_ring;
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bool rx_mac_buf_ring;
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bool vdev_start_delay;
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bool htt_peer_map_v2;
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@ -210,37 +218,24 @@ struct ath12k_hw_params {
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bool supports_shadow_regs;
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bool idle_ps;
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bool supports_sta_ps;
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bool cold_boot_calib;
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bool cbcal_restart_fw;
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int fw_mem_mode;
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uint32_t num_vdevs;
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uint32_t num_peers;
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bool supports_suspend;
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uint32_t hal_desc_sz;
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bool supports_regdb;
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bool fix_l1ss;
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bool credit_flow;
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uint8_t max_tx_ring;
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const struct ath12k_hw_hal_params *hal_params;
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uint64_t qmi_cnss_feature_bitmap;
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#if notyet
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bool supports_dynamic_smps_6ghz;
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bool alloc_cacheable_memory;
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bool supports_rssi_stats;
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#endif
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bool fw_wmi_diag_event;
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bool current_cc_support;
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bool dbr_debug_support;
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bool global_reset;
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#ifdef notyet
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const struct cfg80211_sar_capa *bios_sar_capa;
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#endif
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bool m3_fw_support;
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bool fixed_bdf_addr;
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bool fixed_mem_region;
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bool static_window_map;
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bool hybrid_bus_type;
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bool fixed_fw_mem;
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#if notyet
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bool support_off_channel_tx;
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bool supports_multi_bssid;
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@ -312,21 +307,9 @@ struct ath12k_hw_ops {
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#endif
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};
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extern const struct ath12k_hw_ops ipq8074_ops;
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extern const struct ath12k_hw_ops ipq6018_ops;
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extern const struct ath12k_hw_ops qca6390_ops;
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extern const struct ath12k_hw_ops qcn9074_ops;
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extern const struct ath12k_hw_ops wcn6855_ops;
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extern const struct ath12k_hw_ops wcn6750_ops;
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extern const struct ath12k_hw_ring_mask ath12k_hw_ring_mask_ipq8074;
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extern const struct ath12k_hw_ring_mask ath12k_hw_ring_mask_qca6390;
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extern const struct ath12k_hw_ring_mask ath12k_hw_ring_mask_qcn9074;
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extern const struct ath12k_hw_ring_mask ath12k_hw_ring_mask_wcn6750;
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extern const struct ath12k_hw_ring_mask ath12k_hw_ring_mask_wcn7850;
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struct ath12k_hw_regs {
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uint32_t hal_tcl1_ring_base_lsb;
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uint32_t hal_tcl1_ring_base_msb;
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uint32_t hal_tcl1_ring_id;
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uint32_t hal_tcl1_ring_misc;
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uint32_t hal_tcl1_ring_tp_addr_lsb;
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@ -336,11 +319,38 @@ struct ath12k_hw_regs {
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uint32_t hal_tcl1_ring_msi1_base_lsb;
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uint32_t hal_tcl1_ring_msi1_base_msb;
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uint32_t hal_tcl1_ring_msi1_data;
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uint32_t hal_tcl2_ring_base_lsb;
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uint32_t hal_tcl_ring_base_lsb;
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uint32_t hal_tcl_status_ring_base_lsb;
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uint32_t hal_wbm_idle_ring_base_lsb;
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uint32_t hal_wbm_idle_ring_misc_addr;
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uint32_t hal_wbm_r0_idle_list_cntl_addr;
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uint32_t hal_wbm_r0_idle_list_size_addr;
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uint32_t hal_wbm_scattered_ring_base_lsb;
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uint32_t hal_wbm_scattered_ring_base_msb;
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uint32_t hal_wbm_scattered_desc_head_info_ix0;
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uint32_t hal_wbm_scattered_desc_head_info_ix1;
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uint32_t hal_wbm_scattered_desc_tail_info_ix0;
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uint32_t hal_wbm_scattered_desc_tail_info_ix1;
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uint32_t hal_wbm_scattered_desc_ptr_hp_addr;
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uint32_t hal_wbm_sw_release_ring_base_lsb;
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uint32_t hal_wbm_sw1_release_ring_base_lsb;
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uint32_t hal_wbm0_release_ring_base_lsb;
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uint32_t hal_wbm1_release_ring_base_lsb;
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uint32_t pcie_qserdes_sysclk_en_sel;
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uint32_t pcie_pcs_osc_dtct_config_base;
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uint32_t hal_ppe_rel_ring_base;
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uint32_t hal_reo2_ring_base;
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uint32_t hal_reo1_misc_ctrl_addr;
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uint32_t hal_reo1_sw_cookie_cfg0;
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uint32_t hal_reo1_sw_cookie_cfg1;
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uint32_t hal_reo1_qdesc_lut_base0;
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uint32_t hal_reo1_qdesc_lut_base1;
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uint32_t hal_reo1_ring_base_lsb;
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uint32_t hal_reo1_ring_base_msb;
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uint32_t hal_reo1_ring_id;
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@ -351,53 +361,22 @@ struct ath12k_hw_regs {
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uint32_t hal_reo1_ring_msi1_base_lsb;
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uint32_t hal_reo1_ring_msi1_base_msb;
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uint32_t hal_reo1_ring_msi1_data;
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uint32_t hal_reo2_ring_base_lsb;
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uint32_t hal_reo1_aging_thresh_ix_0;
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uint32_t hal_reo1_aging_thresh_ix_1;
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uint32_t hal_reo1_aging_thresh_ix_2;
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uint32_t hal_reo1_aging_thresh_ix_3;
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uint32_t hal_reo1_aging_thres_ix0;
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uint32_t hal_reo1_aging_thres_ix1;
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uint32_t hal_reo1_aging_thres_ix2;
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uint32_t hal_reo1_aging_thres_ix3;
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uint32_t hal_reo1_ring_hp;
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uint32_t hal_reo1_ring_tp;
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uint32_t hal_reo2_ring_hp;
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uint32_t hal_reo2_sw0_ring_base;
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uint32_t hal_reo_tcl_ring_base_lsb;
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uint32_t hal_reo_tcl_ring_hp;
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uint32_t hal_sw2reo_ring_base;
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uint32_t hal_sw2reo1_ring_base;
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uint32_t hal_reo_status_ring_base_lsb;
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uint32_t hal_reo_status_hp;
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uint32_t hal_reo_cmd_ring_base;
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uint32_t hal_reo_cmd_ring_base_lsb;
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uint32_t hal_reo_cmd_ring_hp;
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uint32_t hal_sw2reo_ring_base_lsb;
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uint32_t hal_sw2reo_ring_hp;
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uint32_t hal_seq_wcss_umac_ce0_src_reg;
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uint32_t hal_seq_wcss_umac_ce0_dst_reg;
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uint32_t hal_seq_wcss_umac_ce1_src_reg;
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uint32_t hal_seq_wcss_umac_ce1_dst_reg;
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uint32_t hal_wbm_idle_link_ring_base_lsb;
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uint32_t hal_wbm_idle_link_ring_misc;
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uint32_t hal_wbm_release_ring_base_lsb;
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uint32_t hal_wbm0_release_ring_base_lsb;
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uint32_t hal_wbm1_release_ring_base_lsb;
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uint32_t pcie_qserdes_sysclk_en_sel;
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uint32_t pcie_pcs_osc_dtct_config_base;
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uint32_t hal_shadow_base_addr;
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uint32_t hal_reo1_misc_ctl;
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uint32_t hal_reo_status_ring_base;
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};
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extern const struct ath12k_hw_regs ipq8074_regs;
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extern const struct ath12k_hw_regs qca6390_regs;
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extern const struct ath12k_hw_regs qcn9074_regs;
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extern const struct ath12k_hw_regs wcn6855_regs;
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extern const struct ath12k_hw_regs wcn6750_regs;
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extern const struct ath12k_hw_regs wcn7850_regs;
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enum ath12k_dev_flags {
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ATH12K_CAC_RUNNING,
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@ -647,9 +626,19 @@ enum hal_ring_type {
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HAL_RXDMA_MONITOR_DST,
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HAL_RXDMA_MONITOR_DESC,
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HAL_RXDMA_DIR_BUF,
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HAL_PPE2TCL,
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HAL_PPE_RELEASE,
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HAL_TX_MONITOR_BUF,
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HAL_TX_MONITOR_DST,
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HAL_MAX_RING_TYPES,
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};
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enum hal_srng_mac_type {
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ATH12K_HAL_SRNG_UMAC,
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ATH12K_HAL_SRNG_DMAC,
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ATH12K_HAL_SRNG_PMAC
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};
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/* HW SRNG configuration table */
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struct hal_srng_config {
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int start_ring_id;
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@ -657,7 +646,7 @@ struct hal_srng_config {
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uint16_t entry_size;
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uint32_t reg_start[HAL_SRNG_NUM_REG_GRP];
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uint16_t reg_size[HAL_SRNG_NUM_REG_GRP];
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uint8_t lmac_ring;
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enum hal_srng_mac_type mac_type;
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enum hal_srng_dir ring_dir;
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uint32_t max_size;
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};
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@ -767,7 +756,7 @@ struct ath12k_hal {
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struct hal_srng srng_list[HAL_SRNG_RING_ID_MAX];
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/* SRNG configuration table */
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struct hal_srng_config srng_config[QWZ_NUM_SRNG_CFG];
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struct hal_srng_config *srng_config;
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/* Remote pointer memory for HW/FW updates */
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struct qwz_dmamem *rdpmem;
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@ -837,7 +826,6 @@ struct ce_attr {
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unsigned int dest_nentries;
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void (*recv_cb)(struct qwz_softc *, struct mbuf *);
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void (*send_cb)(struct qwz_softc *, struct mbuf *);
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};
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#define CE_DESC_RING_ALIGN 8
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@ -912,7 +900,7 @@ struct qwz_ce_ring {
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uint32_t hal_ring_id;
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/*
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* Per-transfer data.
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* Per-transfer data.
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* Size and type of this data depends on how the ring is used.
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*
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* For transfers using DMA, the context contains pointers to
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@ -982,6 +970,12 @@ struct qwz_dp_htt_wbm_tx_status {
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#define DP_RXDMA_MONITOR_BUF_RING_SIZE 4096
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#define DP_RXDMA_MONITOR_DST_RING_SIZE 2048
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#define DP_RXDMA_MONITOR_DESC_RING_SIZE 4096
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#define DP_TX_MONITOR_BUF_RING_SIZE 4096
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#define DP_TX_MONITOR_DEST_RING_SIZE 2048
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#define DP_TX_MONITOR_BUF_SIZE 2048
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#define DP_TX_MONITOR_BUF_SIZE_MIN 48
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#define DP_TX_MONITOR_BUF_SIZE_MAX 8192
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#define DP_RX_RELEASE_RING_NUM 3
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@ -999,6 +993,74 @@ struct qwz_dp_htt_wbm_tx_status {
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#define DP_TX_DESC_ID_MSDU_ID GENMASK(18, 2)
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#define DP_TX_DESC_ID_POOL_ID GENMASK(20, 19)
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#define ATH12K_NUM_POOL_TX_DESC 32768
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/* TODO: revisit this count during testing */
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#define ATH12K_RX_DESC_COUNT (12288)
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#define ATH12K_PAGE_SIZE PAGE_SIZE
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/* Total 1024 entries in PPT, i.e 4K/4 considering 4K aligned
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* SPT pages which makes lower 12bits 0
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*/
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#define ATH12K_MAX_PPT_ENTRIES 1024
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/* Total 512 entries in a SPT, i.e 4K Page/8 */
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#define ATH12K_MAX_SPT_ENTRIES 512
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#define ATH12K_NUM_RX_SPT_PAGES ((ATH12K_RX_DESC_COUNT) / ATH12K_MAX_SPT_ENTRIES)
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#define ATH12K_TX_SPT_PAGES_PER_POOL (ATH12K_NUM_POOL_TX_DESC / \
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ATH12K_MAX_SPT_ENTRIES)
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#define ATH12K_NUM_TX_SPT_PAGES (ATH12K_TX_SPT_PAGES_PER_POOL * ATH12K_HW_MAX_QUEUES)
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#define ATH12K_NUM_SPT_PAGES (ATH12K_NUM_RX_SPT_PAGES + ATH12K_NUM_TX_SPT_PAGES)
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#define ATH12K_TX_SPT_PAGE_OFFSET 0
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#define ATH12K_RX_SPT_PAGE_OFFSET ATH12K_NUM_TX_SPT_PAGES
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/* The SPT pages are divided for RX and TX, first block for RX
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* and remaining for TX
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*/
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#define ATH12K_NUM_TX_SPT_PAGE_START ATH12K_NUM_RX_SPT_PAGES
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#define ATH12K_DP_RX_DESC_MAGIC 0xBABABABA
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/* 4K aligned address have last 12 bits set to 0, this check is done
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* so that two spt pages address can be stored per 8bytes
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* of CMEM (PPT)
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*/
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#define ATH12K_SPT_4K_ALIGN_CHECK 0xFFF
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#define ATH12K_SPT_4K_ALIGN_OFFSET 12
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#define ATH12K_PPT_ADDR_OFFSET(ppt_index) (4 * (ppt_index))
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/* To indicate HW of CMEM address, b0-31 are cmem base received via QMI */
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#define ATH12K_CMEM_ADDR_MSB 0x10
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/* Of 20 bits cookie, b0-b8 is to indicate SPT offset and b9-19 for PPT */
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||||
#define ATH12K_CC_SPT_MSB 8
|
||||
#define ATH12K_CC_PPT_MSB 19
|
||||
#define ATH12K_CC_PPT_SHIFT 9
|
||||
#define ATH12K_DP_CC_COOKIE_SPT GENMASK(8, 0)
|
||||
#define ATH12K_DP_CC_COOKIE_PPT GENMASK(19, 9)
|
||||
|
||||
#define DP_REO_QREF_NUM GENMASK(31, 16)
|
||||
#define DP_MAX_PEER_ID 2047
|
||||
|
||||
/* Total size of the LUT is based on 2K peers, each having reference
|
||||
* for 17tids, note each entry is of type ath12k_reo_queue_ref
|
||||
* hence total size is 2048 * 17 * 8 = 278528
|
||||
*/
|
||||
#define DP_REOQ_LUT_SIZE 278528
|
||||
|
||||
/* Invalid TX Bank ID value */
|
||||
#define DP_INVALID_BANK_ID -1
|
||||
|
||||
struct ath12k_dp_tx_bank_profile {
|
||||
uint8_t is_configured;
|
||||
uint32_t num_users;
|
||||
uint32_t bank_config;
|
||||
};
|
||||
|
||||
struct qwz_hp_update_timer {
|
||||
struct timeout timer;
|
||||
int started;
|
||||
|
|
@ -1010,6 +1072,29 @@ struct qwz_hp_update_timer {
|
|||
struct qwz_softc *sc;
|
||||
};
|
||||
|
||||
struct ath12k_rx_desc_info {
|
||||
TAILQ_ENTRY(ath12k_rx_desc_info) entry;
|
||||
// struct sk_buff *skb;
|
||||
uint32_t cookie;
|
||||
uint32_t magic;
|
||||
uint8_t in_use : 1,
|
||||
reserved : 7;
|
||||
};
|
||||
|
||||
struct ath12k_tx_desc_info {
|
||||
TAILQ_ENTRY(ath12k_tx_desc_info) entry;
|
||||
// struct sk_buff *skb;
|
||||
uint32_t desc_id; /* Cookie */
|
||||
uint8_t mac_id;
|
||||
uint8_t pool_id;
|
||||
};
|
||||
|
||||
struct ath12k_spt_info {
|
||||
struct qwz_dmamem *mem;
|
||||
struct ath12k_rx_desc_info *rxbaddr[ATH12K_NUM_RX_SPT_PAGES];
|
||||
struct ath12k_tx_desc_info *txbaddr[ATH12K_NUM_TX_SPT_PAGES];
|
||||
};
|
||||
|
||||
struct dp_rx_tid {
|
||||
uint8_t tid;
|
||||
struct qwz_dmamem *mem;
|
||||
|
|
@ -1089,6 +1174,14 @@ struct dp_link_desc_bank {
|
|||
#define DP_LINK_DESC_ALLOC_SIZE_THRESH 0x200000
|
||||
#define DP_LINK_DESC_BANKS_MAX 8
|
||||
|
||||
#define DP_LINK_DESC_START 0x4000
|
||||
#define DP_LINK_DESC_SHIFT 3
|
||||
|
||||
#define DP_LINK_DESC_COOKIE_SET(id, page) \
|
||||
((((id) + DP_LINK_DESC_START) << DP_LINK_DESC_SHIFT) | (page))
|
||||
|
||||
#define DP_LINK_DESC_BANK_MASK GENMASK(2, 0)
|
||||
|
||||
struct hal_wbm_idle_scatter_list {
|
||||
struct qwz_dmamem *mem;
|
||||
bus_addr_t paddr;
|
||||
|
|
@ -1131,6 +1224,19 @@ struct qwz_dp {
|
|||
#endif
|
||||
struct qwz_hp_update_timer reo_cmd_timer;
|
||||
struct qwz_hp_update_timer tx_ring_timer[DP_TCL_NUM_RING_MAX];
|
||||
struct ath12k_spt_info *spt_info;
|
||||
uint32_t num_spt_pages;
|
||||
TAILQ_HEAD(,ath12k_rx_desc_info) rx_desc_free_list;
|
||||
#ifdef notyet
|
||||
/* protects the free desc list */
|
||||
spinlock_t rx_desc_lock;
|
||||
#endif
|
||||
TAILQ_HEAD(,ath12k_tx_desc_info) tx_desc_free_list[ATH12K_HW_MAX_QUEUES];
|
||||
TAILQ_HEAD(,ath12k_tx_desc_info) tx_desc_used_list[ATH12K_HW_MAX_QUEUES];
|
||||
#ifdef notyet
|
||||
/* protects the free and used desc lists */
|
||||
spinlock_t tx_desc_lock[ATH12K_HW_MAX_QUEUES];
|
||||
#endif
|
||||
};
|
||||
|
||||
#define ATH12K_SHADOW_DP_TIMER_INTERVAL 20
|
||||
|
|
@ -1143,7 +1249,7 @@ struct qwz_ce_pipe {
|
|||
unsigned int buf_sz;
|
||||
unsigned int rx_buf_needed;
|
||||
|
||||
void (*send_cb)(struct qwz_softc *, struct mbuf *);
|
||||
int (*send_cb)(struct qwz_ce_pipe *pipe);
|
||||
void (*recv_cb)(struct qwz_softc *, struct mbuf *);
|
||||
|
||||
#ifdef notyet
|
||||
|
|
@ -1171,8 +1277,8 @@ struct qwz_ce {
|
|||
struct qwz_qmi_ce_cfg {
|
||||
const uint8_t *shadow_reg;
|
||||
int shadow_reg_len;
|
||||
uint32_t *shadow_reg_v2;
|
||||
uint32_t shadow_reg_v2_len;
|
||||
uint32_t *shadow_reg_v3;
|
||||
uint32_t shadow_reg_v3_len;
|
||||
};
|
||||
|
||||
struct qwz_qmi_target_info {
|
||||
|
|
@ -1187,6 +1293,11 @@ struct qwz_qmi_target_info {
|
|||
char bdf_ext[ATH12K_QMI_BDF_EXT_STR_LENGTH];
|
||||
};
|
||||
|
||||
struct qwz_qmi_dev_mem_info {
|
||||
uint64_t start;
|
||||
uint64_t size;
|
||||
};
|
||||
|
||||
enum ath12k_bdf_search {
|
||||
ATH12K_BDF_SEARCH_DEFAULT,
|
||||
ATH12K_BDF_SEARCH_BUS_AND_BOARD,
|
||||
|
|
@ -1631,7 +1742,8 @@ struct qwz_pdev_dp {
|
|||
struct dp_rxdma_ring rx_refill_buf_ring;
|
||||
struct dp_srng rx_mac_buf_ring[MAX_RXDMA_PER_PDEV];
|
||||
struct dp_srng rxdma_err_dst_ring[MAX_RXDMA_PER_PDEV];
|
||||
struct dp_srng rxdma_mon_dst_ring;
|
||||
struct dp_srng rxdma_mon_dst_ring[MAX_RXDMA_PER_PDEV];
|
||||
struct dp_srng tx_mon_dst_ring[MAX_RXDMA_PER_PDEV];
|
||||
struct dp_srng rxdma_mon_desc_ring;
|
||||
struct dp_rxdma_ring rxdma_mon_buf_ring;
|
||||
struct dp_rxdma_ring rx_mon_status_refill_ring[MAX_RXDMA_PER_PDEV];
|
||||
|
|
@ -1810,11 +1922,10 @@ struct qwz_softc {
|
|||
struct {
|
||||
u_char *data;
|
||||
size_t size;
|
||||
} fw_img[4];
|
||||
} fw_img[3];
|
||||
#define QWZ_FW_AMSS 0
|
||||
#define QWZ_FW_BOARD 1
|
||||
#define QWZ_FW_M3 2
|
||||
#define QWZ_FW_REGDB 3
|
||||
|
||||
int sc_tx_timer;
|
||||
uint32_t qfullmsk;
|
||||
|
|
@ -1839,6 +1950,7 @@ struct qwz_softc {
|
|||
int qmi_cal_done;
|
||||
struct qwz_qmi_ce_cfg qmi_ce_cfg;
|
||||
struct qwz_qmi_target_info qmi_target;
|
||||
struct qwz_qmi_dev_mem_info qmi_dev_mem[ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01];
|
||||
struct ath12k_targ_cap target_caps;
|
||||
int num_radios;
|
||||
uint32_t cc_freq_hz;
|
||||
|
|
@ -1888,7 +2000,7 @@ struct qwz_softc {
|
|||
struct qwz_dmamem *fwmem;
|
||||
int expect_fwmem_req;
|
||||
int fwmem_ready;
|
||||
int fw_init_done;
|
||||
int fw_ready;
|
||||
|
||||
int ctl_resp;
|
||||
|
||||
|
|
@ -1901,6 +2013,7 @@ struct qwz_softc {
|
|||
struct qwz_ops ops;
|
||||
bus_dma_tag_t sc_dmat;
|
||||
enum ath12k_hw_rev sc_hw_rev;
|
||||
int static_window_map;
|
||||
struct qwz_device_id id;
|
||||
char sc_bus_str[4]; /* "pci" or "ahb" */
|
||||
int num_msivec;
|
||||
|
|
|
|||
|
|
@ -3593,6 +3593,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
|
|||
rw_init(&adev->grbm_idx_mutex, "grbmidx");
|
||||
rw_init(&adev->mn_lock, "agpumn");
|
||||
rw_init(&adev->virt.vf_errors.lock, "vferr");
|
||||
rw_init(&adev->virt.rlcg_reg_lock, "vrlcg");
|
||||
hash_init(adev->mn_hash);
|
||||
rw_init(&adev->psp.mutex, "agpsp");
|
||||
rw_init(&adev->notifier_lock, "agnf");
|
||||
|
|
|
|||
|
|
@ -258,9 +258,8 @@ amdgpu_job_prepare_job(struct drm_sched_job *sched_job,
|
|||
struct dma_fence *fence = NULL;
|
||||
int r;
|
||||
|
||||
/* Ignore soft recovered fences here */
|
||||
r = drm_sched_entity_error(s_entity);
|
||||
if (r && r != -ENODATA)
|
||||
if (r)
|
||||
goto error;
|
||||
|
||||
if (!fence && job->gang_submit)
|
||||
|
|
|
|||
|
|
@ -334,7 +334,7 @@ static ssize_t ta_if_invoke_debugfs_write(struct file *fp, const char *buf, size
|
|||
|
||||
set_ta_context_funcs(psp, ta_type, &context);
|
||||
|
||||
if (!context->initialized) {
|
||||
if (!context || !context->initialized) {
|
||||
dev_err(adev->dev, "TA is not initialized\n");
|
||||
ret = -EINVAL;
|
||||
goto err_free_shared_buf;
|
||||
|
|
|
|||
|
|
@ -1800,12 +1800,15 @@ static void amdgpu_ras_interrupt_process_handler(struct work_struct *work)
|
|||
int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
|
||||
struct ras_dispatch_if *info)
|
||||
{
|
||||
struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
|
||||
struct ras_ih_data *data = &obj->ih_data;
|
||||
struct ras_manager *obj;
|
||||
struct ras_ih_data *data;
|
||||
|
||||
obj = amdgpu_ras_find_obj(adev, &info->head);
|
||||
if (!obj)
|
||||
return -EINVAL;
|
||||
|
||||
data = &obj->ih_data;
|
||||
|
||||
if (data->inuse == 0)
|
||||
return 0;
|
||||
|
||||
|
|
|
|||
|
|
@ -1004,6 +1004,9 @@ static u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v
|
|||
scratch_reg1 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg1;
|
||||
scratch_reg2 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg2;
|
||||
scratch_reg3 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg3;
|
||||
|
||||
mutex_lock(&adev->virt.rlcg_reg_lock);
|
||||
|
||||
if (reg_access_ctrl->spare_int)
|
||||
spare_int = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->spare_int;
|
||||
|
||||
|
|
@ -1059,6 +1062,9 @@ static u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v
|
|||
}
|
||||
|
||||
ret = readl(scratch_reg0);
|
||||
|
||||
mutex_unlock(&adev->virt.rlcg_reg_lock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -263,6 +263,8 @@ struct amdgpu_virt {
|
|||
|
||||
/* the ucode id to signal the autoload */
|
||||
uint32_t autoload_ucode_id;
|
||||
|
||||
struct rwlock rlcg_reg_lock;
|
||||
};
|
||||
|
||||
struct amdgpu_video_codec_info;
|
||||
|
|
|
|||
|
|
@ -102,6 +102,11 @@ static int amdgpu_vm_sdma_prepare(struct amdgpu_vm_update_params *p,
|
|||
if (!r)
|
||||
r = amdgpu_sync_push_to_job(&sync, p->job);
|
||||
amdgpu_sync_free(&sync);
|
||||
|
||||
if (r) {
|
||||
p->num_dw_left = 0;
|
||||
amdgpu_job_free(p->job);
|
||||
}
|
||||
return r;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -2632,7 +2632,8 @@ static int dm_suspend(void *handle)
|
|||
|
||||
dm->cached_dc_state = dc_copy_state(dm->dc->current_state);
|
||||
|
||||
dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
|
||||
if (dm->cached_dc_state)
|
||||
dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false);
|
||||
|
||||
amdgpu_dm_commit_zero_streams(dm->dc);
|
||||
|
||||
|
|
@ -6487,7 +6488,8 @@ static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
|
|||
aconnector->dc_sink = aconnector->dc_link->local_sink ?
|
||||
aconnector->dc_link->local_sink :
|
||||
aconnector->dc_em_sink;
|
||||
dc_sink_retain(aconnector->dc_sink);
|
||||
if (aconnector->dc_sink)
|
||||
dc_sink_retain(aconnector->dc_sink);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -7300,7 +7302,8 @@ static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
|
|||
drm_add_modes_noedid(connector, 1920, 1080);
|
||||
} else {
|
||||
amdgpu_dm_connector_ddc_get_modes(connector, edid);
|
||||
amdgpu_dm_connector_add_common_modes(encoder, connector);
|
||||
if (encoder)
|
||||
amdgpu_dm_connector_add_common_modes(encoder, connector);
|
||||
amdgpu_dm_connector_add_freesync_modes(connector, edid);
|
||||
}
|
||||
amdgpu_dm_fbc_init(connector);
|
||||
|
|
|
|||
|
|
@ -1266,6 +1266,9 @@ static bool is_dsc_need_re_compute(
|
|||
}
|
||||
}
|
||||
|
||||
if (new_stream_on_link_num == 0)
|
||||
return false;
|
||||
|
||||
/* check current_state if there stream on link but it is not in
|
||||
* new request state
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -162,7 +162,12 @@ static void set_hpo_fixed_vs_pe_retimer_dp_link_test_pattern(struct dc_link *lin
|
|||
link_res->hpo_dp_link_enc->funcs->set_link_test_pattern(
|
||||
link_res->hpo_dp_link_enc, tp_params);
|
||||
}
|
||||
|
||||
link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_SET_SOURCE_PATTERN);
|
||||
|
||||
// Give retimer extra time to lock before updating DP_TRAINING_PATTERN_SET to TPS1
|
||||
if (tp_params->dp_phy_pattern == DP_TEST_PATTERN_128b_132b_TPS1_TRAINING_MODE)
|
||||
drm_msleep(30);
|
||||
}
|
||||
|
||||
static void set_hpo_fixed_vs_pe_retimer_dp_lane_settings(struct dc_link *link,
|
||||
|
|
|
|||
|
|
@ -927,7 +927,7 @@ static int pp_dpm_switch_power_profile(void *handle,
|
|||
enum PP_SMC_POWER_PROFILE type, bool en)
|
||||
{
|
||||
struct pp_hwmgr *hwmgr = handle;
|
||||
long workload;
|
||||
long workload[1];
|
||||
uint32_t index;
|
||||
|
||||
if (!hwmgr || !hwmgr->pm_en)
|
||||
|
|
@ -945,12 +945,12 @@ static int pp_dpm_switch_power_profile(void *handle,
|
|||
hwmgr->workload_mask &= ~(1 << hwmgr->workload_prority[type]);
|
||||
index = fls(hwmgr->workload_mask);
|
||||
index = index > 0 && index <= Workload_Policy_Max ? index - 1 : 0;
|
||||
workload = hwmgr->workload_setting[index];
|
||||
workload[0] = hwmgr->workload_setting[index];
|
||||
} else {
|
||||
hwmgr->workload_mask |= (1 << hwmgr->workload_prority[type]);
|
||||
index = fls(hwmgr->workload_mask);
|
||||
index = index <= Workload_Policy_Max ? index - 1 : 0;
|
||||
workload = hwmgr->workload_setting[index];
|
||||
workload[0] = hwmgr->workload_setting[index];
|
||||
}
|
||||
|
||||
if (type == PP_SMC_POWER_PROFILE_COMPUTE &&
|
||||
|
|
@ -960,7 +960,7 @@ static int pp_dpm_switch_power_profile(void *handle,
|
|||
}
|
||||
|
||||
if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
|
||||
hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, &workload, 0);
|
||||
hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, workload, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -269,7 +269,7 @@ int psm_adjust_power_state_dynamic(struct pp_hwmgr *hwmgr, bool skip_display_set
|
|||
struct pp_power_state *new_ps)
|
||||
{
|
||||
uint32_t index;
|
||||
long workload;
|
||||
long workload[1];
|
||||
|
||||
if (hwmgr->not_vf) {
|
||||
if (!skip_display_settings)
|
||||
|
|
@ -294,10 +294,10 @@ int psm_adjust_power_state_dynamic(struct pp_hwmgr *hwmgr, bool skip_display_set
|
|||
if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
|
||||
index = fls(hwmgr->workload_mask);
|
||||
index = index > 0 && index <= Workload_Policy_Max ? index - 1 : 0;
|
||||
workload = hwmgr->workload_setting[index];
|
||||
workload[0] = hwmgr->workload_setting[index];
|
||||
|
||||
if (hwmgr->power_profile_mode != workload && hwmgr->hwmgr_func->set_power_profile_mode)
|
||||
hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, &workload, 0);
|
||||
if (hwmgr->power_profile_mode != workload[0] && hwmgr->hwmgr_func->set_power_profile_mode)
|
||||
hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, workload, 0);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -2957,6 +2957,7 @@ static int smu7_update_edc_leakage_table(struct pp_hwmgr *hwmgr)
|
|||
|
||||
static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
|
||||
{
|
||||
struct amdgpu_device *adev = hwmgr->adev;
|
||||
struct smu7_hwmgr *data;
|
||||
int result = 0;
|
||||
|
||||
|
|
@ -2993,40 +2994,37 @@ static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
|
|||
/* Initalize Dynamic State Adjustment Rule Settings */
|
||||
result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
|
||||
|
||||
if (0 == result) {
|
||||
struct amdgpu_device *adev = hwmgr->adev;
|
||||
if (result)
|
||||
goto fail;
|
||||
|
||||
data->is_tlu_enabled = false;
|
||||
data->is_tlu_enabled = false;
|
||||
|
||||
hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
|
||||
hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
|
||||
SMU7_MAX_HARDWARE_POWERLEVELS;
|
||||
hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
|
||||
hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
|
||||
hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
|
||||
hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
|
||||
|
||||
data->pcie_gen_cap = adev->pm.pcie_gen_mask;
|
||||
if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
|
||||
data->pcie_spc_cap = 20;
|
||||
else
|
||||
data->pcie_spc_cap = 16;
|
||||
data->pcie_lane_cap = adev->pm.pcie_mlw_mask;
|
||||
data->pcie_gen_cap = adev->pm.pcie_gen_mask;
|
||||
if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
|
||||
data->pcie_spc_cap = 20;
|
||||
else
|
||||
data->pcie_spc_cap = 16;
|
||||
data->pcie_lane_cap = adev->pm.pcie_mlw_mask;
|
||||
|
||||
hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
|
||||
/* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
|
||||
hwmgr->platform_descriptor.clockStep.engineClock = 500;
|
||||
hwmgr->platform_descriptor.clockStep.memoryClock = 500;
|
||||
smu7_thermal_parameter_init(hwmgr);
|
||||
} else {
|
||||
/* Ignore return value in here, we are cleaning up a mess. */
|
||||
smu7_hwmgr_backend_fini(hwmgr);
|
||||
}
|
||||
hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
|
||||
/* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
|
||||
hwmgr->platform_descriptor.clockStep.engineClock = 500;
|
||||
hwmgr->platform_descriptor.clockStep.memoryClock = 500;
|
||||
smu7_thermal_parameter_init(hwmgr);
|
||||
|
||||
result = smu7_update_edc_leakage_table(hwmgr);
|
||||
if (result) {
|
||||
smu7_hwmgr_backend_fini(hwmgr);
|
||||
return result;
|
||||
}
|
||||
if (result)
|
||||
goto fail;
|
||||
|
||||
return 0;
|
||||
fail:
|
||||
smu7_hwmgr_backend_fini(hwmgr);
|
||||
return result;
|
||||
}
|
||||
|
||||
static int smu7_force_dpm_highest(struct pp_hwmgr *hwmgr)
|
||||
|
|
@ -3316,8 +3314,7 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
|
|||
const struct pp_power_state *current_ps)
|
||||
{
|
||||
struct amdgpu_device *adev = hwmgr->adev;
|
||||
struct smu7_power_state *smu7_ps =
|
||||
cast_phw_smu7_power_state(&request_ps->hardware);
|
||||
struct smu7_power_state *smu7_ps;
|
||||
uint32_t sclk;
|
||||
uint32_t mclk;
|
||||
struct PP_Clocks minimum_clocks = {0};
|
||||
|
|
@ -3334,6 +3331,10 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
|
|||
uint32_t latency;
|
||||
bool latency_allowed = false;
|
||||
|
||||
smu7_ps = cast_phw_smu7_power_state(&request_ps->hardware);
|
||||
if (!smu7_ps)
|
||||
return -EINVAL;
|
||||
|
||||
data->battery_state = (PP_StateUILabel_Battery ==
|
||||
request_ps->classification.ui_label);
|
||||
data->mclk_ignore_signal = false;
|
||||
|
|
|
|||
|
|
@ -1065,16 +1065,18 @@ static int smu8_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
|
|||
struct pp_power_state *prequest_ps,
|
||||
const struct pp_power_state *pcurrent_ps)
|
||||
{
|
||||
struct smu8_power_state *smu8_ps =
|
||||
cast_smu8_power_state(&prequest_ps->hardware);
|
||||
|
||||
const struct smu8_power_state *smu8_current_ps =
|
||||
cast_const_smu8_power_state(&pcurrent_ps->hardware);
|
||||
|
||||
struct smu8_power_state *smu8_ps;
|
||||
const struct smu8_power_state *smu8_current_ps;
|
||||
struct smu8_hwmgr *data = hwmgr->backend;
|
||||
struct PP_Clocks clocks = {0, 0, 0, 0};
|
||||
bool force_high;
|
||||
|
||||
smu8_ps = cast_smu8_power_state(&prequest_ps->hardware);
|
||||
smu8_current_ps = cast_const_smu8_power_state(&pcurrent_ps->hardware);
|
||||
|
||||
if (!smu8_ps || !smu8_current_ps)
|
||||
return -EINVAL;
|
||||
|
||||
smu8_ps->need_dfs_bypass = true;
|
||||
|
||||
data->battery_state = (PP_StateUILabel_Battery == prequest_ps->classification.ui_label);
|
||||
|
|
|
|||
|
|
@ -3259,8 +3259,7 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
|
|||
const struct pp_power_state *current_ps)
|
||||
{
|
||||
struct amdgpu_device *adev = hwmgr->adev;
|
||||
struct vega10_power_state *vega10_ps =
|
||||
cast_phw_vega10_power_state(&request_ps->hardware);
|
||||
struct vega10_power_state *vega10_ps;
|
||||
uint32_t sclk;
|
||||
uint32_t mclk;
|
||||
struct PP_Clocks minimum_clocks = {0};
|
||||
|
|
@ -3278,6 +3277,10 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
|
|||
uint32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;
|
||||
uint32_t latency;
|
||||
|
||||
vega10_ps = cast_phw_vega10_power_state(&request_ps->hardware);
|
||||
if (!vega10_ps)
|
||||
return -EINVAL;
|
||||
|
||||
data->battery_state = (PP_StateUILabel_Battery ==
|
||||
request_ps->classification.ui_label);
|
||||
|
||||
|
|
@ -3415,13 +3418,17 @@ static int vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, co
|
|||
const struct vega10_power_state *vega10_ps =
|
||||
cast_const_phw_vega10_power_state(states->pnew_state);
|
||||
struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
|
||||
uint32_t sclk = vega10_ps->performance_levels
|
||||
[vega10_ps->performance_level_count - 1].gfx_clock;
|
||||
struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
|
||||
uint32_t mclk = vega10_ps->performance_levels
|
||||
[vega10_ps->performance_level_count - 1].mem_clock;
|
||||
uint32_t sclk, mclk;
|
||||
uint32_t i;
|
||||
|
||||
if (vega10_ps == NULL)
|
||||
return -EINVAL;
|
||||
sclk = vega10_ps->performance_levels
|
||||
[vega10_ps->performance_level_count - 1].gfx_clock;
|
||||
mclk = vega10_ps->performance_levels
|
||||
[vega10_ps->performance_level_count - 1].mem_clock;
|
||||
|
||||
for (i = 0; i < sclk_table->count; i++) {
|
||||
if (sclk == sclk_table->dpm_levels[i].value)
|
||||
break;
|
||||
|
|
@ -3728,6 +3735,9 @@ static int vega10_generate_dpm_level_enable_mask(
|
|||
cast_const_phw_vega10_power_state(states->pnew_state);
|
||||
int i;
|
||||
|
||||
if (vega10_ps == NULL)
|
||||
return -EINVAL;
|
||||
|
||||
PP_ASSERT_WITH_CODE(!vega10_trim_dpm_states(hwmgr, vega10_ps),
|
||||
"Attempt to Trim DPM States Failed!",
|
||||
return -1);
|
||||
|
|
@ -4995,6 +5005,8 @@ static int vega10_check_states_equal(struct pp_hwmgr *hwmgr,
|
|||
|
||||
vega10_psa = cast_const_phw_vega10_power_state(pstate1);
|
||||
vega10_psb = cast_const_phw_vega10_power_state(pstate2);
|
||||
if (vega10_psa == NULL || vega10_psb == NULL)
|
||||
return -EINVAL;
|
||||
|
||||
/* If the two states don't even have the same number of performance levels
|
||||
* they cannot be the same state.
|
||||
|
|
@ -5128,6 +5140,8 @@ static int vega10_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
|
|||
return -EINVAL;
|
||||
|
||||
vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
|
||||
if (vega10_ps == NULL)
|
||||
return -EINVAL;
|
||||
|
||||
vega10_ps->performance_levels
|
||||
[vega10_ps->performance_level_count - 1].gfx_clock =
|
||||
|
|
@ -5179,6 +5193,8 @@ static int vega10_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
|
|||
return -EINVAL;
|
||||
|
||||
vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
|
||||
if (vega10_ps == NULL)
|
||||
return -EINVAL;
|
||||
|
||||
vega10_ps->performance_levels
|
||||
[vega10_ps->performance_level_count - 1].mem_clock =
|
||||
|
|
@ -5420,6 +5436,9 @@ static void vega10_odn_update_power_state(struct pp_hwmgr *hwmgr)
|
|||
return;
|
||||
|
||||
vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
|
||||
if (vega10_ps == NULL)
|
||||
return;
|
||||
|
||||
max_level = vega10_ps->performance_level_count - 1;
|
||||
|
||||
if (vega10_ps->performance_levels[max_level].gfx_clock !=
|
||||
|
|
@ -5442,6 +5461,9 @@ static void vega10_odn_update_power_state(struct pp_hwmgr *hwmgr)
|
|||
|
||||
ps = (struct pp_power_state *)((unsigned long)(hwmgr->ps) + hwmgr->ps_size * (hwmgr->num_ps - 1));
|
||||
vega10_ps = cast_phw_vega10_power_state(&ps->hardware);
|
||||
if (vega10_ps == NULL)
|
||||
return;
|
||||
|
||||
max_level = vega10_ps->performance_level_count - 1;
|
||||
|
||||
if (vega10_ps->performance_levels[max_level].gfx_clock !=
|
||||
|
|
@ -5632,6 +5654,8 @@ static int vega10_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_
|
|||
return -EINVAL;
|
||||
|
||||
vega10_ps = cast_const_phw_vega10_power_state(state);
|
||||
if (vega10_ps == NULL)
|
||||
return -EINVAL;
|
||||
|
||||
i = index > vega10_ps->performance_level_count - 1 ?
|
||||
vega10_ps->performance_level_count - 1 : index;
|
||||
|
|
|
|||
|
|
@ -1846,7 +1846,7 @@ static int smu_adjust_power_state_dynamic(struct smu_context *smu,
|
|||
{
|
||||
int ret = 0;
|
||||
int index = 0;
|
||||
long workload;
|
||||
long workload[1];
|
||||
struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
|
||||
|
||||
if (!skip_display_settings) {
|
||||
|
|
@ -1886,10 +1886,10 @@ static int smu_adjust_power_state_dynamic(struct smu_context *smu,
|
|||
smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
|
||||
index = fls(smu->workload_mask);
|
||||
index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
|
||||
workload = smu->workload_setting[index];
|
||||
workload[0] = smu->workload_setting[index];
|
||||
|
||||
if (smu->power_profile_mode != workload)
|
||||
smu_bump_power_profile_mode(smu, &workload, 0);
|
||||
if (smu->power_profile_mode != workload[0])
|
||||
smu_bump_power_profile_mode(smu, workload, 0);
|
||||
}
|
||||
|
||||
return ret;
|
||||
|
|
@ -1939,7 +1939,7 @@ static int smu_switch_power_profile(void *handle,
|
|||
{
|
||||
struct smu_context *smu = handle;
|
||||
struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
|
||||
long workload;
|
||||
long workload[1];
|
||||
uint32_t index;
|
||||
|
||||
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
|
||||
|
|
@ -1952,17 +1952,17 @@ static int smu_switch_power_profile(void *handle,
|
|||
smu->workload_mask &= ~(1 << smu->workload_prority[type]);
|
||||
index = fls(smu->workload_mask);
|
||||
index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
|
||||
workload = smu->workload_setting[index];
|
||||
workload[0] = smu->workload_setting[index];
|
||||
} else {
|
||||
smu->workload_mask |= (1 << smu->workload_prority[type]);
|
||||
index = fls(smu->workload_mask);
|
||||
index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
|
||||
workload = smu->workload_setting[index];
|
||||
workload[0] = smu->workload_setting[index];
|
||||
}
|
||||
|
||||
if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
|
||||
smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)
|
||||
smu_bump_power_profile_mode(smu, &workload, 0);
|
||||
smu_bump_power_profile_mode(smu, workload, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4034,6 +4034,7 @@ static int drm_dp_mst_handle_up_req(struct drm_dp_mst_topology_mgr *mgr)
|
|||
if (up_req->msg.req_type == DP_CONNECTION_STATUS_NOTIFY) {
|
||||
const struct drm_dp_connection_status_notify *conn_stat =
|
||||
&up_req->msg.u.conn_stat;
|
||||
bool handle_csn;
|
||||
|
||||
drm_dbg_kms(mgr->dev, "Got CSN: pn: %d ldps:%d ddps: %d mcs: %d ip: %d pdt: %d\n",
|
||||
conn_stat->port_number,
|
||||
|
|
@ -4042,6 +4043,16 @@ static int drm_dp_mst_handle_up_req(struct drm_dp_mst_topology_mgr *mgr)
|
|||
conn_stat->message_capability_status,
|
||||
conn_stat->input_port,
|
||||
conn_stat->peer_device_type);
|
||||
|
||||
mutex_lock(&mgr->probe_lock);
|
||||
handle_csn = mgr->mst_primary->link_address_sent;
|
||||
mutex_unlock(&mgr->probe_lock);
|
||||
|
||||
if (!handle_csn) {
|
||||
drm_dbg_kms(mgr->dev, "Got CSN before finish topology probing. Skip it.");
|
||||
kfree(up_req);
|
||||
goto out;
|
||||
}
|
||||
} else if (up_req->msg.req_type == DP_RESOURCE_STATUS_NOTIFY) {
|
||||
const struct drm_dp_resource_status_notify *res_stat =
|
||||
&up_req->msg.u.resource_stat;
|
||||
|
|
|
|||
|
|
@ -879,6 +879,11 @@ int drm_client_modeset_probe(struct drm_client_dev *client, unsigned int width,
|
|||
|
||||
kfree(modeset->mode);
|
||||
modeset->mode = drm_mode_duplicate(dev, mode);
|
||||
if (!modeset->mode) {
|
||||
ret = -ENOMEM;
|
||||
break;
|
||||
}
|
||||
|
||||
drm_connector_get(connector);
|
||||
modeset->connectors[modeset->num_connectors++] = connector;
|
||||
modeset->x = offset->x;
|
||||
|
|
|
|||
|
|
@ -325,6 +325,41 @@ out:
|
|||
return i915_error_to_vmf_fault(err);
|
||||
}
|
||||
|
||||
static void set_address_limits(struct vm_area_struct *area,
|
||||
struct i915_vma *vma,
|
||||
unsigned long obj_offset,
|
||||
unsigned long *start_vaddr,
|
||||
unsigned long *end_vaddr)
|
||||
{
|
||||
unsigned long vm_start, vm_end, vma_size; /* user's memory parameters */
|
||||
long start, end; /* memory boundaries */
|
||||
|
||||
/*
|
||||
* Let's move into the ">> PAGE_SHIFT"
|
||||
* domain to be sure not to lose bits
|
||||
*/
|
||||
vm_start = area->vm_start >> PAGE_SHIFT;
|
||||
vm_end = area->vm_end >> PAGE_SHIFT;
|
||||
vma_size = vma->size >> PAGE_SHIFT;
|
||||
|
||||
/*
|
||||
* Calculate the memory boundaries by considering the offset
|
||||
* provided by the user during memory mapping and the offset
|
||||
* provided for the partial mapping.
|
||||
*/
|
||||
start = vm_start;
|
||||
start -= obj_offset;
|
||||
start += vma->gtt_view.partial.offset;
|
||||
end = start + vma_size;
|
||||
|
||||
start = max_t(long, start, vm_start);
|
||||
end = min_t(long, end, vm_end);
|
||||
|
||||
/* Let's move back into the "<< PAGE_SHIFT" domain */
|
||||
*start_vaddr = (unsigned long)start << PAGE_SHIFT;
|
||||
*end_vaddr = (unsigned long)end << PAGE_SHIFT;
|
||||
}
|
||||
|
||||
static vm_fault_t vm_fault_gtt(struct vm_fault *vmf)
|
||||
{
|
||||
#define MIN_CHUNK_PAGES (SZ_1M >> PAGE_SHIFT)
|
||||
|
|
@ -337,14 +372,18 @@ static vm_fault_t vm_fault_gtt(struct vm_fault *vmf)
|
|||
struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
|
||||
bool write = area->vm_flags & VM_WRITE;
|
||||
struct i915_gem_ww_ctx ww;
|
||||
unsigned long obj_offset;
|
||||
unsigned long start, end; /* memory boundaries */
|
||||
intel_wakeref_t wakeref;
|
||||
struct i915_vma *vma;
|
||||
pgoff_t page_offset;
|
||||
unsigned long pfn;
|
||||
int srcu;
|
||||
int ret;
|
||||
|
||||
/* We don't use vmf->pgoff since that has the fake offset */
|
||||
obj_offset = area->vm_pgoff - drm_vma_node_start(&mmo->vma_node);
|
||||
page_offset = (vmf->address - area->vm_start) >> PAGE_SHIFT;
|
||||
page_offset += obj_offset;
|
||||
|
||||
trace_i915_gem_object_fault(obj, page_offset, true, write);
|
||||
|
||||
|
|
@ -437,12 +476,14 @@ retry:
|
|||
if (ret)
|
||||
goto err_unpin;
|
||||
|
||||
set_address_limits(area, vma, obj_offset, &start, &end);
|
||||
|
||||
pfn = (ggtt->gmadr.start + i915_ggtt_offset(vma)) >> PAGE_SHIFT;
|
||||
pfn += (start - area->vm_start) >> PAGE_SHIFT;
|
||||
pfn += obj_offset - vma->gtt_view.partial.offset;
|
||||
|
||||
/* Finally, remap it using the new GTT offset */
|
||||
ret = remap_io_mapping(area,
|
||||
area->vm_start + (vma->gtt_view.partial.offset << PAGE_SHIFT),
|
||||
(ggtt->gmadr.start + i915_ggtt_offset(vma)) >> PAGE_SHIFT,
|
||||
min_t(u64, vma->size, area->vm_end - area->vm_start),
|
||||
&ggtt->iomap);
|
||||
ret = remap_io_mapping(area, start, pfn, end - start, &ggtt->iomap);
|
||||
if (ret)
|
||||
goto err_fence;
|
||||
|
||||
|
|
@ -655,6 +696,41 @@ remap_io_mapping(pmap_t pm, vm_prot_t mapprot,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static void set_address_limits(struct vm_map_entry *entry,
|
||||
struct i915_vma *vma,
|
||||
unsigned long obj_offset,
|
||||
unsigned long *start_vaddr,
|
||||
unsigned long *end_vaddr)
|
||||
{
|
||||
unsigned long vm_start, vm_end, vma_size; /* user's memory parameters */
|
||||
long start, end; /* memory boundaries */
|
||||
|
||||
/*
|
||||
* Let's move into the ">> PAGE_SHIFT"
|
||||
* domain to be sure not to lose bits
|
||||
*/
|
||||
vm_start = entry->start >> PAGE_SHIFT;
|
||||
vm_end = entry->end >> PAGE_SHIFT;
|
||||
vma_size = vma->size >> PAGE_SHIFT;
|
||||
|
||||
/*
|
||||
* Calculate the memory boundaries by considering the offset
|
||||
* provided by the user during memory mapping and the offset
|
||||
* provided for the partial mapping.
|
||||
*/
|
||||
start = vm_start;
|
||||
start -= obj_offset;
|
||||
start += vma->gtt_view.partial.offset;
|
||||
end = start + vma_size;
|
||||
|
||||
start = max_t(long, start, vm_start);
|
||||
end = min_t(long, end, vm_end);
|
||||
|
||||
/* Let's move back into the "<< PAGE_SHIFT" domain */
|
||||
*start_vaddr = (unsigned long)start << PAGE_SHIFT;
|
||||
*end_vaddr = (unsigned long)end << PAGE_SHIFT;
|
||||
}
|
||||
|
||||
static int
|
||||
vm_fault_gtt(struct i915_mmap_offset *mmo, struct uvm_faultinfo *ufi,
|
||||
vaddr_t vaddr, vm_prot_t access_type)
|
||||
|
|
@ -668,13 +744,16 @@ vm_fault_gtt(struct i915_mmap_offset *mmo, struct uvm_faultinfo *ufi,
|
|||
struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
|
||||
int write = !!(access_type & PROT_WRITE);
|
||||
struct i915_gem_ww_ctx ww;
|
||||
unsigned long obj_offset;
|
||||
unsigned long start, end; /* memory boundaries */
|
||||
intel_wakeref_t wakeref;
|
||||
struct i915_vma *vma;
|
||||
pgoff_t page_offset;
|
||||
unsigned long pfn;
|
||||
int srcu;
|
||||
int ret;
|
||||
|
||||
/* We don't use vmf->pgoff since that has the fake offset */
|
||||
obj_offset = entry->offset - drm_vma_node_start(&mmo->vma_node);
|
||||
page_offset = (vaddr - entry->start) >> PAGE_SHIFT;
|
||||
|
||||
trace_i915_gem_object_fault(obj, page_offset, true, write);
|
||||
|
|
@ -768,11 +847,15 @@ retry:
|
|||
if (ret)
|
||||
goto err_unpin;
|
||||
|
||||
set_address_limits(entry, vma, obj_offset, &start, &end);
|
||||
|
||||
pfn = (ggtt->gmadr.start + i915_ggtt_offset(vma)) >> PAGE_SHIFT;
|
||||
pfn += (start - entry->start) >> PAGE_SHIFT;
|
||||
pfn += obj_offset - vma->gtt_view.partial.offset;
|
||||
|
||||
/* Finally, remap it using the new GTT offset */
|
||||
ret = remap_io_mapping(ufi->orig_map->pmap, entry->protection,
|
||||
entry->start + (vma->gtt_view.partial.offset << PAGE_SHIFT),
|
||||
(ggtt->gmadr.start + i915_ggtt_offset(vma)) >> PAGE_SHIFT,
|
||||
min_t(u64, vma->size, entry->end - entry->start));
|
||||
start, pfn, end - start);
|
||||
if (ret)
|
||||
goto err_fence;
|
||||
|
||||
|
|
@ -1507,6 +1590,8 @@ int i915_gem_fb_mmap(struct drm_i915_gem_object *obj, struct vm_area_struct *vma
|
|||
mmo = mmap_offset_attach(obj, mmap_type, NULL);
|
||||
if (IS_ERR(mmo))
|
||||
return PTR_ERR(mmo);
|
||||
|
||||
vma->vm_pgoff += drm_vma_node_start(&mmo->vma_node);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -114,8 +114,8 @@ typedef struct _ATOM_PPLIB_EXTENDEDHEADER
|
|||
USHORT usUVDTableOffset; //points to ATOM_PPLIB_UVD_Table
|
||||
USHORT usSAMUTableOffset; //points to ATOM_PPLIB_SAMU_Table
|
||||
USHORT usPPMTableOffset; //points to ATOM_PPLIB_PPM_Table
|
||||
USHORT usACPTableOffset; //points to ATOM_PPLIB_ACP_Table
|
||||
USHORT usPowerTuneTableOffset; //points to ATOM_PPLIB_POWERTUNE_Table
|
||||
USHORT usACPTableOffset; //points to ATOM_PPLIB_ACP_Table
|
||||
USHORT usPowerTuneTableOffset; //points to ATOM_PPLIB_POWERTUNE_Table
|
||||
} ATOM_PPLIB_EXTENDEDHEADER;
|
||||
|
||||
//// ATOM_PPLIB_POWERPLAYTABLE::ulPlatformCaps
|
||||
|
|
@ -196,14 +196,14 @@ typedef struct _ATOM_PPLIB_POWERPLAYTABLE3
|
|||
typedef struct _ATOM_PPLIB_POWERPLAYTABLE4
|
||||
{
|
||||
ATOM_PPLIB_POWERPLAYTABLE3 basicTable3;
|
||||
ULONG ulGoldenPPID; // PPGen use only
|
||||
ULONG ulGoldenPPID; // PPGen use only
|
||||
ULONG ulGoldenRevision; // PPGen use only
|
||||
USHORT usVddcDependencyOnSCLKOffset;
|
||||
USHORT usVddciDependencyOnMCLKOffset;
|
||||
USHORT usVddcDependencyOnMCLKOffset;
|
||||
USHORT usMaxClockVoltageOnDCOffset;
|
||||
USHORT usVddcPhaseShedLimitsTableOffset; // Points to ATOM_PPLIB_PhaseSheddingLimits_Table
|
||||
USHORT usMvddDependencyOnMCLKOffset;
|
||||
USHORT usMvddDependencyOnMCLKOffset;
|
||||
} ATOM_PPLIB_POWERPLAYTABLE4, *LPATOM_PPLIB_POWERPLAYTABLE4;
|
||||
|
||||
typedef struct _ATOM_PPLIB_POWERPLAYTABLE5
|
||||
|
|
@ -347,23 +347,23 @@ typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO
|
|||
UCHAR ucPadding; // For proper alignment and size.
|
||||
USHORT usVDDC; // For the 780, use: None, Low, High, Variable
|
||||
UCHAR ucMaxHTLinkWidth; // From SBIOS - {2, 4, 8, 16}
|
||||
UCHAR ucMinHTLinkWidth; // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled. Minimum down stream width could
|
||||
UCHAR ucMinHTLinkWidth; // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled. Minimum down stream width could
|
||||
USHORT usHTLinkFreq; // See definition ATOM_PPLIB_RS780_HTLINKFREQ_xxx or in MHz(>=200).
|
||||
ULONG ulFlags;
|
||||
ULONG ulFlags;
|
||||
} ATOM_PPLIB_RS780_CLOCK_INFO;
|
||||
|
||||
#define ATOM_PPLIB_RS780_VOLTAGE_NONE 0
|
||||
#define ATOM_PPLIB_RS780_VOLTAGE_LOW 1
|
||||
#define ATOM_PPLIB_RS780_VOLTAGE_HIGH 2
|
||||
#define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE 3
|
||||
#define ATOM_PPLIB_RS780_VOLTAGE_NONE 0
|
||||
#define ATOM_PPLIB_RS780_VOLTAGE_LOW 1
|
||||
#define ATOM_PPLIB_RS780_VOLTAGE_HIGH 2
|
||||
#define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE 3
|
||||
|
||||
#define ATOM_PPLIB_RS780_SPMCLK_NONE 0 // We cannot change the side port memory clock, leave it as it is.
|
||||
#define ATOM_PPLIB_RS780_SPMCLK_LOW 1
|
||||
#define ATOM_PPLIB_RS780_SPMCLK_HIGH 2
|
||||
|
||||
#define ATOM_PPLIB_RS780_HTLINKFREQ_NONE 0
|
||||
#define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1
|
||||
#define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2
|
||||
#define ATOM_PPLIB_RS780_HTLINKFREQ_NONE 0
|
||||
#define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1
|
||||
#define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2
|
||||
|
||||
typedef struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO
|
||||
{
|
||||
|
|
@ -405,14 +405,14 @@ typedef struct _ATOM_PPLIB_CI_CLOCK_INFO
|
|||
|
||||
USHORT usMemoryClockLow;
|
||||
UCHAR ucMemoryClockHigh;
|
||||
|
||||
|
||||
UCHAR ucPCIEGen;
|
||||
USHORT usPCIELane;
|
||||
} ATOM_PPLIB_CI_CLOCK_INFO;
|
||||
|
||||
typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO{
|
||||
USHORT usEngineClockLow; //clockfrequency & 0xFFFF. The unit is in 10khz
|
||||
UCHAR ucEngineClockHigh; //clockfrequency >> 16.
|
||||
UCHAR ucEngineClockHigh; //clockfrequency >> 16.
|
||||
UCHAR vddcIndex; //2-bit vddc index;
|
||||
USHORT tdpLimit;
|
||||
//please initalize to 0
|
||||
|
|
@ -423,10 +423,10 @@ typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO{
|
|||
|
||||
typedef struct _ATOM_PPLIB_STATE_V2
|
||||
{
|
||||
//number of valid dpm levels in this state; Driver uses it to calculate the whole
|
||||
//number of valid dpm levels in this state; Driver uses it to calculate the whole
|
||||
//size of the state: struct_size(ATOM_PPLIB_STATE_V2, clockInfoIndex, ucNumDPMLevels)
|
||||
UCHAR ucNumDPMLevels;
|
||||
|
||||
|
||||
//a index to the array of nonClockInfos
|
||||
UCHAR nonClockInfoIndex;
|
||||
/**
|
||||
|
|
@ -436,20 +436,20 @@ typedef struct _ATOM_PPLIB_STATE_V2
|
|||
} ATOM_PPLIB_STATE_V2;
|
||||
|
||||
typedef struct _StateArray{
|
||||
//how many states we have
|
||||
//how many states we have
|
||||
UCHAR ucNumEntries;
|
||||
|
||||
ATOM_PPLIB_STATE_V2 states[] __counted_by(ucNumEntries);
|
||||
|
||||
ATOM_PPLIB_STATE_V2 states[] /* __counted_by(ucNumEntries) */;
|
||||
}StateArray;
|
||||
|
||||
|
||||
typedef struct _ClockInfoArray{
|
||||
//how many clock levels we have
|
||||
UCHAR ucNumEntries;
|
||||
|
||||
|
||||
//sizeof(ATOM_PPLIB_CLOCK_INFO)
|
||||
UCHAR ucEntrySize;
|
||||
|
||||
|
||||
UCHAR clockInfo[] __counted_by(ucNumEntries);
|
||||
}ClockInfoArray;
|
||||
|
||||
|
|
@ -459,7 +459,7 @@ typedef struct _NonClockInfoArray{
|
|||
UCHAR ucNumEntries;
|
||||
//sizeof(ATOM_PPLIB_NONCLOCK_INFO)
|
||||
UCHAR ucEntrySize;
|
||||
|
||||
|
||||
ATOM_PPLIB_NONCLOCK_INFO nonClockInfo[] __counted_by(ucNumEntries);
|
||||
}NonClockInfoArray;
|
||||
|
||||
|
|
@ -680,7 +680,7 @@ typedef struct _ATOM_PPLIB_PPM_Table
|
|||
ULONG ulPlatformTDC;
|
||||
ULONG ulSmallACPlatformTDC;
|
||||
ULONG ulApuTDP;
|
||||
ULONG ulDGpuTDP;
|
||||
ULONG ulDGpuTDP;
|
||||
ULONG ulDGpuUlvPower;
|
||||
ULONG ulTjmax;
|
||||
} ATOM_PPLIB_PPM_Table;
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $OpenBSD: if_qwz_pci.c,v 1.1 2024/08/14 14:40:46 patrick Exp $ */
|
||||
/* $OpenBSD: if_qwz_pci.c,v 1.3 2024/08/16 00:26:54 patrick Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright 2023 Stefan Sperling <stsp@openbsd.org>
|
||||
|
|
@ -116,11 +116,12 @@
|
|||
#define ATH12K_PCI_WINDOW_VALUE_MASK GENMASK(24, 19)
|
||||
#define ATH12K_PCI_WINDOW_START 0x80000
|
||||
#define ATH12K_PCI_WINDOW_RANGE_MASK GENMASK(18, 0)
|
||||
#define ATH12K_PCI_WINDOW_STATIC_MASK GENMASK(31, 6)
|
||||
|
||||
/* BAR0 + 4k is always accessible, and no need to force wakeup. */
|
||||
#define ATH12K_PCI_ACCESS_ALWAYS_OFF 0xFE0 /* 4K - 32 = 0xFE0 */
|
||||
|
||||
#define TCSR_SOC_HW_VERSION 0x0224
|
||||
#define TCSR_SOC_HW_VERSION 0x1b00000
|
||||
#define TCSR_SOC_HW_VERSION_MAJOR_MASK GENMASK(11, 8)
|
||||
#define TCSR_SOC_HW_VERSION_MINOR_MASK GENMASK(7, 0)
|
||||
|
||||
|
|
@ -145,7 +146,7 @@
|
|||
#define PCIE_PCIE_PARF_LTSSM 0x1e081b0
|
||||
#define PARM_LTSSM_VALUE 0x111
|
||||
|
||||
#define GCC_GCC_PCIE_HOT_RST 0x1e402bc
|
||||
#define GCC_GCC_PCIE_HOT_RST 0x1e38338
|
||||
#define GCC_GCC_PCIE_HOT_RST_VAL 0x10
|
||||
|
||||
#define PCIE_PCIE_INT_ALL_CLEAR 0x1e08228
|
||||
|
|
@ -170,6 +171,9 @@
|
|||
#define WLAON_QFPROM_PWR_CTRL_REG 0x01f8031c
|
||||
#define QFPROM_PWR_CTRL_VDD4BLOW_MASK 0x4
|
||||
|
||||
#define PCI_MHIREGLEN_REG 0x1e0e100
|
||||
#define PCI_MHI_REGION_END 0x1e0effc
|
||||
|
||||
/*
|
||||
* mhi.h
|
||||
*/
|
||||
|
|
@ -374,11 +378,9 @@ struct qwz_pci_softc {
|
|||
struct qwz_dmamem *cmd_ctxt;
|
||||
|
||||
|
||||
struct qwz_pci_xfer_ring xfer_rings[4];
|
||||
#define QWZ_PCI_XFER_RING_LOOPBACK_OUTBOUND 0
|
||||
#define QWZ_PCI_XFER_RING_LOOPBACK_INBOUND 1
|
||||
#define QWZ_PCI_XFER_RING_IPCR_OUTBOUND 2
|
||||
#define QWZ_PCI_XFER_RING_IPCR_INBOUND 3
|
||||
struct qwz_pci_xfer_ring xfer_rings[2];
|
||||
#define QWZ_PCI_XFER_RING_IPCR_OUTBOUND 0
|
||||
#define QWZ_PCI_XFER_RING_IPCR_INBOUND 1
|
||||
struct qwz_pci_event_ring event_rings[QWZ_NUM_EVENT_CTX];
|
||||
struct qwz_pci_cmd_ring cmd_ring;
|
||||
};
|
||||
|
|
@ -482,28 +484,14 @@ struct qwz_pci_ops {
|
|||
};
|
||||
|
||||
|
||||
static const struct qwz_pci_ops qwz_pci_ops_qca6390 = {
|
||||
static const struct qwz_pci_ops qwz_pci_ops_wcn7850 = {
|
||||
.wakeup = qwz_pci_bus_wake_up,
|
||||
.release = qwz_pci_bus_release,
|
||||
#if notyet
|
||||
.get_msi_irq = qwz_pci_get_msi_irq,
|
||||
#endif
|
||||
.window_write32 = qwz_pci_window_write32,
|
||||
.window_read32 = qwz_pci_window_read32,
|
||||
.alloc_xfer_rings = qwz_pci_alloc_xfer_rings_qca6390,
|
||||
};
|
||||
|
||||
static const struct qwz_pci_ops qwz_pci_ops_qcn9074 = {
|
||||
.wakeup = NULL,
|
||||
.release = NULL,
|
||||
#if notyet
|
||||
.get_msi_irq = qwz_pci_get_msi_irq,
|
||||
#endif
|
||||
.window_write32 = qwz_pci_window_write32,
|
||||
.window_read32 = qwz_pci_window_read32,
|
||||
.alloc_xfer_rings = qwz_pci_alloc_xfer_rings_qcn9074,
|
||||
};
|
||||
|
||||
const struct cfattach qwz_pci_ca = {
|
||||
sizeof(struct qwz_pci_softc),
|
||||
qwz_pci_match,
|
||||
|
|
@ -512,16 +500,8 @@ const struct cfattach qwz_pci_ca = {
|
|||
qwz_activate
|
||||
};
|
||||
|
||||
/* XXX pcidev */
|
||||
#define PCI_PRODUCT_QUALCOMM_QCA6390 0x1101
|
||||
#define PCI_PRODUCT_QUALCOMM_QCN9074 0x1104
|
||||
|
||||
static const struct pci_matchid qwz_pci_devices[] = {
|
||||
#if notyet
|
||||
{ PCI_VENDOR_QUALCOMM, PCI_PRODUCT_QUALCOMM_QCA6390 },
|
||||
{ PCI_VENDOR_QUALCOMM, PCI_PRODUCT_QUALCOMM_QCN9074 },
|
||||
#endif
|
||||
{ PCI_VENDOR_QUALCOMM, PCI_PRODUCT_QUALCOMM_QCNFA765 }
|
||||
{ PCI_VENDOR_QUALCOMM, PCI_PRODUCT_QUALCOMM_WCN7850 }
|
||||
};
|
||||
|
||||
int
|
||||
|
|
@ -535,8 +515,8 @@ qwz_pci_init_qmi_ce_config(struct qwz_softc *sc)
|
|||
{
|
||||
struct qwz_qmi_ce_cfg *cfg = &sc->qmi_ce_cfg;
|
||||
|
||||
qwz_ce_get_shadow_config(sc, &cfg->shadow_reg_v2,
|
||||
&cfg->shadow_reg_v2_len);
|
||||
qwz_ce_get_shadow_config(sc, &cfg->shadow_reg_v3,
|
||||
&cfg->shadow_reg_v3_len);
|
||||
}
|
||||
|
||||
const struct qwz_msi_config qwz_msi_config_one_msi = {
|
||||
|
|
@ -551,17 +531,6 @@ const struct qwz_msi_config qwz_msi_config_one_msi = {
|
|||
};
|
||||
|
||||
const struct qwz_msi_config qwz_msi_config[] = {
|
||||
{
|
||||
.total_vectors = 32,
|
||||
.total_users = 4,
|
||||
.users = (struct qwz_msi_user[]) {
|
||||
{ .name = "MHI", .num_vectors = 3, .base_vector = 0 },
|
||||
{ .name = "CE", .num_vectors = 10, .base_vector = 3 },
|
||||
{ .name = "WAKE", .num_vectors = 1, .base_vector = 13 },
|
||||
{ .name = "DP", .num_vectors = 18, .base_vector = 14 },
|
||||
},
|
||||
.hw_rev = ATH12K_HW_QCA6390_HW20,
|
||||
},
|
||||
{
|
||||
.total_vectors = 16,
|
||||
.total_users = 3,
|
||||
|
|
@ -570,38 +539,7 @@ const struct qwz_msi_config qwz_msi_config[] = {
|
|||
{ .name = "CE", .num_vectors = 5, .base_vector = 3 },
|
||||
{ .name = "DP", .num_vectors = 8, .base_vector = 8 },
|
||||
},
|
||||
.hw_rev = ATH12K_HW_QCN9074_HW10,
|
||||
},
|
||||
{
|
||||
.total_vectors = 32,
|
||||
.total_users = 4,
|
||||
.users = (struct qwz_msi_user[]) {
|
||||
{ .name = "MHI", .num_vectors = 3, .base_vector = 0 },
|
||||
{ .name = "CE", .num_vectors = 10, .base_vector = 3 },
|
||||
{ .name = "WAKE", .num_vectors = 1, .base_vector = 13 },
|
||||
{ .name = "DP", .num_vectors = 18, .base_vector = 14 },
|
||||
},
|
||||
.hw_rev = ATH12K_HW_WCN6855_HW20,
|
||||
},
|
||||
{
|
||||
.total_vectors = 32,
|
||||
.total_users = 4,
|
||||
.users = (struct qwz_msi_user[]) {
|
||||
{ .name = "MHI", .num_vectors = 3, .base_vector = 0 },
|
||||
{ .name = "CE", .num_vectors = 10, .base_vector = 3 },
|
||||
{ .name = "WAKE", .num_vectors = 1, .base_vector = 13 },
|
||||
{ .name = "DP", .num_vectors = 18, .base_vector = 14 },
|
||||
},
|
||||
.hw_rev = ATH12K_HW_WCN6855_HW21,
|
||||
},
|
||||
{
|
||||
.total_vectors = 28,
|
||||
.total_users = 2,
|
||||
.users = (struct qwz_msi_user[]) {
|
||||
{ .name = "CE", .num_vectors = 10, .base_vector = 0 },
|
||||
{ .name = "DP", .num_vectors = 18, .base_vector = 10 },
|
||||
},
|
||||
.hw_rev = ATH12K_HW_WCN6750_HW10,
|
||||
.hw_rev = ATH12K_HW_WCN7850_HW20,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -745,7 +683,6 @@ qwz_pci_attach(struct device *parent, struct device *self, void *aux)
|
|||
struct ieee80211com *ic = &sc->sc_ic;
|
||||
struct ifnet *ifp = &ic->ic_if;
|
||||
uint32_t soc_hw_version_major, soc_hw_version_minor;
|
||||
const struct qwz_pci_ops *pci_ops;
|
||||
struct pci_attach_args *pa = aux;
|
||||
pci_intr_handle_t ih;
|
||||
pcireg_t memtype, reg;
|
||||
|
|
@ -885,54 +822,22 @@ qwz_pci_attach(struct device *parent, struct device *self, void *aux)
|
|||
pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0);
|
||||
|
||||
switch (PCI_PRODUCT(pa->pa_id)) {
|
||||
case PCI_PRODUCT_QUALCOMM_QCA6390:
|
||||
qwz_pci_read_hw_version(sc, &soc_hw_version_major,
|
||||
&soc_hw_version_minor);
|
||||
switch (soc_hw_version_major) {
|
||||
case 2:
|
||||
sc->sc_hw_rev = ATH12K_HW_QCA6390_HW20;
|
||||
break;
|
||||
default:
|
||||
printf(": unsupported QCA6390 SOC version: %d %d\n",
|
||||
soc_hw_version_major, soc_hw_version_minor);
|
||||
return;
|
||||
}
|
||||
|
||||
pci_ops = &qwz_pci_ops_qca6390;
|
||||
psc->max_chan = QWZ_MHI_CONFIG_QCA6390_MAX_CHANNELS;
|
||||
break;
|
||||
case PCI_PRODUCT_QUALCOMM_QCN9074:
|
||||
pci_ops = &qwz_pci_ops_qcn9074;
|
||||
sc->sc_hw_rev = ATH12K_HW_QCN9074_HW10;
|
||||
psc->max_chan = QWZ_MHI_CONFIG_QCA9074_MAX_CHANNELS;
|
||||
break;
|
||||
case PCI_PRODUCT_QUALCOMM_QCNFA765:
|
||||
case PCI_PRODUCT_QUALCOMM_WCN7850:
|
||||
sc->static_window_map = 0;
|
||||
psc->sc_pci_ops = &qwz_pci_ops_wcn7850;
|
||||
sc->id.bdf_search = ATH12K_BDF_SEARCH_BUS_AND_BOARD;
|
||||
qwz_pci_read_hw_version(sc, &soc_hw_version_major,
|
||||
&soc_hw_version_minor);
|
||||
switch (soc_hw_version_major) {
|
||||
case 2:
|
||||
switch (soc_hw_version_minor) {
|
||||
case 0x00:
|
||||
case 0x01:
|
||||
sc->sc_hw_rev = ATH12K_HW_WCN6855_HW20;
|
||||
break;
|
||||
case 0x10:
|
||||
case 0x11:
|
||||
sc->sc_hw_rev = ATH12K_HW_WCN6855_HW21;
|
||||
break;
|
||||
default:
|
||||
goto unsupported_wcn6855_soc;
|
||||
}
|
||||
sc->sc_hw_rev = ATH12K_HW_WCN7850_HW20;
|
||||
break;
|
||||
default:
|
||||
unsupported_wcn6855_soc:
|
||||
printf(": unsupported WCN6855 SOC version: %d %d\n",
|
||||
soc_hw_version_major, soc_hw_version_minor);
|
||||
printf(": unknown hardware version found for WCN785: "
|
||||
"%d\n", soc_hw_version_major);
|
||||
return;
|
||||
}
|
||||
|
||||
pci_ops = &qwz_pci_ops_qca6390;
|
||||
psc->max_chan = QWZ_MHI_CONFIG_QCA6390_MAX_CHANNELS;
|
||||
break;
|
||||
default:
|
||||
|
|
@ -940,9 +845,6 @@ unsupported_wcn6855_soc:
|
|||
return;
|
||||
}
|
||||
|
||||
/* register PCI ops */
|
||||
psc->sc_pci_ops = pci_ops;
|
||||
|
||||
error = qwz_pcic_init_msi_config(sc);
|
||||
if (error)
|
||||
goto err_pci_free_region;
|
||||
|
|
@ -1020,8 +922,6 @@ unsupported_wcn6855_soc:
|
|||
if (sc->sc_nswq == NULL)
|
||||
goto err_ce_free;
|
||||
|
||||
qwz_pci_init_qmi_ce_config(sc);
|
||||
|
||||
error = qwz_pcic_config_irq(sc, pa);
|
||||
if (error) {
|
||||
printf("%s: failed to config irq: %d\n",
|
||||
|
|
@ -1227,7 +1127,7 @@ qwz_pci_alloc_xfer_ring(struct qwz_softc *sc, struct qwz_pci_xfer_ring *ring,
|
|||
memset(ring->data, 0, sizeof(ring->data));
|
||||
for (i = 0; i < ring->num_elements; i++) {
|
||||
struct qwz_xfer_data *xfer = &ring->data[i];
|
||||
|
||||
|
||||
err = bus_dmamap_create(sc->sc_dmat, QWZ_PCI_XFER_MAX_DATA_SIZE,
|
||||
1, QWZ_PCI_XFER_MAX_DATA_SIZE, 0, BUS_DMA_NOWAIT,
|
||||
&xfer->map);
|
||||
|
|
@ -1296,18 +1196,6 @@ qwz_pci_alloc_xfer_rings_qca6390(struct qwz_pci_softc *psc)
|
|||
struct qwz_softc *sc = &psc->sc_sc;
|
||||
int ret;
|
||||
|
||||
ret = qwz_pci_alloc_xfer_ring(sc,
|
||||
&psc->xfer_rings[QWZ_PCI_XFER_RING_LOOPBACK_OUTBOUND],
|
||||
0, MHI_CHAN_TYPE_OUTBOUND, 0, 32);
|
||||
if (ret)
|
||||
goto fail;
|
||||
|
||||
ret = qwz_pci_alloc_xfer_ring(sc,
|
||||
&psc->xfer_rings[QWZ_PCI_XFER_RING_LOOPBACK_INBOUND],
|
||||
1, MHI_CHAN_TYPE_INBOUND, 0, 32);
|
||||
if (ret)
|
||||
goto fail;
|
||||
|
||||
ret = qwz_pci_alloc_xfer_ring(sc,
|
||||
&psc->xfer_rings[QWZ_PCI_XFER_RING_IPCR_OUTBOUND],
|
||||
20, MHI_CHAN_TYPE_OUTBOUND, 1, 64);
|
||||
|
|
@ -1332,18 +1220,6 @@ qwz_pci_alloc_xfer_rings_qcn9074(struct qwz_pci_softc *psc)
|
|||
struct qwz_softc *sc = &psc->sc_sc;
|
||||
int ret;
|
||||
|
||||
ret = qwz_pci_alloc_xfer_ring(sc,
|
||||
&psc->xfer_rings[QWZ_PCI_XFER_RING_LOOPBACK_OUTBOUND],
|
||||
0, MHI_CHAN_TYPE_OUTBOUND, 1, 32);
|
||||
if (ret)
|
||||
goto fail;
|
||||
|
||||
ret = qwz_pci_alloc_xfer_ring(sc,
|
||||
&psc->xfer_rings[QWZ_PCI_XFER_RING_LOOPBACK_INBOUND],
|
||||
1, MHI_CHAN_TYPE_INBOUND, 1, 32);
|
||||
if (ret)
|
||||
goto fail;
|
||||
|
||||
ret = qwz_pci_alloc_xfer_ring(sc,
|
||||
&psc->xfer_rings[QWZ_PCI_XFER_RING_IPCR_OUTBOUND],
|
||||
20, MHI_CHAN_TYPE_OUTBOUND, 1, 32);
|
||||
|
|
@ -1602,11 +1478,13 @@ qwz_pcic_ext_irq_config(struct qwz_softc *sc, struct pci_attach_args *pa)
|
|||
struct qwz_pci_softc *psc = (struct qwz_pci_softc *)sc;
|
||||
int i, ret, num_vectors = 0;
|
||||
uint32_t msi_data_start = 0;
|
||||
uint32_t base_vector = 0;
|
||||
uint32_t base_idx, base_vector = 0;
|
||||
|
||||
if (!test_bit(ATH12K_FLAG_MULTI_MSI_VECTORS, sc->sc_flags))
|
||||
return 0;
|
||||
|
||||
base_idx = ATH12K_PCI_IRQ_CE0_OFFSET + CE_COUNT_MAX;
|
||||
|
||||
ret = qwz_pcic_get_user_msi_vector(sc, "DP", &num_vectors,
|
||||
&msi_data_start, &base_vector);
|
||||
if (ret < 0)
|
||||
|
|
@ -1618,7 +1496,7 @@ qwz_pcic_ext_irq_config(struct qwz_softc *sc, struct pci_attach_args *pa)
|
|||
|
||||
irq_grp->sc = sc;
|
||||
irq_grp->grp_id = i;
|
||||
#if 0
|
||||
#if 0
|
||||
init_dummy_netdev(&irq_grp->napi_ndev);
|
||||
netif_napi_add(&irq_grp->napi_ndev, &irq_grp->napi,
|
||||
ath12k_pcic_ext_grp_napi_poll);
|
||||
|
|
@ -1635,7 +1513,7 @@ qwz_pcic_ext_irq_config(struct qwz_softc *sc, struct pci_attach_args *pa)
|
|||
}
|
||||
|
||||
irq_grp->num_irq = num_irq;
|
||||
irq_grp->irqs[0] = ATH12K_PCI_IRQ_DP_OFFSET + i;
|
||||
irq_grp->irqs[0] = base_idx + i;
|
||||
|
||||
if (num_irq) {
|
||||
int irq_idx = irq_grp->irqs[0];
|
||||
|
|
@ -1805,13 +1683,13 @@ qwz_pci_bus_release(struct qwz_softc *sc)
|
|||
uint32_t
|
||||
qwz_pci_get_window_start(struct qwz_softc *sc, uint32_t offset)
|
||||
{
|
||||
if (!sc->hw_params.static_window_map)
|
||||
if (!sc->static_window_map)
|
||||
return ATH12K_PCI_WINDOW_START;
|
||||
|
||||
if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < ATH12K_PCI_WINDOW_RANGE_MASK)
|
||||
/* if offset lies within DP register range, use 3rd window */
|
||||
return 3 * ATH12K_PCI_WINDOW_START;
|
||||
else if ((offset ^ HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(sc)) <
|
||||
else if ((offset ^ HAL_SEQ_WCSS_UMAC_CE0_SRC_REG) <
|
||||
ATH12K_PCI_WINDOW_RANGE_MASK)
|
||||
/* if offset lies within CE register range, use 2nd window */
|
||||
return 2 * ATH12K_PCI_WINDOW_START;
|
||||
|
|
@ -1829,6 +1707,12 @@ qwz_pci_select_window(struct qwz_softc *sc, uint32_t offset)
|
|||
lockdep_assert_held(&ab_pci->window_lock);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Preserve the static window configuration and reset only
|
||||
* dynamic window.
|
||||
*/
|
||||
window |= psc->register_window & ATH12K_PCI_WINDOW_STATIC_MASK;
|
||||
|
||||
if (window != psc->register_window) {
|
||||
qwz_pci_write(sc, ATH12K_PCI_WINDOW_REG_ADDRESS,
|
||||
ATH12K_PCI_WINDOW_ENABLE_BIT | window);
|
||||
|
|
@ -1837,6 +1721,12 @@ qwz_pci_select_window(struct qwz_softc *sc, uint32_t offset)
|
|||
}
|
||||
}
|
||||
|
||||
static inline bool
|
||||
qwz_pci_is_offset_within_mhi_region(uint32_t offset)
|
||||
{
|
||||
return (offset >= PCI_MHIREGLEN_REG && offset <= PCI_MHI_REGION_END);
|
||||
}
|
||||
|
||||
void
|
||||
qwz_pci_window_write32(struct qwz_softc *sc, uint32_t offset, uint32_t value)
|
||||
{
|
||||
|
|
@ -1849,8 +1739,15 @@ qwz_pci_window_write32(struct qwz_softc *sc, uint32_t offset, uint32_t value)
|
|||
spin_lock_bh(&ab_pci->window_lock);
|
||||
#endif
|
||||
qwz_pci_select_window(sc, offset);
|
||||
qwz_pci_write(sc, window_start +
|
||||
(offset & ATH12K_PCI_WINDOW_RANGE_MASK), value);
|
||||
|
||||
if (qwz_pci_is_offset_within_mhi_region(offset)) {
|
||||
offset = offset - PCI_MHIREGLEN_REG;
|
||||
qwz_pci_write(sc, offset & ATH12K_PCI_WINDOW_RANGE_MASK,
|
||||
value);
|
||||
} else {
|
||||
qwz_pci_write(sc, window_start +
|
||||
(offset & ATH12K_PCI_WINDOW_RANGE_MASK), value);
|
||||
}
|
||||
#if notyet
|
||||
spin_unlock_bh(&ab_pci->window_lock);
|
||||
#endif
|
||||
|
|
@ -1872,8 +1769,15 @@ qwz_pci_window_read32(struct qwz_softc *sc, uint32_t offset)
|
|||
spin_lock_bh(&ab_pci->window_lock);
|
||||
#endif
|
||||
qwz_pci_select_window(sc, offset);
|
||||
val = qwz_pci_read(sc, window_start +
|
||||
(offset & ATH12K_PCI_WINDOW_RANGE_MASK));
|
||||
|
||||
if (qwz_pci_is_offset_within_mhi_region(offset)) {
|
||||
offset = offset - PCI_MHIREGLEN_REG;
|
||||
val = qwz_pci_read(sc,
|
||||
offset & ATH12K_PCI_WINDOW_RANGE_MASK);
|
||||
} else {
|
||||
val = qwz_pci_read(sc, window_start +
|
||||
(offset & ATH12K_PCI_WINDOW_RANGE_MASK));
|
||||
}
|
||||
#if notyet
|
||||
spin_unlock_bh(&ab_pci->window_lock);
|
||||
#endif
|
||||
|
|
@ -2120,7 +2024,7 @@ qwz_pci_msi_config(struct qwz_softc *sc, bool enable)
|
|||
else
|
||||
val &= ~PCI_MSI_MC_MSIE;
|
||||
|
||||
pci_conf_write(psc->sc_pc, psc->sc_tag, psc->sc_msi_off + PCI_MSI_MC,
|
||||
pci_conf_write(psc->sc_pc, psc->sc_tag, psc->sc_msi_off + PCI_MSI_MC,
|
||||
val);
|
||||
}
|
||||
|
||||
|
|
@ -2189,7 +2093,7 @@ qwz_pci_power_up(struct qwz_softc *sc)
|
|||
if (error)
|
||||
return error;
|
||||
|
||||
if (sc->hw_params.static_window_map)
|
||||
if (sc->static_window_map)
|
||||
qwz_pci_select_static_window(sc);
|
||||
|
||||
return 0;
|
||||
|
|
@ -3273,7 +3177,7 @@ qwz_mhi_fw_load_bhi(struct qwz_pci_softc *psc, uint8_t *data, size_t len)
|
|||
qwz_pci_write(sc, psc->bhi_off + MHI_BHI_IMGADDR_LOW,
|
||||
paddr & 0xffffffff);
|
||||
qwz_pci_write(sc, psc->bhi_off + MHI_BHI_IMGSIZE, len);
|
||||
|
||||
|
||||
/* Set a random transaction sequence number. */
|
||||
do {
|
||||
seq = arc4random_uniform(MHI_BHI_TXDB_SEQNUM_BMSK);
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
$OpenBSD: pcidevs,v 1.2083 2024/08/10 11:00:14 jsg Exp $
|
||||
$OpenBSD: pcidevs,v 1.2084 2024/08/15 11:25:37 patrick Exp $
|
||||
/* $NetBSD: pcidevs,v 1.30 1997/06/24 06:20:24 thorpej Exp $ */
|
||||
|
||||
/*
|
||||
|
|
@ -8645,6 +8645,7 @@ product QLOGIC ISP8432 0x8432 ISP8432
|
|||
product QUALCOMM SC8280XP_PCIE 0x010e SC8280XP PCIe
|
||||
product QUALCOMM X1E80100_PCIE 0x0111 X1E80100 PCIe
|
||||
product QUALCOMM QCNFA765 0x1103 QCNFA765
|
||||
product QUALCOMM WCN7850 0x1107 WCN7850
|
||||
|
||||
/* Quancom products */
|
||||
product QUANCOM PWDOG1 0x0010 PWDOG1
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
|
||||
*
|
||||
* generated from:
|
||||
* OpenBSD: pcidevs,v 1.2083 2024/08/10 11:00:14 jsg Exp
|
||||
* OpenBSD: pcidevs,v 1.2084 2024/08/15 11:25:37 patrick Exp
|
||||
*/
|
||||
/* $NetBSD: pcidevs,v 1.30 1997/06/24 06:20:24 thorpej Exp $ */
|
||||
|
||||
|
|
@ -8650,6 +8650,7 @@
|
|||
#define PCI_PRODUCT_QUALCOMM_SC8280XP_PCIE 0x010e /* SC8280XP PCIe */
|
||||
#define PCI_PRODUCT_QUALCOMM_X1E80100_PCIE 0x0111 /* X1E80100 PCIe */
|
||||
#define PCI_PRODUCT_QUALCOMM_QCNFA765 0x1103 /* QCNFA765 */
|
||||
#define PCI_PRODUCT_QUALCOMM_WCN7850 0x1107 /* WCN7850 */
|
||||
|
||||
/* Quancom products */
|
||||
#define PCI_PRODUCT_QUANCOM_PWDOG1 0x0010 /* PWDOG1 */
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
|
||||
*
|
||||
* generated from:
|
||||
* OpenBSD: pcidevs,v 1.2083 2024/08/10 11:00:14 jsg Exp
|
||||
* OpenBSD: pcidevs,v 1.2084 2024/08/15 11:25:37 patrick Exp
|
||||
*/
|
||||
|
||||
/* $NetBSD: pcidevs,v 1.30 1997/06/24 06:20:24 thorpej Exp $ */
|
||||
|
|
@ -31207,6 +31207,10 @@ static const struct pci_known_product pci_known_products[] = {
|
|||
PCI_VENDOR_QUALCOMM, PCI_PRODUCT_QUALCOMM_QCNFA765,
|
||||
"QCNFA765",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_QUALCOMM, PCI_PRODUCT_QUALCOMM_WCN7850,
|
||||
"WCN7850",
|
||||
},
|
||||
{
|
||||
PCI_VENDOR_QUANCOM, PCI_PRODUCT_QUANCOM_PWDOG1,
|
||||
"PWDOG1",
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $OpenBSD: xhci.c,v 1.132 2024/08/06 17:30:04 kettenis Exp $ */
|
||||
/* $OpenBSD: xhci.c,v 1.133 2024/08/15 17:17:05 kettenis Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2014-2015 Martin Pieuchot
|
||||
|
|
@ -415,6 +415,7 @@ xhci_config(struct xhci_softc *sc)
|
|||
{
|
||||
uint64_t paddr;
|
||||
uint32_t hcr;
|
||||
int i;
|
||||
|
||||
/* Make sure to program a number of device slots we can handle. */
|
||||
if (sc->sc_noslot > USB_MAX_DEVICES)
|
||||
|
|
@ -457,6 +458,27 @@ xhci_config(struct xhci_softc *sc)
|
|||
DPRINTF(("%s: ERDP=%#x%#x\n", DEVNAME(sc),
|
||||
XRREAD4(sc, XHCI_ERDP_HI(0)), XRREAD4(sc, XHCI_ERDP_LO(0))));
|
||||
|
||||
/*
|
||||
* If we successfully saved the state during suspend, restore
|
||||
* it here. Otherwise some Intel controllers don't function
|
||||
* correctly after resume.
|
||||
*/
|
||||
if (sc->sc_saved_state) {
|
||||
XOWRITE4(sc, XHCI_USBCMD, XHCI_CMD_CRS); /* Restore state */
|
||||
hcr = XOREAD4(sc, XHCI_USBSTS);
|
||||
for (i = 0; i < 100; i++) {
|
||||
usb_delay_ms(&sc->sc_bus, 1);
|
||||
hcr = XOREAD4(sc, XHCI_USBSTS) & XHCI_STS_RSS;
|
||||
if (!hcr)
|
||||
break;
|
||||
}
|
||||
|
||||
if (hcr)
|
||||
printf("%s: restore state timeout\n", DEVNAME(sc));
|
||||
|
||||
sc->sc_saved_state = 0;
|
||||
}
|
||||
|
||||
/* Enable interrupts. */
|
||||
hcr = XRREAD4(sc, XHCI_IMAN(0));
|
||||
XRWRITE4(sc, XHCI_IMAN(0), hcr | XHCI_IMAN_INTR_ENA);
|
||||
|
|
@ -603,10 +625,6 @@ xhci_suspend(struct xhci_softc *sc)
|
|||
* unless they have seen a save state command. This in turn
|
||||
* will prevent the SoC from reaching its lowest idle state.
|
||||
* So save the state here.
|
||||
*
|
||||
* Note that we don't restore this saved state anywhere.
|
||||
* Instead we reset the controller and reinitialize it from
|
||||
* scratch when we resume.
|
||||
*/
|
||||
|
||||
XOWRITE4(sc, XHCI_USBCMD, XHCI_CMD_CSS); /* Save state */
|
||||
|
|
@ -624,6 +642,8 @@ xhci_suspend(struct xhci_softc *sc)
|
|||
return;
|
||||
}
|
||||
|
||||
sc->sc_saved_state = 1;
|
||||
|
||||
/* Disable interrupts. */
|
||||
XRWRITE4(sc, XHCI_IMOD(0), 0);
|
||||
XRWRITE4(sc, XHCI_IMAN(0), 0);
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $OpenBSD: xhcivar.h,v 1.14 2022/12/12 19:18:25 kettenis Exp $ */
|
||||
/* $OpenBSD: xhcivar.h,v 1.15 2024/08/15 17:17:05 kettenis Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2014 Martin Pieuchot
|
||||
|
|
@ -89,6 +89,7 @@ struct xhci_softc {
|
|||
bus_size_t sc_size;
|
||||
|
||||
int sc_dead;
|
||||
int sc_saved_state;
|
||||
|
||||
bus_size_t sc_oper_off; /* Operational Register space */
|
||||
bus_size_t sc_runt_off; /* Runtime */
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $OpenBSD: bpf.c,v 1.224 2024/08/12 17:02:58 mvs Exp $ */
|
||||
/* $OpenBSD: bpf.c,v 1.225 2024/08/15 12:20:20 dlg Exp $ */
|
||||
/* $NetBSD: bpf.c,v 1.33 1997/02/21 23:59:35 thorpej Exp $ */
|
||||
|
||||
/*
|
||||
|
|
@ -760,7 +760,8 @@ bpf_get_wtimeout(struct bpf_d *d, struct timeval *tv)
|
|||
/*
|
||||
* FIONREAD Check for read packet available.
|
||||
* BIOCGBLEN Get buffer len [for read()].
|
||||
* BIOCSETF Set ethernet read filter.
|
||||
* BIOCSETF Set read filter.
|
||||
* BIOCSETFNR Set read filter without resetting descriptor.
|
||||
* BIOCFLUSH Flush read packet buffer.
|
||||
* BIOCPROMISC Put interface into promiscuous mode.
|
||||
* BIOCGDLTLIST Get supported link layer types.
|
||||
|
|
@ -867,17 +868,12 @@ bpfioctl(dev_t dev, u_long cmd, caddr_t addr, int flag, struct proc *p)
|
|||
break;
|
||||
|
||||
/*
|
||||
* Set link layer read filter.
|
||||
* Set link layer read/write filter.
|
||||
*/
|
||||
case BIOCSETF:
|
||||
error = bpf_setf(d, (struct bpf_program *)addr, 0);
|
||||
break;
|
||||
|
||||
/*
|
||||
* Set link layer write filter.
|
||||
*/
|
||||
case BIOCSETFNR:
|
||||
case BIOCSETWF:
|
||||
error = bpf_setf(d, (struct bpf_program *)addr, 1);
|
||||
error = bpf_setf(d, (struct bpf_program *)addr, cmd);
|
||||
break;
|
||||
|
||||
/*
|
||||
|
|
@ -1122,7 +1118,7 @@ bpfioctl(dev_t dev, u_long cmd, caddr_t addr, int flag, struct proc *p)
|
|||
* free it and replace it. Returns EINVAL for bogus requests.
|
||||
*/
|
||||
int
|
||||
bpf_setf(struct bpf_d *d, struct bpf_program *fp, int wf)
|
||||
bpf_setf(struct bpf_d *d, struct bpf_program *fp, u_long cmd)
|
||||
{
|
||||
struct bpf_program_smr *bps, *old_bps;
|
||||
struct bpf_insn *fcode;
|
||||
|
|
@ -1157,7 +1153,7 @@ bpf_setf(struct bpf_d *d, struct bpf_program *fp, int wf)
|
|||
bps->bps_bf.bf_insns = fcode;
|
||||
}
|
||||
|
||||
if (wf == 0) {
|
||||
if (cmd != BIOCSETWF) {
|
||||
old_bps = SMR_PTR_GET_LOCKED(&d->bd_rfilter);
|
||||
SMR_PTR_SET_LOCKED(&d->bd_rfilter, bps);
|
||||
} else {
|
||||
|
|
@ -1165,9 +1161,12 @@ bpf_setf(struct bpf_d *d, struct bpf_program *fp, int wf)
|
|||
SMR_PTR_SET_LOCKED(&d->bd_wfilter, bps);
|
||||
}
|
||||
|
||||
mtx_enter(&d->bd_mtx);
|
||||
bpf_resetd(d);
|
||||
mtx_leave(&d->bd_mtx);
|
||||
if (cmd == BIOCSETF) {
|
||||
mtx_enter(&d->bd_mtx);
|
||||
bpf_resetd(d);
|
||||
mtx_leave(&d->bd_mtx);
|
||||
}
|
||||
|
||||
if (old_bps != NULL)
|
||||
smr_call(&old_bps->bps_smr, bpf_prog_smr, old_bps);
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $OpenBSD: bpf.h,v 1.72 2024/01/26 21:14:08 jan Exp $ */
|
||||
/* $OpenBSD: bpf.h,v 1.73 2024/08/15 12:20:20 dlg Exp $ */
|
||||
/* $NetBSD: bpf.h,v 1.15 1996/12/13 07:57:33 mikel Exp $ */
|
||||
|
||||
/*
|
||||
|
|
@ -122,6 +122,7 @@ struct bpf_version {
|
|||
#define BIOCSWTIMEOUT _IOW('B',126, struct timeval)
|
||||
#define BIOCGWTIMEOUT _IOR('B',126, struct timeval)
|
||||
#define BIOCDWTIMEOUT _IO('B',126)
|
||||
#define BIOCSETFNR _IOW('B',127, struct bpf_program)
|
||||
|
||||
/*
|
||||
* Direction filters for BIOCSDIRFILT/BIOCGDIRFILT
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $OpenBSD: bpfdesc.h,v 1.48 2023/03/09 05:56:58 dlg Exp $ */
|
||||
/* $OpenBSD: bpfdesc.h,v 1.49 2024/08/15 12:20:20 dlg Exp $ */
|
||||
/* $NetBSD: bpfdesc.h,v 1.11 1995/09/27 18:30:42 thorpej Exp $ */
|
||||
|
||||
/*
|
||||
|
|
@ -123,6 +123,6 @@ struct bpf_if {
|
|||
struct ifnet *bif_ifp; /* corresponding interface */
|
||||
};
|
||||
|
||||
int bpf_setf(struct bpf_d *, struct bpf_program *, int);
|
||||
int bpf_setf(struct bpf_d *, struct bpf_program *, u_long);
|
||||
#endif /* _KERNEL */
|
||||
#endif /* _NET_BPFDESC_H_ */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue