sync with OpenBSD -current
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F42C07F07E2E35B7
72 changed files with 5497 additions and 3934 deletions
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@ -812,6 +812,10 @@ probe_gmdid_display(struct drm_i915_private *i915, u16 *ver, u16 *rel, u16 *step
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void __iomem *addr;
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u32 val;
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int i;
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int mmio_bar, mmio_size, mmio_type;
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bus_space_tag_t bst;
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bus_space_handle_t bsh;
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bus_size_t memsize;
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/* The caller expects to ver, rel and step to be initialized
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* here, and there's no good way to check when there was a
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@ -822,9 +826,7 @@ probe_gmdid_display(struct drm_i915_private *i915, u16 *ver, u16 *rel, u16 *step
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*rel = 0;
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*step = 0;
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STUB();
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return &no_display;
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#ifdef notyet
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#ifdef __linux__
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addr = pci_iomap_range(pdev, 0, i915_mmio_reg_offset(GMD_ID_DISPLAY), sizeof(u32));
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if (!addr) {
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drm_err(&i915->drm, "Cannot map MMIO BAR to read display GMD_ID\n");
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@ -833,6 +835,19 @@ probe_gmdid_display(struct drm_i915_private *i915, u16 *ver, u16 *rel, u16 *step
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val = ioread32(addr);
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pci_iounmap(pdev, addr);
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#else
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mmio_bar = 0x10;
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mmio_type = pci_mapreg_type(i915->pc, i915->tag, mmio_bar);
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if (pci_mapreg_map(i915->pa, mmio_bar, mmio_type, 0,
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&bst, &bsh, NULL, &memsize, 0)) {
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drm_err(&i915->drm, "Cannot map MMIO BAR to read display GMD_ID\n");
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return &no_display;
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}
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val = bus_space_read_4(bst, bsh, i915_mmio_reg_offset(GMD_ID_DISPLAY));
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bus_space_unmap(bst, bsh, memsize);
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#endif
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if (val == 0) {
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drm_dbg_kms(&i915->drm, "Device doesn't have display\n");
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@ -851,7 +866,6 @@ probe_gmdid_display(struct drm_i915_private *i915, u16 *ver, u16 *rel, u16 *step
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drm_err(&i915->drm, "Unrecognized display IP version %d.%02d; disabling display.\n",
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*ver, *rel);
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return &no_display;
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#endif
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}
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const struct intel_display_device_info *
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@ -388,6 +388,27 @@ static void icl_get_stolen_reserved(struct drm_i915_private *i915,
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drm_dbg(&i915->drm, "GEN6_STOLEN_RESERVED = 0x%016llx\n", reg_val);
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/* Wa_14019821291 */
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if (MEDIA_VER_FULL(i915) == IP_VER(13, 0)) {
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/*
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* This workaround is primarily implemented by the BIOS. We
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* just need to figure out whether the BIOS has applied the
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* workaround (meaning the programmed address falls within
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* the DSM) and, if so, reserve that part of the DSM to
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* prevent accidental reuse. The DSM location should be just
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* below the WOPCM.
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*/
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u64 gscpsmi_base = intel_uncore_read64_2x32(uncore,
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MTL_GSCPSMI_BASEADDR_LSB,
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MTL_GSCPSMI_BASEADDR_MSB);
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if (gscpsmi_base >= i915->dsm.stolen.start &&
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gscpsmi_base < i915->dsm.stolen.end) {
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*base = gscpsmi_base;
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*size = i915->dsm.stolen.end - gscpsmi_base;
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return;
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}
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}
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switch (reg_val & GEN8_STOLEN_RESERVED_SIZE_MASK) {
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case GEN8_STOLEN_RESERVED_1M:
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*size = 1024 * 1024;
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@ -470,6 +470,9 @@
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#define XEHP_PSS_MODE2 MCR_REG(0x703c)
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#define SCOREBOARD_STALL_FLUSH_CONTROL REG_BIT(5)
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#define XEHP_PSS_CHICKEN MCR_REG(0x7044)
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#define FD_END_COLLECT REG_BIT(5)
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#define GEN7_SC_INSTDONE _MMIO(0x7100)
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#define GEN12_SC_INSTDONE_EXTRA _MMIO(0x7104)
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#define GEN12_SC_INSTDONE_EXTRA2 _MMIO(0x7108)
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@ -538,6 +541,9 @@
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#define XEHP_SQCM MCR_REG(0x8724)
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#define EN_32B_ACCESS REG_BIT(30)
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#define MTL_GSCPSMI_BASEADDR_LSB _MMIO(0x880c)
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#define MTL_GSCPSMI_BASEADDR_MSB _MMIO(0x8810)
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#define HSW_IDICR _MMIO(0x9008)
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#define IDIHASHMSK(x) (((x) & 0x3f) << 16)
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@ -1209,6 +1215,7 @@
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#define GEN12_DISABLE_EARLY_READ REG_BIT(14)
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#define GEN12_ENABLE_LARGE_GRF_MODE REG_BIT(12)
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#define GEN12_PUSH_CONST_DEREF_HOLD_DIS REG_BIT(8)
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#define XELPG_DISABLE_TDL_SVHS_GATING REG_BIT(1)
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#define GEN12_DISABLE_DOP_GATING REG_BIT(0)
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#define RT_CTRL MCR_REG(0xe530)
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@ -1221,6 +1228,8 @@
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#define XEHP_HDC_CHICKEN0 MCR_REG(0xe5f0)
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#define LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK REG_GENMASK(13, 11)
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#define DIS_ATOMIC_CHAINING_TYPED_WRITES REG_BIT(3)
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#define ICL_HDC_MODE MCR_REG(0xe5f4)
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#define EU_PERF_CNTL2 PERF_REG(0xe658)
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@ -781,6 +781,9 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
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/* Wa_18019271663:dg2 */
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wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);
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/* Wa_14019877138:dg2 */
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wa_mcr_masked_en(wal, XEHP_PSS_CHICKEN, FD_END_COLLECT);
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}
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static void xelpg_ctx_gt_tuning_init(struct intel_engine_cs *engine,
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@ -826,6 +829,9 @@ static void xelpg_ctx_workarounds_init(struct intel_engine_cs *engine,
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/* Wa_18019271663 */
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wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);
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/* Wa_14019877138 */
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wa_mcr_masked_en(wal, XEHP_PSS_CHICKEN, FD_END_COLLECT);
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}
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static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine,
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@ -2338,6 +2344,14 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
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LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK);
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}
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if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) ||
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IS_DG2(i915)) {
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/* Wa_14015150844 */
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wa_mcr_add(wal, XEHP_HDC_CHICKEN0, 0,
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_MASKED_BIT_ENABLE(DIS_ATOMIC_CHAINING_TYPED_WRITES),
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0, true);
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}
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if (IS_DG2_G11(i915) || IS_DG2_G10(i915)) {
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/* Wa_22014600077:dg2 */
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wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0,
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@ -2887,10 +2901,14 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
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if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_B0, STEP_FOREVER) ||
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IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_B0, STEP_FOREVER) ||
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IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 74), IP_VER(12, 74)))
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IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 74), IP_VER(12, 74))) {
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/* Wa_14017856879 */
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wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3, MTL_DISABLE_FIX_FOR_EOT_FLUSH);
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/* Wa_14020495402 */
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wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, XELPG_DISABLE_TDL_SVHS_GATING);
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}
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if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
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IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
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/*
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@ -2258,6 +2258,7 @@ inteldrm_attach(struct device *parent, struct device *self, void *aux)
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int mmio_bar, mmio_size, mmio_type;
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int ret;
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dev_priv->pa = pa;
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dev_priv->pc = pa->pa_pc;
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dev_priv->tag = pa->pa_tag;
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dev_priv->iot = pa->pa_iot;
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@ -239,6 +239,7 @@ struct inteldrm_softc {
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struct i915_dsm dsm;
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#ifdef __OpenBSD__
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struct pci_attach_args *pa;
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pci_chipset_tag_t pc;
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pcitag_t tag;
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struct extent *memex;
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@ -290,20 +290,25 @@ static void intel_device_info_subplatform_init(struct drm_i915_private *i915)
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static void ip_ver_read(struct drm_i915_private *i915, u32 offset, struct intel_ip_version *ip)
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{
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STUB();
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#ifdef notyet
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#ifdef __linux__
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struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
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void __iomem *addr;
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#endif
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u32 val;
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u8 expected_ver = ip->ver;
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u8 expected_rel = ip->rel;
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#ifdef __linux__
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addr = pci_iomap_range(pdev, 0, offset, sizeof(u32));
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if (drm_WARN_ON(&i915->drm, !addr))
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return;
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val = ioread32(addr);
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pci_iounmap(pdev, addr);
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#else
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val = bus_space_read_4(i915->vga_regs->bst, i915->vga_regs->bsh,
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offset);
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#endif
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ip->ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val);
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ip->rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
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@ -314,7 +319,6 @@ static void ip_ver_read(struct drm_i915_private *i915, u32 offset, struct intel_
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drm_dbg(&i915->drm,
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"Hardware reports GMD IP version %u.%u (REG[0x%x] = 0x%08x) but minimum expected is %u.%u\n",
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ip->ver, ip->rel, offset, val, expected_ver, expected_rel);
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#endif
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}
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/*
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