sync with OpenBSD -current
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32e75f5310
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F42C07F07E2E35B7
23 changed files with 206 additions and 161 deletions
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@ -1001,25 +1001,21 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
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u32 pte_flags;
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int ret;
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/* For Modern GENs the PTEs and register space are split in the BAR */
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type = pci_mapreg_type(i915->pc, i915->tag, 0x10);
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ret = -pci_mapreg_info(i915->pc, i915->tag, 0x10, type,
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&addr, &len, NULL);
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if (ret)
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return ret;
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/*
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* On BXT+/ICL+ writes larger than 64 bit to the GTT pagetable range
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* will be dropped. For WC mappings in general we have 64 byte burst
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* writes when the WC buffer is flushed, so we can't use it, but have to
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* resort to an uncached mapping. The WC issue is easily caught by the
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* readback check when writing GTT PTE entries.
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*/
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if (IS_GEN9_LP(i915) || GRAPHICS_VER(i915) >= 11)
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flags = 0;
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else
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GEM_WARN_ON(len != gen6_gttmmadr_size(i915));
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phys_addr = addr + gen6_gttadr_offset(i915);
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if (needs_wc_ggtt_mapping(i915))
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flags = BUS_SPACE_MAP_PREFETCHABLE;
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ret = -bus_space_map(i915->bst, addr + len / 2, size,
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else
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flags = 0;
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ret = -bus_space_map(i915->bst, phys_addr, size,
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flags | BUS_SPACE_MAP_LINEAR, &ggtt->gsm_bsh);
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if (ret) {
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drm_err(&i915->drm, "Failed to map the ggtt page table\n");
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@ -1028,7 +1024,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
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ggtt->gsm = bus_space_vaddr(i915->bst, ggtt->gsm_bsh);
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ggtt->gsm_size = size;
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if (!ggtt->gsm) {
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DRM_ERROR("Failed to map the ggtt page table\n");
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drm_err(&i915->drm, "Failed to map the ggtt page table\n");
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return -ENOMEM;
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}
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@ -184,7 +184,7 @@ static int guc_wait_ucode(struct intel_guc *guc)
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* in the seconds range. However, there is a limit on how long an
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* individual wait_for() can wait. So wrap it in a loop.
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*/
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before_freq = intel_rps_read_actual_frequency(&uncore->gt->rps);
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before_freq = intel_rps_read_actual_frequency(>->rps);
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before = ktime_get();
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for (count = 0; count < GUC_LOAD_RETRY_LIMIT; count++) {
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ret = wait_for(guc_load_done(uncore, &status, &success), 1000);
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@ -192,7 +192,7 @@ static int guc_wait_ucode(struct intel_guc *guc)
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break;
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guc_dbg(guc, "load still in progress, count = %d, freq = %dMHz, status = 0x%08X [0x%02X/%02X]\n",
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count, intel_rps_read_actual_frequency(&uncore->gt->rps), status,
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count, intel_rps_read_actual_frequency(>->rps), status,
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REG_FIELD_GET(GS_BOOTROM_MASK, status),
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REG_FIELD_GET(GS_UKERNEL_MASK, status));
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}
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@ -204,7 +204,7 @@ static int guc_wait_ucode(struct intel_guc *guc)
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u32 bootrom = REG_FIELD_GET(GS_BOOTROM_MASK, status);
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guc_info(guc, "load failed: status = 0x%08X, time = %lldms, freq = %dMHz, ret = %d\n",
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status, delta_ms, intel_rps_read_actual_frequency(&uncore->gt->rps), ret);
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status, delta_ms, intel_rps_read_actual_frequency(>->rps), ret);
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guc_info(guc, "load failed: status: Reset = %d, BootROM = 0x%02X, UKernel = 0x%02X, MIA = 0x%02X, Auth = 0x%02X\n",
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REG_FIELD_GET(GS_MIA_IN_RESET, status),
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bootrom, ukernel,
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@ -254,11 +254,11 @@ static int guc_wait_ucode(struct intel_guc *guc)
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guc_warn(guc, "excessive init time: %lldms! [status = 0x%08X, count = %d, ret = %d]\n",
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delta_ms, status, count, ret);
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guc_warn(guc, "excessive init time: [freq = %dMHz, before = %dMHz, perf_limit_reasons = 0x%08X]\n",
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intel_rps_read_actual_frequency(&uncore->gt->rps), before_freq,
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intel_rps_read_actual_frequency(>->rps), before_freq,
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intel_uncore_read(uncore, intel_gt_perf_limit_reasons_reg(gt)));
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} else {
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guc_dbg(guc, "init took %lldms, freq = %dMHz, before = %dMHz, status = 0x%08X, count = %d, ret = %d\n",
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delta_ms, intel_rps_read_actual_frequency(&uncore->gt->rps),
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delta_ms, intel_rps_read_actual_frequency(>->rps),
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before_freq, status, count, ret);
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}
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@ -6,6 +6,7 @@
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#include <linux/types.h>
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#include "gt/intel_gt.h"
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#include "gt/intel_rps.h"
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#include "intel_guc_reg.h"
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#include "intel_huc.h"
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#include "intel_huc_print.h"
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@ -462,17 +463,68 @@ static const char *auth_mode_string(struct intel_huc *huc,
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return partial ? "clear media" : "all workloads";
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}
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/*
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* Use a longer timeout for debug builds so that problems can be detected
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* and analysed. But a shorter timeout for releases so that user's don't
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* wait forever to find out there is a problem. Note that the only reason
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* an end user should hit the timeout is in case of extreme thermal throttling.
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* And a system that is that hot during boot is probably dead anyway!
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*/
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#if defined(CONFIG_DRM_I915_DEBUG_GEM)
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#define HUC_LOAD_RETRY_LIMIT 20
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#else
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#define HUC_LOAD_RETRY_LIMIT 3
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#endif
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int intel_huc_wait_for_auth_complete(struct intel_huc *huc,
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enum intel_huc_authentication_type type)
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{
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struct intel_gt *gt = huc_to_gt(huc);
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int ret;
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struct intel_uncore *uncore = gt->uncore;
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ktime_t before, after, delta;
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int ret, count;
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u64 delta_ms;
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u32 before_freq;
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ret = __intel_wait_for_register(gt->uncore,
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huc->status[type].reg,
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huc->status[type].mask,
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huc->status[type].value,
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2, 50, NULL);
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/*
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* The KMD requests maximum frequency during driver load, however thermal
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* throttling can force the frequency down to minimum (although the board
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* really should never get that hot in real life!). IFWI issues have been
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* seen to cause sporadic failures to grant the higher frequency. And at
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* minimum frequency, the authentication time can be in the seconds range.
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* Note that there is a limit on how long an individual wait_for() can wait.
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* So wrap it in a loop.
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*/
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before_freq = intel_rps_read_actual_frequency(>->rps);
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before = ktime_get();
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for (count = 0; count < HUC_LOAD_RETRY_LIMIT; count++) {
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ret = __intel_wait_for_register(gt->uncore,
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huc->status[type].reg,
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huc->status[type].mask,
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huc->status[type].value,
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2, 1000, NULL);
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if (!ret)
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break;
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huc_dbg(huc, "auth still in progress, count = %d, freq = %dMHz, status = 0x%08X\n",
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count, intel_rps_read_actual_frequency(>->rps),
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huc->status[type].reg.reg);
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}
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after = ktime_get();
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delta = ktime_sub(after, before);
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delta_ms = ktime_to_ms(delta);
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if (delta_ms > 50) {
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huc_warn(huc, "excessive auth time: %lldms! [status = 0x%08X, count = %d, ret = %d]\n",
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delta_ms, huc->status[type].reg.reg, count, ret);
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huc_warn(huc, "excessive auth time: [freq = %dMHz, before = %dMHz, perf_limit_reasons = 0x%08X]\n",
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intel_rps_read_actual_frequency(>->rps), before_freq,
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intel_uncore_read(uncore, intel_gt_perf_limit_reasons_reg(gt)));
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} else {
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huc_dbg(huc, "auth took %lldms, freq = %dMHz, before = %dMHz, status = 0x%08X, count = %d, ret = %d\n",
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delta_ms, intel_rps_read_actual_frequency(>->rps),
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before_freq, huc->status[type].reg.reg, count, ret);
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}
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/* mark the load process as complete even if the wait failed */
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delayed_huc_load_complete(huc);
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