sync code with last improvements from OpenBSD
This commit is contained in:
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ab8d6e7bca
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GPG key ID:
F42C07F07E2E35B7
52 changed files with 584 additions and 229 deletions
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@ -1,4 +1,4 @@
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/* $OpenBSD: lapic.c,v 1.68 2023/04/26 10:52:55 mlarkin Exp $ */
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/* $OpenBSD: lapic.c,v 1.69 2023/08/23 01:55:46 cheloha Exp $ */
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/* $NetBSD: lapic.c,v 1.2 2003/05/08 01:04:35 fvdl Exp $ */
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/*-
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@ -499,8 +499,6 @@ lapic_initclocks(void)
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stathz = hz;
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profhz = stathz * 10;
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clockintr_init(CL_RNDSTAT);
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lapic_startclock();
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}
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@ -599,6 +597,7 @@ skip_calibration:
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lapic_per_second * (1ULL << 32) / 1000000000;
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lapic_timer_nsec_max = UINT64_MAX / lapic_timer_nsec_cycle_ratio;
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initclock_func = lapic_initclocks;
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startclock_func = lapic_startclock;
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}
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/*
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@ -1,4 +1,4 @@
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/* $OpenBSD: machdep.c,v 1.286 2023/07/27 00:28:25 guenther Exp $ */
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/* $OpenBSD: machdep.c,v 1.287 2023/08/23 01:55:45 cheloha Exp $ */
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/* $NetBSD: machdep.c,v 1.3 2003/05/07 22:58:18 fvdl Exp $ */
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/*-
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@ -227,6 +227,7 @@ paddr_t avail_end;
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void (*delay_func)(int) = i8254_delay;
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void (*initclock_func)(void) = i8254_initclocks;
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void (*startclock_func)(void) = i8254_start_both_clocks;
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/*
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* Format of boot information passed to us by 32-bit /boot
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@ -1880,6 +1881,12 @@ cpu_initclocks(void)
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(*initclock_func)();
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}
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void
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cpu_startclock(void)
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{
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(*startclock_func)();
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}
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void
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need_resched(struct cpu_info *ci)
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{
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@ -1,4 +1,4 @@
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/* $OpenBSD: cpu.h,v 1.158 2023/07/27 00:28:24 guenther Exp $ */
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/* $OpenBSD: cpu.h,v 1.159 2023/08/23 01:55:46 cheloha Exp $ */
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/* $NetBSD: cpu.h,v 1.1 2003/04/26 18:39:39 fvdl Exp $ */
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/*-
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@ -408,6 +408,8 @@ int amd64_pa_used(paddr_t);
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extern void (*cpu_idle_cycle_fcn)(void);
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#define cpu_idle_cycle() (*cpu_idle_cycle_fcn)()
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#define cpu_idle_leave() do { /* nothing */ } while (0)
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extern void (*initclock_func)(void);
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extern void (*startclock_func)(void);
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struct region_descriptor;
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void lgdt(struct region_descriptor *);
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@ -418,7 +420,6 @@ void switch_exit(struct proc *, void (*)(struct proc *));
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void proc_trampoline(void);
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/* clock.c */
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extern void (*initclock_func)(void);
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void startclocks(void);
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void rtcinit(void);
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void rtcstart(void);
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@ -426,6 +427,7 @@ void rtcstop(void);
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void i8254_delay(int);
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void i8254_initclocks(void);
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void i8254_startclock(void);
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void i8254_start_both_clocks(void);
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void i8254_inittimecounter(void);
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void i8254_inittimecounter_simple(void);
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@ -1,4 +1,4 @@
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/* $OpenBSD: clock.c,v 1.40 2023/07/25 18:16:19 cheloha Exp $ */
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/* $OpenBSD: clock.c,v 1.41 2023/08/23 01:55:46 cheloha Exp $ */
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/* $NetBSD: clock.c,v 1.1 2003/04/26 18:39:50 fvdl Exp $ */
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/*-
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@ -284,7 +284,11 @@ i8254_initclocks(void)
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stathz = 128;
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profhz = 1024; /* XXX does not divide into 1 billion */
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clockintr_init(0);
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}
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void
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i8254_start_both_clocks(void)
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{
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clockintr_cpu_init(NULL);
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/*
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@ -1,4 +1,4 @@
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/* $OpenBSD: agtimer.c,v 1.18 2023/07/25 18:16:19 cheloha Exp $ */
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/* $OpenBSD: agtimer.c,v 1.19 2023/08/23 01:55:46 cheloha Exp $ */
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/*
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* Copyright (c) 2011 Dale Rahn <drahn@openbsd.org>
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* Copyright (c) 2013 Patrick Wildt <patrick@blueri.se>
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@ -227,7 +227,6 @@ void
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agtimer_cpu_initclocks(void)
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{
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struct agtimer_softc *sc = agtimer_cd.cd_devs[0];
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uint32_t reg;
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stathz = hz;
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profhz = stathz * 10;
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@ -237,21 +236,11 @@ agtimer_cpu_initclocks(void)
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agtimer_set_clockrate(agtimer_frequency);
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}
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clockintr_cpu_init(&agtimer_intrclock);
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/* Setup secure and non-secure timer IRQs. */
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arm_intr_establish_fdt_idx(sc->sc_node, 0, IPL_CLOCK,
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agtimer_intr, NULL, "tick");
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arm_intr_establish_fdt_idx(sc->sc_node, 1, IPL_CLOCK,
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agtimer_intr, NULL, "tick");
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reg = agtimer_get_ctrl();
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reg &= ~GTIMER_CNTP_CTL_IMASK;
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reg |= GTIMER_CNTP_CTL_ENABLE;
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agtimer_set_tval(INT32_MAX);
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agtimer_set_ctrl(reg);
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clockintr_trigger();
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}
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void
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@ -1,4 +1,4 @@
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/* $OpenBSD: amptimer.c,v 1.17 2023/07/25 18:16:19 cheloha Exp $ */
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/* $OpenBSD: amptimer.c,v 1.18 2023/08/23 01:55:46 cheloha Exp $ */
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/*
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* Copyright (c) 2011 Dale Rahn <drahn@openbsd.org>
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*
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@ -301,10 +301,6 @@ amptimer_cpu_initclocks(void)
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/* Enable private timer counter and interrupt. */
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bus_space_write_4(sc->sc_iot, sc->sc_pioh, PTIMER_CTRL,
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(PTIMER_CTRL_ENABLE | PTIMER_CTRL_IRQEN));
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/* Start the clock interrupt cycle. */
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clockintr_cpu_init(&timer_intrclock);
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clockintr_trigger();
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}
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void
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/* $OpenBSD: cpu.h,v 1.63 2023/07/25 18:16:19 cheloha Exp $ */
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/* $OpenBSD: cpu.h,v 1.64 2023/08/23 01:55:46 cheloha Exp $ */
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/* $NetBSD: cpu.h,v 1.34 2003/06/23 11:01:08 martin Exp $ */
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/*
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@ -329,8 +329,6 @@ intr_restore(u_long cpsr)
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__asm volatile ("msr cpsr_c, %0" :: "r"(cpsr));
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}
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void cpu_startclock(void);
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#endif /* _KERNEL */
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#ifdef MULTIPROCESSOR
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@ -1,4 +1,4 @@
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/* $OpenBSD: agtimer.c,v 1.25 2023/08/11 01:28:19 cheloha Exp $ */
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/* $OpenBSD: agtimer.c,v 1.26 2023/08/23 01:55:46 cheloha Exp $ */
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/*
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* Copyright (c) 2011 Dale Rahn <drahn@openbsd.org>
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* Copyright (c) 2013 Patrick Wildt <patrick@blueri.se>
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@ -290,8 +290,6 @@ void
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agtimer_cpu_initclocks(void)
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{
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struct agtimer_softc *sc = agtimer_cd.cd_devs[0];
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uint32_t reg;
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uint64_t kctl;
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stathz = hz;
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profhz = stathz * 10;
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@ -304,20 +302,6 @@ agtimer_cpu_initclocks(void)
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/* configure virtual timer interrupt */
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sc->sc_ih = arm_intr_establish_fdt_idx(sc->sc_node, 2,
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IPL_CLOCK|IPL_MPSAFE, agtimer_intr, NULL, "tick");
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clockintr_cpu_init(&agtimer_intrclock);
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reg = agtimer_get_ctrl();
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reg &= ~GTIMER_CNTV_CTL_IMASK;
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reg |= GTIMER_CNTV_CTL_ENABLE;
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agtimer_set_tval(INT32_MAX);
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agtimer_set_ctrl(reg);
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clockintr_trigger();
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/* enable userland access to virtual counter */
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kctl = READ_SPECIALREG(CNTKCTL_EL1);
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WRITE_SPECIALREG(CNTKCTL_EL1, kctl | CNTKCTL_EL0VCTEN);
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}
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void
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@ -343,7 +327,8 @@ agtimer_startclock(void)
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uint64_t kctl;
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uint32_t reg;
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arm_intr_route(sc->sc_ih, 1, curcpu());
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if (!CPU_IS_PRIMARY(curcpu()))
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arm_intr_route(sc->sc_ih, 1, curcpu());
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clockintr_cpu_init(&agtimer_intrclock);
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@ -1,4 +1,4 @@
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/* $OpenBSD: cpu.h,v 1.38 2023/07/25 18:16:20 cheloha Exp $ */
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/* $OpenBSD: cpu.h,v 1.39 2023/08/23 01:55:46 cheloha Exp $ */
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/*
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* Copyright (c) 2016 Dale Rahn <drahn@dalerahn.com>
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*
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@ -344,7 +344,6 @@ intr_restore(u_long daif)
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}
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void cpu_halt(void);
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void cpu_startclock(void);
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int cpu_suspend_primary(void);
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void cpu_resume_secondary(struct cpu_info *);
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@ -1,4 +1,4 @@
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/* $OpenBSD: dmtimer.c,v 1.19 2023/07/25 18:16:19 cheloha Exp $ */
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/* $OpenBSD: dmtimer.c,v 1.20 2023/08/23 01:55:46 cheloha Exp $ */
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/*
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* Copyright (c) 2007,2009 Dale Rahn <drahn@openbsd.org>
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* Copyright (c) 2013 Raphael Graf <r@undefined.ch>
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@ -102,6 +102,7 @@ int dmtimer_intr(void *frame);
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void dmtimer_reset_tisr(void);
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void dmtimer_wait(int reg);
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void dmtimer_cpu_initclocks(void);
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void dmtimer_cpu_startclock(void);
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void dmtimer_delay(u_int);
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void dmtimer_setstatclockrate(int newhz);
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@ -195,7 +196,7 @@ dmtimer_attach(struct device *parent, struct device *self, void *args)
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dmtimer_timecounter.tc_priv = sc;
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tc_init(&dmtimer_timecounter);
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arm_clock_register(dmtimer_cpu_initclocks, dmtimer_delay,
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dmtimer_setstatclockrate, NULL);
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dmtimer_setstatclockrate, dmtimer_cpu_startclock);
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}
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else
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panic("attaching too many dmtimers at 0x%lx",
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@ -247,7 +248,11 @@ dmtimer_cpu_initclocks(void)
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bus_space_write_4(sc->sc_iot, sc->sc_ioh[0], DM_TLDR, 0);
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bus_space_write_4(sc->sc_iot, sc->sc_ioh[0], DM_TIER, DM_TIER_OVF_EN);
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bus_space_write_4(sc->sc_iot, sc->sc_ioh[0], DM_TWER, DM_TWER_OVF_EN);
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}
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void
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dmtimer_cpu_startclock(void)
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{
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/* start the clock interrupt cycle */
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clockintr_cpu_init(&dmtimer_intrclock);
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clockintr_trigger();
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@ -1,4 +1,4 @@
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/* $OpenBSD: gptimer.c,v 1.20 2023/07/25 18:16:19 cheloha Exp $ */
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/* $OpenBSD: gptimer.c,v 1.21 2023/08/23 01:55:46 cheloha Exp $ */
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/*
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* Copyright (c) 2007,2009 Dale Rahn <drahn@openbsd.org>
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*
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@ -99,6 +99,7 @@ void gptimer_attach(struct device *parent, struct device *self, void *args);
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int gptimer_intr(void *frame);
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void gptimer_wait(int reg);
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void gptimer_cpu_initclocks(void);
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void gptimer_cpu_startclock(void);
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void gptimer_delay(u_int);
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void gptimer_reset_tisr(void);
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void gptimer_setstatclockrate(int newhz);
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@ -176,7 +177,7 @@ gptimer_attach(struct device *parent, struct device *self, void *args)
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aa->aa_dev->mem[0].addr);
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arm_clock_register(gptimer_cpu_initclocks, gptimer_delay,
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gptimer_setstatclockrate, NULL);
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gptimer_setstatclockrate, gptimer_cpu_startclock);
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}
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int
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@ -216,7 +217,11 @@ gptimer_cpu_initclocks(void)
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gptimer_wait(GP_TWPS_ALL);
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bus_space_write_4(gptimer_iot, gptimer_ioh0, GP_TWER, GP_TWER_OVF_EN);
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gptimer_wait(GP_TWPS_ALL);
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}
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void
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gptimer_cpu_startclock(void)
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{
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/* start the clock interrupt cycle */
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clockintr_cpu_init(&gptimer_intrclock);
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clockintr_trigger();
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/* $OpenBSD: sxitimer.c,v 1.21 2023/07/25 18:16:19 cheloha Exp $ */
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/* $OpenBSD: sxitimer.c,v 1.22 2023/08/23 01:55:46 cheloha Exp $ */
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/*
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* Copyright (c) 2007,2009 Dale Rahn <drahn@openbsd.org>
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* Copyright (c) 2013 Raphael Graf <r@undefined.ch>
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@ -77,6 +77,7 @@ void sxitimer_attach(struct device *, struct device *, void *);
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int sxitimer_tickintr(void *);
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int sxitimer_statintr(void *);
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void sxitimer_cpu_initclocks(void);
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void sxitimer_cpu_startclock(void);
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void sxitimer_setstatclockrate(int);
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uint64_t sxitimer_readcnt64(void);
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uint32_t sxitimer_readcnt32(void);
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@ -191,7 +192,7 @@ sxitimer_attach(struct device *parent, struct device *self, void *aux)
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tc_init(&sxitimer_timecounter);
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arm_clock_register(sxitimer_cpu_initclocks, sxitimer_delay,
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sxitimer_setstatclockrate, NULL);
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sxitimer_setstatclockrate, sxitimer_cpu_startclock);
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printf(": %d kHz", sxitimer_freq[CNTRTIMER] / 1000);
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@ -229,7 +230,11 @@ sxitimer_cpu_initclocks(void)
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bus_space_write_4(sxitimer_iot, sxitimer_ioh,
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TIMER_CTRL(CNTRTIMER),
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ctrl | TIMER_ENABLE | TIMER_RELOAD | TIMER_CONTINOUS);
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}
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void
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sxitimer_cpu_startclock(void)
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{
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/* start clock interrupt cycle */
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clockintr_cpu_init(&sxitimer_intrclock);
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clockintr_trigger();
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@ -1,4 +1,4 @@
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/* $OpenBSD: lapic.c,v 1.55 2023/02/09 01:41:15 cheloha Exp $ */
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/* $OpenBSD: lapic.c,v 1.56 2023/08/23 01:55:46 cheloha Exp $ */
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/* $NetBSD: lapic.c,v 1.1.2.8 2000/02/23 06:10:50 sommerfeld Exp $ */
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/*-
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@ -327,8 +327,6 @@ lapic_initclocks(void)
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stathz = hz;
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profhz = stathz * 10;
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clockintr_init(CL_RNDSTAT);
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lapic_startclock();
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}
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extern int gettick(void); /* XXX put in header file */
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@ -422,6 +420,7 @@ lapic_calibrate_timer(struct cpu_info *ci)
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lapic_per_second * (1ULL << 32) / 1000000000;
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lapic_timer_nsec_max = UINT64_MAX / lapic_timer_nsec_cycle_ratio;
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initclock_func = lapic_initclocks;
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startclock_func = lapic_startclock;
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}
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/*
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@ -1,4 +1,4 @@
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/* $OpenBSD: machdep.c,v 1.668 2023/08/16 09:51:39 jsg Exp $ */
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/* $OpenBSD: machdep.c,v 1.669 2023/08/23 01:55:46 cheloha Exp $ */
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/* $NetBSD: machdep.c,v 1.214 1996/11/10 03:16:17 thorpej Exp $ */
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/*-
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@ -233,6 +233,7 @@ void (*cpusensors_setup)(struct cpu_info *);
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void (*delay_func)(int) = i8254_delay;
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void (*initclock_func)(void) = i8254_initclocks;
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void (*startclock_func)(void) = i8254_start_both_clocks;
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/*
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* Extent maps to manage I/O and ISA memory hole space. Allocate
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@ -3438,6 +3439,12 @@ cpu_initclocks(void)
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(*initclock_func)(); /* lapic or i8254 */
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}
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void
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cpu_startclock(void)
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{
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(*startclock_func)();
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}
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void
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need_resched(struct cpu_info *ci)
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{
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@ -1,4 +1,4 @@
|
|||
/* $OpenBSD: cpu.h,v 1.182 2023/07/25 18:16:20 cheloha Exp $ */
|
||||
/* $OpenBSD: cpu.h,v 1.183 2023/08/23 01:55:46 cheloha Exp $ */
|
||||
/* $NetBSD: cpu.h,v 1.35 1996/05/05 19:29:26 christos Exp $ */
|
||||
|
||||
/*-
|
||||
|
|
@ -399,6 +399,9 @@ extern int i386_has_sse2;
|
|||
|
||||
extern void (*update_cpuspeed)(void);
|
||||
|
||||
extern void (*initclock_func)(void);
|
||||
extern void (*startclock_func)(void);
|
||||
|
||||
/* machdep.c */
|
||||
void dumpconf(void);
|
||||
void cpu_reset(void);
|
||||
|
|
@ -416,7 +419,6 @@ void switch_exit(struct proc *);
|
|||
void proc_trampoline(void);
|
||||
|
||||
/* clock.c */
|
||||
extern void (*initclock_func)(void);
|
||||
void startclocks(void);
|
||||
void rtcinit(void);
|
||||
void rtcstart(void);
|
||||
|
|
@ -424,6 +426,7 @@ void rtcstop(void);
|
|||
void i8254_delay(int);
|
||||
void i8254_initclocks(void);
|
||||
void i8254_startclock(void);
|
||||
void i8254_start_both_clocks(void);
|
||||
void i8254_inittimecounter(void);
|
||||
void i8254_inittimecounter_simple(void);
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $OpenBSD: clock.c,v 1.66 2023/08/22 17:13:22 cheloha Exp $ */
|
||||
/* $OpenBSD: clock.c,v 1.67 2023/08/23 01:55:46 cheloha Exp $ */
|
||||
/* $NetBSD: clock.c,v 1.39 1996/05/12 23:11:54 mycroft Exp $ */
|
||||
|
||||
/*-
|
||||
|
|
@ -427,7 +427,11 @@ i8254_initclocks(void)
|
|||
stathz = 128;
|
||||
profhz = 1024; /* XXX does not divide into 1 billion */
|
||||
clockintr_init(0);
|
||||
}
|
||||
|
||||
void
|
||||
i8254_start_both_clocks(void)
|
||||
{
|
||||
clockintr_cpu_init(NULL);
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -185,7 +185,7 @@ static int amdgpu_cs_pass1(struct amdgpu_cs_parser *p,
|
|||
uint64_t *chunk_array_user;
|
||||
uint64_t *chunk_array;
|
||||
uint32_t uf_offset = 0;
|
||||
unsigned int size;
|
||||
size_t size;
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
|
|
@ -1609,15 +1609,15 @@ static int amdgpu_cs_wait_all_fences(struct amdgpu_device *adev,
|
|||
continue;
|
||||
|
||||
r = dma_fence_wait_timeout(fence, true, timeout);
|
||||
if (r > 0 && fence->error)
|
||||
r = fence->error;
|
||||
|
||||
dma_fence_put(fence);
|
||||
if (r < 0)
|
||||
return r;
|
||||
|
||||
if (r == 0)
|
||||
break;
|
||||
|
||||
if (fence->error)
|
||||
return fence->error;
|
||||
}
|
||||
|
||||
memset(wait, 0, sizeof(*wait));
|
||||
|
|
|
|||
|
|
@ -4354,6 +4354,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)
|
|||
drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, true);
|
||||
|
||||
cancel_delayed_work_sync(&adev->delayed_init_work);
|
||||
flush_delayed_work(&adev->gfx.gfx_off_delay_work);
|
||||
|
||||
amdgpu_ras_suspend(adev);
|
||||
|
||||
|
|
|
|||
|
|
@ -518,6 +518,41 @@ int amdgpu_fence_driver_sw_init(struct amdgpu_device *adev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* amdgpu_fence_need_ring_interrupt_restore - helper function to check whether
|
||||
* fence driver interrupts need to be restored.
|
||||
*
|
||||
* @ring: ring that to be checked
|
||||
*
|
||||
* Interrupts for rings that belong to GFX IP don't need to be restored
|
||||
* when the target power state is s0ix.
|
||||
*
|
||||
* Return true if need to restore interrupts, false otherwise.
|
||||
*/
|
||||
static bool amdgpu_fence_need_ring_interrupt_restore(struct amdgpu_ring *ring)
|
||||
{
|
||||
struct amdgpu_device *adev = ring->adev;
|
||||
bool is_gfx_power_domain = false;
|
||||
|
||||
switch (ring->funcs->type) {
|
||||
case AMDGPU_RING_TYPE_SDMA:
|
||||
/* SDMA 5.x+ is part of GFX power domain so it's covered by GFXOFF */
|
||||
if (adev->ip_versions[SDMA0_HWIP][0] >= IP_VERSION(5, 0, 0))
|
||||
is_gfx_power_domain = true;
|
||||
break;
|
||||
case AMDGPU_RING_TYPE_GFX:
|
||||
case AMDGPU_RING_TYPE_COMPUTE:
|
||||
case AMDGPU_RING_TYPE_KIQ:
|
||||
case AMDGPU_RING_TYPE_MES:
|
||||
is_gfx_power_domain = true;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return !(adev->in_s0ix && is_gfx_power_domain);
|
||||
}
|
||||
|
||||
/**
|
||||
* amdgpu_fence_driver_hw_fini - tear down the fence driver
|
||||
* for all possible rings.
|
||||
|
|
@ -546,7 +581,8 @@ void amdgpu_fence_driver_hw_fini(struct amdgpu_device *adev)
|
|||
amdgpu_fence_driver_force_completion(ring);
|
||||
|
||||
if (!drm_dev_is_unplugged(adev_to_drm(adev)) &&
|
||||
ring->fence_drv.irq_src)
|
||||
ring->fence_drv.irq_src &&
|
||||
amdgpu_fence_need_ring_interrupt_restore(ring))
|
||||
amdgpu_irq_put(adev, ring->fence_drv.irq_src,
|
||||
ring->fence_drv.irq_type);
|
||||
|
||||
|
|
@ -624,7 +660,8 @@ void amdgpu_fence_driver_hw_init(struct amdgpu_device *adev)
|
|||
continue;
|
||||
|
||||
/* enable the interrupt */
|
||||
if (ring->fence_drv.irq_src)
|
||||
if (ring->fence_drv.irq_src &&
|
||||
amdgpu_fence_need_ring_interrupt_restore(ring))
|
||||
amdgpu_irq_get(adev, ring->fence_drv.irq_src,
|
||||
ring->fence_drv.irq_type);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -587,15 +587,8 @@ void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable)
|
|||
|
||||
if (adev->gfx.gfx_off_req_count == 0 &&
|
||||
!adev->gfx.gfx_off_state) {
|
||||
/* If going to s2idle, no need to wait */
|
||||
if (adev->in_s0ix) {
|
||||
if (!amdgpu_dpm_set_powergating_by_smu(adev,
|
||||
AMD_IP_BLOCK_TYPE_GFX, true))
|
||||
adev->gfx.gfx_off_state = true;
|
||||
} else {
|
||||
schedule_delayed_work(&adev->gfx.gfx_off_delay_work,
|
||||
schedule_delayed_work(&adev->gfx.gfx_off_delay_work,
|
||||
delay);
|
||||
}
|
||||
}
|
||||
} else {
|
||||
if (adev->gfx.gfx_off_req_count == 0) {
|
||||
|
|
|
|||
|
|
@ -160,7 +160,6 @@ void amdgpu_irq_disable_all(struct amdgpu_device *adev)
|
|||
continue;
|
||||
|
||||
for (k = 0; k < src->num_types; ++k) {
|
||||
atomic_set(&src->enabled_types[k], 0);
|
||||
r = src->funcs->set(adev, src, k,
|
||||
AMDGPU_IRQ_STATE_DISABLE);
|
||||
if (r)
|
||||
|
|
|
|||
|
|
@ -514,6 +514,8 @@ static int psp_sw_fini(void *handle)
|
|||
kfree(cmd);
|
||||
cmd = NULL;
|
||||
|
||||
psp_free_shared_bufs(psp);
|
||||
|
||||
if (psp->km_ring.ring_mem)
|
||||
amdgpu_bo_free_kernel(&adev->firmware.rbuf,
|
||||
&psp->km_ring.ring_mem_mc_addr,
|
||||
|
|
@ -2686,8 +2688,6 @@ static int psp_hw_fini(void *handle)
|
|||
|
||||
psp_ring_destroy(psp, PSP_RING_TYPE__KM);
|
||||
|
||||
psp_free_shared_bufs(psp);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -361,6 +361,8 @@ void amdgpu_ring_fini(struct amdgpu_ring *ring)
|
|||
amdgpu_bo_free_kernel(&ring->ring_obj,
|
||||
&ring->gpu_addr,
|
||||
(void **)&ring->ring);
|
||||
} else {
|
||||
kfree(ring->fence_drv.fences);
|
||||
}
|
||||
|
||||
dma_fence_put(ring->vmid_wait);
|
||||
|
|
|
|||
|
|
@ -1414,6 +1414,7 @@ struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
|
|||
amdgpu_vm_bo_base_init(&bo_va->base, vm, bo);
|
||||
|
||||
bo_va->ref_count = 1;
|
||||
bo_va->last_pt_update = dma_fence_get_stub();
|
||||
INIT_LIST_HEAD(&bo_va->valids);
|
||||
INIT_LIST_HEAD(&bo_va->invalids);
|
||||
|
||||
|
|
@ -2142,7 +2143,8 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
|
|||
vm->update_funcs = &amdgpu_vm_cpu_funcs;
|
||||
else
|
||||
vm->update_funcs = &amdgpu_vm_sdma_funcs;
|
||||
vm->last_update = NULL;
|
||||
|
||||
vm->last_update = dma_fence_get_stub();
|
||||
vm->last_unlocked = dma_fence_get_stub();
|
||||
vm->last_tlb_flush = dma_fence_get_stub();
|
||||
|
||||
|
|
@ -2271,7 +2273,7 @@ int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
|
|||
goto unreserve_bo;
|
||||
|
||||
dma_fence_put(vm->last_update);
|
||||
vm->last_update = NULL;
|
||||
vm->last_update = dma_fence_get_stub();
|
||||
vm->is_compute_context = true;
|
||||
|
||||
/* Free the shadow bo for compute VM */
|
||||
|
|
|
|||
|
|
@ -7401,27 +7401,55 @@ is_scaling_state_different(const struct dm_connector_state *dm_state,
|
|||
}
|
||||
|
||||
#ifdef CONFIG_DRM_AMD_DC_HDCP
|
||||
static bool is_content_protection_different(struct drm_connector_state *state,
|
||||
const struct drm_connector_state *old_state,
|
||||
const struct drm_connector *connector, struct hdcp_workqueue *hdcp_w)
|
||||
static bool is_content_protection_different(struct drm_crtc_state *new_crtc_state,
|
||||
struct drm_crtc_state *old_crtc_state,
|
||||
struct drm_connector_state *new_conn_state,
|
||||
struct drm_connector_state *old_conn_state,
|
||||
const struct drm_connector *connector,
|
||||
struct hdcp_workqueue *hdcp_w)
|
||||
{
|
||||
struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
|
||||
struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state);
|
||||
|
||||
/* Handle: Type0/1 change */
|
||||
if (old_state->hdcp_content_type != state->hdcp_content_type &&
|
||||
state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
|
||||
state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
|
||||
pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
|
||||
connector->index, connector->status, connector->dpms);
|
||||
pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
|
||||
old_conn_state->content_protection, new_conn_state->content_protection);
|
||||
|
||||
if (old_crtc_state)
|
||||
pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
|
||||
old_crtc_state->enable,
|
||||
old_crtc_state->active,
|
||||
old_crtc_state->mode_changed,
|
||||
old_crtc_state->active_changed,
|
||||
old_crtc_state->connectors_changed);
|
||||
|
||||
if (new_crtc_state)
|
||||
pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
|
||||
new_crtc_state->enable,
|
||||
new_crtc_state->active,
|
||||
new_crtc_state->mode_changed,
|
||||
new_crtc_state->active_changed,
|
||||
new_crtc_state->connectors_changed);
|
||||
|
||||
/* hdcp content type change */
|
||||
if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type &&
|
||||
new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
|
||||
new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
|
||||
pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__);
|
||||
return true;
|
||||
}
|
||||
|
||||
/* CP is being re enabled, ignore this
|
||||
*
|
||||
* Handles: ENABLED -> DESIRED
|
||||
*/
|
||||
if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
|
||||
state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
|
||||
state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
|
||||
/* CP is being re enabled, ignore this */
|
||||
if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED &&
|
||||
new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
|
||||
if (new_crtc_state && new_crtc_state->mode_changed) {
|
||||
new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
|
||||
pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__);
|
||||
return true;
|
||||
};
|
||||
new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED;
|
||||
pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__);
|
||||
return false;
|
||||
}
|
||||
|
||||
|
|
@ -7429,9 +7457,9 @@ static bool is_content_protection_different(struct drm_connector_state *state,
|
|||
*
|
||||
* Handles: UNDESIRED -> ENABLED
|
||||
*/
|
||||
if (old_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
|
||||
state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
|
||||
state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
|
||||
if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED &&
|
||||
new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED)
|
||||
new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
|
||||
|
||||
/* Stream removed and re-enabled
|
||||
*
|
||||
|
|
@ -7441,10 +7469,12 @@ static bool is_content_protection_different(struct drm_connector_state *state,
|
|||
*
|
||||
* Handles: DESIRED -> DESIRED (Special case)
|
||||
*/
|
||||
if (!(old_state->crtc && old_state->crtc->enabled) &&
|
||||
state->crtc && state->crtc->enabled &&
|
||||
if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) &&
|
||||
new_conn_state->crtc && new_conn_state->crtc->enabled &&
|
||||
connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
|
||||
dm_con_state->update_hdcp = false;
|
||||
pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n",
|
||||
__func__);
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
@ -7456,35 +7486,42 @@ static bool is_content_protection_different(struct drm_connector_state *state,
|
|||
*
|
||||
* Handles: DESIRED -> DESIRED (Special case)
|
||||
*/
|
||||
if (dm_con_state->update_hdcp && state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
|
||||
connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) {
|
||||
if (dm_con_state->update_hdcp &&
|
||||
new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED &&
|
||||
connector->dpms == DRM_MODE_DPMS_ON && aconnector->dc_sink != NULL) {
|
||||
dm_con_state->update_hdcp = false;
|
||||
pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n",
|
||||
__func__);
|
||||
return true;
|
||||
}
|
||||
|
||||
/*
|
||||
* Handles: UNDESIRED -> UNDESIRED
|
||||
* DESIRED -> DESIRED
|
||||
* ENABLED -> ENABLED
|
||||
*/
|
||||
if (old_state->content_protection == state->content_protection)
|
||||
if (old_conn_state->content_protection == new_conn_state->content_protection) {
|
||||
if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) {
|
||||
if (new_crtc_state && new_crtc_state->mode_changed) {
|
||||
pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n",
|
||||
__func__);
|
||||
return true;
|
||||
};
|
||||
pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n",
|
||||
__func__);
|
||||
return false;
|
||||
};
|
||||
|
||||
pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__);
|
||||
return false;
|
||||
}
|
||||
|
||||
/*
|
||||
* Handles: UNDESIRED -> DESIRED
|
||||
* DESIRED -> UNDESIRED
|
||||
* ENABLED -> UNDESIRED
|
||||
*/
|
||||
if (state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED)
|
||||
if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED) {
|
||||
pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n",
|
||||
__func__);
|
||||
return true;
|
||||
}
|
||||
|
||||
/*
|
||||
* Handles: DESIRED -> ENABLED
|
||||
*/
|
||||
pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__);
|
||||
return false;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
static void remove_stream(struct amdgpu_device *adev,
|
||||
struct amdgpu_crtc *acrtc,
|
||||
struct dc_stream_state *stream)
|
||||
|
|
@ -8339,10 +8376,67 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
|
|||
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
|
||||
struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
|
||||
|
||||
new_crtc_state = NULL;
|
||||
if (!adev->dm.hdcp_workqueue)
|
||||
continue;
|
||||
|
||||
if (acrtc)
|
||||
pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i);
|
||||
|
||||
if (!connector)
|
||||
continue;
|
||||
|
||||
pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
|
||||
connector->index, connector->status, connector->dpms);
|
||||
pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
|
||||
old_con_state->content_protection, new_con_state->content_protection);
|
||||
|
||||
if (aconnector->dc_sink) {
|
||||
if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
|
||||
aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) {
|
||||
pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n",
|
||||
aconnector->dc_sink->edid_caps.display_name);
|
||||
}
|
||||
}
|
||||
|
||||
new_crtc_state = NULL;
|
||||
old_crtc_state = NULL;
|
||||
|
||||
if (acrtc) {
|
||||
new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
|
||||
old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
|
||||
}
|
||||
|
||||
if (old_crtc_state)
|
||||
pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
|
||||
old_crtc_state->enable,
|
||||
old_crtc_state->active,
|
||||
old_crtc_state->mode_changed,
|
||||
old_crtc_state->active_changed,
|
||||
old_crtc_state->connectors_changed);
|
||||
|
||||
if (new_crtc_state)
|
||||
pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
|
||||
new_crtc_state->enable,
|
||||
new_crtc_state->active,
|
||||
new_crtc_state->mode_changed,
|
||||
new_crtc_state->active_changed,
|
||||
new_crtc_state->connectors_changed);
|
||||
}
|
||||
|
||||
for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
|
||||
struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
|
||||
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
|
||||
struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
|
||||
|
||||
if (!adev->dm.hdcp_workqueue)
|
||||
continue;
|
||||
|
||||
new_crtc_state = NULL;
|
||||
old_crtc_state = NULL;
|
||||
|
||||
if (acrtc) {
|
||||
new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
|
||||
old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
|
||||
}
|
||||
|
||||
dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
|
||||
|
||||
|
|
@ -8354,11 +8448,44 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
|
|||
continue;
|
||||
}
|
||||
|
||||
if (is_content_protection_different(new_con_state, old_con_state, connector, adev->dm.hdcp_workqueue))
|
||||
if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state,
|
||||
old_con_state, connector, adev->dm.hdcp_workqueue)) {
|
||||
/* when display is unplugged from mst hub, connctor will
|
||||
* be destroyed within dm_dp_mst_connector_destroy. connector
|
||||
* hdcp perperties, like type, undesired, desired, enabled,
|
||||
* will be lost. So, save hdcp properties into hdcp_work within
|
||||
* amdgpu_dm_atomic_commit_tail. if the same display is
|
||||
* plugged back with same display index, its hdcp properties
|
||||
* will be retrieved from hdcp_work within dm_dp_mst_get_modes
|
||||
*/
|
||||
|
||||
bool enable_encryption = false;
|
||||
|
||||
if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED)
|
||||
enable_encryption = true;
|
||||
|
||||
if (aconnector->dc_link && aconnector->dc_sink &&
|
||||
aconnector->dc_link->type == dc_connection_mst_branch) {
|
||||
struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue;
|
||||
struct hdcp_workqueue *hdcp_w =
|
||||
&hdcp_work[aconnector->dc_link->link_index];
|
||||
|
||||
hdcp_w->hdcp_content_type[connector->index] =
|
||||
new_con_state->hdcp_content_type;
|
||||
hdcp_w->content_protection[connector->index] =
|
||||
new_con_state->content_protection;
|
||||
}
|
||||
|
||||
if (new_crtc_state && new_crtc_state->mode_changed &&
|
||||
new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED)
|
||||
enable_encryption = true;
|
||||
|
||||
DRM_INFO("[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption);
|
||||
|
||||
hdcp_update_display(
|
||||
adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
|
||||
new_con_state->hdcp_content_type,
|
||||
new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED);
|
||||
new_con_state->hdcp_content_type, enable_encryption);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -52,6 +52,20 @@ struct hdcp_workqueue {
|
|||
struct mod_hdcp_link link;
|
||||
|
||||
enum mod_hdcp_encryption_status encryption_status;
|
||||
|
||||
/* when display is unplugged from mst hub, connctor will be
|
||||
* destroyed within dm_dp_mst_connector_destroy. connector
|
||||
* hdcp perperties, like type, undesired, desired, enabled,
|
||||
* will be lost. So, save hdcp properties into hdcp_work within
|
||||
* amdgpu_dm_atomic_commit_tail. if the same display is
|
||||
* plugged back with same display index, its hdcp properties
|
||||
* will be retrieved from hdcp_work within dm_dp_mst_get_modes
|
||||
*/
|
||||
/* un-desired, desired, enabled */
|
||||
unsigned int content_protection[AMDGPU_DM_MAX_DISPLAY_INDEX];
|
||||
/* hdcp1.x, hdcp2.x */
|
||||
unsigned int hdcp_content_type[AMDGPU_DM_MAX_DISPLAY_INDEX];
|
||||
|
||||
uint8_t max_link;
|
||||
|
||||
uint8_t *srm;
|
||||
|
|
|
|||
|
|
@ -32,6 +32,10 @@
|
|||
#include "amdgpu_dm.h"
|
||||
#include "amdgpu_dm_mst_types.h"
|
||||
|
||||
#ifdef CONFIG_DRM_AMD_DC_HDCP
|
||||
#include "amdgpu_dm_hdcp.h"
|
||||
#endif
|
||||
|
||||
#include "dc.h"
|
||||
#include "dm_helpers.h"
|
||||
|
||||
|
|
@ -363,6 +367,32 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector)
|
|||
/* dc_link_add_remote_sink returns a new reference */
|
||||
aconnector->dc_sink = dc_sink;
|
||||
|
||||
/* when display is unplugged from mst hub, connctor will be
|
||||
* destroyed within dm_dp_mst_connector_destroy. connector
|
||||
* hdcp perperties, like type, undesired, desired, enabled,
|
||||
* will be lost. So, save hdcp properties into hdcp_work within
|
||||
* amdgpu_dm_atomic_commit_tail. if the same display is
|
||||
* plugged back with same display index, its hdcp properties
|
||||
* will be retrieved from hdcp_work within dm_dp_mst_get_modes
|
||||
*/
|
||||
#ifdef CONFIG_DRM_AMD_DC_HDCP
|
||||
if (aconnector->dc_sink && connector->state) {
|
||||
struct drm_device *dev = connector->dev;
|
||||
struct amdgpu_device *adev = drm_to_adev(dev);
|
||||
|
||||
if (adev->dm.hdcp_workqueue) {
|
||||
struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue;
|
||||
struct hdcp_workqueue *hdcp_w =
|
||||
&hdcp_work[aconnector->dc_link->link_index];
|
||||
|
||||
connector->state->hdcp_content_type =
|
||||
hdcp_w->hdcp_content_type[connector->index];
|
||||
connector->state->content_protection =
|
||||
hdcp_w->content_protection[connector->index];
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
if (aconnector->dc_sink) {
|
||||
amdgpu_dm_update_freesync_caps(
|
||||
connector, aconnector->edid);
|
||||
|
|
|
|||
|
|
@ -230,7 +230,8 @@
|
|||
type DTBCLK_P2_SRC_SEL;\
|
||||
type DTBCLK_P2_EN;\
|
||||
type DTBCLK_P3_SRC_SEL;\
|
||||
type DTBCLK_P3_EN;
|
||||
type DTBCLK_P3_EN;\
|
||||
type DENTIST_DISPCLK_CHG_DONE;
|
||||
|
||||
struct dccg_shift {
|
||||
DCCG_REG_FIELD_LIST(uint8_t)
|
||||
|
|
|
|||
|
|
@ -47,6 +47,14 @@ void dccg31_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk)
|
|||
{
|
||||
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
|
||||
|
||||
if (dccg->dpp_clock_gated[dpp_inst]) {
|
||||
/*
|
||||
* Do not update the DPPCLK DTO if the clock is stopped.
|
||||
* It is treated the same as if the pipe itself were in PG.
|
||||
*/
|
||||
return;
|
||||
}
|
||||
|
||||
if (dccg->ref_dppclk && req_dppclk) {
|
||||
int ref_dppclk = dccg->ref_dppclk;
|
||||
int modulo, phase;
|
||||
|
|
|
|||
|
|
@ -296,6 +296,9 @@ static void dccg314_dpp_root_clock_control(
|
|||
{
|
||||
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
|
||||
|
||||
if (dccg->dpp_clock_gated[dpp_inst] != clock_on)
|
||||
return;
|
||||
|
||||
if (clock_on) {
|
||||
/* turn off the DTO and leave phase/modulo at max */
|
||||
REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_ENABLE[dpp_inst], 0);
|
||||
|
|
@ -309,6 +312,8 @@ static void dccg314_dpp_root_clock_control(
|
|||
DPPCLK0_DTO_PHASE, 0,
|
||||
DPPCLK0_DTO_MODULO, 1);
|
||||
}
|
||||
|
||||
dccg->dpp_clock_gated[dpp_inst] = !clock_on;
|
||||
}
|
||||
|
||||
static const struct dccg_funcs dccg314_funcs = {
|
||||
|
|
|
|||
|
|
@ -920,6 +920,22 @@ static const struct dc_debug_options debug_defaults_drv = {
|
|||
.afmt = true,
|
||||
}
|
||||
},
|
||||
|
||||
.root_clock_optimization = {
|
||||
.bits = {
|
||||
.dpp = true,
|
||||
.dsc = false,
|
||||
.hdmistream = false,
|
||||
.hdmichar = false,
|
||||
.dpstream = false,
|
||||
.symclk32_se = false,
|
||||
.symclk32_le = false,
|
||||
.symclk_fe = false,
|
||||
.physymclk = false,
|
||||
.dpiasymclk = false,
|
||||
}
|
||||
},
|
||||
|
||||
.seamless_boot_odm_combine = true
|
||||
};
|
||||
|
||||
|
|
@ -1917,6 +1933,10 @@ static bool dcn314_resource_construct(
|
|||
dc->debug = debug_defaults_drv;
|
||||
else
|
||||
dc->debug = debug_defaults_diags;
|
||||
|
||||
/* Disable root clock optimization */
|
||||
dc->debug.root_clock_optimization.u32All = 0;
|
||||
|
||||
// Init the vm_helper
|
||||
if (dc->vm_helper)
|
||||
vm_helper_init(dc->vm_helper, 16);
|
||||
|
|
|
|||
|
|
@ -42,6 +42,20 @@
|
|||
#define DC_LOGGER \
|
||||
dccg->ctx->logger
|
||||
|
||||
/* This function is a workaround for writing to OTG_PIXEL_RATE_DIV
|
||||
* without the probability of causing a DIG FIFO error.
|
||||
*/
|
||||
static void dccg32_wait_for_dentist_change_done(
|
||||
struct dccg *dccg)
|
||||
{
|
||||
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
|
||||
|
||||
uint32_t dentist_dispclk_value = REG_READ(DENTIST_DISPCLK_CNTL);
|
||||
|
||||
REG_WRITE(DENTIST_DISPCLK_CNTL, dentist_dispclk_value);
|
||||
REG_WAIT(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, 1, 50, 2000);
|
||||
}
|
||||
|
||||
static void dccg32_get_pixel_rate_div(
|
||||
struct dccg *dccg,
|
||||
uint32_t otg_inst,
|
||||
|
|
@ -110,21 +124,29 @@ static void dccg32_set_pixel_rate_div(
|
|||
REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
|
||||
OTG0_PIXEL_RATE_DIVK1, k1,
|
||||
OTG0_PIXEL_RATE_DIVK2, k2);
|
||||
|
||||
dccg32_wait_for_dentist_change_done(dccg);
|
||||
break;
|
||||
case 1:
|
||||
REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
|
||||
OTG1_PIXEL_RATE_DIVK1, k1,
|
||||
OTG1_PIXEL_RATE_DIVK2, k2);
|
||||
|
||||
dccg32_wait_for_dentist_change_done(dccg);
|
||||
break;
|
||||
case 2:
|
||||
REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
|
||||
OTG2_PIXEL_RATE_DIVK1, k1,
|
||||
OTG2_PIXEL_RATE_DIVK2, k2);
|
||||
|
||||
dccg32_wait_for_dentist_change_done(dccg);
|
||||
break;
|
||||
case 3:
|
||||
REG_UPDATE_2(OTG_PIXEL_RATE_DIV,
|
||||
OTG3_PIXEL_RATE_DIVK1, k1,
|
||||
OTG3_PIXEL_RATE_DIVK2, k2);
|
||||
|
||||
dccg32_wait_for_dentist_change_done(dccg);
|
||||
break;
|
||||
default:
|
||||
BREAK_TO_DEBUGGER();
|
||||
|
|
|
|||
|
|
@ -147,7 +147,8 @@
|
|||
DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P3_SRC_SEL, mask_sh),\
|
||||
DCCG_SF(DTBCLK_P_CNTL, DTBCLK_P3_EN, mask_sh),\
|
||||
DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
|
||||
DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh)
|
||||
DCCG_SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\
|
||||
DCCG_SF(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_CHG_DONE, mask_sh)
|
||||
|
||||
|
||||
struct dccg *dccg32_create(
|
||||
|
|
|
|||
|
|
@ -1177,7 +1177,7 @@ unsigned int dcn32_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsign
|
|||
*k2_div = PIXEL_RATE_DIV_BY_2;
|
||||
else
|
||||
*k2_div = PIXEL_RATE_DIV_BY_4;
|
||||
} else if (dc_is_dp_signal(stream->signal)) {
|
||||
} else if (dc_is_dp_signal(stream->signal) || dc_is_virtual_signal(stream->signal)) {
|
||||
if (two_pix_per_container) {
|
||||
*k1_div = PIXEL_RATE_DIV_BY_1;
|
||||
*k2_div = PIXEL_RATE_DIV_BY_2;
|
||||
|
|
|
|||
|
|
@ -1272,7 +1272,8 @@ unsigned int dcn32_calc_num_avail_chans_for_mall(struct dc *dc, int num_chans);
|
|||
DCCG_SRII(PHASE, DTBCLK_DTO, 0), DCCG_SRII(PHASE, DTBCLK_DTO, 1), \
|
||||
DCCG_SRII(PHASE, DTBCLK_DTO, 2), DCCG_SRII(PHASE, DTBCLK_DTO, 3), \
|
||||
SR(DCCG_AUDIO_DTBCLK_DTO_MODULO), SR(DCCG_AUDIO_DTBCLK_DTO_PHASE), \
|
||||
SR(OTG_PIXEL_RATE_DIV), SR(DTBCLK_P_CNTL), SR(DCCG_AUDIO_DTO_SOURCE) \
|
||||
SR(OTG_PIXEL_RATE_DIV), SR(DTBCLK_P_CNTL), \
|
||||
SR(DCCG_AUDIO_DTO_SOURCE), SR(DENTIST_DISPCLK_CNTL) \
|
||||
)
|
||||
|
||||
/* VMID */
|
||||
|
|
|
|||
|
|
@ -808,7 +808,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
|
|||
v->SwathHeightC[k],
|
||||
TWait,
|
||||
(v->DRAMSpeedPerState[mode_lib->vba.VoltageLevel] <= MEM_STROBE_FREQ_MHZ ||
|
||||
v->DCFCLKPerState[mode_lib->vba.VoltageLevel] <= MIN_DCFCLK_FREQ_MHZ) ?
|
||||
v->DCFCLKPerState[mode_lib->vba.VoltageLevel] <= DCFCLK_FREQ_EXTRA_PREFETCH_REQ_MHZ) ?
|
||||
mode_lib->vba.ip.min_prefetch_in_strobe_us : 0,
|
||||
/* Output */
|
||||
&v->DSTXAfterScaler[k],
|
||||
|
|
@ -3289,7 +3289,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
|
|||
v->swath_width_chroma_ub_this_state[k],
|
||||
v->SwathHeightYThisState[k],
|
||||
v->SwathHeightCThisState[k], v->TWait,
|
||||
(v->DRAMSpeedPerState[i] <= MEM_STROBE_FREQ_MHZ || v->DCFCLKState[i][j] <= MIN_DCFCLK_FREQ_MHZ) ?
|
||||
(v->DRAMSpeedPerState[i] <= MEM_STROBE_FREQ_MHZ || v->DCFCLKState[i][j] <= DCFCLK_FREQ_EXTRA_PREFETCH_REQ_MHZ) ?
|
||||
mode_lib->vba.ip.min_prefetch_in_strobe_us : 0,
|
||||
|
||||
/* Output */
|
||||
|
|
|
|||
|
|
@ -52,7 +52,7 @@
|
|||
#define BPP_BLENDED_PIPE 0xffffffff
|
||||
|
||||
#define MEM_STROBE_FREQ_MHZ 1600
|
||||
#define MIN_DCFCLK_FREQ_MHZ 200
|
||||
#define DCFCLK_FREQ_EXTRA_PREFETCH_REQ_MHZ 300
|
||||
#define MEM_STROBE_MAX_DELIVERY_TIME_US 60.0
|
||||
|
||||
struct display_mode_lib;
|
||||
|
|
|
|||
|
|
@ -68,6 +68,7 @@ struct dccg {
|
|||
const struct dccg_funcs *funcs;
|
||||
int pipe_dppclk_khz[MAX_PIPES];
|
||||
int ref_dppclk;
|
||||
bool dpp_clock_gated[MAX_PIPES];
|
||||
//int dtbclk_khz[MAX_PIPES];/* TODO needs to be removed */
|
||||
//int audio_dtbclk_khz;/* TODO needs to be removed */
|
||||
//int ref_dtbclk_khz;/* TODO needs to be removed */
|
||||
|
|
|
|||
|
|
@ -1562,9 +1562,9 @@ static int smu_disable_dpms(struct smu_context *smu)
|
|||
|
||||
/*
|
||||
* For SMU 13.0.4/11, PMFW will handle the features disablement properly
|
||||
* for gpu reset case. Driver involvement is unnecessary.
|
||||
* for gpu reset and S0i3 cases. Driver involvement is unnecessary.
|
||||
*/
|
||||
if (amdgpu_in_reset(adev)) {
|
||||
if (amdgpu_in_reset(adev) || adev->in_s0ix) {
|
||||
switch (adev->ip_versions[MP1_HWIP][0]) {
|
||||
case IP_VERSION(13, 0, 4):
|
||||
case IP_VERSION(13, 0, 11):
|
||||
|
|
|
|||
|
|
@ -588,7 +588,9 @@ err0_out:
|
|||
return -ENOMEM;
|
||||
}
|
||||
|
||||
static uint32_t sienna_cichlid_get_throttler_status_locked(struct smu_context *smu)
|
||||
static uint32_t sienna_cichlid_get_throttler_status_locked(struct smu_context *smu,
|
||||
bool use_metrics_v3,
|
||||
bool use_metrics_v2)
|
||||
{
|
||||
struct smu_table_context *smu_table= &smu->smu_table;
|
||||
SmuMetricsExternal_t *metrics_ext =
|
||||
|
|
@ -596,13 +598,11 @@ static uint32_t sienna_cichlid_get_throttler_status_locked(struct smu_context *s
|
|||
uint32_t throttler_status = 0;
|
||||
int i;
|
||||
|
||||
if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
|
||||
(smu->smc_fw_version >= 0x3A4900)) {
|
||||
if (use_metrics_v3) {
|
||||
for (i = 0; i < THROTTLER_COUNT; i++)
|
||||
throttler_status |=
|
||||
(metrics_ext->SmuMetrics_V3.ThrottlingPercentage[i] ? 1U << i : 0);
|
||||
} else if ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
|
||||
(smu->smc_fw_version >= 0x3A4300)) {
|
||||
} else if (use_metrics_v2) {
|
||||
for (i = 0; i < THROTTLER_COUNT; i++)
|
||||
throttler_status |=
|
||||
(metrics_ext->SmuMetrics_V2.ThrottlingPercentage[i] ? 1U << i : 0);
|
||||
|
|
@ -864,7 +864,7 @@ static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
|
|||
metrics->TemperatureVrSoc) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
|
||||
break;
|
||||
case METRICS_THROTTLER_STATUS:
|
||||
*value = sienna_cichlid_get_throttler_status_locked(smu);
|
||||
*value = sienna_cichlid_get_throttler_status_locked(smu, use_metrics_v3, use_metrics_v2);
|
||||
break;
|
||||
case METRICS_CURR_FANSPEED:
|
||||
*value = use_metrics_v3 ? metrics_v3->CurrFanSpeed :
|
||||
|
|
@ -4019,7 +4019,7 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
|
|||
gpu_metrics->current_dclk1 = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_DCLK_1] :
|
||||
use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] : metrics->CurrClock[PPCLK_DCLK_1];
|
||||
|
||||
gpu_metrics->throttle_status = sienna_cichlid_get_throttler_status_locked(smu);
|
||||
gpu_metrics->throttle_status = sienna_cichlid_get_throttler_status_locked(smu, use_metrics_v3, use_metrics_v2);
|
||||
gpu_metrics->indep_throttle_status =
|
||||
smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status,
|
||||
sienna_cichlid_throttler_map);
|
||||
|
|
|
|||
|
|
@ -2727,7 +2727,7 @@ static struct intel_sdvo_connector *intel_sdvo_connector_alloc(void)
|
|||
__drm_atomic_helper_connector_reset(&sdvo_connector->base.base,
|
||||
&conn_state->base.base);
|
||||
|
||||
INIT_LIST_HEAD(&sdvo_connector->base.panel.fixed_modes);
|
||||
intel_panel_init_alloc(&sdvo_connector->base);
|
||||
|
||||
return sdvo_connector;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $OpenBSD: kern_clock.c,v 1.114 2023/08/22 13:46:20 jsg Exp $ */
|
||||
/* $OpenBSD: kern_clock.c,v 1.115 2023/08/23 01:55:45 cheloha Exp $ */
|
||||
/* $NetBSD: kern_clock.c,v 1.34 1996/06/09 04:51:03 briggs Exp $ */
|
||||
|
||||
/*-
|
||||
|
|
@ -103,6 +103,9 @@ initclocks(void)
|
|||
profclock_period = 1000000000 / profhz;
|
||||
|
||||
inittimecounter();
|
||||
|
||||
/* Start dispatching clock interrupts on the primary CPU. */
|
||||
cpu_startclock();
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $OpenBSD: systm.h,v 1.164 2023/08/05 20:07:56 cheloha Exp $ */
|
||||
/* $OpenBSD: systm.h,v 1.165 2023/08/23 01:55:45 cheloha Exp $ */
|
||||
/* $NetBSD: systm.h,v 1.50 1996/06/09 04:55:09 briggs Exp $ */
|
||||
|
||||
/*-
|
||||
|
|
@ -243,6 +243,7 @@ void initclocks(void);
|
|||
void inittodr(time_t);
|
||||
void resettodr(void);
|
||||
void cpu_initclocks(void);
|
||||
void cpu_startclock(void);
|
||||
|
||||
void startprofclock(struct process *);
|
||||
void stopprofclock(struct process *);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue