sync with OpenBSD -current

This commit is contained in:
purplerain 2024-06-14 20:32:23 +00:00
parent f4a22ff4b2
commit 9dfe537fef
Signed by: purplerain
GPG key ID: F42C07F07E2E35B7
85 changed files with 12490 additions and 6835 deletions

View file

@ -1,4 +1,4 @@
/* $OpenBSD: ccp.c,v 1.4 2024/06/12 12:54:54 bluhm Exp $ */
/* $OpenBSD: ccp.c,v 1.5 2024/06/13 17:59:08 bluhm Exp $ */
/*
* Copyright (c) 2018 David Gwynne <dlg@openbsd.org>
@ -58,7 +58,7 @@ ccp_attach(struct ccp_softc *sc)
timeout_set(&sc->sc_tick, ccp_rng, sc);
ccp_rng(sc);
if (sc->sc_psp_attached)
if (sc->sc_psp_attached != 0)
printf(", RNG\n");
else
printf(": RNG\n");
@ -127,8 +127,6 @@ psp_attach(struct ccp_softc *sc)
if (psp_get_pstatus(&pst) || pst.state != 0)
goto fail_3;
printf(", SEV");
/*
* create and map Trusted Memory Region (TMR); size 1 Mbyte,
* needs to be aligend to 1 Mbyte.
@ -158,6 +156,8 @@ psp_attach(struct ccp_softc *sc)
if (psp_init(&init))
goto fail_7;
printf(", SEV");
psp_get_pstatus(&pst);
if ((pst.state == 1) && (pst.cfges_build & 0x1))
printf(", SEV-ES");
@ -184,6 +184,7 @@ fail_0:
bus_dmamap_destroy(sc->sc_dmat, sc->sc_cmd_map);
ccp_softc = NULL;
sc->sc_psp_attached = -1;
return (0);
}
@ -240,11 +241,8 @@ ccp_docmd(struct ccp_softc *sc, int cmd, uint64_t paddr)
/* Did PSP sent a response code? */
if (status & PSP_CMDRESP_RESPONSE) {
if ((status & PSP_STATUS_MASK) != PSP_STATUS_SUCCESS) {
printf("%s: command failed: 0x%x\n", __func__,
(status & PSP_STATUS_MASK));
if ((status & PSP_STATUS_MASK) != PSP_STATUS_SUCCESS)
return (1);
}
}
return (0);
@ -265,12 +263,11 @@ psp_init(struct psp_init *uinit)
init->tmr_length = uinit->tmr_length;
ret = ccp_docmd(sc, PSP_CMD_INIT, sc->sc_cmd_map->dm_segs[0].ds_addr);
wbinvd_on_all_cpus();
if (ret != 0)
return (EIO);
wbinvd_on_all_cpus();
return (0);
}

View file

@ -1,4 +1,4 @@
/* $OpenBSD: ccpvar.h,v 1.2 2024/06/12 12:54:54 bluhm Exp $ */
/* $OpenBSD: ccpvar.h,v 1.3 2024/06/13 17:59:08 bluhm Exp $ */
/*
* Copyright (c) 2018 David Gwynne <dlg@openbsd.org>
@ -26,7 +26,6 @@ struct ccp_softc {
struct timeout sc_tick;
bus_size_t sc_size;
int sc_psp_attached;
#ifdef __amd64__

View file

@ -1,4 +1,4 @@
/* $OpenBSD: ccp_pci.c,v 1.10 2024/06/12 12:54:54 bluhm Exp $ */
/* $OpenBSD: ccp_pci.c,v 1.11 2024/06/13 17:59:08 bluhm Exp $ */
/*
* Copyright (c) 2018 David Gwynne <dlg@openbsd.org>
@ -74,7 +74,7 @@ ccp_pci_attach(struct device *parent, struct device *self, void *aux)
}
if (pci_mapreg_map(pa, CCP_PCI_BAR, memtype, 0,
&sc->sc_iot, &sc->sc_ioh, NULL, &sc->sc_size, 0) != 0) {
&sc->sc_iot, &sc->sc_ioh, NULL, NULL, 0) != 0) {
printf(": cannot map registers\n");
return;
}
@ -107,7 +107,6 @@ psp_pci_attach(struct device *parent, struct device *self, void *aux)
if (pci_intr_map_msix(pa, 0, &ih) != 0 &&
pci_intr_map_msi(pa, &ih) != 0 && pci_intr_map(pa, &ih) != 0) {
printf(": couldn't map interrupt\n");
bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_size);
return;
}
@ -117,10 +116,14 @@ psp_pci_attach(struct device *parent, struct device *self, void *aux)
if (sc->sc_ih != NULL)
printf(": %s", intrstr);
if (psp_attach(sc)) {
/* enable interrupts */
bus_space_write_4(sc->sc_iot, sc->sc_ioh, PSP_REG_INTEN, -1);
if (!psp_attach(sc)) {
pci_intr_disestablish(pa->pa_pc, sc->sc_ih);
sc->sc_ih = NULL;
return;
}
/* enable interrupts */
bus_space_write_4(sc->sc_iot, sc->sc_ioh, PSP_REG_INTEN, -1);
}
int

View file

@ -1,4 +1,4 @@
/* $OpenBSD: drm_linux.c,v 1.113 2024/06/03 12:48:25 claudio Exp $ */
/* $OpenBSD: drm_linux.c,v 1.114 2024/06/13 18:05:54 kettenis Exp $ */
/*
* Copyright (c) 2013 Jonathan Gray <jsg@openbsd.org>
* Copyright (c) 2015, 2016 Mark Kettenis <kettenis@openbsd.org>
@ -1521,6 +1521,12 @@ acpi_format_exception(acpi_status status)
}
}
int
acpi_target_system_state(void)
{
return acpi_softc->sc_state;
}
#endif
SLIST_HEAD(,backlight_device) backlight_device_list =

View file

@ -2308,19 +2308,25 @@ inteldrm_attach(struct device *parent, struct device *self, void *aux)
intel_device_info_driver_create(dev_priv, dev->pdev->device, info);
mmio_bar = (GRAPHICS_VER(dev_priv) == 2) ? 0x14 : 0x10;
/* Before gen4, the registers and the GTT are behind different BARs.
/* from intel_uncore_setup_mmio() */
/*
* Before gen4, the registers and the GTT are behind different BARs.
* However, from gen4 onwards, the registers and the GTT are shared
* in the same BAR, so we want to restrict this ioremap from
* clobbering the GTT which we want ioremap_wc instead. Fortunately,
* the register BAR remains the same size for all the earlier
* generations up to Ironlake.
* For dgfx chips register range is expanded to 4MB, and this larger
* range is also used for integrated gpus beginning with Meteor Lake.
*/
if (GRAPHICS_VER(dev_priv) < 5)
mmio_size = 512 * 1024;
else if (IS_DGFX(dev_priv))
if (IS_DGFX(dev_priv) || GRAPHICS_VER_FULL(dev_priv) >= IP_VER(12, 70))
mmio_size = 4 * 1024 * 1024;
else
else if (GRAPHICS_VER(dev_priv) >= 5)
mmio_size = 2 * 1024 * 1024;
else
mmio_size = 512 * 1024;
mmio_type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, mmio_bar);
if (pci_mapreg_map(pa, mmio_bar, mmio_type, BUS_SPACE_MAP_LINEAR,

View file

@ -35,6 +35,7 @@
#include "acpi.h"
#if NACPI > 0
#define CONFIG_ACPI 1
#define CONFIG_ACPI_SLEEP 1
#endif
#endif

View file

@ -86,4 +86,6 @@ struct notifier_block;
int register_acpi_notifier(struct notifier_block *);
int unregister_acpi_notifier(struct notifier_block *);
int acpi_target_system_state(void);
#endif