sync with OpenBSD -current
This commit is contained in:
parent
8e82432ef8
commit
9adc065819
GPG key ID:
F42C07F07E2E35B7
23 changed files with 345 additions and 193 deletions
|
|
@ -1,4 +1,4 @@
|
|||
/* $OpenBSD: cpu.c,v 1.108 2024/03/05 18:42:20 kettenis Exp $ */
|
||||
/* $OpenBSD: cpu.c,v 1.110 2024/03/16 09:15:04 jsg Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2016 Dale Rahn <drahn@dalerahn.com>
|
||||
|
|
@ -52,6 +52,7 @@
|
|||
#define CPU_IMPL_AMCC 0x50
|
||||
#define CPU_IMPL_QCOM 0x51
|
||||
#define CPU_IMPL_APPLE 0x61
|
||||
#define CPU_IMPL_AMPERE 0xc0
|
||||
|
||||
/* ARM */
|
||||
#define CPU_PART_CORTEX_A34 0xd02
|
||||
|
|
@ -86,6 +87,8 @@
|
|||
#define CPU_PART_CORTEX_A720 0xd81
|
||||
#define CPU_PART_CORTEX_X4 0xd82
|
||||
#define CPU_PART_NEOVERSE_V3 0xd84
|
||||
#define CPU_PART_CORTEX_A520AE 0xd88
|
||||
#define CPU_PART_CORTEX_A720AE 0xd89
|
||||
#define CPU_PART_NEOVERSE_N3 0xd8e
|
||||
|
||||
/* Cavium */
|
||||
|
|
@ -115,6 +118,9 @@
|
|||
#define CPU_PART_BLIZZARD_MAX 0x038
|
||||
#define CPU_PART_AVALANCHE_MAX 0x039
|
||||
|
||||
/* Ampere */
|
||||
#define CPU_PART_AMPERE1 0xac3
|
||||
|
||||
#define CPU_IMPL(midr) (((midr) >> 24) & 0xff)
|
||||
#define CPU_PART(midr) (((midr) >> 4) & 0xfff)
|
||||
#define CPU_VAR(midr) (((midr) >> 20) & 0xf)
|
||||
|
|
@ -148,9 +154,11 @@ struct cpu_cores cpu_cores_arm[] = {
|
|||
{ CPU_PART_CORTEX_A78C, "Cortex-A78C" },
|
||||
{ CPU_PART_CORTEX_A510, "Cortex-A510" },
|
||||
{ CPU_PART_CORTEX_A520, "Cortex-A520" },
|
||||
{ CPU_PART_CORTEX_A520AE, "Cortex-A520AE" },
|
||||
{ CPU_PART_CORTEX_A710, "Cortex-A710" },
|
||||
{ CPU_PART_CORTEX_A715, "Cortex-A715" },
|
||||
{ CPU_PART_CORTEX_A720, "Cortex-A720" },
|
||||
{ CPU_PART_CORTEX_A720AE, "Cortex-A720AE" },
|
||||
{ CPU_PART_CORTEX_X1, "Cortex-X1" },
|
||||
{ CPU_PART_CORTEX_X1C, "Cortex-X1C" },
|
||||
{ CPU_PART_CORTEX_X2, "Cortex-X2" },
|
||||
|
|
@ -201,6 +209,11 @@ struct cpu_cores cpu_cores_apple[] = {
|
|||
{ 0, NULL },
|
||||
};
|
||||
|
||||
struct cpu_cores cpu_cores_ampere[] = {
|
||||
{ CPU_PART_AMPERE1, "AmpereOne" },
|
||||
{ 0, NULL },
|
||||
};
|
||||
|
||||
/* arm cores makers */
|
||||
const struct implementers {
|
||||
int id;
|
||||
|
|
@ -212,6 +225,7 @@ const struct implementers {
|
|||
{ CPU_IMPL_AMCC, "Applied Micro", cpu_cores_amcc },
|
||||
{ CPU_IMPL_QCOM, "Qualcomm", cpu_cores_qcom },
|
||||
{ CPU_IMPL_APPLE, "Apple", cpu_cores_apple },
|
||||
{ CPU_IMPL_AMPERE, "Ampere", cpu_cores_ampere },
|
||||
{ 0, NULL },
|
||||
};
|
||||
|
||||
|
|
@ -230,6 +244,7 @@ int arm64_has_aes;
|
|||
|
||||
extern char trampoline_vectors_none[];
|
||||
extern char trampoline_vectors_loop_8[];
|
||||
extern char trampoline_vectors_loop_11[];
|
||||
extern char trampoline_vectors_loop_24[];
|
||||
extern char trampoline_vectors_loop_32[];
|
||||
#if NPSCI > 0
|
||||
|
|
@ -419,8 +434,10 @@ cpu_identify(struct cpu_info *ci)
|
|||
* But we might still be vulnerable to Spectre-BHB. If we know the
|
||||
* CPU, we can add a branchy loop that cleans the BHB.
|
||||
*/
|
||||
if (impl == CPU_IMPL_ARM) {
|
||||
switch (impl) {
|
||||
case CPU_IMPL_ARM:
|
||||
switch (part) {
|
||||
case CPU_PART_CORTEX_A57:
|
||||
case CPU_PART_CORTEX_A72:
|
||||
ci->ci_trampoline_vectors =
|
||||
(vaddr_t)trampoline_vectors_loop_8;
|
||||
|
|
@ -444,6 +461,15 @@ cpu_identify(struct cpu_info *ci)
|
|||
(vaddr_t)trampoline_vectors_loop_32;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case CPU_IMPL_AMPERE:
|
||||
switch (part) {
|
||||
case CPU_PART_AMPERE1:
|
||||
ci->ci_trampoline_vectors =
|
||||
(vaddr_t)trampoline_vectors_loop_11;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $OpenBSD: locore.S,v 1.45 2023/12/12 07:37:20 deraadt Exp $ */
|
||||
/* $OpenBSD: locore.S,v 1.46 2024/03/16 20:46:28 kettenis Exp $ */
|
||||
/*-
|
||||
* Copyright (c) 2012-2014 Andrew Turner
|
||||
* All rights reserved.
|
||||
|
|
@ -57,6 +57,7 @@ drop_to_el1:
|
|||
|
||||
/* Configure the Hypervisor */
|
||||
mov x2, #(HCR_RW)
|
||||
orr x2, x2, #(HCR_API | HCR_APK)
|
||||
msr hcr_el2, x2
|
||||
|
||||
/* Load the Virtualization Process ID Register */
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $OpenBSD: trampoline.S,v 1.4 2022/12/10 10:13:58 patrick Exp $ */
|
||||
/* $OpenBSD: trampoline.S,v 1.5 2024/03/15 13:26:09 kettenis Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2018 Mark Kettenis <kettenis@openbsd.org>
|
||||
|
|
@ -45,6 +45,12 @@
|
|||
.macro spectre_bhb_loop_8_late
|
||||
.endm
|
||||
|
||||
.macro spectre_bhb_loop_11_early
|
||||
spectre_bhb_loop 11
|
||||
.endm
|
||||
.macro spectre_bhb_loop_11_late
|
||||
.endm
|
||||
|
||||
.macro spectre_bhb_loop_24_early
|
||||
spectre_bhb_loop 24
|
||||
.endm
|
||||
|
|
@ -92,7 +98,7 @@
|
|||
#endif
|
||||
|
||||
.macro spectre_bhb_clrbhb_early
|
||||
hint #22 /* clrbhb */
|
||||
clrbhb
|
||||
isb
|
||||
.endm
|
||||
.macro spectre_bhb_clrbhb_late
|
||||
|
|
@ -147,6 +153,7 @@ trampoline_vectors_\bhb:
|
|||
trampoline_vectors:
|
||||
tramp_vector none
|
||||
tramp_vector loop_8
|
||||
tramp_vector loop_11
|
||||
tramp_vector loop_24
|
||||
tramp_vector loop_32
|
||||
#if NPSCI > 0
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $OpenBSD: hypervisor.h,v 1.3 2021/02/21 13:14:47 kettenis Exp $ */
|
||||
/* $OpenBSD: hypervisor.h,v 1.4 2024/03/16 20:46:28 kettenis Exp $ */
|
||||
/*-
|
||||
* Copyright (c) 2013, 2014 Andrew Turner
|
||||
* All rights reserved.
|
||||
|
|
@ -82,6 +82,8 @@
|
|||
#define HCR_CD 0x0000000100000000
|
||||
#define HCR_ID 0x0000000200000000
|
||||
#define HCR_E2H 0x0000000400000000
|
||||
#define HCR_APK 0x0000010000000000
|
||||
#define HCR_API 0x0000020000000000
|
||||
|
||||
#endif
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue