sync with OpenBSD -current
This commit is contained in:
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25f7188861
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GPG key ID:
F42C07F07E2E35B7
2137 changed files with 177389 additions and 104447 deletions
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@ -1,4 +1,4 @@
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/* $OpenBSD: ehci_fdt.c,v 1.10 2023/04/03 01:57:41 dlg Exp $ */
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/* $OpenBSD: ehci_fdt.c,v 1.11 2024/01/26 17:11:50 kettenis Exp $ */
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/*
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* Copyright (c) 2005 David Gwynne <dlg@openbsd.org>
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@ -205,6 +205,7 @@ struct ehci_phy ehci_phys[] = {
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{ "allwinner,sun8i-h3-usb-phy", sun4i_phy_init },
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{ "allwinner,sun8i-r40-usb-phy", sun4i_phy_init },
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{ "allwinner,sun8i-v3s-usb-phy", sun4i_phy_init },
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{ "allwinner,sun20i-d1-usb-phy", sun4i_phy_init },
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{ "allwinner,sun50i-h6-usb-phy", sun4i_phy_init },
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{ "allwinner,sun50i-a64-usb-phy", sun4i_phy_init },
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{ "allwinner,sun9i-a80-usb-phy", sun9i_phy_init },
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@ -305,7 +306,7 @@ sun4i_phy_init(struct ehci_fdt_softc *sc, uint32_t *cells)
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/*
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* We need to poke an undocumented register to make the PHY
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* work on Allwinner A64/H3/H5/R40.
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* work on Allwinner A64/D1/H3/H5/R40.
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*/
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if (OF_is_compatible(node, "allwinner,sun8i-h3-usb-phy") ||
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OF_is_compatible(node, "allwinner,sun8i-r40-usb-phy") ||
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@ -314,6 +315,10 @@ sun4i_phy_init(struct ehci_fdt_softc *sc, uint32_t *cells)
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val = bus_space_read_4(sc->sc.iot, sc->sc.ioh, 0x810);
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val &= ~(1 << 1);
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bus_space_write_4(sc->sc.iot, sc->sc.ioh, 0x810, val);
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} else if (OF_is_compatible(node, "allwinner,sun20i-d1-usb-phy")) {
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val = bus_space_read_4(sc->sc.iot, sc->sc.ioh, 0x810);
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val &= ~(1 << 3);
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bus_space_write_4(sc->sc.iot, sc->sc.ioh, 0x810, val);
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}
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pinctrl_byname(node, "default");
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@ -1,4 +1,4 @@
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/* $OpenBSD: sxiccmu.c,v 1.32 2023/08/15 08:27:30 miod Exp $ */
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/* $OpenBSD: sxiccmu.c,v 1.33 2024/01/26 17:50:00 kettenis Exp $ */
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/*
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* Copyright (c) 2007,2009 Dale Rahn <drahn@openbsd.org>
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* Copyright (c) 2013 Artturi Alm
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@ -98,6 +98,8 @@ uint32_t sxiccmu_a64_get_frequency(struct sxiccmu_softc *, uint32_t);
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int sxiccmu_a64_set_frequency(struct sxiccmu_softc *, uint32_t, uint32_t);
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uint32_t sxiccmu_a80_get_frequency(struct sxiccmu_softc *, uint32_t);
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int sxiccmu_a80_set_frequency(struct sxiccmu_softc *, uint32_t, uint32_t);
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uint32_t sxiccmu_d1_get_frequency(struct sxiccmu_softc *, uint32_t);
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int sxiccmu_d1_set_frequency(struct sxiccmu_softc *, uint32_t, uint32_t);
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uint32_t sxiccmu_h3_get_frequency(struct sxiccmu_softc *, uint32_t);
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int sxiccmu_h3_set_frequency(struct sxiccmu_softc *, uint32_t, uint32_t);
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uint32_t sxiccmu_h3_r_get_frequency(struct sxiccmu_softc *, uint32_t);
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@ -145,6 +147,7 @@ sxiccmu_match(struct device *parent, void *match, void *aux)
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OF_is_compatible(node, "allwinner,sun9i-a80-ccu") ||
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OF_is_compatible(node, "allwinner,sun9i-a80-usb-clks") ||
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OF_is_compatible(node, "allwinner,sun9i-a80-mmc-config-clk") ||
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OF_is_compatible(node, "allwinner,sun20i-d1-ccu") ||
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OF_is_compatible(node, "allwinner,sun50i-a64-ccu") ||
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OF_is_compatible(node, "allwinner,sun50i-a64-r-ccu") ||
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OF_is_compatible(node, "allwinner,sun50i-h5-ccu") ||
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@ -252,6 +255,14 @@ sxiccmu_attach(struct device *parent, struct device *self, void *aux)
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sc->sc_nresets = nitems(sun9i_a80_mmc_resets);
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sc->sc_get_frequency = sxiccmu_nop_get_frequency;
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sc->sc_set_frequency = sxiccmu_nop_set_frequency;
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} else if (OF_is_compatible(node, "allwinner,sun20i-d1-ccu")) {
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KASSERT(faa->fa_nreg > 0);
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sc->sc_gates = sun20i_d1_gates;
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sc->sc_ngates = nitems(sun20i_d1_gates);
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sc->sc_resets = sun20i_d1_resets;
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sc->sc_nresets = nitems(sun20i_d1_resets);
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sc->sc_get_frequency = sxiccmu_d1_get_frequency;
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sc->sc_set_frequency = sxiccmu_d1_set_frequency;
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} else if (OF_is_compatible(node, "allwinner,sun50i-a64-ccu")) {
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KASSERT(faa->fa_nreg > 0);
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sc->sc_gates = sun50i_a64_gates;
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@ -1156,6 +1167,21 @@ sxiccmu_a80_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)
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return 0;
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}
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/* Allwinner D1 */
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uint32_t
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sxiccmu_d1_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)
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{
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switch (idx) {
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case D1_CLK_APB1:
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/* XXX Controlled by a MUX. */
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return 24000000;
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}
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printf("%s: 0x%08x\n", __func__, idx);
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return 0;
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}
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/* Allwinner H3/H5 */
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#define H3_PLL_CPUX_CTRL_REG 0x0000
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#define H3_PLL_CPUX_ENABLE (1U << 31)
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@ -1645,6 +1671,13 @@ sxiccmu_a80_set_frequency(struct sxiccmu_softc *sc, uint32_t idx, uint32_t freq)
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return -1;
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}
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int
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sxiccmu_d1_set_frequency(struct sxiccmu_softc *sc, uint32_t idx, uint32_t freq)
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{
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printf("%s: 0x%08x\n", __func__, idx);
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return -1;
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}
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int
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sxiccmu_h3_set_frequency(struct sxiccmu_softc *sc, uint32_t idx, uint32_t freq)
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{
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@ -302,6 +302,37 @@ const struct sxiccmu_ccu_bit sun9i_a80_mmc_gates[] = {
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{ 0x000c, 16 },
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};
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/* D1 */
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#define D1_CLK_APB1 25
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#define D1_CLK_BUS_UART0 62
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#define D1_CLK_BUS_UART1 63
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#define D1_CLK_BUS_UART2 64
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#define D1_CLK_BUS_UART3 65
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#define D1_CLK_BUS_UART4 66
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#define D1_CLK_BUS_UART5 67
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#define D1_CLK_USB_OHCI0 97
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#define D1_CLK_USB_OHCI1 98
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#define D1_CLK_BUS_OHCI0 99
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#define D1_CLK_BUS_OHCI1 100
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#define D1_CLK_BUS_EHCI0 101
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#define D1_CLK_BUS_EHCI1 102
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const struct sxiccmu_ccu_bit sun20i_d1_gates[] = {
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[D1_CLK_BUS_UART0] = { 0x090c, 0, D1_CLK_APB1 },
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[D1_CLK_BUS_UART1] = { 0x090c, 1, D1_CLK_APB1 },
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[D1_CLK_BUS_UART2] = { 0x090c, 2, D1_CLK_APB1 },
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[D1_CLK_BUS_UART3] = { 0x090c, 3, D1_CLK_APB1 },
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[D1_CLK_BUS_UART4] = { 0x090c, 4, D1_CLK_APB1 },
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[D1_CLK_BUS_UART5] = { 0x090c, 5, D1_CLK_APB1 },
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[D1_CLK_USB_OHCI0] = { 0x0a70, 31 },
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[D1_CLK_USB_OHCI1] = { 0x0a74, 31 },
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[D1_CLK_BUS_OHCI0] = { 0x0a8c, 0 },
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[D1_CLK_BUS_OHCI1] = { 0x0a8c, 1 },
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[D1_CLK_BUS_EHCI0] = { 0x0a8c, 4 },
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[D1_CLK_BUS_EHCI1] = { 0x0a8c, 5 },
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};
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/* H3/H5 */
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#define H3_CLK_PLL_CPUX 0
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{ 0x000c, 18 },
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};
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/* D1 */
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#define D1_RST_BUS_UART0 18
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#define D1_RST_BUS_UART1 19
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#define D1_RST_BUS_UART2 20
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#define D1_RST_BUS_UART3 21
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#define D1_RST_BUS_UART4 22
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#define D1_RST_BUS_UART5 23
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#define D1_RST_USB_PHY0 40
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#define D1_RST_USB_PHY1 41
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#define D1_RST_BUS_OHCI0 42
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#define D1_RST_BUS_OHCI1 43
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#define D1_RST_BUS_EHCI0 44
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#define D1_RST_BUS_EHCI1 45
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const struct sxiccmu_ccu_bit sun20i_d1_resets[] = {
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[D1_RST_BUS_UART0] = { 0x090c, 16 },
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[D1_RST_BUS_UART1] = { 0x090c, 17 },
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[D1_RST_BUS_UART2] = { 0x090c, 18 },
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[D1_RST_BUS_UART3] = { 0x090c, 19 },
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[D1_RST_BUS_UART4] = { 0x090c, 20 },
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[D1_RST_BUS_UART5] = { 0x090c, 21 },
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[D1_RST_USB_PHY0] = { 0x0a70, 30 },
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[D1_RST_USB_PHY1] = { 0x0a74, 30 },
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[D1_RST_BUS_OHCI0] = { 0x0a8c, 16 },
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[D1_RST_BUS_OHCI1] = { 0x0a8c, 17 },
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[D1_RST_BUS_EHCI0] = { 0x0a8c, 20 },
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[D1_RST_BUS_EHCI1] = { 0x0a8c, 21 },
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};
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/* H3/H5 */
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#define H3_RST_USB_PHY0 0
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@ -1,4 +1,4 @@
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/* $OpenBSD: sxidog.c,v 1.3 2021/10/24 17:52:27 mpi Exp $ */
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/* $OpenBSD: sxidog.c,v 1.4 2024/01/26 17:03:45 kettenis Exp $ */
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/*
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* Copyright (c) 2007,2009 Dale Rahn <drahn@openbsd.org>
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*
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@ -55,6 +55,7 @@ struct sxidog_softc {
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int sc_type;
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#define SXIDOG_A10 0
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#define SXIDOG_A31 1
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uint32_t sc_key;
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};
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struct sxidog_softc *sxidog_sc = NULL; /* for sxidog_reset() */
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@ -80,7 +81,8 @@ sxidog_match(struct device *parent, void *match, void *aux)
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struct fdt_attach_args *faa = aux;
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return (OF_is_compatible(faa->fa_node, "allwinner,sun4i-a10-wdt") ||
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OF_is_compatible(faa->fa_node, "allwinner,sun6i-a31-wdt"));
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OF_is_compatible(faa->fa_node, "allwinner,sun6i-a31-wdt") ||
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OF_is_compatible(faa->fa_node, "allwinner,sun20i-d1-wdt"));
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}
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void
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faa->fa_reg[0].size, 0, &sc->sc_ioh))
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panic("sxidog_attach: bus_space_map failed!");
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if (OF_is_compatible(faa->fa_node, "allwinner,sun6i-a31-wdt")) {
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SXIWRITE4(sc, WDOG0_CFG_REG, WDOG0_RST_EN);
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if (OF_is_compatible(faa->fa_node, "allwinner,sun20i-d1-wdt"))
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sc->sc_key = 0x16aa0000;
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if (OF_is_compatible(faa->fa_node, "allwinner,sun6i-a31-wdt") ||
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OF_is_compatible(faa->fa_node, "allwinner,sun20i-d1-wdt")) {
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SXIWRITE4(sc, WDOG0_MODE_REG, sc->sc_key);
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SXIWRITE4(sc, WDOG0_CFG_REG, WDOG0_RST_EN | sc->sc_key);
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sc->sc_type = SXIDOG_A31;
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} else
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} else {
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SXIWRITE4(sc, WDOG_MODE_REG, 0);
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sc->sc_type = SXIDOG_A10;
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}
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sxidog_sc = sc;
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cpuresetfn = sxidog_reset;
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@ -152,7 +161,7 @@ sxidog_callback(void *arg, int period)
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case SXIDOG_A31:
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enable = (period > 0) ? WDOG0_EN : 0;
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SXIWRITE4(sc, WDOG0_MODE_REG,
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enable | WDOG0_INTV_VALUE(period));
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enable | WDOG0_INTV_VALUE(period) | sc->sc_key);
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SXIWRITE4(sc, WDOG0_CTRL_REG, WDOG0_KEY | WDOG0_RSTART);
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break;
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}
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@ -1085,9 +1085,6 @@ out:
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static int amdgpu_acpi_enumerate_xcc(void)
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{
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STUB();
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return -ENOSYS;
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#ifdef notyet
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struct amdgpu_acpi_dev_info *dev_info = NULL;
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struct amdgpu_acpi_xcc_info *xcc_info;
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struct acpi_device *acpi_dev;
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@ -1098,6 +1095,7 @@ static int amdgpu_acpi_enumerate_xcc(void)
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INIT_LIST_HEAD(&amdgpu_acpi_dev_list);
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xa_init(&numa_info_xa);
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#ifdef notyet
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for (id = 0; id < AMD_XCC_MAX_HID; id++) {
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snprintf(hid, sizeof(hid), "%s%d", "AMD", AMD_XCC_HID_START + id);
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acpi_dev = acpi_dev_get_first_match_dev(hid, NULL, -1);
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@ -1142,9 +1140,9 @@ static int amdgpu_acpi_enumerate_xcc(void)
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list_add_tail(&xcc_info->list, &dev_info->xcc_list);
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}
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#endif
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return 0;
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#endif
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}
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int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset,
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@ -51,4 +51,6 @@ struct pci_device_id {
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unsigned long driver_data;
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};
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#define ACPI_ID_LEN 16
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#endif
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@ -176,4 +176,10 @@ xa_empty(const struct xarray *xa)
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return SPLAY_EMPTY(&xa->xa_tree);
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}
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static inline void
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xa_init(struct xarray *xa)
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{
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xa_init_flags(xa, 0);
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}
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#endif
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