sync with OpenBSD -current
This commit is contained in:
parent
1b6040b16e
commit
8b26203154
GPG key ID:
F42C07F07E2E35B7
38 changed files with 1417 additions and 324 deletions
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@ -1,4 +1,4 @@
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/* $OpenBSD: if_qwx_pci.c,v 1.10 2024/02/16 16:37:42 stsp Exp $ */
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/* $OpenBSD: if_qwx_pci.c,v 1.14 2024/02/22 09:15:34 stsp Exp $ */
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/*
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* Copyright 2023 Stefan Sperling <stsp@openbsd.org>
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@ -323,16 +323,6 @@ struct qwx_pci_cmd_ring {
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struct qwx_pci_ops;
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struct qwx_msi_config;
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struct qwx_mhi_newstate {
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struct {
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int mhi_state;
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int ee;
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} queue[4];
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int cur;
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int tail;
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int queued;
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};
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#define QWX_NUM_MSI_VEC 32
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struct qwx_pci_softc {
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@ -366,12 +356,8 @@ struct qwx_pci_softc {
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uint64_t wake_db;
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struct qwx_mhi_newstate mhi_newstate;
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struct task mhi_newstate_task;
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struct taskq *mhi_taskq;
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/*
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* DMA memory for AMMS.bin firmware image.
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* DMA memory for AMSS.bin firmware image.
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* This memory must remain available to the device until
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* the device is powered down.
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*/
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@ -402,7 +388,6 @@ int qwx_pci_match(struct device *, void *, void *);
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void qwx_pci_attach(struct device *, struct device *, void *);
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int qwx_pci_detach(struct device *, int);
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void qwx_pci_attach_hook(struct device *);
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int qwx_pci_activate(struct device *, int);
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void qwx_pci_free_xfer_rings(struct qwx_pci_softc *);
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int qwx_pci_alloc_xfer_ring(struct qwx_softc *, struct qwx_pci_xfer_ring *,
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uint32_t, uint32_t, uint32_t, size_t);
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@ -463,7 +448,6 @@ int qwx_mhi_fw_load_handler(struct qwx_pci_softc *);
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int qwx_mhi_await_device_reset(struct qwx_softc *);
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int qwx_mhi_await_device_ready(struct qwx_softc *);
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void qwx_mhi_ready_state_transition(struct qwx_pci_softc *);
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void qwx_mhi_ee_amss_state_transition(struct qwx_pci_softc *);
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void qwx_mhi_mission_mode_state_transition(struct qwx_pci_softc *);
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void qwx_mhi_low_power_mode_state_transition(struct qwx_pci_softc *);
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void qwx_mhi_set_state(struct qwx_softc *, uint32_t);
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@ -473,8 +457,6 @@ int qwx_mhi_fw_load_bhie(struct qwx_pci_softc *, uint8_t *, size_t);
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void qwx_rddm_prepare(struct qwx_pci_softc *);
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void qwx_rddm_task(void *);
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void * qwx_pci_event_ring_get_elem(struct qwx_pci_event_ring *, uint64_t);
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void qwx_mhi_queue_state_change(struct qwx_pci_softc *, int, int);
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void qwx_mhi_state_change(void *);
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void qwx_pci_intr_ctrl_event_mhi(struct qwx_pci_softc *, uint32_t);
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void qwx_pci_intr_ctrl_event_ee(struct qwx_pci_softc *, uint32_t);
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void qwx_pci_intr_ctrl_event_cmd_complete(struct qwx_pci_softc *,
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@ -526,7 +508,7 @@ const struct cfattach qwx_pci_ca = {
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qwx_pci_match,
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qwx_pci_attach,
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qwx_pci_detach,
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qwx_pci_activate
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qwx_activate
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};
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/* XXX pcidev */
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@ -1037,10 +1019,6 @@ unsupported_wcn6855_soc:
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if (sc->sc_nswq == NULL)
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goto err_ce_free;
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psc->mhi_taskq = taskq_create("qwxmhi", 1, IPL_NET, 0);
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if (psc->mhi_taskq == NULL)
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goto err_ce_free;
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qwx_pci_init_qmi_ce_config(sc);
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error = qwx_pcic_config_irq(sc, pa);
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@ -1067,7 +1045,6 @@ unsupported_wcn6855_soc:
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goto err_irq_affinity_cleanup;
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}
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#endif
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task_set(&psc->mhi_newstate_task, qwx_mhi_state_change, psc);
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task_set(&psc->rddm_task, qwx_rddm_task, psc);
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ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
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@ -1204,19 +1181,6 @@ qwx_pci_attach_hook(struct device *self)
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splx(s);
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}
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int
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qwx_pci_activate(struct device *self, int act)
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{
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switch (act) {
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case DVACT_SUSPEND:
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break;
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case DVACT_WAKEUP:
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break;
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}
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return 0;
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}
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void
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qwx_pci_free_xfer_rings(struct qwx_pci_softc *psc)
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{
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@ -2203,12 +2167,8 @@ int
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qwx_pci_power_up(struct qwx_softc *sc)
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{
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struct qwx_pci_softc *psc = (struct qwx_pci_softc *)sc;
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struct qwx_mhi_newstate *ns = &psc->mhi_newstate;
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int error;
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task_del(psc->mhi_taskq, &psc->mhi_newstate_task);
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memset(ns, 0, sizeof(*ns));
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psc->register_window = 0;
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clear_bit(ATH11K_FLAG_DEVICE_INIT_DONE, sc->sc_flags);
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@ -2234,12 +2194,6 @@ qwx_pci_power_up(struct qwx_softc *sc)
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void
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qwx_pci_power_down(struct qwx_softc *sc)
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{
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struct qwx_pci_softc *psc = (struct qwx_pci_softc *)sc;
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struct qwx_mhi_newstate *ns = &psc->mhi_newstate;
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task_del(psc->mhi_taskq, &psc->mhi_newstate_task);
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memset(ns, 0, sizeof(*ns));
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/* restore aspm in case firmware bootup fails */
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qwx_pci_aspm_restore(sc);
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@ -2951,6 +2905,10 @@ qwx_mhi_start(struct qwx_pci_softc *psc)
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ret = qwx_mhi_fw_load_handler(psc);
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if (ret)
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return ret;
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/* XXX without this delay starting the channels may fail */
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delay(1000);
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qwx_mhi_start_channels(psc);
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} else {
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/* XXX Handle partially initialized device...?!? */
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ee = qwx_pci_read(sc, psc->bhi_off + MHI_BHI_EXECENV);
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@ -3046,23 +3004,31 @@ qwx_mhi_fw_load_handler(struct qwx_pci_softc *psc)
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u_char *data;
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size_t len;
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ret = snprintf(amss_path, sizeof(amss_path), "%s-%s-%s",
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ATH11K_FW_DIR, sc->hw_params.fw.dir, ATH11K_AMSS_FILE);
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if (ret < 0 || ret >= sizeof(amss_path))
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return ENOSPC;
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if (sc->fw_img[QWX_FW_AMSS].data) {
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data = sc->fw_img[QWX_FW_AMSS].data;
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len = sc->fw_img[QWX_FW_AMSS].size;
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} else {
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ret = snprintf(amss_path, sizeof(amss_path), "%s-%s-%s",
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ATH11K_FW_DIR, sc->hw_params.fw.dir, ATH11K_AMSS_FILE);
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if (ret < 0 || ret >= sizeof(amss_path))
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return ENOSPC;
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ret = loadfirmware(amss_path, &data, &len);
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if (ret) {
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printf("%s: could not read %s (error %d)\n",
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sc->sc_dev.dv_xname, amss_path, ret);
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return ret;
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}
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ret = loadfirmware(amss_path, &data, &len);
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if (ret) {
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printf("%s: could not read %s (error %d)\n",
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sc->sc_dev.dv_xname, amss_path, ret);
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return ret;
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}
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if (len < MHI_DMA_VEC_CHUNK_SIZE) {
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printf("%s: %s is too short, have only %zu bytes\n",
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sc->sc_dev.dv_xname, amss_path, len);
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free(data, M_DEVBUF, len);
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return EINVAL;
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if (len < MHI_DMA_VEC_CHUNK_SIZE) {
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printf("%s: %s is too short, have only %zu bytes\n",
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sc->sc_dev.dv_xname, amss_path, len);
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free(data, M_DEVBUF, len);
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return EINVAL;
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}
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sc->fw_img[QWX_FW_AMSS].data = data;
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sc->fw_img[QWX_FW_AMSS].size = len;
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}
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/* Second-stage boot loader sits in the first 512 KB of image. */
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@ -3070,7 +3036,6 @@ qwx_mhi_fw_load_handler(struct qwx_pci_softc *psc)
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if (ret != 0) {
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printf("%s: could not load firmware %s\n",
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sc->sc_dev.dv_xname, amss_path);
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free(data, M_DEVBUF, len);
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return ret;
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}
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@ -3079,6 +3044,7 @@ qwx_mhi_fw_load_handler(struct qwx_pci_softc *psc)
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if (ret != 0) {
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printf("%s: could not load firmware %s\n",
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sc->sc_dev.dv_xname, amss_path);
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return ret;
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}
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while (psc->bhi_ee < MHI_EE_AMSS) {
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@ -3090,11 +3056,8 @@ qwx_mhi_fw_load_handler(struct qwx_pci_softc *psc)
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if (ret != 0) {
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printf("%s: device failed to enter AMSS EE\n",
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sc->sc_dev.dv_xname);
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free(data, M_DEVBUF, len);
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return ret;
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}
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free(data, M_DEVBUF, len);
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return ret;
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}
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@ -3182,15 +3145,6 @@ qwx_mhi_ready_state_transition(struct qwx_pci_softc *psc)
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qwx_mhi_set_state(sc, MHI_STATE_M0);
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}
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void
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qwx_mhi_ee_amss_state_transition(struct qwx_pci_softc *psc)
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{
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/* XXX without this delay starting the channels may fail */
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delay(1000);
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qwx_mhi_start_channels(psc);
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}
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void
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qwx_mhi_mission_mode_state_transition(struct qwx_pci_softc *psc)
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{
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@ -3627,120 +3581,87 @@ qwx_pci_event_ring_get_elem(struct qwx_pci_event_ring *ring, uint64_t rp)
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}
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void
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qwx_mhi_state_change(void *arg)
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qwx_mhi_state_change(struct qwx_pci_softc *psc, int ee, int mhi_state)
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{
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struct qwx_pci_softc *psc = arg;
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struct qwx_softc *sc = &psc->sc_sc;
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struct qwx_mhi_newstate *ns = &psc->mhi_newstate;
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int s = splnet();
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uint32_t old_ee = psc->bhi_ee;
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uint32_t old_mhi_state = psc->mhi_state;
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while (ns->tail != ns->cur) {
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int mhi_state = ns->queue[ns->tail].mhi_state;
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int ee = ns->queue[ns->tail].ee;
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uint32_t old_ee = psc->bhi_ee;
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uint32_t old_mhi_state = psc->mhi_state;
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KASSERT(ns->queued > 0);
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if (ee != -1 && psc->bhi_ee != ee) {
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switch (ee) {
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case MHI_EE_PBL:
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DNPRINTF(QWX_D_MHI, "%s: new EE PBL\n",
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sc->sc_dev.dv_xname);
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psc->bhi_ee = ee;
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break;
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case MHI_EE_SBL:
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psc->bhi_ee = ee;
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DNPRINTF(QWX_D_MHI, "%s: new EE SBL\n",
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sc->sc_dev.dv_xname);
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break;
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case MHI_EE_AMSS:
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DNPRINTF(QWX_D_MHI, "%s: new EE AMSS\n",
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sc->sc_dev.dv_xname);
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psc->bhi_ee = ee;
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qwx_mhi_ee_amss_state_transition(psc);
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/* Wake thread loading the full AMSS image. */
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wakeup(&psc->bhie_off);
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break;
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case MHI_EE_WFW:
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DNPRINTF(QWX_D_MHI, "%s: new EE WFW\n",
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sc->sc_dev.dv_xname);
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psc->bhi_ee = ee;
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break;
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default:
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printf("%s: unhandled EE change to %x\n",
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sc->sc_dev.dv_xname, ee);
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break;
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}
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if (ee != -1 && psc->bhi_ee != ee) {
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switch (ee) {
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case MHI_EE_PBL:
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DNPRINTF(QWX_D_MHI, "%s: new EE PBL\n",
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sc->sc_dev.dv_xname);
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psc->bhi_ee = ee;
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break;
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case MHI_EE_SBL:
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psc->bhi_ee = ee;
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DNPRINTF(QWX_D_MHI, "%s: new EE SBL\n",
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sc->sc_dev.dv_xname);
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break;
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case MHI_EE_AMSS:
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DNPRINTF(QWX_D_MHI, "%s: new EE AMSS\n",
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sc->sc_dev.dv_xname);
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psc->bhi_ee = ee;
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/* Wake thread loading the full AMSS image. */
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wakeup(&psc->bhie_off);
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break;
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case MHI_EE_WFW:
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DNPRINTF(QWX_D_MHI, "%s: new EE WFW\n",
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sc->sc_dev.dv_xname);
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psc->bhi_ee = ee;
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break;
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default:
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printf("%s: unhandled EE change to %x\n",
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sc->sc_dev.dv_xname, ee);
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break;
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}
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if (mhi_state != -1 && psc->mhi_state != mhi_state) {
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switch (mhi_state) {
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case -1:
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break;
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case MHI_STATE_RESET:
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DNPRINTF(QWX_D_MHI, "%s: new MHI state RESET\n",
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sc->sc_dev.dv_xname);
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psc->mhi_state = mhi_state;
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break;
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case MHI_STATE_READY:
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DNPRINTF(QWX_D_MHI, "%s: new MHI state READY\n",
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sc->sc_dev.dv_xname);
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psc->mhi_state = mhi_state;
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qwx_mhi_ready_state_transition(psc);
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break;
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case MHI_STATE_M0:
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DNPRINTF(QWX_D_MHI, "%s: new MHI state M0\n",
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sc->sc_dev.dv_xname);
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psc->mhi_state = mhi_state;
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qwx_mhi_mission_mode_state_transition(psc);
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break;
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case MHI_STATE_M1:
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DNPRINTF(QWX_D_MHI, "%s: new MHI state M1\n",
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sc->sc_dev.dv_xname);
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psc->mhi_state = mhi_state;
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qwx_mhi_low_power_mode_state_transition(psc);
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break;
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case MHI_STATE_SYS_ERR:
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DNPRINTF(QWX_D_MHI,
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"%s: new MHI state SYS ERR\n",
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sc->sc_dev.dv_xname);
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psc->mhi_state = mhi_state;
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break;
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default:
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printf("%s: unhandled MHI state change to %x\n",
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sc->sc_dev.dv_xname, mhi_state);
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break;
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}
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}
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if (old_ee != psc->bhi_ee)
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wakeup(&psc->bhi_ee);
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if (old_mhi_state != psc->mhi_state)
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wakeup(&psc->mhi_state);
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ns->tail = (ns->tail + 1) % nitems(ns->queue);
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ns->queued--;
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}
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splx(s);
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}
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void
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qwx_mhi_queue_state_change(struct qwx_pci_softc *psc, int ee, int mhi_state)
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{
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struct qwx_mhi_newstate *ns = &psc->mhi_newstate;
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if (ns->queued >= nitems(ns->queue)) {
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printf("%s: event queue full, dropping event\n", __func__);
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return;
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if (mhi_state != -1 && psc->mhi_state != mhi_state) {
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switch (mhi_state) {
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case -1:
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break;
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case MHI_STATE_RESET:
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DNPRINTF(QWX_D_MHI, "%s: new MHI state RESET\n",
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sc->sc_dev.dv_xname);
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psc->mhi_state = mhi_state;
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break;
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case MHI_STATE_READY:
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DNPRINTF(QWX_D_MHI, "%s: new MHI state READY\n",
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sc->sc_dev.dv_xname);
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psc->mhi_state = mhi_state;
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qwx_mhi_ready_state_transition(psc);
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break;
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case MHI_STATE_M0:
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DNPRINTF(QWX_D_MHI, "%s: new MHI state M0\n",
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sc->sc_dev.dv_xname);
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psc->mhi_state = mhi_state;
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qwx_mhi_mission_mode_state_transition(psc);
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break;
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case MHI_STATE_M1:
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DNPRINTF(QWX_D_MHI, "%s: new MHI state M1\n",
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||||
sc->sc_dev.dv_xname);
|
||||
psc->mhi_state = mhi_state;
|
||||
qwx_mhi_low_power_mode_state_transition(psc);
|
||||
break;
|
||||
case MHI_STATE_SYS_ERR:
|
||||
DNPRINTF(QWX_D_MHI,
|
||||
"%s: new MHI state SYS ERR\n",
|
||||
sc->sc_dev.dv_xname);
|
||||
psc->mhi_state = mhi_state;
|
||||
break;
|
||||
default:
|
||||
printf("%s: unhandled MHI state change to %x\n",
|
||||
sc->sc_dev.dv_xname, mhi_state);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
ns->queue[ns->cur].ee = ee;
|
||||
ns->queue[ns->cur].mhi_state = mhi_state;
|
||||
ns->queued++;
|
||||
ns->cur = (ns->cur + 1) % nitems(ns->queue);
|
||||
task_add(psc->mhi_taskq, &psc->mhi_newstate_task);
|
||||
if (old_ee != psc->bhi_ee)
|
||||
wakeup(&psc->bhi_ee);
|
||||
if (old_mhi_state != psc->mhi_state)
|
||||
wakeup(&psc->mhi_state);
|
||||
}
|
||||
|
||||
void
|
||||
|
|
@ -3750,7 +3671,7 @@ qwx_pci_intr_ctrl_event_mhi(struct qwx_pci_softc *psc, uint32_t mhi_state)
|
|||
psc->mhi_state, mhi_state);
|
||||
|
||||
if (psc->mhi_state != mhi_state)
|
||||
qwx_mhi_queue_state_change(psc, -1, mhi_state);
|
||||
qwx_mhi_state_change(psc, -1, mhi_state);
|
||||
}
|
||||
|
||||
void
|
||||
|
|
@ -3760,7 +3681,7 @@ qwx_pci_intr_ctrl_event_ee(struct qwx_pci_softc *psc, uint32_t ee)
|
|||
psc->bhi_ee, ee);
|
||||
|
||||
if (psc->bhi_ee != ee)
|
||||
qwx_mhi_queue_state_change(psc, ee, -1);
|
||||
qwx_mhi_state_change(psc, ee, -1);
|
||||
}
|
||||
|
||||
void
|
||||
|
|
@ -4169,7 +4090,7 @@ qwx_pci_intr(void *arg)
|
|||
new_mhi_state = state;
|
||||
|
||||
if (new_ee != -1 || new_mhi_state != -1)
|
||||
qwx_mhi_queue_state_change(psc, new_ee, new_mhi_state);
|
||||
qwx_mhi_state_change(psc, new_ee, new_mhi_state);
|
||||
|
||||
ret = 1;
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue