sync with OpenBSD -current
This commit is contained in:
parent
6fc9e02a30
commit
7768d1f254
GPG key ID:
F42C07F07E2E35B7
35 changed files with 335 additions and 351 deletions
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@ -1,4 +1,4 @@
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/* $OpenBSD: vmm_machdep.c,v 1.24 2024/04/13 21:57:22 dv Exp $ */
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/* $OpenBSD: vmm_machdep.c,v 1.25 2024/04/29 14:47:05 dv Exp $ */
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/*
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* Copyright (c) 2014 Mike Larkin <mlarkin@openbsd.org>
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*
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@ -3691,18 +3691,14 @@ vm_run(struct vm_run_params *vrp)
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}
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/*
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* We may be returning from userland helping us from the last exit.
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* If so (vrp_continue == 1), copy in the exit data from vmd. The
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* exit data will be consumed before the next entry (this typically
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* comprises VCPU register changes as the result of vmd(8)'s actions).
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* We may be returning from userland helping us from the last
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* exit. Copy in the exit data from vmd. The exit data will be
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* consumed before the next entry (this typically comprises
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* VCPU register changes as the result of vmd(8)'s actions).
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*/
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if (vrp->vrp_continue) {
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if (copyin(vrp->vrp_exit, &vcpu->vc_exit,
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sizeof(struct vm_exit)) == EFAULT) {
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ret = EFAULT;
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goto out_unlock;
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}
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}
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ret = copyin(vrp->vrp_exit, &vcpu->vc_exit, sizeof(struct vm_exit));
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if (ret)
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goto out_unlock;
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vcpu->vc_inject.vie_type = vrp->vrp_inject.vie_type;
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vcpu->vc_inject.vie_vector = vrp->vrp_inject.vie_vector;
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@ -4001,67 +3997,28 @@ vcpu_run_vmx(struct vcpu *vcpu, struct vm_run_params *vrp)
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else
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vcpu->vc_intr = 0;
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if (vrp->vrp_continue) {
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switch (vcpu->vc_gueststate.vg_exit_reason) {
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case VMX_EXIT_IO:
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if (vcpu->vc_exit.vei.vei_dir == VEI_DIR_IN)
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vcpu->vc_gueststate.vg_rax =
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vcpu->vc_exit.vei.vei_data;
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vcpu->vc_gueststate.vg_rip =
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vcpu->vc_exit.vrs.vrs_gprs[VCPU_REGS_RIP];
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if (vmwrite(VMCS_GUEST_IA32_RIP,
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vcpu->vc_gueststate.vg_rip)) {
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printf("%s: failed to update rip\n", __func__);
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return (EINVAL);
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}
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break;
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case VMX_EXIT_EPT_VIOLATION:
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ret = vcpu_writeregs_vmx(vcpu, VM_RWREGS_GPRS, 0,
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&vcpu->vc_exit.vrs);
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if (ret) {
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printf("%s: vm %d vcpu %d failed to update "
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"registers\n", __func__,
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vcpu->vc_parent->vm_id, vcpu->vc_id);
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return (EINVAL);
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}
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break;
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case VM_EXIT_NONE:
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case VMX_EXIT_HLT:
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case VMX_EXIT_INT_WINDOW:
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case VMX_EXIT_EXTINT:
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case VMX_EXIT_CPUID:
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case VMX_EXIT_XSETBV:
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break;
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#ifdef VMM_DEBUG
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case VMX_EXIT_TRIPLE_FAULT:
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DPRINTF("%s: vm %d vcpu %d triple fault\n",
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__func__, vcpu->vc_parent->vm_id,
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vcpu->vc_id);
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vmx_vcpu_dump_regs(vcpu);
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dump_vcpu(vcpu);
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vmx_dump_vmcs(vcpu);
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break;
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case VMX_EXIT_ENTRY_FAILED_GUEST_STATE:
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DPRINTF("%s: vm %d vcpu %d failed entry "
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"due to invalid guest state\n",
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__func__, vcpu->vc_parent->vm_id,
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vcpu->vc_id);
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vmx_vcpu_dump_regs(vcpu);
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dump_vcpu(vcpu);
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switch (vcpu->vc_gueststate.vg_exit_reason) {
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case VMX_EXIT_IO:
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if (vcpu->vc_exit.vei.vei_dir == VEI_DIR_IN)
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vcpu->vc_gueststate.vg_rax = vcpu->vc_exit.vei.vei_data;
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vcpu->vc_gueststate.vg_rip =
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vcpu->vc_exit.vrs.vrs_gprs[VCPU_REGS_RIP];
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if (vmwrite(VMCS_GUEST_IA32_RIP, vcpu->vc_gueststate.vg_rip)) {
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printf("%s: failed to update rip\n", __func__);
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return (EINVAL);
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default:
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DPRINTF("%s: unimplemented exit type %d (%s)\n",
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__func__,
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vcpu->vc_gueststate.vg_exit_reason,
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vmx_exit_reason_decode(
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vcpu->vc_gueststate.vg_exit_reason));
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vmx_vcpu_dump_regs(vcpu);
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dump_vcpu(vcpu);
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break;
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#endif /* VMM_DEBUG */
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}
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memset(&vcpu->vc_exit, 0, sizeof(vcpu->vc_exit));
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break;
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case VMX_EXIT_EPT_VIOLATION:
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ret = vcpu_writeregs_vmx(vcpu, VM_RWREGS_GPRS, 0,
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&vcpu->vc_exit.vrs);
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if (ret) {
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printf("%s: vm %d vcpu %d failed to update registers\n",
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__func__, vcpu->vc_parent->vm_id, vcpu->vc_id);
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return (EINVAL);
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}
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break;
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}
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memset(&vcpu->vc_exit, 0, sizeof(vcpu->vc_exit));
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/* Host CR3 */
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cr3 = rcr3();
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@ -6519,31 +6476,29 @@ vcpu_run_svm(struct vcpu *vcpu, struct vm_run_params *vrp)
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* needs to be fixed up depends on what vmd populated in the
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* exit data structure.
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*/
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if (vrp->vrp_continue) {
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switch (vcpu->vc_gueststate.vg_exit_reason) {
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case SVM_VMEXIT_IOIO:
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if (vcpu->vc_exit.vei.vei_dir == VEI_DIR_IN) {
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vcpu->vc_gueststate.vg_rax =
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vcpu->vc_exit.vei.vei_data;
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vmcb->v_rax = vcpu->vc_gueststate.vg_rax;
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}
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vcpu->vc_gueststate.vg_rip =
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vcpu->vc_exit.vrs.vrs_gprs[VCPU_REGS_RIP];
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vmcb->v_rip = vcpu->vc_gueststate.vg_rip;
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break;
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case SVM_VMEXIT_NPF:
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ret = vcpu_writeregs_svm(vcpu, VM_RWREGS_GPRS,
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&vcpu->vc_exit.vrs);
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if (ret) {
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printf("%s: vm %d vcpu %d failed to update "
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"registers\n", __func__,
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vcpu->vc_parent->vm_id, vcpu->vc_id);
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return (EINVAL);
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}
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break;
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switch (vcpu->vc_gueststate.vg_exit_reason) {
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case SVM_VMEXIT_IOIO:
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if (vcpu->vc_exit.vei.vei_dir == VEI_DIR_IN) {
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vcpu->vc_gueststate.vg_rax =
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vcpu->vc_exit.vei.vei_data;
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vmcb->v_rax = vcpu->vc_gueststate.vg_rax;
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}
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memset(&vcpu->vc_exit, 0, sizeof(vcpu->vc_exit));
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vcpu->vc_gueststate.vg_rip =
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vcpu->vc_exit.vrs.vrs_gprs[VCPU_REGS_RIP];
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vmcb->v_rip = vcpu->vc_gueststate.vg_rip;
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break;
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case SVM_VMEXIT_NPF:
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ret = vcpu_writeregs_svm(vcpu, VM_RWREGS_GPRS,
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&vcpu->vc_exit.vrs);
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if (ret) {
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printf("%s: vm %d vcpu %d failed to update "
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"registers\n", __func__,
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vcpu->vc_parent->vm_id, vcpu->vc_id);
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return (EINVAL);
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}
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break;
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}
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memset(&vcpu->vc_exit, 0, sizeof(vcpu->vc_exit));
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while (ret == 0) {
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vmm_update_pvclock(vcpu);
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@ -1,4 +1,4 @@
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/* $OpenBSD: vmmvar.h,v 1.100 2024/04/09 21:55:16 dv Exp $ */
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/* $OpenBSD: vmmvar.h,v 1.101 2024/04/29 14:47:05 dv Exp $ */
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/*
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* Copyright (c) 2014 Mike Larkin <mlarkin@openbsd.org>
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*
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@ -478,7 +478,6 @@ struct vm_run_params {
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/* Input parameters to VMM_IOC_RUN */
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uint32_t vrp_vm_id;
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uint32_t vrp_vcpu_id;
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uint8_t vrp_continue; /* Continuing from an exit */
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struct vcpu_inject_event vrp_inject;
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uint8_t vrp_intr_pending; /* Additional intrs pending? */
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@ -1,4 +1,4 @@
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/* $OpenBSD: fault.c,v 1.47 2023/01/05 20:35:44 kettenis Exp $ */
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/* $OpenBSD: fault.c,v 1.48 2024/04/29 12:33:17 jsg Exp $ */
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/* $NetBSD: fault.c,v 1.46 2004/01/21 15:39:21 skrll Exp $ */
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/*
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@ -96,10 +96,6 @@
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#include <arm/machdep.h>
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#include <arm/vfp.h>
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#ifdef DEBUG
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int last_fault_code; /* For the benefit of pmap_fault_fixup() */
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#endif
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struct sigdata {
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int signo;
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int code;
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@ -1,4 +1,4 @@
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/* $OpenBSD: machdep.h,v 1.5 2016/09/24 13:43:25 kettenis Exp $ */
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/* $OpenBSD: machdep.h,v 1.6 2024/04/29 12:24:46 jsg Exp $ */
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/* $NetBSD: machdep.h,v 1.7 2002/02/21 02:52:21 thorpej Exp $ */
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#ifndef _ARM_MACHDEP_H_
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@ -6,7 +6,6 @@
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/* misc prototypes used by the many arm machdeps */
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void halt (void);
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void parse_mi_bootargs (char *);
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void data_abort_handler (trapframe_t *);
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void prefetch_abort_handler (trapframe_t *);
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void undefinedinstruction_bounce (trapframe_t *);
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@ -18,10 +17,4 @@ void dumpsys (void);
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*/
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u_int initarm (void *, void *, void *, paddr_t);
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/* from arm/arm/intr.c */
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void dosoftints (void);
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void set_spl_masks (void);
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#ifdef DIAGNOSTIC
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void dump_spl_masks (void);
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#endif
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#endif
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@ -1,4 +1,4 @@
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/* $OpenBSD: pmap.h,v 1.55 2023/12/11 22:12:53 kettenis Exp $ */
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/* $OpenBSD: pmap.h,v 1.56 2024/04/29 12:24:46 jsg Exp $ */
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/* $NetBSD: pmap.h,v 1.76 2003/09/06 09:10:46 rearnsha Exp $ */
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/*
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@ -153,18 +153,6 @@ union pmap_cache_state {
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*/
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#define PMAP_CACHE_STATE_ALL 0xffffffffu
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/*
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* This structure is used by machine-dependent code to describe
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* static mappings of devices, created at bootstrap time.
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*/
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struct pmap_devmap {
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vaddr_t pd_va; /* virtual address */
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paddr_t pd_pa; /* physical address */
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psize_t pd_size; /* size of region */
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vm_prot_t pd_prot; /* protection code */
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int pd_cache; /* cache attributes */
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};
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/*
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* The pmap structure itself
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*/
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@ -245,12 +233,6 @@ extern struct pmap kernel_pmap_store;
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#define pmap_unuse_final(p) do { /* nothing */ } while (0)
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#define pmap_remove_holes(vm) do { /* nothing */ } while (0)
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/*
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* Functions that we need to export
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*/
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void pmap_remove_all(pmap_t);
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void pmap_uncache_page(paddr_t, vaddr_t);
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#define PMAP_CHECK_COPYIN 1
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#define PMAP_GROWKERNEL /* turn on pmap_growkernel interface */
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@ -258,7 +240,6 @@ void pmap_uncache_page(paddr_t, vaddr_t);
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/* Functions we use internally. */
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void pmap_bootstrap(pd_entry_t *, vaddr_t, vaddr_t);
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int pmap_fault_fixup(pmap_t, vaddr_t, vm_prot_t, int);
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int pmap_get_pde_pte(pmap_t, vaddr_t, pd_entry_t **, pt_entry_t **);
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int pmap_get_pde(pmap_t, vaddr_t, pd_entry_t **);
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void pmap_set_pcb_pagedir(pmap_t, struct pcb *);
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@ -270,16 +251,11 @@ void vector_page_setprot(int);
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/* XXX */
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void pmap_kenter_cache(vaddr_t va, paddr_t pa, vm_prot_t prot, int cacheable);
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const struct pmap_devmap *pmap_devmap_find_pa(paddr_t, psize_t);
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const struct pmap_devmap *pmap_devmap_find_va(vaddr_t, vsize_t);
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/* Bootstrapping routines. */
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void pmap_map_section(vaddr_t, vaddr_t, paddr_t, int, int);
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void pmap_map_entry(vaddr_t, vaddr_t, paddr_t, int, int);
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vsize_t pmap_map_chunk(vaddr_t, vaddr_t, paddr_t, vsize_t, int, int);
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void pmap_link_l2pt(vaddr_t, vaddr_t, pv_addr_t *);
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void pmap_devmap_bootstrap(vaddr_t, const struct pmap_devmap *);
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void pmap_devmap_register(const struct pmap_devmap *);
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/*
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* The current top of kernel VM
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@ -1,4 +1,4 @@
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/* $OpenBSD: machdep.c,v 1.88 2024/03/17 13:05:40 kettenis Exp $ */
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/* $OpenBSD: machdep.c,v 1.89 2024/04/29 13:01:54 jsg Exp $ */
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/*
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* Copyright (c) 2014 Patrick Wildt <patrick@blueri.se>
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* Copyright (c) 2021 Mark Kettenis <kettenis@openbsd.org>
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@ -620,11 +620,6 @@ dumpsys(void)
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int (*dump)(dev_t, daddr_t, caddr_t, size_t);
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int error;
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#if 0
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/* Save registers. */
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savectx(&dumppcb);
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#endif
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if (dumpdev == NODEV)
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return;
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@ -1,4 +1,4 @@
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/* $OpenBSD: cpu.h,v 1.45 2024/04/19 10:22:50 mpi Exp $ */
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/* $OpenBSD: cpu.h,v 1.46 2024/04/29 13:01:54 jsg Exp $ */
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/*
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* Copyright (c) 2016 Dale Rahn <drahn@dalerahn.com>
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*
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@ -96,10 +96,6 @@ extern uint64_t cpu_id_aa64pfr1;
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#define PROC_PC(p) ((p)->p_addr->u_pcb.pcb_tf->tf_elr)
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#define PROC_STACK(p) ((p)->p_addr->u_pcb.pcb_tf->tf_sp)
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/* The address of the vector page. */
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extern vaddr_t vector_page;
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void arm32_vector_init(vaddr_t, int);
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/*
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* Per-CPU information. For now we assume one CPU.
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*/
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@ -276,29 +272,15 @@ void need_resched(struct cpu_info *);
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// asm code to start new kernel contexts.
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void proc_trampoline(void);
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void child_trampoline(void);
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/*
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* Random cruft
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*/
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void dumpconf(void);
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// cpuswitch.S
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struct pcb;
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void savectx (struct pcb *pcb);
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// machdep.h
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void bootsync (int);
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// fault.c
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int badaddr_read (void *, size_t, void *);
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// syscall.c
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void svc_handler (trapframe_t *);
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/* machine_machdep.c */
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void board_startup(void);
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// functions to manipulate interrupt state
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static __inline void
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restore_daif(uint32_t daif)
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|
|
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|
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@ -1,4 +1,4 @@
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/* $OpenBSD: intc.c,v 1.12 2022/01/03 03:06:50 jsg Exp $ */
|
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/* $OpenBSD: intc.c,v 1.14 2024/04/29 12:42:06 jsg Exp $ */
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/*
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* Copyright (c) 2007,2009 Dale Rahn <drahn@openbsd.org>
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*
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@ -91,8 +91,6 @@ struct intrq {
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int iq_ist; /* share type */
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};
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volatile int softint_pending;
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|
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struct intrq intc_handler[INTC_MAX_IRQ];
|
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u_int32_t intc_smask[NIPL];
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u_int32_t intc_imask[INTC_MAX_BANKS][NIPL];
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|
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@ -310,18 +308,6 @@ intc_setipl(int new)
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restore_interrupts(psw);
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}
|
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|
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void
|
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intc_intr_bootstrap(vaddr_t addr)
|
||||
{
|
||||
int i, j;
|
||||
extern struct bus_space armv7_bs_tag;
|
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intc_iot = &armv7_bs_tag;
|
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intc_ioh = addr;
|
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for (i = 0; i < INTC_NUM_BANKS; i++)
|
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for (j = 0; j < NIPL; j++)
|
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intc_imask[i][j] = 0xffffffff;
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}
|
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|
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void
|
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intc_irq_handler(void *frame)
|
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{
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|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
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/* $OpenBSD: intc.h,v 1.4 2020/07/14 15:34:15 patrick Exp $ */
|
||||
/* $OpenBSD: intc.h,v 1.8 2024/04/29 12:46:22 jsg Exp $ */
|
||||
/*
|
||||
* Copyright (c) 2007,2009 Dale Rahn <drahn@openbsd.org>
|
||||
*
|
||||
|
|
@ -25,42 +25,11 @@
|
|||
#include <machine/intr.h>
|
||||
#include <arm/softintr.h>
|
||||
|
||||
extern volatile int current_spl_level;
|
||||
extern volatile int softint_pending;
|
||||
void intc_do_pending(void);
|
||||
|
||||
#define SI_TO_IRQBIT(si) (1U<<(si))
|
||||
void intc_setipl(int new);
|
||||
void intc_splx(int new);
|
||||
int intc_splraise(int ipl);
|
||||
int intc_spllower(int ipl);
|
||||
void intc_setsoftintr(int si);
|
||||
|
||||
/*
|
||||
* An useful function for interrupt handlers.
|
||||
* XXX: This shouldn't be here.
|
||||
*/
|
||||
static __inline int
|
||||
find_first_bit( uint32_t bits )
|
||||
{
|
||||
int count;
|
||||
|
||||
/* since CLZ is available only on ARMv5, this isn't portable
|
||||
* to all ARM CPUs. This file is for OMAPINTC processor.
|
||||
*/
|
||||
asm( "clz %0, %1" : "=r" (count) : "r" (bits) );
|
||||
return 31-count;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* This function *MUST* be called very early on in a port's
|
||||
* initarm() function, before ANY spl*() functions are called.
|
||||
*
|
||||
* The parameter is the virtual address of the OMAPINTC's Interrupt
|
||||
* Controller registers.
|
||||
*/
|
||||
void intc_intr_bootstrap(vaddr_t);
|
||||
|
||||
void intc_irq_handler(void *);
|
||||
void *intc_intr_establish(int irqno, int level, struct cpu_info *ci,
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $OpenBSD: sxiintc.c,v 1.11 2022/01/03 03:06:50 jsg Exp $ */
|
||||
/* $OpenBSD: sxiintc.c,v 1.12 2024/04/29 12:33:17 jsg Exp $ */
|
||||
/*
|
||||
* Copyright (c) 2007,2009 Dale Rahn <drahn@openbsd.org>
|
||||
* Copyright (c) 2013 Artturi Alm
|
||||
|
|
@ -131,8 +131,6 @@ struct intrq {
|
|||
int iq_ist; /* share type */
|
||||
};
|
||||
|
||||
volatile int a1xsoftint_pending;
|
||||
|
||||
struct intrq sxiintc_handler[NIRQ];
|
||||
u_int32_t sxiintc_smask[NIPL];
|
||||
u_int32_t sxiintc_imask[NBANKS][NIPL];
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $OpenBSD: sxiintc.h,v 1.2 2020/07/14 15:34:15 patrick Exp $ */
|
||||
/* $OpenBSD: sxiintc.h,v 1.4 2024/04/29 12:33:17 jsg Exp $ */
|
||||
/*
|
||||
* Copyright (c) 2007,2009 Dale Rahn <drahn@openbsd.org>
|
||||
*
|
||||
|
|
@ -25,16 +25,11 @@
|
|||
#include <machine/intr.h>
|
||||
#include <arm/softintr.h>
|
||||
|
||||
extern volatile int current_spl_level;
|
||||
extern volatile int softint_pending;
|
||||
void sxiintc_do_pending(void);
|
||||
|
||||
#define SI_TO_IRQBIT(si) (1U<<(si))
|
||||
void sxiintc_setipl(int);
|
||||
void sxiintc_splx(int);
|
||||
int sxiintc_splraise(int);
|
||||
int sxiintc_spllower(int);
|
||||
void sxiintc_setsoftintr(int);
|
||||
|
||||
void sxiintc_irq_handler(void *);
|
||||
void *sxiintc_intr_establish(int, int, struct cpu_info *,
|
||||
|
|
|
|||
|
|
@ -562,7 +562,6 @@ static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev,
|
|||
struct ttm_resource *mem)
|
||||
{
|
||||
struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
|
||||
size_t bus_size = (size_t)mem->size;
|
||||
|
||||
switch (mem->mem_type) {
|
||||
case TTM_PL_SYSTEM:
|
||||
|
|
@ -573,9 +572,6 @@ static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev,
|
|||
break;
|
||||
case TTM_PL_VRAM:
|
||||
mem->bus.offset = mem->start << PAGE_SHIFT;
|
||||
/* check if it's visible */
|
||||
if ((mem->bus.offset + bus_size) > adev->gmc.visible_vram_size)
|
||||
return -EINVAL;
|
||||
|
||||
if (adev->mman.aper_base_kaddr &&
|
||||
mem->placement & TTM_PL_FLAG_CONTIGUOUS)
|
||||
|
|
|
|||
|
|
@ -1562,6 +1562,37 @@ static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev,
|
|||
trace_amdgpu_vm_bo_map(bo_va, mapping);
|
||||
}
|
||||
|
||||
/* Validate operation parameters to prevent potential abuse */
|
||||
static int amdgpu_vm_verify_parameters(struct amdgpu_device *adev,
|
||||
struct amdgpu_bo *bo,
|
||||
uint64_t saddr,
|
||||
uint64_t offset,
|
||||
uint64_t size)
|
||||
{
|
||||
uint64_t tmp, lpfn;
|
||||
|
||||
if (saddr & AMDGPU_GPU_PAGE_MASK
|
||||
|| offset & AMDGPU_GPU_PAGE_MASK
|
||||
|| size & AMDGPU_GPU_PAGE_MASK)
|
||||
return -EINVAL;
|
||||
|
||||
if (check_add_overflow(saddr, size, &tmp)
|
||||
|| check_add_overflow(offset, size, &tmp)
|
||||
|| size == 0 /* which also leads to end < begin */)
|
||||
return -EINVAL;
|
||||
|
||||
/* make sure object fit at this offset */
|
||||
if (bo && offset + size > amdgpu_bo_size(bo))
|
||||
return -EINVAL;
|
||||
|
||||
/* Ensure last pfn not exceed max_pfn */
|
||||
lpfn = (saddr + size - 1) >> AMDGPU_GPU_PAGE_SHIFT;
|
||||
if (lpfn >= adev->vm_manager.max_pfn)
|
||||
return -EINVAL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* amdgpu_vm_bo_map - map bo inside a vm
|
||||
*
|
||||
|
|
@ -1588,21 +1619,14 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
|
|||
struct amdgpu_bo *bo = bo_va->base.bo;
|
||||
struct amdgpu_vm *vm = bo_va->base.vm;
|
||||
uint64_t eaddr;
|
||||
int r;
|
||||
|
||||
/* validate the parameters */
|
||||
if (saddr & ~LINUX_PAGE_MASK || offset & ~LINUX_PAGE_MASK || size & ~LINUX_PAGE_MASK)
|
||||
return -EINVAL;
|
||||
if (saddr + size <= saddr || offset + size <= offset)
|
||||
return -EINVAL;
|
||||
|
||||
/* make sure object fit at this offset */
|
||||
eaddr = saddr + size - 1;
|
||||
if ((bo && offset + size > amdgpu_bo_size(bo)) ||
|
||||
(eaddr >= adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT))
|
||||
return -EINVAL;
|
||||
r = amdgpu_vm_verify_parameters(adev, bo, saddr, offset, size);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
saddr /= AMDGPU_GPU_PAGE_SIZE;
|
||||
eaddr /= AMDGPU_GPU_PAGE_SIZE;
|
||||
eaddr = saddr + (size - 1) / AMDGPU_GPU_PAGE_SIZE;
|
||||
|
||||
tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
|
||||
if (tmp) {
|
||||
|
|
@ -1655,17 +1679,9 @@ int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
|
|||
uint64_t eaddr;
|
||||
int r;
|
||||
|
||||
/* validate the parameters */
|
||||
if (saddr & ~LINUX_PAGE_MASK || offset & ~LINUX_PAGE_MASK || size & ~LINUX_PAGE_MASK)
|
||||
return -EINVAL;
|
||||
if (saddr + size <= saddr || offset + size <= offset)
|
||||
return -EINVAL;
|
||||
|
||||
/* make sure object fit at this offset */
|
||||
eaddr = saddr + size - 1;
|
||||
if ((bo && offset + size > amdgpu_bo_size(bo)) ||
|
||||
(eaddr >= adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT))
|
||||
return -EINVAL;
|
||||
r = amdgpu_vm_verify_parameters(adev, bo, saddr, offset, size);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
/* Allocate all the needed memory */
|
||||
mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
|
||||
|
|
@ -1679,7 +1695,7 @@ int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
|
|||
}
|
||||
|
||||
saddr /= AMDGPU_GPU_PAGE_SIZE;
|
||||
eaddr /= AMDGPU_GPU_PAGE_SIZE;
|
||||
eaddr = saddr + (size - 1) / AMDGPU_GPU_PAGE_SIZE;
|
||||
|
||||
mapping->start = saddr;
|
||||
mapping->last = eaddr;
|
||||
|
|
@ -1766,10 +1782,14 @@ int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
|
|||
struct amdgpu_bo_va_mapping *before, *after, *tmp, *next;
|
||||
DRM_LIST_HEAD(removed);
|
||||
uint64_t eaddr;
|
||||
int r;
|
||||
|
||||
r = amdgpu_vm_verify_parameters(adev, NULL, saddr, 0, size);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
eaddr = saddr + size - 1;
|
||||
saddr /= AMDGPU_GPU_PAGE_SIZE;
|
||||
eaddr /= AMDGPU_GPU_PAGE_SIZE;
|
||||
eaddr = saddr + (size - 1) / AMDGPU_GPU_PAGE_SIZE;
|
||||
|
||||
/* Allocate all the needed memory */
|
||||
before = kzalloc(sizeof(*before), GFP_KERNEL);
|
||||
|
|
|
|||
|
|
@ -818,9 +818,9 @@ struct kfd_process *kfd_create_process(struct task_struct *thread)
|
|||
mutex_lock(&kfd_processes_mutex);
|
||||
|
||||
if (kfd_is_locked()) {
|
||||
mutex_unlock(&kfd_processes_mutex);
|
||||
pr_debug("KFD is locked! Cannot create process");
|
||||
return ERR_PTR(-EINVAL);
|
||||
process = ERR_PTR(-EINVAL);
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* A prior open of /dev/kfd could have already created the process. */
|
||||
|
|
|
|||
|
|
@ -236,9 +236,6 @@ static void optc32_setup_manual_trigger(struct timing_generator *optc)
|
|||
OTG_V_TOTAL_MAX_SEL, 1,
|
||||
OTG_FORCE_LOCK_ON_EVENT, 0,
|
||||
OTG_SET_V_TOTAL_MIN_MASK, (1 << 1)); /* TRIGA */
|
||||
|
||||
// Setup manual flow control for EOF via TRIG_A
|
||||
optc->funcs->setup_manual_trigger(optc);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -259,6 +259,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
|
|||
drm_property_blob_get(crtc_state->post_csc_lut);
|
||||
|
||||
crtc_state->update_pipe = false;
|
||||
crtc_state->update_m_n = false;
|
||||
crtc_state->disable_lp_wm = false;
|
||||
crtc_state->disable_cxsr = false;
|
||||
crtc_state->update_wm_pre = false;
|
||||
|
|
|
|||
|
|
@ -2453,7 +2453,8 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
|
|||
intel_atomic_get_old_cdclk_state(state);
|
||||
const struct intel_cdclk_state *new_cdclk_state =
|
||||
intel_atomic_get_new_cdclk_state(state);
|
||||
enum pipe pipe = new_cdclk_state->pipe;
|
||||
struct intel_cdclk_config cdclk_config;
|
||||
enum pipe pipe;
|
||||
|
||||
if (!intel_cdclk_changed(&old_cdclk_state->actual,
|
||||
&new_cdclk_state->actual))
|
||||
|
|
@ -2462,12 +2463,25 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
|
|||
if (IS_DG2(i915))
|
||||
intel_cdclk_pcode_pre_notify(state);
|
||||
|
||||
if (new_cdclk_state->disable_pipes ||
|
||||
old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) {
|
||||
drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
|
||||
if (new_cdclk_state->disable_pipes) {
|
||||
cdclk_config = new_cdclk_state->actual;
|
||||
pipe = INVALID_PIPE;
|
||||
} else {
|
||||
if (new_cdclk_state->actual.cdclk >= old_cdclk_state->actual.cdclk) {
|
||||
cdclk_config = new_cdclk_state->actual;
|
||||
pipe = new_cdclk_state->pipe;
|
||||
} else {
|
||||
cdclk_config = old_cdclk_state->actual;
|
||||
pipe = INVALID_PIPE;
|
||||
}
|
||||
|
||||
intel_set_cdclk(i915, &new_cdclk_state->actual, pipe);
|
||||
cdclk_config.voltage_level = max(new_cdclk_state->actual.voltage_level,
|
||||
old_cdclk_state->actual.voltage_level);
|
||||
}
|
||||
|
||||
drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
|
||||
|
||||
intel_set_cdclk(i915, &cdclk_config, pipe);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -2485,7 +2499,7 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
|
|||
intel_atomic_get_old_cdclk_state(state);
|
||||
const struct intel_cdclk_state *new_cdclk_state =
|
||||
intel_atomic_get_new_cdclk_state(state);
|
||||
enum pipe pipe = new_cdclk_state->pipe;
|
||||
enum pipe pipe;
|
||||
|
||||
if (!intel_cdclk_changed(&old_cdclk_state->actual,
|
||||
&new_cdclk_state->actual))
|
||||
|
|
@ -2495,11 +2509,14 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
|
|||
intel_cdclk_pcode_post_notify(state);
|
||||
|
||||
if (!new_cdclk_state->disable_pipes &&
|
||||
old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) {
|
||||
drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
|
||||
new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk)
|
||||
pipe = new_cdclk_state->pipe;
|
||||
else
|
||||
pipe = INVALID_PIPE;
|
||||
|
||||
intel_set_cdclk(i915, &new_cdclk_state->actual, pipe);
|
||||
}
|
||||
drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
|
||||
|
||||
intel_set_cdclk(i915, &new_cdclk_state->actual, pipe);
|
||||
}
|
||||
|
||||
static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
|
||||
|
|
|
|||
|
|
@ -468,9 +468,56 @@ static int intel_mode_vblank_start(const struct drm_display_mode *mode)
|
|||
return vblank_start;
|
||||
}
|
||||
|
||||
static void intel_crtc_vblank_evade_scanlines(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc,
|
||||
int *min, int *max, int *vblank_start)
|
||||
{
|
||||
const struct intel_crtc_state *old_crtc_state =
|
||||
intel_atomic_get_old_crtc_state(state, crtc);
|
||||
const struct intel_crtc_state *new_crtc_state =
|
||||
intel_atomic_get_new_crtc_state(state, crtc);
|
||||
const struct intel_crtc_state *crtc_state;
|
||||
const struct drm_display_mode *adjusted_mode;
|
||||
|
||||
/*
|
||||
* During fastsets/etc. the transcoder is still
|
||||
* running with the old timings at this point.
|
||||
*
|
||||
* TODO: maybe just use the active timings here?
|
||||
*/
|
||||
if (intel_crtc_needs_modeset(new_crtc_state))
|
||||
crtc_state = new_crtc_state;
|
||||
else
|
||||
crtc_state = old_crtc_state;
|
||||
|
||||
adjusted_mode = &crtc_state->hw.adjusted_mode;
|
||||
|
||||
if (crtc->mode_flags & I915_MODE_FLAG_VRR) {
|
||||
if (intel_vrr_is_push_sent(crtc_state))
|
||||
*vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
|
||||
else
|
||||
*vblank_start = intel_vrr_vmax_vblank_start(crtc_state);
|
||||
} else {
|
||||
*vblank_start = intel_mode_vblank_start(adjusted_mode);
|
||||
}
|
||||
|
||||
/* FIXME needs to be calibrated sensibly */
|
||||
*min = *vblank_start - intel_usecs_to_scanlines(adjusted_mode,
|
||||
VBLANK_EVASION_TIME_US);
|
||||
*max = *vblank_start - 1;
|
||||
|
||||
/*
|
||||
* M/N is double buffered on the transcoder's undelayed vblank,
|
||||
* so with seamless M/N we must evade both vblanks.
|
||||
*/
|
||||
if (new_crtc_state->update_m_n)
|
||||
*min -= adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay;
|
||||
}
|
||||
|
||||
/**
|
||||
* intel_pipe_update_start() - start update of a set of display registers
|
||||
* @new_crtc_state: the new crtc state
|
||||
* @state: the atomic state
|
||||
* @crtc: the crtc
|
||||
*
|
||||
* Mark the start of an update to pipe registers that should be updated
|
||||
* atomically regarding vblank. If the next vblank will happens within
|
||||
|
|
@ -480,11 +527,12 @@ static int intel_mode_vblank_start(const struct drm_display_mode *mode)
|
|||
* until a subsequent call to intel_pipe_update_end(). That is done to
|
||||
* avoid random delays.
|
||||
*/
|
||||
void intel_pipe_update_start(struct intel_crtc_state *new_crtc_state)
|
||||
void intel_pipe_update_start(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc)
|
||||
{
|
||||
struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
|
||||
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
|
||||
const struct drm_display_mode *adjusted_mode = &new_crtc_state->hw.adjusted_mode;
|
||||
struct intel_crtc_state *new_crtc_state =
|
||||
intel_atomic_get_new_crtc_state(state, crtc);
|
||||
long timeout = msecs_to_jiffies_timeout(1);
|
||||
int scanline, min, max, vblank_start;
|
||||
wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
|
||||
|
|
@ -500,27 +548,7 @@ void intel_pipe_update_start(struct intel_crtc_state *new_crtc_state)
|
|||
if (intel_crtc_needs_vblank_work(new_crtc_state))
|
||||
intel_crtc_vblank_work_init(new_crtc_state);
|
||||
|
||||
if (new_crtc_state->vrr.enable) {
|
||||
if (intel_vrr_is_push_sent(new_crtc_state))
|
||||
vblank_start = intel_vrr_vmin_vblank_start(new_crtc_state);
|
||||
else
|
||||
vblank_start = intel_vrr_vmax_vblank_start(new_crtc_state);
|
||||
} else {
|
||||
vblank_start = intel_mode_vblank_start(adjusted_mode);
|
||||
}
|
||||
|
||||
/* FIXME needs to be calibrated sensibly */
|
||||
min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
|
||||
VBLANK_EVASION_TIME_US);
|
||||
max = vblank_start - 1;
|
||||
|
||||
/*
|
||||
* M/N is double buffered on the transcoder's undelayed vblank,
|
||||
* so with seamless M/N we must evade both vblanks.
|
||||
*/
|
||||
if (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state))
|
||||
min -= adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay;
|
||||
|
||||
intel_crtc_vblank_evade_scanlines(state, crtc, &min, &max, &vblank_start);
|
||||
if (min <= 0 || max <= 0)
|
||||
goto irq_disable;
|
||||
|
||||
|
|
@ -631,15 +659,18 @@ static void dbg_vblank_evade(struct intel_crtc *crtc, ktime_t end) {}
|
|||
|
||||
/**
|
||||
* intel_pipe_update_end() - end update of a set of display registers
|
||||
* @new_crtc_state: the new crtc state
|
||||
* @state: the atomic state
|
||||
* @crtc: the crtc
|
||||
*
|
||||
* Mark the end of an update started with intel_pipe_update_start(). This
|
||||
* re-enables interrupts and verifies the update was actually completed
|
||||
* before a vblank.
|
||||
*/
|
||||
void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
|
||||
void intel_pipe_update_end(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc)
|
||||
{
|
||||
struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
|
||||
struct intel_crtc_state *new_crtc_state =
|
||||
intel_atomic_get_new_crtc_state(state, crtc);
|
||||
enum pipe pipe = crtc->pipe;
|
||||
int scanline_end = intel_get_crtc_scanline(crtc);
|
||||
u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
|
||||
|
|
@ -697,15 +728,6 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
|
|||
*/
|
||||
intel_vrr_send_push(new_crtc_state);
|
||||
|
||||
/*
|
||||
* Seamless M/N update may need to update frame timings.
|
||||
*
|
||||
* FIXME Should be synchronized with the start of vblank somehow...
|
||||
*/
|
||||
if (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state))
|
||||
intel_crtc_update_active_timings(new_crtc_state,
|
||||
new_crtc_state->vrr.enable);
|
||||
|
||||
local_irq_enable();
|
||||
|
||||
if (intel_vgpu_active(dev_priv))
|
||||
|
|
|
|||
|
|
@ -37,8 +37,10 @@ void intel_crtc_state_reset(struct intel_crtc_state *crtc_state,
|
|||
u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
|
||||
void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state);
|
||||
void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state);
|
||||
void intel_pipe_update_start(struct intel_crtc_state *new_crtc_state);
|
||||
void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
|
||||
void intel_pipe_update_start(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc);
|
||||
void intel_pipe_update_end(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc);
|
||||
void intel_wait_for_vblank_workers(struct intel_atomic_state *state);
|
||||
struct intel_crtc *intel_first_crtc(struct drm_i915_private *i915);
|
||||
struct intel_crtc *intel_crtc_for_pipe(struct drm_i915_private *i915,
|
||||
|
|
|
|||
|
|
@ -5215,7 +5215,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
|
|||
PIPE_CONF_CHECK_X(lane_lat_optim_mask);
|
||||
|
||||
if (HAS_DOUBLE_BUFFERED_M_N(dev_priv)) {
|
||||
if (!fastset || !pipe_config->seamless_m_n)
|
||||
if (!fastset || !pipe_config->update_m_n)
|
||||
PIPE_CONF_CHECK_M_N(dp_m_n);
|
||||
} else {
|
||||
PIPE_CONF_CHECK_M_N(dp_m_n);
|
||||
|
|
@ -5353,7 +5353,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
|
|||
if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5)
|
||||
PIPE_CONF_CHECK_I(pipe_bpp);
|
||||
|
||||
if (!fastset || !pipe_config->seamless_m_n) {
|
||||
if (!fastset || !pipe_config->update_m_n) {
|
||||
PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock);
|
||||
PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock);
|
||||
}
|
||||
|
|
@ -5448,6 +5448,7 @@ int intel_modeset_all_pipes(struct intel_atomic_state *state,
|
|||
|
||||
crtc_state->uapi.mode_changed = true;
|
||||
crtc_state->update_pipe = false;
|
||||
crtc_state->update_m_n = false;
|
||||
|
||||
ret = drm_atomic_add_affected_connectors(&state->base,
|
||||
&crtc->base);
|
||||
|
|
@ -5565,13 +5566,14 @@ static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_sta
|
|||
{
|
||||
struct drm_i915_private *i915 = to_i915(old_crtc_state->uapi.crtc->dev);
|
||||
|
||||
if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true)) {
|
||||
if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
|
||||
drm_dbg_kms(&i915->drm, "fastset requirement not met, forcing full modeset\n");
|
||||
else
|
||||
new_crtc_state->uapi.mode_changed = false;
|
||||
|
||||
return;
|
||||
}
|
||||
if (intel_crtc_needs_modeset(new_crtc_state))
|
||||
new_crtc_state->update_m_n = false;
|
||||
|
||||
new_crtc_state->uapi.mode_changed = false;
|
||||
if (!intel_crtc_needs_modeset(new_crtc_state))
|
||||
new_crtc_state->update_pipe = true;
|
||||
}
|
||||
|
|
@ -6297,6 +6299,7 @@ int intel_atomic_check(struct drm_device *dev,
|
|||
if (intel_cpu_transcoders_need_modeset(state, BIT(master))) {
|
||||
new_crtc_state->uapi.mode_changed = true;
|
||||
new_crtc_state->update_pipe = false;
|
||||
new_crtc_state->update_m_n = false;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -6309,6 +6312,7 @@ int intel_atomic_check(struct drm_device *dev,
|
|||
if (intel_cpu_transcoders_need_modeset(state, trans)) {
|
||||
new_crtc_state->uapi.mode_changed = true;
|
||||
new_crtc_state->update_pipe = false;
|
||||
new_crtc_state->update_m_n = false;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -6316,6 +6320,7 @@ int intel_atomic_check(struct drm_device *dev,
|
|||
if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes)) {
|
||||
new_crtc_state->uapi.mode_changed = true;
|
||||
new_crtc_state->update_pipe = false;
|
||||
new_crtc_state->update_m_n = false;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -6494,7 +6499,7 @@ static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
|
|||
IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
|
||||
hsw_set_linetime_wm(new_crtc_state);
|
||||
|
||||
if (new_crtc_state->seamless_m_n)
|
||||
if (new_crtc_state->update_m_n)
|
||||
intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder,
|
||||
&new_crtc_state->dp_m_n);
|
||||
}
|
||||
|
|
@ -6533,6 +6538,8 @@ static void commit_pipe_post_planes(struct intel_atomic_state *state,
|
|||
struct intel_crtc *crtc)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
|
||||
const struct intel_crtc_state *old_crtc_state =
|
||||
intel_atomic_get_old_crtc_state(state, crtc);
|
||||
const struct intel_crtc_state *new_crtc_state =
|
||||
intel_atomic_get_new_crtc_state(state, crtc);
|
||||
|
||||
|
|
@ -6544,6 +6551,9 @@ static void commit_pipe_post_planes(struct intel_atomic_state *state,
|
|||
if (DISPLAY_VER(dev_priv) >= 9 &&
|
||||
!intel_crtc_needs_modeset(new_crtc_state))
|
||||
skl_detach_scalers(new_crtc_state);
|
||||
|
||||
if (vrr_enabling(old_crtc_state, new_crtc_state))
|
||||
intel_vrr_enable(new_crtc_state);
|
||||
}
|
||||
|
||||
static void intel_enable_crtc(struct intel_atomic_state *state,
|
||||
|
|
@ -6584,12 +6594,6 @@ static void intel_update_crtc(struct intel_atomic_state *state,
|
|||
intel_dpt_configure(crtc);
|
||||
}
|
||||
|
||||
if (vrr_enabling(old_crtc_state, new_crtc_state)) {
|
||||
intel_vrr_enable(new_crtc_state);
|
||||
intel_crtc_update_active_timings(new_crtc_state,
|
||||
new_crtc_state->vrr.enable);
|
||||
}
|
||||
|
||||
if (!modeset) {
|
||||
if (new_crtc_state->preload_luts &&
|
||||
intel_crtc_needs_color_update(new_crtc_state))
|
||||
|
|
@ -6616,7 +6620,7 @@ static void intel_update_crtc(struct intel_atomic_state *state,
|
|||
intel_crtc_planes_update_noarm(state, crtc);
|
||||
|
||||
/* Perform vblank evasion around commit operation */
|
||||
intel_pipe_update_start(new_crtc_state);
|
||||
intel_pipe_update_start(state, crtc);
|
||||
|
||||
commit_pipe_pre_planes(state, crtc);
|
||||
|
||||
|
|
@ -6624,7 +6628,16 @@ static void intel_update_crtc(struct intel_atomic_state *state,
|
|||
|
||||
commit_pipe_post_planes(state, crtc);
|
||||
|
||||
intel_pipe_update_end(new_crtc_state);
|
||||
intel_pipe_update_end(state, crtc);
|
||||
|
||||
/*
|
||||
* VRR/Seamless M/N update may need to update frame timings.
|
||||
*
|
||||
* FIXME Should be synchronized with the start of vblank somehow...
|
||||
*/
|
||||
if (vrr_enabling(old_crtc_state, new_crtc_state) || new_crtc_state->update_m_n)
|
||||
intel_crtc_update_active_timings(new_crtc_state,
|
||||
new_crtc_state->vrr.enable);
|
||||
|
||||
/*
|
||||
* We usually enable FIFO underrun interrupts as part of the
|
||||
|
|
|
|||
|
|
@ -47,6 +47,7 @@ struct drm_printer;
|
|||
#define HAS_DPT(i915) (DISPLAY_VER(i915) >= 13)
|
||||
#define HAS_DSB(i915) (DISPLAY_INFO(i915)->has_dsb)
|
||||
#define HAS_DSC(__i915) (DISPLAY_RUNTIME_INFO(__i915)->has_dsc)
|
||||
#define HAS_DSC_MST(__i915) (DISPLAY_VER(__i915) >= 12 && HAS_DSC(__i915))
|
||||
#define HAS_FBC(i915) (DISPLAY_RUNTIME_INFO(i915)->fbc_mask != 0)
|
||||
#define HAS_FPGA_DBG_UNCLAIMED(i915) (DISPLAY_INFO(i915)->has_fpga_dbg)
|
||||
#define HAS_FW_BLC(i915) (DISPLAY_VER(i915) > 2)
|
||||
|
|
|
|||
|
|
@ -1084,6 +1084,7 @@ struct intel_crtc_state {
|
|||
|
||||
unsigned fb_bits; /* framebuffers to flip */
|
||||
bool update_pipe; /* can a fast modeset be performed? */
|
||||
bool update_m_n; /* update M/N seamlessly during fastset? */
|
||||
bool disable_cxsr;
|
||||
bool update_wm_pre, update_wm_post; /* watermarks are updated */
|
||||
bool fifo_changed; /* FIFO split is changed */
|
||||
|
|
@ -1196,7 +1197,6 @@ struct intel_crtc_state {
|
|||
/* m2_n2 for eDP downclock */
|
||||
struct intel_link_m_n dp_m2_n2;
|
||||
bool has_drrs;
|
||||
bool seamless_m_n;
|
||||
|
||||
/* PSR is supported but might not be enabled due the lack of enabled planes */
|
||||
bool has_psr;
|
||||
|
|
|
|||
|
|
@ -1310,13 +1310,14 @@ bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp)
|
|||
static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
|
||||
const struct intel_crtc_state *pipe_config)
|
||||
{
|
||||
struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
|
||||
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
|
||||
|
||||
/* On TGL, FEC is supported on all Pipes */
|
||||
if (DISPLAY_VER(dev_priv) >= 12)
|
||||
return true;
|
||||
|
||||
if (DISPLAY_VER(dev_priv) == 11 && pipe_config->cpu_transcoder != TRANSCODER_A)
|
||||
if (DISPLAY_VER(dev_priv) == 11 && encoder->port != PORT_A &&
|
||||
!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))
|
||||
return true;
|
||||
|
||||
return false;
|
||||
|
|
@ -2147,8 +2148,12 @@ intel_dp_drrs_compute_config(struct intel_connector *connector,
|
|||
intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode);
|
||||
int pixel_clock;
|
||||
|
||||
if (has_seamless_m_n(connector))
|
||||
pipe_config->seamless_m_n = true;
|
||||
/*
|
||||
* FIXME all joined pipes share the same transcoder.
|
||||
* Need to account for that when updating M/N live.
|
||||
*/
|
||||
if (has_seamless_m_n(connector) && !pipe_config->bigjoiner_pipes)
|
||||
pipe_config->update_m_n = true;
|
||||
|
||||
if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {
|
||||
if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder))
|
||||
|
|
|
|||
|
|
@ -964,7 +964,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
|
|||
return 0;
|
||||
}
|
||||
|
||||
if (DISPLAY_VER(dev_priv) >= 10 &&
|
||||
if (HAS_DSC_MST(dev_priv) &&
|
||||
drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
|
||||
/*
|
||||
* TBD pass the connector BPC,
|
||||
|
|
|
|||
|
|
@ -33,6 +33,7 @@
|
|||
#include "gt/intel_engine.h"
|
||||
#include "gt/intel_engine_heartbeat.h"
|
||||
#include "gt/intel_gt.h"
|
||||
#include "gt/intel_gt_pm.h"
|
||||
#include "gt/intel_gt_requests.h"
|
||||
#include "gt/intel_tlb.h"
|
||||
|
||||
|
|
@ -110,12 +111,34 @@ static inline struct i915_vma *active_to_vma(struct i915_active *ref)
|
|||
|
||||
static int __i915_vma_active(struct i915_active *ref)
|
||||
{
|
||||
return i915_vma_tryget(active_to_vma(ref)) ? 0 : -ENOENT;
|
||||
struct i915_vma *vma = active_to_vma(ref);
|
||||
|
||||
if (!i915_vma_tryget(vma))
|
||||
return -ENOENT;
|
||||
|
||||
/*
|
||||
* Exclude global GTT VMA from holding a GT wakeref
|
||||
* while active, otherwise GPU never goes idle.
|
||||
*/
|
||||
if (!i915_vma_is_ggtt(vma))
|
||||
intel_gt_pm_get(vma->vm->gt);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __i915_vma_retire(struct i915_active *ref)
|
||||
{
|
||||
i915_vma_put(active_to_vma(ref));
|
||||
struct i915_vma *vma = active_to_vma(ref);
|
||||
|
||||
if (!i915_vma_is_ggtt(vma)) {
|
||||
/*
|
||||
* Since we can be called from atomic contexts,
|
||||
* use an async variant of intel_gt_pm_put().
|
||||
*/
|
||||
intel_gt_pm_put_async(vma->vm->gt);
|
||||
}
|
||||
|
||||
i915_vma_put(vma);
|
||||
}
|
||||
|
||||
static struct i915_vma *
|
||||
|
|
@ -1413,7 +1436,7 @@ int i915_vma_pin_ww(struct i915_vma *vma, struct i915_gem_ww_ctx *ww,
|
|||
struct i915_vma_work *work = NULL;
|
||||
struct dma_fence *moving = NULL;
|
||||
struct i915_vma_resource *vma_res = NULL;
|
||||
intel_wakeref_t wakeref = 0;
|
||||
intel_wakeref_t wakeref;
|
||||
unsigned int bound;
|
||||
int err;
|
||||
|
||||
|
|
@ -1433,8 +1456,14 @@ int i915_vma_pin_ww(struct i915_vma *vma, struct i915_gem_ww_ctx *ww,
|
|||
if (err)
|
||||
return err;
|
||||
|
||||
if (flags & PIN_GLOBAL)
|
||||
wakeref = intel_runtime_pm_get(&vma->vm->i915->runtime_pm);
|
||||
/*
|
||||
* In case of a global GTT, we must hold a runtime-pm wakeref
|
||||
* while global PTEs are updated. In other cases, we hold
|
||||
* the rpm reference while the VMA is active. Since runtime
|
||||
* resume may require allocations, which are forbidden inside
|
||||
* vm->mutex, get the first rpm wakeref outside of the mutex.
|
||||
*/
|
||||
wakeref = intel_runtime_pm_get(&vma->vm->i915->runtime_pm);
|
||||
|
||||
if (flags & vma->vm->bind_async_flags) {
|
||||
/* lock VM */
|
||||
|
|
@ -1570,8 +1599,7 @@ err_fence:
|
|||
if (work)
|
||||
dma_fence_work_commit_imm(&work->base);
|
||||
err_rpm:
|
||||
if (wakeref)
|
||||
intel_runtime_pm_put(&vma->vm->i915->runtime_pm, wakeref);
|
||||
intel_runtime_pm_put(&vma->vm->i915->runtime_pm, wakeref);
|
||||
|
||||
if (moving)
|
||||
dma_fence_put(moving);
|
||||
|
|
|
|||
|
|
@ -8,4 +8,8 @@
|
|||
#define struct_size(p, member, n) \
|
||||
(sizeof(*(p)) + ((n) * (sizeof(*(p)->member))))
|
||||
|
||||
#if defined(__clang__) || (defined(__GNUC__) && __GNUC__ >= 5)
|
||||
#define check_add_overflow(x, y, sum) __builtin_add_overflow(x, y, sum)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -926,8 +926,12 @@ bool radeon_get_atom_connector_info_from_supported_devices_table(struct
|
|||
max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
|
||||
|
||||
for (i = 0; i < max_device; i++) {
|
||||
ATOM_CONNECTOR_INFO_I2C ci =
|
||||
supported_devices->info.asConnInfo[i];
|
||||
ATOM_CONNECTOR_INFO_I2C ci;
|
||||
|
||||
if (frev > 1)
|
||||
ci = supported_devices->info_2d1.asConnInfo[i];
|
||||
else
|
||||
ci = supported_devices->info.asConnInfo[i];
|
||||
|
||||
bios_connectors[i].valid = false;
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue