sync with OpenBSD -current

sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c

@@ -4228,6 +4228,8 @@ int amdgpu_device_prepare(struct drm_device *dev)
 	if (r)
 		return r;
 
+	flush_delayed_work(&adev->gfx.gfx_off_delay_work);
+
 	for (i = 0; i < adev->num_ip_blocks; i++) {
 		if (!adev->ip_blocks[i].status.valid)
 			continue;

sys/dev/pci/drm/drm_prime.c

@@ -586,7 +586,16 @@ int drm_gem_map_attach(struct dma_buf *dma_buf,
 {
 	struct drm_gem_object *obj = dma_buf->priv;
 
+	/*
+	 * drm_gem_map_dma_buf() requires obj->get_sg_table(), but drivers
+	 * that implement their own ->map_dma_buf() do not.
+	 */
+#ifdef notyet
+	if (dma_buf->ops->map_dma_buf == drm_gem_map_dma_buf &&
+	    !obj->funcs->get_sg_table)
+#else
 	if (!obj->funcs->get_sg_table)
+#endif
 		return -ENOSYS;
 
 	return drm_gem_pin(obj);

sys/dev/pci/drm/files.drm

@@ -1,4 +1,4 @@
-# $OpenBSD: files.drm,v 1.62 2024/01/22 18:54:01 kettenis Exp $
+# $OpenBSD: files.drm,v 1.63 2024/04/11 03:40:05 jsg Exp $
 
 #file	dev/pci/drm/aperture.c			drm
 file	dev/pci/drm/dma-resv.c			drm
@@ -292,6 +292,7 @@ file	dev/pci/drm/i915/gt/intel_ggtt_gmch.c		inteldrm
 file	dev/pci/drm/i915/gt/intel_gsc.c			inteldrm
 file	dev/pci/drm/i915/gt/intel_gt.c			inteldrm
 file	dev/pci/drm/i915/gt/intel_gt_buffer_pool.c	inteldrm
+file	dev/pci/drm/i915/gt/intel_gt_ccs_mode.c		inteldrm
 file	dev/pci/drm/i915/gt/intel_gt_clock_utils.c	inteldrm
 file	dev/pci/drm/i915/gt/intel_gt_debugfs.c		inteldrm
 file	dev/pci/drm/i915/gt/intel_gt_engines_debugfs.c	inteldrm

sys/dev/pci/drm/i915/gt/intel_engine_cs.c

@@ -916,6 +916,23 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
 		info->engine_mask &= ~BIT(GSC0);
 	}
 
+	/*
+	 * Do not create the command streamer for CCS slices beyond the first.
+	 * All the workload submitted to the first engine will be shared among
+	 * all the slices.
+	 *
+	 * Once the user will be allowed to customize the CCS mode, then this
+	 * check needs to be removed.
+	 */
+	if (IS_DG2(gt->i915)) {
+		u8 first_ccs = __ffs(CCS_MASK(gt));
+
+		/* Mask off all the CCS engine */
+		info->engine_mask &= ~GENMASK(CCS3, CCS0);
+		/* Put back in the first CCS engine */
+		info->engine_mask |= BIT(_CCS(first_ccs));
+	}
+
 	return info->engine_mask;
 }
 

sys/dev/pci/drm/i915/gt/intel_gt_ccs_mode.c

@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2024 Intel Corporation
+ */
+
+#include "i915_drv.h"
+#include "intel_gt.h"
+#include "intel_gt_ccs_mode.h"
+#include "intel_gt_regs.h"
+
+void intel_gt_apply_ccs_mode(struct intel_gt *gt)
+{
+	int cslice;
+	u32 mode = 0;
+	int first_ccs = __ffs(CCS_MASK(gt));
+
+	if (!IS_DG2(gt->i915))
+		return;
+
+	/* Build the value for the fixed CCS load balancing */
+	for (cslice = 0; cslice < I915_MAX_CCS; cslice++) {
+		if (CCS_MASK(gt) & BIT(cslice))
+			/*
+			 * If available, assign the cslice
+			 * to the first available engine...
+			 */
+			mode |= XEHP_CCS_MODE_CSLICE(cslice, first_ccs);
+
+		else
+			/*
+			 * ... otherwise, mark the cslice as
+			 * unavailable if no CCS dispatches here
+			 */
+			mode |= XEHP_CCS_MODE_CSLICE(cslice,
+						     XEHP_CCS_MODE_CSLICE_MASK);
+	}
+
+	intel_uncore_write(gt->uncore, XEHP_CCS_MODE, mode);
+}

sys/dev/pci/drm/i915/gt/intel_gt_ccs_mode.h

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2024 Intel Corporation
+ */
+
+#ifndef __INTEL_GT_CCS_MODE_H__
+#define __INTEL_GT_CCS_MODE_H__
+
+struct intel_gt;
+
+void intel_gt_apply_ccs_mode(struct intel_gt *gt);
+
+#endif /* __INTEL_GT_CCS_MODE_H__ */

sys/dev/pci/drm/i915/gt/intel_gt_regs.h

@@ -1468,8 +1468,14 @@
 #define   ECOBITS_PPGTT_CACHE4B			(0 << 8)
 
 #define GEN12_RCU_MODE				_MMIO(0x14800)
+#define   XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE	REG_BIT(1)
 #define   GEN12_RCU_MODE_CCS_ENABLE		REG_BIT(0)
 
+#define XEHP_CCS_MODE				_MMIO(0x14804)
+#define   XEHP_CCS_MODE_CSLICE_MASK		REG_GENMASK(2, 0) /* CCS0-3 + rsvd */
+#define   XEHP_CCS_MODE_CSLICE_WIDTH		ilog2(XEHP_CCS_MODE_CSLICE_MASK + 1)
+#define   XEHP_CCS_MODE_CSLICE(cslice, ccs)	(ccs << (cslice * XEHP_CCS_MODE_CSLICE_WIDTH))
+
 #define CHV_FUSE_GT				_MMIO(VLV_GUNIT_BASE + 0x2168)
 #define   CHV_FGT_DISABLE_SS0			(1 << 10)
 #define   CHV_FGT_DISABLE_SS1			(1 << 11)

sys/dev/pci/drm/i915/gt/intel_workarounds.c

@@ -10,6 +10,7 @@
 #include "intel_engine_regs.h"
 #include "intel_gpu_commands.h"
 #include "intel_gt.h"
+#include "intel_gt_ccs_mode.h"
 #include "intel_gt_mcr.h"
 #include "intel_gt_regs.h"
 #include "intel_ring.h"
@@ -50,7 +51,8 @@
  *   registers belonging to BCS, VCS or VECS should be implemented in
  *   xcs_engine_wa_init(). Workarounds for registers not belonging to a specific
  *   engine's MMIO range but that are part of of the common RCS/CCS reset domain
- *   should be implemented in general_render_compute_wa_init().
+ *   should be implemented in general_render_compute_wa_init(). The settings
+ *   about the CCS load balancing should be added in ccs_engine_wa_mode().
  *
  * - GT workarounds: the list of these WAs is applied whenever these registers
  *   revert to their default values: on GPU reset, suspend/resume [1]_, etc.
@@ -2823,6 +2825,28 @@ add_render_compute_tuning_settings(struct intel_gt *gt,
 		wa_write_clr(wal, GEN8_GARBCNTL, GEN12_BUS_HASH_CTL_BIT_EXC);
 }
 
+static void ccs_engine_wa_mode(struct intel_engine_cs *engine, struct i915_wa_list *wal)
+{
+	struct intel_gt *gt = engine->gt;
+
+	if (!IS_DG2(gt->i915))
+		return;
+
+	/*
+	 * Wa_14019159160: This workaround, along with others, leads to
+	 * significant challenges in utilizing load balancing among the
+	 * CCS slices. Consequently, an architectural decision has been
+	 * made to completely disable automatic CCS load balancing.
+	 */
+	wa_masked_en(wal, GEN12_RCU_MODE, XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE);
+
+	/*
+	 * After having disabled automatic load balancing we need to
+	 * assign all slices to a single CCS. We will call it CCS mode 1
+	 */
+	intel_gt_apply_ccs_mode(gt);
+}
+
 /*
  * The workarounds in this function apply to shared registers in
  * the general render reset domain that aren't tied to a
@@ -2970,8 +2994,10 @@ engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal
 	 * to a single RCS/CCS engine's workaround list since
 	 * they're reset as part of the general render domain reset.
 	 */
-	if (engine->flags & I915_ENGINE_FIRST_RENDER_COMPUTE)
+	if (engine->flags & I915_ENGINE_FIRST_RENDER_COMPUTE) {
 		general_render_compute_wa_init(engine, wal);
+		ccs_engine_wa_mode(engine, wal);
+	}
 
 	if (engine->class == COMPUTE_CLASS)
 		ccs_engine_wa_init(engine, wal);

sys/dev/pci/if_mcx.c

@@ -1,4 +1,4 @@
-/*	$OpenBSD: if_mcx.c,v 1.111 2023/11/10 15:51:20 bluhm Exp $ */
+/*	$OpenBSD: if_mcx.c,v 1.113 2024/04/11 06:42:12 jmatthew Exp $ */
 
 /*
  * Copyright (c) 2017 David Gwynne <dlg@openbsd.org>
@@ -199,6 +199,19 @@ CTASSERT(MCX_MAX_QUEUES * MCX_WQ_DOORBELL_STRIDE <
 #define MCX_ETHER_CAP_50G_CR2		30
 #define MCX_ETHER_CAP_50G_KR2		31
 
+#define MCX_ETHER_EXT_CAP_SGMII_100	0
+#define MCX_ETHER_EXT_CAP_1000_X	1
+#define MCX_ETHER_EXT_CAP_5G_R		3
+#define MCX_ETHER_EXT_CAP_XAUI		4
+#define MCX_ETHER_EXT_CAP_XLAUI		5
+#define MCX_ETHER_EXT_CAP_25G_AUI1	6
+#define MCX_ETHER_EXT_CAP_50G_AUI2	7
+#define MCX_ETHER_EXT_CAP_50G_AUI1	8
+#define MCX_ETHER_EXT_CAP_CAUI4		9
+#define MCX_ETHER_EXT_CAP_100G_AUI2	10
+#define MCX_ETHER_EXT_CAP_200G_AUI4	12
+#define MCX_ETHER_EXT_CAP_400G_AUI8	15
+
 #define MCX_MAX_CQE			32
 
 #define MCX_CMD_QUERY_HCA_CAP		0x100
@@ -406,11 +419,14 @@ struct mcx_reg_ptys {
 	uint8_t			rp_reserved2;
 	uint8_t			rp_proto_mask;
 #define MCX_REG_PTYS_PROTO_MASK_ETH		(1 << 2)
-	uint8_t			rp_reserved3[8];
+	uint8_t			rp_reserved3[4];
+	uint32_t		rp_ext_eth_proto_cap;
 	uint32_t		rp_eth_proto_cap;
-	uint8_t			rp_reserved4[8];
+	uint8_t			rp_reserved4[4];
+	uint32_t		rp_ext_eth_proto_admin;
 	uint32_t		rp_eth_proto_admin;
-	uint8_t			rp_reserved5[8];
+	uint8_t			rp_reserved5[4];
+	uint32_t		rp_ext_eth_proto_oper;
 	uint32_t		rp_eth_proto_oper;
 	uint8_t			rp_reserved6[24];
 } __packed __aligned(4);
@@ -2657,6 +2673,7 @@ static const struct pci_matchid mcx_devices[] = {
 	{ PCI_VENDOR_MELLANOX,	PCI_PRODUCT_MELLANOX_MT28800 },
 	{ PCI_VENDOR_MELLANOX,	PCI_PRODUCT_MELLANOX_MT28800VF },
 	{ PCI_VENDOR_MELLANOX,	PCI_PRODUCT_MELLANOX_MT28908 },
+	{ PCI_VENDOR_MELLANOX,	PCI_PRODUCT_MELLANOX_MT28908VF },
 	{ PCI_VENDOR_MELLANOX,	PCI_PRODUCT_MELLANOX_MT2892 },
 	{ PCI_VENDOR_MELLANOX,	PCI_PRODUCT_MELLANOX_MT2894 },
 };
@@ -2691,6 +2708,21 @@ static const struct mcx_eth_proto_capability mcx_eth_cap_map[] = {
 	[MCX_ETHER_CAP_50G_KR2]		= { IFM_50G_KR2,	IF_Gbps(50) },
 };
 
+static const struct mcx_eth_proto_capability mcx_ext_eth_cap_map[] = {
+	[MCX_ETHER_EXT_CAP_SGMII_100]	= { IFM_100_FX,		IF_Mbps(100) },
+	[MCX_ETHER_EXT_CAP_1000_X]	= { IFM_1000_SX,	IF_Gbps(1) },
+	[MCX_ETHER_EXT_CAP_5G_R]	= { IFM_5000_T,		IF_Gbps(5) },
+	[MCX_ETHER_EXT_CAP_XAUI]	= { IFM_10G_SFI,	IF_Gbps(10) },
+	[MCX_ETHER_EXT_CAP_XLAUI]	= { IFM_40G_XLPPI,	IF_Gbps(40) },
+	[MCX_ETHER_EXT_CAP_25G_AUI1]	= { 0 /*IFM_25G_AUI*/,	IF_Gbps(25) },
+	[MCX_ETHER_EXT_CAP_50G_AUI2]	= { 0 /*IFM_50G_AUI*/,	IF_Gbps(50) },
+	[MCX_ETHER_EXT_CAP_50G_AUI1]	= { 0 /*IFM_50G_AUI*/,	IF_Gbps(50) },
+	[MCX_ETHER_EXT_CAP_CAUI4]	= { 0 /*IFM_100G_AUI*/,	IF_Gbps(100) },
+	[MCX_ETHER_EXT_CAP_100G_AUI2]	= { 0 /*IFM_100G_AUI*/,	IF_Gbps(100) },
+	[MCX_ETHER_EXT_CAP_200G_AUI4]	= { 0 /*IFM_200G_AUI*/,	IF_Gbps(200) },
+	[MCX_ETHER_EXT_CAP_400G_AUI8]	= { 0 /*IFM_400G_AUI*/,	IF_Gbps(400) },
+};
+
 static int
 mcx_get_id(uint32_t val)
 {
@@ -7956,6 +7988,19 @@ mcx_media_add_types(struct mcx_softc *sc)
 
 		ifmedia_add(&sc->sc_media, IFM_ETHER | cap->cap_media, 0, NULL);
 	}
+
+	proto_cap = betoh32(ptys.rp_ext_eth_proto_cap);
+	for (i = 0; i < nitems(mcx_ext_eth_cap_map); i++) {
+		const struct mcx_eth_proto_capability *cap;
+		if (!ISSET(proto_cap, 1 << i))
+			continue;
+
+		cap = &mcx_ext_eth_cap_map[i];
+		if (cap->cap_media == 0)
+			continue;
+
+		ifmedia_add(&sc->sc_media, IFM_ETHER | cap->cap_media, 0, NULL);
+	}
 }
 
 static void
@@ -7965,6 +8010,7 @@ mcx_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
 	struct mcx_reg_ptys ptys;
 	int i;
 	uint32_t proto_oper;
+	uint32_t ext_proto_oper;
 	uint64_t media_oper;
 
 	memset(&ptys, 0, sizeof(ptys));
@@ -7979,6 +8025,7 @@ mcx_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
 	}
 
 	proto_oper = betoh32(ptys.rp_eth_proto_oper);
+	ext_proto_oper = betoh32(ptys.rp_ext_eth_proto_oper);
 
 	media_oper = 0;
 
@@ -7993,8 +8040,21 @@ mcx_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
 			media_oper = cap->cap_media;
 	}
 
+	if (media_oper == 0) {
+		for (i = 0; i < nitems(mcx_ext_eth_cap_map); i++) {
+			const struct mcx_eth_proto_capability *cap;
+			if (!ISSET(ext_proto_oper, 1 << i))
+				continue;
+
+			cap = &mcx_ext_eth_cap_map[i];
+
+			if (cap->cap_media != 0)
+				media_oper = cap->cap_media;
+		}
+	}
+
 	ifmr->ifm_status = IFM_AVALID;
-	if (proto_oper != 0) {
+	if ((proto_oper | ext_proto_oper) != 0) {
 		ifmr->ifm_status |= IFM_ACTIVE;
 		ifmr->ifm_active = IFM_ETHER | IFM_AUTO | media_oper;
 		/* txpause, rxpause, duplex? */
@@ -8010,6 +8070,7 @@ mcx_media_change(struct ifnet *ifp)
 	struct mcx_reg_ptys ptys;
 	struct mcx_reg_paos paos;
 	uint32_t media;
+	uint32_t ext_media;
 	int i, error;
 
 	if (IFM_TYPE(sc->sc_media.ifm_media) != IFM_ETHER)
@@ -8032,6 +8093,7 @@ mcx_media_change(struct ifnet *ifp)
 		}
 
 		media = betoh32(ptys.rp_eth_proto_cap);
+		ext_media = betoh32(ptys.rp_ext_eth_proto_cap);
 	} else {
 		/* map media type */
 		media = 0;
@@ -8045,6 +8107,17 @@ mcx_media_change(struct ifnet *ifp)
 				break;
 			}
 		}
+
+		for (i = 0; i < nitems(mcx_ext_eth_cap_map); i++) {
+			const struct  mcx_eth_proto_capability *cap;
+
+			cap = &mcx_ext_eth_cap_map[i];
+			if (cap->cap_media ==
+			    IFM_SUBTYPE(sc->sc_media.ifm_media)) {
+				media = (1 << i);
+				break;
+			}
+		}
 	}
 
 	/* disable the port */
@@ -8063,6 +8136,7 @@ mcx_media_change(struct ifnet *ifp)
 	ptys.rp_local_port = 1;
 	ptys.rp_proto_mask = MCX_REG_PTYS_PROTO_MASK_ETH;
 	ptys.rp_eth_proto_admin = htobe32(media);
+	ptys.rp_ext_eth_proto_admin = htobe32(ext_media);
 	if (mcx_access_hca_reg(sc, MCX_REG_PTYS, MCX_REG_OP_WRITE, &ptys,
 	    sizeof(ptys), MCX_CMDQ_SLOT_IOCTL) != 0) {
 		printf("%s: unable to set port media type/speed\n",
@@ -8107,10 +8181,11 @@ mcx_port_change(void *xsc)
 	if (mcx_access_hca_reg(sc, MCX_REG_PTYS, MCX_REG_OP_READ, &ptys,
 	    sizeof(ptys), slot) == 0) {
 		uint32_t proto_oper = betoh32(ptys.rp_eth_proto_oper);
+		uint32_t ext_proto_oper = betoh32(ptys.rp_ext_eth_proto_oper);
 		uint64_t baudrate = 0;
 		unsigned int i;
 
-		if (proto_oper != 0)
+		if ((proto_oper | ext_proto_oper) != 0)
 			link_state = LINK_STATE_FULL_DUPLEX;
 
 		for (i = 0; i < nitems(mcx_eth_cap_map); i++) {
@@ -8126,6 +8201,21 @@ mcx_port_change(void *xsc)
 			break;
 		}
 
+		if (baudrate == 0) {
+			for (i = 0; i < nitems(mcx_ext_eth_cap_map); i++) {
+				const struct mcx_eth_proto_capability *cap;
+				if (!ISSET(ext_proto_oper, 1 << i))
+					continue;
+
+				cap = &mcx_ext_eth_cap_map[i];
+				if (cap->cap_baudrate == 0)
+					continue;
+
+				baudrate = cap->cap_baudrate;
+				break;
+			}
+		}
+
 		ifp->if_baudrate = baudrate;
 	}