sync with OpenBSD -current
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parent
e58e794ac2
commit
729656abba
GPG key ID:
F42C07F07E2E35B7
61 changed files with 532 additions and 321 deletions
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@ -4249,7 +4249,6 @@ int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)
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drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, true);
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cancel_delayed_work_sync(&adev->delayed_init_work);
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flush_delayed_work(&adev->gfx.gfx_off_delay_work);
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amdgpu_ras_suspend(adev);
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@ -704,8 +704,15 @@ void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable)
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if (adev->gfx.gfx_off_req_count == 0 &&
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!adev->gfx.gfx_off_state) {
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schedule_delayed_work(&adev->gfx.gfx_off_delay_work,
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/* If going to s2idle, no need to wait */
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if (adev->in_s0ix) {
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if (!amdgpu_dpm_set_powergating_by_smu(adev,
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AMD_IP_BLOCK_TYPE_GFX, true))
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adev->gfx.gfx_off_state = true;
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} else {
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schedule_delayed_work(&adev->gfx.gfx_off_delay_work,
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delay);
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}
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}
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} else {
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if (adev->gfx.gfx_off_req_count == 0) {
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@ -204,6 +204,12 @@ static u32 cik_ih_get_wptr(struct amdgpu_device *adev,
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tmp = RREG32(mmIH_RB_CNTL);
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tmp |= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
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WREG32(mmIH_RB_CNTL, tmp);
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/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
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* can be detected.
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*/
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tmp &= ~IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
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WREG32(mmIH_RB_CNTL, tmp);
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}
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return (wptr & ih->ptr_mask);
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}
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@ -216,6 +216,11 @@ static u32 cz_ih_get_wptr(struct amdgpu_device *adev,
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tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
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WREG32(mmIH_RB_CNTL, tmp);
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/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
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* can be detected.
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*/
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tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
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WREG32(mmIH_RB_CNTL, tmp);
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out:
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return (wptr & ih->ptr_mask);
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@ -4020,8 +4020,6 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
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err = 0;
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adev->gfx.mec2_fw = NULL;
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}
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amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2);
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amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT);
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gfx_v10_0_check_fw_write_wait(adev);
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out:
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@ -215,6 +215,11 @@ static u32 iceland_ih_get_wptr(struct amdgpu_device *adev,
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tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
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WREG32(mmIH_RB_CNTL, tmp);
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/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
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* can be detected.
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*/
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tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
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WREG32(mmIH_RB_CNTL, tmp);
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out:
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return (wptr & ih->ptr_mask);
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@ -418,6 +418,12 @@ static u32 ih_v6_0_get_wptr(struct amdgpu_device *adev,
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tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
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tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
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WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
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/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
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* can be detected.
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*/
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tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
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WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
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out:
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return (wptr & ih->ptr_mask);
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}
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@ -418,6 +418,13 @@ static u32 ih_v6_1_get_wptr(struct amdgpu_device *adev,
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tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
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tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
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WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
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/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
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* can be detected.
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*/
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tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
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WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
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out:
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return (wptr & ih->ptr_mask);
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}
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@ -442,6 +442,12 @@ static u32 navi10_ih_get_wptr(struct amdgpu_device *adev,
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tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
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tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
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WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
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/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
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* can be detected.
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*/
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tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
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WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
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out:
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return (wptr & ih->ptr_mask);
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}
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@ -119,6 +119,12 @@ static u32 si_ih_get_wptr(struct amdgpu_device *adev,
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tmp = RREG32(IH_RB_CNTL);
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tmp |= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
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WREG32(IH_RB_CNTL, tmp);
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/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
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* can be detected.
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*/
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tmp &= ~IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
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WREG32(IH_RB_CNTL, tmp);
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}
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return (wptr & ih->ptr_mask);
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}
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@ -50,13 +50,13 @@ static const struct amd_ip_funcs soc21_common_ip_funcs;
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/* SOC21 */
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static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn0[] = {
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{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
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{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
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{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
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{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
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};
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static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn1[] = {
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{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
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{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
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{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
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};
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static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn0 = {
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@ -219,6 +219,12 @@ static u32 tonga_ih_get_wptr(struct amdgpu_device *adev,
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tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
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WREG32(mmIH_RB_CNTL, tmp);
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/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
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* can be detected.
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*/
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tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
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WREG32(mmIH_RB_CNTL, tmp);
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out:
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return (wptr & ih->ptr_mask);
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}
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@ -373,6 +373,12 @@ static u32 vega10_ih_get_wptr(struct amdgpu_device *adev,
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tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
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WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
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/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
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* can be detected.
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*/
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tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
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WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
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out:
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return (wptr & ih->ptr_mask);
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}
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@ -421,6 +421,12 @@ static u32 vega20_ih_get_wptr(struct amdgpu_device *adev,
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tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
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WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
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/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
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* can be detected.
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*/
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tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
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WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
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out:
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return (wptr & ih->ptr_mask);
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}
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