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sync with OpenBSD -current

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This commit is contained in:
purplerain 2024-02-27 05:02:43 +00:00
parent e58e794ac2
commit 729656abba
Signed by: purplerain
GPG key ID: F42C07F07E2E35B7
61 changed files with 532 additions and 321 deletions
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6
sys/dev/fdt/dwpcie.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: dwpcie.c,v 1.51 2024/02/03 10:37:26 kettenis Exp $ */
/* $OpenBSD: dwpcie.c,v 1.52 2024/02/26 21:41:24 kettenis Exp $ */
/*
* Copyright (c) 2018 Mark Kettenis <kettenis@openbsd.org>
*
@ -733,10 +733,6 @@ dwpcie_attach_deferred(struct device *self)
if (OF_getproplen(sc->sc_node, "msi-map") > 0)
pba.pba_flags |= PCI_FLAGS_MSIVEC_ENABLED;
/* XXX No working MSI on RK3588 yet. */
if (OF_is_compatible(sc->sc_node, "rockchip,rk3588-pcie"))
pba.pba_flags &= ~PCI_FLAGS_MSI_ENABLED;
pci_dopm = 1;
config_found(self, &pba, NULL);

175
sys/dev/fdt/if_dwqe_fdt.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: if_dwqe_fdt.c,v 1.17 2023/10/10 07:11:50 stsp Exp $ */
/* $OpenBSD: if_dwqe_fdt.c,v 1.18 2024/02/26 18:57:50 kettenis Exp $ */
/*
* Copyright (c) 2008, 2019 Mark Kettenis <kettenis@openbsd.org>
* Copyright (c) 2017, 2022 Patrick Wildt <patrick@blueri.se>
@ -73,6 +73,7 @@ void dwqe_setup_jh7110(struct dwqe_softc *);
void dwqe_mii_statchg_jh7110(struct device *);
void dwqe_setup_rk3568(struct dwqe_fdt_softc *);
void dwqe_mii_statchg_rk3568(struct device *);
void dwqe_setup_rk3588(struct dwqe_fdt_softc *);
void dwqe_mii_statchg_rk3588(struct device *);
const struct cfattach dwqe_fdt_ca = {
@ -114,10 +115,12 @@ dwqe_fdt_attach(struct device *parent, struct device *self, void *aux)
/* Decide GMAC id through address */
switch (faa->fa_reg[0].addr) {
case 0xfe2a0000: /* RK3568 */
case 0xfe1b0000: /* RK3588 */
case 0x16030000: /* JH7110 */
fsc->sc_gmac_id = 0;
break;
case 0xfe010000: /* RK3568 */
case 0xfe1c0000: /* RK3588 */
case 0x16040000: /* JH7110 */
fsc->sc_gmac_id = 1;
break;
@ -137,6 +140,8 @@ dwqe_fdt_attach(struct device *parent, struct device *self, void *aux)
sc->sc_phy_mode = DWQE_PHY_MODE_RGMII_TXID;
else if (strcmp(phy_mode, "rgmii-id") == 0)
sc->sc_phy_mode = DWQE_PHY_MODE_RGMII_ID;
else if (strcmp(phy_mode, "rmii") == 0)
sc->sc_phy_mode = DWQE_PHY_MODE_RMII;
else
sc->sc_phy_mode = DWQE_PHY_MODE_UNKNOWN;
@ -162,11 +167,17 @@ dwqe_fdt_attach(struct device *parent, struct device *self, void *aux)
if (OF_is_compatible(faa->fa_node, "starfive,jh7110-dwmac")) {
clock_enable(faa->fa_node, "tx");
clock_enable(faa->fa_node, "gtx");
} else if (OF_is_compatible(faa->fa_node, "rockchip,rk3568-gmac")) {
clock_enable(faa->fa_node, "mac_clk_rx");
clock_enable(faa->fa_node, "mac_clk_tx");
} else if (OF_is_compatible(faa->fa_node, "rockchip,rk3568-gmac") ||
OF_is_compatible(faa->fa_node, "rockchip,rk3588-gmac")) {
clock_enable(faa->fa_node, "aclk_mac");
clock_enable(faa->fa_node, "pclk_mac");
clock_enable(faa->fa_node, "mac_clk_tx");
clock_enable(faa->fa_node, "clk_mac_speed");
if (strcmp(phy_mode, "rmii") == 0) {
clock_enable(faa->fa_node, "mac_clk_rx");
clock_enable(faa->fa_node, "clk_mac_ref");
clock_enable(faa->fa_node, "clk_mac_refout");
}
}
delay(5000);
@ -175,6 +186,8 @@ dwqe_fdt_attach(struct device *parent, struct device *self, void *aux)
dwqe_setup_jh7110(sc);
else if (OF_is_compatible(faa->fa_node, "rockchip,rk3568-gmac"))
dwqe_setup_rk3568(fsc);
else if (OF_is_compatible(faa->fa_node, "rockchip,rk3588-gmac"))
dwqe_setup_rk3588(fsc);
/* Power up PHY. */
phy_supply = OF_getpropint(faa->fa_node, "phy-supply", 0);
@ -329,6 +342,26 @@ dwqe_reset_phy(struct dwqe_softc *sc, uint32_t phy)
#define RK3568_GMAC_TXCLK_DLY_SET(_v) ((1 << 0) << 16 | ((_v) << 0))
#define RK3568_GMAC_RXCLK_DLY_SET(_v) ((1 << 1) << 16 | ((_v) << 1))
/* RK3588 registers */
#define RK3588_GRF_GMAC_CON7 0x031c
#define RK3588_GMACx_RXCLK_DLY_ENA(id) ((1 << (2 * (id) + 3)) << 16 | (1 << (2 * (id) + 3)))
#define RK3588_GMACx_TXCLK_DLY_ENA(id) ((1 << (2 * (id) + 2)) << 16 | (1 << (2 * (id) + 2)))
#define RK3588_GRF_GMAC_CON8 0x0320
#define RK3588_GRF_GMAC_CON9 0x0324
#define RK3588_GMAC_CLK_RX_DL_CFG(val) ((0x7f << 8) << 16 | ((val) << 8))
#define RK3588_GMAC_CLK_TX_DL_CFG(val) ((0x7f << 0) << 16 | ((val) << 0))
#define RK3588_PHP_GRF_GMAC_CON0 0x0008
#define RK3588_GMACx_PHY_INTF_SEL_RGMII(id) ((0x7 << (6 * (id) + 3)) << 16 | (0x1 << (6 * (id) + 3)))
#define RK3588_GMACx_PHY_INTF_SEL_RMII(id) ((0x7 << (6 * (id) + 3)) << 16 | (0x4 << (6 * (id) + 3)))
#define RK3588_PHP_GRF_CLK_CON1 0x0070
#define RK3588_RMII_MODE_GMACx_RMII(id) ((0x1 << (5 * (id))) << 16 | (0x1 << (5 * (id))))
#define RK3588_RMII_MODE_GMACx_RGMII(id) ((0x1 << (5 * (id))) << 16 | (0x0 << (5 * (id))))
#define RK3588_MII_TX_CLK_SEL_RMII_2_5(id) ((0x3 << (5 * (id) + 2)) << 16 | (0x1 << (5 * (id) + 2)))
#define RK3588_MII_TX_CLK_SEL_RMII_25(id) ((0x3 << (5 * (id) + 2)) << 16 | (0x0 << (5 * (id) + 2)))
#define RK3588_MII_TX_CLK_SEL_RGMII_2_5(id) ((0x3 << (5 * (id) + 2)) << 16 | (0x2 << (5 * (id) + 2)))
#define RK3588_MII_TX_CLK_SEL_RGMII_25(id) ((0x3 << (5 * (id) + 2)) << 16 | (0x3 << (5 * (id) + 2)))
#define RK3588_MII_TX_CLK_SEL_RGMII_125(id) ((0x3 << (5 * (id) + 2)) << 16 | (0x0 << (5 * (id) + 2)))
void dwqe_mii_statchg_jh7110_task(void *);
void dwqe_mii_statchg_rk3568_task(void *);
@ -410,7 +443,6 @@ void
dwqe_setup_rk3568(struct dwqe_fdt_softc *fsc)
{
struct dwqe_softc *sc = &fsc->sc_sc;
char phy_mode[32];
struct regmap *rm;
uint32_t grf;
int tx_delay, rx_delay;
@ -421,30 +453,35 @@ dwqe_setup_rk3568(struct dwqe_fdt_softc *fsc)
if (rm == NULL)
return;
if (OF_getprop(sc->sc_node, "phy-mode",
phy_mode, sizeof(phy_mode)) <= 0)
switch (sc->sc_phy_mode) {
case DWQE_PHY_MODE_RGMII:
case DWQE_PHY_MODE_RGMII_ID:
case DWQE_PHY_MODE_RGMII_RXID:
case DWQE_PHY_MODE_RGMII_TXID:
iface = RK3568_GMAC_PHY_INTF_SEL_RGMII;
break;
case DWQE_PHY_MODE_RMII:
iface = RK3568_GMAC_PHY_INTF_SEL_RMII;
break;
default:
return;
}
tx_delay = OF_getpropint(sc->sc_node, "tx_delay", 0x30);
rx_delay = OF_getpropint(sc->sc_node, "rx_delay", 0x10);
if (strcmp(phy_mode, "rgmii") == 0) {
iface = RK3568_GMAC_PHY_INTF_SEL_RGMII;
} else if (strcmp(phy_mode, "rgmii-id") == 0) {
iface = RK3568_GMAC_PHY_INTF_SEL_RGMII;
/* id is "internal delay" */
switch (sc->sc_phy_mode) {
case DWQE_PHY_MODE_RGMII_ID:
tx_delay = rx_delay = 0;
} else if (strcmp(phy_mode, "rgmii-rxid") == 0) {
iface = RK3568_GMAC_PHY_INTF_SEL_RGMII;
break;
case DWQE_PHY_MODE_RGMII_RXID:
rx_delay = 0;
} else if (strcmp(phy_mode, "rgmii-txid") == 0) {
iface = RK3568_GMAC_PHY_INTF_SEL_RGMII;
break;
case DWQE_PHY_MODE_RGMII_TXID:
tx_delay = 0;
} else if (strcmp(phy_mode, "rmii") == 0) {
iface = RK3568_GMAC_PHY_INTF_SEL_RMII;
tx_delay = rx_delay = 0;
} else
return;
break;
default:
break;
}
/* Program clock delay lines. */
regmap_write_4(rm, RK3568_GRF_GMACx_CON0(fsc->sc_gmac_id),
@ -490,21 +527,99 @@ dwqe_mii_statchg_rk3568(struct device *self)
}
void
dwqe_mii_statchg_rk3588(struct device *self)
dwqe_setup_rk3588(struct dwqe_fdt_softc *fsc)
{
struct dwqe_softc *sc = (void *)self;
struct ifnet *ifp = &sc->sc_ac.ac_if;
struct dwqe_softc *sc = &fsc->sc_sc;
struct regmap *rm;
uint32_t grf;
uint32_t gmac_clk_sel = 0;
dwqe_mii_statchg(self);
struct regmap *php_rm;
uint32_t grf, php_grf;
int tx_delay, rx_delay;
uint32_t iface, clk;
grf = OF_getpropint(sc->sc_node, "rockchip,grf", 0);
rm = regmap_byphandle(grf);
if (rm == NULL)
return;
php_grf = OF_getpropint(sc->sc_node, "rockchip,php-grf", 0);
php_rm = regmap_byphandle(php_grf);
if (php_rm == NULL)
return;
switch (sc->sc_phy_mode) {
case DWQE_PHY_MODE_RGMII:
case DWQE_PHY_MODE_RGMII_ID:
case DWQE_PHY_MODE_RGMII_RXID:
case DWQE_PHY_MODE_RGMII_TXID:
iface = RK3588_GMACx_PHY_INTF_SEL_RGMII(fsc->sc_gmac_id);
clk = RK3588_RMII_MODE_GMACx_RGMII(fsc->sc_gmac_id);
sc->sc_clk_sel_2_5 =
RK3588_MII_TX_CLK_SEL_RGMII_2_5(fsc->sc_gmac_id);
sc->sc_clk_sel_25 =
RK3588_MII_TX_CLK_SEL_RGMII_25(fsc->sc_gmac_id);
sc->sc_clk_sel_125 =
RK3588_MII_TX_CLK_SEL_RGMII_125(fsc->sc_gmac_id);
break;
case DWQE_PHY_MODE_RMII:
iface = RK3588_GMACx_PHY_INTF_SEL_RMII(fsc->sc_gmac_id);
clk = RK3588_RMII_MODE_GMACx_RMII(fsc->sc_gmac_id);
sc->sc_clk_sel_2_5 =
RK3588_MII_TX_CLK_SEL_RMII_2_5(fsc->sc_gmac_id);
sc->sc_clk_sel_25 =
RK3588_MII_TX_CLK_SEL_RMII_25(fsc->sc_gmac_id);
break;
default:
return;
}
tx_delay = OF_getpropint(sc->sc_node, "tx_delay", 0x30);
rx_delay = OF_getpropint(sc->sc_node, "rx_delay", 0x10);
switch (sc->sc_phy_mode) {
case DWQE_PHY_MODE_RGMII_ID:
tx_delay = rx_delay = 0;
break;
case DWQE_PHY_MODE_RGMII_RXID:
rx_delay = 0;
break;
case DWQE_PHY_MODE_RGMII_TXID:
tx_delay = 0;
break;
default:
break;
}
/* Set interface and clock. */
regmap_write_4(php_rm, RK3588_PHP_GRF_GMAC_CON0, iface);
regmap_write_4(php_rm, RK3588_PHP_GRF_CLK_CON1, clk);
/* Enable clock delay. */
regmap_write_4(rm, RK3588_GRF_GMAC_CON7,
RK3588_GMACx_TXCLK_DLY_ENA(fsc->sc_gmac_id) |
RK3588_GMACx_RXCLK_DLY_ENA(fsc->sc_gmac_id));
/* Program clock delay lines. */
regmap_write_4(rm, fsc->sc_gmac_id == 1 ?
RK3588_GRF_GMAC_CON9 : RK3588_GRF_GMAC_CON8,
RK3588_GMAC_CLK_TX_DL_CFG(tx_delay) |
RK3588_GMAC_CLK_RX_DL_CFG(rx_delay));
}
void
dwqe_mii_statchg_rk3588(struct device *self)
{
struct dwqe_softc *sc = (void *)self;
struct ifnet *ifp = &sc->sc_ac.ac_if;
struct regmap *php_rm;
uint32_t php_grf;
uint32_t gmac_clk_sel = 0;
dwqe_mii_statchg(self);
php_grf = OF_getpropint(sc->sc_node, "rockchip,php-grf", 0);
php_rm = regmap_byphandle(php_grf);
if (php_rm == NULL)
return;
switch (ifp->if_baudrate) {
case IF_Mbps(10):
gmac_clk_sel = sc->sc_clk_sel_2_5;
@ -517,5 +632,5 @@ dwqe_mii_statchg_rk3588(struct device *self)
break;
}
regmap_write_4(rm, sc->sc_clk_sel, gmac_clk_sel);
regmap_write_4(php_rm, RK3588_PHP_GRF_CLK_CON1, gmac_clk_sel);
}

15
sys/dev/fdt/rkclock.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: rkclock.c,v 1.84 2023/11/26 13:47:45 kettenis Exp $ */
/* $OpenBSD: rkclock.c,v 1.85 2024/02/26 18:54:25 kettenis Exp $ */
/*
* Copyright (c) 2017, 2018 Mark Kettenis <kettenis@openbsd.org>
*
@ -4107,6 +4107,11 @@ const struct rkclock rk3588_clocks[] = {
{ RK3588_CLK_GPU_SRC },
SET_PARENT
},
{
RK3588_CLK_GMAC_125M, RK3588_CRU_CLKSEL_CON(83),
SEL(15, 15), DIV(14, 8),
{ RK3588_PLL_GPLL, RK3588_PLL_CPLL }
},
{
RK3588_CCLK_SRC_SDIO, RK3588_CRU_CLKSEL_CON(172),
SEL(9, 8), DIV(7, 2),
@ -4444,6 +4449,14 @@ rk3588_reset(void *cookie, uint32_t *cells, int on)
uint32_t bit, mask, reg;
switch (idx) {
case RK3588_SRST_A_GMAC0:
reg = RK3588_CRU_SOFTRST_CON(32);
bit = 10;
break;
case RK3588_SRST_A_GMAC1:
reg = RK3588_CRU_SOFTRST_CON(32);
bit = 11;
break;
case RK3588_SRST_PCIE0_POWER_UP:
reg = RK3588_CRU_SOFTRST_CON(32);
bit = 13;

3
sys/dev/fdt/rkclock_clocks.h
View file

@ -458,6 +458,7 @@
#define RK3588_ACLK_LOW_TOP_ROOT 258
#define RK3588_CLK_GPU_SRC 261
#define RK3588_CLK_GPU 262
#define RK3588_CLK_GMAC_125M 310
#define RK3588_CCLK_SRC_SDIO 395
#define RK3588_ACLK_VOP_ROOT 600
#define RK3588_ACLK_VOP 605
@ -488,6 +489,8 @@
#define RK3588_PLL_SPLL 1022
#define RK3588_XIN24M 1023
#define RK3588_SRST_A_GMAC0 291
#define RK3588_SRST_A_GMAC1 292
#define RK3588_SRST_PCIE0_POWER_UP 294
#define RK3588_SRST_PCIE1_POWER_UP 295
#define RK3588_SRST_PCIE2_POWER_UP 296

3
sys/dev/ic/dwqevar.h
View file

@ -1,4 +1,4 @@
/* $OpenBSD: dwqevar.h,v 1.10 2023/11/11 16:50:25 stsp Exp $ */
/* $OpenBSD: dwqevar.h,v 1.11 2024/02/26 18:57:50 kettenis Exp $ */
/*
* Copyright (c) 2008, 2019 Mark Kettenis <kettenis@openbsd.org>
* Copyright (c) 2017, 2022 Patrick Wildt <patrick@blueri.se>
@ -18,6 +18,7 @@
enum dwqe_phy_mode {
DWQE_PHY_MODE_UNKNOWN,
DWQE_PHY_MODE_RMII,
DWQE_PHY_MODE_RGMII,
DWQE_PHY_MODE_RGMII_ID,
DWQE_PHY_MODE_RGMII_TXID,

1
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
View file

@ -4249,7 +4249,6 @@ int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)
drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, true);
cancel_delayed_work_sync(&adev->delayed_init_work);
flush_delayed_work(&adev->gfx.gfx_off_delay_work);
amdgpu_ras_suspend(adev);

9
sys/dev/pci/drm/amd/amdgpu/amdgpu_gfx.c
View file

@ -704,8 +704,15 @@ void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable)
if (adev->gfx.gfx_off_req_count == 0 &&
!adev->gfx.gfx_off_state) {
schedule_delayed_work(&adev->gfx.gfx_off_delay_work,
/* If going to s2idle, no need to wait */
if (adev->in_s0ix) {
if (!amdgpu_dpm_set_powergating_by_smu(adev,
AMD_IP_BLOCK_TYPE_GFX, true))
adev->gfx.gfx_off_state = true;
} else {
schedule_delayed_work(&adev->gfx.gfx_off_delay_work,
delay);
}
}
} else {
if (adev->gfx.gfx_off_req_count == 0) {

6
sys/dev/pci/drm/amd/amdgpu/cik_ih.c
View file

@ -204,6 +204,12 @@ static u32 cik_ih_get_wptr(struct amdgpu_device *adev,
tmp = RREG32(mmIH_RB_CNTL);
tmp |= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
WREG32(mmIH_RB_CNTL, tmp);
/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
* can be detected.
*/
tmp &= ~IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
WREG32(mmIH_RB_CNTL, tmp);
}
return (wptr & ih->ptr_mask);
}

5
sys/dev/pci/drm/amd/amdgpu/cz_ih.c
View file

@ -216,6 +216,11 @@ static u32 cz_ih_get_wptr(struct amdgpu_device *adev,
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
WREG32(mmIH_RB_CNTL, tmp);
/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
* can be detected.
*/
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
WREG32(mmIH_RB_CNTL, tmp);
out:
return (wptr & ih->ptr_mask);

2
sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
View file

@ -4020,8 +4020,6 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
err = 0;
adev->gfx.mec2_fw = NULL;
}
amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2);
amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT);
gfx_v10_0_check_fw_write_wait(adev);
out:

5
sys/dev/pci/drm/amd/amdgpu/iceland_ih.c
View file

@ -215,6 +215,11 @@ static u32 iceland_ih_get_wptr(struct amdgpu_device *adev,
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
WREG32(mmIH_RB_CNTL, tmp);
/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
* can be detected.
*/
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
WREG32(mmIH_RB_CNTL, tmp);
out:
return (wptr & ih->ptr_mask);

6
sys/dev/pci/drm/amd/amdgpu/ih_v6_0.c
View file

@ -418,6 +418,12 @@ static u32 ih_v6_0_get_wptr(struct amdgpu_device *adev,
tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
* can be detected.
*/
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
out:
return (wptr & ih->ptr_mask);
}

7
sys/dev/pci/drm/amd/amdgpu/ih_v6_1.c
View file

@ -418,6 +418,13 @@ static u32 ih_v6_1_get_wptr(struct amdgpu_device *adev,
tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
* can be detected.
*/
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
out:
return (wptr & ih->ptr_mask);
}

6
sys/dev/pci/drm/amd/amdgpu/navi10_ih.c
View file

@ -442,6 +442,12 @@ static u32 navi10_ih_get_wptr(struct amdgpu_device *adev,
tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
* can be detected.
*/
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
out:
return (wptr & ih->ptr_mask);
}

6
sys/dev/pci/drm/amd/amdgpu/si_ih.c
View file

@ -119,6 +119,12 @@ static u32 si_ih_get_wptr(struct amdgpu_device *adev,
tmp = RREG32(IH_RB_CNTL);
tmp |= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
WREG32(IH_RB_CNTL, tmp);
/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
* can be detected.
*/
tmp &= ~IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK;
WREG32(IH_RB_CNTL, tmp);
}
return (wptr & ih->ptr_mask);
}

4
sys/dev/pci/drm/amd/amdgpu/soc21.c
View file

@ -50,13 +50,13 @@ static const struct amd_ip_funcs soc21_common_ip_funcs;
/* SOC21 */
static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn0[] = {
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
};
static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn1[] = {
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
};
static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn0 = {

6
sys/dev/pci/drm/amd/amdgpu/tonga_ih.c
View file

@ -219,6 +219,12 @@ static u32 tonga_ih_get_wptr(struct amdgpu_device *adev,
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
WREG32(mmIH_RB_CNTL, tmp);
/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
* can be detected.
*/
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
WREG32(mmIH_RB_CNTL, tmp);
out:
return (wptr & ih->ptr_mask);
}

6
sys/dev/pci/drm/amd/amdgpu/vega10_ih.c
View file

@ -373,6 +373,12 @@ static u32 vega10_ih_get_wptr(struct amdgpu_device *adev,
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
* can be detected.
*/
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
out:
return (wptr & ih->ptr_mask);
}

6
sys/dev/pci/drm/amd/amdgpu/vega20_ih.c
View file

@ -421,6 +421,12 @@ static u32 vega20_ih_get_wptr(struct amdgpu_device *adev,
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
/* Unset the CLEAR_OVERFLOW bit immediately so new overflows
* can be detected.
*/
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
out:
return (wptr & ih->ptr_mask);
}

14
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
View file

@ -6076,7 +6076,9 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
if (recalculate_timing) {
freesync_mode = get_highest_refresh_rate_mode(aconnector, false);
drm_mode_copy(&saved_mode, &mode);
saved_mode.picture_aspect_ratio = mode.picture_aspect_ratio;
drm_mode_copy(&mode, freesync_mode);
mode.picture_aspect_ratio = saved_mode.picture_aspect_ratio;
} else {
decide_crtc_timing_for_drm_display_mode(
&mode, preferred_mode, scale);
@ -10364,11 +10366,13 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
goto fail;
}
ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars);
if (ret) {
DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n");
ret = -EINVAL;
goto fail;
if (dc_resource_is_dsc_encoding_supported(dc)) {
ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars);
if (ret) {
DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n");
ret = -EINVAL;
goto fail;
}
}
ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars);

5
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_training.c
View file

@ -517,6 +517,7 @@ enum link_training_result dp_check_link_loss_status(
{
enum link_training_result status = LINK_TRAINING_SUCCESS;
union lane_status lane_status;
union lane_align_status_updated dpcd_lane_status_updated;
uint8_t dpcd_buf[6] = {0};
uint32_t lane;
@ -532,10 +533,12 @@ enum link_training_result dp_check_link_loss_status(
* check lanes status
*/
lane_status.raw = dp_get_nibble_at_index(&dpcd_buf[2], lane);
dpcd_lane_status_updated.raw = dpcd_buf[4];
if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
!lane_status.bits.CR_DONE_0 ||
!lane_status.bits.SYMBOL_LOCKED_0) {
!lane_status.bits.SYMBOL_LOCKED_0 ||
!dp_is_interlane_aligned(dpcd_lane_status_updated)) {
/* if one of the channel equalization, clock
* recovery or symbol lock is dropped
* consider it as (link has been

2
sys/dev/pci/drm/drm_prime.c
View file

@ -849,7 +849,7 @@ struct sg_table *drm_prime_pages_to_sg(struct drm_device *dev,
if (max_segment == 0)
max_segment = UINT_MAX;
err = sg_alloc_table_from_pages_segment(sg, pages, nr_pages, 0,
nr_pages << PAGE_SHIFT,
(unsigned long)nr_pages << PAGE_SHIFT,
max_segment, GFP_KERNEL);
if (err) {
kfree(sg);

7
sys/dev/pci/if_iwx.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: if_iwx.c,v 1.181 2024/02/16 11:44:52 stsp Exp $ */
/* $OpenBSD: if_iwx.c,v 1.182 2024/02/26 18:00:09 stsp Exp $ */
/*
* Copyright (c) 2014, 2016 genua gmbh <info@genua.de>
@ -6085,13 +6085,12 @@ iwx_tx_fill_cmd(struct iwx_softc *sc, struct iwx_node *in,
} else if (sc->sc_rate_n_flags_version >= 2)
rate_flags |= IWX_RATE_MCS_LEGACY_OFDM_MSK;
rval = (rs->rs_rates[ni->ni_txrate] & IEEE80211_RATE_VAL);
if (sc->sc_rate_n_flags_version >= 2) {
if (rate_flags & IWX_RATE_MCS_LEGACY_OFDM_MSK) {
rate_flags |= (iwx_fw_rateidx_ofdm(rval) &
rate_flags |= (iwx_fw_rateidx_ofdm(rinfo->rate) &
IWX_RATE_LEGACY_RATE_MSK);
} else {
rate_flags |= (iwx_fw_rateidx_cck(rval) &
rate_flags |= (iwx_fw_rateidx_cck(rinfo->rate) &
IWX_RATE_LEGACY_RATE_MSK);
}
} else