sync code with last improvements from OpenBSD
This commit is contained in:
parent
256236394b
commit
6b03483410
GPG key ID:
F42C07F07E2E35B7
31 changed files with 409 additions and 280 deletions
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@ -1574,17 +1574,8 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
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u16 bridge_cfg2, gpu_cfg2;
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u32 max_lw, current_lw, tmp;
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pcie_capability_read_word(root, PCI_EXP_LNKCTL,
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&bridge_cfg);
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pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL,
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&gpu_cfg);
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tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;
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pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16);
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tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;
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pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL,
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tmp16);
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pcie_capability_set_word(root, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD);
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pcie_capability_set_word(adev->pdev, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD);
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tmp = RREG32_PCIE(ixPCIE_LC_STATUS1);
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max_lw = (tmp & PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK) >>
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@ -1637,21 +1628,14 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
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drm_msleep(100);
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/* linkctl */
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pcie_capability_read_word(root, PCI_EXP_LNKCTL,
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&tmp16);
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tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
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tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);
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pcie_capability_write_word(root, PCI_EXP_LNKCTL,
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tmp16);
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pcie_capability_read_word(adev->pdev,
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PCI_EXP_LNKCTL,
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&tmp16);
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tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
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tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);
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pcie_capability_write_word(adev->pdev,
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PCI_EXP_LNKCTL,
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tmp16);
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pcie_capability_clear_and_set_word(root, PCI_EXP_LNKCTL,
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PCI_EXP_LNKCTL_HAWD,
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bridge_cfg &
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PCI_EXP_LNKCTL_HAWD);
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pcie_capability_clear_and_set_word(adev->pdev, PCI_EXP_LNKCTL,
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PCI_EXP_LNKCTL_HAWD,
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gpu_cfg &
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PCI_EXP_LNKCTL_HAWD);
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/* linkctl2 */
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pcie_capability_read_word(root, PCI_EXP_LNKCTL2,
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@ -1229,6 +1229,9 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
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u16 cmd;
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int r;
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if (!IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT))
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return 0;
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/* Bypass for VF */
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if (amdgpu_sriov_vf(adev))
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return 0;
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@ -558,6 +558,7 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
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crtc = (struct drm_crtc *)minfo->crtcs[i];
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if (crtc && crtc->base.id == info->mode_crtc.id) {
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struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
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ui32 = amdgpu_crtc->crtc_id;
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found = 1;
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break;
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@ -576,7 +577,7 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
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if (ret)
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return ret;
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ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip)));
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ret = copy_to_user(out, &ip, min_t(size_t, size, sizeof(ip)));
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return ret ? -EFAULT : 0;
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}
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case AMDGPU_INFO_HW_IP_COUNT: {
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@ -722,17 +723,18 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
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? -EFAULT : 0;
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}
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case AMDGPU_INFO_READ_MMR_REG: {
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unsigned n, alloc_size;
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unsigned int n, alloc_size;
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uint32_t *regs;
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unsigned se_num = (info->read_mmr_reg.instance >>
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unsigned int se_num = (info->read_mmr_reg.instance >>
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AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
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AMDGPU_INFO_MMR_SE_INDEX_MASK;
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unsigned sh_num = (info->read_mmr_reg.instance >>
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unsigned int sh_num = (info->read_mmr_reg.instance >>
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AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
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AMDGPU_INFO_MMR_SH_INDEX_MASK;
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/* set full masks if the userspace set all bits
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* in the bitfields */
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* in the bitfields
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*/
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if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
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se_num = 0xffffffff;
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else if (se_num >= AMDGPU_GFX_MAX_SE)
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@ -856,7 +858,7 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
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return ret;
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}
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case AMDGPU_INFO_VCE_CLOCK_TABLE: {
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unsigned i;
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unsigned int i;
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struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
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struct amd_vce_state *vce_state;
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@ -2276,17 +2276,8 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
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u16 bridge_cfg2, gpu_cfg2;
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u32 max_lw, current_lw, tmp;
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pcie_capability_read_word(root, PCI_EXP_LNKCTL,
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&bridge_cfg);
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pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL,
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&gpu_cfg);
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tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;
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pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16);
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tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;
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pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL,
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tmp16);
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pcie_capability_set_word(root, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD);
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pcie_capability_set_word(adev->pdev, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD);
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tmp = RREG32_PCIE(PCIE_LC_STATUS1);
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max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT;
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@ -2331,21 +2322,14 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
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mdelay(100);
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pcie_capability_read_word(root, PCI_EXP_LNKCTL,
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&tmp16);
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tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
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tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);
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pcie_capability_write_word(root, PCI_EXP_LNKCTL,
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tmp16);
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pcie_capability_read_word(adev->pdev,
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PCI_EXP_LNKCTL,
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&tmp16);
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tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
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tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);
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pcie_capability_write_word(adev->pdev,
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PCI_EXP_LNKCTL,
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tmp16);
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pcie_capability_clear_and_set_word(root, PCI_EXP_LNKCTL,
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PCI_EXP_LNKCTL_HAWD,
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bridge_cfg &
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PCI_EXP_LNKCTL_HAWD);
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pcie_capability_clear_and_set_word(adev->pdev, PCI_EXP_LNKCTL,
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PCI_EXP_LNKCTL_HAWD,
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gpu_cfg &
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PCI_EXP_LNKCTL_HAWD);
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pcie_capability_read_word(root, PCI_EXP_LNKCTL2,
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&tmp16);
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@ -147,14 +147,15 @@ static int psp_v13_0_wait_for_bootloader(struct psp_context *psp)
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int ret;
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int retry_loop;
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/* Wait for bootloader to signify that it is ready having bit 31 of
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* C2PMSG_35 set to 1. All other bits are expected to be cleared.
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* If there is an error in processing command, bits[7:0] will be set.
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* This is applicable for PSP v13.0.6 and newer.
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*/
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for (retry_loop = 0; retry_loop < 10; retry_loop++) {
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/* Wait for bootloader to signify that is
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ready having bit 31 of C2PMSG_35 set to 1 */
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ret = psp_wait_for(psp,
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SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
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0x80000000,
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0x80000000,
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false);
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ret = psp_wait_for(
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psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
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0x80000000, 0xffffffff, false);
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if (ret == 0)
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return 0;
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