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sync code with last improvements from OpenBSD

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This commit is contained in:
purplerain 2023-09-13 16:41:13 +00:00
parent 256236394b
commit 6b03483410
Signed by: purplerain
GPG key ID: F42C07F07E2E35B7
31 changed files with 409 additions and 280 deletions
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36
sys/dev/pci/drm/amd/amdgpu/amdgpu_cik.c
View file

@ -1574,17 +1574,8 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
u16 bridge_cfg2, gpu_cfg2;
u32 max_lw, current_lw, tmp;
pcie_capability_read_word(root, PCI_EXP_LNKCTL,
&bridge_cfg);
pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL,
&gpu_cfg);
tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;
pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16);
tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;
pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL,
tmp16);
pcie_capability_set_word(root, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD);
pcie_capability_set_word(adev->pdev, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD);
tmp = RREG32_PCIE(ixPCIE_LC_STATUS1);
max_lw = (tmp & PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK) >>
@ -1637,21 +1628,14 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
drm_msleep(100);
/* linkctl */
pcie_capability_read_word(root, PCI_EXP_LNKCTL,
&tmp16);
tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);
pcie_capability_write_word(root, PCI_EXP_LNKCTL,
tmp16);
pcie_capability_read_word(adev->pdev,
PCI_EXP_LNKCTL,
&tmp16);
tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);
pcie_capability_write_word(adev->pdev,
PCI_EXP_LNKCTL,
tmp16);
pcie_capability_clear_and_set_word(root, PCI_EXP_LNKCTL,
PCI_EXP_LNKCTL_HAWD,
bridge_cfg &
PCI_EXP_LNKCTL_HAWD);
pcie_capability_clear_and_set_word(adev->pdev, PCI_EXP_LNKCTL,
PCI_EXP_LNKCTL_HAWD,
gpu_cfg &
PCI_EXP_LNKCTL_HAWD);
/* linkctl2 */
pcie_capability_read_word(root, PCI_EXP_LNKCTL2,

3
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
View file

@ -1229,6 +1229,9 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
u16 cmd;
int r;
if (!IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT))
return 0;
/* Bypass for VF */
if (amdgpu_sriov_vf(adev))
return 0;

14
sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c
View file

@ -558,6 +558,7 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
crtc = (struct drm_crtc *)minfo->crtcs[i];
if (crtc && crtc->base.id == info->mode_crtc.id) {
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
ui32 = amdgpu_crtc->crtc_id;
found = 1;
break;
@ -576,7 +577,7 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
if (ret)
return ret;
ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip)));
ret = copy_to_user(out, &ip, min_t(size_t, size, sizeof(ip)));
return ret ? -EFAULT : 0;
}
case AMDGPU_INFO_HW_IP_COUNT: {
@ -722,17 +723,18 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
? -EFAULT : 0;
}
case AMDGPU_INFO_READ_MMR_REG: {
unsigned n, alloc_size;
unsigned int n, alloc_size;
uint32_t *regs;
unsigned se_num = (info->read_mmr_reg.instance >>
unsigned int se_num = (info->read_mmr_reg.instance >>
AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
AMDGPU_INFO_MMR_SE_INDEX_MASK;
unsigned sh_num = (info->read_mmr_reg.instance >>
unsigned int sh_num = (info->read_mmr_reg.instance >>
AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
AMDGPU_INFO_MMR_SH_INDEX_MASK;
/* set full masks if the userspace set all bits
* in the bitfields */
* in the bitfields
*/
if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
se_num = 0xffffffff;
else if (se_num >= AMDGPU_GFX_MAX_SE)
@ -856,7 +858,7 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
return ret;
}
case AMDGPU_INFO_VCE_CLOCK_TABLE: {
unsigned i;
unsigned int i;
struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
struct amd_vce_state *vce_state;

36
sys/dev/pci/drm/amd/amdgpu/amdgpu_si.c
View file

@ -2276,17 +2276,8 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
u16 bridge_cfg2, gpu_cfg2;
u32 max_lw, current_lw, tmp;
pcie_capability_read_word(root, PCI_EXP_LNKCTL,
&bridge_cfg);
pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL,
&gpu_cfg);
tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;
pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16);
tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;
pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL,
tmp16);
pcie_capability_set_word(root, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD);
pcie_capability_set_word(adev->pdev, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD);
tmp = RREG32_PCIE(PCIE_LC_STATUS1);
max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT;
@ -2331,21 +2322,14 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
mdelay(100);
pcie_capability_read_word(root, PCI_EXP_LNKCTL,
&tmp16);
tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);
pcie_capability_write_word(root, PCI_EXP_LNKCTL,
tmp16);
pcie_capability_read_word(adev->pdev,
PCI_EXP_LNKCTL,
&tmp16);
tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);
pcie_capability_write_word(adev->pdev,
PCI_EXP_LNKCTL,
tmp16);
pcie_capability_clear_and_set_word(root, PCI_EXP_LNKCTL,
PCI_EXP_LNKCTL_HAWD,
bridge_cfg &
PCI_EXP_LNKCTL_HAWD);
pcie_capability_clear_and_set_word(adev->pdev, PCI_EXP_LNKCTL,
PCI_EXP_LNKCTL_HAWD,
gpu_cfg &
PCI_EXP_LNKCTL_HAWD);
pcie_capability_read_word(root, PCI_EXP_LNKCTL2,
&tmp16);

15
sys/dev/pci/drm/amd/amdgpu/psp_v13_0.c
View file

@ -147,14 +147,15 @@ static int psp_v13_0_wait_for_bootloader(struct psp_context *psp)
int ret;
int retry_loop;
/* Wait for bootloader to signify that it is ready having bit 31 of
* C2PMSG_35 set to 1. All other bits are expected to be cleared.
* If there is an error in processing command, bits[7:0] will be set.
* This is applicable for PSP v13.0.6 and newer.
*/
for (retry_loop = 0; retry_loop < 10; retry_loop++) {
/* Wait for bootloader to signify that is
ready having bit 31 of C2PMSG_35 set to 1 */
ret = psp_wait_for(psp,
SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
0x80000000,
0x80000000,
false);
ret = psp_wait_for(
psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
0x80000000, 0xffffffff, false);
if (ret == 0)
return 0;

36
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
View file

@ -5923,8 +5923,7 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
*/
DRM_DEBUG_DRIVER("No preferred mode found\n");
} else {
recalculate_timing = amdgpu_freesync_vid_mode &&
is_freesync_video_mode(&mode, aconnector);
recalculate_timing = is_freesync_video_mode(&mode, aconnector);
if (recalculate_timing) {
freesync_mode = get_highest_refresh_rate_mode(aconnector, false);
drm_mode_copy(&saved_mode, &mode);
@ -7018,7 +7017,7 @@ static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connect
struct amdgpu_dm_connector *amdgpu_dm_connector =
to_amdgpu_dm_connector(connector);
if (!(amdgpu_freesync_vid_mode && edid))
if (!edid)
return;
if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
@ -7863,10 +7862,12 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
* fast updates.
*/
if (crtc->state->async_flip &&
acrtc_state->update_type != UPDATE_TYPE_FAST)
(acrtc_state->update_type != UPDATE_TYPE_FAST ||
get_mem_type(old_plane_state->fb) != get_mem_type(fb)))
drm_warn_once(state->dev,
"[PLANE:%d:%s] async flip with non-fast update\n",
plane->base.id, plane->name);
bundle->flip_addrs[planes_count].flip_immediate =
crtc->state->async_flip &&
acrtc_state->update_type == UPDATE_TYPE_FAST &&
@ -9026,8 +9027,7 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
* TODO: Refactor this function to allow this check to work
* in all conditions.
*/
if (amdgpu_freesync_vid_mode &&
dm_new_crtc_state->stream &&
if (dm_new_crtc_state->stream &&
is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state))
goto skip_modeset;
@ -9067,7 +9067,7 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
}
/* Now check if we should set freesync video mode */
if (amdgpu_freesync_vid_mode && dm_new_crtc_state->stream &&
if (dm_new_crtc_state->stream &&
dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream) &&
is_timing_unchanged_for_freesync(new_crtc_state,
@ -9080,7 +9080,7 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
set_freesync_fixed_config(dm_new_crtc_state);
goto skip_modeset;
} else if (amdgpu_freesync_vid_mode && aconnector &&
} else if (aconnector &&
is_freesync_video_mode(&new_crtc_state->mode,
aconnector)) {
struct drm_display_mode *high_mode;
@ -9819,6 +9819,11 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
/* Remove exiting planes if they are modified */
for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
if (old_plane_state->fb && new_plane_state->fb &&
get_mem_type(old_plane_state->fb) !=
get_mem_type(new_plane_state->fb))
lock_and_validation_needed = true;
ret = dm_update_plane_state(dc, state, plane,
old_plane_state,
new_plane_state,
@ -10070,9 +10075,20 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
struct dm_crtc_state *dm_new_crtc_state =
to_dm_crtc_state(new_crtc_state);
/*
* Only allow async flips for fast updates that don't change
* the FB pitch, the DCC state, rotation, etc.
*/
if (new_crtc_state->async_flip && lock_and_validation_needed) {
drm_dbg_atomic(crtc->dev,
"[CRTC:%d:%s] async flips are only supported for fast updates\n",
crtc->base.id, crtc->name);
ret = -EINVAL;
goto fail;
}
dm_new_crtc_state->update_type = lock_and_validation_needed ?
UPDATE_TYPE_FULL :
UPDATE_TYPE_FAST;
UPDATE_TYPE_FULL : UPDATE_TYPE_FAST;
}
/* Must be success */

12
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
View file

@ -406,18 +406,6 @@ static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
return -EINVAL;
}
/*
* Only allow async flips for fast updates that don't change the FB
* pitch, the DCC state, rotation, etc.
*/
if (crtc_state->async_flip &&
dm_crtc_state->update_type != UPDATE_TYPE_FAST) {
drm_dbg_atomic(crtc->dev,
"[CRTC:%d:%s] async flips are only supported for fast updates\n",
crtc->base.id, crtc->name);
return -EINVAL;
}
/* In some use cases, like reset, no stream is attached */
if (!dm_crtc_state->stream)
return 0;

20
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c
View file

@ -32,6 +32,7 @@
#define MAX_INSTANCE 6
#define MAX_SEGMENT 6
#define SMU_REGISTER_WRITE_RETRY_COUNT 5
struct IP_BASE_INSTANCE
{
@ -134,6 +135,8 @@ static int dcn315_smu_send_msg_with_param(
unsigned int msg_id, unsigned int param)
{
uint32_t result;
uint32_t i = 0;
uint32_t read_back_data;
result = dcn315_smu_wait_for_response(clk_mgr, 10, 200000);
@ -150,10 +153,19 @@ static int dcn315_smu_send_msg_with_param(
/* Set the parameter register for the SMU message, unit is Mhz */
REG_WRITE(MP1_SMN_C2PMSG_37, param);
/* Trigger the message transaction by writing the message ID */
generic_write_indirect_reg(CTX,
REG_NBIO(RSMU_INDEX), REG_NBIO(RSMU_DATA),
mmMP1_C2PMSG_3, msg_id);
for (i = 0; i < SMU_REGISTER_WRITE_RETRY_COUNT; i++) {
/* Trigger the message transaction by writing the message ID */
generic_write_indirect_reg(CTX,
REG_NBIO(RSMU_INDEX), REG_NBIO(RSMU_DATA),
mmMP1_C2PMSG_3, msg_id);
read_back_data = generic_read_indirect_reg(CTX,
REG_NBIO(RSMU_INDEX), REG_NBIO(RSMU_DATA),
mmMP1_C2PMSG_3);
if (read_back_data == msg_id)
break;
udelay(2);
smu_print("SMU msg id write fail %x times. \n", i + 1);
}
result = dcn315_smu_wait_for_response(clk_mgr, 10, 200000);

3
sys/dev/pci/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
View file

@ -1813,10 +1813,13 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)
hws->funcs.edp_backlight_control(edp_link_with_sink, false);
}
/*resume from S3, no vbios posting, no need to power down again*/
clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);
power_down_all_hw_blocks(dc);
disable_vga_and_power_gate_all_controllers(dc);
if (edp_link_with_sink && !keep_edp_vdd_on)
dc->hwss.edp_power_control(edp_link_with_sink, false);
clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);
}
bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 1);
}

1
sys/dev/pci/drm/amd/display/dc/dcn301/dcn301_init.c
View file

@ -75,6 +75,7 @@ static const struct hw_sequencer_funcs dcn301_funcs = {
.get_hw_state = dcn10_get_hw_state,
.clear_status_bits = dcn10_clear_status_bits,
.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
.edp_backlight_control = dce110_edp_backlight_control,
.edp_power_control = dce110_edp_power_control,
.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
.set_cursor_position = dcn10_set_cursor_position,

3
sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_dccg.c
View file

@ -84,7 +84,8 @@ static enum phyd32clk_clock_source get_phy_mux_symclk(
struct dcn_dccg *dccg_dcn,
enum phyd32clk_clock_source src)
{
if (dccg_dcn->base.ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) {
if (dccg_dcn->base.ctx->asic_id.chip_family == FAMILY_YELLOW_CARP &&
dccg_dcn->base.ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) {
if (src == PHYD32CLKC)
src = PHYD32CLKF;
if (src == PHYD32CLKD)

2
sys/dev/pci/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
View file

@ -32,7 +32,7 @@
#include "dml/display_mode_vba.h"
struct _vcs_dpi_ip_params_st dcn3_14_ip = {
.VBlankNomDefaultUS = 800,
.VBlankNomDefaultUS = 668,
.gpuvm_enable = 1,
.gpuvm_max_page_table_levels = 1,
.hostvm_enable = 1,

10
sys/dev/pci/drm/amd/pm/amdgpu_pm.c
View file

@ -2074,15 +2074,19 @@ static int amdgpu_device_attr_create(struct amdgpu_device *adev,
uint32_t mask, struct list_head *attr_list)
{
int ret = 0;
struct device_attribute *dev_attr = &attr->dev_attr;
const char *name = dev_attr->attr.name;
enum amdgpu_device_attr_states attr_states = ATTR_STATE_SUPPORTED;
struct amdgpu_device_attr_entry *attr_entry;
struct device_attribute *dev_attr;
const char *name;
int (*attr_update)(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
uint32_t mask, enum amdgpu_device_attr_states *states) = default_attr_update;
BUG_ON(!attr);
if (!attr)
return -EINVAL;
dev_attr = &attr->dev_attr;
name = dev_attr->attr.name;
attr_update = attr->attr_update ? attr->attr_update : default_attr_update;

2
sys/dev/pci/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
View file

@ -1307,7 +1307,7 @@ static ssize_t smu_v13_0_0_get_gpu_metrics(struct smu_context *smu,
gpu_metrics->average_vclk1_frequency = metrics->AverageVclk1Frequency;
gpu_metrics->average_dclk1_frequency = metrics->AverageDclk1Frequency;
gpu_metrics->current_gfxclk = metrics->CurrClock[PPCLK_GFXCLK];
gpu_metrics->current_gfxclk = gpu_metrics->average_gfxclk_frequency;
gpu_metrics->current_socclk = metrics->CurrClock[PPCLK_SOCCLK];
gpu_metrics->current_uclk = metrics->CurrClock[PPCLK_UCLK];
gpu_metrics->current_vclk0 = metrics->CurrClock[PPCLK_VCLK_0];

2
sys/dev/pci/drm/include/drm/drm_device.h
View file

@ -2,7 +2,7 @@
#define _DRM_DEVICE_H_
#include <sys/types.h>
#include <sys/selinfo.h>
#include <sys/event.h>
#include <linux/list.h>
#include <linux/kref.h>

23
sys/dev/pci/drm/include/linux/pci.h
View file

@ -1,4 +1,4 @@
/* $OpenBSD: pci.h,v 1.13 2023/01/01 01:34:58 jsg Exp $ */
/* $OpenBSD: pci.h,v 1.14 2023/09/13 12:31:49 jsg Exp $ */
/*
* Copyright (c) 2015 Mark Kettenis
*
@ -305,6 +305,27 @@ pcie_capability_write_word(struct pci_dev *pdev, int off, u16 val)
return 0;
}
static inline int
pcie_capability_set_word(struct pci_dev *pdev, int off, u16 val)
{
u16 r;
pcie_capability_read_word(pdev, off, &r);
r |= val;
pcie_capability_write_word(pdev, off, r);
return 0;
}
static inline int
pcie_capability_clear_and_set_word(struct pci_dev *pdev, int off, u16 c, u16 s)
{
u16 r;
pcie_capability_read_word(pdev, off, &r);
r &= ~c;
r |= s;
pcie_capability_write_word(pdev, off, r);
return 0;
}
static inline int
pcie_get_readrq(struct pci_dev *pdev)
{

36
sys/dev/pci/drm/radeon/cik.c
View file

@ -9536,17 +9536,8 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev)
u16 bridge_cfg2, gpu_cfg2;
u32 max_lw, current_lw, tmp;
pcie_capability_read_word(root, PCI_EXP_LNKCTL,
&bridge_cfg);
pcie_capability_read_word(rdev->pdev, PCI_EXP_LNKCTL,
&gpu_cfg);
tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;
pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16);
tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;
pcie_capability_write_word(rdev->pdev, PCI_EXP_LNKCTL,
tmp16);
pcie_capability_set_word(root, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD);
pcie_capability_set_word(rdev->pdev, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD);
tmp = RREG32_PCIE_PORT(PCIE_LC_STATUS1);
max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT;
@ -9593,21 +9584,14 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev)
drm_msleep(100);
/* linkctl */
pcie_capability_read_word(root, PCI_EXP_LNKCTL,
&tmp16);
tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);
pcie_capability_write_word(root, PCI_EXP_LNKCTL,
tmp16);
pcie_capability_read_word(rdev->pdev,
PCI_EXP_LNKCTL,
&tmp16);
tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);
pcie_capability_write_word(rdev->pdev,
PCI_EXP_LNKCTL,
tmp16);
pcie_capability_clear_and_set_word(root, PCI_EXP_LNKCTL,
PCI_EXP_LNKCTL_HAWD,
bridge_cfg &
PCI_EXP_LNKCTL_HAWD);
pcie_capability_clear_and_set_word(rdev->pdev, PCI_EXP_LNKCTL,
PCI_EXP_LNKCTL_HAWD,
gpu_cfg &
PCI_EXP_LNKCTL_HAWD);
/* linkctl2 */
pcie_capability_read_word(root, PCI_EXP_LNKCTL2,

3
sys/dev/pci/drm/radeon/radeon_combios.c
View file

@ -1500,7 +1500,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
} else if (of_machine_is_compatible("PowerMac3,5")) {
/* PowerMac G4 Silver radeon 7500 */
rdev->mode_info.connector_table = CT_MAC_G4_SILVER;
} else if (of_machine_is_compatible("PowerMac4,4")) {
} else if (of_machine_is_compatible("PowerMac4,4") ||
of_machine_is_compatible("PowerMac6,4")) {
/* emac */
rdev->mode_info.connector_table = CT_EMAC;
} else if (of_machine_is_compatible("PowerMac10,1")) {

37
sys/dev/pci/drm/radeon/si.c
View file

@ -7133,17 +7133,8 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev)
u16 bridge_cfg2, gpu_cfg2;
u32 max_lw, current_lw, tmp;
pcie_capability_read_word(root, PCI_EXP_LNKCTL,
&bridge_cfg);
pcie_capability_read_word(rdev->pdev, PCI_EXP_LNKCTL,
&gpu_cfg);
tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;
pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16);
tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;
pcie_capability_write_word(rdev->pdev, PCI_EXP_LNKCTL,
tmp16);
pcie_capability_set_word(root, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD);
pcie_capability_set_word(rdev->pdev, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD);
tmp = RREG32_PCIE(PCIE_LC_STATUS1);
max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT;
@ -7190,22 +7181,14 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev)
drm_msleep(100);
/* linkctl */
pcie_capability_read_word(root, PCI_EXP_LNKCTL,
&tmp16);
tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);
pcie_capability_write_word(root,
PCI_EXP_LNKCTL,
tmp16);
pcie_capability_read_word(rdev->pdev,
PCI_EXP_LNKCTL,
&tmp16);
tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);
pcie_capability_write_word(rdev->pdev,
PCI_EXP_LNKCTL,
tmp16);
pcie_capability_clear_and_set_word(root, PCI_EXP_LNKCTL,
PCI_EXP_LNKCTL_HAWD,
bridge_cfg &
PCI_EXP_LNKCTL_HAWD);
pcie_capability_clear_and_set_word(rdev->pdev, PCI_EXP_LNKCTL,
PCI_EXP_LNKCTL_HAWD,
gpu_cfg &
PCI_EXP_LNKCTL_HAWD);
/* linkctl2 */
pcie_capability_read_word(root, PCI_EXP_LNKCTL2,