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This commit is contained in:
parent
f609457dcf
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62073e0295
GPG key ID:
F42C07F07E2E35B7
318 changed files with 8112 additions and 4346 deletions
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@ -1,5 +1,5 @@
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/*
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* Copyright 2006-2007 Advanced Micro Devices, Inc.
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* Copyright 2006-2007 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@ -37,13 +37,13 @@
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#define GRAPH_OBJECT_TYPE_CONNECTOR 0x3
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#define GRAPH_OBJECT_TYPE_ROUTER 0x4
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/* deleted */
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#define GRAPH_OBJECT_TYPE_DISPLAY_PATH 0x6
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#define GRAPH_OBJECT_TYPE_DISPLAY_PATH 0x6
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#define GRAPH_OBJECT_TYPE_GENERIC 0x7
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/****************************************************/
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/* Encoder Object ID Definition */
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/****************************************************/
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#define ENCODER_OBJECT_ID_NONE 0x00
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#define ENCODER_OBJECT_ID_NONE 0x00
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/* Radeon Class Display Hardware */
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#define ENCODER_OBJECT_ID_INTERNAL_LVDS 0x01
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@ -96,7 +96,7 @@
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/****************************************************/
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/* Connector Object ID Definition */
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/****************************************************/
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#define CONNECTOR_OBJECT_ID_NONE 0x00
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#define CONNECTOR_OBJECT_ID_NONE 0x00
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#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I 0x01
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#define CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I 0x02
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#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D 0x03
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@ -158,7 +158,7 @@
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#define RESERVED1_ID_MASK 0x0800
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#define OBJECT_TYPE_MASK 0x7000
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#define RESERVED2_ID_MASK 0x8000
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#define OBJECT_ID_SHIFT 0x00
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#define ENUM_ID_SHIFT 0x08
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#define OBJECT_TYPE_SHIFT 0x0C
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@ -179,14 +179,14 @@
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/* Encoder Object ID definition - Shared with BIOS */
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/****************************************************/
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/*
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#define ENCODER_INTERNAL_LVDS_ENUM_ID1 0x2101
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#define ENCODER_INTERNAL_LVDS_ENUM_ID1 0x2101
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#define ENCODER_INTERNAL_TMDS1_ENUM_ID1 0x2102
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#define ENCODER_INTERNAL_TMDS2_ENUM_ID1 0x2103
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#define ENCODER_INTERNAL_DAC1_ENUM_ID1 0x2104
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#define ENCODER_INTERNAL_DAC2_ENUM_ID1 0x2105
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#define ENCODER_INTERNAL_SDVOA_ENUM_ID1 0x2106
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#define ENCODER_INTERNAL_SDVOB_ENUM_ID1 0x2107
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#define ENCODER_SIL170B_ENUM_ID1 0x2108
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#define ENCODER_SIL170B_ENUM_ID1 0x2108
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#define ENCODER_CH7303_ENUM_ID1 0x2109
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#define ENCODER_CH7301_ENUM_ID1 0x210A
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#define ENCODER_INTERNAL_DVO1_ENUM_ID1 0x210B
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@ -200,8 +200,8 @@
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#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1 0x2113
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#define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1 0x2114
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#define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1 0x2115
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#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 0x2116
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#define ENCODER_SI178_ENUM_ID1 0x2117
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#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 0x2116
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#define ENCODER_SI178_ENUM_ID1 0x2117
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#define ENCODER_MVPU_FPGA_ENUM_ID1 0x2118
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#define ENCODER_INTERNAL_DDI_ENUM_ID1 0x2119
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#define ENCODER_VT1625_ENUM_ID1 0x211A
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@ -316,7 +316,7 @@
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#define ENCODER_SI178_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
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GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
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ENCODER_OBJECT_ID_SI178 << OBJECT_ID_SHIFT)
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ENCODER_OBJECT_ID_SI178 << OBJECT_ID_SHIFT)
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#define ENCODER_MVPU_FPGA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
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GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
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@ -324,7 +324,7 @@
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#define ENCODER_INTERNAL_DDI_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
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GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
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ENCODER_OBJECT_ID_INTERNAL_DDI << OBJECT_ID_SHIFT)
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ENCODER_OBJECT_ID_INTERNAL_DDI << OBJECT_ID_SHIFT)
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#define ENCODER_VT1625_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
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GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
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@ -352,7 +352,7 @@
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#define ENCODER_INTERNAL_KLDSCP_LVTMA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
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GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
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ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA << OBJECT_ID_SHIFT)
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ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA << OBJECT_ID_SHIFT)
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#define ENCODER_INTERNAL_UNIPHY1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
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GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
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@ -35,6 +35,7 @@
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#include <linux/devcoredump.h>
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#include <generated/utsrelease.h>
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#include <linux/pci-p2pdma.h>
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#include <linux/apple-gmux.h>
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#include <drm/drm_aperture.h>
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#include <drm/drm_atomic_helper.h>
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@ -4023,12 +4024,15 @@ fence_driver_init:
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vga_client_register(adev->pdev, amdgpu_device_vga_set_decode);
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#endif
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if (amdgpu_device_supports_px(ddev)) {
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px = true;
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px = amdgpu_device_supports_px(ddev);
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if (px || (!pci_is_thunderbolt_attached(adev->pdev) &&
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apple_gmux_detect(NULL, NULL)))
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vga_switcheroo_register_client(adev->pdev,
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&amdgpu_switcheroo_ops, px);
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if (px)
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vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
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}
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if (adev->gmc.xgmi.pending_reset)
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queue_delayed_work(system_wq, &mgpu_info.delayed_reset_work,
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@ -4152,6 +4156,7 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev)
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void amdgpu_device_fini_sw(struct amdgpu_device *adev)
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{
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int idx;
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bool px;
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amdgpu_fence_driver_sw_fini(adev);
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amdgpu_device_ip_fini(adev);
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@ -4171,10 +4176,16 @@ void amdgpu_device_fini_sw(struct amdgpu_device *adev)
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kfree(adev->bios);
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adev->bios = NULL;
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if (amdgpu_device_supports_px(adev_to_drm(adev))) {
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px = amdgpu_device_supports_px(adev_to_drm(adev));
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if (px || (!pci_is_thunderbolt_attached(adev->pdev) &&
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apple_gmux_detect(NULL, NULL)))
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vga_switcheroo_unregister_client(adev->pdev);
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if (px)
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vga_switcheroo_fini_domain_pm_ops(adev->dev);
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}
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if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
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vga_client_unregister(adev->pdev);
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@ -6137,7 +6148,7 @@ int amdgpu_in_reset(struct amdgpu_device *adev)
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{
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return atomic_read(&adev->reset_domain->in_gpu_reset);
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}
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/**
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* amdgpu_device_halt() - bring hardware to some kind of halt state
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*
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@ -3418,7 +3418,7 @@ amdgpu_init_backlight(struct amdgpu_device *adev)
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if (bd == NULL)
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return;
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drm_connector_list_iter_begin(dev, &conn_iter);
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drm_for_each_connector_iter(connector, &conn_iter) {
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if (connector->connector_type != DRM_MODE_CONNECTOR_LVDS &&
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@ -1100,7 +1100,7 @@ void amdgpu_bo_fini(struct amdgpu_device *adev)
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arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
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#else
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drm_mtrr_del(0, adev->gmc.aper_base, adev->gmc.aper_size, DRM_MTRR_WC);
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#endif
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}
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drm_dev_exit(idx);
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@ -101,7 +101,7 @@ amdgpu_vm_it_iter_next(struct amdgpu_bo_va_mapping *node, uint64_t start,
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static void
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amdgpu_vm_it_remove(struct amdgpu_bo_va_mapping *node,
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struct rb_root_cached *root)
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struct rb_root_cached *root)
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{
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rb_erase_cached(&node->rb, root);
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}
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@ -1906,7 +1906,7 @@ static int gfx_v11_0_rlc_load_microcode(struct amdgpu_device *adev)
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if (version_minor == 3)
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gfx_v11_0_load_rlcp_rlcv_microcode(adev);
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}
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return 0;
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}
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@ -3348,7 +3348,7 @@ static int gfx_v11_0_cp_compute_load_microcode(struct amdgpu_device *adev)
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}
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memcpy(fw, fw_data, fw_size);
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amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
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amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
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@ -58,7 +58,7 @@ static int imu_v11_0_init_microcode(struct amdgpu_device *adev)
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imu_hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data;
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adev->gfx.imu_fw_version = le32_to_cpu(imu_hdr->header.ucode_version);
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//adev->gfx.imu_feature_version = le32_to_cpu(imu_hdr->ucode_feature_version);
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if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
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info = &adev->firmware.ucode[AMDGPU_UCODE_ID_IMU_I];
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info->ucode_id = AMDGPU_UCODE_ID_IMU_I;
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@ -240,9 +240,9 @@ static const struct imu_rlc_ram_golden imu_rlc_ram_golden_11[] =
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IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_BOT, 0x00000002, 0xe0000000),
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IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_TOP, 0x00000000, 0xe0000000),
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IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL2, 0x00020000, 0xe0000000),
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IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA0_UCODE_SELFLOAD_CONTROL, 0x00000210, 0),
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IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA1_UCODE_SELFLOAD_CONTROL, 0x00000210, 0),
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IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCPC_PSP_DEBUG, CPC_PSP_DEBUG__GPA_OVERRIDE_MASK, 0),
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IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA0_UCODE_SELFLOAD_CONTROL, 0x00000210, 0),
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IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA1_UCODE_SELFLOAD_CONTROL, 0x00000210, 0),
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IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCPC_PSP_DEBUG, CPC_PSP_DEBUG__GPA_OVERRIDE_MASK, 0),
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IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCPG_PSP_DEBUG, CPG_PSP_DEBUG__GPA_OVERRIDE_MASK, 0)
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};
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@ -186,7 +186,7 @@ static int xgpu_ai_send_access_requests(struct amdgpu_device *adev,
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/* Dummy REQ_GPU_INIT_DATA handling */
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r = xgpu_ai_poll_msg(adev, IDH_REQ_GPU_INIT_DATA_READY);
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/* version set to 0 since dummy */
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adev->virt.req_init_data_ver = 0;
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adev->virt.req_init_data_ver = 0;
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}
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return 0;
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@ -273,7 +273,7 @@ static int sdma_v5_0_init_microcode(struct amdgpu_device *adev)
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if (ret)
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return ret;
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}
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return ret;
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}
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@ -1765,7 +1765,8 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev)
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dc_deinit_callbacks(adev->dm.dc);
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#endif
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dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
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if (adev->dm.dc)
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dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
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if (dc_enable_dmub_notifications(adev->dm.dc)) {
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kfree(adev->dm.dmub_notify);
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@ -122,6 +122,9 @@ bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream)
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psr_config.allow_multi_disp_optimizations =
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(amdgpu_dc_feature_mask & DC_PSR_ALLOW_MULTI_DISP_OPT);
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if (!psr_su_set_y_granularity(dc, link, stream, &psr_config))
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return false;
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ret = dc_link_setup_psr(link, stream, &psr_config, &psr_context);
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}
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@ -26,6 +26,8 @@
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#ifndef DAL_DC_RN_CLK_MGR_VBIOS_SMU_H_
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#define DAL_DC_RN_CLK_MGR_VBIOS_SMU_H_
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enum dcn_pwr_state;
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int rn_vbios_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
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int rn_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
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int rn_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);
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@ -33,7 +35,7 @@ int rn_vbios_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int reque
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int rn_vbios_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz);
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void rn_vbios_smu_set_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz);
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int rn_vbios_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
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void rn_vbios_smu_set_dcn_low_power_state(struct clk_mgr_internal *clk_mgr, int display_count);
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void rn_vbios_smu_set_dcn_low_power_state(struct clk_mgr_internal *clk_mgr, enum dcn_pwr_state);
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void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
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void rn_vbios_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
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int rn_vbios_smu_is_periodic_retraining_disabled(struct clk_mgr_internal *clk_mgr);
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@ -1641,7 +1641,8 @@ noinline bool dcn30_internal_validate_bw(
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display_e2e_pipe_params_st *pipes,
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int *pipe_cnt_out,
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int *vlevel_out,
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bool fast_validate)
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bool fast_validate,
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bool allow_self_refresh_only)
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{
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bool out = false;
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bool repopulate_pipes = false;
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@ -1668,7 +1669,7 @@ noinline bool dcn30_internal_validate_bw(
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dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt);
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if (!fast_validate) {
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if (!fast_validate || !allow_self_refresh_only) {
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/*
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* DML favors voltage over p-state, but we're more interested in
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* supporting p-state over voltage. We can't support p-state in
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@ -1681,11 +1682,12 @@ noinline bool dcn30_internal_validate_bw(
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if (vlevel < context->bw_ctx.dml.soc.num_states)
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vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
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}
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if (fast_validate || vlevel == context->bw_ctx.dml.soc.num_states ||
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vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported) {
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if (allow_self_refresh_only &&
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(fast_validate || vlevel == context->bw_ctx.dml.soc.num_states ||
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vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported)) {
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/*
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* If mode is unsupported or there's still no p-state support then
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* fall back to favoring voltage.
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* If mode is unsupported or there's still no p-state support
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* then fall back to favoring voltage.
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*
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* We don't actually support prefetch mode 2, so require that we
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* at least support prefetch mode 1.
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@ -2056,7 +2058,7 @@ bool dcn30_validate_bandwidth(struct dc *dc,
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BW_VAL_TRACE_COUNT();
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DC_FP_START();
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out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate);
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out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate, true);
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DC_FP_END();
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if (pipe_cnt == 0)
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@ -64,7 +64,8 @@ bool dcn30_internal_validate_bw(
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display_e2e_pipe_params_st *pipes,
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int *pipe_cnt_out,
|
||||
int *vlevel_out,
|
||||
bool fast_validate);
|
||||
bool fast_validate,
|
||||
bool allow_self_refresh_only);
|
||||
void dcn30_calculate_wm_and_dlg(
|
||||
struct dc *dc, struct dc_state *context,
|
||||
display_e2e_pipe_params_st *pipes,
|
||||
|
|
|
|||
|
|
@ -1770,7 +1770,7 @@ bool dcn31_validate_bandwidth(struct dc *dc,
|
|||
BW_VAL_TRACE_COUNT();
|
||||
|
||||
DC_FP_START();
|
||||
out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate);
|
||||
out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate, true);
|
||||
DC_FP_END();
|
||||
|
||||
// Disable fast_validate to set min dcfclk in alculate_wm_and_dlg
|
||||
|
|
|
|||
|
|
@ -1689,6 +1689,81 @@ static void dcn314_get_panel_config_defaults(struct dc_panel_config *panel_confi
|
|||
*panel_config = panel_config_defaults;
|
||||
}
|
||||
|
||||
static bool filter_modes_for_single_channel_workaround(struct dc *dc,
|
||||
struct dc_state *context)
|
||||
{
|
||||
// Filter 2K@240Hz+8K@24fps above combination timing if memory only has single dimm LPDDR
|
||||
if (dc->clk_mgr->bw_params->vram_type == 34 && dc->clk_mgr->bw_params->num_channels < 2) {
|
||||
int total_phy_pix_clk = 0;
|
||||
|
||||
for (int i = 0; i < context->stream_count; i++)
|
||||
if (context->res_ctx.pipe_ctx[i].stream)
|
||||
total_phy_pix_clk += context->res_ctx.pipe_ctx[i].stream->phy_pix_clk;
|
||||
|
||||
if (total_phy_pix_clk >= (1148928+826260)) //2K@240Hz+8K@24fps
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
bool dcn314_validate_bandwidth(struct dc *dc,
|
||||
struct dc_state *context,
|
||||
bool fast_validate)
|
||||
{
|
||||
bool out = false;
|
||||
|
||||
BW_VAL_TRACE_SETUP();
|
||||
|
||||
int vlevel = 0;
|
||||
int pipe_cnt = 0;
|
||||
display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
|
||||
DC_LOGGER_INIT(dc->ctx->logger);
|
||||
|
||||
BW_VAL_TRACE_COUNT();
|
||||
|
||||
if (filter_modes_for_single_channel_workaround(dc, context))
|
||||
goto validate_fail;
|
||||
|
||||
DC_FP_START();
|
||||
// do not support self refresh only
|
||||
out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate, false);
|
||||
DC_FP_END();
|
||||
|
||||
// Disable fast_validate to set min dcfclk in calculate_wm_and_dlg
|
||||
if (pipe_cnt == 0)
|
||||
fast_validate = false;
|
||||
|
||||
if (!out)
|
||||
goto validate_fail;
|
||||
|
||||
BW_VAL_TRACE_END_VOLTAGE_LEVEL();
|
||||
|
||||
if (fast_validate) {
|
||||
BW_VAL_TRACE_SKIP(fast);
|
||||
goto validate_out;
|
||||
}
|
||||
|
||||
dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
|
||||
|
||||
BW_VAL_TRACE_END_WATERMARKS();
|
||||
|
||||
goto validate_out;
|
||||
|
||||
validate_fail:
|
||||
DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
|
||||
dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
|
||||
|
||||
BW_VAL_TRACE_SKIP(fail);
|
||||
out = false;
|
||||
|
||||
validate_out:
|
||||
kfree(pipes);
|
||||
|
||||
BW_VAL_TRACE_FINISH();
|
||||
|
||||
return out;
|
||||
}
|
||||
|
||||
static struct resource_funcs dcn314_res_pool_funcs = {
|
||||
.destroy = dcn314_destroy_resource_pool,
|
||||
.link_enc_create = dcn31_link_encoder_create,
|
||||
|
|
@ -1696,7 +1771,7 @@ static struct resource_funcs dcn314_res_pool_funcs = {
|
|||
.link_encs_assign = link_enc_cfg_link_encs_assign,
|
||||
.link_enc_unassign = link_enc_cfg_link_enc_unassign,
|
||||
.panel_cntl_create = dcn31_panel_cntl_create,
|
||||
.validate_bandwidth = dcn31_validate_bandwidth,
|
||||
.validate_bandwidth = dcn314_validate_bandwidth,
|
||||
.calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg,
|
||||
.update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
|
||||
.populate_dml_pipes = dcn314_populate_dml_pipes_from_context,
|
||||
|
|
|
|||
|
|
@ -39,6 +39,10 @@ struct dcn314_resource_pool {
|
|||
struct resource_pool base;
|
||||
};
|
||||
|
||||
bool dcn314_validate_bandwidth(struct dc *dc,
|
||||
struct dc_state *context,
|
||||
bool fast_validate);
|
||||
|
||||
struct resource_pool *dcn314_create_resource_pool(
|
||||
const struct dc_init_data *init_data,
|
||||
struct dc *dc);
|
||||
|
|
|
|||
|
|
@ -636,7 +636,7 @@ int dcn30_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc,
|
|||
while (dummy_latency_index < max_latency_table_entries) {
|
||||
context->bw_ctx.dml.soc.dram_clock_change_latency_us =
|
||||
dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;
|
||||
dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false);
|
||||
dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false, true);
|
||||
|
||||
if (context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank ==
|
||||
dm_allow_self_refresh_and_mclk_switch)
|
||||
|
|
|
|||
|
|
@ -907,3 +907,38 @@ bool mod_power_only_edp(const struct dc_state *context, const struct dc_stream_s
|
|||
{
|
||||
return context && context->stream_count == 1 && dc_is_embedded_signal(stream->signal);
|
||||
}
|
||||
|
||||
bool psr_su_set_y_granularity(struct dc *dc, struct dc_link *link,
|
||||
struct dc_stream_state *stream,
|
||||
struct psr_config *config)
|
||||
{
|
||||
uint16_t pic_height;
|
||||
uint8_t slice_height;
|
||||
|
||||
if ((link->connector_signal & SIGNAL_TYPE_EDP) &&
|
||||
(!dc->caps.edp_dsc_support ||
|
||||
link->panel_config.dsc.disable_dsc_edp ||
|
||||
!link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT ||
|
||||
!stream->timing.dsc_cfg.num_slices_v))
|
||||
return true;
|
||||
|
||||
pic_height = stream->timing.v_addressable +
|
||||
stream->timing.v_border_top + stream->timing.v_border_bottom;
|
||||
|
||||
if (stream->timing.dsc_cfg.num_slices_v == 0)
|
||||
return false;
|
||||
|
||||
slice_height = pic_height / stream->timing.dsc_cfg.num_slices_v;
|
||||
|
||||
if (slice_height) {
|
||||
if (config->su_y_granularity &&
|
||||
(slice_height % config->su_y_granularity)) {
|
||||
ASSERT(0);
|
||||
return false;
|
||||
}
|
||||
|
||||
config->su_y_granularity = slice_height;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -59,4 +59,7 @@ void mod_power_calc_psr_configs(struct psr_config *psr_config,
|
|||
const struct dc_stream_state *stream);
|
||||
bool mod_power_only_edp(const struct dc_state *context,
|
||||
const struct dc_stream_state *stream);
|
||||
bool psr_su_set_y_granularity(struct dc *dc, struct dc_link *link,
|
||||
struct dc_stream_state *stream,
|
||||
struct psr_config *config);
|
||||
#endif /* MODULES_POWER_POWER_HELPERS_H_ */
|
||||
|
|
|
|||
|
|
@ -60,7 +60,7 @@ enum amd_apu_flags {
|
|||
* acquires the list of IP blocks for the GPU in use on initialization.
|
||||
* It can then operate on this list to perform standard driver operations
|
||||
* such as: init, fini, suspend, resume, etc.
|
||||
*
|
||||
*
|
||||
*
|
||||
* IP block implementations are named using the following convention:
|
||||
* <functionality>_v<version> (E.g.: gfx_v6_0).
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,12 +1,12 @@
|
|||
/****************************************************************************\
|
||||
*
|
||||
*
|
||||
* File Name atomfirmwareid.h
|
||||
*
|
||||
* Description ATOM BIOS command/data table ID definition header file
|
||||
*
|
||||
* Copyright 2016 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
|
||||
* and associated documentation files (the "Software"), to deal in the Software without restriction,
|
||||
* including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
|
|
|
|||
|
|
@ -1,14 +1,14 @@
|
|||
/****************************************************************************\
|
||||
*
|
||||
*
|
||||
* Module Name displayobjectsoc15.h
|
||||
* Project
|
||||
* Device
|
||||
* Project
|
||||
* Device
|
||||
*
|
||||
* Description Contains the common definitions for display objects for SoC15 products.
|
||||
*
|
||||
* Copyright 2014 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
|
||||
* and associated documentation files (the "Software"), to deal in the Software without restriction,
|
||||
* including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
|
|
@ -35,7 +35,7 @@
|
|||
|
||||
|
||||
/****************************************************
|
||||
* Display Object Type Definition
|
||||
* Display Object Type Definition
|
||||
*****************************************************/
|
||||
enum display_object_type{
|
||||
DISPLAY_OBJECT_TYPE_NONE =0x00,
|
||||
|
|
@ -45,7 +45,7 @@ DISPLAY_OBJECT_TYPE_CONNECTOR =0x03
|
|||
};
|
||||
|
||||
/****************************************************
|
||||
* Encorder Object Type Definition
|
||||
* Encorder Object Type Definition
|
||||
*****************************************************/
|
||||
enum encoder_object_type{
|
||||
ENCODER_OBJECT_ID_NONE =0x00,
|
||||
|
|
@ -56,11 +56,11 @@ ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 =0x03,
|
|||
|
||||
|
||||
/****************************************************
|
||||
* Connector Object ID Definition
|
||||
* Connector Object ID Definition
|
||||
*****************************************************/
|
||||
|
||||
enum connector_object_type{
|
||||
CONNECTOR_OBJECT_ID_NONE =0x00,
|
||||
CONNECTOR_OBJECT_ID_NONE =0x00,
|
||||
CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D =0x01,
|
||||
CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D =0x02,
|
||||
CONNECTOR_OBJECT_ID_HDMI_TYPE_A =0x03,
|
||||
|
|
@ -72,12 +72,12 @@ CONNECTOR_OBJECT_ID_OPM =0x07
|
|||
|
||||
|
||||
/****************************************************
|
||||
* Protection Object ID Definition
|
||||
* Protection Object ID Definition
|
||||
*****************************************************/
|
||||
//No need
|
||||
|
||||
/****************************************************
|
||||
* Object ENUM ID Definition
|
||||
* Object ENUM ID Definition
|
||||
*****************************************************/
|
||||
|
||||
enum object_enum_id{
|
||||
|
|
@ -90,7 +90,7 @@ OBJECT_ENUM_ID6 =0x06
|
|||
};
|
||||
|
||||
/****************************************************
|
||||
*Object ID Bit definition
|
||||
*Object ID Bit definition
|
||||
*****************************************************/
|
||||
enum object_id_bit{
|
||||
OBJECT_ID_MASK =0x00FF,
|
||||
|
|
|
|||
|
|
@ -28,7 +28,7 @@
|
|||
struct IP_BASE_INSTANCE {
|
||||
unsigned int segment[MAX_SEGMENT];
|
||||
};
|
||||
|
||||
|
||||
struct IP_BASE {
|
||||
struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
|
||||
} __maybe_unused;
|
||||
|
|
|
|||
|
|
@ -133,7 +133,7 @@ typedef struct _ATOM_PPLIB_EXTENDEDHEADER
|
|||
USHORT usUVDTableOffset; //points to ATOM_PPLIB_UVD_Table
|
||||
USHORT usSAMUTableOffset; //points to ATOM_PPLIB_SAMU_Table
|
||||
USHORT usPPMTableOffset; //points to ATOM_PPLIB_PPM_Table
|
||||
USHORT usACPTableOffset; //points to ATOM_PPLIB_ACP_Table
|
||||
USHORT usACPTableOffset; //points to ATOM_PPLIB_ACP_Table
|
||||
/* points to ATOM_PPLIB_POWERTUNE_Table */
|
||||
USHORT usPowerTuneTableOffset;
|
||||
/* points to ATOM_PPLIB_CLOCK_Voltage_Dependency_Table for sclkVddgfxTable */
|
||||
|
|
@ -223,14 +223,14 @@ typedef struct _ATOM_PPLIB_POWERPLAYTABLE3
|
|||
typedef struct _ATOM_PPLIB_POWERPLAYTABLE4
|
||||
{
|
||||
ATOM_PPLIB_POWERPLAYTABLE3 basicTable3;
|
||||
ULONG ulGoldenPPID; // PPGen use only
|
||||
ULONG ulGoldenPPID; // PPGen use only
|
||||
ULONG ulGoldenRevision; // PPGen use only
|
||||
USHORT usVddcDependencyOnSCLKOffset;
|
||||
USHORT usVddciDependencyOnMCLKOffset;
|
||||
USHORT usVddcDependencyOnMCLKOffset;
|
||||
USHORT usMaxClockVoltageOnDCOffset;
|
||||
USHORT usVddcPhaseShedLimitsTableOffset; // Points to ATOM_PPLIB_PhaseSheddingLimits_Table
|
||||
USHORT usMvddDependencyOnMCLKOffset;
|
||||
USHORT usMvddDependencyOnMCLKOffset;
|
||||
} ATOM_PPLIB_POWERPLAYTABLE4, *LPATOM_PPLIB_POWERPLAYTABLE4;
|
||||
|
||||
typedef struct _ATOM_PPLIB_POWERPLAYTABLE5
|
||||
|
|
@ -376,21 +376,21 @@ typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO
|
|||
UCHAR ucMaxHTLinkWidth; // From SBIOS - {2, 4, 8, 16}
|
||||
UCHAR ucMinHTLinkWidth; // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled. Minimum down stream width could
|
||||
USHORT usHTLinkFreq; // See definition ATOM_PPLIB_RS780_HTLINKFREQ_xxx or in MHz(>=200).
|
||||
ULONG ulFlags;
|
||||
ULONG ulFlags;
|
||||
} ATOM_PPLIB_RS780_CLOCK_INFO;
|
||||
|
||||
#define ATOM_PPLIB_RS780_VOLTAGE_NONE 0
|
||||
#define ATOM_PPLIB_RS780_VOLTAGE_LOW 1
|
||||
#define ATOM_PPLIB_RS780_VOLTAGE_HIGH 2
|
||||
#define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE 3
|
||||
#define ATOM_PPLIB_RS780_VOLTAGE_NONE 0
|
||||
#define ATOM_PPLIB_RS780_VOLTAGE_LOW 1
|
||||
#define ATOM_PPLIB_RS780_VOLTAGE_HIGH 2
|
||||
#define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE 3
|
||||
|
||||
#define ATOM_PPLIB_RS780_SPMCLK_NONE 0 // We cannot change the side port memory clock, leave it as it is.
|
||||
#define ATOM_PPLIB_RS780_SPMCLK_LOW 1
|
||||
#define ATOM_PPLIB_RS780_SPMCLK_HIGH 2
|
||||
|
||||
#define ATOM_PPLIB_RS780_HTLINKFREQ_NONE 0
|
||||
#define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1
|
||||
#define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2
|
||||
#define ATOM_PPLIB_RS780_HTLINKFREQ_NONE 0
|
||||
#define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1
|
||||
#define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2
|
||||
|
||||
typedef struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO
|
||||
{
|
||||
|
|
@ -432,14 +432,14 @@ typedef struct _ATOM_PPLIB_CI_CLOCK_INFO
|
|||
|
||||
USHORT usMemoryClockLow;
|
||||
UCHAR ucMemoryClockHigh;
|
||||
|
||||
|
||||
UCHAR ucPCIEGen;
|
||||
USHORT usPCIELane;
|
||||
} ATOM_PPLIB_CI_CLOCK_INFO;
|
||||
|
||||
typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO{
|
||||
USHORT usEngineClockLow; //clockfrequency & 0xFFFF. The unit is in 10khz
|
||||
UCHAR ucEngineClockHigh; //clockfrequency >> 16.
|
||||
UCHAR ucEngineClockHigh; //clockfrequency >> 16.
|
||||
UCHAR vddcIndex; //2-bit vddc index;
|
||||
USHORT tdpLimit;
|
||||
//please initalize to 0
|
||||
|
|
@ -464,10 +464,10 @@ typedef struct _ATOM_PPLIB_CZ_CLOCK_INFO {
|
|||
|
||||
typedef struct _ATOM_PPLIB_STATE_V2
|
||||
{
|
||||
//number of valid dpm levels in this state; Driver uses it to calculate the whole
|
||||
//number of valid dpm levels in this state; Driver uses it to calculate the whole
|
||||
//size of the state: sizeof(ATOM_PPLIB_STATE_V2) + (ucNumDPMLevels - 1) * sizeof(UCHAR)
|
||||
UCHAR ucNumDPMLevels;
|
||||
|
||||
|
||||
//a index to the array of nonClockInfos
|
||||
UCHAR nonClockInfoIndex;
|
||||
/**
|
||||
|
|
@ -477,9 +477,9 @@ typedef struct _ATOM_PPLIB_STATE_V2
|
|||
} ATOM_PPLIB_STATE_V2;
|
||||
|
||||
typedef struct _StateArray{
|
||||
//how many states we have
|
||||
//how many states we have
|
||||
UCHAR ucNumEntries;
|
||||
|
||||
|
||||
ATOM_PPLIB_STATE_V2 states[1];
|
||||
}StateArray;
|
||||
|
||||
|
|
@ -487,10 +487,10 @@ typedef struct _StateArray{
|
|||
typedef struct _ClockInfoArray{
|
||||
//how many clock levels we have
|
||||
UCHAR ucNumEntries;
|
||||
|
||||
|
||||
//sizeof(ATOM_PPLIB_CLOCK_INFO)
|
||||
UCHAR ucEntrySize;
|
||||
|
||||
|
||||
UCHAR clockInfo[1];
|
||||
}ClockInfoArray;
|
||||
|
||||
|
|
@ -500,7 +500,7 @@ typedef struct _NonClockInfoArray{
|
|||
UCHAR ucNumEntries;
|
||||
//sizeof(ATOM_PPLIB_NONCLOCK_INFO)
|
||||
UCHAR ucEntrySize;
|
||||
|
||||
|
||||
ATOM_PPLIB_NONCLOCK_INFO nonClockInfo[1];
|
||||
}NonClockInfoArray;
|
||||
|
||||
|
|
@ -722,7 +722,7 @@ typedef struct _ATOM_PPLIB_PPM_Table
|
|||
ULONG ulPlatformTDC;
|
||||
ULONG ulSmallACPlatformTDC;
|
||||
ULONG ulApuTDP;
|
||||
ULONG ulDGpuTDP;
|
||||
ULONG ulDGpuTDP;
|
||||
ULONG ulDGpuUlvPower;
|
||||
ULONG ulTjmax;
|
||||
} ATOM_PPLIB_PPM_Table;
|
||||
|
|
|
|||
|
|
@ -365,7 +365,7 @@ typedef struct {
|
|||
uint16_t FanMaximumRpm;
|
||||
uint16_t FanTargetTemperature;
|
||||
uint16_t FanTargetGfxclk;
|
||||
uint8_t FanZeroRpmEnable;
|
||||
uint8_t FanZeroRpmEnable;
|
||||
uint8_t FanTachEdgePerRev;
|
||||
|
||||
|
||||
|
|
@ -659,8 +659,8 @@ typedef struct {
|
|||
uint8_t Gfx_IdleHystLimit;
|
||||
uint8_t Gfx_FPS;
|
||||
uint8_t Gfx_MinActiveFreqType;
|
||||
uint8_t Gfx_BoosterFreqType;
|
||||
uint8_t Gfx_UseRlcBusy;
|
||||
uint8_t Gfx_BoosterFreqType;
|
||||
uint8_t Gfx_UseRlcBusy;
|
||||
uint16_t Gfx_MinActiveFreq;
|
||||
uint16_t Gfx_BoosterFreq;
|
||||
uint16_t Gfx_PD_Data_time_constant;
|
||||
|
|
@ -674,7 +674,7 @@ typedef struct {
|
|||
uint8_t Soc_IdleHystLimit;
|
||||
uint8_t Soc_FPS;
|
||||
uint8_t Soc_MinActiveFreqType;
|
||||
uint8_t Soc_BoosterFreqType;
|
||||
uint8_t Soc_BoosterFreqType;
|
||||
uint8_t Soc_UseRlcBusy;
|
||||
uint16_t Soc_MinActiveFreq;
|
||||
uint16_t Soc_BoosterFreq;
|
||||
|
|
@ -690,7 +690,7 @@ typedef struct {
|
|||
uint8_t Mem_FPS;
|
||||
uint8_t Mem_MinActiveFreqType;
|
||||
uint8_t Mem_BoosterFreqType;
|
||||
uint8_t Mem_UseRlcBusy;
|
||||
uint8_t Mem_UseRlcBusy;
|
||||
uint16_t Mem_MinActiveFreq;
|
||||
uint16_t Mem_BoosterFreq;
|
||||
uint16_t Mem_PD_Data_time_constant;
|
||||
|
|
|
|||
|
|
@ -161,10 +161,15 @@ int smu_get_dpm_freq_range(struct smu_context *smu,
|
|||
|
||||
int smu_set_gfx_power_up_by_imu(struct smu_context *smu)
|
||||
{
|
||||
if (!smu->ppt_funcs && !smu->ppt_funcs->set_gfx_power_up_by_imu)
|
||||
return -EOPNOTSUPP;
|
||||
int ret = 0;
|
||||
struct amdgpu_device *adev = smu->adev;
|
||||
|
||||
return smu->ppt_funcs->set_gfx_power_up_by_imu(smu);
|
||||
if (smu->ppt_funcs->set_gfx_power_up_by_imu) {
|
||||
ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu);
|
||||
if (ret)
|
||||
dev_err(adev->dev, "Failed to enable gfx imu!\n");
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static u32 smu_get_mclk(void *handle, bool low)
|
||||
|
|
@ -195,6 +200,19 @@ static u32 smu_get_sclk(void *handle, bool low)
|
|||
return clk_freq * 100;
|
||||
}
|
||||
|
||||
static int smu_set_gfx_imu_enable(struct smu_context *smu)
|
||||
{
|
||||
struct amdgpu_device *adev = smu->adev;
|
||||
|
||||
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
|
||||
return 0;
|
||||
|
||||
if (amdgpu_in_reset(smu->adev) || adev->in_s0ix)
|
||||
return 0;
|
||||
|
||||
return smu_set_gfx_power_up_by_imu(smu);
|
||||
}
|
||||
|
||||
static int smu_dpm_set_vcn_enable(struct smu_context *smu,
|
||||
bool enable)
|
||||
{
|
||||
|
|
@ -1386,15 +1404,9 @@ static int smu_hw_init(void *handle)
|
|||
}
|
||||
|
||||
if (smu->is_apu) {
|
||||
if ((smu->ppt_funcs->set_gfx_power_up_by_imu) &&
|
||||
likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
|
||||
ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu);
|
||||
if (ret) {
|
||||
dev_err(adev->dev, "Failed to Enable gfx imu!\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
ret = smu_set_gfx_imu_enable(smu);
|
||||
if (ret)
|
||||
return ret;
|
||||
smu_dpm_set_vcn_enable(smu, true);
|
||||
smu_dpm_set_jpeg_enable(smu, true);
|
||||
smu_set_gfx_cgpg(smu, true);
|
||||
|
|
@ -1670,6 +1682,10 @@ static int smu_resume(void *handle)
|
|||
return ret;
|
||||
}
|
||||
|
||||
ret = smu_set_gfx_imu_enable(smu);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
smu_set_gfx_cgpg(smu, true);
|
||||
|
||||
smu->disable_uclk_switch = 0;
|
||||
|
|
|
|||
|
|
@ -1312,8 +1312,8 @@ struct pptable_funcs {
|
|||
* @get_ecc_table: message SMU to get ECC INFO table.
|
||||
*/
|
||||
ssize_t (*get_ecc_info)(struct smu_context *smu, void *table);
|
||||
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @stb_collect_info: Collects Smart Trace Buffers data.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -90,7 +90,7 @@ DEFINE_STATIC_SRCU(drm_unplug_srcu);
|
|||
* Some functions are only called once on init regardless of how many times
|
||||
* drm attaches. In linux this is handled via module_init()/module_exit()
|
||||
*/
|
||||
int drm_refcnt;
|
||||
int drm_refcnt;
|
||||
|
||||
struct drm_softc {
|
||||
struct device sc_dev;
|
||||
|
|
@ -1225,7 +1225,7 @@ drm_attach_pci(const struct drm_driver *driver, struct pci_attach_args *pa,
|
|||
sc = (struct drm_softc *)config_found_sm(dev, &arg, drmprint, drmsubmatch);
|
||||
if (sc == NULL)
|
||||
return NULL;
|
||||
|
||||
|
||||
return sc->sc_drm;
|
||||
}
|
||||
|
||||
|
|
@ -1522,7 +1522,7 @@ const struct pci_device_id *
|
|||
drm_find_description(int vendor, int device, const struct pci_device_id *idlist)
|
||||
{
|
||||
int i = 0;
|
||||
|
||||
|
||||
for (i = 0; idlist[i].vendor != 0; i++) {
|
||||
if ((idlist[i].vendor == vendor) &&
|
||||
(idlist[i].device == device ||
|
||||
|
|
@ -1546,7 +1546,7 @@ struct drm_file *
|
|||
drm_find_file_by_minor(struct drm_device *dev, int minor)
|
||||
{
|
||||
struct drm_file key;
|
||||
|
||||
|
||||
key.fminor = minor;
|
||||
return (SPLAY_FIND(drm_file_tree, &dev->files, &key));
|
||||
}
|
||||
|
|
@ -1886,7 +1886,7 @@ drm_dmamem_alloc(bus_dma_tag_t dmat, bus_size_t size, bus_size_t alignment,
|
|||
struct drm_dmamem *mem;
|
||||
size_t strsize;
|
||||
/*
|
||||
* segs is the last member of the struct since we modify the size
|
||||
* segs is the last member of the struct since we modify the size
|
||||
* to allow extra segments if more than one are allowed.
|
||||
*/
|
||||
strsize = sizeof(*mem) + (sizeof(bus_dma_segment_t) * (nsegments - 1));
|
||||
|
|
@ -1904,7 +1904,7 @@ drm_dmamem_alloc(bus_dma_tag_t dmat, bus_size_t size, bus_size_t alignment,
|
|||
&mem->nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO) != 0)
|
||||
goto destroy;
|
||||
|
||||
if (bus_dmamem_map(dmat, mem->segs, mem->nsegs, size,
|
||||
if (bus_dmamem_map(dmat, mem->segs, mem->nsegs, size,
|
||||
&mem->kva, BUS_DMA_NOWAIT | mapflags) != 0)
|
||||
goto free;
|
||||
|
||||
|
|
|
|||
|
|
@ -102,7 +102,7 @@ drm_fault(struct uvm_faultinfo *ufi, vaddr_t vaddr, vm_page_t *pps,
|
|||
* we do not allow device mappings to be mapped copy-on-write
|
||||
* so we kill any attempt to do so here.
|
||||
*/
|
||||
|
||||
|
||||
if (UVM_ET_ISCOPYONWRITE(entry)) {
|
||||
uvmfault_unlockall(ufi, ufi->entry->aref.ar_amap, uobj);
|
||||
return(VM_PAGER_ERROR);
|
||||
|
|
@ -144,7 +144,7 @@ drm_fault(struct uvm_faultinfo *ufi, vaddr_t vaddr, vm_page_t *pps,
|
|||
return (ret);
|
||||
}
|
||||
|
||||
boolean_t
|
||||
boolean_t
|
||||
drm_flush(struct uvm_object *uobj, voff_t start, voff_t stop, int flags)
|
||||
{
|
||||
return (TRUE);
|
||||
|
|
@ -309,10 +309,10 @@ int drm_gem_object_init(struct drm_device *dev,
|
|||
printf("%s size too big %lu\n", __func__, size);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
|
||||
obj->uao = uao_create(size, 0);
|
||||
uvm_obj_init(&obj->uobj, &drm_pgops, 1);
|
||||
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -251,7 +251,7 @@ kthread_run(int (*func)(void *), void *data, const char *name)
|
|||
thread->func = func;
|
||||
thread->data = data;
|
||||
thread->flags = 0;
|
||||
|
||||
|
||||
if (kthread_create(kthread_func, thread, &thread->proc, name)) {
|
||||
free(thread, M_DRM, sizeof(*thread));
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
|
@ -272,7 +272,7 @@ kthread_create_worker(unsigned int flags, const char *fmt, ...)
|
|||
vsnprintf(name, sizeof(name), fmt, ap);
|
||||
va_end(ap);
|
||||
w->tq = taskq_create(name, 1, IPL_HIGH, 0);
|
||||
|
||||
|
||||
return w;
|
||||
}
|
||||
|
||||
|
|
@ -281,7 +281,7 @@ kthread_destroy_worker(struct kthread_worker *worker)
|
|||
{
|
||||
taskq_destroy(worker->tq);
|
||||
free(worker, M_DRM, sizeof(*worker));
|
||||
|
||||
|
||||
}
|
||||
|
||||
void
|
||||
|
|
@ -551,7 +551,7 @@ __free_pages(struct vm_page *page, unsigned int order)
|
|||
{
|
||||
struct pglist mlist;
|
||||
int i;
|
||||
|
||||
|
||||
TAILQ_INIT(&mlist);
|
||||
for (i = 0; i < (1 << order); i++)
|
||||
TAILQ_INSERT_TAIL(&mlist, &page[i], pageq);
|
||||
|
|
@ -623,7 +623,7 @@ void
|
|||
kunmap_atomic(void *addr)
|
||||
{
|
||||
KASSERT(kmap_atomic_inuse);
|
||||
|
||||
|
||||
pmap_kremove(kmap_atomic_va, PAGE_SIZE);
|
||||
kmap_atomic_inuse = 0;
|
||||
}
|
||||
|
|
@ -1193,7 +1193,7 @@ retry:
|
|||
int
|
||||
i2c_transfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
|
||||
{
|
||||
int ret;
|
||||
int ret;
|
||||
|
||||
if (adap->lock_ops)
|
||||
adap->lock_ops->lock_bus(adap, 0);
|
||||
|
|
@ -1497,7 +1497,7 @@ backlight_device_register(const char *name, void *kdev, void *data,
|
|||
bd->data = data;
|
||||
|
||||
task_set(&bd->task, backlight_do_update_status, bd);
|
||||
|
||||
|
||||
return bd;
|
||||
}
|
||||
|
||||
|
|
@ -1720,7 +1720,7 @@ dma_fence_wait(struct dma_fence *fence, bool intr)
|
|||
ret = dma_fence_wait_timeout(fence, intr, MAX_SCHEDULE_TIMEOUT);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -1880,7 +1880,7 @@ dma_fence_default_wait(struct dma_fence *fence, bool intr, signed long timeout)
|
|||
list_del(&cb.base.node);
|
||||
out:
|
||||
mtx_leave(fence->lock);
|
||||
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -1926,7 +1926,7 @@ dma_fence_wait_any_timeout(struct dma_fence **fences, uint32_t count,
|
|||
cb = mallocarray(count, sizeof(*cb), M_DRM, M_WAITOK|M_CANFAIL|M_ZERO);
|
||||
if (cb == NULL)
|
||||
return -ENOMEM;
|
||||
|
||||
|
||||
for (i = 0; i < count; i++) {
|
||||
struct dma_fence *fence = fences[i];
|
||||
cb[i].proc = curproc;
|
||||
|
|
@ -2022,7 +2022,7 @@ dma_fence_array_cb_func(struct dma_fence *f, struct dma_fence_cb *cb)
|
|||
struct dma_fence_array_cb *array_cb =
|
||||
container_of(cb, struct dma_fence_array_cb, cb);
|
||||
struct dma_fence_array *dfa = array_cb->array;
|
||||
|
||||
|
||||
if (atomic_dec_and_test(&dfa->num_pending))
|
||||
timeout_add(&dfa->to, 1);
|
||||
else
|
||||
|
|
@ -2046,7 +2046,7 @@ dma_fence_array_enable_signaling(struct dma_fence *fence)
|
|||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
@ -2526,7 +2526,7 @@ pcie_get_speed_cap(struct pci_dev *pdev)
|
|||
tag = pdev->tag;
|
||||
|
||||
if (!pci_get_capability(pc, tag, PCI_CAP_PCIEXPRESS,
|
||||
&pos, NULL))
|
||||
&pos, NULL))
|
||||
return PCI_SPEED_UNKNOWN;
|
||||
|
||||
id = pci_conf_read(pc, tag, PCI_ID_REG);
|
||||
|
|
@ -2582,7 +2582,7 @@ pcie_get_width_cap(struct pci_dev *pdev)
|
|||
int bus, device, function;
|
||||
|
||||
if (!pci_get_capability(pc, tag, PCI_CAP_PCIEXPRESS,
|
||||
&pos, NULL))
|
||||
&pos, NULL))
|
||||
return PCIE_LNK_WIDTH_UNKNOWN;
|
||||
|
||||
id = pci_conf_read(pc, tag, PCI_ID_REG);
|
||||
|
|
@ -2607,13 +2607,13 @@ pcie_aspm_enabled(struct pci_dev *pdev)
|
|||
pcireg_t lcsr;
|
||||
|
||||
if (!pci_get_capability(pc, tag, PCI_CAP_PCIEXPRESS,
|
||||
&pos, NULL))
|
||||
&pos, NULL))
|
||||
return false;
|
||||
|
||||
lcsr = pci_conf_read(pc, tag, pos + PCI_PCIE_LCSR);
|
||||
if ((lcsr & (PCI_PCIE_LCSR_ASPM_L0S | PCI_PCIE_LCSR_ASPM_L1)) != 0)
|
||||
return true;
|
||||
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
|
|
@ -2896,7 +2896,7 @@ interval_tree_iter_first(struct rb_root_cached *root, unsigned long start,
|
|||
|
||||
void
|
||||
interval_tree_remove(struct interval_tree_node *node,
|
||||
struct rb_root_cached *root)
|
||||
struct rb_root_cached *root)
|
||||
{
|
||||
rb_erase_cached(&node->rb, root);
|
||||
}
|
||||
|
|
@ -3021,7 +3021,7 @@ fput(struct file *fp)
|
|||
{
|
||||
if (fp->f_type != DTYPE_SYNC)
|
||||
return;
|
||||
|
||||
|
||||
FRELE(fp, curproc);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -223,7 +223,7 @@ int drm_legacy_lock(struct drm_device *dev, void *data,
|
|||
ret ? "interrupted" : "has lock");
|
||||
if (ret) return ret;
|
||||
|
||||
/* don't set the block all signals on the master process for now
|
||||
/* don't set the block all signals on the master process for now
|
||||
* really probably not the correct answer but lets us debug xkb
|
||||
* xserver for now */
|
||||
if (!drm_is_current_master(file_priv)) {
|
||||
|
|
|
|||
|
|
@ -95,7 +95,7 @@ drmm_kfree(struct drm_device *dev, void *p)
|
|||
}
|
||||
}
|
||||
mtx_leave(&dev->managed.lock);
|
||||
|
||||
|
||||
if (m != NULL) {
|
||||
free(m->p, M_DRM, m->size);
|
||||
free(m, M_DRM, sizeof(*m));
|
||||
|
|
|
|||
|
|
@ -174,7 +174,7 @@ drm_mm_interval_tree_iter_first(const struct rb_root_cached *root,
|
|||
|
||||
static void
|
||||
drm_mm_interval_tree_remove(struct drm_mm_node *node,
|
||||
struct rb_root_cached *root)
|
||||
struct rb_root_cached *root)
|
||||
{
|
||||
rb_erase_cached(&node->rb, root);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -557,8 +557,9 @@ retry:
|
|||
*/
|
||||
dev->mode_config.delayed_event = true;
|
||||
if (dev->mode_config.poll_enabled)
|
||||
schedule_delayed_work(&dev->mode_config.output_poll_work,
|
||||
0);
|
||||
mod_delayed_work(system_wq,
|
||||
&dev->mode_config.output_poll_work,
|
||||
0);
|
||||
}
|
||||
|
||||
/* Re-enable polling in case the global poll config changed. */
|
||||
|
|
|
|||
|
|
@ -1079,7 +1079,7 @@ intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
|
|||
num_encoders++;
|
||||
}
|
||||
|
||||
drm_WARN(encoder->base.dev, num_encoders != 1,
|
||||
drm_WARN(state->base.dev, num_encoders != 1,
|
||||
"%d encoders for pipe %c\n",
|
||||
num_encoders, pipe_name(master_crtc->pipe));
|
||||
|
||||
|
|
|
|||
|
|
@ -177,7 +177,7 @@ intel_gmch_gtt_get(u64 *gtt_total,
|
|||
{
|
||||
struct inteldrm_softc *dev_priv = (void *)inteldrm_cd.cd_devs[0];
|
||||
struct agp_info *ai = &dev_priv->drm.agp->info;
|
||||
|
||||
|
||||
*gtt_total = ai->ai_aperture_size;
|
||||
*mappable_base = ai->ai_aperture_base;
|
||||
*mappable_end = ai->ai_aperture_size;
|
||||
|
|
|
|||
|
|
@ -228,7 +228,7 @@ static int __uao_rw(struct uvm_object *uao, loff_t off,
|
|||
unsigned int this =
|
||||
min_t(size_t, PAGE_SIZE - offset_in_page(off), len);
|
||||
void *vaddr = kmap(page);
|
||||
|
||||
|
||||
if (write) {
|
||||
memcpy(vaddr + offset_in_page(off), ptr, this);
|
||||
set_page_dirty(page);
|
||||
|
|
|
|||
|
|
@ -707,7 +707,6 @@
|
|||
INTEL_VGA_DEVICE(0x5693, info), \
|
||||
INTEL_VGA_DEVICE(0x5694, info), \
|
||||
INTEL_VGA_DEVICE(0x5695, info), \
|
||||
INTEL_VGA_DEVICE(0x5698, info), \
|
||||
INTEL_VGA_DEVICE(0x56A5, info), \
|
||||
INTEL_VGA_DEVICE(0x56A6, info), \
|
||||
INTEL_VGA_DEVICE(0x56B0, info), \
|
||||
|
|
|
|||
12
sys/dev/pci/drm/include/linux/apple-gmux.h
Normal file
12
sys/dev/pci/drm/include/linux/apple-gmux.h
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
/* Public domain. */
|
||||
|
||||
#ifndef _LINUX_APPLE_GMUX_H
|
||||
#define _LINUX_APPLE_GMUX_H
|
||||
|
||||
static inline bool
|
||||
apple_gmux_detect(void *a, void *b)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -2,7 +2,7 @@
|
|||
/**
|
||||
* \file drm_atomic.h
|
||||
* Atomic operations used in the DRM which may or may not be provided by the OS.
|
||||
*
|
||||
*
|
||||
* \author Eric Anholt <anholt@FreeBSD.org>
|
||||
*/
|
||||
|
||||
|
|
@ -298,7 +298,7 @@ __test_and_set_bit(u_int b, volatile void *p)
|
|||
volatile u_int *ptr = (volatile u_int *)p;
|
||||
unsigned int prev = ptr[b >> 5];
|
||||
ptr[b >> 5] |= m;
|
||||
|
||||
|
||||
return (prev & m) != 0;
|
||||
}
|
||||
|
||||
|
|
@ -428,7 +428,7 @@ find_next_bit(const volatile void *p, int max, int b)
|
|||
#define wmb() __membar("dsb sy")
|
||||
#define mb() __membar("dsb sy")
|
||||
#elif defined(__mips64__)
|
||||
#define rmb() mips_sync()
|
||||
#define rmb() mips_sync()
|
||||
#define wmb() mips_sync()
|
||||
#define mb() mips_sync()
|
||||
#elif defined(__powerpc64__)
|
||||
|
|
|
|||
|
|
@ -12,8 +12,8 @@
|
|||
#define CAP_SYS_NICE 0x2
|
||||
|
||||
static inline bool
|
||||
capable(int cap)
|
||||
{
|
||||
capable(int cap)
|
||||
{
|
||||
switch (cap) {
|
||||
case CAP_SYS_ADMIN:
|
||||
case CAP_SYS_NICE:
|
||||
|
|
@ -21,7 +21,7 @@ capable(int cap)
|
|||
default:
|
||||
panic("unhandled capability");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static inline bool
|
||||
perfmon_capable(void)
|
||||
|
|
|
|||
|
|
@ -61,7 +61,7 @@ struct dma_buf_export_info {
|
|||
struct dma_resv *resv;
|
||||
};
|
||||
|
||||
#define DEFINE_DMA_BUF_EXPORT_INFO(x) struct dma_buf_export_info x
|
||||
#define DEFINE_DMA_BUF_EXPORT_INFO(x) struct dma_buf_export_info x
|
||||
|
||||
struct dma_buf *dma_buf_export(const struct dma_buf_export_info *);
|
||||
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
#define _LINUX_FILE_H
|
||||
|
||||
/* both for printf */
|
||||
#include <sys/types.h>
|
||||
#include <sys/types.h>
|
||||
#include <sys/systm.h>
|
||||
|
||||
void fd_install(int, struct file *);
|
||||
|
|
|
|||
|
|
@ -106,7 +106,7 @@ tasklet_hi_schedule(struct tasklet_struct *ts)
|
|||
task_add(taskletq, &ts->task);
|
||||
}
|
||||
|
||||
static inline void
|
||||
static inline void
|
||||
tasklet_disable_nosync(struct tasklet_struct *ts)
|
||||
{
|
||||
atomic_inc(&ts->count);
|
||||
|
|
|
|||
|
|
@ -119,7 +119,7 @@ static inline u32
|
|||
ioread32(const volatile void __iomem *addr)
|
||||
{
|
||||
uint32_t val;
|
||||
|
||||
|
||||
iobarrier();
|
||||
val = lemtoh32(addr);
|
||||
rmb();
|
||||
|
|
|
|||
|
|
@ -135,7 +135,7 @@ pci_read_config_dword(struct pci_dev *pdev, int reg, u32 *val)
|
|||
{
|
||||
*val = pci_conf_read(pdev->pc, pdev->tag, reg);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
static inline int
|
||||
pci_read_config_word(struct pci_dev *pdev, int reg, u16 *val)
|
||||
|
|
@ -145,7 +145,7 @@ pci_read_config_word(struct pci_dev *pdev, int reg, u16 *val)
|
|||
v = pci_conf_read(pdev->pc, pdev->tag, (reg & ~0x2));
|
||||
*val = (v >> ((reg & 0x2) * 8));
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
static inline int
|
||||
pci_read_config_byte(struct pci_dev *pdev, int reg, u8 *val)
|
||||
|
|
@ -155,14 +155,14 @@ pci_read_config_byte(struct pci_dev *pdev, int reg, u8 *val)
|
|||
v = pci_conf_read(pdev->pc, pdev->tag, (reg & ~0x3));
|
||||
*val = (v >> ((reg & 0x3) * 8));
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
static inline int
|
||||
pci_write_config_dword(struct pci_dev *pdev, int reg, u32 val)
|
||||
{
|
||||
pci_conf_write(pdev->pc, pdev->tag, reg, val);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
static inline int
|
||||
pci_write_config_word(struct pci_dev *pdev, int reg, u16 val)
|
||||
|
|
@ -174,7 +174,7 @@ pci_write_config_word(struct pci_dev *pdev, int reg, u16 val)
|
|||
v |= (val << ((reg & 0x2) * 8));
|
||||
pci_conf_write(pdev->pc, pdev->tag, (reg & ~0x2), v);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
static inline int
|
||||
pci_write_config_byte(struct pci_dev *pdev, int reg, u8 val)
|
||||
|
|
@ -319,7 +319,7 @@ static inline int
|
|||
pcie_set_readrq(struct pci_dev *pdev, int rrq)
|
||||
{
|
||||
uint16_t val;
|
||||
|
||||
|
||||
pcie_capability_read_word(pdev, PCI_PCIE_DCSR, &val);
|
||||
val &= ~PCI_PCIE_DCSR_MPS;
|
||||
val |= (ffs(rrq) - 8) << 12;
|
||||
|
|
|
|||
|
|
@ -99,7 +99,7 @@ __rb_deepest_left(struct rb_node *node)
|
|||
else
|
||||
node = RB_RIGHT(node, __entry);
|
||||
}
|
||||
return parent;
|
||||
return parent;
|
||||
}
|
||||
|
||||
static inline struct rb_node *
|
||||
|
|
|
|||
|
|
@ -77,7 +77,7 @@ static inline bool
|
|||
__sg_page_iter_next(struct sg_page_iter *iter)
|
||||
{
|
||||
iter->sg_pgoffset++;
|
||||
while (iter->__nents > 0 &&
|
||||
while (iter->__nents > 0 &&
|
||||
iter->sg_pgoffset >= (iter->sg->length / PAGE_SIZE)) {
|
||||
iter->sg_pgoffset -= (iter->sg->length / PAGE_SIZE);
|
||||
iter->sg++;
|
||||
|
|
|
|||
|
|
@ -91,7 +91,7 @@ typedef struct {
|
|||
|
||||
static inline void
|
||||
seqlock_init(seqlock_t *sl, int wantipl)
|
||||
{
|
||||
{
|
||||
sl->seq = 0;
|
||||
mtx_init(&sl->lock, wantipl);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -74,7 +74,7 @@ match_string(const char * const *array, size_t n, const char *str)
|
|||
for (i = 0; i < n; i++) {
|
||||
if (array[i] == NULL)
|
||||
break;
|
||||
if (!strcmp(array[i], str))
|
||||
if (!strcmp(array[i], str))
|
||||
return i;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -30,11 +30,11 @@
|
|||
|
||||
static inline long
|
||||
get_nr_swap_pages(void)
|
||||
{
|
||||
{
|
||||
return uvmexp.swpages - uvmexp.swpginuse;
|
||||
}
|
||||
|
||||
/*
|
||||
/*
|
||||
* XXX For now, we don't want the shrinker to be too aggressive, so
|
||||
* pretend we're not called from the pagedaemon even if we are.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -30,12 +30,12 @@ typedef uint32_t u32;
|
|||
typedef int64_t s64;
|
||||
typedef uint64_t u64;
|
||||
|
||||
typedef uint16_t __le16;
|
||||
typedef uint16_t __be16;
|
||||
typedef uint32_t __le32;
|
||||
typedef uint16_t __le16;
|
||||
typedef uint16_t __be16;
|
||||
typedef uint32_t __le32;
|
||||
typedef uint32_t __be32;
|
||||
typedef uint64_t __le64;
|
||||
typedef uint64_t __be64;
|
||||
typedef uint64_t __le64;
|
||||
typedef uint64_t __be64;
|
||||
|
||||
typedef bus_addr_t dma_addr_t;
|
||||
typedef paddr_t phys_addr_t;
|
||||
|
|
|
|||
|
|
@ -221,7 +221,7 @@ wake_up(wait_queue_head_t *wqh)
|
|||
wait_queue_entry_t *wqe;
|
||||
wait_queue_entry_t *tmp;
|
||||
mtx_enter(&wqh->lock);
|
||||
|
||||
|
||||
list_for_each_entry_safe(wqe, tmp, &wqh->head, entry) {
|
||||
KASSERT(wqe->func != NULL);
|
||||
if (wqe->func != NULL)
|
||||
|
|
@ -255,7 +255,7 @@ wake_up_all_locked(wait_queue_head_t *wqh)
|
|||
.private = curproc, \
|
||||
.func = autoremove_wake_function, \
|
||||
.entry = LIST_HEAD_INIT((name).entry), \
|
||||
}
|
||||
}
|
||||
|
||||
static inline void
|
||||
prepare_to_wait(wait_queue_head_t *wqh, wait_queue_entry_t *wqe, int state)
|
||||
|
|
|
|||
|
|
@ -209,7 +209,7 @@ static inline int
|
|||
ww_mutex_lock(struct ww_mutex *lock, struct ww_acquire_ctx *ctx) {
|
||||
return __ww_mutex_lock(lock, ctx, false, false);
|
||||
}
|
||||
|
||||
|
||||
static inline void
|
||||
ww_mutex_lock_slow(struct ww_mutex *lock, struct ww_acquire_ctx *ctx) {
|
||||
(void)__ww_mutex_lock(lock, ctx, true, false);
|
||||
|
|
@ -219,7 +219,7 @@ static inline int
|
|||
ww_mutex_lock_interruptible(struct ww_mutex *lock, struct ww_acquire_ctx *ctx) {
|
||||
return __ww_mutex_lock(lock, ctx, false, true);
|
||||
}
|
||||
|
||||
|
||||
static inline int __must_check
|
||||
ww_mutex_lock_slow_interruptible(struct ww_mutex *lock, struct ww_acquire_ctx *ctx) {
|
||||
return __ww_mutex_lock(lock, ctx, true, true);
|
||||
|
|
|
|||
|
|
@ -233,7 +233,7 @@ typedef union {
|
|||
# define R300_WAIT_3D 0x2
|
||||
/* these two defines are DOING IT WRONG - however
|
||||
* we have userspace which relies on using these.
|
||||
* The wait interface is backwards compat new
|
||||
* The wait interface is backwards compat new
|
||||
* code should use the NEW_WAIT defines below
|
||||
* THESE ARE NOT BIT FIELDS
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -56,7 +56,7 @@ static __inline void swapfunc(char *, char *, size_t, int);
|
|||
static __inline void
|
||||
swapfunc(char *a, char *b, size_t n, int swaptype)
|
||||
{
|
||||
if (swaptype <= 1)
|
||||
if (swaptype <= 1)
|
||||
swapcode(long, a, b, n)
|
||||
else
|
||||
swapcode(char, a, b, n)
|
||||
|
|
@ -167,7 +167,7 @@ loop: SWAPINIT(a, es);
|
|||
|
||||
void
|
||||
sort(void *a, size_t n, size_t es, int (*cmp)(const void *, const void *),
|
||||
void *x)
|
||||
void *x)
|
||||
{
|
||||
KASSERT(x == NULL);
|
||||
qsort(a, n, es, cmp);
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright 2006-2007 Advanced Micro Devices, Inc.
|
||||
* Copyright 2006-2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
|
|
@ -37,13 +37,13 @@
|
|||
#define GRAPH_OBJECT_TYPE_CONNECTOR 0x3
|
||||
#define GRAPH_OBJECT_TYPE_ROUTER 0x4
|
||||
/* deleted */
|
||||
#define GRAPH_OBJECT_TYPE_DISPLAY_PATH 0x6
|
||||
#define GRAPH_OBJECT_TYPE_DISPLAY_PATH 0x6
|
||||
#define GRAPH_OBJECT_TYPE_GENERIC 0x7
|
||||
|
||||
/****************************************************/
|
||||
/* Encoder Object ID Definition */
|
||||
/****************************************************/
|
||||
#define ENCODER_OBJECT_ID_NONE 0x00
|
||||
#define ENCODER_OBJECT_ID_NONE 0x00
|
||||
|
||||
/* Radeon Class Display Hardware */
|
||||
#define ENCODER_OBJECT_ID_INTERNAL_LVDS 0x01
|
||||
|
|
@ -96,7 +96,7 @@
|
|||
/****************************************************/
|
||||
/* Connector Object ID Definition */
|
||||
/****************************************************/
|
||||
#define CONNECTOR_OBJECT_ID_NONE 0x00
|
||||
#define CONNECTOR_OBJECT_ID_NONE 0x00
|
||||
#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I 0x01
|
||||
#define CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I 0x02
|
||||
#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D 0x03
|
||||
|
|
@ -156,7 +156,7 @@
|
|||
#define RESERVED1_ID_MASK 0x0800
|
||||
#define OBJECT_TYPE_MASK 0x7000
|
||||
#define RESERVED2_ID_MASK 0x8000
|
||||
|
||||
|
||||
#define OBJECT_ID_SHIFT 0x00
|
||||
#define ENUM_ID_SHIFT 0x08
|
||||
#define OBJECT_TYPE_SHIFT 0x0C
|
||||
|
|
@ -177,14 +177,14 @@
|
|||
/* Encoder Object ID definition - Shared with BIOS */
|
||||
/****************************************************/
|
||||
/*
|
||||
#define ENCODER_INTERNAL_LVDS_ENUM_ID1 0x2101
|
||||
#define ENCODER_INTERNAL_LVDS_ENUM_ID1 0x2101
|
||||
#define ENCODER_INTERNAL_TMDS1_ENUM_ID1 0x2102
|
||||
#define ENCODER_INTERNAL_TMDS2_ENUM_ID1 0x2103
|
||||
#define ENCODER_INTERNAL_DAC1_ENUM_ID1 0x2104
|
||||
#define ENCODER_INTERNAL_DAC2_ENUM_ID1 0x2105
|
||||
#define ENCODER_INTERNAL_SDVOA_ENUM_ID1 0x2106
|
||||
#define ENCODER_INTERNAL_SDVOB_ENUM_ID1 0x2107
|
||||
#define ENCODER_SIL170B_ENUM_ID1 0x2108
|
||||
#define ENCODER_SIL170B_ENUM_ID1 0x2108
|
||||
#define ENCODER_CH7303_ENUM_ID1 0x2109
|
||||
#define ENCODER_CH7301_ENUM_ID1 0x210A
|
||||
#define ENCODER_INTERNAL_DVO1_ENUM_ID1 0x210B
|
||||
|
|
@ -198,8 +198,8 @@
|
|||
#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1 0x2113
|
||||
#define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1 0x2114
|
||||
#define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1 0x2115
|
||||
#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 0x2116
|
||||
#define ENCODER_SI178_ENUM_ID1 0x2117
|
||||
#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 0x2116
|
||||
#define ENCODER_SI178_ENUM_ID1 0x2117
|
||||
#define ENCODER_MVPU_FPGA_ENUM_ID1 0x2118
|
||||
#define ENCODER_INTERNAL_DDI_ENUM_ID1 0x2119
|
||||
#define ENCODER_VT1625_ENUM_ID1 0x211A
|
||||
|
|
@ -314,7 +314,7 @@
|
|||
|
||||
#define ENCODER_SI178_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
|
||||
ENCODER_OBJECT_ID_SI178 << OBJECT_ID_SHIFT)
|
||||
ENCODER_OBJECT_ID_SI178 << OBJECT_ID_SHIFT)
|
||||
|
||||
#define ENCODER_MVPU_FPGA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
|
||||
|
|
@ -322,7 +322,7 @@
|
|||
|
||||
#define ENCODER_INTERNAL_DDI_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
|
||||
ENCODER_OBJECT_ID_INTERNAL_DDI << OBJECT_ID_SHIFT)
|
||||
ENCODER_OBJECT_ID_INTERNAL_DDI << OBJECT_ID_SHIFT)
|
||||
|
||||
#define ENCODER_VT1625_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
|
||||
|
|
@ -350,7 +350,7 @@
|
|||
|
||||
#define ENCODER_INTERNAL_KLDSCP_LVTMA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
|
||||
ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA << OBJECT_ID_SHIFT)
|
||||
ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA << OBJECT_ID_SHIFT)
|
||||
|
||||
#define ENCODER_INTERNAL_UNIPHY1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
|
||||
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -485,6 +485,68 @@ static unsigned int ttm_pool_page_order(struct ttm_pool *pool, struct vm_page *p
|
|||
|
||||
#endif /* notyet */
|
||||
|
||||
/* Called when we got a page, either from a pool or newly allocated */
|
||||
static int ttm_pool_page_allocated(struct ttm_pool *pool, unsigned int order,
|
||||
struct vm_page *p, dma_addr_t **dma_addr,
|
||||
unsigned long *num_pages,
|
||||
struct vm_page ***pages,
|
||||
unsigned long **orders)
|
||||
{
|
||||
unsigned int i;
|
||||
int r;
|
||||
|
||||
if (*dma_addr) {
|
||||
r = ttm_pool_map(pool, order, p, dma_addr);
|
||||
if (r)
|
||||
return r;
|
||||
}
|
||||
|
||||
*num_pages -= 1 << order;
|
||||
for (i = 1 << order; i; --i, ++(*pages), ++p, ++(*orders)) {
|
||||
**pages = p;
|
||||
**orders = order;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* ttm_pool_free_range() - Free a range of TTM pages
|
||||
* @pool: The pool used for allocating.
|
||||
* @tt: The struct ttm_tt holding the page pointers.
|
||||
* @caching: The page caching mode used by the range.
|
||||
* @start_page: index for first page to free.
|
||||
* @end_page: index for last page to free + 1.
|
||||
*
|
||||
* During allocation the ttm_tt page-vector may be populated with ranges of
|
||||
* pages with different attributes if allocation hit an error without being
|
||||
* able to completely fulfill the allocation. This function can be used
|
||||
* to free these individual ranges.
|
||||
*/
|
||||
static void ttm_pool_free_range(struct ttm_pool *pool, struct ttm_tt *tt,
|
||||
enum ttm_caching caching,
|
||||
pgoff_t start_page, pgoff_t end_page)
|
||||
{
|
||||
struct vm_page **pages = tt->pages;
|
||||
unsigned int order;
|
||||
pgoff_t i, nr;
|
||||
|
||||
for (i = start_page; i < end_page; i += nr, pages += nr) {
|
||||
struct ttm_pool_type *pt = NULL;
|
||||
|
||||
order = tt->orders[i];
|
||||
nr = (1UL << order);
|
||||
if (tt->dma_address)
|
||||
ttm_pool_unmap(pool, tt->dma_address[i], nr);
|
||||
|
||||
pt = ttm_pool_select_type(pool, caching, order);
|
||||
if (pt)
|
||||
ttm_pool_type_give(pt, *pages);
|
||||
else
|
||||
ttm_pool_free_page(pool, caching, order, *pages);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* ttm_pool_alloc - Fill a ttm_tt object
|
||||
*
|
||||
|
|
@ -500,15 +562,17 @@ static unsigned int ttm_pool_page_order(struct ttm_pool *pool, struct vm_page *p
|
|||
int ttm_pool_alloc(struct ttm_pool *pool, struct ttm_tt *tt,
|
||||
struct ttm_operation_ctx *ctx)
|
||||
{
|
||||
unsigned long num_pages = tt->num_pages;
|
||||
pgoff_t num_pages = tt->num_pages;
|
||||
dma_addr_t *dma_addr = tt->dma_address;
|
||||
struct vm_page **caching = tt->pages;
|
||||
struct vm_page **pages = tt->pages;
|
||||
unsigned long *orders = tt->orders;
|
||||
enum ttm_caching page_caching;
|
||||
gfp_t gfp_flags = GFP_USER;
|
||||
unsigned int i, order;
|
||||
pgoff_t caching_divide;
|
||||
unsigned int order;
|
||||
struct vm_page *p;
|
||||
int r;
|
||||
unsigned long *orders = tt->orders;
|
||||
|
||||
WARN_ON(!num_pages || ttm_tt_is_populated(tt));
|
||||
#ifdef __linux__
|
||||
|
|
@ -529,17 +593,51 @@ int ttm_pool_alloc(struct ttm_pool *pool, struct ttm_tt *tt,
|
|||
for (order = min_t(unsigned int, MAX_ORDER - 1, __fls(num_pages));
|
||||
num_pages;
|
||||
order = min_t(unsigned int, order, __fls(num_pages))) {
|
||||
bool apply_caching = false;
|
||||
struct ttm_pool_type *pt;
|
||||
|
||||
page_caching = tt->caching;
|
||||
pt = ttm_pool_select_type(pool, tt->caching, order);
|
||||
p = pt ? ttm_pool_type_take(pt) : NULL;
|
||||
if (p) {
|
||||
apply_caching = true;
|
||||
} else {
|
||||
p = ttm_pool_alloc_page(pool, gfp_flags, order, tt->dmat);
|
||||
if (p && PageHighMem(p))
|
||||
apply_caching = true;
|
||||
r = ttm_pool_apply_caching(caching, pages,
|
||||
tt->caching);
|
||||
if (r)
|
||||
goto error_free_page;
|
||||
|
||||
caching = pages;
|
||||
do {
|
||||
r = ttm_pool_page_allocated(pool, order, p,
|
||||
&dma_addr,
|
||||
&num_pages,
|
||||
&pages, &orders);
|
||||
if (r)
|
||||
goto error_free_page;
|
||||
|
||||
caching = pages;
|
||||
if (num_pages < (1 << order))
|
||||
break;
|
||||
|
||||
p = ttm_pool_type_take(pt);
|
||||
} while (p);
|
||||
}
|
||||
|
||||
page_caching = ttm_cached;
|
||||
while (num_pages >= (1 << order) &&
|
||||
(p = ttm_pool_alloc_page(pool, gfp_flags, order, tt->dmat))) {
|
||||
|
||||
if (PageHighMem(p)) {
|
||||
r = ttm_pool_apply_caching(caching, pages,
|
||||
tt->caching);
|
||||
if (r)
|
||||
goto error_free_page;
|
||||
caching = pages;
|
||||
}
|
||||
r = ttm_pool_page_allocated(pool, order, p, &dma_addr,
|
||||
&num_pages, &pages, &orders);
|
||||
if (r)
|
||||
goto error_free_page;
|
||||
if (PageHighMem(p))
|
||||
caching = pages;
|
||||
}
|
||||
|
||||
if (!p) {
|
||||
|
|
@ -550,26 +648,6 @@ int ttm_pool_alloc(struct ttm_pool *pool, struct ttm_tt *tt,
|
|||
r = -ENOMEM;
|
||||
goto error_free_all;
|
||||
}
|
||||
|
||||
if (apply_caching) {
|
||||
r = ttm_pool_apply_caching(caching, pages,
|
||||
tt->caching);
|
||||
if (r)
|
||||
goto error_free_page;
|
||||
caching = pages + (1 << order);
|
||||
}
|
||||
|
||||
if (dma_addr) {
|
||||
r = ttm_pool_map(pool, order, p, &dma_addr);
|
||||
if (r)
|
||||
goto error_free_page;
|
||||
}
|
||||
|
||||
num_pages -= 1 << order;
|
||||
for (i = 1 << order; i; --i) {
|
||||
*(pages++) = p++;
|
||||
*(orders++) = order;
|
||||
}
|
||||
}
|
||||
|
||||
r = ttm_pool_apply_caching(caching, pages, tt->caching);
|
||||
|
|
@ -579,15 +657,13 @@ int ttm_pool_alloc(struct ttm_pool *pool, struct ttm_tt *tt,
|
|||
return 0;
|
||||
|
||||
error_free_page:
|
||||
ttm_pool_free_page(pool, tt->caching, order, p);
|
||||
ttm_pool_free_page(pool, page_caching, order, p);
|
||||
|
||||
error_free_all:
|
||||
num_pages = tt->num_pages - num_pages;
|
||||
for (i = 0; i < num_pages; ) {
|
||||
order = tt->orders[i];
|
||||
ttm_pool_free_page(pool, tt->caching, order, tt->pages[i]);
|
||||
i += 1 << order;
|
||||
}
|
||||
caching_divide = caching - tt->pages;
|
||||
ttm_pool_free_range(pool, tt, tt->caching, 0, caching_divide);
|
||||
ttm_pool_free_range(pool, tt, ttm_cached, caching_divide, num_pages);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
|
@ -603,26 +679,7 @@ EXPORT_SYMBOL(ttm_pool_alloc);
|
|||
*/
|
||||
void ttm_pool_free(struct ttm_pool *pool, struct ttm_tt *tt)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < tt->num_pages; ) {
|
||||
unsigned int order, num_pages;
|
||||
struct ttm_pool_type *pt;
|
||||
|
||||
order = tt->orders[i];
|
||||
num_pages = 1ULL << order;
|
||||
if (tt->dma_address)
|
||||
ttm_pool_unmap(pool, tt->dma_address[i], num_pages);
|
||||
|
||||
pt = ttm_pool_select_type(pool, tt->caching, order);
|
||||
if (pt)
|
||||
ttm_pool_type_give(pt, tt->pages[i]);
|
||||
else
|
||||
ttm_pool_free_page(pool, tt->caching, order,
|
||||
tt->pages[i]);
|
||||
|
||||
i += num_pages;
|
||||
}
|
||||
ttm_pool_free_range(pool, tt, tt->caching, 0, tt->num_pages);
|
||||
|
||||
while (atomic_long_read(&allocated_pages) > page_pool_size)
|
||||
ttm_pool_shrink();
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue