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This commit is contained in:
purplerain 2023-05-13 14:25:18 +00:00
parent f609457dcf
commit 62073e0295
Signed by: purplerain
GPG key ID: F42C07F07E2E35B7
318 changed files with 8112 additions and 4346 deletions
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5
sys/dev/fdt/dwpcie.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: dwpcie.c,v 1.48 2023/04/27 09:03:06 kettenis Exp $ */
/* $OpenBSD: dwpcie.c,v 1.49 2023/05/03 15:25:25 jsg Exp $ */
/*
* Copyright (c) 2018 Mark Kettenis <kettenis@openbsd.org>
*
@ -1480,13 +1480,14 @@ dwpcie_rk3568_intr_disestablish(void *cookie)
evcount_detach(&di->di_count);
TAILQ_REMOVE(&sc->sc_intx[di->di_pin], di, di_next);
free(di, M_DEVBUF, sizeof(*di));
if (!TAILQ_EMPTY(&sc->sc_intx[di->di_pin])) {
/* Unmask the interrupt. */
bus_space_write_4(sc->sc_iot, sc->sc_glue_ioh,
PCIE_CLIENT_INTR_MASK_LEGACY, mask << 16);
}
free(di, M_DEVBUF, sizeof(*di));
}
void

2
sys/dev/pci/aac_pci.c
View file

@ -285,7 +285,7 @@ aac_pci_attach(parent, self, aux)
printf("%s\n", intrstr);
sc->aac_dmat = pa->pa_dmat;
for (m = aac_identifiers; m->vendor != 0; m++)
if (m->vendor == PCI_VENDOR(pa->pa_id) &&
m->device == PCI_PRODUCT(pa->pa_id)) {

8
sys/dev/pci/agp.c
View file

@ -64,7 +64,7 @@ agpbus_probe(struct agp_attach_args *aa)
struct pci_attach_args *pa = aa->aa_pa;
if (strncmp(aa->aa_busname, "agp", 3) == 0 &&
PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE &&
PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE &&
PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_HOST)
return (1);
return (0);
@ -215,7 +215,7 @@ agp_generic_enable(struct agp_softc *sc, u_int32_t mode)
struct pci_attach_args pa;
pcireg_t tstatus, mstatus, command;
int rq, sba, fw, rate, capoff;
if (pci_find_device(&pa, agpvga_match) == 0 ||
pci_get_capability(pa.pa_pc, pa.pa_tag, PCI_CAP_AGP,
&capoff, NULL) == 0) {
@ -359,7 +359,7 @@ agp_acquire(void *dev)
{
struct agp_softc *sc = (struct agp_softc *)dev;
if (sc->sc_chipc == NULL)
if (sc->sc_chipc == NULL)
return (EINVAL);
if (sc->sc_state != AGP_ACQUIRE_FREE)
@ -377,7 +377,7 @@ agp_release(void *dev)
if (sc->sc_state == AGP_ACQUIRE_FREE)
return (0);
if (sc->sc_state != AGP_ACQUIRE_KERNEL)
if (sc->sc_state != AGP_ACQUIRE_KERNEL)
return (EBUSY);
sc->sc_state = AGP_ACQUIRE_FREE;

6
sys/dev/pci/agp_ali.c
View file

@ -96,7 +96,7 @@ agp_ali_probe(struct device *parent, void *match, void *aux)
return (0);
}
void
void
agp_ali_attach(struct device *parent, struct device *self, void *aux)
{
struct agp_ali_softc *asc = (struct agp_ali_softc *)self;
@ -135,7 +135,7 @@ agp_ali_attach(struct device *parent, struct device *self, void *aux)
reg = pci_conf_read(asc->asc_pc, asc->asc_tag, AGP_ALI_ATTBASE);
reg = (reg & 0xff) | gatt->ag_physical;
pci_conf_write(asc->asc_pc, asc->asc_tag, AGP_ALI_ATTBASE, reg);
/* Enable the TLB. */
reg = pci_conf_read(asc->asc_pc, asc->asc_tag, AGP_ALI_TLBCTRL);
reg = (reg & ~0xff) | 0x10;
@ -179,7 +179,7 @@ agp_ali_restore(struct agp_ali_softc *asc)
/* Install the gatt and aperture size. */
pci_conf_write(asc->asc_pc, asc->asc_tag, AGP_ALI_ATTBASE,
asc->asc_attbase);
/* Enable the TLB. */
pci_conf_write(asc->asc_pc, asc->asc_tag, AGP_ALI_TLBCTRL,
asc->asc_tlbctrl);

8
sys/dev/pci/agp_i810.c
View file

@ -59,7 +59,7 @@
/* I810/I815 only, memory is in dcache */
#define INTEL_LOCAL 0x2
/* Memory is snooped, must not be accessed through gtt from the cpu. */
#define INTEL_COHERENT 0x6
#define INTEL_COHERENT 0x6
enum {
CHIP_NONE = 0, /* not integrated graphics */
@ -194,7 +194,7 @@ agp_i810_get_chiptype(struct pci_attach_args *pa)
return (CHIP_IRONLAKE);
break;
}
return (CHIP_NONE);
}
@ -379,7 +379,7 @@ agp_i810_attach(struct device *parent, struct device *self, void *aux)
/* FALLTHROUGH */
case CHIP_I915:
/* FALLTHROUGH */
case CHIP_I965:
case CHIP_I965:
/* FALLTHROUGH */
case CHIP_G33:
/* FALLTHROUGH */
@ -559,7 +559,7 @@ agp_i810_configure(struct agp_i810_softc *isc)
tmp = isc->isc_apaddr;
if (isc->chiptype == CHIP_I810) {
tmp += isc->dcache_size;
} else {
} else {
tmp += isc->stolen << AGP_PAGE_SHIFT;
}

10
sys/dev/pci/agp_intel.c
View file

@ -59,7 +59,7 @@ struct agp_intel_softc {
CHIP_I845,
CHIP_I850,
CHIP_I865
} chiptype;
} chiptype;
/* registers saved during a suspend/resume cycle. */
pcireg_t savectrl;
pcireg_t savecmd;
@ -115,7 +115,7 @@ agp_intel_probe(struct device *parent, void *match, void *aux)
case PCI_PRODUCT_INTEL_82840_HB:
case PCI_PRODUCT_INTEL_82845_HB:
case PCI_PRODUCT_INTEL_82845G_HB:
case PCI_PRODUCT_INTEL_82850_HB:
case PCI_PRODUCT_INTEL_82850_HB:
case PCI_PRODUCT_INTEL_82855PM_HB:
case PCI_PRODUCT_INTEL_82855GM_HB:
case PCI_PRODUCT_INTEL_82860_HB:
@ -202,7 +202,7 @@ agp_intel_attach(struct device *parent, struct device *self, void *aux)
/* Install the gatt. */
pci_conf_write(pa->pa_pc, pa->pa_tag, AGP_INTEL_ATTBASE,
gatt->ag_physical);
/* Enable the GLTB and setup the control register. */
switch (isc->chiptype) {
case CHIP_I443:
@ -262,7 +262,7 @@ agp_intel_attach(struct device *parent, struct device *self, void *aux)
pci_conf_write(isc->isc_pc, isc->isc_tag,
AGP_INTEL_ERRCMD, reg);
}
isc->agpdev = (struct agp_softc *)agp_attach_bus(pa, &agp_intel_methods,
isc->isc_apaddr, isc->isc_apsize, &isc->dev);
return;
@ -329,7 +329,7 @@ agp_intel_restore(struct agp_intel_softc *isc)
/* Install the gatt. */
pci_conf_write(isc->isc_pc, isc->isc_tag, AGP_INTEL_ATTBASE,
isc->gatt->ag_physical);
/* Enable the GLTB and setup the control register. */
switch (isc->chiptype) {
case CHIP_I443:

6
sys/dev/pci/agp_sis.c
View file

@ -135,7 +135,7 @@ agp_sis_attach(struct device *parent, struct device *self, void *aux)
/* Install the gatt. */
pci_conf_write(ssc->ssc_pc, ssc->ssc_tag, AGP_SIS_ATTBASE,
gatt->ag_physical);
/* Enable the aperture and auto-tlb-inval */
reg = pci_conf_read(ssc->ssc_pc, ssc->ssc_tag, AGP_SIS_WINCTRL);
reg |= (0x05 << 24) | 3;
@ -176,7 +176,7 @@ agp_sis_restore(struct agp_sis_softc *ssc)
/* Install the gatt. */
pci_conf_write(ssc->ssc_pc, ssc->ssc_tag, AGP_SIS_ATTBASE,
ssc->gatt->ag_physical);
/*
* Enable the aperture, reset the aperture size and enable and
* auto-tlb-inval.
@ -217,7 +217,7 @@ agp_sis_set_aperture(void *sc, bus_size_t aperture)
gws = ffs(aperture / 4*1024*1024) - 1;
reg = pci_conf_read(ssc->ssc_pc, ssc->ssc_tag, AGP_SIS_WINCTRL);
reg = pci_conf_read(ssc->ssc_pc, ssc->ssc_tag, AGP_SIS_WINCTRL);
reg &= ~0x00000070;
reg |= gws << 4;
pci_conf_write(ssc->ssc_pc, ssc->ssc_tag, AGP_SIS_WINCTRL, reg);

2
sys/dev/pci/agp_via.c
View file

@ -238,7 +238,7 @@ agp_via_get_aperture(void *sc)
struct agp_via_softc *vsc = sc;
bus_size_t apsize;
apsize = pci_conf_read(vsc->vsc_pc, vsc->vsc_tag,
apsize = pci_conf_read(vsc->vsc_pc, vsc->vsc_tag,
vsc->regs[REG_APSIZE]) & 0x1f;
/*

2
sys/dev/pci/agpreg.h
View file

@ -210,7 +210,7 @@
#define AGP_I810_MISCC_RPTC 0x00c0
#define AGP_I810_MISCC_RPTC_NOLIMIT 0x0000
#define AGP_I810_MISCC_RPTC_62 0x0040
#define AGP_I810_MISCC_RPTC_50 0x0080
#define AGP_I810_MISCC_RPTC_50 0x0080
#define AGP_I810_MISCC_RPTC_37 0x00c0
/*

2
sys/dev/pci/agpvar.h
View file

@ -105,7 +105,7 @@ struct agp_softc {
pcireg_t sc_id;
int sc_opened;
int sc_capoff;
int sc_capoff;
int sc_nextid; /* next mem block id */
enum agp_acquire_state sc_state;

16
sys/dev/pci/ahc_pci.c
View file

@ -459,7 +459,7 @@ const struct ahc_pci_identity ahc_pci_ident_table [] =
ID_ALL_MASK,
ahc_aic7892_setup
},
/* aic7895 based controllers */
/* aic7895 based controllers */
{
ID_AHA_2940U_DUAL,
ID_ALL_MASK,
@ -480,7 +480,7 @@ const struct ahc_pci_identity ahc_pci_ident_table [] =
ID_AIC7895_ARO_MASK,
ahc_aic7895_setup
},
/* aic7896/97 based controllers */
/* aic7896/97 based controllers */
{
ID_AHA_3950U2B_0,
ID_ALL_MASK,
@ -506,7 +506,7 @@ const struct ahc_pci_identity ahc_pci_ident_table [] =
ID_ALL_MASK,
ahc_aic7896_setup
},
/* aic7899 based controllers */
/* aic7899 based controllers */
{
ID_AHA_3960D,
ID_ALL_MASK,
@ -665,7 +665,7 @@ ahc_find_pci_device(pcireg_t id, pcireg_t subid, u_int func)
* ID as valid.
*/
if (func > 0
&& ahc_9005_subdevinfo_valid(PCI_VENDOR(id), PCI_PRODUCT(id),
&& ahc_9005_subdevinfo_valid(PCI_VENDOR(id), PCI_PRODUCT(id),
PCI_VENDOR(subid), PCI_PRODUCT(subid))
&& SUBID_9005_MFUNCENB(PCI_PRODUCT(subid)) == 0)
return (NULL);
@ -834,7 +834,7 @@ ahc_pci_attach(struct device *parent, struct device *self, void *aux)
ahc_name(ahc));
devconfig |= DACEN;
}
/* Ensure that pci error generation, a test feature, is disabled. */
devconfig |= PCIERRGENDIS;
@ -963,7 +963,7 @@ ahc_pci_attach(struct device *parent, struct device *self, void *aux)
M_NOWAIT | M_ZERO);
if (ahc->seep_config == NULL)
goto error_out;
/* See if we have a SEEPROM and perform auto-term */
ahc_check_extport(ahc, &sxfrctl1);
@ -1208,7 +1208,7 @@ ahc_probe_ext_scbram(struct ahc_softc *ahc)
fast = FALSE;
large = FALSE;
num_scbs = 0;
if (ahc_ext_scbram_present(ahc) == 0)
goto done;
@ -1402,7 +1402,7 @@ ahc_pci_intr(struct ahc_softc *ahc)
if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) {
printf("%s: Latched PCIERR interrupt with "
"no status bits set\n", ahc_name(ahc));
"no status bits set\n", ahc_name(ahc));
} else {
ahc_outb(ahc, CLRINT, CLRPARERR);
}

26
sys/dev/pci/ahd_pci.c
View file

@ -170,7 +170,7 @@ const struct ahd_pci_identity ahd_pci_ident_table[] =
ID_ALL_MASK,
ahd_aic7901A_setup
},
/* aic7902 based controllers */
/* aic7902 based controllers */
{
ID_AHA_29320,
ID_ALL_MASK,
@ -240,7 +240,7 @@ const struct ahd_pci_identity ahd_pci_ident_table[] =
};
const u_int ahd_num_pci_devs = NUM_ELEMENTS(ahd_pci_ident_table);
#define DEVCONFIG 0x40
#define PCIXINITPAT 0x0000E000ul
#define PCIXINIT_PCI33_66 0x0000E000ul
@ -342,7 +342,7 @@ ahd_pci_attach(struct device *parent, struct device *self, void *aux)
pci_intr_handle_t ih;
const char *intrstr;
pcireg_t devconfig, memtype, subid;
uint16_t device, subvendor;
uint16_t device, subvendor;
int error, ioh_valid, ioh2_valid, l, memh_valid;
ahd->dev_softc = pa;
@ -373,10 +373,10 @@ ahd_pci_attach(struct device *parent, struct device *self, void *aux)
error = entry->setup(ahd, pa);
if (error != 0)
return;
/* XXX ahc on sparc64 needs this twice */
devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG);
if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) {
ahd->chip |= AHD_PCI;
/* Disable PCIX workarounds when running in PCI mode. */
@ -482,7 +482,7 @@ ahd_pci_attach(struct device *parent, struct device *self, void *aux)
devconfig |= DACEN;
pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG, devconfig);
}
ahd_softc_init(ahd);
/*
@ -514,7 +514,7 @@ ahd_pci_attach(struct device *parent, struct device *self, void *aux)
}
if (intrstr != NULL)
printf(": %s\n", intrstr);
/* Get the size of the cache */
ahd->pci_cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG);
ahd->pci_cachesize *= 4;
@ -668,7 +668,7 @@ ahd_check_extport(struct ahd_softc *ahd)
/*
* Fetch VPD for this function and parse it.
*/
if (bootverbose)
if (bootverbose)
printf("%s: Reading VPD from SEEPROM...",
ahd_name(ahd));
@ -681,12 +681,12 @@ ahd_check_extport(struct ahd_softc *ahd)
/*bytestream*/TRUE);
if (error == 0)
error = ahd_parse_vpddata(ahd, &vpd);
if (bootverbose)
if (bootverbose)
printf("%s: VPD parsing %s\n",
ahd_name(ahd),
error == 0 ? "successful" : "failed");
if (bootverbose)
if (bootverbose)
printf("%s: Reading SEEPROM...", ahd_name(ahd));
/* Address is always in units of 16bit words */
@ -941,7 +941,7 @@ ahd_pci_intr(struct ahd_softc *ahd)
u_int intstat;
u_int i;
u_int reg;
intstat = ahd_inb(ahd, INTSTAT);
if ((intstat & SPLTINT) != 0)
@ -965,7 +965,7 @@ ahd_pci_intr(struct ahd_softc *ahd)
for (i = 0; i < 8; i++) {
u_int bit;
if (i == 5)
continue;
@ -980,7 +980,7 @@ ahd_pci_intr(struct ahd_softc *ahd)
pci_status_strings[bit],
pci_status_source[i]);
}
}
}
}
pci_status1 = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG , pci_status1);

24
sys/dev/pci/drm/amd/amdgpu/ObjectID.h
View file

@ -1,5 +1,5 @@
/*
* Copyright 2006-2007 Advanced Micro Devices, Inc.
* Copyright 2006-2007 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -37,13 +37,13 @@
#define GRAPH_OBJECT_TYPE_CONNECTOR 0x3
#define GRAPH_OBJECT_TYPE_ROUTER 0x4
/* deleted */
#define GRAPH_OBJECT_TYPE_DISPLAY_PATH 0x6
#define GRAPH_OBJECT_TYPE_DISPLAY_PATH 0x6
#define GRAPH_OBJECT_TYPE_GENERIC 0x7
/****************************************************/
/* Encoder Object ID Definition */
/****************************************************/
#define ENCODER_OBJECT_ID_NONE 0x00
#define ENCODER_OBJECT_ID_NONE 0x00
/* Radeon Class Display Hardware */
#define ENCODER_OBJECT_ID_INTERNAL_LVDS 0x01
@ -96,7 +96,7 @@
/****************************************************/
/* Connector Object ID Definition */
/****************************************************/
#define CONNECTOR_OBJECT_ID_NONE 0x00
#define CONNECTOR_OBJECT_ID_NONE 0x00
#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I 0x01
#define CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I 0x02
#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D 0x03
@ -158,7 +158,7 @@
#define RESERVED1_ID_MASK 0x0800
#define OBJECT_TYPE_MASK 0x7000
#define RESERVED2_ID_MASK 0x8000
#define OBJECT_ID_SHIFT 0x00
#define ENUM_ID_SHIFT 0x08
#define OBJECT_TYPE_SHIFT 0x0C
@ -179,14 +179,14 @@
/* Encoder Object ID definition - Shared with BIOS */
/****************************************************/
/*
#define ENCODER_INTERNAL_LVDS_ENUM_ID1 0x2101
#define ENCODER_INTERNAL_LVDS_ENUM_ID1 0x2101
#define ENCODER_INTERNAL_TMDS1_ENUM_ID1 0x2102
#define ENCODER_INTERNAL_TMDS2_ENUM_ID1 0x2103
#define ENCODER_INTERNAL_DAC1_ENUM_ID1 0x2104
#define ENCODER_INTERNAL_DAC2_ENUM_ID1 0x2105
#define ENCODER_INTERNAL_SDVOA_ENUM_ID1 0x2106
#define ENCODER_INTERNAL_SDVOB_ENUM_ID1 0x2107
#define ENCODER_SIL170B_ENUM_ID1 0x2108
#define ENCODER_SIL170B_ENUM_ID1 0x2108
#define ENCODER_CH7303_ENUM_ID1 0x2109
#define ENCODER_CH7301_ENUM_ID1 0x210A
#define ENCODER_INTERNAL_DVO1_ENUM_ID1 0x210B
@ -200,8 +200,8 @@
#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1 0x2113
#define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1 0x2114
#define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1 0x2115
#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 0x2116
#define ENCODER_SI178_ENUM_ID1 0x2117
#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 0x2116
#define ENCODER_SI178_ENUM_ID1 0x2117
#define ENCODER_MVPU_FPGA_ENUM_ID1 0x2118
#define ENCODER_INTERNAL_DDI_ENUM_ID1 0x2119
#define ENCODER_VT1625_ENUM_ID1 0x211A
@ -316,7 +316,7 @@
#define ENCODER_SI178_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_SI178 << OBJECT_ID_SHIFT)
ENCODER_OBJECT_ID_SI178 << OBJECT_ID_SHIFT)
#define ENCODER_MVPU_FPGA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
@ -324,7 +324,7 @@
#define ENCODER_INTERNAL_DDI_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_INTERNAL_DDI << OBJECT_ID_SHIFT)
ENCODER_OBJECT_ID_INTERNAL_DDI << OBJECT_ID_SHIFT)
#define ENCODER_VT1625_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
@ -352,7 +352,7 @@
#define ENCODER_INTERNAL_KLDSCP_LVTMA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA << OBJECT_ID_SHIFT)
ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA << OBJECT_ID_SHIFT)
#define ENCODER_INTERNAL_UNIPHY1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\

23
sys/dev/pci/drm/amd/amdgpu/amdgpu_device.c
View file

@ -35,6 +35,7 @@
#include <linux/devcoredump.h>
#include <generated/utsrelease.h>
#include <linux/pci-p2pdma.h>
#include <linux/apple-gmux.h>
#include <drm/drm_aperture.h>
#include <drm/drm_atomic_helper.h>
@ -4023,12 +4024,15 @@ fence_driver_init:
vga_client_register(adev->pdev, amdgpu_device_vga_set_decode);
#endif
if (amdgpu_device_supports_px(ddev)) {
px = true;
px = amdgpu_device_supports_px(ddev);
if (px || (!pci_is_thunderbolt_attached(adev->pdev) &&
apple_gmux_detect(NULL, NULL)))
vga_switcheroo_register_client(adev->pdev,
&amdgpu_switcheroo_ops, px);
if (px)
vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
}
if (adev->gmc.xgmi.pending_reset)
queue_delayed_work(system_wq, &mgpu_info.delayed_reset_work,
@ -4152,6 +4156,7 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev)
void amdgpu_device_fini_sw(struct amdgpu_device *adev)
{
int idx;
bool px;
amdgpu_fence_driver_sw_fini(adev);
amdgpu_device_ip_fini(adev);
@ -4171,10 +4176,16 @@ void amdgpu_device_fini_sw(struct amdgpu_device *adev)
kfree(adev->bios);
adev->bios = NULL;
if (amdgpu_device_supports_px(adev_to_drm(adev))) {
px = amdgpu_device_supports_px(adev_to_drm(adev));
if (px || (!pci_is_thunderbolt_attached(adev->pdev) &&
apple_gmux_detect(NULL, NULL)))
vga_switcheroo_unregister_client(adev->pdev);
if (px)
vga_switcheroo_fini_domain_pm_ops(adev->dev);
}
if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
vga_client_unregister(adev->pdev);
@ -6137,7 +6148,7 @@ int amdgpu_in_reset(struct amdgpu_device *adev)
{
return atomic_read(&adev->reset_domain->in_gpu_reset);
}
/**
* amdgpu_device_halt() - bring hardware to some kind of halt state
*

2
sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c
View file

@ -3418,7 +3418,7 @@ amdgpu_init_backlight(struct amdgpu_device *adev)
if (bd == NULL)
return;
drm_connector_list_iter_begin(dev, &conn_iter);
drm_for_each_connector_iter(connector, &conn_iter) {
if (connector->connector_type != DRM_MODE_CONNECTOR_LVDS &&

2
sys/dev/pci/drm/amd/amdgpu/amdgpu_object.c
View file

@ -1100,7 +1100,7 @@ void amdgpu_bo_fini(struct amdgpu_device *adev)
arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
#else
drm_mtrr_del(0, adev->gmc.aper_base, adev->gmc.aper_size, DRM_MTRR_WC);
#endif
}
drm_dev_exit(idx);

2
sys/dev/pci/drm/amd/amdgpu/amdgpu_vm.c
View file

@ -101,7 +101,7 @@ amdgpu_vm_it_iter_next(struct amdgpu_bo_va_mapping *node, uint64_t start,
static void
amdgpu_vm_it_remove(struct amdgpu_bo_va_mapping *node,
struct rb_root_cached *root)
struct rb_root_cached *root)
{
rb_erase_cached(&node->rb, root);
}

4
sys/dev/pci/drm/amd/amdgpu/gfx_v11_0.c
View file

@ -1906,7 +1906,7 @@ static int gfx_v11_0_rlc_load_microcode(struct amdgpu_device *adev)
if (version_minor == 3)
gfx_v11_0_load_rlcp_rlcv_microcode(adev);
}
return 0;
}
@ -3348,7 +3348,7 @@ static int gfx_v11_0_cp_compute_load_microcode(struct amdgpu_device *adev)
}
memcpy(fw, fw_data, fw_size);
amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);

8
sys/dev/pci/drm/amd/amdgpu/imu_v11_0.c
View file

@ -58,7 +58,7 @@ static int imu_v11_0_init_microcode(struct amdgpu_device *adev)
imu_hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data;
adev->gfx.imu_fw_version = le32_to_cpu(imu_hdr->header.ucode_version);
//adev->gfx.imu_feature_version = le32_to_cpu(imu_hdr->ucode_feature_version);
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_IMU_I];
info->ucode_id = AMDGPU_UCODE_ID_IMU_I;
@ -240,9 +240,9 @@ static const struct imu_rlc_ram_golden imu_rlc_ram_golden_11[] =
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_BOT, 0x00000002, 0xe0000000),
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCMC_VM_AGP_TOP, 0x00000000, 0xe0000000),
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL2, 0x00020000, 0xe0000000),
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA0_UCODE_SELFLOAD_CONTROL, 0x00000210, 0),
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA1_UCODE_SELFLOAD_CONTROL, 0x00000210, 0),
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCPC_PSP_DEBUG, CPC_PSP_DEBUG__GPA_OVERRIDE_MASK, 0),
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA0_UCODE_SELFLOAD_CONTROL, 0x00000210, 0),
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regSDMA1_UCODE_SELFLOAD_CONTROL, 0x00000210, 0),
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCPC_PSP_DEBUG, CPC_PSP_DEBUG__GPA_OVERRIDE_MASK, 0),
IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCPG_PSP_DEBUG, CPG_PSP_DEBUG__GPA_OVERRIDE_MASK, 0)
};

2
sys/dev/pci/drm/amd/amdgpu/mxgpu_ai.c
View file

@ -186,7 +186,7 @@ static int xgpu_ai_send_access_requests(struct amdgpu_device *adev,
/* Dummy REQ_GPU_INIT_DATA handling */
r = xgpu_ai_poll_msg(adev, IDH_REQ_GPU_INIT_DATA_READY);
/* version set to 0 since dummy */
adev->virt.req_init_data_ver = 0;
adev->virt.req_init_data_ver = 0;
}
return 0;

2
sys/dev/pci/drm/amd/amdgpu/sdma_v5_0.c
View file

@ -273,7 +273,7 @@ static int sdma_v5_0_init_microcode(struct amdgpu_device *adev)
if (ret)
return ret;
}
return ret;
}

3
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
View file

@ -1765,7 +1765,8 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev)
dc_deinit_callbacks(adev->dm.dc);
#endif
dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
if (adev->dm.dc)
dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);
if (dc_enable_dmub_notifications(adev->dm.dc)) {
kfree(adev->dm.dmub_notify);

3
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
View file

@ -122,6 +122,9 @@ bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream)
psr_config.allow_multi_disp_optimizations =
(amdgpu_dc_feature_mask & DC_PSR_ALLOW_MULTI_DISP_OPT);
if (!psr_su_set_y_granularity(dc, link, stream, &psr_config))
return false;
ret = dc_link_setup_psr(link, stream, &psr_config, &psr_context);
}

4
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.h
View file

@ -26,6 +26,8 @@
#ifndef DAL_DC_RN_CLK_MGR_VBIOS_SMU_H_
#define DAL_DC_RN_CLK_MGR_VBIOS_SMU_H_
enum dcn_pwr_state;
int rn_vbios_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
int rn_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
int rn_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr);
@ -33,7 +35,7 @@ int rn_vbios_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int reque
int rn_vbios_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz);
void rn_vbios_smu_set_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz);
int rn_vbios_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
void rn_vbios_smu_set_dcn_low_power_state(struct clk_mgr_internal *clk_mgr, int display_count);
void rn_vbios_smu_set_dcn_low_power_state(struct clk_mgr_internal *clk_mgr, enum dcn_pwr_state);
void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
void rn_vbios_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
int rn_vbios_smu_is_periodic_retraining_disabled(struct clk_mgr_internal *clk_mgr);

16
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_resource.c
View file

@ -1641,7 +1641,8 @@ noinline bool dcn30_internal_validate_bw(
display_e2e_pipe_params_st *pipes,
int *pipe_cnt_out,
int *vlevel_out,
bool fast_validate)
bool fast_validate,
bool allow_self_refresh_only)
{
bool out = false;
bool repopulate_pipes = false;
@ -1668,7 +1669,7 @@ noinline bool dcn30_internal_validate_bw(
dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt);
if (!fast_validate) {
if (!fast_validate || !allow_self_refresh_only) {
/*
* DML favors voltage over p-state, but we're more interested in
* supporting p-state over voltage. We can't support p-state in
@ -1681,11 +1682,12 @@ noinline bool dcn30_internal_validate_bw(
if (vlevel < context->bw_ctx.dml.soc.num_states)
vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
}
if (fast_validate || vlevel == context->bw_ctx.dml.soc.num_states ||
vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported) {
if (allow_self_refresh_only &&
(fast_validate || vlevel == context->bw_ctx.dml.soc.num_states ||
vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported)) {
/*
* If mode is unsupported or there's still no p-state support then
* fall back to favoring voltage.
* If mode is unsupported or there's still no p-state support
* then fall back to favoring voltage.
*
* We don't actually support prefetch mode 2, so require that we
* at least support prefetch mode 1.
@ -2056,7 +2058,7 @@ bool dcn30_validate_bandwidth(struct dc *dc,
BW_VAL_TRACE_COUNT();
DC_FP_START();
out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate);
out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate, true);
DC_FP_END();
if (pipe_cnt == 0)

3
sys/dev/pci/drm/amd/display/dc/dcn30/dcn30_resource.h
View file

@ -64,7 +64,8 @@ bool dcn30_internal_validate_bw(
display_e2e_pipe_params_st *pipes,
int *pipe_cnt_out,
int *vlevel_out,
bool fast_validate);
bool fast_validate,
bool allow_self_refresh_only);
void dcn30_calculate_wm_and_dlg(
struct dc *dc, struct dc_state *context,
display_e2e_pipe_params_st *pipes,

2
sys/dev/pci/drm/amd/display/dc/dcn31/dcn31_resource.c
View file

@ -1770,7 +1770,7 @@ bool dcn31_validate_bandwidth(struct dc *dc,
BW_VAL_TRACE_COUNT();
DC_FP_START();
out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate);
out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate, true);
DC_FP_END();
// Disable fast_validate to set min dcfclk in alculate_wm_and_dlg

77
sys/dev/pci/drm/amd/display/dc/dcn314/dcn314_resource.c
View file

@ -1689,6 +1689,81 @@ static void dcn314_get_panel_config_defaults(struct dc_panel_config *panel_confi
*panel_config = panel_config_defaults;
}
static bool filter_modes_for_single_channel_workaround(struct dc *dc,
struct dc_state *context)
{
// Filter 2K@240Hz+8K@24fps above combination timing if memory only has single dimm LPDDR
if (dc->clk_mgr->bw_params->vram_type == 34 && dc->clk_mgr->bw_params->num_channels < 2) {
int total_phy_pix_clk = 0;
for (int i = 0; i < context->stream_count; i++)
if (context->res_ctx.pipe_ctx[i].stream)
total_phy_pix_clk += context->res_ctx.pipe_ctx[i].stream->phy_pix_clk;
if (total_phy_pix_clk >= (1148928+826260)) //2K@240Hz+8K@24fps
return true;
}
return false;
}
bool dcn314_validate_bandwidth(struct dc *dc,
struct dc_state *context,
bool fast_validate)
{
bool out = false;
BW_VAL_TRACE_SETUP();
int vlevel = 0;
int pipe_cnt = 0;
display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
DC_LOGGER_INIT(dc->ctx->logger);
BW_VAL_TRACE_COUNT();
if (filter_modes_for_single_channel_workaround(dc, context))
goto validate_fail;
DC_FP_START();
// do not support self refresh only
out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate, false);
DC_FP_END();
// Disable fast_validate to set min dcfclk in calculate_wm_and_dlg
if (pipe_cnt == 0)
fast_validate = false;
if (!out)
goto validate_fail;
BW_VAL_TRACE_END_VOLTAGE_LEVEL();
if (fast_validate) {
BW_VAL_TRACE_SKIP(fast);
goto validate_out;
}
dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
BW_VAL_TRACE_END_WATERMARKS();
goto validate_out;
validate_fail:
DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
BW_VAL_TRACE_SKIP(fail);
out = false;
validate_out:
kfree(pipes);
BW_VAL_TRACE_FINISH();
return out;
}
static struct resource_funcs dcn314_res_pool_funcs = {
.destroy = dcn314_destroy_resource_pool,
.link_enc_create = dcn31_link_encoder_create,
@ -1696,7 +1771,7 @@ static struct resource_funcs dcn314_res_pool_funcs = {
.link_encs_assign = link_enc_cfg_link_encs_assign,
.link_enc_unassign = link_enc_cfg_link_enc_unassign,
.panel_cntl_create = dcn31_panel_cntl_create,
.validate_bandwidth = dcn31_validate_bandwidth,
.validate_bandwidth = dcn314_validate_bandwidth,
.calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg,
.update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
.populate_dml_pipes = dcn314_populate_dml_pipes_from_context,

4
sys/dev/pci/drm/amd/display/dc/dcn314/dcn314_resource.h
View file

@ -39,6 +39,10 @@ struct dcn314_resource_pool {
struct resource_pool base;
};
bool dcn314_validate_bandwidth(struct dc *dc,
struct dc_state *context,
bool fast_validate);
struct resource_pool *dcn314_create_resource_pool(
const struct dc_init_data *init_data,
struct dc *dc);

2
sys/dev/pci/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
View file

@ -636,7 +636,7 @@ int dcn30_find_dummy_latency_index_for_fw_based_mclk_switch(struct dc *dc,
while (dummy_latency_index < max_latency_table_entries) {
context->bw_ctx.dml.soc.dram_clock_change_latency_us =
dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dummy_pstate_latency_us;
dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false);
dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false, true);
if (context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank ==
dm_allow_self_refresh_and_mclk_switch)

35
sys/dev/pci/drm/amd/display/modules/power/power_helpers.c
View file

@ -907,3 +907,38 @@ bool mod_power_only_edp(const struct dc_state *context, const struct dc_stream_s
{
return context && context->stream_count == 1 && dc_is_embedded_signal(stream->signal);
}
bool psr_su_set_y_granularity(struct dc *dc, struct dc_link *link,
struct dc_stream_state *stream,
struct psr_config *config)
{
uint16_t pic_height;
uint8_t slice_height;
if ((link->connector_signal & SIGNAL_TYPE_EDP) &&
(!dc->caps.edp_dsc_support ||
link->panel_config.dsc.disable_dsc_edp ||
!link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT ||
!stream->timing.dsc_cfg.num_slices_v))
return true;
pic_height = stream->timing.v_addressable +
stream->timing.v_border_top + stream->timing.v_border_bottom;
if (stream->timing.dsc_cfg.num_slices_v == 0)
return false;
slice_height = pic_height / stream->timing.dsc_cfg.num_slices_v;
if (slice_height) {
if (config->su_y_granularity &&
(slice_height % config->su_y_granularity)) {
ASSERT(0);
return false;
}
config->su_y_granularity = slice_height;
}
return true;
}

3
sys/dev/pci/drm/amd/display/modules/power/power_helpers.h
View file

@ -59,4 +59,7 @@ void mod_power_calc_psr_configs(struct psr_config *psr_config,
const struct dc_stream_state *stream);
bool mod_power_only_edp(const struct dc_state *context,
const struct dc_stream_state *stream);
bool psr_su_set_y_granularity(struct dc *dc, struct dc_link *link,
struct dc_stream_state *stream,
struct psr_config *config);
#endif /* MODULES_POWER_POWER_HELPERS_H_ */

2
sys/dev/pci/drm/amd/include/amd_shared.h
View file

@ -60,7 +60,7 @@ enum amd_apu_flags {
* acquires the list of IP blocks for the GPU in use on initialization.
* It can then operate on this list to perform standard driver operations
* such as: init, fini, suspend, resume, etc.
*
*
*
* IP block implementations are named using the following convention:
* <functionality>_v<version> (E.g.: gfx_v6_0).

534
sys/dev/pci/drm/amd/include/atomfirmware.h
View file

File diff suppressed because it is too large Load diff

4
sys/dev/pci/drm/amd/include/atomfirmwareid.h
View file

@ -1,12 +1,12 @@
/****************************************************************************\
*
*
* File Name atomfirmwareid.h
*
* Description ATOM BIOS command/data table ID definition header file
*
* Copyright 2016 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
* and associated documentation files (the "Software"), to deal in the Software without restriction,
* including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so,

22
sys/dev/pci/drm/amd/include/displayobject.h
View file

@ -1,14 +1,14 @@
/****************************************************************************\
*
*
* Module Name displayobjectsoc15.h
* Project
* Device
* Project
* Device
*
* Description Contains the common definitions for display objects for SoC15 products.
*
* Copyright 2014 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
* and associated documentation files (the "Software"), to deal in the Software without restriction,
* including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so,
@ -35,7 +35,7 @@
/****************************************************
* Display Object Type Definition
* Display Object Type Definition
*****************************************************/
enum display_object_type{
DISPLAY_OBJECT_TYPE_NONE =0x00,
@ -45,7 +45,7 @@ DISPLAY_OBJECT_TYPE_CONNECTOR =0x03
};
/****************************************************
* Encorder Object Type Definition
* Encorder Object Type Definition
*****************************************************/
enum encoder_object_type{
ENCODER_OBJECT_ID_NONE =0x00,
@ -56,11 +56,11 @@ ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 =0x03,
/****************************************************
* Connector Object ID Definition
* Connector Object ID Definition
*****************************************************/
enum connector_object_type{
CONNECTOR_OBJECT_ID_NONE =0x00,
CONNECTOR_OBJECT_ID_NONE =0x00,
CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D =0x01,
CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D =0x02,
CONNECTOR_OBJECT_ID_HDMI_TYPE_A =0x03,
@ -72,12 +72,12 @@ CONNECTOR_OBJECT_ID_OPM =0x07
/****************************************************
* Protection Object ID Definition
* Protection Object ID Definition
*****************************************************/
//No need
/****************************************************
* Object ENUM ID Definition
* Object ENUM ID Definition
*****************************************************/
enum object_enum_id{
@ -90,7 +90,7 @@ OBJECT_ENUM_ID6 =0x06
};
/****************************************************
*Object ID Bit definition
*Object ID Bit definition
*****************************************************/
enum object_id_bit{
OBJECT_ID_MASK =0x00FF,

2
sys/dev/pci/drm/amd/include/navi10_ip_offset.h
View file

@ -28,7 +28,7 @@
struct IP_BASE_INSTANCE {
unsigned int segment[MAX_SEGMENT];
};
struct IP_BASE {
struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
} __maybe_unused;

42
sys/dev/pci/drm/amd/include/pptable.h
View file

@ -133,7 +133,7 @@ typedef struct _ATOM_PPLIB_EXTENDEDHEADER
USHORT usUVDTableOffset; //points to ATOM_PPLIB_UVD_Table
USHORT usSAMUTableOffset; //points to ATOM_PPLIB_SAMU_Table
USHORT usPPMTableOffset; //points to ATOM_PPLIB_PPM_Table
USHORT usACPTableOffset; //points to ATOM_PPLIB_ACP_Table
USHORT usACPTableOffset; //points to ATOM_PPLIB_ACP_Table
/* points to ATOM_PPLIB_POWERTUNE_Table */
USHORT usPowerTuneTableOffset;
/* points to ATOM_PPLIB_CLOCK_Voltage_Dependency_Table for sclkVddgfxTable */
@ -223,14 +223,14 @@ typedef struct _ATOM_PPLIB_POWERPLAYTABLE3
typedef struct _ATOM_PPLIB_POWERPLAYTABLE4
{
ATOM_PPLIB_POWERPLAYTABLE3 basicTable3;
ULONG ulGoldenPPID; // PPGen use only
ULONG ulGoldenPPID; // PPGen use only
ULONG ulGoldenRevision; // PPGen use only
USHORT usVddcDependencyOnSCLKOffset;
USHORT usVddciDependencyOnMCLKOffset;
USHORT usVddcDependencyOnMCLKOffset;
USHORT usMaxClockVoltageOnDCOffset;
USHORT usVddcPhaseShedLimitsTableOffset; // Points to ATOM_PPLIB_PhaseSheddingLimits_Table
USHORT usMvddDependencyOnMCLKOffset;
USHORT usMvddDependencyOnMCLKOffset;
} ATOM_PPLIB_POWERPLAYTABLE4, *LPATOM_PPLIB_POWERPLAYTABLE4;
typedef struct _ATOM_PPLIB_POWERPLAYTABLE5
@ -376,21 +376,21 @@ typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO
UCHAR ucMaxHTLinkWidth; // From SBIOS - {2, 4, 8, 16}
UCHAR ucMinHTLinkWidth; // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled. Minimum down stream width could
USHORT usHTLinkFreq; // See definition ATOM_PPLIB_RS780_HTLINKFREQ_xxx or in MHz(>=200).
ULONG ulFlags;
ULONG ulFlags;
} ATOM_PPLIB_RS780_CLOCK_INFO;
#define ATOM_PPLIB_RS780_VOLTAGE_NONE 0
#define ATOM_PPLIB_RS780_VOLTAGE_LOW 1
#define ATOM_PPLIB_RS780_VOLTAGE_HIGH 2
#define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE 3
#define ATOM_PPLIB_RS780_VOLTAGE_NONE 0
#define ATOM_PPLIB_RS780_VOLTAGE_LOW 1
#define ATOM_PPLIB_RS780_VOLTAGE_HIGH 2
#define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE 3
#define ATOM_PPLIB_RS780_SPMCLK_NONE 0 // We cannot change the side port memory clock, leave it as it is.
#define ATOM_PPLIB_RS780_SPMCLK_LOW 1
#define ATOM_PPLIB_RS780_SPMCLK_HIGH 2
#define ATOM_PPLIB_RS780_HTLINKFREQ_NONE 0
#define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1
#define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2
#define ATOM_PPLIB_RS780_HTLINKFREQ_NONE 0
#define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1
#define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2
typedef struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO
{
@ -432,14 +432,14 @@ typedef struct _ATOM_PPLIB_CI_CLOCK_INFO
USHORT usMemoryClockLow;
UCHAR ucMemoryClockHigh;
UCHAR ucPCIEGen;
USHORT usPCIELane;
} ATOM_PPLIB_CI_CLOCK_INFO;
typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO{
USHORT usEngineClockLow; //clockfrequency & 0xFFFF. The unit is in 10khz
UCHAR ucEngineClockHigh; //clockfrequency >> 16.
UCHAR ucEngineClockHigh; //clockfrequency >> 16.
UCHAR vddcIndex; //2-bit vddc index;
USHORT tdpLimit;
//please initalize to 0
@ -464,10 +464,10 @@ typedef struct _ATOM_PPLIB_CZ_CLOCK_INFO {
typedef struct _ATOM_PPLIB_STATE_V2
{
//number of valid dpm levels in this state; Driver uses it to calculate the whole
//number of valid dpm levels in this state; Driver uses it to calculate the whole
//size of the state: sizeof(ATOM_PPLIB_STATE_V2) + (ucNumDPMLevels - 1) * sizeof(UCHAR)
UCHAR ucNumDPMLevels;
//a index to the array of nonClockInfos
UCHAR nonClockInfoIndex;
/**
@ -477,9 +477,9 @@ typedef struct _ATOM_PPLIB_STATE_V2
} ATOM_PPLIB_STATE_V2;
typedef struct _StateArray{
//how many states we have
//how many states we have
UCHAR ucNumEntries;
ATOM_PPLIB_STATE_V2 states[1];
}StateArray;
@ -487,10 +487,10 @@ typedef struct _StateArray{
typedef struct _ClockInfoArray{
//how many clock levels we have
UCHAR ucNumEntries;
//sizeof(ATOM_PPLIB_CLOCK_INFO)
UCHAR ucEntrySize;
UCHAR clockInfo[1];
}ClockInfoArray;
@ -500,7 +500,7 @@ typedef struct _NonClockInfoArray{
UCHAR ucNumEntries;
//sizeof(ATOM_PPLIB_NONCLOCK_INFO)
UCHAR ucEntrySize;
ATOM_PPLIB_NONCLOCK_INFO nonClockInfo[1];
}NonClockInfoArray;
@ -722,7 +722,7 @@ typedef struct _ATOM_PPLIB_PPM_Table
ULONG ulPlatformTDC;
ULONG ulSmallACPlatformTDC;
ULONG ulApuTDP;
ULONG ulDGpuTDP;
ULONG ulDGpuTDP;
ULONG ulDGpuUlvPower;
ULONG ulTjmax;
} ATOM_PPLIB_PPM_Table;

10
sys/dev/pci/drm/amd/pm/powerplay/inc/vega12/smu9_driver_if.h
View file

@ -365,7 +365,7 @@ typedef struct {
uint16_t FanMaximumRpm;
uint16_t FanTargetTemperature;
uint16_t FanTargetGfxclk;
uint8_t FanZeroRpmEnable;
uint8_t FanZeroRpmEnable;
uint8_t FanTachEdgePerRev;
@ -659,8 +659,8 @@ typedef struct {
uint8_t Gfx_IdleHystLimit;
uint8_t Gfx_FPS;
uint8_t Gfx_MinActiveFreqType;
uint8_t Gfx_BoosterFreqType;
uint8_t Gfx_UseRlcBusy;
uint8_t Gfx_BoosterFreqType;
uint8_t Gfx_UseRlcBusy;
uint16_t Gfx_MinActiveFreq;
uint16_t Gfx_BoosterFreq;
uint16_t Gfx_PD_Data_time_constant;
@ -674,7 +674,7 @@ typedef struct {
uint8_t Soc_IdleHystLimit;
uint8_t Soc_FPS;
uint8_t Soc_MinActiveFreqType;
uint8_t Soc_BoosterFreqType;
uint8_t Soc_BoosterFreqType;
uint8_t Soc_UseRlcBusy;
uint16_t Soc_MinActiveFreq;
uint16_t Soc_BoosterFreq;
@ -690,7 +690,7 @@ typedef struct {
uint8_t Mem_FPS;
uint8_t Mem_MinActiveFreqType;
uint8_t Mem_BoosterFreqType;
uint8_t Mem_UseRlcBusy;
uint8_t Mem_UseRlcBusy;
uint16_t Mem_MinActiveFreq;
uint16_t Mem_BoosterFreq;
uint16_t Mem_PD_Data_time_constant;

40
sys/dev/pci/drm/amd/pm/swsmu/amdgpu_smu.c
View file

@ -161,10 +161,15 @@ int smu_get_dpm_freq_range(struct smu_context *smu,
int smu_set_gfx_power_up_by_imu(struct smu_context *smu)
{
if (!smu->ppt_funcs && !smu->ppt_funcs->set_gfx_power_up_by_imu)
return -EOPNOTSUPP;
int ret = 0;
struct amdgpu_device *adev = smu->adev;
return smu->ppt_funcs->set_gfx_power_up_by_imu(smu);
if (smu->ppt_funcs->set_gfx_power_up_by_imu) {
ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu);
if (ret)
dev_err(adev->dev, "Failed to enable gfx imu!\n");
}
return ret;
}
static u32 smu_get_mclk(void *handle, bool low)
@ -195,6 +200,19 @@ static u32 smu_get_sclk(void *handle, bool low)
return clk_freq * 100;
}
static int smu_set_gfx_imu_enable(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
return 0;
if (amdgpu_in_reset(smu->adev) || adev->in_s0ix)
return 0;
return smu_set_gfx_power_up_by_imu(smu);
}
static int smu_dpm_set_vcn_enable(struct smu_context *smu,
bool enable)
{
@ -1386,15 +1404,9 @@ static int smu_hw_init(void *handle)
}
if (smu->is_apu) {
if ((smu->ppt_funcs->set_gfx_power_up_by_imu) &&
likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu);
if (ret) {
dev_err(adev->dev, "Failed to Enable gfx imu!\n");
return ret;
}
}
ret = smu_set_gfx_imu_enable(smu);
if (ret)
return ret;
smu_dpm_set_vcn_enable(smu, true);
smu_dpm_set_jpeg_enable(smu, true);
smu_set_gfx_cgpg(smu, true);
@ -1670,6 +1682,10 @@ static int smu_resume(void *handle)
return ret;
}
ret = smu_set_gfx_imu_enable(smu);
if (ret)
return ret;
smu_set_gfx_cgpg(smu, true);
smu->disable_uclk_switch = 0;

4
sys/dev/pci/drm/amd/pm/swsmu/inc/amdgpu_smu.h
View file

@ -1312,8 +1312,8 @@ struct pptable_funcs {
* @get_ecc_table: message SMU to get ECC INFO table.
*/
ssize_t (*get_ecc_info)(struct smu_context *smu, void *table);
/**
* @stb_collect_info: Collects Smart Trace Buffers data.
*/

12
sys/dev/pci/drm/drm_drv.c
View file

@ -90,7 +90,7 @@ DEFINE_STATIC_SRCU(drm_unplug_srcu);
* Some functions are only called once on init regardless of how many times
* drm attaches. In linux this is handled via module_init()/module_exit()
*/
int drm_refcnt;
int drm_refcnt;
struct drm_softc {
struct device sc_dev;
@ -1225,7 +1225,7 @@ drm_attach_pci(const struct drm_driver *driver, struct pci_attach_args *pa,
sc = (struct drm_softc *)config_found_sm(dev, &arg, drmprint, drmsubmatch);
if (sc == NULL)
return NULL;
return sc->sc_drm;
}
@ -1522,7 +1522,7 @@ const struct pci_device_id *
drm_find_description(int vendor, int device, const struct pci_device_id *idlist)
{
int i = 0;
for (i = 0; idlist[i].vendor != 0; i++) {
if ((idlist[i].vendor == vendor) &&
(idlist[i].device == device ||
@ -1546,7 +1546,7 @@ struct drm_file *
drm_find_file_by_minor(struct drm_device *dev, int minor)
{
struct drm_file key;
key.fminor = minor;
return (SPLAY_FIND(drm_file_tree, &dev->files, &key));
}
@ -1886,7 +1886,7 @@ drm_dmamem_alloc(bus_dma_tag_t dmat, bus_size_t size, bus_size_t alignment,
struct drm_dmamem *mem;
size_t strsize;
/*
* segs is the last member of the struct since we modify the size
* segs is the last member of the struct since we modify the size
* to allow extra segments if more than one are allowed.
*/
strsize = sizeof(*mem) + (sizeof(bus_dma_segment_t) * (nsegments - 1));
@ -1904,7 +1904,7 @@ drm_dmamem_alloc(bus_dma_tag_t dmat, bus_size_t size, bus_size_t alignment,
&mem->nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO) != 0)
goto destroy;
if (bus_dmamem_map(dmat, mem->segs, mem->nsegs, size,
if (bus_dmamem_map(dmat, mem->segs, mem->nsegs, size,
&mem->kva, BUS_DMA_NOWAIT | mapflags) != 0)
goto free;

8
sys/dev/pci/drm/drm_gem.c
View file

@ -102,7 +102,7 @@ drm_fault(struct uvm_faultinfo *ufi, vaddr_t vaddr, vm_page_t *pps,
* we do not allow device mappings to be mapped copy-on-write
* so we kill any attempt to do so here.
*/
if (UVM_ET_ISCOPYONWRITE(entry)) {
uvmfault_unlockall(ufi, ufi->entry->aref.ar_amap, uobj);
return(VM_PAGER_ERROR);
@ -144,7 +144,7 @@ drm_fault(struct uvm_faultinfo *ufi, vaddr_t vaddr, vm_page_t *pps,
return (ret);
}
boolean_t
boolean_t
drm_flush(struct uvm_object *uobj, voff_t start, voff_t stop, int flags)
{
return (TRUE);
@ -309,10 +309,10 @@ int drm_gem_object_init(struct drm_device *dev,
printf("%s size too big %lu\n", __func__, size);
return -ENOMEM;
}
obj->uao = uao_create(size, 0);
uvm_obj_init(&obj->uobj, &drm_pgops, 1);
return 0;
}

36
sys/dev/pci/drm/drm_linux.c
View file

@ -251,7 +251,7 @@ kthread_run(int (*func)(void *), void *data, const char *name)
thread->func = func;
thread->data = data;
thread->flags = 0;
if (kthread_create(kthread_func, thread, &thread->proc, name)) {
free(thread, M_DRM, sizeof(*thread));
return ERR_PTR(-ENOMEM);
@ -272,7 +272,7 @@ kthread_create_worker(unsigned int flags, const char *fmt, ...)
vsnprintf(name, sizeof(name), fmt, ap);
va_end(ap);
w->tq = taskq_create(name, 1, IPL_HIGH, 0);
return w;
}
@ -281,7 +281,7 @@ kthread_destroy_worker(struct kthread_worker *worker)
{
taskq_destroy(worker->tq);
free(worker, M_DRM, sizeof(*worker));
}
void
@ -551,7 +551,7 @@ __free_pages(struct vm_page *page, unsigned int order)
{
struct pglist mlist;
int i;
TAILQ_INIT(&mlist);
for (i = 0; i < (1 << order); i++)
TAILQ_INSERT_TAIL(&mlist, &page[i], pageq);
@ -623,7 +623,7 @@ void
kunmap_atomic(void *addr)
{
KASSERT(kmap_atomic_inuse);
pmap_kremove(kmap_atomic_va, PAGE_SIZE);
kmap_atomic_inuse = 0;
}
@ -1193,7 +1193,7 @@ retry:
int
i2c_transfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
{
int ret;
int ret;
if (adap->lock_ops)
adap->lock_ops->lock_bus(adap, 0);
@ -1497,7 +1497,7 @@ backlight_device_register(const char *name, void *kdev, void *data,
bd->data = data;
task_set(&bd->task, backlight_do_update_status, bd);
return bd;
}
@ -1720,7 +1720,7 @@ dma_fence_wait(struct dma_fence *fence, bool intr)
ret = dma_fence_wait_timeout(fence, intr, MAX_SCHEDULE_TIMEOUT);
if (ret < 0)
return ret;
return 0;
}
@ -1880,7 +1880,7 @@ dma_fence_default_wait(struct dma_fence *fence, bool intr, signed long timeout)
list_del(&cb.base.node);
out:
mtx_leave(fence->lock);
return ret;
}
@ -1926,7 +1926,7 @@ dma_fence_wait_any_timeout(struct dma_fence **fences, uint32_t count,
cb = mallocarray(count, sizeof(*cb), M_DRM, M_WAITOK|M_CANFAIL|M_ZERO);
if (cb == NULL)
return -ENOMEM;
for (i = 0; i < count; i++) {
struct dma_fence *fence = fences[i];
cb[i].proc = curproc;
@ -2022,7 +2022,7 @@ dma_fence_array_cb_func(struct dma_fence *f, struct dma_fence_cb *cb)
struct dma_fence_array_cb *array_cb =
container_of(cb, struct dma_fence_array_cb, cb);
struct dma_fence_array *dfa = array_cb->array;
if (atomic_dec_and_test(&dfa->num_pending))
timeout_add(&dfa->to, 1);
else
@ -2046,7 +2046,7 @@ dma_fence_array_enable_signaling(struct dma_fence *fence)
return false;
}
}
return true;
}
@ -2526,7 +2526,7 @@ pcie_get_speed_cap(struct pci_dev *pdev)
tag = pdev->tag;
if (!pci_get_capability(pc, tag, PCI_CAP_PCIEXPRESS,
&pos, NULL))
&pos, NULL))
return PCI_SPEED_UNKNOWN;
id = pci_conf_read(pc, tag, PCI_ID_REG);
@ -2582,7 +2582,7 @@ pcie_get_width_cap(struct pci_dev *pdev)
int bus, device, function;
if (!pci_get_capability(pc, tag, PCI_CAP_PCIEXPRESS,
&pos, NULL))
&pos, NULL))
return PCIE_LNK_WIDTH_UNKNOWN;
id = pci_conf_read(pc, tag, PCI_ID_REG);
@ -2607,13 +2607,13 @@ pcie_aspm_enabled(struct pci_dev *pdev)
pcireg_t lcsr;
if (!pci_get_capability(pc, tag, PCI_CAP_PCIEXPRESS,
&pos, NULL))
&pos, NULL))
return false;
lcsr = pci_conf_read(pc, tag, pos + PCI_PCIE_LCSR);
if ((lcsr & (PCI_PCIE_LCSR_ASPM_L0S | PCI_PCIE_LCSR_ASPM_L1)) != 0)
return true;
return false;
}
@ -2896,7 +2896,7 @@ interval_tree_iter_first(struct rb_root_cached *root, unsigned long start,
void
interval_tree_remove(struct interval_tree_node *node,
struct rb_root_cached *root)
struct rb_root_cached *root)
{
rb_erase_cached(&node->rb, root);
}
@ -3021,7 +3021,7 @@ fput(struct file *fp)
{
if (fp->f_type != DTYPE_SYNC)
return;
FRELE(fp, curproc);
}

2
sys/dev/pci/drm/drm_lock.c
View file

@ -223,7 +223,7 @@ int drm_legacy_lock(struct drm_device *dev, void *data,
ret ? "interrupted" : "has lock");
if (ret) return ret;
/* don't set the block all signals on the master process for now
/* don't set the block all signals on the master process for now
* really probably not the correct answer but lets us debug xkb
* xserver for now */
if (!drm_is_current_master(file_priv)) {

2
sys/dev/pci/drm/drm_managed.c
View file

@ -95,7 +95,7 @@ drmm_kfree(struct drm_device *dev, void *p)
}
}
mtx_leave(&dev->managed.lock);
if (m != NULL) {
free(m->p, M_DRM, m->size);
free(m, M_DRM, sizeof(*m));

2
sys/dev/pci/drm/drm_mm.c
View file

@ -174,7 +174,7 @@ drm_mm_interval_tree_iter_first(const struct rb_root_cached *root,
static void
drm_mm_interval_tree_remove(struct drm_mm_node *node,
struct rb_root_cached *root)
struct rb_root_cached *root)
{
rb_erase_cached(&node->rb, root);
}

5
sys/dev/pci/drm/drm_probe_helper.c
View file

@ -557,8 +557,9 @@ retry:
*/
dev->mode_config.delayed_event = true;
if (dev->mode_config.poll_enabled)
schedule_delayed_work(&dev->mode_config.output_poll_work,
0);
mod_delayed_work(system_wq,
&dev->mode_config.output_poll_work,
0);
}
/* Re-enable polling in case the global poll config changed. */

2
sys/dev/pci/drm/i915/display/intel_display.c
View file

@ -1079,7 +1079,7 @@ intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
num_encoders++;
}
drm_WARN(encoder->base.dev, num_encoders != 1,
drm_WARN(state->base.dev, num_encoders != 1,
"%d encoders for pipe %c\n",
num_encoders, pipe_name(master_crtc->pipe));

2
sys/dev/pci/drm/i915/gt/agp_intel_gtt.c
View file

@ -177,7 +177,7 @@ intel_gmch_gtt_get(u64 *gtt_total,
{
struct inteldrm_softc *dev_priv = (void *)inteldrm_cd.cd_devs[0];
struct agp_info *ai = &dev_priv->drm.agp->info;
*gtt_total = ai->ai_aperture_size;
*mappable_base = ai->ai_aperture_base;
*mappable_end = ai->ai_aperture_size;

2
sys/dev/pci/drm/i915/gt/shmem_utils.c
View file

@ -228,7 +228,7 @@ static int __uao_rw(struct uvm_object *uao, loff_t off,
unsigned int this =
min_t(size_t, PAGE_SIZE - offset_in_page(off), len);
void *vaddr = kmap(page);
if (write) {
memcpy(vaddr + offset_in_page(off), ptr, this);
set_page_dirty(page);

1
sys/dev/pci/drm/include/drm/i915_pciids.h
View file

@ -707,7 +707,6 @@
INTEL_VGA_DEVICE(0x5693, info), \
INTEL_VGA_DEVICE(0x5694, info), \
INTEL_VGA_DEVICE(0x5695, info), \
INTEL_VGA_DEVICE(0x5698, info), \
INTEL_VGA_DEVICE(0x56A5, info), \
INTEL_VGA_DEVICE(0x56A6, info), \
INTEL_VGA_DEVICE(0x56B0, info), \

12
sys/dev/pci/drm/include/linux/apple-gmux.h Normal file
View file

@ -0,0 +1,12 @@
/* Public domain. */
#ifndef _LINUX_APPLE_GMUX_H
#define _LINUX_APPLE_GMUX_H
static inline bool
apple_gmux_detect(void *a, void *b)
{
return false;
}
#endif

6
sys/dev/pci/drm/include/linux/atomic.h
View file

@ -2,7 +2,7 @@
/**
* \file drm_atomic.h
* Atomic operations used in the DRM which may or may not be provided by the OS.
*
*
* \author Eric Anholt <anholt@FreeBSD.org>
*/
@ -298,7 +298,7 @@ __test_and_set_bit(u_int b, volatile void *p)
volatile u_int *ptr = (volatile u_int *)p;
unsigned int prev = ptr[b >> 5];
ptr[b >> 5] |= m;
return (prev & m) != 0;
}
@ -428,7 +428,7 @@ find_next_bit(const volatile void *p, int max, int b)
#define wmb() __membar("dsb sy")
#define mb() __membar("dsb sy")
#elif defined(__mips64__)
#define rmb() mips_sync()
#define rmb() mips_sync()
#define wmb() mips_sync()
#define mb() mips_sync()
#elif defined(__powerpc64__)

6
sys/dev/pci/drm/include/linux/capability.h
View file

@ -12,8 +12,8 @@
#define CAP_SYS_NICE 0x2
static inline bool
capable(int cap)
{
capable(int cap)
{
switch (cap) {
case CAP_SYS_ADMIN:
case CAP_SYS_NICE:
@ -21,7 +21,7 @@ capable(int cap)
default:
panic("unhandled capability");
}
}
}
static inline bool
perfmon_capable(void)

2
sys/dev/pci/drm/include/linux/dma-buf.h
View file

@ -61,7 +61,7 @@ struct dma_buf_export_info {
struct dma_resv *resv;
};
#define DEFINE_DMA_BUF_EXPORT_INFO(x) struct dma_buf_export_info x
#define DEFINE_DMA_BUF_EXPORT_INFO(x) struct dma_buf_export_info x
struct dma_buf *dma_buf_export(const struct dma_buf_export_info *);

2
sys/dev/pci/drm/include/linux/file.h
View file

@ -4,7 +4,7 @@
#define _LINUX_FILE_H
/* both for printf */
#include <sys/types.h>
#include <sys/types.h>
#include <sys/systm.h>
void fd_install(int, struct file *);

2
sys/dev/pci/drm/include/linux/interrupt.h
View file

@ -106,7 +106,7 @@ tasklet_hi_schedule(struct tasklet_struct *ts)
task_add(taskletq, &ts->task);
}
static inline void
static inline void
tasklet_disable_nosync(struct tasklet_struct *ts)
{
atomic_inc(&ts->count);

2
sys/dev/pci/drm/include/linux/io.h
View file

@ -119,7 +119,7 @@ static inline u32
ioread32(const volatile void __iomem *addr)
{
uint32_t val;
iobarrier();
val = lemtoh32(addr);
rmb();

12
sys/dev/pci/drm/include/linux/pci.h
View file

@ -135,7 +135,7 @@ pci_read_config_dword(struct pci_dev *pdev, int reg, u32 *val)
{
*val = pci_conf_read(pdev->pc, pdev->tag, reg);
return 0;
}
}
static inline int
pci_read_config_word(struct pci_dev *pdev, int reg, u16 *val)
@ -145,7 +145,7 @@ pci_read_config_word(struct pci_dev *pdev, int reg, u16 *val)
v = pci_conf_read(pdev->pc, pdev->tag, (reg & ~0x2));
*val = (v >> ((reg & 0x2) * 8));
return 0;
}
}
static inline int
pci_read_config_byte(struct pci_dev *pdev, int reg, u8 *val)
@ -155,14 +155,14 @@ pci_read_config_byte(struct pci_dev *pdev, int reg, u8 *val)
v = pci_conf_read(pdev->pc, pdev->tag, (reg & ~0x3));
*val = (v >> ((reg & 0x3) * 8));
return 0;
}
}
static inline int
pci_write_config_dword(struct pci_dev *pdev, int reg, u32 val)
{
pci_conf_write(pdev->pc, pdev->tag, reg, val);
return 0;
}
}
static inline int
pci_write_config_word(struct pci_dev *pdev, int reg, u16 val)
@ -174,7 +174,7 @@ pci_write_config_word(struct pci_dev *pdev, int reg, u16 val)
v |= (val << ((reg & 0x2) * 8));
pci_conf_write(pdev->pc, pdev->tag, (reg & ~0x2), v);
return 0;
}
}
static inline int
pci_write_config_byte(struct pci_dev *pdev, int reg, u8 val)
@ -319,7 +319,7 @@ static inline int
pcie_set_readrq(struct pci_dev *pdev, int rrq)
{
uint16_t val;
pcie_capability_read_word(pdev, PCI_PCIE_DCSR, &val);
val &= ~PCI_PCIE_DCSR_MPS;
val |= (ffs(rrq) - 8) << 12;

2
sys/dev/pci/drm/include/linux/rbtree.h
View file

@ -99,7 +99,7 @@ __rb_deepest_left(struct rb_node *node)
else
node = RB_RIGHT(node, __entry);
}
return parent;
return parent;
}
static inline struct rb_node *

2
sys/dev/pci/drm/include/linux/scatterlist.h
View file

@ -77,7 +77,7 @@ static inline bool
__sg_page_iter_next(struct sg_page_iter *iter)
{
iter->sg_pgoffset++;
while (iter->__nents > 0 &&
while (iter->__nents > 0 &&
iter->sg_pgoffset >= (iter->sg->length / PAGE_SIZE)) {
iter->sg_pgoffset -= (iter->sg->length / PAGE_SIZE);
iter->sg++;

2
sys/dev/pci/drm/include/linux/seqlock.h
View file

@ -91,7 +91,7 @@ typedef struct {
static inline void
seqlock_init(seqlock_t *sl, int wantipl)
{
{
sl->seq = 0;
mtx_init(&sl->lock, wantipl);
}

2
sys/dev/pci/drm/include/linux/string.h
View file

@ -74,7 +74,7 @@ match_string(const char * const *array, size_t n, const char *str)
for (i = 0; i < n; i++) {
if (array[i] == NULL)
break;
if (!strcmp(array[i], str))
if (!strcmp(array[i], str))
return i;
}

4
sys/dev/pci/drm/include/linux/swap.h
View file

@ -30,11 +30,11 @@
static inline long
get_nr_swap_pages(void)
{
{
return uvmexp.swpages - uvmexp.swpginuse;
}
/*
/*
* XXX For now, we don't want the shrinker to be too aggressive, so
* pretend we're not called from the pagedaemon even if we are.
*/

10
sys/dev/pci/drm/include/linux/types.h
View file

@ -30,12 +30,12 @@ typedef uint32_t u32;
typedef int64_t s64;
typedef uint64_t u64;
typedef uint16_t __le16;
typedef uint16_t __be16;
typedef uint32_t __le32;
typedef uint16_t __le16;
typedef uint16_t __be16;
typedef uint32_t __le32;
typedef uint32_t __be32;
typedef uint64_t __le64;
typedef uint64_t __be64;
typedef uint64_t __le64;
typedef uint64_t __be64;
typedef bus_addr_t dma_addr_t;
typedef paddr_t phys_addr_t;

4
sys/dev/pci/drm/include/linux/wait.h
View file

@ -221,7 +221,7 @@ wake_up(wait_queue_head_t *wqh)
wait_queue_entry_t *wqe;
wait_queue_entry_t *tmp;
mtx_enter(&wqh->lock);
list_for_each_entry_safe(wqe, tmp, &wqh->head, entry) {
KASSERT(wqe->func != NULL);
if (wqe->func != NULL)
@ -255,7 +255,7 @@ wake_up_all_locked(wait_queue_head_t *wqh)
.private = curproc, \
.func = autoremove_wake_function, \
.entry = LIST_HEAD_INIT((name).entry), \
}
}
static inline void
prepare_to_wait(wait_queue_head_t *wqh, wait_queue_entry_t *wqe, int state)

4
sys/dev/pci/drm/include/linux/ww_mutex.h
View file

@ -209,7 +209,7 @@ static inline int
ww_mutex_lock(struct ww_mutex *lock, struct ww_acquire_ctx *ctx) {
return __ww_mutex_lock(lock, ctx, false, false);
}
static inline void
ww_mutex_lock_slow(struct ww_mutex *lock, struct ww_acquire_ctx *ctx) {
(void)__ww_mutex_lock(lock, ctx, true, false);
@ -219,7 +219,7 @@ static inline int
ww_mutex_lock_interruptible(struct ww_mutex *lock, struct ww_acquire_ctx *ctx) {
return __ww_mutex_lock(lock, ctx, false, true);
}
static inline int __must_check
ww_mutex_lock_slow_interruptible(struct ww_mutex *lock, struct ww_acquire_ctx *ctx) {
return __ww_mutex_lock(lock, ctx, true, true);

2
sys/dev/pci/drm/include/uapi/drm/radeon_drm.h
View file

@ -233,7 +233,7 @@ typedef union {
# define R300_WAIT_3D 0x2
/* these two defines are DOING IT WRONG - however
* we have userspace which relies on using these.
* The wait interface is backwards compat new
* The wait interface is backwards compat new
* code should use the NEW_WAIT defines below
* THESE ARE NOT BIT FIELDS
*/

4
sys/dev/pci/drm/linux_sort.c
View file

@ -56,7 +56,7 @@ static __inline void swapfunc(char *, char *, size_t, int);
static __inline void
swapfunc(char *a, char *b, size_t n, int swaptype)
{
if (swaptype <= 1)
if (swaptype <= 1)
swapcode(long, a, b, n)
else
swapcode(char, a, b, n)
@ -167,7 +167,7 @@ loop: SWAPINIT(a, es);
void
sort(void *a, size_t n, size_t es, int (*cmp)(const void *, const void *),
void *x)
void *x)
{
KASSERT(x == NULL);
qsort(a, n, es, cmp);

24
sys/dev/pci/drm/radeon/ObjectID.h
View file

@ -1,5 +1,5 @@
/*
* Copyright 2006-2007 Advanced Micro Devices, Inc.
* Copyright 2006-2007 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@ -37,13 +37,13 @@
#define GRAPH_OBJECT_TYPE_CONNECTOR 0x3
#define GRAPH_OBJECT_TYPE_ROUTER 0x4
/* deleted */
#define GRAPH_OBJECT_TYPE_DISPLAY_PATH 0x6
#define GRAPH_OBJECT_TYPE_DISPLAY_PATH 0x6
#define GRAPH_OBJECT_TYPE_GENERIC 0x7
/****************************************************/
/* Encoder Object ID Definition */
/****************************************************/
#define ENCODER_OBJECT_ID_NONE 0x00
#define ENCODER_OBJECT_ID_NONE 0x00
/* Radeon Class Display Hardware */
#define ENCODER_OBJECT_ID_INTERNAL_LVDS 0x01
@ -96,7 +96,7 @@
/****************************************************/
/* Connector Object ID Definition */
/****************************************************/
#define CONNECTOR_OBJECT_ID_NONE 0x00
#define CONNECTOR_OBJECT_ID_NONE 0x00
#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I 0x01
#define CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I 0x02
#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D 0x03
@ -156,7 +156,7 @@
#define RESERVED1_ID_MASK 0x0800
#define OBJECT_TYPE_MASK 0x7000
#define RESERVED2_ID_MASK 0x8000
#define OBJECT_ID_SHIFT 0x00
#define ENUM_ID_SHIFT 0x08
#define OBJECT_TYPE_SHIFT 0x0C
@ -177,14 +177,14 @@
/* Encoder Object ID definition - Shared with BIOS */
/****************************************************/
/*
#define ENCODER_INTERNAL_LVDS_ENUM_ID1 0x2101
#define ENCODER_INTERNAL_LVDS_ENUM_ID1 0x2101
#define ENCODER_INTERNAL_TMDS1_ENUM_ID1 0x2102
#define ENCODER_INTERNAL_TMDS2_ENUM_ID1 0x2103
#define ENCODER_INTERNAL_DAC1_ENUM_ID1 0x2104
#define ENCODER_INTERNAL_DAC2_ENUM_ID1 0x2105
#define ENCODER_INTERNAL_SDVOA_ENUM_ID1 0x2106
#define ENCODER_INTERNAL_SDVOB_ENUM_ID1 0x2107
#define ENCODER_SIL170B_ENUM_ID1 0x2108
#define ENCODER_SIL170B_ENUM_ID1 0x2108
#define ENCODER_CH7303_ENUM_ID1 0x2109
#define ENCODER_CH7301_ENUM_ID1 0x210A
#define ENCODER_INTERNAL_DVO1_ENUM_ID1 0x210B
@ -198,8 +198,8 @@
#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1 0x2113
#define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1 0x2114
#define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1 0x2115
#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 0x2116
#define ENCODER_SI178_ENUM_ID1 0x2117
#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 0x2116
#define ENCODER_SI178_ENUM_ID1 0x2117
#define ENCODER_MVPU_FPGA_ENUM_ID1 0x2118
#define ENCODER_INTERNAL_DDI_ENUM_ID1 0x2119
#define ENCODER_VT1625_ENUM_ID1 0x211A
@ -314,7 +314,7 @@
#define ENCODER_SI178_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_SI178 << OBJECT_ID_SHIFT)
ENCODER_OBJECT_ID_SI178 << OBJECT_ID_SHIFT)
#define ENCODER_MVPU_FPGA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
@ -322,7 +322,7 @@
#define ENCODER_INTERNAL_DDI_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_INTERNAL_DDI << OBJECT_ID_SHIFT)
ENCODER_OBJECT_ID_INTERNAL_DDI << OBJECT_ID_SHIFT)
#define ENCODER_VT1625_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
@ -350,7 +350,7 @@
#define ENCODER_INTERNAL_KLDSCP_LVTMA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA << OBJECT_ID_SHIFT)
ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA << OBJECT_ID_SHIFT)
#define ENCODER_INTERNAL_UNIPHY1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\

1842
sys/dev/pci/drm/radeon/atombios.h
View file

File diff suppressed because it is too large Load diff

167
sys/dev/pci/drm/ttm/ttm_pool.c
View file

@ -485,6 +485,68 @@ static unsigned int ttm_pool_page_order(struct ttm_pool *pool, struct vm_page *p
#endif /* notyet */
/* Called when we got a page, either from a pool or newly allocated */
static int ttm_pool_page_allocated(struct ttm_pool *pool, unsigned int order,
struct vm_page *p, dma_addr_t **dma_addr,
unsigned long *num_pages,
struct vm_page ***pages,
unsigned long **orders)
{
unsigned int i;
int r;
if (*dma_addr) {
r = ttm_pool_map(pool, order, p, dma_addr);
if (r)
return r;
}
*num_pages -= 1 << order;
for (i = 1 << order; i; --i, ++(*pages), ++p, ++(*orders)) {
**pages = p;
**orders = order;
}
return 0;
}
/**
* ttm_pool_free_range() - Free a range of TTM pages
* @pool: The pool used for allocating.
* @tt: The struct ttm_tt holding the page pointers.
* @caching: The page caching mode used by the range.
* @start_page: index for first page to free.
* @end_page: index for last page to free + 1.
*
* During allocation the ttm_tt page-vector may be populated with ranges of
* pages with different attributes if allocation hit an error without being
* able to completely fulfill the allocation. This function can be used
* to free these individual ranges.
*/
static void ttm_pool_free_range(struct ttm_pool *pool, struct ttm_tt *tt,
enum ttm_caching caching,
pgoff_t start_page, pgoff_t end_page)
{
struct vm_page **pages = tt->pages;
unsigned int order;
pgoff_t i, nr;
for (i = start_page; i < end_page; i += nr, pages += nr) {
struct ttm_pool_type *pt = NULL;
order = tt->orders[i];
nr = (1UL << order);
if (tt->dma_address)
ttm_pool_unmap(pool, tt->dma_address[i], nr);
pt = ttm_pool_select_type(pool, caching, order);
if (pt)
ttm_pool_type_give(pt, *pages);
else
ttm_pool_free_page(pool, caching, order, *pages);
}
}
/**
* ttm_pool_alloc - Fill a ttm_tt object
*
@ -500,15 +562,17 @@ static unsigned int ttm_pool_page_order(struct ttm_pool *pool, struct vm_page *p
int ttm_pool_alloc(struct ttm_pool *pool, struct ttm_tt *tt,
struct ttm_operation_ctx *ctx)
{
unsigned long num_pages = tt->num_pages;
pgoff_t num_pages = tt->num_pages;
dma_addr_t *dma_addr = tt->dma_address;
struct vm_page **caching = tt->pages;
struct vm_page **pages = tt->pages;
unsigned long *orders = tt->orders;
enum ttm_caching page_caching;
gfp_t gfp_flags = GFP_USER;
unsigned int i, order;
pgoff_t caching_divide;
unsigned int order;
struct vm_page *p;
int r;
unsigned long *orders = tt->orders;
WARN_ON(!num_pages || ttm_tt_is_populated(tt));
#ifdef __linux__
@ -529,17 +593,51 @@ int ttm_pool_alloc(struct ttm_pool *pool, struct ttm_tt *tt,
for (order = min_t(unsigned int, MAX_ORDER - 1, __fls(num_pages));
num_pages;
order = min_t(unsigned int, order, __fls(num_pages))) {
bool apply_caching = false;
struct ttm_pool_type *pt;
page_caching = tt->caching;
pt = ttm_pool_select_type(pool, tt->caching, order);
p = pt ? ttm_pool_type_take(pt) : NULL;
if (p) {
apply_caching = true;
} else {
p = ttm_pool_alloc_page(pool, gfp_flags, order, tt->dmat);
if (p && PageHighMem(p))
apply_caching = true;
r = ttm_pool_apply_caching(caching, pages,
tt->caching);
if (r)
goto error_free_page;
caching = pages;
do {
r = ttm_pool_page_allocated(pool, order, p,
&dma_addr,
&num_pages,
&pages, &orders);
if (r)
goto error_free_page;
caching = pages;
if (num_pages < (1 << order))
break;
p = ttm_pool_type_take(pt);
} while (p);
}
page_caching = ttm_cached;
while (num_pages >= (1 << order) &&
(p = ttm_pool_alloc_page(pool, gfp_flags, order, tt->dmat))) {
if (PageHighMem(p)) {
r = ttm_pool_apply_caching(caching, pages,
tt->caching);
if (r)
goto error_free_page;
caching = pages;
}
r = ttm_pool_page_allocated(pool, order, p, &dma_addr,
&num_pages, &pages, &orders);
if (r)
goto error_free_page;
if (PageHighMem(p))
caching = pages;
}
if (!p) {
@ -550,26 +648,6 @@ int ttm_pool_alloc(struct ttm_pool *pool, struct ttm_tt *tt,
r = -ENOMEM;
goto error_free_all;
}
if (apply_caching) {
r = ttm_pool_apply_caching(caching, pages,
tt->caching);
if (r)
goto error_free_page;
caching = pages + (1 << order);
}
if (dma_addr) {
r = ttm_pool_map(pool, order, p, &dma_addr);
if (r)
goto error_free_page;
}
num_pages -= 1 << order;
for (i = 1 << order; i; --i) {
*(pages++) = p++;
*(orders++) = order;
}
}
r = ttm_pool_apply_caching(caching, pages, tt->caching);
@ -579,15 +657,13 @@ int ttm_pool_alloc(struct ttm_pool *pool, struct ttm_tt *tt,
return 0;
error_free_page:
ttm_pool_free_page(pool, tt->caching, order, p);
ttm_pool_free_page(pool, page_caching, order, p);
error_free_all:
num_pages = tt->num_pages - num_pages;
for (i = 0; i < num_pages; ) {
order = tt->orders[i];
ttm_pool_free_page(pool, tt->caching, order, tt->pages[i]);
i += 1 << order;
}
caching_divide = caching - tt->pages;
ttm_pool_free_range(pool, tt, tt->caching, 0, caching_divide);
ttm_pool_free_range(pool, tt, ttm_cached, caching_divide, num_pages);
return r;
}
@ -603,26 +679,7 @@ EXPORT_SYMBOL(ttm_pool_alloc);
*/
void ttm_pool_free(struct ttm_pool *pool, struct ttm_tt *tt)
{
unsigned int i;
for (i = 0; i < tt->num_pages; ) {
unsigned int order, num_pages;
struct ttm_pool_type *pt;
order = tt->orders[i];
num_pages = 1ULL << order;
if (tt->dma_address)
ttm_pool_unmap(pool, tt->dma_address[i], num_pages);
pt = ttm_pool_select_type(pool, tt->caching, order);
if (pt)
ttm_pool_type_give(pt, tt->pages[i]);
else
ttm_pool_free_page(pool, tt->caching, order,
tt->pages[i]);
i += num_pages;
}
ttm_pool_free_range(pool, tt, tt->caching, 0, tt->num_pages);
while (atomic_long_read(&allocated_pages) > page_pool_size)
ttm_pool_shrink();

13
sys/dev/pci/if_iwx.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: if_iwx.c,v 1.170 2023/04/14 12:45:10 stsp Exp $ */
/* $OpenBSD: if_iwx.c,v 1.171 2023/05/11 16:55:46 stsp Exp $ */
/*
* Copyright (c) 2014, 2016 genua gmbh <info@genua.de>
@ -8431,17 +8431,6 @@ iwx_run_stop(struct iwx_softc *sc)
return err;
}
/* Reset Tx chains in case MIMO or 40 MHz channels were enabled. */
if (in->in_ni.ni_flags & IEEE80211_NODE_HT) {
err = iwx_phy_ctxt_update(sc, in->in_phyctxt,
in->in_phyctxt->channel, 1, 1, 0, IEEE80211_HTOP0_SCO_SCN,
IEEE80211_VHTOP0_CHAN_WIDTH_HT);
if (err) {
printf("%s: failed to update PHY\n", DEVNAME(sc));
return err;
}
}
return 0;
}

12
sys/dev/pci/pcidevs
View file

@ -1,4 +1,4 @@
$OpenBSD: pcidevs,v 1.2034 2023/05/01 07:24:04 dlg Exp $
$OpenBSD: pcidevs,v 1.2036 2023/05/12 11:42:22 jsg Exp $
/* $NetBSD: pcidevs,v 1.30 1997/06/24 06:20:24 thorpej Exp $ */
/*
@ -5892,16 +5892,15 @@ product INTEL DG2_G11_2 0x5694 Arc A350M
product INTEL DG2_G11_3 0x5695 Graphics
product INTEL DG2_G12_1 0x5696 Graphics
product INTEL DG2_G12_2 0x5697 Graphics
product INTEL DG2_G11_4 0x5698 Graphics
product INTEL DG2_G10_4 0x56a0 Arc A770
product INTEL DG2_G10_5 0x56a1 Arc A750
product INTEL DG2_G10_6 0x56a2 Arc A580
product INTEL DG2_G12_3 0x56a3 Graphics
product INTEL DG2_G12_4 0x56a4 Graphics
product INTEL DG2_G11_5 0x56a5 Arc A380
product INTEL DG2_G11_6 0x56a6 Arc A310
product INTEL DG2_G11_7 0x56b0 Arc Pro A30M
product INTEL DG2_G11_8 0x56b1 Arc Pro A40/A50
product INTEL DG2_G11_4 0x56a5 Arc A380
product INTEL DG2_G11_5 0x56a6 Arc A310
product INTEL DG2_G11_6 0x56b0 Arc Pro A30M
product INTEL DG2_G11_7 0x56b1 Arc Pro A40/A50
product INTEL DG2_G12_5 0x56b2 Graphics
product INTEL DG2_G12_6 0x56b3 Graphics
product INTEL ATS_M150 0x56c0 Flex 170
@ -7063,6 +7062,7 @@ product LEADTEK WINFAST_XP 0x6609 Leadtek WinFast TV 2000 XP
/* Lenovo products */
product LENOVO NVME 0x0003 NVMe
product LENOVO NVME_2 0x0006 NVMe
/* Level 1 (Intel) */
product LEVEL1 LXT1001 0x0001 LXT1001

12
sys/dev/pci/pcidevs.h
View file

@ -2,7 +2,7 @@
* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* generated from:
* OpenBSD: pcidevs,v 1.2034 2023/05/01 07:24:04 dlg Exp
* OpenBSD: pcidevs,v 1.2036 2023/05/12 11:42:22 jsg Exp
*/
/* $NetBSD: pcidevs,v 1.30 1997/06/24 06:20:24 thorpej Exp $ */
@ -5897,16 +5897,15 @@
#define PCI_PRODUCT_INTEL_DG2_G11_3 0x5695 /* Graphics */
#define PCI_PRODUCT_INTEL_DG2_G12_1 0x5696 /* Graphics */
#define PCI_PRODUCT_INTEL_DG2_G12_2 0x5697 /* Graphics */
#define PCI_PRODUCT_INTEL_DG2_G11_4 0x5698 /* Graphics */
#define PCI_PRODUCT_INTEL_DG2_G10_4 0x56a0 /* Arc A770 */
#define PCI_PRODUCT_INTEL_DG2_G10_5 0x56a1 /* Arc A750 */
#define PCI_PRODUCT_INTEL_DG2_G10_6 0x56a2 /* Arc A580 */
#define PCI_PRODUCT_INTEL_DG2_G12_3 0x56a3 /* Graphics */
#define PCI_PRODUCT_INTEL_DG2_G12_4 0x56a4 /* Graphics */
#define PCI_PRODUCT_INTEL_DG2_G11_5 0x56a5 /* Arc A380 */
#define PCI_PRODUCT_INTEL_DG2_G11_6 0x56a6 /* Arc A310 */
#define PCI_PRODUCT_INTEL_DG2_G11_7 0x56b0 /* Arc Pro A30M */
#define PCI_PRODUCT_INTEL_DG2_G11_8 0x56b1 /* Arc Pro A40/A50 */
#define PCI_PRODUCT_INTEL_DG2_G11_4 0x56a5 /* Arc A380 */
#define PCI_PRODUCT_INTEL_DG2_G11_5 0x56a6 /* Arc A310 */
#define PCI_PRODUCT_INTEL_DG2_G11_6 0x56b0 /* Arc Pro A30M */
#define PCI_PRODUCT_INTEL_DG2_G11_7 0x56b1 /* Arc Pro A40/A50 */
#define PCI_PRODUCT_INTEL_DG2_G12_5 0x56b2 /* Graphics */
#define PCI_PRODUCT_INTEL_DG2_G12_6 0x56b3 /* Graphics */
#define PCI_PRODUCT_INTEL_ATS_M150 0x56c0 /* Flex 170 */
@ -7068,6 +7067,7 @@
/* Lenovo products */
#define PCI_PRODUCT_LENOVO_NVME 0x0003 /* NVMe */
#define PCI_PRODUCT_LENOVO_NVME_2 0x0006 /* NVMe */
/* Level 1 (Intel) */
#define PCI_PRODUCT_LEVEL1_LXT1001 0x0001 /* LXT1001 */

18
sys/dev/pci/pcidevs_data.h
View file

@ -2,7 +2,7 @@
* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* generated from:
* OpenBSD: pcidevs,v 1.2034 2023/05/01 07:24:04 dlg Exp
* OpenBSD: pcidevs,v 1.2036 2023/05/12 11:42:22 jsg Exp
*/
/* $NetBSD: pcidevs,v 1.30 1997/06/24 06:20:24 thorpej Exp $ */
@ -20943,10 +20943,6 @@ static const struct pci_known_product pci_known_products[] = {
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DG2_G12_2,
"Graphics",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DG2_G11_4,
"Graphics",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DG2_G10_4,
"Arc A770",
@ -20968,19 +20964,19 @@ static const struct pci_known_product pci_known_products[] = {
"Graphics",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DG2_G11_5,
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DG2_G11_4,
"Arc A380",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DG2_G11_6,
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DG2_G11_5,
"Arc A310",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DG2_G11_7,
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DG2_G11_6,
"Arc Pro A30M",
},
{
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DG2_G11_8,
PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DG2_G11_7,
"Arc Pro A40/A50",
},
{
@ -25507,6 +25503,10 @@ static const struct pci_known_product pci_known_products[] = {
PCI_VENDOR_LENOVO, PCI_PRODUCT_LENOVO_NVME,
"NVMe",
},
{
PCI_VENDOR_LENOVO, PCI_PRODUCT_LENOVO_NVME_2,
"NVMe",
},
{
PCI_VENDOR_LEVEL1, PCI_PRODUCT_LEVEL1_LXT1001,
"LXT1001",

77
sys/dev/usb/if_ure.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: if_ure.c,v 1.31 2022/10/27 13:21:14 patrick Exp $ */
/* $OpenBSD: if_ure.c,v 1.32 2023/05/06 08:07:10 kevlo Exp $ */
/*-
* Copyright (c) 2015, 2016, 2019 Kevin Lo <kevlo@openbsd.org>
* Copyright (c) 2020 Jonathon Fletcher <jonathon.fletcher@gmail.com>
@ -270,7 +270,7 @@ ure_read_1(struct ure_softc *sc, uint16_t reg, uint16_t index)
shift = (reg & 3) << 3;
reg &= ~3;
ure_read_mem(sc, reg, index, &temp, 4);
val = UGETDW(temp);
val >>= shift;
@ -466,8 +466,8 @@ ure_ifmedia_init(struct ifnet *ifp)
reg = sc->ure_rxbufsz - URE_FRAMELEN(ifp->if_mtu) -
sizeof(struct ure_rxpkt) - URE_RX_BUF_ALIGN;
if (sc->ure_flags & (URE_FLAG_8153B | URE_FLAG_8156 |
URE_FLAG_8156B)) {
if (sc->ure_flags &
(URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B)) {
ure_write_2(sc, URE_USB_RX_EARLY_SIZE, URE_MCU_TYPE_USB,
reg / 8);
@ -493,6 +493,11 @@ ure_ifmedia_init(struct ifnet *ifp)
reg);
}
if (sc->ure_chip & URE_CHIP_VER_7420) {
URE_SETBIT_2(sc, URE_PLA_MAC_PWR_CTRL4,
URE_MCU_TYPE_PLA, URE_IDLE_SPDWN_EN);
}
if ((sc->ure_chip & URE_CHIP_VER_6010) ||
(sc->ure_flags & URE_FLAG_8156B)) {
URE_CLRBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB,
@ -502,7 +507,7 @@ ure_ifmedia_init(struct ifnet *ifp)
URE_FC_PATCH_TASK);
}
}
/* Reset the packet filter. */
URE_CLRBIT_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, URE_FMC_FCR_MCU_EN);
URE_SETBIT_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, URE_FMC_FCR_MCU_EN);
@ -530,15 +535,18 @@ ure_ifmedia_upd(struct ifnet *ifp)
if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
return (EINVAL);
reg = ure_ocp_reg_read(sc, 0xa5d4);
reg &= ~URE_ADV_2500TFDX;
if (!(sc->ure_chip & URE_CHIP_VER_7420)) {
reg = ure_ocp_reg_read(sc, URE_OCP_10GBT_CTRL);
reg &= ~URE_ADV_2500TFDX;
}
anar = gig = 0;
switch (IFM_SUBTYPE(ifm->ifm_media)) {
case IFM_AUTO:
anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10;
gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX;
reg |= URE_ADV_2500TFDX;
if (!(sc->ure_chip & URE_CHIP_VER_7420))
reg |= URE_ADV_2500TFDX;
break;
case IFM_2500_T:
anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10;
@ -566,9 +574,10 @@ ure_ifmedia_upd(struct ifnet *ifp)
}
ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_ANAR * 2,
anar | ANAR_PAUSE_ASYM | ANAR_FC);
ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_100T2CR * 2, gig);
ure_ocp_reg_write(sc, 0xa5d4, reg);
anar | ANAR_PAUSE_ASYM | ANAR_FC);
ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_100T2CR * 2, gig);
if (!(sc->ure_chip & URE_CHIP_VER_7420))
ure_ocp_reg_write(sc, URE_OCP_10GBT_CTRL, reg);
ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_BMCR,
BMCR_AUTOEN | BMCR_STARTNEG);
@ -602,7 +611,7 @@ ure_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
status = ure_read_2(sc, URE_PLA_PHYSTATUS,
URE_MCU_TYPE_PLA);
if ((status & URE_PHYSTATUS_FDX) ||
(status & URE_PHYSTATUS_2500MBPS))
(status & URE_PHYSTATUS_2500MBPS))
ifmr->ifm_active |= IFM_FDX;
else
ifmr->ifm_active |= IFM_HDX;
@ -634,9 +643,11 @@ ure_add_media_types(struct ure_softc *sc)
ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL);
ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX, 0,
NULL);
ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_2500_T, 0, NULL);
ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_2500_T | IFM_FDX, 0,
NULL);
if (!(sc->ure_chip & URE_CHIP_VER_7420)) {
ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_2500_T, 0, NULL);
ifmedia_add(&sc->ure_ifmedia, IFM_ETHER | IFM_2500_T | IFM_FDX,
0, NULL);
}
}
void
@ -929,7 +940,7 @@ ure_start(struct ifnet *ifp)
continue;
}
/*
/*
* If packet larger than remaining space, send buffer and
* continue.
*/
@ -1176,12 +1187,12 @@ ure_rtl8153_init(struct ure_softc *sc)
}
URE_SETBIT_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB, URE_EP4_FULL_FC);
URE_CLRBIT_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB, URE_TIMER11_EN);
URE_CLRBIT_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA,
URE_LED_MODE_MASK);
if ((sc->ure_chip & URE_CHIP_VER_5C10) &&
sc->ure_udev->speed != USB_SPEED_SUPER)
reg = URE_LPM_TIMER_500MS;
@ -1269,7 +1280,7 @@ ure_rtl8153b_init(struct ure_softc *sc)
URE_CLRBIT_1(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB,
URE_UPS_EN | URE_USP_PREWAKE);
URE_CLRBIT_1(sc, URE_USB_MISC_2, URE_MCU_TYPE_USB,
URE_UPS_FORCE_PWR_DOWN);
URE_UPS_FORCE_PWR_DOWN | URE_UPS_NO_UPS);
URE_CLRBIT_1(sc, URE_PLA_INDICATE_FALG, URE_MCU_TYPE_PLA,
URE_UPCOMING_RUNTIME_D3);
@ -1318,7 +1329,7 @@ ure_rtl8153b_init(struct ure_softc *sc)
URE_SETBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB,
URE_FC_PATCH_TASK);
}
/* MAC clock speed down. */
if (sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) {
ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 0x0403);
@ -1350,6 +1361,17 @@ ure_rtl8153b_init(struct ure_softc *sc)
URE_SETBIT_1(sc, URE_USB_BMU_CONFIG, URE_MCU_TYPE_USB,
URE_ACT_ODMA);
if (!(sc->ure_flags & URE_FLAG_8153B)) {
/*
* Select force mode through 0xa5b4 bit 15
* 0: MDIO force mode
* 1: MMD force mode
*/
reg = ure_ocp_reg_read(sc, 0xa5b4);
if (reg & 0x8000)
ure_ocp_reg_write(sc, 0xa5b4, reg & ~0x8000);
}
URE_SETBIT_2(sc, URE_PLA_RSTTALLY, URE_MCU_TYPE_PLA, URE_TALLY_RESET);
}
@ -1523,9 +1545,7 @@ ure_rtl8153_nic_reset(struct ure_softc *sc)
ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB,
0x00600400);
}
if (!(sc->ure_flags & (URE_FLAG_8156 | URE_FLAG_8156B))) {
} else {
URE_SETBIT_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA,
URE_TCR0_AUTO_FIFO);
ure_reset(sc);
@ -1611,7 +1631,7 @@ ure_wait_for_flash(struct ure_softc *sc)
int i;
if ((ure_read_2(sc, URE_PLA_GPHY_CTRL, URE_MCU_TYPE_PLA) &
URE_GPHY_FLASH) &&
URE_GPHY_FLASH) &&
!(ure_read_2(sc, URE_USB_GPHY_CTRL, URE_MCU_TYPE_USB) &
URE_BYPASS_FLASH)) {
for (i = 0; i < 100; i++) {
@ -1712,7 +1732,7 @@ ure_match(struct device *parent, void *match, void *aux)
if (uaa->iface == NULL || uaa->configno != 1)
return (UMATCH_NONE);
return (usb_lookup(ure_devs, uaa->vendor, uaa->product) != NULL ?
UMATCH_VENDOR_PRODUCT_CONF_IFACE : UMATCH_NONE);
}
@ -1811,6 +1831,11 @@ ure_attach(struct device *parent, struct device *self, void *aux)
sc->ure_flags = URE_FLAG_8156B;
printf("RTL8156B (0x7410)");
break;
case 0x7420:
sc->ure_flags = URE_FLAG_8156B;
sc->ure_chip = URE_CHIP_VER_7420;
printf("RTL8153D (0x7420)");
break;
default:
printf(", unknown ver %02x", ver);
break;
@ -1981,7 +2006,7 @@ ure_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status)
struct mbuf *m;
int pktlen = 0, s;
struct ure_rxpkt rxhdr;
if (usbd_is_dying(sc->ure_udev))
return;

30
sys/dev/usb/if_urereg.h
View file

@ -1,4 +1,4 @@
/* $OpenBSD: if_urereg.h,v 1.11 2022/04/02 12:22:56 kevlo Exp $ */
/* $OpenBSD: if_urereg.h,v 1.12 2023/05/06 08:07:10 kevlo Exp $ */
/*-
* Copyright (c) 2015, 2016, 2019 Kevin Lo <kevlo@openbsd.org>
* All rights reserved.
@ -167,6 +167,7 @@
#define URE_OCP_EEE_ABLE 0xa5c4
#define URE_OCP_EEE_ADV 0xa5d0
#define URE_OCP_EEE_LPABLE 0xa5d2
#define URE_OCP_10GBT_CTRL 0xa5d4
#define URE_OCP_PHY_STATE 0xa708
#define URE_OCP_ADC_CFG 0xbc06
@ -248,19 +249,19 @@
#define URE_CRWECR_CONFIG 0xc0
/* URE_PLA_OOB_CTRL */
#define URE_DIS_MCU_CLROOB 0x01
#define URE_LINK_LIST_READY 0x02
#define URE_RXFIFO_EMPTY 0x10
#define URE_TXFIFO_EMPTY 0x20
#define URE_NOW_IS_OOB 0x80
#define URE_DIS_MCU_CLROOB 0x01
#define URE_LINK_LIST_READY 0x02
#define URE_RXFIFO_EMPTY 0x10
#define URE_TXFIFO_EMPTY 0x20
#define URE_NOW_IS_OOB 0x80
#define URE_FIFO_EMPTY (URE_TXFIFO_EMPTY | URE_RXFIFO_EMPTY)
/* URE_PLA_MISC_1 */
#define URE_RXDY_GATED_EN 0x0008
#define URE_RXDY_GATED_EN 0x0008
/* URE_PLA_SFF_STS_7 */
#define URE_MCU_BORW_EN 0x4000
#define URE_RE_INIT_LL 0x8000
#define URE_MCU_BORW_EN 0x4000
#define URE_RE_INIT_LL 0x8000
/* URE_PLA_CPCR */
#define URE_FLOW_CTRL_EN 0x0001
@ -312,6 +313,7 @@
#define URE_TP1000_SPDWN_EN 0x0008
#define URE_TP500_SPDWN_EN 0x0010
#define URE_TP100_SPDWN_EN 0x0020
#define URE_IDLE_SPDWN_EN 0x0040
#define URE_TX10MIDLE_EN 0x0100
#define URE_RXDV_SPDWN_EN 0x0800
#define URE_PWRSAVE_SPDWN_EN 0x1000
@ -391,6 +393,7 @@
/* URE_USB_MISC_2 */
#define URE_UPS_FORCE_PWR_DOWN 0x01
#define URE_UPS_NO_UPS 0x80
/* URE_USB_ECM_OPTION */
#define URE_BYPASS_MAC_RESET 0x0020
@ -493,15 +496,15 @@
#define URE_UPS_FLAGS_MASK 0xffffffff
/* URE_OCP_ALDPS_CONFIG */
#define URE_ENPWRSAVE 0x8000
#define URE_ENPDNPS 0x0200
#define URE_LINKENA 0x0100
#define URE_ENPWRSAVE 0x8000
#define URE_ENPDNPS 0x0200
#define URE_LINKENA 0x0100
#define URE_DIS_SDSAVE 0x0010
/* URE_OCP_PHY_STATUS */
#define URE_PHY_STAT_MASK 0x0007
#define URE_PHY_STAT_EXT_INIT 2
#define URE_PHY_STAT_LAN_ON 3
#define URE_PHY_STAT_LAN_ON 3
#define URE_PHY_STAT_PWRDN 5
/* URE_OCP_POWER_CFG */
@ -646,4 +649,5 @@ struct ure_softc {
#define URE_CHIP_VER_5C20 0x10
#define URE_CHIP_VER_5C30 0x20
#define URE_CHIP_VER_6010 0x40
#define URE_CHIP_VER_7420 0x80
};

5
sys/dev/usb/udl.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: udl.c,v 1.98 2022/07/15 17:57:27 kettenis Exp $ */
/* $OpenBSD: udl.c,v 1.99 2023/05/10 18:28:04 miod Exp $ */
/*
* Copyright (c) 2009 Marcus Glocker <mglocker@openbsd.org>
@ -249,7 +249,8 @@ static const struct udl_type udl_devs[] = {
{ { USB_VENDOR_DISPLAYLINK, USB_PRODUCT_DISPLAYLINK_CONV }, DL160 },
{ { USB_VENDOR_DISPLAYLINK, USB_PRODUCT_DISPLAYLINK_LUM70 }, DL125 },
{ { USB_VENDOR_DISPLAYLINK, USB_PRODUCT_DISPLAYLINK_POLARIS2 }, DLUNK },
{ { USB_VENDOR_DISPLAYLINK, USB_PRODUCT_DISPLAYLINK_LT1421 }, DLUNK }
{ { USB_VENDOR_DISPLAYLINK, USB_PRODUCT_DISPLAYLINK_LT1421 }, DLUNK },
{ { USB_VENDOR_DISPLAYLINK, USB_PRODUCT_DISPLAYLINK_TOSHIBA }, DLUNK }
};
#define udl_lookup(v, p) ((struct udl_type *)usb_lookup(udl_devs, v, p))

7
sys/dev/usb/umass_scsi.c
View file

@ -1,4 +1,4 @@
/* $OpenBSD: umass_scsi.c,v 1.63 2022/04/16 19:19:59 naddy Exp $ */
/* $OpenBSD: umass_scsi.c,v 1.64 2023/05/10 15:28:26 krw Exp $ */
/* $NetBSD: umass_scsipi.c,v 1.9 2003/02/16 23:14:08 augustss Exp $ */
/*
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@ -96,6 +96,11 @@ umass_scsi_attach(struct umass_softc *sc)
sc->sc_dev.dv_xname, sc, scbus));
break;
case UMASS_CPROTO_UFI:
flags |= SDEV_UFI | SDEV_ATAPI;
DPRINTF(UDMASS_USB, ("%s: umass_attach_bus: UFI\n"
"sc = 0x%p, scbus = 0x%p\n",
sc->sc_dev.dv_xname, sc, scbus));
break;
case UMASS_CPROTO_ATAPI:
flags |= SDEV_ATAPI;
DPRINTF(UDMASS_USB, ("%s: umass_attach_bus: ATAPI\n"

3
sys/dev/usb/usbdevs
View file

@ -1,4 +1,4 @@
$OpenBSD: usbdevs,v 1.755 2023/04/28 01:24:14 kevlo Exp $
$OpenBSD: usbdevs,v 1.756 2023/05/10 18:26:05 miod Exp $
/* $NetBSD: usbdevs,v 1.322 2003/05/10 17:47:14 hamajima Exp $ */
/*
@ -1575,6 +1575,7 @@ product DIGITALSTREAM PS2 0x0001 PS/2 Active
/* DisplayLink products */
product DISPLAYLINK GUC2020 0x0059 IOGEAR DVI GUC2020
product DISPLAYLINK LD220 0x0100 Samsung LD220
product DISPLAYLINK TOSHIBA 0x0110 TOSHIBA Video Dock
product DISPLAYLINK POLARIS2 0x0117 Polaris2 USB dock
product DISPLAYLINK VCUD60 0x0136 Rextron DVI
product DISPLAYLINK CONV 0x0138 StarTech CONV-USB2DVI

5
sys/dev/usb/usbdevs.h
View file

@ -1,10 +1,10 @@
/* $OpenBSD: usbdevs.h,v 1.767 2023/04/28 01:24:51 kevlo Exp $ */
/* $OpenBSD: usbdevs.h,v 1.768 2023/05/10 18:26:43 miod Exp $ */
/*
* THIS FILE IS AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* generated from:
* OpenBSD: usbdevs,v 1.755 2023/04/28 01:24:14 kevlo Exp
* OpenBSD: usbdevs,v 1.756 2023/05/10 18:26:05 miod Exp
*/
/* $NetBSD: usbdevs,v 1.322 2003/05/10 17:47:14 hamajima Exp $ */
@ -1582,6 +1582,7 @@
/* DisplayLink products */
#define USB_PRODUCT_DISPLAYLINK_GUC2020 0x0059 /* IOGEAR DVI GUC2020 */
#define USB_PRODUCT_DISPLAYLINK_LD220 0x0100 /* Samsung LD220 */
#define USB_PRODUCT_DISPLAYLINK_TOSHIBA 0x0110 /* TOSHIBA Video Dock */
#define USB_PRODUCT_DISPLAYLINK_POLARIS2 0x0117 /* Polaris2 USB dock */
#define USB_PRODUCT_DISPLAYLINK_VCUD60 0x0136 /* Rextron DVI */
#define USB_PRODUCT_DISPLAYLINK_CONV 0x0138 /* StarTech CONV-USB2DVI */

8
sys/dev/usb/usbdevs_data.h
View file

@ -1,10 +1,10 @@
/* $OpenBSD: usbdevs_data.h,v 1.761 2023/04/28 01:24:51 kevlo Exp $ */
/* $OpenBSD: usbdevs_data.h,v 1.762 2023/05/10 18:26:43 miod Exp $ */
/*
* THIS FILE IS AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* generated from:
* OpenBSD: usbdevs,v 1.755 2023/04/28 01:24:14 kevlo Exp
* OpenBSD: usbdevs,v 1.756 2023/05/10 18:26:05 miod Exp
*/
/* $NetBSD: usbdevs,v 1.322 2003/05/10 17:47:14 hamajima Exp $ */
@ -2589,6 +2589,10 @@ const struct usb_known_product usb_known_products[] = {
USB_VENDOR_DISPLAYLINK, USB_PRODUCT_DISPLAYLINK_LD220,
"Samsung LD220",
},
{
USB_VENDOR_DISPLAYLINK, USB_PRODUCT_DISPLAYLINK_TOSHIBA,
"TOSHIBA Video Dock",
},
{
USB_VENDOR_DISPLAYLINK, USB_PRODUCT_DISPLAYLINK_POLARIS2,
"Polaris2 USB dock",