sync with OpenBSD -current
This commit is contained in:
parent
20629a8b0d
commit
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GPG key ID:
F42C07F07E2E35B7
58 changed files with 592 additions and 377 deletions
340
sys/dev/ic/qwx.c
340
sys/dev/ic/qwx.c
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@ -1,4 +1,4 @@
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/* $OpenBSD: qwx.c,v 1.8 2024/01/25 17:00:20 stsp Exp $ */
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/* $OpenBSD: qwx.c,v 1.9 2024/01/28 22:30:39 stsp Exp $ */
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/*
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* Copyright 2023 Stefan Sperling <stsp@openbsd.org>
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@ -134,6 +134,8 @@ int qwx_qmi_event_server_arrive(struct qwx_softc *);
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int qwx_mac_register(struct qwx_softc *);
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int qwx_mac_start(struct qwx_softc *);
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void qwx_mac_scan_finish(struct qwx_softc *);
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int qwx_mac_mgmt_tx_wmi(struct qwx_softc *, struct qwx_vif *, uint8_t,
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struct mbuf *);
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int qwx_dp_tx_send_reo_cmd(struct qwx_softc *, struct dp_rx_tid *,
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enum hal_reo_cmd_type , struct ath11k_hal_reo_cmd *,
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void (*func)(struct qwx_dp *, void *, enum hal_reo_cmd_status));
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@ -343,13 +345,86 @@ qwx_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
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return err;
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}
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int
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qwx_tx(struct qwx_softc *sc, struct mbuf *m, struct ieee80211_node *ni)
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{
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struct ieee80211_frame *wh;
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struct qwx_vif *arvif = TAILQ_FIRST(&sc->vif_list); /* XXX */
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uint8_t pdev_id = 0; /* TODO: derive pdev ID somehow? */
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uint8_t frame_type;
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wh = mtod(m, struct ieee80211_frame *);
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frame_type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
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if (frame_type == IEEE80211_FC0_TYPE_MGT)
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return qwx_mac_mgmt_tx_wmi(sc, arvif, pdev_id, m);
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printf("%s: not implemented\n", sc->sc_dev.dv_xname);
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m_freem(m);
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return ENOTSUP;
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}
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void
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qwx_start(struct ifnet *ifp)
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{
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struct qwx_softc *sc = ifp->if_softc;
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struct ieee80211com *ic = &sc->sc_ic;
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struct ieee80211_node *ni;
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struct ether_header *eh;
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struct mbuf *m;
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if (!(ifp->if_flags & IFF_RUNNING) || ifq_is_oactive(&ifp->if_snd))
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return;
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printf("%s: not implemented\n", __func__);
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for (;;) {
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/* why isn't this done per-queue? */
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if (sc->qfullmsk != 0) {
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ifq_set_oactive(&ifp->if_snd);
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break;
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}
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/* need to send management frames even if we're not RUNning */
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m = mq_dequeue(&ic->ic_mgtq);
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if (m) {
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ni = m->m_pkthdr.ph_cookie;
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goto sendit;
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}
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if (ic->ic_state != IEEE80211_S_RUN ||
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(ic->ic_xflags & IEEE80211_F_TX_MGMT_ONLY))
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break;
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m = ifq_dequeue(&ifp->if_snd);
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if (!m)
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break;
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if (m->m_len < sizeof (*eh) &&
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(m = m_pullup(m, sizeof (*eh))) == NULL) {
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ifp->if_oerrors++;
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continue;
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}
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#if NBPFILTER > 0
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if (ifp->if_bpf != NULL)
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bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT);
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#endif
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if ((m = ieee80211_encap(ifp, m, &ni)) == NULL) {
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ifp->if_oerrors++;
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continue;
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}
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sendit:
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#if NBPFILTER > 0
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if (ic->ic_rawbpf != NULL)
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bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT);
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#endif
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if (qwx_tx(sc, m, ni) != 0) {
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ieee80211_release_node(ic, ni);
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ifp->if_oerrors++;
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continue;
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}
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if (ifp->if_flags & IFF_UP)
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ifp->if_timer = 1;
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}
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}
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void
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@ -11646,6 +11721,91 @@ exit:
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#endif
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}
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int
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qwx_pull_mgmt_tx_compl_param_tlv(struct qwx_softc *sc, struct mbuf *m,
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struct wmi_mgmt_tx_compl_event *param)
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{
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const void **tb;
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const struct wmi_mgmt_tx_compl_event *ev;
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int ret = 0;
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tb = qwx_wmi_tlv_parse_alloc(sc, mtod(m, void *), m->m_pkthdr.len);
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if (tb == NULL) {
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ret = ENOMEM;
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printf("%s: failed to parse tlv: %d\n",
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sc->sc_dev.dv_xname, ret);
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return ENOMEM;
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}
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ev = tb[WMI_TAG_MGMT_TX_COMPL_EVENT];
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if (!ev) {
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printf("%s: failed to fetch mgmt tx compl ev\n",
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sc->sc_dev.dv_xname);
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free(tb, M_DEVBUF, WMI_TAG_MAX * sizeof(*tb));
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return EPROTO;
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}
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param->pdev_id = ev->pdev_id;
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param->desc_id = ev->desc_id;
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param->status = ev->status;
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param->ack_rssi = ev->ack_rssi;
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free(tb, M_DEVBUF, WMI_TAG_MAX * sizeof(*tb));
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return 0;
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}
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void
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qwx_wmi_process_mgmt_tx_comp(struct qwx_softc *sc,
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struct wmi_mgmt_tx_compl_event *tx_compl_param)
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{
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struct ieee80211com *ic = &sc->sc_ic;
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struct qwx_vif *arvif = TAILQ_FIRST(&sc->vif_list); /* XXX */
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struct ifnet *ifp = &ic->ic_if;
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struct qwx_tx_data *tx_data;
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if (tx_compl_param->desc_id >= nitems(arvif->txmgmt.data)) {
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printf("%s: received mgmt tx compl for invalid buf_id: %d\n",
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sc->sc_dev.dv_xname, tx_compl_param->desc_id);
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return;
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}
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tx_data = &arvif->txmgmt.data[tx_compl_param->desc_id];
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if (tx_data->m == NULL) {
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printf("%s: received mgmt tx compl for invalid buf_id: %d\n",
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sc->sc_dev.dv_xname, tx_compl_param->desc_id);
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return;
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}
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bus_dmamap_unload(sc->sc_dmat, tx_data->map);
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m_freem(tx_data->m);
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tx_data->m = NULL;
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if (arvif->txmgmt.queued > 0)
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arvif->txmgmt.queued--;
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if (tx_compl_param->status != 0)
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ifp->if_oerrors++;
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}
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void
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qwx_mgmt_tx_compl_event(struct qwx_softc *sc, struct mbuf *m)
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{
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struct wmi_mgmt_tx_compl_event tx_compl_param = { 0 };
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if (qwx_pull_mgmt_tx_compl_param_tlv(sc, m, &tx_compl_param) != 0) {
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printf("%s: failed to extract mgmt tx compl event\n",
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sc->sc_dev.dv_xname);
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return;
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}
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qwx_wmi_process_mgmt_tx_comp(sc, &tx_compl_param);
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DNPRINTF(QWX_D_MGMT, "%s: event mgmt tx compl ev pdev_id %d, "
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"desc_id %d, status %d ack_rssi %d", __func__,
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tx_compl_param.pdev_id, tx_compl_param.desc_id,
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tx_compl_param.status, tx_compl_param.ack_rssi);
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}
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void
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qwx_wmi_tlv_op_rx(struct qwx_softc *sc, struct mbuf *m)
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{
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@ -11696,11 +11856,9 @@ qwx_wmi_tlv_op_rx(struct qwx_softc *sc, struct mbuf *m)
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qwx_mgmt_rx_event(sc, m);
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/* mgmt_rx_event() owns the skb now! */
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return;
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#if 0
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case WMI_MGMT_TX_COMPLETION_EVENTID:
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ath11k_mgmt_tx_compl_event(ab, skb);
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qwx_mgmt_tx_compl_event(sc, m);
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break;
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#endif
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case WMI_SCAN_EVENTID:
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DPRINTF("%s: 0x%x: scan event\n", __func__, id);
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qwx_scan_event(sc, m);
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@ -15249,6 +15407,66 @@ qwx_wmi_set_sta_ps_param(struct qwx_softc *sc, uint32_t vdev_id,
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return 0;
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}
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int
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qwx_wmi_mgmt_send(struct qwx_softc *sc, struct qwx_vif *arvif, uint8_t pdev_id,
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uint32_t buf_id, struct mbuf *frame, struct qwx_tx_data *tx_data)
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{
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struct qwx_pdev_wmi *wmi = &sc->wmi.wmi[pdev_id];
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struct wmi_mgmt_send_cmd *cmd;
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struct wmi_tlv *frame_tlv;
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struct mbuf *m;
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uint32_t buf_len;
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int ret, len;
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uint64_t paddr;
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paddr = tx_data->map->dm_segs[0].ds_addr;
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buf_len = frame->m_pkthdr.len < WMI_MGMT_SEND_DOWNLD_LEN ?
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frame->m_pkthdr.len : WMI_MGMT_SEND_DOWNLD_LEN;
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len = sizeof(*cmd) + sizeof(*frame_tlv) + roundup(buf_len, 4);
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m = qwx_wmi_alloc_mbuf(len);
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if (!m)
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return ENOMEM;
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cmd = (struct wmi_mgmt_send_cmd *)(mtod(m, uint8_t *) +
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sizeof(struct ath11k_htc_hdr) + sizeof(struct wmi_cmd_hdr));
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cmd->tlv_header = FIELD_PREP(WMI_TLV_TAG, WMI_TAG_MGMT_TX_SEND_CMD) |
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FIELD_PREP(WMI_TLV_LEN, sizeof(*cmd) - TLV_HDR_SIZE);
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cmd->vdev_id = arvif->vdev_id;
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cmd->desc_id = buf_id;
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cmd->chanfreq = 0;
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cmd->paddr_lo = paddr & 0xffffffff;
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cmd->paddr_hi = paddr >> 32;
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cmd->frame_len = frame->m_pkthdr.len;
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cmd->buf_len = buf_len;
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cmd->tx_params_valid = 0;
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frame_tlv = (struct wmi_tlv *)(mtod(m, uint8_t *) +
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sizeof(struct ath11k_htc_hdr) + sizeof(struct wmi_cmd_hdr) +
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sizeof(*cmd));
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frame_tlv->header = FIELD_PREP(WMI_TLV_TAG, WMI_TAG_ARRAY_BYTE) |
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FIELD_PREP(WMI_TLV_LEN, buf_len);
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memcpy(frame_tlv->value, mtod(frame, void *), buf_len);
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#if 0 /* Not needed on OpenBSD? */
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ath11k_ce_byte_swap(frame_tlv->value, buf_len);
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#endif
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ret = qwx_wmi_cmd_send(wmi, m, WMI_MGMT_TX_SEND_CMDID);
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if (ret) {
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printf("%s: failed to submit WMI_MGMT_TX_SEND_CMDID cmd\n",
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sc->sc_dev.dv_xname);
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m_freem(m);
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return ret;
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}
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DNPRINTF(QWX_D_WMI, "%s: cmd mgmt tx send", __func__);
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tx_data->m = frame;
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return 0;
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}
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int
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qwx_wmi_vdev_create(struct qwx_softc *sc, uint8_t *macaddr,
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struct vdev_create_params *param)
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@ -18710,6 +18928,61 @@ qwx_mac_vdev_start(struct qwx_softc *sc, struct qwx_vif *arvif, int pdev_id)
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return qwx_mac_vdev_start_restart(sc, arvif, pdev_id, 0);
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}
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void
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qwx_vif_free(struct qwx_softc *sc, struct qwx_vif *arvif)
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{
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struct qwx_txmgmt_queue *txmgmt;
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int i;
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if (arvif == NULL)
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return;
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txmgmt = &arvif->txmgmt;
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for (i = 0; i < nitems(txmgmt->data); i++) {
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struct qwx_tx_data *tx_data = &txmgmt->data[i];
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if (tx_data->m) {
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m_freem(tx_data->m);
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tx_data->m = NULL;
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}
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if (tx_data->map) {
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bus_dmamap_destroy(sc->sc_dmat, tx_data->map);
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tx_data->map = NULL;
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}
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}
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free(arvif, M_DEVBUF, sizeof(*arvif));
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}
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struct qwx_vif *
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qwx_vif_alloc(struct qwx_softc *sc)
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{
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struct qwx_vif *arvif;
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struct qwx_txmgmt_queue *txmgmt;
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int i, ret = 0;
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const bus_size_t size = IEEE80211_MAX_LEN;
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arvif = malloc(sizeof(*arvif), M_DEVBUF, M_NOWAIT | M_ZERO);
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if (arvif == NULL)
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return NULL;
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txmgmt = &arvif->txmgmt;
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for (i = 0; i < nitems(txmgmt->data); i++) {
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struct qwx_tx_data *tx_data = &txmgmt->data[i];
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ret = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0,
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BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &tx_data->map);
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if (ret) {
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qwx_vif_free(sc, arvif);
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return NULL;
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}
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}
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arvif->sc = sc;
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return arvif;
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}
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int
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qwx_mac_op_add_interface(struct qwx_pdev *pdev)
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{
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@ -18746,13 +19019,11 @@ qwx_mac_op_add_interface(struct qwx_pdev *pdev)
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goto err;
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}
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arvif = malloc(sizeof(*arvif), M_DEVBUF, M_NOWAIT | M_ZERO);
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arvif = qwx_vif_alloc(sc);
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if (arvif == NULL) {
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ret = ENOMEM;
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goto err;
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}
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arvif->sc = sc;
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#if 0
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INIT_DELAYED_WORK(&arvif->connection_loss_work,
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ath11k_mac_vif_sta_connection_loss_work);
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@ -18983,7 +19254,7 @@ err:
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#ifdef notyet
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mutex_unlock(&ar->conf_mutex);
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#endif
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free(arvif, M_DEVBUF, sizeof(*arvif));
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qwx_vif_free(sc, arvif);
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return ret;
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}
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@ -19907,6 +20178,57 @@ free_peer:
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return ret;
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}
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int
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qwx_mac_mgmt_tx_wmi(struct qwx_softc *sc, struct qwx_vif *arvif,
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uint8_t pdev_id, struct mbuf *m)
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{
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struct qwx_txmgmt_queue *txmgmt = &arvif->txmgmt;
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struct qwx_tx_data *tx_data;
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int buf_id;
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int ret;
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buf_id = txmgmt->cur;
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DNPRINTF(QWX_D_MAC, "%s: tx mgmt frame, buf id %d\n", __func__, buf_id);
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if (txmgmt->queued >= nitems(txmgmt->data))
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return ENOSPC;
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tx_data = &txmgmt->data[buf_id];
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#if 0
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if (!(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP)) {
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if ((ieee80211_is_action(hdr->frame_control) ||
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ieee80211_is_deauth(hdr->frame_control) ||
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ieee80211_is_disassoc(hdr->frame_control)) &&
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ieee80211_has_protected(hdr->frame_control)) {
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skb_put(skb, IEEE80211_CCMP_MIC_LEN);
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}
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}
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#endif
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ret = bus_dmamap_load_mbuf(sc->sc_dmat, tx_data->map,
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m, BUS_DMA_WRITE | BUS_DMA_NOWAIT);
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if (ret) {
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printf("%s: failed to map mgmt Tx buffer: %d\n",
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sc->sc_dev.dv_xname, ret);
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return ret;
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}
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|
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ret = qwx_wmi_mgmt_send(sc, arvif, pdev_id, buf_id, m, tx_data);
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if (ret) {
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printf("%s: failed to send mgmt frame: %d\n",
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sc->sc_dev.dv_xname, ret);
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goto err_unmap_buf;
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}
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txmgmt->cur = (txmgmt->cur + 1) % nitems(txmgmt->data);
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txmgmt->queued++;
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return 0;
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err_unmap_buf:
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bus_dmamap_unload(sc->sc_dmat, tx_data->map);
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return ret;
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}
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|
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void
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qwx_wmi_start_scan_init(struct qwx_softc *sc, struct scan_req_params *arg)
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{
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|
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|
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|
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@ -1,4 +1,4 @@
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/* $OpenBSD: qwxreg.h,v 1.2 2024/01/25 10:11:04 stsp Exp $ */
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/* $OpenBSD: qwxreg.h,v 1.3 2024/01/28 22:30:39 stsp Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc.
|
||||
|
|
@ -3857,12 +3857,6 @@ struct wmi_scan_prob_req_oui_cmd {
|
|||
#define WMI_TX_PARAMS_DWORD1_FRAME_TYPE BIT(20)
|
||||
#define WMI_TX_PARAMS_DWORD1_RSVD GENMASK(31, 21)
|
||||
|
||||
struct wmi_mgmt_send_params {
|
||||
uint32_t tlv_header;
|
||||
uint32_t tx_params_dword0;
|
||||
uint32_t tx_params_dword1;
|
||||
};
|
||||
|
||||
struct wmi_mgmt_send_cmd {
|
||||
uint32_t tlv_header;
|
||||
uint32_t vdev_id;
|
||||
|
|
@ -3874,9 +3868,13 @@ struct wmi_mgmt_send_cmd {
|
|||
uint32_t buf_len;
|
||||
uint32_t tx_params_valid;
|
||||
|
||||
/* This TLV is followed by struct wmi_mgmt_frame */
|
||||
|
||||
/* Followed by struct wmi_mgmt_send_params */
|
||||
/*
|
||||
* Followed by struct wmi_tlv and buf_len bytes of frame data with
|
||||
* buf_len <= WMI_MGMT_SEND_DOWNLD_LEN, which may be exceeded by
|
||||
* frame_len. The full frame is mapped at paddr_lo/hi.
|
||||
* Presumably the idea is that small frames can skip the extra DMA
|
||||
* transfer of frame data after the command has been transferred.
|
||||
*/
|
||||
} __packed;
|
||||
|
||||
struct wmi_sta_powersave_mode_cmd {
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $OpenBSD: qwxvar.h,v 1.5 2024/01/25 17:00:21 stsp Exp $ */
|
||||
/* $OpenBSD: qwxvar.h,v 1.6 2024/01/28 22:30:39 stsp Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2018-2019 The Linux Foundation.
|
||||
|
|
@ -718,7 +718,7 @@ struct qwx_tx_data {
|
|||
uint8_t eid;
|
||||
uint8_t flags;
|
||||
uint32_t cipher;
|
||||
} __packed;
|
||||
};
|
||||
|
||||
struct qwx_ce_ring {
|
||||
/* Number of entries in this ring; must be power of 2 */
|
||||
|
|
@ -1468,6 +1468,12 @@ struct qwx_pdev_dp {
|
|||
struct qwx_mon_data mon_data;
|
||||
};
|
||||
|
||||
struct qwx_txmgmt_queue {
|
||||
struct qwx_tx_data data[8];
|
||||
int cur;
|
||||
int queued;
|
||||
};
|
||||
|
||||
struct qwx_vif {
|
||||
uint32_t vdev_id;
|
||||
enum wmi_vdev_type vdev_type;
|
||||
|
|
@ -1528,6 +1534,8 @@ struct qwx_vif {
|
|||
#ifdef CONFIG_ATH11K_DEBUGFS
|
||||
struct dentry *debugfs_twt;
|
||||
#endif /* CONFIG_ATH11K_DEBUGFS */
|
||||
|
||||
struct qwx_txmgmt_queue txmgmt;
|
||||
};
|
||||
|
||||
TAILQ_HEAD(qwx_vif_list, qwx_vif);
|
||||
|
|
@ -1591,6 +1599,7 @@ struct qwx_softc {
|
|||
int have_firmware;
|
||||
|
||||
int sc_tx_timer;
|
||||
uint32_t qfullmsk;
|
||||
|
||||
bus_addr_t mem;
|
||||
struct ath11k_hw_params hw_params;
|
||||
|
|
|
|||
|
|
@ -755,7 +755,7 @@ static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf,
|
|||
int r;
|
||||
|
||||
if (!adev->smc_rreg)
|
||||
return -EPERM;
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
if (size & 0x3 || *pos & 0x3)
|
||||
return -EINVAL;
|
||||
|
|
@ -814,7 +814,7 @@ static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *
|
|||
int r;
|
||||
|
||||
if (!adev->smc_wreg)
|
||||
return -EPERM;
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
if (size & 0x3 || *pos & 0x3)
|
||||
return -EINVAL;
|
||||
|
|
|
|||
|
|
@ -1026,7 +1026,12 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
|
|||
if (amdgpu_dpm_read_sensor(adev,
|
||||
AMDGPU_PP_SENSOR_GPU_AVG_POWER,
|
||||
(void *)&ui32, &ui32_size)) {
|
||||
return -EINVAL;
|
||||
/* fall back to input power for backwards compat */
|
||||
if (amdgpu_dpm_read_sensor(adev,
|
||||
AMDGPU_PP_SENSOR_GPU_INPUT_POWER,
|
||||
(void *)&ui32, &ui32_size)) {
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
ui32 >>= 8;
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -330,12 +330,6 @@ static void kfd_init_apertures_vi(struct kfd_process_device *pdd, uint8_t id)
|
|||
pdd->gpuvm_limit =
|
||||
pdd->dev->kfd->shared_resources.gpuvm_size - 1;
|
||||
|
||||
/* dGPUs: the reserved space for kernel
|
||||
* before SVM
|
||||
*/
|
||||
pdd->qpd.cwsr_base = SVM_CWSR_BASE;
|
||||
pdd->qpd.ib_base = SVM_IB_BASE;
|
||||
|
||||
pdd->scratch_base = MAKE_SCRATCH_APP_BASE_VI();
|
||||
pdd->scratch_limit = MAKE_SCRATCH_APP_LIMIT(pdd->scratch_base);
|
||||
}
|
||||
|
|
@ -345,18 +339,18 @@ static void kfd_init_apertures_v9(struct kfd_process_device *pdd, uint8_t id)
|
|||
pdd->lds_base = MAKE_LDS_APP_BASE_V9();
|
||||
pdd->lds_limit = MAKE_LDS_APP_LIMIT(pdd->lds_base);
|
||||
|
||||
pdd->gpuvm_base = PAGE_SIZE;
|
||||
/* Raven needs SVM to support graphic handle, etc. Leave the small
|
||||
* reserved space before SVM on Raven as well, even though we don't
|
||||
* have to.
|
||||
* Set gpuvm_base and gpuvm_limit to CANONICAL addresses so that they
|
||||
* are used in Thunk to reserve SVM.
|
||||
*/
|
||||
pdd->gpuvm_base = SVM_USER_BASE;
|
||||
pdd->gpuvm_limit =
|
||||
pdd->dev->kfd->shared_resources.gpuvm_size - 1;
|
||||
|
||||
pdd->scratch_base = MAKE_SCRATCH_APP_BASE_V9();
|
||||
pdd->scratch_limit = MAKE_SCRATCH_APP_LIMIT(pdd->scratch_base);
|
||||
|
||||
/*
|
||||
* Place TBA/TMA on opposite side of VM hole to prevent
|
||||
* stray faults from triggering SVM on these pages.
|
||||
*/
|
||||
pdd->qpd.cwsr_base = pdd->dev->kfd->shared_resources.gpuvm_size;
|
||||
}
|
||||
|
||||
int kfd_init_apertures(struct kfd_process *process)
|
||||
|
|
@ -413,6 +407,12 @@ int kfd_init_apertures(struct kfd_process *process)
|
|||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
/* dGPUs: the reserved space for kernel
|
||||
* before SVM
|
||||
*/
|
||||
pdd->qpd.cwsr_base = SVM_CWSR_BASE;
|
||||
pdd->qpd.ib_base = SVM_IB_BASE;
|
||||
}
|
||||
|
||||
dev_dbg(kfd_device, "node id %u\n", id);
|
||||
|
|
|
|||
|
|
@ -1021,7 +1021,7 @@ int kgd2kfd_init_zone_device(struct amdgpu_device *adev)
|
|||
} else {
|
||||
res = devm_request_free_mem_region(adev->dev, &iomem_resource, size);
|
||||
if (IS_ERR(res))
|
||||
return -ENOMEM;
|
||||
return PTR_ERR(res);
|
||||
pgmap->range.start = res->start;
|
||||
pgmap->range.end = res->end;
|
||||
pgmap->type = MEMORY_DEVICE_PRIVATE;
|
||||
|
|
@ -1037,10 +1037,10 @@ int kgd2kfd_init_zone_device(struct amdgpu_device *adev)
|
|||
r = devm_memremap_pages(adev->dev, pgmap);
|
||||
if (IS_ERR(r)) {
|
||||
pr_err("failed to register HMM device memory\n");
|
||||
/* Disable SVM support capability */
|
||||
pgmap->type = 0;
|
||||
if (pgmap->type == MEMORY_DEVICE_PRIVATE)
|
||||
devm_release_mem_region(adev->dev, res->start, resource_size(res));
|
||||
/* Disable SVM support capability */
|
||||
pgmap->type = 0;
|
||||
return PTR_ERR(r);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -971,7 +971,7 @@ struct kfd_process {
|
|||
struct work_struct debug_event_workarea;
|
||||
|
||||
/* Tracks debug per-vmid request for debug flags */
|
||||
bool dbg_flags;
|
||||
u32 dbg_flags;
|
||||
|
||||
atomic_t poison;
|
||||
/* Queues are in paused stated because we are in the process of doing a CRIU checkpoint */
|
||||
|
|
|
|||
|
|
@ -1342,10 +1342,11 @@ static int kfd_create_indirect_link_prop(struct kfd_topology_device *kdev, int g
|
|||
num_cpu++;
|
||||
}
|
||||
|
||||
if (list_empty(&kdev->io_link_props))
|
||||
return -ENODATA;
|
||||
|
||||
gpu_link = list_first_entry(&kdev->io_link_props,
|
||||
struct kfd_iolink_properties, list);
|
||||
if (!gpu_link)
|
||||
return -ENOMEM;
|
||||
struct kfd_iolink_properties, list);
|
||||
|
||||
for (i = 0; i < num_cpu; i++) {
|
||||
/* CPU <--> GPU */
|
||||
|
|
@ -1423,15 +1424,17 @@ static int kfd_add_peer_prop(struct kfd_topology_device *kdev,
|
|||
peer->gpu->adev))
|
||||
return ret;
|
||||
|
||||
if (list_empty(&kdev->io_link_props))
|
||||
return -ENODATA;
|
||||
|
||||
iolink1 = list_first_entry(&kdev->io_link_props,
|
||||
struct kfd_iolink_properties, list);
|
||||
if (!iolink1)
|
||||
return -ENOMEM;
|
||||
struct kfd_iolink_properties, list);
|
||||
|
||||
if (list_empty(&peer->io_link_props))
|
||||
return -ENODATA;
|
||||
|
||||
iolink2 = list_first_entry(&peer->io_link_props,
|
||||
struct kfd_iolink_properties, list);
|
||||
if (!iolink2)
|
||||
return -ENOMEM;
|
||||
struct kfd_iolink_properties, list);
|
||||
|
||||
props = kfd_alloc_struct(props);
|
||||
if (!props)
|
||||
|
|
|
|||
|
|
@ -6886,7 +6886,7 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
|
|||
max_bpc);
|
||||
bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
|
||||
clock = adjusted_mode->clock;
|
||||
dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false);
|
||||
dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp << 4);
|
||||
}
|
||||
|
||||
dm_new_connector_state->vcpi_slots =
|
||||
|
|
|
|||
|
|
@ -1636,7 +1636,7 @@ enum dc_status dm_dp_mst_is_port_support_mode(
|
|||
} else {
|
||||
/* check if mode could be supported within full_pbn */
|
||||
bpp = convert_dc_color_depth_into_bpc(stream->timing.display_color_depth) * 3;
|
||||
pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp, false);
|
||||
pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp << 4);
|
||||
if (pbn > full_pbn)
|
||||
return DC_FAIL_BANDWIDTH_VALIDATE;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -807,7 +807,7 @@ void dp_decide_lane_settings(
|
|||
const struct link_training_settings *lt_settings,
|
||||
const union lane_adjust ln_adjust[LANE_COUNT_DP_MAX],
|
||||
struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX],
|
||||
union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX])
|
||||
union dpcd_training_lane *dpcd_lane_settings)
|
||||
{
|
||||
uint32_t lane;
|
||||
|
||||
|
|
|
|||
|
|
@ -111,7 +111,7 @@ void dp_decide_lane_settings(
|
|||
const struct link_training_settings *lt_settings,
|
||||
const union lane_adjust ln_adjust[LANE_COUNT_DP_MAX],
|
||||
struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX],
|
||||
union dpcd_training_lane dpcd_lane_settings[LANE_COUNT_DP_MAX]);
|
||||
union dpcd_training_lane *dpcd_lane_settings);
|
||||
|
||||
enum dc_dp_training_pattern decide_cr_training_pattern(
|
||||
const struct dc_link_settings *link_settings);
|
||||
|
|
|
|||
|
|
@ -2735,10 +2735,8 @@ static int kv_parse_power_table(struct amdgpu_device *adev)
|
|||
non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
|
||||
&non_clock_info_array->nonClockInfo[non_clock_array_index];
|
||||
ps = kzalloc(sizeof(struct kv_ps), GFP_KERNEL);
|
||||
if (ps == NULL) {
|
||||
kfree(adev->pm.dpm.ps);
|
||||
if (ps == NULL)
|
||||
return -ENOMEM;
|
||||
}
|
||||
adev->pm.dpm.ps[i].ps_priv = ps;
|
||||
k = 0;
|
||||
idx = (u8 *)&power_state->v2.clockInfoIndex[0];
|
||||
|
|
|
|||
|
|
@ -7379,10 +7379,9 @@ static int si_dpm_init(struct amdgpu_device *adev)
|
|||
kcalloc(4,
|
||||
sizeof(struct amdgpu_clock_voltage_dependency_entry),
|
||||
GFP_KERNEL);
|
||||
if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
|
||||
amdgpu_free_extended_power_table(adev);
|
||||
if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries)
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
|
||||
adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
|
||||
adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
|
||||
|
|
|
|||
|
|
@ -272,10 +272,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev)
|
|||
le16_to_cpu(power_info->pplib4.usVddcDependencyOnSCLKOffset));
|
||||
ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
|
||||
dep_table);
|
||||
if (ret) {
|
||||
amdgpu_free_extended_power_table(adev);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
if (power_info->pplib4.usVddciDependencyOnMCLKOffset) {
|
||||
dep_table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *)
|
||||
|
|
@ -283,10 +281,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev)
|
|||
le16_to_cpu(power_info->pplib4.usVddciDependencyOnMCLKOffset));
|
||||
ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
|
||||
dep_table);
|
||||
if (ret) {
|
||||
amdgpu_free_extended_power_table(adev);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
if (power_info->pplib4.usVddcDependencyOnMCLKOffset) {
|
||||
dep_table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *)
|
||||
|
|
@ -294,10 +290,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev)
|
|||
le16_to_cpu(power_info->pplib4.usVddcDependencyOnMCLKOffset));
|
||||
ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
|
||||
dep_table);
|
||||
if (ret) {
|
||||
amdgpu_free_extended_power_table(adev);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
if (power_info->pplib4.usMvddDependencyOnMCLKOffset) {
|
||||
dep_table = (ATOM_PPLIB_Clock_Voltage_Dependency_Table *)
|
||||
|
|
@ -305,10 +299,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev)
|
|||
le16_to_cpu(power_info->pplib4.usMvddDependencyOnMCLKOffset));
|
||||
ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
|
||||
dep_table);
|
||||
if (ret) {
|
||||
amdgpu_free_extended_power_table(adev);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
if (power_info->pplib4.usMaxClockVoltageOnDCOffset) {
|
||||
ATOM_PPLIB_Clock_Voltage_Limit_Table *clk_v =
|
||||
|
|
@ -339,10 +331,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev)
|
|||
kcalloc(psl->ucNumEntries,
|
||||
sizeof(struct amdgpu_phase_shedding_limits_entry),
|
||||
GFP_KERNEL);
|
||||
if (!adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries) {
|
||||
amdgpu_free_extended_power_table(adev);
|
||||
if (!adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries)
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
entry = &psl->entries[0];
|
||||
for (i = 0; i < psl->ucNumEntries; i++) {
|
||||
|
|
@ -383,10 +373,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev)
|
|||
ATOM_PPLIB_CAC_Leakage_Record *entry;
|
||||
u32 size = cac_table->ucNumEntries * sizeof(struct amdgpu_cac_leakage_table);
|
||||
adev->pm.dpm.dyn_state.cac_leakage_table.entries = kzalloc(size, GFP_KERNEL);
|
||||
if (!adev->pm.dpm.dyn_state.cac_leakage_table.entries) {
|
||||
amdgpu_free_extended_power_table(adev);
|
||||
if (!adev->pm.dpm.dyn_state.cac_leakage_table.entries)
|
||||
return -ENOMEM;
|
||||
}
|
||||
entry = &cac_table->entries[0];
|
||||
for (i = 0; i < cac_table->ucNumEntries; i++) {
|
||||
if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
|
||||
|
|
@ -438,10 +426,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev)
|
|||
sizeof(struct amdgpu_vce_clock_voltage_dependency_entry);
|
||||
adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries =
|
||||
kzalloc(size, GFP_KERNEL);
|
||||
if (!adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries) {
|
||||
amdgpu_free_extended_power_table(adev);
|
||||
if (!adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries)
|
||||
return -ENOMEM;
|
||||
}
|
||||
adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count =
|
||||
limits->numEntries;
|
||||
entry = &limits->entries[0];
|
||||
|
|
@ -493,10 +479,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev)
|
|||
sizeof(struct amdgpu_uvd_clock_voltage_dependency_entry);
|
||||
adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries =
|
||||
kzalloc(size, GFP_KERNEL);
|
||||
if (!adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries) {
|
||||
amdgpu_free_extended_power_table(adev);
|
||||
if (!adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries)
|
||||
return -ENOMEM;
|
||||
}
|
||||
adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count =
|
||||
limits->numEntries;
|
||||
entry = &limits->entries[0];
|
||||
|
|
@ -525,10 +509,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev)
|
|||
sizeof(struct amdgpu_clock_voltage_dependency_entry);
|
||||
adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries =
|
||||
kzalloc(size, GFP_KERNEL);
|
||||
if (!adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries) {
|
||||
amdgpu_free_extended_power_table(adev);
|
||||
if (!adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries)
|
||||
return -ENOMEM;
|
||||
}
|
||||
adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count =
|
||||
limits->numEntries;
|
||||
entry = &limits->entries[0];
|
||||
|
|
@ -548,10 +530,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev)
|
|||
le16_to_cpu(ext_hdr->usPPMTableOffset));
|
||||
adev->pm.dpm.dyn_state.ppm_table =
|
||||
kzalloc(sizeof(struct amdgpu_ppm_table), GFP_KERNEL);
|
||||
if (!adev->pm.dpm.dyn_state.ppm_table) {
|
||||
amdgpu_free_extended_power_table(adev);
|
||||
if (!adev->pm.dpm.dyn_state.ppm_table)
|
||||
return -ENOMEM;
|
||||
}
|
||||
adev->pm.dpm.dyn_state.ppm_table->ppm_design = ppm->ucPpmDesign;
|
||||
adev->pm.dpm.dyn_state.ppm_table->cpu_core_number =
|
||||
le16_to_cpu(ppm->usCpuCoreNumber);
|
||||
|
|
@ -583,10 +563,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev)
|
|||
sizeof(struct amdgpu_clock_voltage_dependency_entry);
|
||||
adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries =
|
||||
kzalloc(size, GFP_KERNEL);
|
||||
if (!adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries) {
|
||||
amdgpu_free_extended_power_table(adev);
|
||||
if (!adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries)
|
||||
return -ENOMEM;
|
||||
}
|
||||
adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count =
|
||||
limits->numEntries;
|
||||
entry = &limits->entries[0];
|
||||
|
|
@ -606,10 +584,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev)
|
|||
ATOM_PowerTune_Table *pt;
|
||||
adev->pm.dpm.dyn_state.cac_tdp_table =
|
||||
kzalloc(sizeof(struct amdgpu_cac_tdp_table), GFP_KERNEL);
|
||||
if (!adev->pm.dpm.dyn_state.cac_tdp_table) {
|
||||
amdgpu_free_extended_power_table(adev);
|
||||
if (!adev->pm.dpm.dyn_state.cac_tdp_table)
|
||||
return -ENOMEM;
|
||||
}
|
||||
if (rev > 0) {
|
||||
ATOM_PPLIB_POWERTUNE_Table_V1 *ppt = (ATOM_PPLIB_POWERTUNE_Table_V1 *)
|
||||
(mode_info->atom_context->bios + data_offset +
|
||||
|
|
@ -645,10 +621,8 @@ int amdgpu_parse_extended_power_table(struct amdgpu_device *adev)
|
|||
ret = amdgpu_parse_clk_voltage_dep_table(
|
||||
&adev->pm.dpm.dyn_state.vddgfx_dependency_on_sclk,
|
||||
dep_table);
|
||||
if (ret) {
|
||||
kfree(adev->pm.dpm.dyn_state.vddgfx_dependency_on_sclk.entries);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -2974,6 +2974,8 @@ static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
|
|||
result = smu7_get_evv_voltages(hwmgr);
|
||||
if (result) {
|
||||
pr_info("Get EVV Voltage Failed. Abort Driver loading!\n");
|
||||
kfree(hwmgr->backend);
|
||||
hwmgr->backend = NULL;
|
||||
return -EINVAL;
|
||||
}
|
||||
} else {
|
||||
|
|
@ -3019,8 +3021,10 @@ static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
|
|||
}
|
||||
|
||||
result = smu7_update_edc_leakage_table(hwmgr);
|
||||
if (result)
|
||||
if (result) {
|
||||
smu7_hwmgr_backend_fini(hwmgr);
|
||||
return result;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4700,13 +4700,12 @@ EXPORT_SYMBOL(drm_dp_check_act_status);
|
|||
|
||||
/**
|
||||
* drm_dp_calc_pbn_mode() - Calculate the PBN for a mode.
|
||||
* @clock: dot clock for the mode
|
||||
* @bpp: bpp for the mode.
|
||||
* @dsc: DSC mode. If true, bpp has units of 1/16 of a bit per pixel
|
||||
* @clock: dot clock
|
||||
* @bpp: bpp as .4 binary fixed point
|
||||
*
|
||||
* This uses the formula in the spec to calculate the PBN value for a mode.
|
||||
*/
|
||||
int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc)
|
||||
int drm_dp_calc_pbn_mode(int clock, int bpp)
|
||||
{
|
||||
/*
|
||||
* margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
|
||||
|
|
@ -4717,18 +4716,9 @@ int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc)
|
|||
* peak_kbps *= (1006/1000)
|
||||
* peak_kbps *= (64/54)
|
||||
* peak_kbps *= 8 convert to bytes
|
||||
*
|
||||
* If the bpp is in units of 1/16, further divide by 16. Put this
|
||||
* factor in the numerator rather than the denominator to avoid
|
||||
* integer overflow
|
||||
*/
|
||||
|
||||
if (dsc)
|
||||
return DIV_ROUND_UP_ULL(mul_u32_u32(clock * (bpp / 16), 64 * 1006),
|
||||
8 * 54 * 1000 * 1000);
|
||||
|
||||
return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006),
|
||||
8 * 54 * 1000 * 1000);
|
||||
return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006 >> 4),
|
||||
1000 * 8 * 54 * 1000);
|
||||
}
|
||||
EXPORT_SYMBOL(drm_dp_calc_pbn_mode);
|
||||
|
||||
|
|
|
|||
|
|
@ -1042,8 +1042,11 @@ int drm_dev_register(struct drm_device *dev, unsigned long flags)
|
|||
goto err_minors;
|
||||
}
|
||||
|
||||
if (drm_core_check_feature(dev, DRIVER_MODESET))
|
||||
drm_modeset_register_all(dev);
|
||||
if (drm_core_check_feature(dev, DRIVER_MODESET)) {
|
||||
ret = drm_modeset_register_all(dev);
|
||||
if (ret)
|
||||
goto err_unload;
|
||||
}
|
||||
|
||||
DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n",
|
||||
driver->name, driver->major, driver->minor,
|
||||
|
|
@ -1053,6 +1056,9 @@ int drm_dev_register(struct drm_device *dev, unsigned long flags)
|
|||
|
||||
goto out_unlock;
|
||||
|
||||
err_unload:
|
||||
if (dev->driver->unload)
|
||||
dev->driver->unload(dev);
|
||||
err_minors:
|
||||
remove_compat_control_link(dev);
|
||||
drm_minor_unregister(dev, DRM_MINOR_ACCEL);
|
||||
|
|
|
|||
|
|
@ -109,8 +109,7 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
|
|||
continue;
|
||||
|
||||
crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock,
|
||||
dsc ? bpp << 4 : bpp,
|
||||
dsc);
|
||||
bpp << 4);
|
||||
|
||||
slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr,
|
||||
connector->port,
|
||||
|
|
@ -941,7 +940,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
|
|||
return ret;
|
||||
|
||||
if (mode_rate > max_rate || mode->clock > max_dotclk ||
|
||||
drm_dp_calc_pbn_mode(mode->clock, min_bpp, false) > port->full_pbn) {
|
||||
drm_dp_calc_pbn_mode(mode->clock, min_bpp << 4) > port->full_pbn) {
|
||||
*status = MODE_CLOCK_HIGH;
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -832,7 +832,7 @@ struct edid *drm_dp_mst_get_edid(struct drm_connector *connector,
|
|||
int drm_dp_get_vc_payload_bw(const struct drm_dp_mst_topology_mgr *mgr,
|
||||
int link_rate, int link_lane_count);
|
||||
|
||||
int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc);
|
||||
int drm_dp_calc_pbn_mode(int clock, int bpp);
|
||||
|
||||
void drm_dp_mst_update_slots(struct drm_dp_mst_topology_state *mst_state, uint8_t link_encoding_cap);
|
||||
|
||||
|
|
|
|||
|
|
@ -192,7 +192,7 @@ struct drm_bridge_funcs {
|
|||
* or &drm_encoder_helper_funcs.dpms hook.
|
||||
*
|
||||
* The bridge must assume that the display pipe (i.e. clocks and timing
|
||||
* singals) feeding it is no longer running when this callback is
|
||||
* signals) feeding it is no longer running when this callback is
|
||||
* called.
|
||||
*
|
||||
* The @post_disable callback is optional.
|
||||
|
|
|
|||
|
|
@ -2321,7 +2321,7 @@ int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
|
|||
switch (prim_walk) {
|
||||
case 1:
|
||||
for (i = 0; i < track->num_arrays; i++) {
|
||||
size = track->arrays[i].esize * track->max_indx * 4;
|
||||
size = track->arrays[i].esize * track->max_indx * 4UL;
|
||||
if (track->arrays[i].robj == NULL) {
|
||||
DRM_ERROR("(PW %u) Vertex array %u no buffer "
|
||||
"bound\n", prim_walk, i);
|
||||
|
|
@ -2340,7 +2340,7 @@ int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
|
|||
break;
|
||||
case 2:
|
||||
for (i = 0; i < track->num_arrays; i++) {
|
||||
size = track->arrays[i].esize * (nverts - 1) * 4;
|
||||
size = track->arrays[i].esize * (nverts - 1) * 4UL;
|
||||
if (track->arrays[i].robj == NULL) {
|
||||
DRM_ERROR("(PW %u) Vertex array %u no buffer "
|
||||
"bound\n", prim_walk, i);
|
||||
|
|
|
|||
|
|
@ -1275,7 +1275,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
|
|||
return -EINVAL;
|
||||
}
|
||||
tmp = (reg - CB_COLOR0_BASE) / 4;
|
||||
track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
|
||||
track->cb_color_bo_offset[tmp] = (u64)radeon_get_ib_value(p, idx) << 8;
|
||||
ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
|
||||
track->cb_color_base_last[tmp] = ib[idx];
|
||||
track->cb_color_bo[tmp] = reloc->robj;
|
||||
|
|
@ -1302,7 +1302,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
|
|||
"0x%04X\n", reg);
|
||||
return -EINVAL;
|
||||
}
|
||||
track->htile_offset = radeon_get_ib_value(p, idx) << 8;
|
||||
track->htile_offset = (u64)radeon_get_ib_value(p, idx) << 8;
|
||||
ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);
|
||||
track->htile_bo = reloc->robj;
|
||||
track->db_dirty = true;
|
||||
|
|
|
|||
|
|
@ -687,11 +687,16 @@ static void radeon_crtc_init(struct drm_device *dev, int index)
|
|||
if (radeon_crtc == NULL)
|
||||
return;
|
||||
|
||||
radeon_crtc->flip_queue = alloc_workqueue("radeon-crtc", WQ_HIGHPRI, 0);
|
||||
if (!radeon_crtc->flip_queue) {
|
||||
kfree(radeon_crtc);
|
||||
return;
|
||||
}
|
||||
|
||||
drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
|
||||
|
||||
drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
|
||||
radeon_crtc->crtc_id = index;
|
||||
radeon_crtc->flip_queue = alloc_workqueue("radeon-crtc", WQ_HIGHPRI, 0);
|
||||
rdev->mode_info.crtcs[index] = radeon_crtc;
|
||||
|
||||
if (rdev->family >= CHIP_BONAIRE) {
|
||||
|
|
|
|||
|
|
@ -1204,13 +1204,17 @@ int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm)
|
|||
r = radeon_bo_create(rdev, pd_size, align, true,
|
||||
RADEON_GEM_DOMAIN_VRAM, 0, NULL,
|
||||
NULL, &vm->page_directory);
|
||||
if (r)
|
||||
if (r) {
|
||||
kfree(vm->page_tables);
|
||||
vm->page_tables = NULL;
|
||||
return r;
|
||||
|
||||
}
|
||||
r = radeon_vm_clear_bo(rdev, vm->page_directory);
|
||||
if (r) {
|
||||
radeon_bo_unref(&vm->page_directory);
|
||||
vm->page_directory = NULL;
|
||||
kfree(vm->page_tables);
|
||||
vm->page_tables = NULL;
|
||||
return r;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -3611,6 +3611,10 @@ static int si_cp_start(struct radeon_device *rdev)
|
|||
for (i = RADEON_RING_TYPE_GFX_INDEX; i <= CAYMAN_RING_TYPE_CP2_INDEX; ++i) {
|
||||
ring = &rdev->ring[i];
|
||||
r = radeon_ring_lock(rdev, ring, 2);
|
||||
if (r) {
|
||||
DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
|
||||
return r;
|
||||
}
|
||||
|
||||
/* clear the compute context state */
|
||||
radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0));
|
||||
|
|
|
|||
|
|
@ -1493,8 +1493,10 @@ static int sumo_parse_power_table(struct radeon_device *rdev)
|
|||
non_clock_array_index = power_state->v2.nonClockInfoIndex;
|
||||
non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
|
||||
&non_clock_info_array->nonClockInfo[non_clock_array_index];
|
||||
if (!rdev->pm.power_state[i].clock_info)
|
||||
if (!rdev->pm.power_state[i].clock_info) {
|
||||
kfree(rdev->pm.dpm.ps);
|
||||
return -EINVAL;
|
||||
}
|
||||
ps = kzalloc(sizeof(struct sumo_ps), GFP_KERNEL);
|
||||
if (ps == NULL) {
|
||||
kfree(rdev->pm.dpm.ps);
|
||||
|
|
|
|||
|
|
@ -1726,8 +1726,10 @@ static int trinity_parse_power_table(struct radeon_device *rdev)
|
|||
non_clock_array_index = power_state->v2.nonClockInfoIndex;
|
||||
non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
|
||||
&non_clock_info_array->nonClockInfo[non_clock_array_index];
|
||||
if (!rdev->pm.power_state[i].clock_info)
|
||||
if (!rdev->pm.power_state[i].clock_info) {
|
||||
kfree(rdev->pm.dpm.ps);
|
||||
return -EINVAL;
|
||||
}
|
||||
ps = kzalloc(sizeof(struct sumo_ps), GFP_KERNEL);
|
||||
if (ps == NULL) {
|
||||
kfree(rdev->pm.dpm.ps);
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@ POSSIBILITY OF SUCH DAMAGE.
|
|||
|
||||
***************************************************************************/
|
||||
|
||||
/* $OpenBSD: if_em.c,v 1.370 2023/12/31 08:42:33 mglocker Exp $ */
|
||||
/* $OpenBSD: if_em.c,v 1.371 2024/01/28 18:42:58 mglocker Exp $ */
|
||||
/* $FreeBSD: if_em.c,v 1.46 2004/09/29 18:28:28 mlaier Exp $ */
|
||||
|
||||
#include <dev/pci/if_em.h>
|
||||
|
|
@ -291,8 +291,6 @@ void em_receive_checksum(struct em_softc *, struct em_rx_desc *,
|
|||
struct mbuf *);
|
||||
u_int em_transmit_checksum_setup(struct em_queue *, struct mbuf *, u_int,
|
||||
u_int32_t *, u_int32_t *);
|
||||
u_int em_tso_setup(struct em_queue *, struct mbuf *, u_int, u_int32_t *,
|
||||
u_int32_t *);
|
||||
u_int em_tx_ctx_setup(struct em_queue *, struct mbuf *, u_int, u_int32_t *,
|
||||
u_int32_t *);
|
||||
void em_iff(struct em_softc *);
|
||||
|
|
@ -1190,7 +1188,7 @@ em_flowstatus(struct em_softc *sc)
|
|||
*
|
||||
* This routine maps the mbufs to tx descriptors.
|
||||
*
|
||||
* return 0 on failure, positive on success
|
||||
* return 0 on success, positive on failure
|
||||
**********************************************************************/
|
||||
u_int
|
||||
em_encap(struct em_queue *que, struct mbuf *m)
|
||||
|
|
@ -1238,15 +1236,7 @@ em_encap(struct em_queue *que, struct mbuf *m)
|
|||
}
|
||||
|
||||
if (sc->hw.mac_type >= em_82575 && sc->hw.mac_type <= em_i210) {
|
||||
if (ISSET(m->m_pkthdr.csum_flags, M_TCP_TSO)) {
|
||||
used += em_tso_setup(que, m, head, &txd_upper,
|
||||
&txd_lower);
|
||||
if (!used)
|
||||
return (used);
|
||||
} else {
|
||||
used += em_tx_ctx_setup(que, m, head, &txd_upper,
|
||||
&txd_lower);
|
||||
}
|
||||
used += em_tx_ctx_setup(que, m, head, &txd_upper, &txd_lower);
|
||||
} else if (sc->hw.mac_type >= em_82543) {
|
||||
used += em_transmit_checksum_setup(que, m, head,
|
||||
&txd_upper, &txd_lower);
|
||||
|
|
@ -1579,21 +1569,6 @@ em_update_link_status(struct em_softc *sc)
|
|||
ifp->if_link_state = link_state;
|
||||
if_link_state_change(ifp);
|
||||
}
|
||||
|
||||
/* Disable TSO for 10/100 speeds to avoid some hardware issues */
|
||||
switch (sc->link_speed) {
|
||||
case SPEED_10:
|
||||
case SPEED_100:
|
||||
if (sc->hw.mac_type >= em_82575 && sc->hw.mac_type <= em_i210) {
|
||||
ifp->if_capabilities &= ~IFCAP_TSOv4;
|
||||
ifp->if_capabilities &= ~IFCAP_TSOv6;
|
||||
}
|
||||
break;
|
||||
case SPEED_1000:
|
||||
if (sc->hw.mac_type >= em_82575 && sc->hw.mac_type <= em_i210)
|
||||
ifp->if_capabilities |= IFCAP_TSOv4 | IFCAP_TSOv6;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
|
|
@ -2013,7 +1988,6 @@ em_setup_interface(struct em_softc *sc)
|
|||
if (sc->hw.mac_type >= em_82575 && sc->hw.mac_type <= em_i210) {
|
||||
ifp->if_capabilities |= IFCAP_CSUM_IPv4;
|
||||
ifp->if_capabilities |= IFCAP_CSUM_TCPv6 | IFCAP_CSUM_UDPv6;
|
||||
ifp->if_capabilities |= IFCAP_TSOv4 | IFCAP_TSOv6;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -2257,9 +2231,9 @@ em_setup_transmit_structures(struct em_softc *sc)
|
|||
|
||||
for (i = 0; i < sc->sc_tx_slots; i++) {
|
||||
pkt = &que->tx.sc_tx_pkts_ring[i];
|
||||
error = bus_dmamap_create(sc->sc_dmat, EM_TSO_SIZE,
|
||||
error = bus_dmamap_create(sc->sc_dmat, MAX_JUMBO_FRAME_SIZE,
|
||||
EM_MAX_SCATTER / (sc->pcix_82544 ? 2 : 1),
|
||||
EM_TSO_SEG_SIZE, 0, BUS_DMA_NOWAIT, &pkt->pkt_map);
|
||||
MAX_JUMBO_FRAME_SIZE, 0, BUS_DMA_NOWAIT, &pkt->pkt_map);
|
||||
if (error != 0) {
|
||||
printf("%s: Unable to create TX DMA map\n",
|
||||
DEVNAME(sc));
|
||||
|
|
@ -2431,81 +2405,6 @@ em_free_transmit_structures(struct em_softc *sc)
|
|||
}
|
||||
}
|
||||
|
||||
u_int
|
||||
em_tso_setup(struct em_queue *que, struct mbuf *mp, u_int head,
|
||||
u_int32_t *olinfo_status, u_int32_t *cmd_type_len)
|
||||
{
|
||||
struct ether_extracted ext;
|
||||
struct e1000_adv_tx_context_desc *TD;
|
||||
uint32_t vlan_macip_lens = 0, type_tucmd_mlhl = 0, mss_l4len_idx = 0;
|
||||
uint32_t paylen = 0;
|
||||
uint8_t iphlen = 0;
|
||||
|
||||
*olinfo_status = 0;
|
||||
*cmd_type_len = 0;
|
||||
TD = (struct e1000_adv_tx_context_desc *)&que->tx.sc_tx_desc_ring[head];
|
||||
|
||||
#if NVLAN > 0
|
||||
if (ISSET(mp->m_flags, M_VLANTAG)) {
|
||||
uint32_t vtag = mp->m_pkthdr.ether_vtag;
|
||||
vlan_macip_lens |= vtag << E1000_ADVTXD_VLAN_SHIFT;
|
||||
*cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
|
||||
}
|
||||
#endif
|
||||
|
||||
ether_extract_headers(mp, &ext);
|
||||
if (ext.tcp == NULL)
|
||||
goto out;
|
||||
|
||||
vlan_macip_lens |= (sizeof(*ext.eh) << E1000_ADVTXD_MACLEN_SHIFT);
|
||||
|
||||
if (ext.ip4) {
|
||||
iphlen = ext.ip4->ip_hl << 2;
|
||||
|
||||
type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4;
|
||||
*olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
|
||||
#ifdef INET6
|
||||
} else if (ext.ip6) {
|
||||
iphlen = sizeof(*ext.ip6);
|
||||
|
||||
type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV6;
|
||||
#endif
|
||||
} else {
|
||||
goto out;
|
||||
}
|
||||
|
||||
*cmd_type_len |= E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS;
|
||||
*cmd_type_len |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DCMD_TSE;
|
||||
paylen = mp->m_pkthdr.len - sizeof(*ext.eh) - iphlen -
|
||||
(ext.tcp->th_off << 2);
|
||||
*olinfo_status |= paylen << E1000_ADVTXD_PAYLEN_SHIFT;
|
||||
vlan_macip_lens |= iphlen;
|
||||
type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
|
||||
|
||||
type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP;
|
||||
*olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
|
||||
|
||||
mss_l4len_idx |= mp->m_pkthdr.ph_mss << E1000_ADVTXD_MSS_SHIFT;
|
||||
mss_l4len_idx |= (ext.tcp->th_off << 2) << E1000_ADVTXD_L4LEN_SHIFT;
|
||||
/* 82575 needs the queue index added */
|
||||
if (que->sc->hw.mac_type == em_82575)
|
||||
mss_l4len_idx |= (que->me & 0xff) << 4;
|
||||
|
||||
htolem32(&TD->vlan_macip_lens, vlan_macip_lens);
|
||||
htolem32(&TD->type_tucmd_mlhl, type_tucmd_mlhl);
|
||||
htolem32(&TD->u.seqnum_seed, 0);
|
||||
htolem32(&TD->mss_l4len_idx, mss_l4len_idx);
|
||||
|
||||
tcpstat_add(tcps_outpkttso, (paylen + mp->m_pkthdr.ph_mss - 1) /
|
||||
mp->m_pkthdr.ph_mss);
|
||||
|
||||
return 1;
|
||||
|
||||
out:
|
||||
tcpstat_inc(tcps_outbadtso);
|
||||
return 0;
|
||||
}
|
||||
|
||||
u_int
|
||||
em_tx_ctx_setup(struct em_queue *que, struct mbuf *mp, u_int head,
|
||||
u_int32_t *olinfo_status, u_int32_t *cmd_type_len)
|
||||
|
|
|
|||
|
|
@ -32,7 +32,7 @@ POSSIBILITY OF SUCH DAMAGE.
|
|||
***************************************************************************/
|
||||
|
||||
/* $FreeBSD: if_em.h,v 1.26 2004/09/01 23:22:41 pdeuskar Exp $ */
|
||||
/* $OpenBSD: if_em.h,v 1.81 2023/12/31 08:42:33 mglocker Exp $ */
|
||||
/* $OpenBSD: if_em.h,v 1.82 2024/01/28 18:42:58 mglocker Exp $ */
|
||||
|
||||
#ifndef _EM_H_DEFINED_
|
||||
#define _EM_H_DEFINED_
|
||||
|
|
@ -55,14 +55,11 @@ POSSIBILITY OF SUCH DAMAGE.
|
|||
|
||||
#include <net/if.h>
|
||||
#include <net/if_media.h>
|
||||
#include <net/route.h>
|
||||
|
||||
#include <netinet/in.h>
|
||||
#include <netinet/ip.h>
|
||||
#include <netinet/if_ether.h>
|
||||
#include <netinet/tcp.h>
|
||||
#include <netinet/tcp_timer.h>
|
||||
#include <netinet/tcp_var.h>
|
||||
#include <netinet/udp.h>
|
||||
|
||||
#if NBPFILTER > 0
|
||||
|
|
@ -272,7 +269,6 @@ typedef int boolean_t;
|
|||
|
||||
#define EM_MAX_SCATTER 64
|
||||
#define EM_TSO_SIZE 65535
|
||||
#define EM_TSO_SEG_SIZE 4096 /* Max dma segment size */
|
||||
|
||||
struct em_packet {
|
||||
int pkt_eop; /* Index of the desc to watch */
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@
|
|||
|
||||
*******************************************************************************/
|
||||
|
||||
/* $OpenBSD: if_em_hw.h,v 1.91 2023/12/31 08:42:33 mglocker Exp $ */
|
||||
/* $OpenBSD: if_em_hw.h,v 1.92 2024/01/28 18:42:58 mglocker Exp $ */
|
||||
/* $FreeBSD: if_em_hw.h,v 1.15 2005/05/26 23:32:02 tackerman Exp $ */
|
||||
|
||||
/* if_em_hw.h
|
||||
|
|
@ -2150,7 +2150,6 @@ struct e1000_adv_tx_context_desc {
|
|||
#define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
|
||||
#define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */
|
||||
#define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */
|
||||
#define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
|
||||
#define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
|
||||
|
||||
/* Adv Transmit Descriptor Config Masks */
|
||||
|
|
@ -2161,10 +2160,6 @@ struct e1000_adv_tx_context_desc {
|
|||
#define E1000_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */
|
||||
#define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
|
||||
|
||||
/* Req requires Markers and CRC */
|
||||
#define E1000_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
|
||||
#define E1000_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
|
||||
|
||||
/* Multiple Receive Queue Control */
|
||||
#define E1000_MRQC_ENABLE_MASK 0x00000003
|
||||
#define E1000_MRQC_ENABLE_RSS_2Q 0x00000001
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $OpenBSD: pucdata.c,v 1.118 2022/10/24 05:57:58 jsg Exp $ */
|
||||
/* $OpenBSD: pucdata.c,v 1.119 2024/01/28 03:01:39 jsg Exp $ */
|
||||
/* $NetBSD: pucdata.c,v 1.6 1999/07/03 05:55:23 cgd Exp $ */
|
||||
|
||||
/*
|
||||
|
|
@ -306,6 +306,13 @@ const struct puc_device_description puc_devs[] = {
|
|||
{ PUC_PORT_COM, 0x10, 0x0000 },
|
||||
},
|
||||
},
|
||||
{ /* Intel C3000 UART */
|
||||
{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C3000_HSUART, 0x0000, 0x0000 },
|
||||
{ 0xffff, 0xffff, 0x0000, 0x0000 },
|
||||
{
|
||||
{ PUC_PORT_COM, 0x10, 0x0000 },
|
||||
},
|
||||
},
|
||||
/*
|
||||
* XXX no entry because I have no data:
|
||||
* XXX Dolphin Peripherals 4006 (single parallel)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue