sync with OpenBSD -current
This commit is contained in:
parent
2d7157972b
commit
6040ea8924
GPG key ID:
F42C07F07E2E35B7
17 changed files with 989 additions and 255 deletions
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@ -1,4 +1,4 @@
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/* $OpenBSD: hibernate_machdep.c,v 1.50 2023/04/24 09:04:03 dv Exp $ */
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/* $OpenBSD: hibernate_machdep.c,v 1.51 2024/06/05 04:58:05 mglocker Exp $ */
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/*
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* Copyright (c) 2012 Mike Larkin <mlarkin@openbsd.org>
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@ -51,6 +51,7 @@
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#include "sd.h"
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#include "nvme.h"
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#include "sdmmc.h"
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#include "ufshci.h"
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/* Hibernate support */
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void hibernate_enter_resume_4k_pte(vaddr_t, paddr_t);
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@ -97,6 +98,8 @@ get_hibernate_io_function(dev_t dev)
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vaddr_t addr, size_t size, int op, void *page);
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extern int sdmmc_scsi_hibernate_io(dev_t dev, daddr_t blkno,
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vaddr_t addr, size_t size, int op, void *page);
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extern int ufshci_hibernate_io(dev_t dev, daddr_t blkno,
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vaddr_t addr, size_t size, int op, void *page);
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struct device *dv = disk_lookup(&sd_cd, DISKUNIT(dev));
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struct {
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const char *driver;
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@ -113,6 +116,9 @@ get_hibernate_io_function(dev_t dev)
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#endif
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#if NSDMMC > 0
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{ "sdmmc", sdmmc_scsi_hibernate_io },
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#endif
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#if NUFSHCI > 0
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{ "ufshci", ufshci_hibernate_io },
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#endif
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};
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@ -1,4 +1,4 @@
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# $OpenBSD: Makefile.amd64,v 1.135 2024/06/04 15:14:45 deraadt Exp $
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# $OpenBSD: Makefile.amd64,v 1.136 2024/06/05 20:19:26 deraadt Exp $
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# For instructions on building kernels consult the config(8) and options(4)
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# manual pages.
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@ -73,7 +73,7 @@ CMACHFLAGS+= -mno-retpoline -fcf-protection=none
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.endif
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.else
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CMACHFLAGS+= -mretpoline-external-thunk -fcf-protection=branch
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CMACHFLAGS+= -fret-clean
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#CMACHFLAGS+= -fret-clean
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.endif
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.if ${COMPILER_VERSION:Mclang}
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NO_INTEGR_AS= -no-integrated-as
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@ -1,4 +1,4 @@
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/* $OpenBSD: dwqe.c,v 1.21 2024/05/06 09:54:38 stsp Exp $ */
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/* $OpenBSD: dwqe.c,v 1.22 2024/06/05 10:19:55 stsp Exp $ */
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/*
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* Copyright (c) 2008, 2019 Mark Kettenis <kettenis@openbsd.org>
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* Copyright (c) 2017, 2022 Patrick Wildt <patrick@blueri.se>
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@ -21,6 +21,7 @@
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*/
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#include "bpfilter.h"
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#include "vlan.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -99,6 +100,53 @@ dwqe_have_tx_csum_offload(struct dwqe_softc *sc)
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return (sc->sc_hw_feature[0] & GMAC_MAC_HW_FEATURE0_TXCOESEL);
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}
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int
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dwqe_have_tx_vlan_offload(struct dwqe_softc *sc)
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{
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#if NVLAN > 0
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return (sc->sc_hw_feature[0] & GMAC_MAC_HW_FEATURE0_SAVLANINS);
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#else
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return 0;
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#endif
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}
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void
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dwqe_set_vlan_rx_mode(struct dwqe_softc *sc)
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{
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#if NVLAN > 0
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uint32_t reg;
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/* Enable outer VLAN tag stripping on Rx. */
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reg = dwqe_read(sc, GMAC_VLAN_TAG_CTRL);
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reg |= GMAC_VLAN_TAG_CTRL_EVLRXS | GMAC_VLAN_TAG_CTRL_STRIP_ALWAYS;
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dwqe_write(sc, GMAC_VLAN_TAG_CTRL, reg);
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#endif
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}
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void
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dwqe_set_vlan_tx_mode(struct dwqe_softc *sc)
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{
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#if NVLAN > 0
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uint32_t reg;
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reg = dwqe_read(sc, GMAC_VLAN_TAG_INCL);
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/* Enable insertion of outer VLAN tag. */
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reg |= GMAC_VLAN_TAG_INCL_INSERT;
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/*
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* Generate C-VLAN tags (type 0x8100, 802.1Q). Setting this
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* bit would result in S-VLAN tags (type 0x88A8, 802.1ad).
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*/
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reg &= ~GMAC_VLAN_TAG_INCL_CSVL;
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/* Use VLAN tags provided in Tx context descriptors. */
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reg |= GMAC_VLAN_TAG_INCL_VLTI;
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dwqe_write(sc, GMAC_VLAN_TAG_INCL, reg);
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#endif
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}
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int
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dwqe_attach(struct dwqe_softc *sc)
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{
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@ -127,6 +175,8 @@ dwqe_attach(struct dwqe_softc *sc)
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bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ);
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ifp->if_capabilities = IFCAP_VLAN_MTU;
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if (dwqe_have_tx_vlan_offload(sc))
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ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING;
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if (dwqe_have_tx_csum_offload(sc)) {
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ifp->if_capabilities |= (IFCAP_CSUM_IPv4 |
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IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4 |
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@ -218,6 +268,14 @@ dwqe_attach(struct dwqe_softc *sc)
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if (!sc->sc_fixed_link)
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dwqe_mii_attach(sc);
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/*
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* All devices support VLAN tag stripping on Rx but inserting
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* VLAN tags during Tx is an optional feature.
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*/
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dwqe_set_vlan_rx_mode(sc);
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if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING)
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dwqe_set_vlan_tx_mode(sc);
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if_attach(ifp);
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ether_ifattach(ifp);
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@ -329,7 +387,8 @@ dwqe_start(struct ifqueue *ifq)
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used = 0;
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for (;;) {
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if (used + DWQE_NTXSEGS + 1 > left) {
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/* VLAN tags require an extra Tx context descriptor. */
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if (used + DWQE_NTXSEGS + 2 > left) {
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ifq_set_oactive(ifq);
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break;
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}
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@ -714,6 +773,21 @@ dwqe_rx_csum(struct dwqe_softc *sc, struct mbuf *m, struct dwqe_desc *rxd)
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m->m_pkthdr.csum_flags |= csum_flags;
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}
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void
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dwqe_vlan_strip(struct dwqe_softc *sc, struct mbuf *m, struct dwqe_desc *rxd)
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{
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#if NVLAN > 0
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uint16_t tag;
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if ((rxd->sd_tdes3 & RDES3_RDES0_VALID) &&
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(rxd->sd_tdes3 & RDES3_LD)) {
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tag = rxd->sd_tdes0 & RDES0_OVT;
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m->m_pkthdr.ether_vtag = le16toh(tag);
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m->m_flags |= M_VLANTAG;
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}
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#endif
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}
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void
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dwqe_rx_proc(struct dwqe_softc *sc)
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{
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@ -763,6 +837,7 @@ dwqe_rx_proc(struct dwqe_softc *sc)
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m->m_pkthdr.len = m->m_len = len;
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dwqe_rx_csum(sc, m, rxd);
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dwqe_vlan_strip(sc, m, rxd);
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ml_enqueue(&ml, m);
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}
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@ -1107,12 +1182,34 @@ dwqe_tx_csum(struct dwqe_softc *sc, struct mbuf *m, struct dwqe_desc *txd)
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txd->sd_tdes3 |= TDES3_CSUM_IPHDR_PAYLOAD_PSEUDOHDR;
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}
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uint16_t
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dwqe_set_tx_context_desc(struct dwqe_softc *sc, struct mbuf *m, int idx)
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{
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uint16_t tag = 0;
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#if NVLAN > 0
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struct dwqe_desc *ctxt_txd;
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if ((m->m_flags & M_VLANTAG) == 0)
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return 0;
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tag = m->m_pkthdr.ether_vtag;
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if (tag) {
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ctxt_txd = &sc->sc_txdesc[idx];
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ctxt_txd->sd_tdes3 |= (htole16(tag) & TDES3_VLAN_TAG);
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ctxt_txd->sd_tdes3 |= TDES3_VLAN_TAG_VALID;
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ctxt_txd->sd_tdes3 |= (TDES3_CTXT | TDES3_OWN);
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}
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#endif
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return tag;
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}
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int
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dwqe_encap(struct dwqe_softc *sc, struct mbuf *m, int *idx, int *used)
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{
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struct dwqe_desc *txd, *txd_start;
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bus_dmamap_t map;
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int cur, frag, i;
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uint16_t vlan_tag = 0;
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cur = frag = *idx;
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map = sc->sc_txbuf[cur].tb_map;
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@ -1128,6 +1225,17 @@ dwqe_encap(struct dwqe_softc *sc, struct mbuf *m, int *idx, int *used)
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bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
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BUS_DMASYNC_PREWRITE);
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if (dwqe_have_tx_vlan_offload(sc)) {
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vlan_tag = dwqe_set_tx_context_desc(sc, m, frag);
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if (vlan_tag) {
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(*used)++;
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if (frag == (DWQE_NTXDESC - 1))
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frag = 0;
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else
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frag++;
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}
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}
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txd = txd_start = &sc->sc_txdesc[frag];
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for (i = 0; i < map->dm_nsegs; i++) {
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/* TODO: check for 32-bit vs 64-bit support */
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@ -1140,6 +1248,8 @@ dwqe_encap(struct dwqe_softc *sc, struct mbuf *m, int *idx, int *used)
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if (i == 0) {
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txd->sd_tdes3 |= TDES3_FS;
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dwqe_tx_csum(sc, m, txd);
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if (vlan_tag)
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txd->sd_tdes2 |= TDES2_VLAN_TAG_INSERT;
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}
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if (i == (map->dm_nsegs - 1)) {
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txd->sd_tdes2 |= TDES2_IC;
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@ -1,4 +1,4 @@
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/* $OpenBSD: dwqereg.h,v 1.9 2024/05/06 09:54:38 stsp Exp $ */
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/* $OpenBSD: dwqereg.h,v 1.10 2024/06/05 10:19:55 stsp Exp $ */
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/*
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* Copyright (c) 2008, 2019 Mark Kettenis <kettenis@openbsd.org>
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* Copyright (c) 2017, 2022 Patrick Wildt <patrick@blueri.se>
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@ -44,6 +44,19 @@
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#define GMAC_INT_MASK_LPIIM (1 << 10)
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#define GMAC_INT_MASK_PIM (1 << 3)
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#define GMAC_INT_MASK_RIM (1 << 0)
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#define GMAC_VLAN_TAG_CTRL 0x0050
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#define GMAC_VLAN_TAG_CTRL_EVLRXS (1 << 24)
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#define GMAC_VLAN_TAG_CTRL_STRIP_ALWAYS ((1 << 21) | (1 << 22))
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#define GMAC_VLAN_TAG_DATA 0x0054
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#define GMAC_VLAN_TAG_INCL 0x0060
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#define GMAC_VLAN_TAG_INCL_VLTI (1 << 20)
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#define GMAC_VLAN_TAG_INCL_CSVL (1 << 19)
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#define GMAC_VLAN_TAG_INCL_DELETE 0x10000
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#define GMAC_VLAN_TAG_INCL_INSERT 0x20000
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#define GMAC_VLAN_TAG_INCL_REPLACE 0x30000
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#define GMAC_VLAN_TAG_INCL_VLT 0x0ffff
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#define GMAC_VLAN_TAG_INCL_RDWR (1U << 30)
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#define GMAC_VLAN_TAG_INCL_BUSY (1U << 31)
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#define GMAC_QX_TX_FLOW_CTRL(x) (0x0070 + (x) * 4)
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#define GMAC_QX_TX_FLOW_CTRL_PT_SHIFT 16
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#define GMAC_QX_TX_FLOW_CTRL_TFE (1 << 0)
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@ -64,6 +77,7 @@
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#define GMAC_MAC_HW_FEATURE(x) (0x011c + (x) * 0x4)
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#define GMAC_MAC_HW_FEATURE0_TXCOESEL (1 << 14)
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#define GMAC_MAC_HW_FEATURE0_RXCOESEL (1 << 16)
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#define GMAC_MAC_HW_FEATURE0_SAVLANINS (1 << 27)
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#define GMAC_MAC_HW_FEATURE1_TXFIFOSIZE(x) (((x) >> 6) & 0x1f)
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#define GMAC_MAC_HW_FEATURE1_RXFIFOSIZE(x) (((x) >> 0) & 0x1f)
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#define GMAC_MAC_MDIO_ADDR 0x0200
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@ -230,6 +244,12 @@ struct dwqe_desc {
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uint32_t sd_tdes3;
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};
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/* Tx context descriptor bits (host to device); precedes regular descriptor */
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#define TDES3_CTXT (1 << 30)
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#define TDES3_VLAN_TAG_VALID (1 << 16)
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#define TDES3_VLAN_TAG 0xffff
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/* Bit 31 is the OWN bit, as in regular Tx descriptor. */
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/* Tx bits (read format; host to device) */
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#define TDES2_HDR_LEN 0x000003ff /* if TSO is enabled */
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#define TDES2_BUF1_LEN 0x00003fff /* if TSO is disabled */
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@ -250,6 +270,11 @@ struct dwqe_desc {
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#define TDES3_CSUM_IPHDR_PAYLOAD (0x2 << 16)
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#define TDES3_CSUM_IPHDR_PAYLOAD_PSEUDOHDR (0x3 << 16)
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#define TDES3_TSO_EN (1 << 18)
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#define TDES3_CPC ((1 << 26) | (1 << 27)) /* if TSO is disabled */
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#define TDES3_CPC_CRC_AND_PAD (0x0 << 26)
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#define TDES3_CPC_CRC_NO_PAD (0x1 << 26)
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#define TDES3_CPC_DISABLE (0x2 << 26)
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#define TDES3_CPC_CRC_REPLACE (0x3 << 26)
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#define TDES3_LS (1 << 28)
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#define TDES3_FS (1 << 29)
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#define TDES3_OWN (1U << 31)
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@ -268,6 +293,8 @@ struct dwqe_desc {
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#define RDES3_OWN (1U << 31)
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/* Rx bits (writeback format; device to host) */
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#define RDES0_IVT 0xffff0000
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#define RDES0_OVT 0x0000ffff
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#define RDES1_IP_PAYLOAD_TYPE 0x7
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#define RDES1_IP_PAYLOAD_UNKNOWN 0x0
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#define RDES1_IP_PAYLOAD_UDP 0x1
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@ -1,4 +1,4 @@
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/* $OpenBSD: ufshci.c,v 1.33 2024/05/27 10:27:58 mglocker Exp $ */
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/* $OpenBSD: ufshci.c,v 1.34 2024/06/05 04:58:05 mglocker Exp $ */
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/*
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* Copyright (c) 2022 Marcus Glocker <mglocker@openbsd.org>
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@ -42,6 +42,13 @@
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#include <dev/ic/ufshcivar.h>
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#include <dev/ic/ufshcireg.h>
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#ifdef HIBERNATE
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#include <uvm/uvm_extern.h>
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#include <sys/hibernate.h>
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#include <sys/disklabel.h>
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#include <sys/disk.h>
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#endif
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#ifdef UFSHCI_DEBUG
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int ufshci_dbglvl = 1;
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#define DPRINTF(l, x...) do { if ((l) <= ufshci_dbglvl) printf(x); } \
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@ -59,7 +66,9 @@ int ufshci_is_poll(struct ufshci_softc *, uint32_t);
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struct ufshci_dmamem *ufshci_dmamem_alloc(struct ufshci_softc *, size_t);
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void ufshci_dmamem_free(struct ufshci_softc *,
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struct ufshci_dmamem *);
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int ufshci_alloc(struct ufshci_softc *);
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int ufshci_init(struct ufshci_softc *);
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int ufshci_disable(struct ufshci_softc *);
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int ufshci_doorbell_read(struct ufshci_softc *);
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void ufshci_doorbell_write(struct ufshci_softc *, int);
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int ufshci_doorbell_poll(struct ufshci_softc *, int,
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@ -104,6 +113,11 @@ void ufshci_scsi_io_done(struct ufshci_softc *,
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void ufshci_scsi_done(struct ufshci_softc *,
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struct ufshci_ccb *);
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#if HIBERNATE
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int ufshci_hibernate_io(dev_t, daddr_t, vaddr_t, size_t,
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int, void *);
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#endif
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const struct scsi_adapter ufshci_switch = {
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ufshci_scsi_cmd, NULL, NULL, NULL, NULL
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};
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@ -227,6 +241,8 @@ ufshci_attach(struct ufshci_softc *sc)
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#if 0
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sc->sc_flags |= UFSHCI_FLAGS_AGGR_INTR; /* Enable intr. aggregation */
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#endif
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/* Allocate the DMA buffers and initialize the controller. */
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ufshci_alloc(sc);
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ufshci_init(sc);
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if (ufshci_ccb_alloc(sc, sc->sc_nutrs) != 0) {
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@ -371,6 +387,39 @@ ufshci_dmamem_free(struct ufshci_softc *sc, struct ufshci_dmamem *udm)
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free(udm, M_DEVBUF, sizeof(*udm));
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}
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int
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ufshci_alloc(struct ufshci_softc *sc)
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{
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/* 7.1.1 Host Controller Initialization: 13) */
|
||||
sc->sc_dmamem_utmrd = ufshci_dmamem_alloc(sc,
|
||||
sizeof(struct ufshci_utmrd) * sc->sc_nutmrs);
|
||||
if (sc->sc_dmamem_utmrd == NULL) {
|
||||
printf("%s: Can't allocate DMA memory for UTMRD\n",
|
||||
sc->sc_dev.dv_xname);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* 7.1.1 Host Controller Initialization: 15) */
|
||||
sc->sc_dmamem_utrd = ufshci_dmamem_alloc(sc,
|
||||
sizeof(struct ufshci_utrd) * sc->sc_nutrs);
|
||||
if (sc->sc_dmamem_utrd == NULL) {
|
||||
printf("%s: Can't allocate DMA memory for UTRD\n",
|
||||
sc->sc_dev.dv_xname);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Allocate UCDs. */
|
||||
sc->sc_dmamem_ucd = ufshci_dmamem_alloc(sc,
|
||||
sizeof(struct ufshci_ucd) * sc->sc_nutrs);
|
||||
if (sc->sc_dmamem_ucd == NULL) {
|
||||
printf("%s: Can't allocate DMA memory for UCD\n",
|
||||
sc->sc_dev.dv_xname);
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
ufshci_init(struct ufshci_softc *sc)
|
||||
{
|
||||
|
|
@ -430,44 +479,18 @@ ufshci_init(struct ufshci_softc *sc)
|
|||
* TODO: More UIC commands to issue?
|
||||
*/
|
||||
|
||||
/* 7.1.1 Host Controller Initialization: 13) */
|
||||
sc->sc_dmamem_utmrd = ufshci_dmamem_alloc(sc,
|
||||
sizeof(struct ufshci_utmrd) * sc->sc_nutmrs);
|
||||
if (sc->sc_dmamem_utmrd == NULL) {
|
||||
printf("%s: Can't allocate DMA memory for UTMRD\n",
|
||||
sc->sc_dev.dv_xname);
|
||||
return -1;
|
||||
}
|
||||
/* 7.1.1 Host Controller Initialization: 14) */
|
||||
dva = UFSHCI_DMA_DVA(sc->sc_dmamem_utmrd);
|
||||
DPRINTF(2, "%s: utmrd dva=%llu\n", __func__, dva);
|
||||
UFSHCI_WRITE_4(sc, UFSHCI_REG_UTMRLBA, (uint32_t)dva);
|
||||
UFSHCI_WRITE_4(sc, UFSHCI_REG_UTMRLBAU, (uint32_t)(dva >> 32));
|
||||
|
||||
/* 7.1.1 Host Controller Initialization: 15) */
|
||||
sc->sc_dmamem_utrd = ufshci_dmamem_alloc(sc,
|
||||
sizeof(struct ufshci_utrd) * sc->sc_nutrs);
|
||||
if (sc->sc_dmamem_utrd == NULL) {
|
||||
printf("%s: Can't allocate DMA memory for UTRD\n",
|
||||
sc->sc_dev.dv_xname);
|
||||
return -1;
|
||||
}
|
||||
/* 7.1.1 Host Controller Initialization: 16) */
|
||||
dva = UFSHCI_DMA_DVA(sc->sc_dmamem_utrd);
|
||||
DPRINTF(2, "%s: utrd dva=%llu\n", __func__, dva);
|
||||
UFSHCI_WRITE_4(sc, UFSHCI_REG_UTRLBA, (uint32_t)dva);
|
||||
UFSHCI_WRITE_4(sc, UFSHCI_REG_UTRLBAU, (uint32_t)(dva >> 32));
|
||||
|
||||
|
||||
/* Allocate UCDs. */
|
||||
sc->sc_dmamem_ucd = ufshci_dmamem_alloc(sc,
|
||||
sizeof(struct ufshci_ucd) * sc->sc_nutrs);
|
||||
if (sc->sc_dmamem_ucd == NULL) {
|
||||
printf("%s: Can't allocate DMA memory for UCD\n",
|
||||
sc->sc_dev.dv_xname);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* 7.1.1 Host Controller Initialization: 17) */
|
||||
UFSHCI_WRITE_4(sc, UFSHCI_REG_UTMRLRSR, UFSHCI_REG_UTMRLRSR_START);
|
||||
|
||||
|
|
@ -482,6 +505,19 @@ ufshci_init(struct ufshci_softc *sc)
|
|||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
ufshci_disable(struct ufshci_softc *sc)
|
||||
{
|
||||
/* Stop run queues. */
|
||||
UFSHCI_WRITE_4(sc, UFSHCI_REG_UTMRLRSR, UFSHCI_REG_UTMRLRSR_STOP);
|
||||
UFSHCI_WRITE_4(sc, UFSHCI_REG_UTRLRSR, UFSHCI_REG_UTRLRSR_STOP);
|
||||
|
||||
/* Disable interrupts. */
|
||||
UFSHCI_WRITE_4(sc, UFSHCI_REG_IE, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
ufshci_doorbell_read(struct ufshci_softc *sc)
|
||||
{
|
||||
|
|
@ -1353,11 +1389,11 @@ ufshci_activate(struct ufshci_softc *sc, int act)
|
|||
case DVACT_POWERDOWN:
|
||||
DPRINTF(1, "%s: POWERDOWN\n", __func__);
|
||||
rv = config_activate_children(&sc->sc_dev, act);
|
||||
ufshci_powerdown(sc);
|
||||
ufshci_disable(sc);
|
||||
break;
|
||||
case DVACT_RESUME:
|
||||
DPRINTF(1, "%s: RESUME\n", __func__);
|
||||
ufshci_resume(sc);
|
||||
rv = ufshci_init(sc);
|
||||
if (rv == 0)
|
||||
rv = config_activate_children(&sc->sc_dev, act);
|
||||
break;
|
||||
|
|
@ -1369,56 +1405,6 @@ ufshci_activate(struct ufshci_softc *sc, int act)
|
|||
return rv;
|
||||
}
|
||||
|
||||
int
|
||||
ufshci_powerdown(struct ufshci_softc *sc)
|
||||
{
|
||||
uint32_t reg;
|
||||
|
||||
/* Send "hibernate enter" command. */
|
||||
UFSHCI_WRITE_4(sc, UFSHCI_REG_UICCMD,
|
||||
UFSHCI_REG_UICCMD_CMDOP_DME_HIBERNATE_ENTER);
|
||||
if (ufshci_is_poll(sc, UFSHCI_REG_IS_UHES) != 0) {
|
||||
printf("%s: hibernate enter cmd failed\n", __func__);
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Check if "hibernate enter" command was executed successfully. */
|
||||
reg = UFSHCI_READ_4(sc, UFSHCI_REG_HCS);
|
||||
DPRINTF(1, "%s: UPMCRS=0x%x\n", __func__, UFSHCI_REG_HCS_UPMCRS(reg));
|
||||
if (UFSHCI_REG_HCS_UPMCRS(reg) > UFSHCI_REG_HCS_UPMCRS_PWR_REMTOTE) {
|
||||
printf("%s: hibernate enter cmd returned UPMCRS error=0x%x\n",
|
||||
__func__, UFSHCI_REG_HCS_UPMCRS(reg));
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
ufshci_resume(struct ufshci_softc *sc)
|
||||
{
|
||||
uint32_t reg;
|
||||
|
||||
/* Send "hibernate exit" command. */
|
||||
UFSHCI_WRITE_4(sc, UFSHCI_REG_UICCMD,
|
||||
UFSHCI_REG_UICCMD_CMDOP_DME_HIBERNATE_EXIT);
|
||||
if (ufshci_is_poll(sc, UFSHCI_REG_IS_UHXS) != 0) {
|
||||
printf("%s: hibernate exit command failed\n", __func__);
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Check if "hibernate exit" command was executed successfully. */
|
||||
reg = UFSHCI_READ_4(sc, UFSHCI_REG_HCS);
|
||||
DPRINTF(1, "%s: UPMCRS=0x%x\n", __func__, UFSHCI_REG_HCS_UPMCRS(reg));
|
||||
if (UFSHCI_REG_HCS_UPMCRS(reg) > UFSHCI_REG_HCS_UPMCRS_PWR_REMTOTE) {
|
||||
printf("%s: hibernate exit cmd returned UPMCRS error=0x%x\n",
|
||||
__func__, UFSHCI_REG_HCS_UPMCRS(reg));
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* SCSI */
|
||||
|
||||
int
|
||||
|
|
@ -1928,3 +1914,155 @@ ufshci_scsi_done(struct ufshci_softc *sc, struct ufshci_ccb *ccb)
|
|||
xs->resid = 0;
|
||||
scsi_done(xs);
|
||||
}
|
||||
|
||||
#if HIBERNATE
|
||||
int
|
||||
ufshci_hibernate_io(dev_t dev, daddr_t blkno, vaddr_t addr, size_t size,
|
||||
int op, void *page)
|
||||
{
|
||||
struct ufshci_hibernate_page {
|
||||
struct ufshci_utrd utrd;
|
||||
struct ufshci_ucd ucd;
|
||||
|
||||
struct ufshci_softc *sc; /* Copy of softc */
|
||||
|
||||
daddr_t poffset; /* Start of SWAP partition */
|
||||
size_t psize; /* Size of SWAP partition */
|
||||
uint32_t secsize; /* Our sector size */
|
||||
} *my = page;
|
||||
paddr_t data_phys, page_phys;
|
||||
uint64_t data_bus_phys, page_bus_phys;
|
||||
uint64_t timeout_us;
|
||||
int off, len, slot;
|
||||
uint32_t blocks, reg;
|
||||
uint64_t lba;
|
||||
|
||||
if (op == HIB_INIT) {
|
||||
struct device *disk;
|
||||
struct device *scsibus;
|
||||
extern struct cfdriver sd_cd;
|
||||
|
||||
/* Find ufshci softc. */
|
||||
disk = disk_lookup(&sd_cd, DISKUNIT(dev));
|
||||
if (disk == NULL)
|
||||
return ENOTTY;
|
||||
scsibus = disk->dv_parent;
|
||||
my->sc = (struct ufshci_softc *)disk->dv_parent->dv_parent;
|
||||
|
||||
/* Stop run queues and disable interrupts. */
|
||||
ufshci_disable(my->sc);
|
||||
|
||||
/* Tell the controler the new hibernate UTRD address. */
|
||||
pmap_extract(pmap_kernel(), (vaddr_t)page, &page_phys);
|
||||
page_bus_phys = page_phys + ((void *)&my->utrd - page);
|
||||
UFSHCI_WRITE_4(my->sc, UFSHCI_REG_UTRLBA,
|
||||
(uint32_t)page_bus_phys);
|
||||
UFSHCI_WRITE_4(my->sc, UFSHCI_REG_UTRLBAU,
|
||||
(uint32_t)(page_bus_phys >> 32));
|
||||
|
||||
/* Start run queues. */
|
||||
UFSHCI_WRITE_4(my->sc, UFSHCI_REG_UTMRLRSR,
|
||||
UFSHCI_REG_UTMRLRSR_START);
|
||||
UFSHCI_WRITE_4(my->sc, UFSHCI_REG_UTRLRSR,
|
||||
UFSHCI_REG_UTRLRSR_START);
|
||||
|
||||
my->poffset = blkno;
|
||||
my->psize = size;
|
||||
my->secsize = UFSHCI_LBS;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (op != HIB_W)
|
||||
return 0;
|
||||
|
||||
if (blkno + (size / DEV_BSIZE) > my->psize)
|
||||
return E2BIG;
|
||||
blocks = size / my->secsize;
|
||||
lba = (blkno + my->poffset) / (my->secsize / DEV_BSIZE);
|
||||
|
||||
/*
|
||||
* The following code is a ripped down version of ufshci_utr_cmd_io()
|
||||
* adapted for hibernate.
|
||||
*/
|
||||
slot = 0; /* We only use the first slot for hibernate */
|
||||
|
||||
memset(&my->utrd, 0, sizeof(struct ufshci_utrd));
|
||||
|
||||
my->utrd.dw0 = UFSHCI_UTRD_DW0_CT_UFS;
|
||||
my->utrd.dw0 |= UFSHCI_UTRD_DW0_DD_I2T;
|
||||
my->utrd.dw0 |= UFSHCI_UTRD_DW0_I_REG;
|
||||
my->utrd.dw2 = UFSHCI_UTRD_DW2_OCS_IOV;
|
||||
|
||||
memset(&my->ucd, 0, sizeof(struct ufshci_ucd));
|
||||
|
||||
my->ucd.cmd.hdr.tc = UPIU_TC_I2T_COMMAND;
|
||||
my->ucd.cmd.hdr.flags = (1 << 5); /* Bit-5 = Write */
|
||||
|
||||
my->ucd.cmd.hdr.lun = 0;
|
||||
my->ucd.cmd.hdr.task_tag = slot;
|
||||
my->ucd.cmd.hdr.cmd_set_type = 0; /* SCSI command */
|
||||
my->ucd.cmd.hdr.query = 0;
|
||||
my->ucd.cmd.hdr.response = 0;
|
||||
my->ucd.cmd.hdr.status = 0;
|
||||
my->ucd.cmd.hdr.ehs_len = 0;
|
||||
my->ucd.cmd.hdr.device_info = 0;
|
||||
my->ucd.cmd.hdr.ds_len = 0;
|
||||
|
||||
my->ucd.cmd.expected_xfer_len = htobe32(UFSHCI_LBS * blocks);
|
||||
my->ucd.cmd.cdb[0] = WRITE_10; /* 0x2a */
|
||||
my->ucd.cmd.cdb[1] = (1 << 3); /* FUA: Force Unit Access */
|
||||
my->ucd.cmd.cdb[2] = (lba >> 24) & 0xff;
|
||||
my->ucd.cmd.cdb[3] = (lba >> 16) & 0xff;
|
||||
my->ucd.cmd.cdb[4] = (lba >> 8) & 0xff;
|
||||
my->ucd.cmd.cdb[5] = (lba >> 0) & 0xff;
|
||||
my->ucd.cmd.cdb[7] = (blocks >> 8) & 0xff;
|
||||
my->ucd.cmd.cdb[8] = (blocks >> 0) & 0xff;
|
||||
|
||||
pmap_extract(pmap_kernel(), (vaddr_t)page, &page_phys);
|
||||
page_bus_phys = page_phys + ((void *)&my->ucd - page);
|
||||
my->utrd.dw4 = (uint32_t)page_bus_phys;
|
||||
my->utrd.dw5 = (uint32_t)(page_bus_phys >> 32);
|
||||
|
||||
off = sizeof(struct upiu_command) / 4; /* DWORD offset */
|
||||
my->utrd.dw6 = UFSHCI_UTRD_DW6_RUO(off);
|
||||
|
||||
len = sizeof(struct upiu_response) / 4; /* DWORD length */
|
||||
my->utrd.dw6 |= UFSHCI_UTRD_DW6_RUL(len);
|
||||
|
||||
off = (sizeof(struct upiu_command) + sizeof(struct upiu_response)) / 4;
|
||||
my->utrd.dw7 = UFSHCI_UTRD_DW7_PRDTO(off);
|
||||
|
||||
my->utrd.dw7 |= UFSHCI_UTRD_DW7_PRDTL(1); /* dm_nsegs */
|
||||
|
||||
pmap_extract(pmap_kernel(), (vaddr_t)addr, &data_phys);
|
||||
data_bus_phys = data_phys;
|
||||
my->ucd.prdt[0].dw0 = (uint32_t)data_bus_phys;
|
||||
my->ucd.prdt[0].dw1 = (uint32_t)(data_bus_phys >> 32);
|
||||
my->ucd.prdt[0].dw2 = 0;
|
||||
my->ucd.prdt[0].dw3 = size - 1; /* ds_len */
|
||||
|
||||
if (UFSHCI_READ_4(my->sc, UFSHCI_REG_UTRLRSR) != 1)
|
||||
return EIO;
|
||||
|
||||
ufshci_doorbell_write(my->sc, slot);
|
||||
|
||||
/* ufshci_doorbell_poll() adaption for hibernate. */
|
||||
for (timeout_us = 1000000 * 1000; timeout_us != 0;
|
||||
timeout_us -= 1000) {
|
||||
reg = UFSHCI_READ_4(my->sc, UFSHCI_REG_UTRLDBR);
|
||||
if ((reg & (1U << slot)) == 0)
|
||||
break;
|
||||
delay(1000);
|
||||
}
|
||||
if (timeout_us == 0)
|
||||
return EIO;
|
||||
UFSHCI_WRITE_4(my->sc, UFSHCI_REG_UTRLCNR, (1U << slot));
|
||||
|
||||
/* Check if the command was succesfully executed. */
|
||||
if (my->utrd.dw2 != UFSHCI_UTRD_DW2_OCS_SUCCESS)
|
||||
return EIO;
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* HIBERNATE */
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $OpenBSD: subr_hibernate.c,v 1.140 2024/06/04 20:31:35 krw Exp $ */
|
||||
/* $OpenBSD: subr_hibernate.c,v 1.141 2024/06/05 11:04:17 krw Exp $ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2011 Ariane van der Steldt <ariane@stack.nl>
|
||||
|
|
@ -72,6 +72,7 @@ vaddr_t hibernate_rle_page;
|
|||
|
||||
/* Hibernate info as read from disk during resume */
|
||||
union hibernate_info disk_hib;
|
||||
struct bdevsw *bdsw;
|
||||
|
||||
/*
|
||||
* Global copy of the pig start address. This needs to be a global as we
|
||||
|
|
@ -1004,18 +1005,9 @@ hibernate_block_io(union hibernate_info *hib, daddr_t blkctr,
|
|||
size_t xfer_size, vaddr_t dest, int iswrite)
|
||||
{
|
||||
struct buf *bp;
|
||||
struct bdevsw *bdsw;
|
||||
int error;
|
||||
|
||||
bp = geteblk(xfer_size);
|
||||
bdsw = &bdevsw[major(hib->dev)];
|
||||
|
||||
error = (*bdsw->d_open)(hib->dev, FREAD, S_IFCHR, curproc);
|
||||
if (error) {
|
||||
printf("hibernate_block_io open failed\n");
|
||||
return (1);
|
||||
}
|
||||
|
||||
if (iswrite)
|
||||
bcopy((caddr_t)dest, bp->b_data, xfer_size);
|
||||
|
||||
|
|
@ -1030,26 +1022,13 @@ hibernate_block_io(union hibernate_info *hib, daddr_t blkctr,
|
|||
if (error) {
|
||||
printf("hib block_io biowait error %d blk %lld size %zu\n",
|
||||
error, (long long)blkctr, xfer_size);
|
||||
error = (*bdsw->d_close)(hib->dev, 0, S_IFCHR,
|
||||
curproc);
|
||||
if (error)
|
||||
printf("hibernate_block_io error close failed\n");
|
||||
return (1);
|
||||
}
|
||||
|
||||
error = (*bdsw->d_close)(hib->dev, FREAD, S_IFCHR, curproc);
|
||||
if (error) {
|
||||
printf("hibernate_block_io close failed\n");
|
||||
return (1);
|
||||
}
|
||||
|
||||
if (!iswrite)
|
||||
} else if (!iswrite)
|
||||
bcopy(bp->b_data, (caddr_t)dest, xfer_size);
|
||||
|
||||
bp->b_flags |= B_INVAL;
|
||||
brelse(bp);
|
||||
|
||||
return (0);
|
||||
return (error != 0);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -1140,6 +1119,13 @@ hibernate_resume(void)
|
|||
/* Read hibernate info from disk */
|
||||
s = splbio();
|
||||
|
||||
bdsw = &bdevsw[major(hib->dev)];
|
||||
if ((*bdsw->d_open)(hib->dev, FREAD, S_IFCHR, curproc)) {
|
||||
printf("hibernate_resume device open failed\n");
|
||||
splx(s);
|
||||
return;
|
||||
}
|
||||
|
||||
DPRINTF("reading hibernate signature block location: %lld\n",
|
||||
hib->sig_offset);
|
||||
|
||||
|
|
@ -1147,16 +1133,14 @@ hibernate_resume(void)
|
|||
hib->sig_offset,
|
||||
hib->sec_size, (vaddr_t)&disk_hib, 0)) {
|
||||
DPRINTF("error in hibernate read\n");
|
||||
splx(s);
|
||||
return;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
/* Check magic number */
|
||||
if (disk_hib.magic != HIBERNATE_MAGIC) {
|
||||
DPRINTF("wrong magic number in hibernate signature: %x\n",
|
||||
disk_hib.magic);
|
||||
splx(s);
|
||||
return;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -1165,8 +1149,7 @@ hibernate_resume(void)
|
|||
*/
|
||||
if (hibernate_clear_signature(hib)) {
|
||||
DPRINTF("error clearing hibernate signature block\n");
|
||||
splx(s);
|
||||
return;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -1175,8 +1158,7 @@ hibernate_resume(void)
|
|||
*/
|
||||
if (hibernate_compare_signature(hib, &disk_hib)) {
|
||||
DPRINTF("mismatched hibernate signature block\n");
|
||||
splx(s);
|
||||
return;
|
||||
goto fail;
|
||||
}
|
||||
disk_hib.dev = hib->dev;
|
||||
|
||||
|
|
@ -1189,6 +1171,9 @@ hibernate_resume(void)
|
|||
/* Read the image from disk into the image (pig) area */
|
||||
if (hibernate_read_image(&disk_hib))
|
||||
goto fail;
|
||||
if ((*bdsw->d_close)(hib->dev, 0, S_IFCHR, curproc))
|
||||
printf("hibernate_resume device close failed\n");
|
||||
bdsw = NULL;
|
||||
|
||||
DPRINTF("hibernate: quiescing devices\n");
|
||||
if (config_suspend_all(DVACT_QUIESCE) != 0)
|
||||
|
|
@ -1235,8 +1220,11 @@ hibernate_resume(void)
|
|||
hibernate_unpack_image(&disk_hib);
|
||||
|
||||
fail:
|
||||
if (!bdsw)
|
||||
printf("\nUnable to resume hibernated image\n");
|
||||
else if ((*bdsw->d_close)(hib->dev, 0, S_IFCHR, curproc))
|
||||
printf("hibernate_resume device close failed\n");
|
||||
splx(s);
|
||||
printf("\nUnable to resume hibernated image\n");
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue