sync code with last fixes and improvements from OpenBSD
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parent
58b04bcee7
commit
58df21ce75
GPG key ID:
F42C07F07E2E35B7
33 changed files with 383 additions and 312 deletions
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@ -1,4 +1,4 @@
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/* $OpenBSD: cpu.c,v 1.170 2023/07/10 03:32:10 guenther Exp $ */
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/* $OpenBSD: cpu.c,v 1.171 2023/07/21 04:04:51 guenther Exp $ */
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/* $NetBSD: cpu.c,v 1.1 2003/04/26 18:39:26 fvdl Exp $ */
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/*-
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@ -273,7 +273,7 @@ replacemds(void)
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if (strcmp(cpu_vendor, "GenuineIntel") != 0 ||
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((ci->ci_feature_sefflags_edx & SEFF0EDX_ARCH_CAP) &&
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(rdmsr(MSR_ARCH_CAPABILITIES) & ARCH_CAPABILITIES_MDS_NO))) {
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(rdmsr(MSR_ARCH_CAPABILITIES) & ARCH_CAP_MDS_NO))) {
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/* Unaffected, nop out the handling code */
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has_verw = 0;
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} else if (ci->ci_feature_sefflags_edx & SEFF0EDX_MD_CLEAR) {
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@ -1242,7 +1242,7 @@ cpu_tsx_disable(struct cpu_info *ci)
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if (strcmp(cpu_vendor, "GenuineIntel") == 0 &&
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(sefflags_edx & SEFF0EDX_ARCH_CAP)) {
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msr = rdmsr(MSR_ARCH_CAPABILITIES);
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if (msr & ARCH_CAPABILITIES_TSX_CTRL) {
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if (msr & ARCH_CAP_TSX_CTRL) {
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msr = rdmsr(MSR_TSX_CTRL);
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msr |= TSX_CTRL_RTM_DISABLE | TSX_CTRL_TSX_CPUID_CLEAR;
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wrmsr(MSR_TSX_CTRL, msr);
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@ -1,4 +1,4 @@
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/* $OpenBSD: identcpu.c,v 1.133 2023/04/22 18:27:28 guenther Exp $ */
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/* $OpenBSD: identcpu.c,v 1.134 2023/07/21 04:04:51 guenther Exp $ */
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/* $NetBSD: identcpu.c,v 1.1 2003/04/26 18:39:28 fvdl Exp $ */
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/*
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@ -1049,8 +1049,8 @@ cpu_check_vmm_cap(struct cpu_info *ci)
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*/
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if (ci->ci_feature_sefflags_edx & SEFF0EDX_ARCH_CAP) {
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msr = rdmsr(MSR_ARCH_CAPABILITIES);
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if ((msr & ARCH_CAPABILITIES_RDCL_NO) ||
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((msr & ARCH_CAPABILITIES_SKIP_L1DFL_VMENTRY) &&
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if ((msr & ARCH_CAP_RDCL_NO) ||
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((msr & ARCH_CAP_SKIP_L1DFL_VMENTRY) &&
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ci->ci_vmm_cap.vcc_vmx.vmx_has_l1_flush_msr))
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ci->ci_vmm_cap.vcc_vmx.vmx_has_l1_flush_msr =
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VMX_SKIP_L1D_FLUSH;
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@ -1,4 +1,4 @@
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/* $OpenBSD: locore0.S,v 1.21 2022/12/01 00:26:15 guenther Exp $ */
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/* $OpenBSD: locore0.S,v 1.22 2023/07/21 04:04:51 guenther Exp $ */
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/* $NetBSD: locore.S,v 1.13 2004/03/25 18:33:17 drochner Exp $ */
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/*
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@ -235,7 +235,7 @@ bi_size_ok:
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/* IA32_ARCH_CAPABILITIES MSR available, use it to check CPU security */
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movl $MSR_ARCH_CAPABILITIES, %ecx
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rdmsr
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testl $ARCH_CAPABILITIES_RDCL_NO, %eax
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testl $ARCH_CAP_RDCL_NO, %eax
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jz .Lcpu_check_finished
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.Lcpu_secure:
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@ -1,4 +1,4 @@
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/* $OpenBSD: specialreg.h,v 1.103 2023/07/10 03:32:10 guenther Exp $ */
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/* $OpenBSD: specialreg.h,v 1.104 2023/07/21 04:04:51 guenther Exp $ */
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/* $NetBSD: specialreg.h,v 1.1 2003/04/26 18:39:48 fvdl Exp $ */
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/* $NetBSD: x86/specialreg.h,v 1.2 2003/04/25 21:54:30 fvdl Exp $ */
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@ -400,15 +400,29 @@
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#define MTRRcap_WC 0x400 /* bit 10 - WC type supported */
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#define MTRRcap_SMRR 0x800 /* bit 11 - SMM range reg supported */
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#define MSR_ARCH_CAPABILITIES 0x10a
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#define ARCH_CAPABILITIES_RDCL_NO (1 << 0) /* Meltdown safe */
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#define ARCH_CAPABILITIES_IBRS_ALL (1 << 1) /* enhanced IBRS */
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#define ARCH_CAPABILITIES_RSBA (1 << 2) /* RSB Alternate */
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#define ARCH_CAPABILITIES_SKIP_L1DFL_VMENTRY (1 << 3)
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#define ARCH_CAPABILITIES_SSB_NO (1 << 4) /* Spec St Byp safe */
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#define ARCH_CAPABILITIES_MDS_NO (1 << 5) /* microarch data-sampling */
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#define ARCH_CAPABILITIES_IF_PSCHANGE_MC_NO (1 << 6) /* PS MCE safe */
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#define ARCH_CAPABILITIES_TSX_CTRL (1 << 7) /* has TSX_CTRL MSR */
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#define ARCH_CAPABILITIES_TAA_NO (1 << 8) /* TSX AA safe */
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#define ARCH_CAP_RDCL_NO (1 << 0) /* Meltdown safe */
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#define ARCH_CAP_IBRS_ALL (1 << 1) /* enhanced IBRS */
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#define ARCH_CAP_RSBA (1 << 2) /* RSB Alternate */
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#define ARCH_CAP_SKIP_L1DFL_VMENTRY (1 << 3)
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#define ARCH_CAP_SSB_NO (1 << 4) /* Spec St Byp safe */
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#define ARCH_CAP_MDS_NO (1 << 5) /* microarch data-sampling */
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#define ARCH_CAP_IF_PSCHANGE_MC_NO (1 << 6) /* PS MCE safe */
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#define ARCH_CAP_TSX_CTRL (1 << 7) /* has TSX_CTRL MSR */
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#define ARCH_CAP_TAA_NO (1 << 8) /* TSX AA safe */
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#define ARCH_CAP_MCU_CONTROL (1 << 9) /* has MCU_CTRL MSR */
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#define ARCH_CAP_MISC_PACKAGE_CTLS (1 << 10) /* has MISC_PKG_CTLS MSR */
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#define ARCH_CAP_ENERGY_FILTERING_CTL (1 << 11) /* r/w energy fltring bit */
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#define ARCH_CAP_DOITM (1 << 12) /* Data oprnd indpdnt tmng */
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#define ARCH_CAP_SBDR_SSDP_NO (1 << 13) /* SBDR/SSDP safe */
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#define ARCH_CAP_FBSDP_NO (1 << 14) /* FBSDP safe */
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#define ARCH_CAP_PSDP_NO (1 << 15) /* PSDP safe */
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#define ARCH_CAP_FB_CLEAR (1 << 17) /* MD_CLEAR covers FB */
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#define ARCH_CAP_FB_CLEAR_CTRL (1 << 18)
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#define ARCH_CAP_RRSBA (1 << 19) /* has RRSBA if not dis */
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#define ARCH_CAP_BHI_NO (1 << 20) /* BHI safe */
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#define ARCH_CAP_XAPIC_DISABLE_STATUS (1 << 21) /* can disable xAPIC */
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#define ARCH_CAP_OVERCLOCKING_STATUS (1 << 23) /* has OVRCLCKNG_STAT MSR */
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#define ARCH_CAP_PBRSB_NO (1 << 24) /* PBSR safe */
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#define MSR_FLUSH_CMD 0x10b
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#define FLUSH_CMD_L1D_FLUSH 0x1 /* (1ULL << 0) */
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#define MSR_BBL_CR_ADDR 0x116 /* PII+ only */
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@ -1,4 +1,4 @@
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/* $OpenBSD: cpu.c,v 1.112 2023/06/15 22:18:07 cheloha Exp $ */
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/* $OpenBSD: cpu.c,v 1.113 2023/07/21 04:04:52 guenther Exp $ */
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/* $NetBSD: cpu.c,v 1.1.2.7 2000/06/26 02:04:05 sommerfeld Exp $ */
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/*-
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@ -478,7 +478,7 @@ cpu_tsx_disable(struct cpu_info *ci)
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if (strcmp(cpu_vendor, "GenuineIntel") == 0 &&
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(sefflags_edx & SEFF0EDX_ARCH_CAP)) {
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msr = rdmsr(MSR_ARCH_CAPABILITIES);
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if (msr & ARCH_CAPABILITIES_TSX_CTRL) {
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if (msr & ARCH_CAP_TSX_CTRL) {
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msr = rdmsr(MSR_TSX_CTRL);
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msr |= TSX_CTRL_RTM_DISABLE | TSX_CTRL_TSX_CPUID_CLEAR;
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wrmsr(MSR_TSX_CTRL, msr);
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@ -1,4 +1,4 @@
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/* $OpenBSD: locore0.S,v 1.10 2022/12/08 01:25:44 guenther Exp $ */
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/* $OpenBSD: locore0.S,v 1.11 2023/07/21 04:04:52 guenther Exp $ */
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/* $NetBSD: locore.s,v 1.145 1996/05/03 19:41:19 christos Exp $ */
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/*-
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/* IA32_ARCH_CAPABILITIES MSR available, use it to check CPU security */
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movl $MSR_ARCH_CAPABILITIES,%ecx
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rdmsr
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testl $ARCH_CAPABILITIES_RDCL_NO,%eax
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testl $ARCH_CAP_RDCL_NO,%eax
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jz .Lcpu_check_finished
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.Lcpu_secure:
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@ -1,4 +1,4 @@
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/* $OpenBSD: specialreg.h,v 1.81 2023/01/10 01:09:14 dv Exp $ */
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/* $OpenBSD: specialreg.h,v 1.82 2023/07/21 04:04:52 guenther Exp $ */
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/* $NetBSD: specialreg.h,v 1.7 1994/10/27 04:16:26 cgd Exp $ */
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/*-
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#define MTRRcap_WC 0x400 /* bit 10 - WC type supported */
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#define MTRRcap_SMRR 0x800 /* bit 11 - SMM range reg supported */
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#define MSR_ARCH_CAPABILITIES 0x10a
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#define ARCH_CAPABILITIES_RDCL_NO (1 << 0) /* Meltdown safe */
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#define ARCH_CAPABILITIES_IBRS_ALL (1 << 1) /* enhanced IBRS */
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#define ARCH_CAPABILITIES_RSBA (1 << 2) /* RSB Alternate */
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#define ARCH_CAPABILITIES_SKIP_L1DFL_VMENTRY (1 << 3)
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#define ARCH_CAPABILITIES_SSB_NO (1 << 4) /* Spec St Byp safe */
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#define ARCH_CAPABILITIES_MDS_NO (1 << 5) /* microarch data-sampling */
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#define ARCH_CAPABILITIES_IF_PSCHANGE_MC_NO (1 << 6) /* PS MCE safe */
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#define ARCH_CAPABILITIES_TSX_CTRL (1 << 7) /* has TSX_CTRL MSR */
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#define ARCH_CAPABILITIES_TAA_NO (1 << 8) /* TSX AA safe */
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#define ARCH_CAP_RDCL_NO (1 << 0) /* Meltdown safe */
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#define ARCH_CAP_IBRS_ALL (1 << 1) /* enhanced IBRS */
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#define ARCH_CAP_RSBA (1 << 2) /* RSB Alternate */
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#define ARCH_CAP_SKIP_L1DFL_VMENTRY (1 << 3)
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#define ARCH_CAP_SSB_NO (1 << 4) /* Spec St Byp safe */
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#define ARCH_CAP_MDS_NO (1 << 5) /* microarch data-sampling */
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#define ARCH_CAP_IF_PSCHANGE_MC_NO (1 << 6) /* PS MCE safe */
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#define ARCH_CAP_TSX_CTRL (1 << 7) /* has TSX_CTRL MSR */
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#define ARCH_CAP_TAA_NO (1 << 8) /* TSX AA safe */
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#define ARCH_CAP_MCU_CONTROL (1 << 9) /* has MCU_CTRL MSR */
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#define ARCH_CAP_MISC_PACKAGE_CTLS (1 << 10) /* has MISC_PKG_CTLS MSR */
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#define ARCH_CAP_ENERGY_FILTERING_CTL (1 << 11) /* r/w energy fltring bit */
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#define ARCH_CAP_DOITM (1 << 12) /* Data oprnd indpdnt tmng */
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#define ARCH_CAP_SBDR_SSDP_NO (1 << 13) /* SBDR/SSDP safe */
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#define ARCH_CAP_FBSDP_NO (1 << 14) /* FBSDP safe */
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#define ARCH_CAP_PSDP_NO (1 << 15) /* PSDP safe */
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#define ARCH_CAP_FB_CLEAR (1 << 17) /* MD_CLEAR covers FB */
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#define ARCH_CAP_FB_CLEAR_CTRL (1 << 18)
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#define ARCH_CAP_RRSBA (1 << 19) /* has RRSBA if not dis */
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#define ARCH_CAP_BHI_NO (1 << 20) /* BHI safe */
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#define ARCH_CAP_XAPIC_DISABLE_STATUS (1 << 21) /* can disable xAPIC */
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#define ARCH_CAP_OVERCLOCKING_STATUS (1 << 23) /* has OVRCLCKNG_STAT MSR */
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#define ARCH_CAP_PBRSB_NO (1 << 24) /* PBSR safe */
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#define MSR_FLUSH_CMD 0x10b
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#define FLUSH_CMD_L1D_FLUSH (1ULL << 0)
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#define MSR_BBL_CR_ADDR 0x116 /* PII+ only */
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